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Control technique

Subclass of:

711 - Electrical computers and digital processing systems: memory

711100000 - STORAGE ACCESSING AND CONTROL

Patent class list (only not empty are listed)

Deeper subclasses:

Class / Patent application numberDescriptionNumber of patent applications / Date published
711161000 Archiving 1072
711163000 Access limiting 360
711165000 Internal relocation 232
711159000 Entry replacement strategy 113
711166000 Resetting 93
711156000 Status storage 90
711155000 Read-modify-write (RMW) 72
711157000 Interleaving 59
711158000 Prioritizing 45
Entries
DocumentTitleDate
20120203985Data Structure For Tiling And Packetizing A Sparse Matrix - A computer system retrieves a slice of sparse matrix data, which includes multiple rows that each includes multiple elements. The computer system identifies one or more non-zero values stored in one or more of the rows. Each identified non-zero value corresponds to a different row, and also corresponds to an element location within the corresponding row. In turn, the computer system stores each of the identified non-zero values and corresponding element locations within a packet at predefined fields corresponding to the different rows.08-09-2012
20120203983COMPRESSION ON THIN PROVISIONED VOLUMES USING EXTENT BASED MAPPING - A set of logical extents, each having compressed logical tracks of data, is mapped to a head physical extent and, if the head physical extent is determined to have been filled, to at least one overflow extent having spatial proximity to the head physical extent. Pursuant to at least one subsequent write operation and destage operation, the at least one subsequent write operation and destage operation determined to be associated with the head physical extent, the write operation is mapped to one of the head physical extent, the at least one overflow extent, and an additional extent having spatial proximity to the at least one overflow extent.08-09-2012
20120203980APPARATUS, SYSTEM, AND METHOD FOR VALIDATING THAT A CORRECT DATA SEGMENT IS READ FROM A DATA STORAGE DEVICE - An apparatus, system, and method are disclosed for validating that correct data is read from a storage device. A read request receiver module receives a read storage request to read a data segment of a file or object stored on a data storage device. The storage request includes one or more source parameters for the data segment. The source parameters include one or more virtual addresses that identify the data segment. A hash generation module generates one or more hash values from the virtual addresses. A read data module reads the requested data segment and returns one or more data packets and corresponding stored hash values stored with the data packets. The stored hash values were generated from a data segment written to the data storage device that contains data of the data packets. A hash check module verifies that the generated hash values match the respective stored hash values.08-09-2012
20090198923APPARATUS FOR PREDICTING MEMORY ACCESS AND METHOD THEREOF - A method for predicting memory access, where each data processing procedure is performed in a plurality of stages with segment processing, and the plurality of stages include at least a first stage and a second stage, includes: dividing a memory into a plurality of memory blocks, generating a predicting value of a second position information according to a correct value of a first position information at the first stage, accessing the memory blocks of the corresponding position in the memory according to the predicting value of the second position information, and identifying whether the predicting value of the second position information is correct or not for determining whether the memory is re-accessed, where the first stage occurs before the second stage in a same data processing procedure.08-06-2009
20080209139Rapid Input/Output Doorbell Coalescing To minimize CPU Utilization And Reduce System Interrupt Latency - Status/error reporting is implemented using a doorbell system. A plurality of flag registers are included on a system device, such as a serial buffer. Each flag register has a corresponding address, and stores a plurality of flags. A flag scan controller accesses the flag registers in a predetermined priority order, using the flag register addresses. Upon detecting that one or more of the flags of a flag register are activated, the flag scan controller causes a doorbell command to be generated. The doorbell command includes the flag register address and the corresponding flags. A system processor receives the doorbell command and services the activated flags. Once the activated flags are serviced, the system processor performs one or more software write operations to clear the flags within the system device. The system processor can simultaneously service multiple flags. The system processor can also simultaneously clear multiple flags.08-28-2008
20080301380Data Processor - To provide editing processing that can shorten a data stream editing processing time.12-04-2008
20120173828INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, AND COMPUTER READABLE MEDIUM STORING PROGRAM - An information processing apparatus includes an operation detector that detects an operation performed on information, a history memory controller that controls a history memory such that the history memory stores as history information an operator and information, serving as an operation target, in a mapped state if the operation detector has detected the operation, an extractor that extracts from the history memory an operator having performed the operation if the operation detector has detected the operation, and a notifier that notifies the operator extracted by the extractor that the operation has been performed on the information.07-05-2012
20100017570METHOD FOR STORING DATA AS WELL AS A TRANSPONDER, A READ/WRITE-DEVICE, A COMPUTER READABLE MEDIUM INCLUDING A PROGRAM ELEMENT AND SUCH A PROGRAM ELEMENT ADAPTED TO PERFORM THIS METHOD - A method for storing or reading data in a memory array of a transponder and a corresponding transponder, read/write device and program element is described. Therein, a data file system for storing data within the memory array is defined by a predetermined protocol. The data structure comprises: a capability container file containing management data and an application data file for storing application data. The capability container file includes an application data file control data block containing information to control the application data file. The application data file includes an application data length indicator indicating a memory size of first application data stored in the application data file in compliance with the predetermined protocol. The method for storing additional data comprises: checking whether a memory size of the application data file is larger than the memory size indicated by the application data length indicator; and storing second application data in a partial memory area of the application data file not occupied by the first application data. Thereby, memory areas which, according to the predetermined protocol, are not used can be used for new applications, data can be hidden in these areas such that they can not be read by protocol compliant reader devices and the data structure read or written by the method of the invention is compatible with the former predetermined protocol.01-21-2010
20090106504Memory system and method for operating a memory system - A memory system, in particular a buffered memory system, e.g., a fully buffered memory system, a method for operating a memory system, and a device for use with a memory system is disclosed. The memory system may include a first buffered memory module, and a second buffered memory module, wherein the first and the second buffered memory modules are adapted to be accessed in parallel. According to a further embodiment of the invention, a device is provided which is adapted to map consecutive accesses to the first or the second memory module to a parallel access of both the first and the second memory module.04-23-2009
20100058002SYSTEM AND METHOD FOR FILE SYSTEM LEVEL COMPRESSION USING COMPRESSION GROUP DESCRIPTORS - A system and method for transparently compressing file system data using compression group descriptors is provided. When data contained within a compression group be compressed beyond a predefined threshold value, a compression group descriptor is included in the compression group that signifies that the data for the group of level 0 blocks is compressed into a lesser number of physical data blocks. When performing a read operation, the file system first determines the appropriate compression group that contains the desired data and determines whether the compression group has been compressed. If so, the file system decompresses the data in the compression group before returning the decompressed data. If the magic value is not the first pointer position, then the data within the compression group was previously stored in an uncompressed format, and the data may be returned without performing a decompression operation.03-04-2010
20110191552MEMORY CONTROLLER, MEMORY SYSTEM, RECORDING AND REPRODUCING METHOD FOR MEMORY SYSTEM, AND RECORDING APPARATUS - A memory system has a memory unit that is made of memory cells, each of which assumes a record state with a threshold voltage according to data. If an inverter has performed reverse processing on a data sequence so as to make the number of the memory cells in a predetermined record state great based on a count of a counter in a record operation, the memory system sets a flag added to the data sequence to indicate that the reverse processing has been performed, and performs re-reverse processing on the data sequence to which the flag indicating that the inverter has performed the reverse processing is added in a reproducing operation.08-04-2011
20110191549Data Array Manipulation - Data array manipulation is described. In an embodiment, concurrent access to a multi-dimensional data array stored on a storage device is enabled by providing separate computational elements with access to a model of the data array for processing the data and consequently request changes to the model. The data array is updated in accordance with the changes, and notification of the changes is provided to the other computational elements concurrently accessing the model. In another embodiment, a data interface apparatus is provided that comprises a storage interface that generates a model of the data array, and an application interface that provides access to the model to the computational element for processing. The application interface receives changes to the model resulting from the processing, and a command to commit the changes to the data array. The storage interface then writes the changes to the data array as an atomic operation.08-04-2011
20090193202MULTI-COLUMN ADDRESSING MODE MEMORY SYSTEM INCLUDING AN INTEGRATED CIRCUIT MEMORY DEVICE - A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a memory bank. During a first mode of operation, a first row of storage cells in a first memory bank is accessible in response to a first column address. During a second mode of operation, a first plurality of storage cells in the first row of storage cells is accessible in response to a second column address during a column cycle time interval. A second plurality of storage cells in the first row of storage cells is accessible in response to a third column address during the column cycle time interval. The first and second pluralities of storage cells are concurrently accessible from the interface.07-30-2009
20090193201System to Increase the Overall Bandwidth of a Memory Channel By Allowing the Memory Channel to Operate at a Frequency Independent from a Memory Device Frequency - A memory system is provided that increases the overall bandwidth of a memory channel by operating the memory channel at a independent frequency. The memory system comprises a memory hub device integrated in a memory module. The memory hub device comprises a command queue that receives a memory access command from an external memory controller via a memory channel at a first operating frequency. The memory system also comprises a memory hub controller integrated in the memory hub device. The memory hub controller reads the memory access command from the command queue at a second operating frequency. By receiving the memory access command at the first operating frequency and reading the memory access command at the second operating frequency an asynchronous boundary is implemented. Using the asynchronous boundary, the memory channel operates at a maximum designed operating bandwidth, which is independent of the second operating frequency.07-30-2009
20090193200System to Support a Full Asynchronous Interface within a Memory Hub Device - A memory system is provided that implements an asynchronous boundary in a memory module. The memory system comprises a memory hub device integrated in a memory module. The memory system also comprises a set of memory devices coupled to the memory hub device. The memory hub device comprises a command queue that receives a memory access command from an external memory controller via a memory channel at a first operating frequency. The memory system further comprises a memory hub controller integrated in the memory hub device. The memory hub controller reads the memory access command from the command queue at a second operating frequency. By receiving the memory access command at the first operating frequency and reading the memory access command at the second operating frequency an asynchronous boundary is implemented within the memory hub device of the memory module.07-30-2009
20130031318APPARATUS, METHOD AND ARTICLE FOR PROVIDING VEHICLE DIAGNOSTIC DATA - A network of collection, charging and distribution machines collects, charges and distributes portable electrical energy storage devices (e.g., batteries, supercapacitors or ultracapacitors). Vehicle diagnostic data of a vehicle using the portable electrical energy storage device is stored on a diagnostic data storage system of the portable electrical energy storage device during use of a respective portable electrical energy storage device by a respective vehicle. Once the user places the portable electrical energy storage device in the collection, charging and distribution machine, or comes within wireless communications range of a collection, charging and distribution machine, a connection is established between the collection, charging and distribution machine and the portable electrical energy storage device. The collection, charging and distribution machine then reads vehicle diagnostic data stored on the diagnostic data storage system of the portable electrical energy storage device and provides information regarding the diagnostic data.01-31-2013
20130031317METHOD AND APPARATUS FOR REDIRECTING DATA WRITES - Apparatuses and methods for redirecting data writes are disclosed. In one embodiment a controller may be configured to receive a command including write data and address data identifying a target zone of a data storage medium; determine whether the target zone contains sufficient available data sectors to store the write data; and record the write data to a common area of a different zone when the target zone does not contain sufficient available data sectors, the common area available to store data when a target zone lacks sufficient available data sectors. In another embodiment, a method may comprise receiving a write command identifying a target zone of a data storage medium; determining whether the target zone contains sufficient available data sectors to store the write data; and recording the write data to a common area of a different zone when the target zone does not contain sufficient available data sectors.01-31-2013
20110202733SYSTEM AND/OR METHOD FOR REDUCING DISK SPACE USAGE AND IMPROVING INPUT/OUTPUT PERFORMANCE OF COMPUTER SYSTEMS - The present invention provides a system and/or method for reducing disk space usage and/or improving I/O performance of a computer system through the use of data compression and mapping of data page blocks to reduced size data file blocks. The system and/or method can be used to intercept activity at an interface of a computer system I/O subsystem and then map logical data page blocks to reduced sized physical file data blocks on a one-to-one basis, utilizing a suitable data compression algorithm. The system and/or method also allows data compression to be reversed when reading data from a physical disk storage medium associated with that computer system. The system may be implemented as either a device driver or a module linked to an I/O module of a computer system.08-18-2011
20110202732EXTENT MIGRATION SCHEDULING FOR MULTI-TIER STORAGE ARCHITECTURES - A method for scheduling the migration of extents between extent pools of a storage system is disclosed herein. In certain embodiments, such a method includes periodically profiling an extent pool to generate a historical data access profile of the extent pool. Using this historical data access profile, the method determines an optimal migration window for migrating an extent to the extent pool. The method then identifies an actual extent for migration to the extent pool. Once the actual extent is identified, the method schedules the extent for migration to the extent pool during the optimal migration window. A corresponding apparatus and computer program product are also disclosed herein.08-18-2011
20120246422SEMICONDUCTOR MEMORY DEVICE WHICH INCLUDES MEMORY CELL HAVING CHARGE ACCUMULATION LAYER AND CONTROL GATE - A semiconductor memory device includes a memory cell array, a power source circuit, a sense amplifier, a control circuit, and a processor. The memory cell array includes a nonvolatile memory cell. The power source circuit includes a first register and generates a voltage. The sense amplifier includes a second register, reads from the memory cell and amplifies the read data. The control circuit includes a third register and controls operations of the power source circuit and the sense amplifier. The processor controls the operations of the power source circuit, the sense amplifier and the control circuit by giving an instruction to the first to third registers. The control circuit decodes the instruction received at the third register so as to control the power source circuit and the sense amplifier directly based on a result of decoding.09-27-2012
20120246421System, Methods, and Apparatus for Subdividing Data for Storage in a Dispersed Data Storage Grid - An efficient method for breaking source data into smaller data subsets and storing those subsets along with coded information about some of the other data subsets on different storage nodes such that the original data can be recreated from a portion of those data subsets in an efficient manner.09-27-2012
20120246415DATA MERGING METHOD FOR NON-VOLATILE MEMORY AND CONTROLLER AND STORAGE APPARATUS USING THE SAME - A data merging method for merging data belonging to a first logical block in a rewritable non-volatile memory module is provided. The method includes getting a second physical block from a free area of the rewritable non-volatile memory module and determining whether a valid logical page number is smaller than a predetermined number. The method also includes, when the valid logical page number is smaller than the predetermined number, storing a corresponding page mapping table in a start physical page of the second physical block and writing at least one valid page data belonging to the first logical block into at least one physical page of the second physical block. Accordingly, the method can effectively shorten the time for merging data.09-27-2012
20100077158COMPUTER SYSTEM AND CONTROL METHOD THEREFOR - A physical storage area that is allocated to an unused area of a virtual volume is removed. A management unit sends a request to a server computer to make every piece of data stored in a first logical volume migrate to a second logical volume. The server reads all the data out of the first logical volume and writes the data in the second logical volume. A storage system that includes the first logical volume and the second logical volume allocates a physical storage area to an area of the second logical volume where the data is to be written, and writes the data in the allocated physical storage area. The storage system then deletes the first logical volume.03-25-2010
20130086336SCALABLE STORAGE DEVICES - Techniques using scalable storage devices represent a plurality of host-accessible storage devices as a single logical interface, conceptually aggregating storage implemented by the devices. A primary agent of the devices accepts storage requests from the host using a host-interface protocol, processing the requests internally and/or forwarding the requests as sub-requests to secondary agents of the storage devices using a peer-to-peer protocol. The secondary agents accept and process the sub-requests, and report sub-status information for each of the sub-requests to the primary agent and/or the host. The primary agent optionally accumulates the sub-statuses into an overall status for providing to the host. Peer-to-peer communication between the agents is optionally used to communicate redundancy information during host accesses and/or failure recoveries. Various failure recovery techniques reallocate storage, reassign agents, recover data via redundancy information, or any combination thereof.04-04-2013
20130086335MEMORY SYSTEM AND MEMORY INTERFACE DEVICE - A memory access source regards a plurality of memory circuits as single memory circuit and transmits a row address and a column address in time division to an access control circuit. The access control circuit performs a speculative access to the plurality of memory circuits when receiving the row address, and performs an access to a memory circuit which is specified by the column address after receiving the column address and sends a cancel command of the speculative access to the other memory circuit out of target. Or, in the case of read access, the access control circuit receives read data from the plurality of memory circuits and discards the read data of the memory circuit out of the target by the column address.04-04-2013
20130080719Shopping Cart - A shopping cart is disclosed. The shopping cart comprises a frame, a receptacle for holding items and a scanning apparatus for scanning items to be placed within the receptacle. The shopping cart further comprising weighing means for monitoring the weight of the receptacle.03-28-2013
20130080713STORAGE CARTRIDGE AND CARTRIDGE DRIVE - A docking station for receiving a cartridge includes a housing having a receiving space configured to receive the cartridge. A movable carriage is disposed in the receiving space and configured to transport the cartridge into the receiving space. A movable mouth piece is configured to at least partially surround a multipoint connector of a non-tape storage medium of the cartridge through a horizontal access side opening of the cartridge so as to fix the multipoint connector. A fixing slider is configured to move the mouth piece through the horizontal access side opening so as to fix the multipoint connector within the receiving space. A connector slider is configured to move a connector within the docking station through a vertical access bottom opening of the cartridge against the electrical multipoint connector.03-28-2013
20130080715COMPUTING DEVICE SYSTEM AND INFORMATION MANAGING METHOD - The present invention provides a technique of suitably configuring a decision criterion for determining a transfer destination layer in rearrangement processing according to a task type and operation status and preventing performance degradation caused by arranging task data requiring a high response to a lower layer. At least one computing device (or management computing device or each host computing device) of a plurality of computing devices configures rearrangement reference information showing whether an access characteristic related to a task executed on a plurality of host computing devices is considered as a decision criterion for transfer destination determination in rearrangement processing of transferring data between actual storage areas of physical storage devices of different response performance. Also, a storage subsystem refers to the rearrangement reference information and, based on an access characteristic of the plurality of computing devices with respect to the actual storage areas assigned to the plurality of computing devices, executes rearrangement processing of transferring data stored in the actual storage areas to different actual storage areas in the physical storage devices of different response performance (see FIG. 03-28-2013
20130080718SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor memory device includes a memory string including memory cells formed by word lines covering a vertical semiconductor layer on a semiconductor substrate at different heights, the memory string coupled between a bit line and a source line, a control circuit configured to control an erase operation of the memory cells, a first erase verify operation of the memory cells coupled to even word lines, and a second erase verify operation of the memory cells coupled to odd word lines, and an operation circuit, performing the erase operation of the memory cells, applying a first voltage to the odd and even word lines to form a channel in the vertical semiconductor layer between the odd and even word lines when the first and second erase verify operations are performed, respectively.03-28-2013
20130080716CONTROLLER, MEMORY SYSTEM, AND INSPECTION METHOD - According to embodiments, a controller includes a read inspection unit, an inspection block setting unit, and a timing determining unit. The read inspection unit performs a read inspection for determining whether to perform rewriting of valid data to a block in which the valid data is stored among a plurality of blocks included in a nonvolatile memory. The inspection block setting unit generates an inspection block by writing inspection pattern data having a threshold as high as possible in at least one of the blocks included in the nonvolatile memory. The timing determining unit determines a timing of performing the read inspection by the read inspection unit based on the number of inverted bits that occurs in inspection pattern data written in the inspection block.03-28-2013
20130080714I/O MEMORY TRANSLATION UNIT WITH SUPPORT FOR LEGACY DEVICES - An apparatus, method, and medium are disclosed for managing memory access from I/O devices. The apparatus comprises a memory management unit configured to receive, from an I/O device, a request to perform a memory access operation to a system memory location. The memory management unit is configured to detect that the request omits a memory access parameter, determine a value for the omitted parameter, and cause the memory access to be performed using the determined value.03-28-2013
20130086334SERIALLY CONNECTED MEMORY HAVING SUBDIVIDED DATA INTERFACE - A memory system has a controller. A plurality of memory devices are serially interconnected with the controller via an n-bit data interface. The memory system is configurable in a first mode to communicate each read and write operation between the controller and the memory devices using all n bits of the data interface. The memory system is configurable in a second mode to concurrently: communicate data associated with a first operation between the controller and a first target memory device using only m bits of the data interface, where m is less than n; and communicate data associated with a second operation between the controller and a second target memory device using the remaining n-m bits of the data interface. A memory device, a memory controller, and a method are also described.04-04-2013
20130036275CIRCUIT AND METHOD FOR RAPIDLY TRANSMITTING DATA - A circuit for the rapid transmission of data is presented. The circuit includes a control unit, a data storage unit, and a data processing unit. The data processing unit includes an interrupt module, a processor chipset, an access controller, a first register and a second register. The interrupt module is connected to the control unit and receives an interrupt signal from the control unit. The access controller reads data from the data storage unit according to a beginning address and an ending address included in the interrupt signal and stores the retrieved data alternately in the first register and in the second register. The processor chipset retrieves and displays data from the second register when data is in the first register and retrieves and displays data from the first register when data is in the second register.02-07-2013
20130080717INFORMATION PROCESSING APPARATUS AND CONTROL METHOD - According to one embodiment, an apparatus includes a volatile memory, a nonvolatile semiconductor disk drive, a hibernation control module, a resume control module, and a release module. The drive includes SLC and MLC areas. The hibernation control module saves system context data in a first storage area in the SLC area in response to a hibernate request. The system context data includes contents of the volatile memory. The resume control module reads the system context data from the first storage area to restore the contents of the volatile memory, in response to a resume request. The release module releases the first storage area so as to allow the first storage area to be used to store other data, in response to completion of the read of the system context data.03-28-2013
20090172313ELECTRONIC DEVICE WITH SERIAL ATA INTERFACE AND POWER SAVING METHOD FOR SERIAL ATA BUSES - In an electronic device with a serial ATA interface, upon detection of the issue or reception of a preset command, a confirmation device, such as a CPU, confirms the completion of execution of the command. Upon confirming the completion of execution of the command, a controller, which may also be the CPU, controls shifting of the serial ATA interface to a power saving mode.07-02-2009
20090172310APPARATUS AND METHOD FOR CONTROLLING MEMORY OVERRUN - A memory address filter is configurable to emulate memory overrun performance of a legacy memory using an electronic memory of equal or greater capacity. The address filter includes a comparator configured to determine whether a target address is greater than a maximum legacy-address. Memory emulation at target address values greater than the maximum legacy-address value includes one or more of inhibiting the memory transaction; accomplishing the requested memory transaction at the maximum legacy-address value; and accomplishing the requested memory transaction at an address equivalent to the target address wrapped according to the maximum legacy-address value. In some embodiments, the address filter accepts one or more configuration parameters, such as memory depth, wrap-around, and overwrite enable.07-02-2009
20090172309Apparatus and method for controlling queue - An apparatus includes a queue element which stores a plurality of memory access requests to be issued to a memory device, the memory access requests including a store request and a load request, and a controller which changes an order of the store and load requests so that the order includes a string of the store requests and a string of the load requests.07-02-2009
20090172306System and Method for Supporting Phased Transactional Memory Modes - A phased transactional memory (PhTM) may support a plurality of transactional memory implementations, including software, hardware, and hybrid implementations, and may provide mechanisms for dynamically transitioning between transactional memory modes in response to changing workload characteristics; upon discovering that the current mode does not perform well, is not suitable, or does not support functionality required for particular transactions; or according to scheduled phases. A system providing PhTM may be configured to transition from a first transactional memory mode to a second transactional memory mode while ensuring that transactions executing in the first transactional memory mode do not interfere with correct execution of transactions in the second transactional memory mode. The system may be configured to abort transactions in progress or to wait for transactions to complete, be aborted, or reach a safe transition point before transitioning to a new mode, and may use a global mode indicator in coordinating transitions.07-02-2009
20090172305EFFICIENT NON-TRANSACTIONAL WRITE BARRIERS FOR STRONG ATOMICITY - A method and apparatus for providing optimized strong atomicity operations for non-transactional writes is herein described. Locks are acquired upon initial non-transactional writes to memory locations. The locks are maintained until an event is detected resulting in the release of the locks. As a result, in the intermediary period between acquiring and releasing the locks, any subsequent writes to memory locations that are locked are accelerated through non-execution of lock acquire operations.07-02-2009
20090172303HYBRID TRANSACTIONS FOR LOW-OVERHEAD SPECULATIVE PARALLELIZATION - A method and apparatus for a hybrid transactional memory system is herein described. A first transaction is executed utilizing a first style of a transactional memory system and a second transaction is executed in parallel utilizing a second style of a transactional memory system. For example, a main thread is executed utilizing an update-in place Software Transactional Memory (STM) system while a parallel thread, such as a helper thread, is executed utilizing a write buffering STM. As a result, a main thread may directly update memory locations, while a helper thread's transactional writes are buffered to ensure they do not invalidate transactional reads of the main thread. Therefore, parallel execution of threads is achieved, while ensuring at least one thread, such as a main thread, does not degrade below an amount of execution cycles it would take to execute the main thread serially.07-02-2009
20130042082INFORMATION PROCESSING APPARATUS AND STORAGE CONTROL METHOD - An information processing apparatus includes a first storage unit and a processor. The first storage unit includes a first storage area. The processor receives a first request to write first data into the first storage area. The processor requests an external apparatus to write the first data into a second storage area in a second storage unit included in the external apparatus. The processor determines whether a first response has been received from the external apparatus. The first response indicates that the first data has been written into the second storage area. The processor writes the first data into the first storage area when the first response has been received. The processor requests, without writing the first data into the first storage area, the external apparatus to write second data stored in the first storage area into the second storage area when the first response has not been received.02-14-2013
20130042081MAGNETIC TUNNELING JUNCTION DEVICES, MEMORIES, MEMORY SYSTEMS, AND ELECTRONIC DEVICES - Provided is a magnetic tunneling junction device including a first structure including a magnetic layer; a second structure including at least two extrinsic perpendicular magnetization structures, each including a magnetic layer and; a perpendicular magnetization inducing layer on the magnetic layer; and a tunnel barrier between the first and second structures.02-14-2013
20100042789CHECK-HAZARD INSTRUCTIONS FOR PROCESSING VECTORS - The described embodiments provide a system that determines data dependencies between two vector memory operations or two memory operations that use vectors of memory addresses. During operation, the system receives a first input vector and a second input vector. The first input vector includes a number of elements containing memory addresses for a first memory operation, while the second input vector includes a number of elements containing memory addresses for a second memory operation, wherein the first memory operation occurs before the second memory operation in program order. The system then determines elements in the first and second input vectors where the memory addresses indicate that a dependency exists between the memory operations. The system next generates a result vector, wherein the result vector indicates the elements where dependencies exist between the memory operations.02-18-2010
20100325372PARALLEL TRAINING OF DYNAMIC RANDOM ACCESS MEMORY CHANNEL CONTROLLERS - In order to reduce training time and therefore boot time in computer systems, multiple memory channels are trained simultaneously. A training synchronizer receives training data and parameters for multiple memory channel controllers and includes a plurality of communication interfaces that simultaneously communicate over the communication interfaces with the memory channel controllers. The memory channel controllers are responsive to the training synchronizer to simultaneously train a plurality of memory channels coupled to respective ones of the memory channel controllers.12-23-2010
20090157988DATA PROCESSING APPARATUS AND DATA PROCESSING METHOD - Disclosed is a data processing apparatus that includes a plurality of ports inputting and outputting a clip including a plurality of types of essence, a memory storing the clip when recording or playing back of the clip from a recording medium, and a generator storing types of essence in separate regions of the memory, and generate identification information identifying the types of essence, while generating linking information indicating an association between regions of the memory storing one of the types of essence as a master essence and regions of the memory storing the remaining types of essence. The apparatus further includes a control unit outputting the master essence in the regions and the remaining essence in the regions associated therewith via linking information from the designated ports when the master essence in the clip of the video data subjected to playback request designating the ports is stored in the memory.06-18-2009
20090157986MEMORY CONTROLLER - A memory controller includes an digitally programmable delay unit having a selectable delay time receiving a read-enable signal and outputting a delayed read-enable signal. The delay time is selected in response to an externally applied delay-control signal. A sampling unit in the memory controller outputs data received from a separate memory, in synchronization with the delayed enable signal. The delay time may be a multiple of the period of a clock signal.06-18-2009
20090157985Accessing memory arrays - A memory controller for controlling access to a memory, said memory comprising at least one memory array, said at least one memory array comprising a plurality of rows and a plurality of columns, access to an element within said memory array being performed by opening a row comprising said element and then accessing a column comprising said element, said at least one memory array being adapted to have no more than one row in said at least one memory array open at a time; said memory controller being responsive to a memory access request to access an element within said memory and following said access to determine if said row comprising said accessed element should be closed or should remain open in dependence upon a property of said memory access request.06-18-2009
20100332772APPARATUS, COMPUTER-READABLE RECORDING MEDIUM AND STORAGE SYSTEM - A apparatus for controlling a first storage and a second storage, has a controller for receiving a write command and a read command sent out from a host and for sending out the write command and the read command to the first storage and the second storage, a determining unit for sending out a request corresponding to the write command to the first storage and the second storage, for receiving a first response corresponding to the request from the first storage and a second response corresponding to the request from the second storage, and for determining one of the storages on the basis of each of response times, a first writing unit for writing data into the determined storage, and a second writing unit for writing the data written in the determined storage into the other storage after writing the data into the determined storage by the first writing unit.12-30-2010
20100106921SYSTEM AND METHOD FOR CONCURRENTLY MANAGING MEMORY ACCESS REQUESTS - A shared memory management system and method are described. In one embodiment, a memory management system includes a memory management unit for concurrently managing memory access requests from a plurality of engines. The shared memory management system independently controls access to the context memory without interference from other engine activities. In one exemplary implementation, the memory management unit tracks an identifier for each of the plurality of engines making a memory access request. The memory management unit associates each of the plurality of engines with particular translation information respectively. This translation information is specified by a block bind operation. In one embodiment the translation information is stored in a portion of instance memory. A memory management unit can be non-blocking and can also permit a hit under miss.04-29-2010
20100106920DATA LOCATION OBFUSCATION - Programs running on an open architecture, such as a personal computer, are vulnerable to inspection and modification. This is a concern as the program may include or provide access to valuable information. As a defense, the actual location of data can be hidden throughout execution of the program by way of periodic location reordering and pointer scrambling, among other things. These techniques serve to complicate static data flow analysis and dynamic data tracking thereby at least deterring program tampering.04-29-2010
20100106919LOGICAL UNIT OPERATION - The present disclosure includes methods and devices for logical unit operation. One device embodiment includes a number of logical units, wherein each of the number of logical units has a unique address. The device includes control circuitry coupled to the number of logical units and configured optionally to control more than one of the number of logical units with one of a number of commands and one address.04-29-2010
20090132771Method and apparatus for accessing image data - The invention relates to data accessing method and apparatus, and more particularly to data accessing method and apparatus for accessing a first-in first-out (FIFO) buffer compatible with mini-low voltage differential signal (mini-LVDS) transmission interface. The image data accessing apparatus comprises a FIFO memory for storing the image data, and a controller for accessing the FIFO memory in circular manner; wherein the controller writes the image data in pixel-basis and reads the stored image data in channel-basis.05-21-2009
20090125686IMAGE FORMING APPARATUS AND METHOD OF CONTROLLING THE SAME - An image forming apparatus and method of controlling the same, the image forming apparatus including: an article of consumption including a memory; and a print controller to perform a memory access to read and/or to write data from/to the memory. Addresses for the memory of the article of consumption are changed using access counts updated each time a memory access is requested, so that the memory access can be performed according to the changed addresses.05-14-2009
20090125690SYSTEMS AND METHODS FOR PERFORMING STORAGE OPERATIONS IN A COMPUTER NETWORK - Methods and systems are described for performing storage operations on electronic data in a network. In response to the initiation of a storage operation and according to a first set of selection logic, a media management component is selected to manage the storage operation. In response to the initiation of a storage operation and according to a second set of selection logic, a network storage device to associate with the storage operation. The selected media management component and the selected network storage device perform the storage operation on the electronic data.05-14-2009
20090125689SYSTEM AND ARTICLE OF MANUFACTURE FOR PROVIDING AN ADDRESS FORMAT COMPATIBLE WITH DIFFERENT ADDRESSING FORMATS USED FOR ADDRESSING DIFFERENT SIZED ADDRESS SPACES - Provided are a system and article of manufacture for providing an address format compatible with different addressing formats used for addressing different sized address spaces. An address format is used in an operating system to address storage space in a storage device comprising a first region and a second region of storage space. A first group of applications uses the address format to only address the storage space in the first region and is not coded to use the address format to access the second region and a second group of applications uses the address format to address the storage space in the first and second regions.05-14-2009
20090125688MEMORY HUB WITH INTERNAL CACHE AND/OR MEMORY ACCESS PREDICTION - A computer system includes a memory hub for coupling a processor to a plurality of synchronous dynamic random access memory (“SDRAM”) devices. The memory hub includes a processor interface coupled to the processor and a plurality of memory interfaces coupled to respective SDRAM devices. The processor interface is coupled to the memory interfaces by a switch. Each of the memory interfaces includes a memory controller, a cache memory, and a prediction unit. The cache memory stores data recently read from or written to the respective SDRAM device so that it can be subsequently read by processor with relatively little latency. The prediction unit prefetches data from an address from which a read access is likely based on a previously accessed address.05-14-2009
20090125687METHOD OF CONTROLLING INTERNAL VOLTAGE AND MULTI-CHIP PACKAGE MEMORY PREPARED USING THE SAME - The invention relates generally to a multi-chip package (MCP) memory device, and more particularly, but without limitation, to a MCP memory device having a reduced size. In one embodiment, the MCP memory device includes: a transfer memory chip; and a plurality of memory chips coupled to the transfer memory chip, each of the plurality of memory chips including an internal voltage generating circuit, the transfer memory chip configured to receive a plurality of command signals from outside the MCP memory device, the transfer memory chip further configured to output a plurality of control signals to the plurality of memory chips based on the plurality of command signals. Embodiments of the invention also relate to a method of controlling an internal voltage of the MCP memory device.05-14-2009
20100095074MAPPED OFFSETS PRESET AHEAD OF PROCESS MIGRATION - Disclosed is a computer implemented method and computer program product to prioritize paging-in pages in a remote paging device. An arrival machine receives checkpoint data from a departure machine. The arrival machine restarts at least one process corresponding to the checkpoint data. The arrival machine determines whether a page associated with the process is pinned. The arrival machine associates the page to the remote paging device, responsive to a determination that the page is pinned. The arrival machine touches the page.04-15-2010
20130046940OPTIMIZATION OF MEMORY BY TAILORED GENERATION OF RUNTIME STRUCTURES - Data structures used to store data in an enterprise resource planning (ERP) system may be configured and custom-generated in a configuration mode of the ERP system where a subset of selectable data fields may be selected to avoid allocating space and resources to unused data fields. The data structures may then be generated in the configuration mode to eliminate the unused data fields at runtime. This in turn saves space and resources that would otherwise be allocated but not used. In ERP systems substantial space and computing resources may be saved by only allocating space and resources to only those resources that a specific customer intends to use.02-21-2013
20090119466SYSTEMS FOR PROVIDING PERFORMANCE MONITORING IN A MEMORY SYSTEM - Systems for providing performance monitoring in a memory system. The memory system includes a memory controller, a plurality of memory devices, a memory bus and a memory hub device. The memory controller receives and responds to memory access requests. The memory bus is in communication with the memory controller. The memory hub device is in communication with the memory bus. The memory hub device includes a memory interface for transferring one or more of address, control and data information between the memory hub device and the memory controller via the memory bus. The memory hub device also includes a memory device interface for communicating with the memory devices. The memory hub device further includes a performance monitor for monitoring and reporting one or more of memory bus utilization, memory device utilization, and performance characteristics over defined intervals during system operation.05-07-2009
20090119464MEMORY CHAIN - A memory system having a plurality of memory devices and a memory controller. The memory devices are coupled to one another in a chain. The memory controller is coupled to the chain and configured to output a memory access command that is received by each of the memory devices in the chain and that selects a set of two or more of the memory devices to be accessed.05-07-2009
20090157983METHOD AND APPARATUS FOR USING A VARIABLE PAGE LENGTH IN A MEMORY - A controller, a memory device including a memory array, and a method for accessing the memory device. The method includes, during a first access, activating a first page of the memory array corresponding to a first row address and accessing data from the first page with a first column address. The method further includes, during a second access, activating a first sub-page of the memory array corresponding to a second row address and accessing data from the first sub-page with a second column address. The activated first sub-page of the memory array is smaller than the first page of the memory array. The method further includes activating a second sub-page without receiving a separate activate command.06-18-2009
20090106506Method and Apparatus for Memory Access Optimization - Access to a memory is optimized by monitoring physical memory addresses and by detecting a memory access conflict based on the monitored physical memory addresses. The data stored at a physical address for which a conflict was detected is transferred to a new physical address.04-23-2009
20110010509SYSTEM AND METHOD OF SORTING AND CALCULATING STATISTICS ON LARGE DATA SETS WITH A KNOWN VALUE RANGE - A system for sorting data and calculating statistics on large data sets with a known value range includes a memory element and a processing element configured to execute steps of the methods. Methods for sorting data include establishing an array of counters such that each counter corresponds to a value in the data set, reading the numbers and incrementing the counter corresponding to the value of each number, and listing the values in sequential order wherein each value occurs in the list according to the count of the corresponding counter. Methods for calculating statistics utilize the count stored in each counter from the sorted data and the value that corresponds thereto.01-13-2011
20090037672Method and System for Tracking Data Correspondences - One embodiment is a method for tracking data correspondences in a computer system including a host hardware platform, virtualization software running on the host hardware platform, and a virtual machine running on the virtualization software, the method including: (a) monitoring one or more data movement operations of the computer system; and (b) storing information regarding the one or more data movement operations in a data correspondence structure, which information provides a correspondence between data before one of the one or more data movement operations and data after the one of the one or more data movement operations.02-05-2009
20090307445Shared Memory Partition Data Processing System With Hypervisor Managed Paging - Hypervisor managed memory paging is provided in a data processing system having multiple logical partitions. The data processing system includes a shared memory pool defined within physical memory. The shared memory pool includes a volume of physical memory with dynamically adjustable sub-volumes or sets of physical pages associated with the multiple logical partitions. Each sub-volume or set is associated with a particular logical partition and includes mapped logical memory pages for that logical partition. A hypervisor memory manager interfaces the multiple logical partitions and the shared memory pool, and manages access to logical memory pages within the shared memory pool. The hypervisor memory manager further manages page-out and page-in of logical memory pages from the shared memory pool to one or more external paging devices. This page-out and page-in managing by the hypervisor memory manager is transparent to the multiple logical partitions.12-10-2009
20090307444Systems and Methods For Virtualizing Storage For WPAR Clients Using Node Port ID Virtualization - Systems, methods and media for providing to a plurality of WPARs private access to physical storage connected to a server through a VIOS are disclosed. In one embodiment, a server is logically partitioned to form a working partition comprising a WPAR manager and individual WPARs. Each WPAR is assigned to a different virtual port. The virtual ports are created by using NPIV protocol between the WPAR and VIOS. Thereby, each WPAR has private access to the physical storage connected to the VIOS.12-10-2009
20090307443Flexible and Efficient Configuration of Multiple Common Interfaces - In a system for communicating data from a processor to a plurality of register groupings that includes a plurality of registers and a plurality of register decoding logic entities, each register is associated with one of the plurality of register groupings. The plurality of register decoding logic entities is arranged in a data communication ring and is assigned to a register grouping. Each register decoding logic entity is configured to: receive a data packet that includes a data unit intended for a set of the registers in communication with the register decoding logic entity; write the data unit to each of the set of registers; determine if the register decoding logic entity is set to a relay mode; and if the register decoding logic entity is set to the relay mode, then update the data packet to reflect an address corresponding to a next register decoding logic entity in the data communication ring and then transmit the data packet to the next register decoding logic entity for which the data packet is intended.12-10-2009
20090307442Memory Access Control - An embodiment of a method of controlling memory access includes an initial step of receiving a first request to control memory access. The embodiment of the method also includes the step of creating an instance of a data structure based on the first request. In addition to the previous two steps the embodiment of the method also includes the steps of receiving a second request to access a memory, and examining the instance of the data structure to determine whether the memory can be accessed.12-10-2009
20090113144ELECTRONIC DEVICE AND METHOD OF CONTROLLING THE SAME - According to one embodiment, an electronic device includes a main memory, a main controller which controls the main memory, a system BIOS which stores default access parameter data of the main memory, a substrates including a memory device installing region in which the main memory and a memory device storing other access parameter data of the main memory are to be installed, and a setting section which sets, when a memory device is installed in the memory device installing region, access parameter data read out from the memory device to the memory controller, and sets, when a memory device is not installed in the memory element region, access parameter data read out from the system BIOS to the memory controller.04-30-2009
20120191926INFORMATION PROCESSING APPARATUS THAT EXECUTES RESPONSE PROCESS TO RECEIVED INFORMATION, CONTROL METHOD THEREFOR, AND STORAGE MEDIUM STORING CONTROL PROGRAM THEREFOR - An information processing apparatus that is capable of preventing the overwriting of an incoming packet without disconnecting the network connection. The information processing apparatus receives incoming information via a network, stores it into a storage area, and executes a response process thereto. A response processing unit executes the response process to the incoming information. A first change unit switches so that the incoming information is stored into a second storage area after the incoming information, which is a factor to shift to a power mode from a power saving mode, is stored into a first storage area. A second change unit switches so that the incoming information is stored into the first storage area after the response processing unit executes the response process to the incoming information stored in the first storage area.07-26-2012
20120191925MEMORY ACCESS CONTROL CIRCUIT, PREFETCH CIRCUIT, MEMORY DEVICE AND INFORMATION PROCESSING SYSTEM - Disclosed herein is a memory access control circuit including: a determination section adapted to determine whether a target requested by a first wraparound memory access request from a processor is stored in a prefetch buffer; a request generation section adapted to generate a second wraparound memory access request including the target if it is determined that the target is not stored in the prefetch buffer; and an address conversion section adapted to convert the start address of the first wraparound memory access request according to predetermined rules for use as a start address of the second wraparound memory access request.07-26-2012
20120191924PREPARATION OF MEMORY DEVICE FOR ACCESS USING MEMORY ACCESS TYPE INDICATOR SIGNAL - Subject matter disclosed herein relates to memory devices or accessing memory devices, and more particularly, but by way of example and not limitation, to preparation of a memory device to perform a memory access operation based at least partly on at least one indicator signal that indicates a memory access type.07-26-2012
20120191923OUTPUTTING A PARTICULAR DATA QUANTIZATION FROM MEMORY - The present disclosure includes methods, devices, and systems for outputting data particular quantization of data from memory devices and systems. Outputting data particular quantization of data can include enabling a particular one of a plurality of different quantizations of data. The particular one of the plurality of quantizations of data can then be output.07-26-2012
20130073816METHOD OF STORING DATA IN A STORAGE MEDIUM AND DATA STORAGE DEVICE INCLUDING THE STORAGE MEDIUM - A method of storing data in a storage medium and a data storage device including the storage medium are provided. The method of storing data in accordance with exemplary embodiments of the inventive concept may include receiving data to be stored in the storage medium; determining whether the received data is user data or metadata used to manage the user data; and selectively compressing the received data according to a type of the determined data. Selectively compressed data is stored in the storage medium.03-21-2013
20130073815FLEXIBLE COMMAND PACKET-HEADER FOR FRAGMENTING DATA STORAGE ACROSS MULTIPLE MEMORY DEVICES AND LOCATIONS - A memory system has a plurality of memory devices and a memory controller coupled to one another in a chain. A packet transmitted through the chain includes a flexible command packet header identifying at least two non-sequential memory devices to be accessed, bypassing interim devices in the chain. The flexible command packet header also allows data to be fragmented in non-sequential memory locations within a memory device, and to be stored non-symmetrically (in different addressable locations among separate memory devices). The flexible command packet header does not have a fixed number of words, but is flexibly configurable to address various numbers of memory devices and various numbers of memory areas within the memory devices.03-21-2013
20130073817TERMINAL CAPABLE OF EXTENDING STORAGE SPACE AND METHOD EXTENDING STORAGE SPACE THEREOF - A terminal and a method extend a storage space. The terminal includes a contents receiver, an interface, an external memory measure unit, a store determining unit, and a transmission controller. The contents receiver receives contents via a network. The interface accesses at least one external memory. The external memory measure unit measures at least one of a speed of the interface, an available capacity and a use history of the external memory accessed via the interface. The store determining unit determines whether to store the contents in the external memory based on a value measured by the external memory measure unit. The transmission controller controls to transmit the contents to the external memory via the interface when it is determined that the contents are stored in the external memory.03-21-2013
20130061008CONCURRENT CODING OF DATA STREAMS - A method begins by a dispersed storage (DS) processing module concurrently receiving a first data stream and a second data stream for transmission to a receiving entity. The method continues with the DS processing module segmenting each of the first and second data streams to produce a first plurality of data segments and a second plurality of data segments, dividing one of the first plurality of data segments into a first plurality of data blocks, and dividing one of the second plurality of data segments into a second plurality of data blocks. The method continues with the DS processing module creating a data matrix from the first and second plurality of data blocks and generating a coded matrix from the data matrix and an encoding matrix. The method continues with the DS processing module outputting one or more pairs of coded values of the coded matrix to the receiving entity.03-07-2013
20130061009High Performance Free Buffer Allocation and Deallocation - The disclosure includes an apparatus comprising a memory configured to store a free list comprising a plurality of nodes, wherein at least one of the plurality of nodes is configured to store a plurality of node addresses, and wherein each of the plurality of node addresses corresponds to one node in the plurality of nodes. The disclosure further includes a method of memory management comprising using a free list comprising a plurality of nodes and storing a plurality of node addresses in at least one of the plurality of nodes, and wherein each of the plurality of node addresses corresponds to one node in the plurality of nodes.03-07-2013
20130061007GENERATING CODE THAT CALLS FUNCTIONS BASED ON TYPES OF MEMORY - In an embodiment, in response to reading a declaration of a function that specifies a name of the function and a type of memory on which the function operates, the name of the function, a pointer to the function, and the type are saved to a template. In response to reading a call statement that specifies the name of the function and an identifier of an object, first code is generated. The first code, when executed, reads the pointer to the function from a virtual function table pointed to by the object, finds an entry in the virtual function table that represents the function, and reads the pointer from the entry in the virtual function table. The call statement, when executed, requests a call of the function. Second code is generated that, when executed, calls the function using the pointer read from the virtual function table.03-07-2013
20130061006DATA MASK ENCODING IN DATA BIT INVERSION SCHEME - Devices, circuits, and methods for data mask and data bit inversion encoding and decoding for a memory circuit. According to these methods and circuits, the number of data lines/pins required to encode data mask information and data bit inversion information can be reduced. In an embodiment the data mask and data inversion functions for a portion of data, such as a data word, can be merged onto a common pin/data line. In other embodiments, a data mask instruction can be conveyed through a transmitted data word itself without using any extra pins. According to these embodiments, the pin overhead can be reduced from two pins per byte to one pin per byte.03-07-2013
20130061010ORDERING WRITE BURSTS TO MEMORY - A device may receive requests intended for a memory that includes a number of banks, determine a number of the requests intended for each of the banks, determine an order for the requests based on the determined number of the requests intended for each of the banks, and send one of the requests to the memory based on the determined order.03-07-2013
20130097393MEMORY CONTROL DEVICE, MEMORY CONTROL METHOD, DATA PROCESSING DEVICE, AND IMAGE PROCESSING SYSTEM - A memory control device that transfers data from an external memory to a data processing unit having plural processing mechanisms, includes an absolute address storage unit that stores an absolute address serving as a common reference value in a given data transfer period; a differential address storage unit that stores plural differential addresses therein; a differential address selection unit that selects any one of the plurality of differential addresses in a given order; a memory address generation unit that combines any differential address selected by the differential address selection unit with the absolute address to generate a memory address; and a data transfer unit that inputs the memory address generated by the memory address generation unit to the external memory, reads the data from the memory address, and transfers the data to the data processing unit.04-18-2013
20120226874CHARACTERIZATION AND OPTIMIZATION OF TRACKS ON DISKS - Embodiment of the invention related to characterization and optimization of tracks on a disk, magnetic or optical by determining an input/output (I/O) characteristics for a plurality of blocks on a disk by a processor, wherein the characteristics comprise at least one of a data size or data type or an association between the data files, and determining a plurality of parameters affecting operation performed on the disk for placement of the plurality of data clusters.09-06-2012
20090031093Memory System and Method for Two Step Memory Write Operations - A method of operating a memory component that includes a memory core includes receiving, from external control lines, a write command that specifies a write operation. The write command is stored for a first time period after receiving the write command. After the first time period, the write operation is initiated in response to the write command. During the write operation, unmasked portions of received data are written to the memory core, where the unmasked portions of the data are bits of the data that are identified by received mask information as not being masked.01-29-2009
20090031092Data reception system - A data reception system includes a data acquisition unit acquiring data from a predetermined transmission path, an access control unit storing the data acquired by the data acquisition unit in a predetermined storage area, and a plurality of storage areas. The plurality of storage areas includes a first storage area and a second storage area having a greater storable capacity and a lower storing speed compared to the first storage area. The access control unit further includes a transfer unit. The access control unit determines whether the total amount of data stored in the first storage area is in the excess of a predetermined threshold or not and causes a transfer unit to transfer the data acquired by the data acquisition unit to the second storage area to store the data in the second storage area when the total amount is in the excess of the threshold.01-29-2009
20130067177INFORMATION PROCESSING METHOD, INFORMATION PROCESSING SYSTEM, INFORMATION PROCESSING APPARATUS, AND PROGRAM - An information processing method includes: grouping temporarily consecutive data into a plurality of groups based on a reference defined in advance and storing the grouped data; reading, in response to an access request from an external apparatus, target data to be a target of the request from a first group including the target data and outputting the read target data to the external apparatus; and reading, in response to the reading of the target data, at least part of data from a second group different from the first group as read-ahead target data.03-14-2013
20130067176INFORMATION PROCESSING DEVICE AND PROGRAM PRODUCT - In an information processing device according to an embodiment, a generating unit generates a descriptor including information indicating an area in a storage unit and state information indicating a state of an entry in which the information indicating the area is stored, and an update unit updates the state information according to at least one of writing and reading of data to the area indicated in the entry selected according to the state information by the input/output unit. The generating unit generates the descriptor in advance before at least one of writing and reading of data to/from the storage unit is started.03-14-2013
20130067175METHOD AND SYSTEM FOR USING COMPRESSION IN PARTIAL CLONING - Method and system for partially cloning a data container with compression is provided. A storage operating system determines if a portion of a source data container that is to be cloned includes a plurality of compressed blocks that are compressed using a non-variable compression group size. The operating system clones the plurality compressed blocks with the non-variable compression group size and de-compresses a plurality of blocks of the data container that are not within the non-variable compression group size. The plurality of compressed blocks and the plurality of blocks that are not within the non-variable compression group size are then stored as a partially cloned copy of the source data container.03-14-2013
20130067174NONVOLATILE MEDIA JOURNALING OF VERIFIED DATA SETS - The storage of data sets in a storage set (e.g., data sets written to hard disk drives comprising a RAID array) may diminish the performance of the storage set through non-sequential writes, particularly if the storage devices promptly write data sets that are followed by sequentially following data sets. Additionally, storage sets may exhibit inconsistencies due to non-atomic writes of data sets and verifiers (e.g., checksums) and an intervening failure, such as an occurrence of the RAID write hole. Instead, data sets and verifiers may first be written to a stored on the nonvolatile media of a storage device before being committed to the storage set. Such writes may be sequentially written to the journal, irrespective of the locations of the data sets in the storage set; and recovery of a failure may simply involve re-committing the consistent records in the journal to correct incomplete writes to the storage set.03-14-2013
20110022808OUTPUT DRIVER, MEMORY HAVING OUTPUT DRIVER, MEMORY CONTROLLER, AND MEMORY SYSTEM - An output driver has a first driver connected between a first power source and an output terminal and a second driver connected between a second power source and the output terminal. One of the first driver and the second driver has two driving parts connected in parallel to each other. The two driving parts and the other of the first driver and the second driver are operated by independent input signals.01-27-2011
20110022807WRITE ONCE RECORDING DEVICE - An access device 01-27-2011
20120198185INFORMATION PROCESSING DEVICE AND INFORMATION PROCESSING METHOD - A newer generation game terminal according to one embodiment of the present invention is provided with a storage access control unit. The storage access control unit accesses a newer generation storage according to a request for access from an AP designed to execute a synchronization process on the assumption of a speed of access to an older generation storage. The storage access control unit estimates time required to access the older generation storage in accordance with an evaluation function for calculating the required time. The storage access control unit executes an adjustment process to fill time gap between record time required to access the newer generation storage and time estimated to be required for access.08-02-2012
20090248996APPARATUS AND METHODS FOR WIDGET-RELATED MEMORY MANAGEMENT - Apparatus and methods for changing operational modes of a widget and changing content feed to a widget based on operational mode changes and/or memory availability on the wireless device are provided. Apparatus and methods for managing the runtime memory usage of mobile widgets on a wireless device by changing widget states based on widget usage data are also provided.10-01-2009
20090031090APPARATUS AND METHOD FOR FAST ONE-TO-MANY MICROCODE PATCH - A microcode patch apparatus including a patch array, a mux, and a RAM. The patch array receives a microcode ROM address and determines that the microcode ROM address matches one of a plurality of entries within the patch array. The patch array outputs a corresponding branch instruction and asserts a hit signal. The branch instruction prescribes a microcode branch target address. The mux receives the branch instruction from the patch array and a micro instruction corresponding to the microcode ROM address from a microcode ROM. The mux provides the micro instruction or the corresponding branch instruction to an instruction register based upon the state of the hit signal. The RAM stores a plurality of patch instructions that are to be executed in place of the micro instruction. The first one of the plurality of patch instructions is stored at a location in the RAM corresponding to the microcode branch target address.01-29-2009
20090006784ADDRESS EXCLUSIVE CONTROL SYSTEM AND ADDRESS EXCLUSIVE CONTROL METHOD - An address lock register managing address exclusive control is made to retain not only an address but also a request type, an access destination, and a cache block. Upon receiving a new request, firstly, the address lock register is referred to judge whether an exclusive condition is satisfied, that is, whether an address match, CPU match, LINE match or SX-WAY match is present, and whether the address lock is busy in accordance with the output of an AND circuit. Further, the configuration is such that the address lock register is referred to confirm that the addresses are identical to each other, and, additionally, the response source is validated to be identical to a lock flag and the new request causing the lock is validated to be consistent with the response request upon receiving a response request so that the lock is not released unless a correct response is made.01-01-2009
20090006781 Structure for Memory Chip for High Capacity Memory Subsystem Supporting Multiple Speed Bus - A design structure is provided for a memory module containing an interface for receiving memory access commands from an external source, in which a first portion of the interface receives memory access data at a first bus frequency and a second portion of the interface receives memory access data at a second different bus frequency. Preferably, the memory module contains a second interface for re-transmitting memory access data, also operating at dual frequency. The memory module is preferably used in a high-capacity memory subsystem organized in a tree configuration in which data accesses are interleaved. Preferably, the memory module has multiple-mode operation, one of which supports dual-speed buses for receiving and re-transmitting different parts of data access commands, and another of which supports conventional daisy-chaining.01-01-2009
20090006780Storage system and path management method - A storage system and a path management method, which can facilitate node replacement are proposed. In the storage system, the host sets plural paths between the host and the volume and holds path information composed of management information on each of the paths; and the management apparatus includes an integrated path management unit that collects the path information on each of the paths defined between the host and the volume from the corresponding host to manage all the collected information as integrated path information; retrieves an alternate path going through a node other than a specified node and but that has the same function as the specified node, for the path going through the specified node, based on the integrated path information; and displays results of the retrieval.01-01-2009
20090006779Memory control system and memory data fetching method - The invention discloses a memory control system and a method to read data from memory. The memory control system comprises a control unit, a storage device, and a microprocessor. The memory control system and the method to read data from memory according to the invention utilize an unbalanced microprocessor clock signal with different duration length to control the microprocessor so as to increase the speed of reading memory.01-01-2009
20090006777APPARATUS FOR REDUCING CACHE LATENCY WHILE PRESERVING CACHE BANDWIDTH IN A CACHE SUBSYSTEM OF A PROCESSOR - A processor cache memory subsystem includes a cache controller coupled to a tag logic unit. The cache controller may monitor read request resources associated with the cache subsystem and receive read requests for data stored in a data storage array of the cache subsystem. The tag logic unit may determine whether one or more requested address bits match any address tag stored within a tag array of the cache subsystem. The cache controller may, in response to determining the read request resources associated with the cache subsystem are available, selectably send the request for data with an implicit request indication being asserted. In response to determining the read request resources associated with the cache subsystem are not available, the cache controller may send the request for data without an implicit request indication being asserted.01-01-2009
20090006776MEMORY LINK TRAINING - An apparatus and method are disclosed. In one embodiment, the apparatus trains a memory link using a signal alignment unit. The signal alignment unit aligns a read data strobe signal that is transmitted on the link with the center of a read data eye transmitted on the link. Next, the signal alignment unit aligns a receive enable signal that is transmitted on the link with the absolute time that data returns the data lines of the link a column address strobe signal is sent to the memory coupled to the link. Next, the signal alignment unit aligns a write data strobe signal transmitted on the link with the link's clock signal. Finally, the signal alignment unit aligns the center of the write data eye transmitted on the link with the write data strobe transmitted on the link.01-01-2009
20090006775Dual-Mode Memory Chip for High Capacity Memory Subsystem - A dual-mode memory chip supports a first operation mode in which received data access commands contain chip select data to identify the chip addressed by the command, and control logic in the memory chip determines whether the command is addressed to the chip, and a second operation mode in which the received data access command addresses a set of multiple chips. Preferably, the first mode supports a daisy-chained configuration of memory chips. Preferably the second mode supports a hierarchical interleaved memory subsystem, in which each addressable set of chips is configured as a tree, command and write data being propagated down the tree, the number of chips increasing at each succeeding level of the tree.01-01-2009
20090006774High Capacity Memory Subsystem Architecture Employing Multiple-Speed Bus - A high-capacity memory subsystem architecture utilizes multiple memory modules coupled to one or more access modules by a communications medium, in which at least some data is transferred between an access module and memory modules at a first bus frequency, and at least some data is transferred between the access module and memory modules at a second bus frequency different from the first. Preferably, data is interleaved to reduce the required bus speed for read/write data, and the higher bus frequency is used to transfer command/address data. Preferably, the memory system employs memory chips having dual-mode operation, one of which supports a dual-speed bus.01-01-2009
20090006773Signal Processing Apparatus - A signal processing apparatus able to raise a processing capability in processing accompanying access to a storing means is provided. Stream control units (SCU) 01-01-2009
20130166856SYSTEMS AND METHODS FOR PRESERVING THE ORDER OF DATA - A device includes an input processing unit and an output processing unit. The input processing unit dispatches first data to one of a group of processing engines, records an identity of the one processing engine in a location in a first memory, reserves one or more corresponding locations in a second memory, causes the first data to be processed by the one processing engine, and stores the processed first data in one of the locations in the second memory. The output processing unit receives second data, assigns an entry address corresponding to a location in an output memory to the second data, transfers the second data and the entry address to one of a group of second processing engines, causes the second data to be processed by the second processing engine, and stores the processed second data to the location in the output memory.06-27-2013
20130166853SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF - In a semiconductor memory device, when input data is latched to page buffers, first, the data is sequentially latched to even page buffers and subsequently latched to odd page buffers, and then the data is programmed to each memory cell. Thus, when data having a size of a half page or smaller is read, a read operation is performed only on even memory cells or odd memory cells, thus reducing a time required for the read operation.06-27-2013
20130166854STORAGE APPARATUS - An information processing apparatus that performs examination-mode processing to read test data from a first special area included in a first storage device of a plurality of storage devices and write the test data to a second special area included in a second storage device of the plurality of storage devices; and stores an execution result of the examination-mode processing in a result storage area. The execution result including information that identifies the first storage device, information that identifies the second storage device and a characteristic of the transfer of the test data.06-27-2013
20130166855SYSTEMS, METHODS, AND INTERFACES FOR VECTOR INPUT/OUTPUT OPERATIONS - Data of a vector storage request pertaining to one or more disjoint, non-adjacent, and/or non-contiguous logical identifier ranges are stored contiguously within a log on a non-volatile storage medium. A request consolidation module modifies one or more sub-requests of the vector storage request in response to other, cached storage requests. Data of an atomic vector storage request may comprise persistent indicators, such as persistent metadata flags, to identify data pertaining to incomplete atomic storage requests. A restart recovery module identifies and excludes data of incomplete atomic operations.06-27-2013
20130166851INCOMING BUS TRAFFIC STORAGE SYSTEM - In managing incoming bus traffic storage for store cell memory (SCM) in a sequential-write, random-read system, a priority encoder system can be used to find a next empty cell in the sequential-write step. Each cell in the SCM has a bit that indicates whether the cell is full or empty. The priority encoder encodes the next empty cell using these bits and the current write pointer. The priority encoder can also find next group of empty cells by being coupled to AND operators that are coupled to each group of cells. Further, a cell locator selector selects a next empty cell location among priority encoders for cell groups of various sizes according to an opcode by appending ‘0’s to cell locations outputs from priority encoders that are smaller than the size of the SCM.06-27-2013
20130166852METHOD FOR HIBERNATION MECHANISM AND COMPUTER SYSTEM THEREFOR - A method for hibernation mechanism and a computer system therefor are provided. The method includes the followings. An initial process of a hibernation mechanism is performed in a computer system, in which a non-swappable memory of a main memory is partitioned into a plurality of non-swappable segments, and each segment corresponds to a status value indicating whether the content of the segment has been changed. During a process of entering a hibernation state, for each non-swappable segment, it is determined whether the segment is to be written to a storage device according to the status value. The segment is written into the storage device when a determination result indicates the segment has been changed, or else the computer does not write the segment to the storage device when the determination result indicates the segment is has not been changed.06-27-2013
20130166850CONTENT ADDRESSABLE MEMORY DATA CLUSTERING BLOCK ARCHITECTURE - An apparatus having a first circuit and a second circuit. The first circuit may be configured to (i) parse a first data word into a first data portion and a second data portion and (ii) parse a first address into a first address portion and a second address portion. The second circuit generally has a plurality of memory blocks. The second circuit may be configured to store the second data portion in a particular one of the memory blocks using (i) the first data portion to determine the particular memory block and (ii) the first address portion to determine a particular one of a plurality of locations within the particular memory block. The data portion may not be stored in the memory blocks. The particular location may be determined independently of the second address portion.06-27-2013
20080294856MEMORY ARBITRATION SYSTEM AND METHOD HAVING AN ARBITRATION PACKET PROTOCOL - A memory hub and method for transmitting a read response on a data path of a memory hub interposed between a transmitting memory hub and a receiving memory hub. An arbitration packet including data indicative of a data path configuration for an associated read response is received at the memory hub. The arbitration packet is decoded, and the data path is configured in accordance with the data of the arbitration packet. The associated read response is received at the memory hub and the associated read response is coupled to the configured data path for transmitting the same to the receiving memory hub.11-27-2008
20080294855Memory control system and memory data fetching method - The invention discloses a memory control system and a method to read data from memory. The memory control system comprises a microprocessor, a serial storage device, a first buffer, a second buffer, a memory control unit, and a multiplexer. The memory control system and the method to read data from memory according to the invention utilize the charateristics that the microprocessor reades data from continuous addresses of a serial memory during most of the time. By reading in advance and temporarily storing the data that the microprocessor requests to read, increasing the reading memory speed can be achieved.11-27-2008
20080294853Method and System for Pinpointing Memory Leaks - A method and a system configured for dynamically pinpointing information relating to occurrences of memory leaks. A first set of machine instructions received as input at a system and executable by a processor of the system thereby generating a second set of machine instructions from the first set of machine instructions in a main memory of the system. While executing the second set of instruction, an additional memory is allocated from a heap memory when the second set of instructions creates a heap allocated memory. The additional memory is configured to store a reference count indicating number of memory location comprising addresses of the heap allocated memory. The reference count approach is used to indicate when a memory leak has occurred.11-27-2008
20090100233PERSISTENT MEMORY MODULE - A persistent memory module (04-16-2009
20100217943MICROCONTROLLER AND ELECTRONIC CONTROL UNIT - A microcontroller in which respective CPUs execute different applications so as to improve processing performance, and the respective CPUs execute an application that requires safety and mutually compare the results thereof so as to enhance the reliability of write data is provided. The microcontroller has a plurality of processing systems made up of a first CPU, a second CPU, a first memory and a second memory, and for the instruction processing about specific processing set in advance, the write to peripheral modules which are not multiplexed is executed twice, and the write data of the first time and the second time are mutually collated.08-26-2010
20100088479MEMORY ACCESS CONTROLLER - A memory access controller is disclosed. A packet memory stores a packet and has a clock parallel outputting function of parallel-outputting first data and a clock. A read controller reads the first data. A clock transfer unit performs a clock transfer operation by writing the first data using the clock and reading second data using a system clock. A packet assembly unit receives the second data and reassembles the packet. An information memory stores a read start address where head data of the packet is stored and packet length information indicating a length of the packet. A read controller receives the read start address and the packet length information, generates a read address necessary for reading one packet, and reads the first data from the packet memory.04-08-2010
20120210082DATA CODING USING DIVISIONS OF MEMORY CELL STATES - Data storage devices and methods to encode and decode data using divisions of memory cell states are disclosed. A method includes dividing data bits into disjoint multiple groups of data bits and storing the data bits into a plurality of memory cells. The storing is done by setting each of the plurality of memory cells to a corresponding state selected from at least three ordered states. For each of the multiple groups of data bits, when a request is received for reading a particular group of the data bits, the request is serviced by selecting a disjoint division of the at least three ordered states of the memory cells into a first set of states and a second set of states. Each of the states in the first set of states has a higher position than any of the states in the second set of states according to the order of the states. For each cell of the plurality of memory cells, a determination is made whether the cell is in the first set of states or the second set of states. Based on the determination, the particular group of the data bits is generated in response to the request for reading the particular group of the data bits without use of additional data that depends upon a state of one of the memory cells.08-16-2012
20120221804NON-VOLATILE MEMORY DEVICE WITH IMPROVED PROGRAMMING MANAGEMENT AND RELATED METHOD - A non-volatile memory device includes a plurality of memory cells, with each memory cell for storing a bit having a first logic value or a second logic value. An input is for receiving a word defined by bits to be stored in the plurality of memory cells. Programming circuitry is for programming a corresponding memory cell for each bit having the first logic value. Forming circuitry is for receiving the word from the input and for providing to the programming circuitry at least one additional word defined by bits to also be stored in the plurality of memory cells. The forming circuitry includes processing circuitry for calculating a current maximum number of simultaneously programmable bits, and logic circuitry for generating the additional word, with the additional word having a number of bits having the first logic value equal to the current maximum number.08-30-2012
20110264872SYSTEMS AND METHODS FOR TRANSFORMATION OF LOGICAL DATA OBJECTS FOR STORAGE - Systems and methods for transforming a logical data object for storage in a storage device operable with at least one storage protocol, creating, reading, writing, optimization and restoring thereof. Transforming the logical data object comprises creating in the storage device a transformed logical data object comprising and one or more allocated storage sections with a predefined size; processing one or more sequentially obtained chunks corresponding to the transforming logical data object, wherein at least one of said processed data chunks comprises transformed data resulting from said processing; sequentially storing the processed data chunks into said storage sections in accordance with an order the chunks received. The method further includes reading a data range from the transformed logical object in response to a read request specifying desired point in time to be read.10-27-2011
20110191551STORAGE APPARATUS AND STORAGE MANAGEMENT METHOD - A storage apparatus capable of copying data to a destination apparatus includes storages including a plurality of volumes for storing data, memories for temporarily storing data to be copied to the destination apparatus, and processors for controlling to copy the data, each processor being configured to manage the memories and parts of the volumes, respectively, and wherein one processor executes storing received write data to one memory and the part, detecting each data amounts stored in the memories when an data amount of one memory is greater than a predetermined amount, allocating management of a part of the part managed by the one processor to other processor when the amount of the data stored in the one memory is greater than an amount calculated by using the data stored in the memories, and transmitting the data stored in the memories to the destination apparatus.08-04-2011
20090271578Reducing Memory Fetch Latency Using Next Fetch Hint - In one aspect, a processor is provided. The processor may include logic, coupled to the processor, and to issue a currently issued memory fetch over a processor bus. The currently issued memory fetch may include a next fetch hint that may include information about a next memory fetch.10-29-2009
20110283068MEMORY ACCESS APPARATUS AND METHOD - A memory access apparatus is coupled to a memory unit and includes a header access circuit and a payload access circuit. The header access circuit includes a header fetching unit used to fetch a header descriptor in the memory unit, and the payload access circuit includes a payload fetching unit used to fetch a payload descriptor in the memory unit. The header access circuit and the payload access circuit perform fetching with respect to the memory unit in a non-sequenced manner.11-17-2011
20110296117STORAGE SUBSYSTEM AND ITS CONTROL METHOD - Provided is a storage subsystem capable of maintaining the reliability of I/O processing to a host apparatus, even if there is an unauthorized access from a processor core to a switch circuit, by applying a multi-core system to a processor. A multi-core processor is applied to a second logical address space that is different from a first logical address space to be commonly applied to multiple controlled units such as a host interface to be accessed by the processor. The switch circuit determines the processor core that issued an access based on an address belonging to a second address space, and maps an address containing in an access from the processor core to an address of a first address space.12-01-2011
20080320247Processor and interface - A data processing apparatus comprises a processor constructed to operate under control of a sequence of program instructions selected from a predetermined instruction set; master circuitry to request access to storage locations of the processor; an interface circuit to provide an interface for an external apparatus to signal a request for access to the storage locations and an interface for the master circuitry to signal a request for access to the storage locations; and control to provide access between the storage locations and the interface circuit in response to the request only at predetermined points in execution of the stored program, the control being operable to fix periods of time for providing such access relative to the sequence of program instructions such that execution timing of the stored instructions is independent of whether a request is supplied to the interface.12-25-2008
20120159092METHOD AND DEVICE FOR STORING ONLINE DATA - The present invention relates to a method for reserving an online data storage space comprising: 06-21-2012
20110289280STORAGE SYSTEM, CONTROL METHOD THEREFOR, AND PROGRAM - A disk array device that can detect the successful completion of data overwrite/update at high speed only by checking a UDT is provided. When a DIF is used as a verification code appended to data, check information that detects the successful completion of overwrite is defined in the UDT, in addition to address information that detects positional errors. Upon request of overwrite/update of data stored in a cache, a check bit of the data in the cache is changed to a value different from a check bit to be appended to new data by a host adapter. Then, data transfer is initiated. Upon completion of the data overwrite, the check bit is changed back to the original value, whereby it is possible to detect the successful completion of overwrite/update (FIG. 11-24-2011
20110289286MEMORY CONTROLLER AND A METHOD FOR WRITING INFORMATION TO A K-LEVEL MEMORY UNIT - A method, a computer readable medium and a memory controller. The method for writing information to a K-level memory unit, includes: receiving a sequence of information bits; generating an information value that represents the sequence of information bits; applying a first function to the information value, to provide a first function result; selecting a first cell of the K-level memory unit as a current cell; wherein K is a positive integer that is greater than 1; writing the first function result to the first cell; and repeating the stages of: (a) reading a current cell to provide a current read result; (b) applying a second function to the current read result and to a function result that was written to the current cell, to provide a second function result; (c) selecting another cell as a current cell; and (d) writing the second function result to the current cell.11-24-2011
20110289281Policy Based Data Retrieval Performance for Deduplicated Data - A method that includes, by one or more computer systems, determining a data retrieval rate policy based on at least one data retrieval rate parameter. The method also includes determining at least one storage subsystem performance parameter. The method further includes determining a fragmentation value based on the data retrieval rate policy and the at least one storage subsystem performance parameter. The method additionally includes determining a storage subsystem fragmentation of a first data object. The storage subsystem fragmentation includes fragmenting the first data object into a plurality of first data object fragments. The method also includes deduplicating the first data object based on the fragmentation value and the storage subsystem fragmentation.11-24-2011
20110289284MULTI-PROCESSOR DEVICE AND INTER-PROCESS COMMUNICATION METHOD THEREOF - Provided are a multi-process device and an inter-process communication (IPC) method thereof. The multi-processor device includes a first processor, a second processor, a first memory connected to the first processor, and a second memory connected to the second processor. When an inter-process communication (IPC) operation is performed between the first processor and the second processor, data is exchanged between the first memory and the second memory.11-24-2011
20110289285CONTROL APPARATUS HAVING NON-VOLATILE RAM, PROTECTION APPARATUS AND METHOD APPLIED THERETO - A control apparatus including a non-volatile RAM divided into a plurality of memory regions including ROM region and RAM region, CPU capable of executing a plurality of types of access to the non-volatile RAM and a protecting portion intervening between the CPU and the non-volatile RAM. The protecting portion includes a register for storing address information capable of specifying address ranges corresponding to the ROM region and RAM region among the memory regions of the non-volatile RAM, access enabling means for enabling the CPU to write data to the ROM region while an enable signal inputted to the protecting portion externally is active, when the CPU performs a write-access to the ROM region, and initializing for initializing the address information stored in the register to be predetermined access information as an initial value when the enable signal is deactivated after activating the enable signal.11-24-2011
20110289282Sessions for Direct Attached Storage Devices - A mechanism and a storage device are provided for registering a component of a computing device, with a user-removably attached storage device and managing sessions between the component and the storage device. The storage device may record time information regarding a beginning and an ending of an activity session with the component. The storage device may determine whether at least a logical block address range of a storage device medium, registered by the component, may have been modified by a different component, since a last session with the component. When the storage device indicates to the component that at least the logical block address range of the medium has not been modified since the last session, the component may trust contents of the medium. The computing device may provide time information to the storage device, such that the storage device may determine whether management operations are to be performed.11-24-2011
20110289283MEMORY DEVICE UTILIZATION IN A DISPERSED STORAGE NETWORK - A method begins by a processing module determining whether a memory device of a dispersed storage (DS) unit is unavailable to produce an unavailable memory device. The method continues with the processing module determining a methodology regarding DS encoded data stored in the unavailable memory device based on one or more dispersed storage network (DSN) conditions to produce a determined methodology when the memory device is unavailable. The method continues with the processing module initiating, in accordance with the determined methodology, a rebuilding function to rebuild the DS encoded data to produce rebuilt DS encoded data when the determined methodology includes a rebuilding component. The method continues with the processing module storing the rebuilt DS encoded data within available memory of the DS unit.11-24-2011
20090094421Manufacturing mode for secure firmware using lock byte - Upon initialization or startup of an electronic device, the device checks a predetermined section of non-volatile memory, referred to as the signature byte or lock byte, and allows either the manufacturing mode which allows for installation of the final or production version of firmware to be loaded into non-volatile memory, or the production mode which write-protects certain portions of non-volatile memory before giving operating control of the electronic device to another program, for example, an operating system. By only allowing execution of operating system or other executable code after write-protecting certain portions of non-volatile memory, system security, integrity, and robustness are substantially increased.04-09-2009
20110296118Dynamic Row-Width Memory - A mechanism is provided for dynamic row-width memory. The memory adapts row width to usage based on memory controller and memory management system software control. The mechanism uses an organization and control of memory array access logic. The memory controller may receive an explicit command using existing column address lines or using a command line into the memory controller. In a first option, the memory controller receives a row width and disables the unused columns and turns off the unused sense amps. In a second option, the memory controller receives a row width and adjusts row count, keeping the number of active cells constant. In a third option, the memory controller receives a row width and adjusts a number of banks.12-01-2011
20090287887Storage system and method of managing a storage system using a management apparatus - A storage system has NAS apparatuses each including virtual file servers to be provided to host apparatuses, a storage apparatus including logical units, and a management apparatus for managing the NAS apparatuses and the storage apparatus. The management apparatus requests the NAS apparatuses and the storage apparatus to transfer management information, acquires the management information. The management apparatus then creates system performance information concerning the virtual file servers based on the acquired management information to display the created system performance information on a user interface.11-19-2009
20100223435Method and Apparatus for Providing a Packet Buffer Random Access Memory - The present invention generally provides a packet buffer random access memory (PBRAM) device including a memory array, a plurality of input ports, and a plurality of serial registers associated with the input ports. The plurality of input ports permit multiple devices to concurrently access the memory in a non-blocking manner. The serial registers enable receiving data from the input ports and concurrently packet data to the memory array. The memory performs all management of network data queues so that all port requests can be satisfied within the real-time constraints of network packet switching.09-02-2010
20100146223Apparatus and method for data management - Provided is a data processing method that may transmit, from a host unit including at least one host to a tiling unit, an input parameter and first data, tile the first data using a predetermined block interleaving scheme to convert the first data to second data, and store the converted second data in a memory unit. The data processing method may transmit, from a host unit including at least one host to an inverse tiling unit, an input parameter and a request signal for first data, extract second data corresponding to the request signal from the memory unit to store at least one second data that is tiled using a predetermined block interleaving scheme, and may transmit, to the host unit, the first data that is converted by inverse tiling the second data. Here, the first data may be in a data structure of a sequential scanning scheme.06-10-2010
20100005249Finding the Source Statement of the Definition of a Storage Location - In an embodiment, an identifier of a storage location that is accessed by a program is received. While execution of the program is halted at a halted statement, a first source statement is determined that must have stored to the storage location. The program comprises the halted statement and the first source statement, and the halted statement is different than the first source statement. The first source statement is presented, in response to the determination. In an embodiment, while execution of the program is halted at the halted statement, a second source statement is determined that might have stored to the storage location, and the second source statement is presented.01-07-2010
20100082916Highly Reliable Disk Controller - Provided is a unit for protecting data with respect to data transfer between memories of a disk controller. The disk controller for controlling data transfer between a host computer and a disk drive includes: a channel unit having a channel memory; a cache unit having a cache memory, and a control unit for controlling the data transfer. The data transferred to/from the host computer is transferred in a packet between the channel memory and the cache memory, and The control unit for verifying consistency of information included in a header of the packet to be transferred to decide whether transfer can be permitted when the packet is transferred.04-01-2010
20100153661PROCESSING OF READ REQUESTS IN A MEMORY CONTROLLER USING PRE-FETCH MECHANISM - A memory controller provided according to an aspect of the present invention includes a predictor block which predicts future read requests after converting the memory address in a prior read request received from the processor to an address space consistent with the implementation of a memory unit. According to another aspect of the present invention, the predicted requests are granted access to a memory unit only when there are no requests pending from processors and the peripherals sending access requests to the memory unit.06-17-2010
20110219198MEMORY CONTROL SYSTEM AND METHOD - A memory control system includes a first queue unit, a second queue unit, a first transforming unit, a second transforming unit, an arbiter and a control unit. The first queue unit temporarily stores multiple first request instructions. The second queue unit temporarily stores multiple second request instructions. The first transforming unit selectively re-assigns memory addresses corresponding to these first request instructions. The second transforming unit selectively re-assigns memory addresses corresponding to these second request instructions. The arbiter performs immediate scheduling of the first request instructions and the second request instructions to the memory. The control unit compares bandwidths of the first request instructions with bandwidths of the second request instructions, and controls the first transforming unit and the second transforming unit to perform re-assigning operations or not according to compared results.09-08-2011
20110219197Memory Controllers, Systems, and Methods Supporting Multiple Request Modes - A memory system includes a memory controller with a plurality N of memory-controller blocks, each of which conveys independent transaction requests over external request ports. The request ports are coupled, via point-to-point connections, to from one to N memory devices, each of which includes N independently addressable memory blocks. All of the external request ports are connected to respective external request ports on the memory device or devices used in a given configuration. The number of request ports per memory device and the data width of each memory device changes with the number of memory devices such that the ratio of the request-access granularity to the data granularity remains constant irrespective of the number of memory devices.09-08-2011
20100030975APPARATUS AND METHOD FOR HANDLING PAGE PROTECTION FAULTS IN A COMPUTING SYSTEM - Method and apparatus for handling page protection faults in combination particularly with the dynamic conversion of binary code executable by a one computing platform into binary code executed instead by another computing platform. In one exemplary aspect, a page protection fault handling unit (02-04-2010
20090138666WRITE SET BOUNDARY MANAGEMENT IN SUPPORT OF ASYNCHRONOUS UPDATE OF SECONDARY STORAGE - A color control node includes an interface for communicating with multiple storage controllers, wherein the storage controllers maintain a primary storage system at a primary site and a secondary storage system at a secondary site; and wherein the storage controllers maintain a current color and associate all writes with the current color without polling the color control node. The color control node also includes operational capability for issuing a polling command to instruct the storage controllers to poll the color control node for the current color prior to associating each write with a new color; receiving an acknowledgment of receipt of the polling command; changing the current color to a new color responsive to receiving the acknowledgment; issuing a storage command to the storage controllers indicating the new color; and instructing each storage controller to cease polling the color control node for the current color.05-28-2009
20100268900METHOD FOR TRACKING OF NON-RESIDENT PAGES - Embodiments of the present invention provide methods and systems for efficiently tracking evicted or non-resident pages. For each non-resident page, a first hash value is generated from the page's metadata, such as the page's mapping and offset parameters. This first hash value is then used as an index to point one of a plurality of circular buffers. Each circular buffer comprises an entry for a clock pointer and entries that uniquely represent non-resident pages. The clock pointer points to the next page that is suitable for replacement and moves through the circular buffer as pages are evicted. In some embodiments, the entries that uniquely represent non-resident pages are a hash value that is generated from the page's inode data.10-21-2010
20110191553Data Storage Control Apparatus and Data Storage Control Method - According to one embodiment, a data storage control method, which is applied to a virtual memory that controls access to the data stored in each of the physical memory regions by the corresponding one of the virtual addresses on the basis of an address management table that manages the correspondence relationship between a plurality of virtual addresses corresponding to a plurality of virtual memory regions and a plurality of physical addresses corresponding to a plurality of physical memory regions of a first memory, includes writing the data stored in a specific number of nonconsecutive physical memory regions made to correspond to a specific number of virtual memory regions on the basis of the address management table to a specific number of consecutive physical memory regions.08-04-2011
20110191550APPARATUS AND METHOD FOR PROCESSING DATA - An apparatus and method for processing data capable of providing an application with data converted based on various data types is provided. The data processing apparatus converts data, which is input from an input system, into various types of data. Various applications receive and use the data that is converted in the data processing apparatus.08-04-2011
20100169586Memory storage device and a control method thereof - The present invention discloses a control method of a memory storage device which includes a high density memory. The high density memory is composed of a plurality of MSB pages and LSB pages. The major feature of the method is such that it determines the property of data by its data length, and then decides where the data is to be written according to its property.07-01-2010
20100115212MEMORY ACCESS APPARATUS - A memory access apparatus is provided with a processor, an I/F circuit, and a memory control circuit. The processor is provided with an access-request generating circuit which issues a memory access request. The I/F circuit is provided with an F/F circuit which holds the memory access request outputted from the processor in response to a clock signal. The memory control circuit is provided with an access processing circuit which executes an access process that complies with the memory access request held by the F/F circuit.05-06-2010
20100115210METHOD AND APPARATUS FOR EXPANDING A VIRTUAL STORAGE DEVICE - The present invention provides for the expansion of a virtual storage device. Expansion of the virtual storage device includes adding one or more additional storage device units to an existing virtual storage device. Blocks or strips included in an added storage device unit are assigned addresses, to allow the added storage capacity to be accessed immediately. In order to reestablish a pattern of data storage addresses from the original storage device units of the pre-expanded virtual storage device across all of the storage device units of the post-expanded virtual storage device, temporary storage is provided. In particular, as a strip of data is relocated to its proper post-expand location, the data occupying that location is placed in a temporary storage buffer. Data in the temporary storage buffer is then written to the proper post-expand location for that data, with displaced data being written to a second temporary storage buffer.05-06-2010
20100115209METHODS AND APPARATUS FOR DETECTING A SYNCMARK IN A HARD DISK DRIVE - Methods and apparatus are provided for detecting a syncMark in a read channel, such as a hard disk drive. A syncMark is detected in a sector in an iterative read channel by obtaining a sector signal from a storage media, the sector signal comprising a first syncMark, data and a second syncMark substantially at an end of the sector; determining whether the first syncMark is detected in the sector signal; searching for the second syncMark if the first syncMark is not detected in the sector signal; and detecting and decoding the sector signal based on a detection of the second syncMark. The second syncMark may be positioned, for example, following data in the sector signal. The second syncMark can be searched for in a window within the signal sector that is based on an estimated location of the first syncMark.05-06-2010
20100268898SCHEDULED RETRIEVAL, STORAGE AND ACCESS OF MEDIA DATA - A system and method automates a scheduled retrieval, storage, and access of media data. Media data is retrieved from an external source and downloaded to an end user media device storage for subsequent playback at the end user media device. Media data is accessible from the end user media device storage based upon criteria including a selection of the end user, rules regulating the media data, and whether a playback time of the media data is sufficient to retrieve additional media data. The system performs regularly scheduled dynamic controls to determine whether additional media data is required for continuous and uninterrupted access of the media data.10-21-2010
20100268897MEMORY DEVICE AND MEMORY DEVICE CONTROLLER - A memory device controller interposed between a memory device and a host device includes a data communication unit configured to transfer data to and from the memory device in synchronization with a clock signal. The data communication unit supports a single edge synchronization mode in which data is transferred in synchronization with either one of a rising edge and a falling edge of the clock signal, and a double edge synchronization mode in which data is transferred in synchronization with both the rising edge and the falling edge. The data communication unit transfers data in the double edge synchronization mode when data is transferred by the memory device operating as a bus master.10-21-2010
20090150622SYSTEM AND METHOD FOR HANDLING DATA REQUESTS - A system and method for handling speculative read requests for a memory controller in a computer system are provided. In one example, a method includes the steps of providing a speculative read threshold corresponding to a selected percentage of the total number of reads that can be speculatively issued, and intermixing demand reads and speculative reads in accordance with the speculative read threshold. In another example, a computer system includes a CPU, a memory controller, memory, a bus connecting the CPU, memory controller and memory, circuitry for providing a speculative read threshold corresponding to a selected percentage of the total number of reads that can be speculatively issued, and circuitry for intermixing demand reads and speculative reads in accordance with the speculative read threshold. In another example, a method includes the steps of providing a speculative dispatch time threshold corresponding to a selected percentage of a period of time required to search a cache of the computer system, and intermixing demand reads and speculative reads in accordance with the speculative dispatch time threshold.06-11-2009
20110264870Using region status array to determine write barrier actions - A fast method for determining which actions to take in a write barrier in a concurrent garbage collector is described. A region status array indexed by a region index computed from the written address is used for determining the status of the region containing the written object and for selecting, in part, the actions taken by the write barrier. By carefully manipulating the region status array, various operations and changes in write barrier actions can be performed very efficiently.10-27-2011
20120110283DATA PROCESSING APPARATUS AND IMAGE PROCESSING APPARATUS - A data processing apparatus may include a plurality of buffer units that stores data, a data write control unit that writes input data to any one of the plurality of buffer units by exclusively controlling the plurality of buffer units, and a data read control unit that reads data to be output from any one of the plurality of buffer units by exclusively controlling the plurality of buffer units. The data write control unit may output a data write completion signal indicating that the writing of the data is completed when the writing of the input data is completed. The data read control unit may output a data read completion signal indicating that the reading of the data is completed when the reading of the data to be output is completed.05-03-2012
20120110282SYSTEMS AND METHODS FOR MANAGING INFORMATION OBJECTS IN DYNAMIC DATA STORAGE DEVICES - According to one aspect, a system for managing information objects in dynamic data storage devices including a first data storage device having a plurality of information objects, a second data storage device operatively connectable to an output device for providing at least some of the information objects to at least one user, and at least one processor operatively coupled to the first data storage device and the second data storage device. The at least one processor is configured to automatically divide the plurality of information objects in the first data storage device to form at least one data subdivision based on division criteria, and repeatedly, in response to a dynamic operating condition determine a relevance value of at least one of the data subdivisions in the first data storage device and the second data storage device indicative of the relevance of those data subdivision to the user, and based on the relevance value, perform at least one of loading those data subdivision to the second data storage, or unloading those data subdivision from the second data storage.05-03-2012
20120110281VIRTUALIZATION AND OFFLOAD READS AND WRITES - Aspects of the subject matter described herein relate to virtualization and offload reads and writes. In aspects, an offload read allows a requestor to obtain a token that represents data while an offload write allows the requestor to request that the data (or a part thereof) represented by a token be logically written. Offload reads and writes may be used to perform various actions for virtual environments.05-03-2012
20120110279METHOD AND SYSTEM FOR NON-DISRUPTIVE MIGRATION - Method and system for migrating a virtual storage system from a source storage system having access to a source storage device to a destination storage system having access to a destination storage device is provided. A processor executable management application estimates a likelihood of success for a migration operation before the migration operation enters a cut-over duration during which client access to the source storage system and the destination storage system is restricted. The migration operation enters the cut-over duration if there is high likelihood of success for completing the migration during the cut-over duration or aborted, if there is a low likelihood of success for completing the migration during the cut-over duration.05-03-2012
20120110278REMAPPING OF INOPERABLE MEMORY BLOCKS - Inoperable phase change memory (PCM) blocks in a PCM device are remapped to one or more operable PCM blocks, e.g. by maintaining an inoperable block table that includes an entry for each inoperable PCM block and an address of a remapped PCM block. Alternatively, the PCM blocks may be remapped by storing the address of the remapped block in the block itself, and setting a remapping bit that indicate the block has been remapped. Where the remapping is performed by a processor, an inoperable block bit may be set in a translation look aside buffer that indicates whether a virtual memory page is associated with an inoperable or remapped PCM block. When a request to access a virtual memory page is received, the processor references the inoperable block bit associated with the virtual memory page to determine whether to check for remapped PCM blocks in the inoperable block table.05-03-2012
20120110277METHOD AND SYSTEM FOR STORAGE-SYSTEM MANAGEMENT - One example of the present invention is directed to a data-storage system comprising a plurality of data-storage devices, one or more communications connections through which the data-storage system receives management and data-access commands and sends responses to received commands, and one or more processors. The one or more processors execute controller functionality that controls command and response exchanges through the communications connections, accesses the data-storage devices, and provides a data-storage-system interface that includes a management-interface portion that provides access to management functionality, a data-interface portion that provides access to data-access functionality, and a management-interface tunnel that provides alternative access to management functionality through the data-interface portion of the data-storage-system interface.05-03-2012
20100058003MULTI-PLANE DATA ORDER - Systems, methods and computer program products for programming data into a multi-plane memory device employ a multi-plane data order. To allow multiple data pages to be programmed without a need to increase the size of page buffers, in some implementations, a data transfer scheme at which the data pages are programmed can be manipulated. Specifically, data across all channels can first be programmed into a first plane of the multi-plane flash memory device in parallel. While the data transfer program operation is in progress, data to be programmed into a succeeding plane (e.g., plane “1”) can be read into and cached in one or more page buffers. After the data transfer program for the first plane is complete, data cached in the page buffers can be immediately latched and programmed into the multi-plane flash memory device.03-04-2010
20100122044Data dependency scoreboarding - A parallel processing technique is described for performing parallel processing operations upon N-dimensional arrays of data elements for which a corresponding N-dimensional Scoreboard of status data is held. Hazard checking for data dependencies upon data elements within the N-dimensional array of data elements is performed by looking up the corresponding status value within the Scoreboard. The status data for a given data element within the Scoreboard is located at a position which can be derived from the position of the data elements within its N-dimensional array. Thus, a two-dimensional array of video macroblocks can have a corresponding two-dimensional Scoreboard of status data indicating whether individual macroblocks have, for example, either already been deblocked or have not already been deblocked.05-13-2010
20100125708Recursive Logical Partition Real Memory Map - A recursive logical partition real memory map mechanism is provided for use in address translation. The mechanism, which is provided in a data processing system, receives a first address based on an address submitted from a process of a currently active logical partition. The first address is translated into a second address using a recursive logical partition real memory (RLPRM) map data structure for the currently active logical partition. The memory is accessed using the second address. The RLPRM map data structure provides a plurality of translation table pointers, each translation table pointer pointing to a separate page table for a separate level of virtualization in the data processing system with the data processing system supporting multiple levels of virtualization.05-20-2010
20100125709Logical Partition Memory - A mechanism is provided, in a data processing system, for accessing memory based on an effective address submitted by a process of a partition. The mechanism may translate the effective address into a virtual address using a segment look-aside buffer. The mechanism may further translate the virtual address into a partition real address using a page table. Moreover, the mechanism may translate the partition real address into a system real address using a logical partition real memory map for the partition. The system real address may then be used to access the memory.05-20-2010
20110197035DATA STORAGE DEVICE, STORING MEDIUM ACCESS METHOD AND STORING MEDIUM THEREOF - A data storage device including a storing medium to shingle write and a controller to access the storing medium so that data is sequentially written on the storing medium using a mapping table based on Logical Block Address (LBA) included in a write command.08-11-2011
20100088478System for Internally Monitoring an Integrated Circuit - A system for internally monitoring an integrated circuit, wherein the contents of memory locations in the integrated circuit can be displayed on a dedicated display unit via a graphical interface device provided in the integrated circuit. The system provides a built-in means for observing the internal state of both firmware and hardware (as applicable) on the integrated circuit device. This facilitates the development of, and ongoing health monitoring of, the device in any system into which it may be incorporated. The provision of a graphical interface device provides a relatively high bandwidth for the outgoing data and so allows the internal state of the device to be monitored in real time.04-08-2010
20090210637PROVIDING DEVICE PARAMETERS - A non-volatile storage device has first and second controllers that provide external access to non-volatile memory using different protocols. In response to a request from the first controller, the second controller retrieves parameters from the non-volatile memory and provides the retrieved parameters to the first controller. In one embodiment, the device parameters are USB descriptors, which may include a vendor ID, a product ID, a product string, and/or a serial number. The first controller may be a Universal Serial Bus (USB) card reader controller. Examples of the second controller include a Secure Digital (SD) controller, a CompactFlash (CF) controller, a MemoryStick controller, or a different type of controller that is able to provide external access to the non-volatile memory. The first controller provides the device parameters to a host during enumeration of the non-volatile storage device. The device parameters may be used to establish settings for the first controller.08-20-2009
20100100693DETECTION OF ACTIVITY PATTERNS - A monitoring system (04-22-2010
20100082915Method and system for accessing storage via the internet - Embodiments of the present invention set forth methods and systems for accessing storage via the Internet. Specifically, one embodiment of the present invention sets forth a method, which includes the steps of automatically establishing a connection to the Internet, automatically logging into a first account and a second account, wherein first storage space is allocated to the first account and second storage space is allocated to the second account, aggregating the first storage space and the second storage space to formulate an aggregated storage space, and mapping the aggregated storage space into a set of contiguous memory locations.04-01-2010
20100082914RECORDING MEDIUM, DRIVE DEVICE, AND MOUNTING METHOD - A recording medium coupled to a drive device includes a management information storage area and a master boot record. Management information used for a mounting process of the recording medium by the drive device is stored in the management information storage area and a starting location and an area size of a drive area is stored in the master boot record.04-01-2010
20100082913STORAGE DEVICE AND METHOD FOR CONTROLLING STORAGE DEVICE - A storage device includes: a printed circuit board; a semiconductor memory package mounted on the printed circuit board via solder joints, the semiconductor memory package incorporating semiconductor memories; a sensor configured to measure a physical quantity relating to a state of the storage device; a database including a damage estimation model base to be used for estimating damage of the solder joints from the physical quantity measured by the sensor; a damage estimating module configured to calculate a damage estimation value of the solder joints from the physical quantity using the damage estimation model base; and a controller configured to control writing, reading, and erasure of electronic data to or from the semiconductor memories based on the damage estimation values calculated by the damage estimating module.04-01-2010
20100082911LOW POWER TERMINATION FOR MEMORY MODULES - An apparatus is provided that includes a memory controller to provide a first on-die termination (ODT) signal and a second ODT signal, a memory channel, a first memory module to couple to the memory channel, and a second memory module to couple to the memory channel. The first memory module may include a first memory having a first ODT circuit to receive the first ODT signal, and a second memory having a second ODT circuit to receive the first ODT signal. The first ODT signal may disable the ODT circuit of the first memory when the first memory is to be ACTIVE.04-01-2010
20100100692Exploiting Register High-Words - A method of utilizing registers in a processor device is provided. The method includes: determining a first operand based on an operand notation indicating a subset of high-order bits of a first register, the first register having a total of sixty-four bits; determining a second operand based on an operand notation indicating at least one of a subset of high-order bits of a second register and a subset of low-order bits of the second register, the second register having a total of sixty-four bits; performing an operation based on the first operand and the second operand; and updating at least one of the first register and the second register based on a result of the operation, and wherein the high-order bits include bits that are greater than thirty-two, and wherein the low-order bits include bits that are less than or equal to thirty-two.04-22-2010
20080235467MEMORY MANAGEMENT DEVICE AND METHOD, PROGRAM, AND MEMORY MANAGEMENT SYSTEM - A memory management device which is capable of allocating a memory unit accessible at a higher speed to data which is stored in a storage device having memory units different in access speed, without being limited in an storage area. The storage device comprises a BLC flash memory accessible at a predetermined access speed, an MLC flash memory accessible at a lower access speed than the predetermined access speed, a controller, and a RAM. The controller manages the BLC flash memory and the BLC flash memory in units each formed by a plurality of physical pages, and writes data in the physical pages, and the RAM holds page allocation information in which logical pages designated when writing data and the physical pages are associated with each other.09-25-2008
20110173399DISTRIBUTED PARALLEL MESSAGING FOR MULTIPROCESSOR SYSTEMS - A method and apparatus for distributed parallel messaging in a parallel computing system. The apparatus includes, at each node of a multiprocessor network, multiple injection messaging engine units and reception messaging engine units, each implementing a DMA engine and each supporting both multiple packet injection into and multiple reception from a network, in parallel. The reception side of the messaging unit (MU) includes a switch interface enabling writing of data of a packet received from the network to the memory system. The transmission side of the messaging unit, includes switch interface for reading from the memory system when injecting packets into the network.07-14-2011
20120290799GATHER AND SCATTER OPERATIONS IN MULTI-LEVEL MEMORY HIERARCHY - Methods and apparatus relating to gather or scatter operations in a multi-level cache are described. In some embodiments, a logic may determine whether to perform gather or scatter operations at a first memory or a second memory, based in part on a relative performance of performing the gather or scatter operations at the first memory and the second memory. Other embodiments are also described and claimed.11-15-2012
20120290798Data Compression and Compacting for Memory Devices - Embodiments of the present disclosure provide apparatuses and methods for determining a compacting arrangement to store logical addressable units, which include compressed data sectors, into hardware addressable units of a storage device. The compacting arrangement is based on compression information associated with the logical addressable units. A write module is used to write the compressed data sectors to the storage device according to the compacting arrangement.11-15-2012
20090006783Information Processing System, Reader/Writer, Information Processing Apparatus, Access Control Management Method and Program - There is provided an information processing system having a reader/writer and an information processing apparatus. The reader/writer include a processing section for executing service processing, a processing completion determining section for determining completion of the processing, a control information generating section for generating control information, depending on the determination result and a control information transmitting section for transmitting the control information, and the information processing apparatus includes an internal memory having an access control area, an in-chip communication section for receiving the control information, an internal memory managing section for storing the received control information in the internal memory, a control information obtaining section for obtaining the control information from the internal memory and an access control managing section for setting the access control for the access control area based on the control information.01-01-2009
20100228932METHOD OF TRANSFERRING AND ALIGNING OF INPUT DATA AND MEMORY DEVICE USING THE SAME - A method of transferring input data is disclosed. In one embodiment, during a burst having a burst length of N, the method comprises transferring to a memory device data for each of a plurality of unit intervals (UIs) of the burst through a plurality of terminals, wherein each of the transfers includes D bits of input data and at least some of the input data is to be written to the memory device. The method further comprises transferring to the memory device mask data during the burst as part of the input data, the mask data occupying at least two UIs, and transferring to the memory device content data during the burst as part of the input data, wherein the mask data transferred during each of the at least two UIs has the same value.09-09-2010
20090276586Wrap-around sequence numbers for recovering from power-fall in non-volatile memory - Incrementing sequence numbers in the metadata of non-volatile memory is used in the event of a resume from power fail to determine which data in the memory is current and valid, and which data is not. To reduce the amount of metadata space consumed by these sequence numbers, the numbers are permitted to be small enough to wrap around when the maximum value is reached. Two different techniques are disclosed to keep this wrap around condition from causing ambiguity in the relative values of the sequence numbers.11-05-2009
20090100234Data Access System and Data Access Method - A data access system and a data access method achieving effects of power saving and access synchronization during data access are provided. The data access system includes a data processing unit, a bridge device and a memory device. The data processing unit sends an access request signal to initiate data access of at least one unit data. The access of unit data is completed within a plurality of clock cycles of a reference clock signal. The bridge device generates an access signal according to the access request signal, the reference clock signal and a leading time. A pulse of the access signal is determined by the leading time within the clock cycles. The memory device executes the access of the unit data according to the access signal.04-16-2009
20090089516Reclaiming storage on a thin-provisioning storage device - A method, medium and apparatus for managing storage in a thin-provisioning storage device. The method includes ceasing to use storage on thinly provisioned storage delivered by a thin-provisioning storage device and notifying the thin-provisioning storage device of the unused storage. The method may further include reclaiming the unused storage in response to the notification. Alternatively, the notification may include recognizing the storage being freed and communicating the recognition to the storage device. In another form, the invention is a method, medium and apparatus for managing storage in a thin-provisioning storage device. This method includes delivering thinly provisioned storage and receiving notification that part of the thinly provisioned storage is no longer in use. The method may further include reclaiming that part of the thinly provisioned storage in response to the notification. Between receiving and reclaiming, the method may wait for a time to pass.04-02-2009
20090089517MEMORY CONTROL DEVICE AND SEMICONDUCTOR PROCESSING APPARATUS - The present invention provides a memory control device and a semiconductor processing apparatus which can be flexibly made adapted to a plurality of kinds of semiconductor memories. An SDRAM controller has: a register unit to which a command to be issued and a minimum interval (wait time) between issue of the command and issue of the next command are written by a CPU; and a command issuing unit that stops issue of the next command until the minimum interval written in the register elapses since issue of the command written in the register. Therefore, by changing software for the CPU, the SDRAM controller can be flexibly adapted to a plurality of kinds of SDRAMs.04-02-2009
20080209140Method for Managing Memories of Digital Computing Devices - The invention relates to a method for managing memories. When carrying out a process, at least one stack (08-28-2008
20110173400BUFFER MEMORY DEVICE, MEMORY SYSTEM, AND DATA TRANSFER METHOD - This invention may be applied for performing a burst write of write data, and increases efficiency of data transfer to memory. A buffer memory device transfers data between processors and a main memory in response to a memory access request issued by each of the processors. The buffer memory device includes: buffer memories each of which holds write data corresponding to the write request issued by a corresponding processor; a memory access information obtaining unit which obtains memory access information indicating a type of the memory access request; a determining unit which determines whether or not the type indicated by the memory access information obtained by the memory access information obtaining unit meets a predetermined condition; and a control unit which drains, to the main memory, data held in one of the buffer memories which meets the predetermined condition, when determined that the predetermined condition is met.07-14-2011
20110271065STORAGE SYSTEM FRONT END WITH PROTOCOL TRANSLATION - A storage system may include a first storage device and a protocol translator. The protocol translator may be programmed to receive a storage-access command formatted in a first protocol format. The protocol translator may also be programmed to translate the storage-access command into a second protocol format. The storage system may include a pseudo-target-module coupled to the protocol translator. The pseudo-target module may be programmed to send the command to the first storage device after the command is translated into the second protocol format. A virtualization engine may provide an interface to the first storage device, and the storage-access command may be sent to the first storage device through the virtualization engine. The pseudo-target module may be programmed to receive data from both storage-area-network devices and network-attached-storage devices.11-03-2011
20110271064STORAGE DEVICE AND METHOD FOR ACCESSING THE SAME - The present invention provides a storage device, which includes: a storage medium including a data address table, the data address table recording addresses for data stored in the storage medium; and a control module for receiving an external operation instruction and determining whether the operation instruction is an acceptable instruction, wherein if the operation instruction is the acceptable instruction, the control module determines an operation address corresponding to the operation instruction according to the data address table and executes the operation instruction in the storage medium according to the determined operation address, and if the operation instruction is not the acceptable instruction, the control module rejects the operation instruction.11-03-2011
20090276585Information Processing Device Having Securing Function - An access information storage section (11-05-2009
20090300295MECHANISM FOR MAINTAINING DETAILED TRACE INFORMATION RELEVANT TO THE CURRENT OPERATION BEING PROCESSED - A system, method, computer program product, and program storage device for storing trace information of a program is disclosed. Upon entering or calling a subroutine, a memory buffer is created. Whenever a nested subroutine is called inside the subroutine, a subordinate memory buffer is created. Upon completion of a subroutine execution, a corresponding memory buffer is deleted. When encountering an event (e.g., an error, a defect, a failure, a warning) during execution, all data in currently existing memory buffers are transferred to a secondary memory storage device (e.g., a disk).12-03-2009
20090282200Storage Device Procurement System - A storage device procurement system for managing storage failure and full warnings and conditions to minimize a need for storage device inventory. Such a system minimizes a need for storage system administrators to be knowledgeable with procurement options and procedures. Such a system provides for an end-to-end automated storage device procurement system by combining elements of a direct order model with elements of storage array monitoring.11-12-2009
20090282199Memory control system and method - The present invention systems and methods enable dynamic allocation and control of on-chip memory. In one embodiment, a system includes a plurality of internal memory components and a control component. The plurality of internal memory components store information. The control component controls access requests from a plurality of heterogeneous components to the internal memory components. The plurality of internal memory components are dynamically assigned to the plurality of heterogeneous components. The heterogeneous components can include different types of engines. In one embodiment, the system includes a clock compensation component for coordinating clocking for access requests from the heterogeneous engines.11-12-2009
20090287888SEMICONDUCTOR MEMORY DEVICE AND DATA INPUT/OUTPUT METHOD THEREOF - To solve a problem in that it is difficult for a conventional semiconductor memory device to improve a data transfer rate, there is provided a semiconductor memory device including: a first sub-array (data sub-array) that holds write data input from an outside of the semiconductor memory device; an input data recognition circuit (11-19-2009
20090287889READ/WRITE CLUSTERING SYSTEMS AND METHODS - Various embodiments include fault tolerant memory apparatus, methods, and systems, including a memory manager for supplying read and write requests to a memory device having a plurality of addressable memory locations. The memory manager includes a plurality of banks. Each bank includes a bank queue for storing read and write requests. The memory manager also includes a request arbiter connected to the plurality of banks. The request arbiter removes read and write requests from the bank queues for presentation to the memory device. The request arbiter includes a read phase of operation and a write phase of operation, wherein the request arbiter preferentially selects read requests for servicing during the read phase of operation and preferentially selects write requests for servicing during the write phase of operation.11-19-2009
20110271062INTEGRATED STORAGE CONTROLLER AND APPLIANCE METHOD AND SYSTEM - An integrated data center method and system combines a storage controller and one or more appliances onto a computer platform. Storage controller component executes on the hardware of a computer platform and has exclusive access to a first storage controller host bus adapter coupled to a storage shelf having one or more storage devices. The method and system provisions a virtualized instance of the hardware from the computer platform to deliver application services from an appliance component. The appliance component may share the processing resources from the computer platform through multiple different virtual machines. With respect to storage, aspects of the present invention exclusively associates an appliance host bus adapter from the computer platform to the appliance component. In addition, aspects of the present invention also provide control of the appliance host bus adapter to the appliance component passing through the virtualized instance of the hardware. To access the storage devices, the appliance host bus adapter and corresponding appliance component are coupled with a second storage controller host bus adapter associated with the storage controller component. Aspects of the present invention enable the access to the storage controller component and storage devices from each appliance host bus adapter. This enables applications associated with the appliance component to perform storage operations on the storage devices at a high throughput even though the applications are executing within a virtualized instance of the hardware.11-03-2011
20110271061STORAGE CONTROLLER AND STORAGE SUBSYSTEM - Some functions of multiple structural elements are integrated into a specific structural element and the specific structural element controls transmission/reception of signals to/from the respective structural elements.11-03-2011
20120297152HARDWARE ACCELERATION OF A WRITE-BUFFERING SOFTWARE TRANSACTIONAL MEMORY - A method and apparatus for accelerating a software transactional memory (STM) system is described herein. Annotation field are associated with lines of a transactional memory. An annotation field associated with a line of the transaction memory is initialized to a first value upon starting a transaction. In response to encountering a read operation in the transaction, then annotation field is checked. If the annotation field includes a first value, the read is serviced from the line of the transaction memory without having to search an additional write space. A second and third value in the annotation field potentially indicates whether a read operation missed the transactional memory or a tentative value is stored in a write space. Additionally, an additional bit in the annotation field, may be utilized to indicate whether previous read operations have been logged, allowing for subsequent redundant read logging to be reduced.11-22-2012
20120297150DATA STORAGE APPARATUS, CODING UNIT, SYSTEMS INCLUDING THE SAME, METHOD OF CODING AND METHOD OF READING DATA - In one embodiment, the data storage apparatus includes a control unit configured to decode at least one input command and configured to generate at least one of a read signal and a start signal in response to the input command. The start signal indicates to start an internal mode determination process. The data storage apparatus also includes a memory unit configured to output data in response to the read signal, and a coding unit configured to start and perform the internal mode determination process in response to the start signal. The internal mode determination process includes autonomously determining a coding mode, and the coding unit is configured to code the output data based on the determined coding mode to produce coded data.11-22-2012
20110208924DATA STORAGE CONTROL ON STORAGE DEVICES - An object of the present invention is to improve the usage efficiency of a storage extent in a storage system using the Allocation on Use (AOU) technique. A controller in the storage system allocates a storage extent in an actual volume to an extent in a virtual volume accessed by a host computer, detects any decrease in necessity for maintaining that allocation, and cancels the allocation of the storage extent in the actual volume to the extent in the virtual volume based on the detection result.08-25-2011
20080215827SELECTING STORAGE CLUSTERS TO USE TO ACCESS STORAGE - Provided are a method, system and program for selecting storage clusters to use to access storage. Input/Output (I/O) requests are transferred to a first storage cluster over a network to access storage. The storage may be additionally accessed via a second storage cluster over the network and both the first and second storage clusters are capable of accessing the storage. An unavailability of a first storage cluster is detected when the second storage cluster is available. A request is transmitted to hosts over the network to use the second storage cluster to access the storage. Hosts receiving the transmitted request send I/O requests to the storage via the second storage cluster if the second storage cluster is available.09-04-2008
20120297153BIT INVERSION IN MEMORY DEVICES - Bit inversions occurring in memory systems and apparatus are provided. Data is acquired from a source destined for a target. As the data is acquired from the source, the set bits associated with data are tabulated. If the total number of set bits exceeds more than half of the total bits, then an inversion flag is set. When the data is transferred to the target, the bits are inverted during the transfer if the inversion flag is set.11-22-2012
20090037670DISK CONTROLLER WITH MILLIMETER WAVE HOST INTERFACE AND METHOD FOR USE THEREWITH - A host interface module couples a disk controller of a disk drive to a host device. The host interface module includes a millimeter wave transceiver that is coupled to wirelessly communicate read commands, write commands, the read data and the write data between the disk controller and the host device over a millimeter wave communication path in accordance with a host interface protocol. A protocol conversion module is coupled to convert the read commands, the write commands and the write data from the host interface protocol and to convert the read data to the host interface protocol. A host module is coupled to decode the read commands and the write commands from the host device, to process the read commands to retrieve the read data from the disk drive via a read/write channel and to process the write commands to write the write data to the disk drive via the read/write channel.02-05-2009
20100146224REQUEST PROCESSING DEVICE, REQUEST PROCESSING SYSTEM, AND ACCESS TESTING METHOD - A request processing device includes a request sender that sends a write request or a read request to a storage device, a response processor that receives a response to a request which the request sender has sent, and a test request processor that converts a read response which is a response to a read request, into a test write request, and converts a write response which is a response to a write request into a test read request, from among responses that the response processor has received or from among responses that have been input from a device which is provided outside the request processing device.06-10-2010
20100146222Chipset Support For Non-Uniform Memory Access Among Heterogeneous Processing Units - A method for providing a first processor access to a memory associated with a second processor. The method includes receiving a first address map from the first processor that includes an MMIO aperture for a NUMA device, receiving a second address map from a second processor that includes MMIO apertures for hardware devices that the second processor is configured to access, and generating a global address map by combining the first and second address maps. The method further includes receiving an access request transmitted from the first processor to the NUMA device, generating a memory access request based on the first access request and a translation table that maps a first address associated with the first access request into a second address associated with the memory associated with the second processor, and routing the memory access request to the memory based on the global address map.06-10-2010
20080244198MICROPROCESSOR DESIGNING PROGRAM, MICROPOROCESSOR DESIGNING APPARATUS, AND MICROPROCESSOR - A microprocessor which can be operated with small power consumption, a microprocessor designing program which can design it in a short period of time, and a microprocessor designing apparatus. The microprocessor designing program comprises an execution program storing step of storing each of the execution programs in said specified address areas, in correspondence with the specification of said address areas made for each of the execution programs, an access number totalizing step of counting a total number of accesses given by the computation processing unit for each of the address areas, and an execution program name outputting step of outputting an execution program name outputted in an order based on said total number. The microprocessor designing apparatus packages a microprocessor designing program, and comprises an execution program name displaying component displaying, in characters, the name of an execution program outputted by the execution program name displaying step.10-02-2008
20100138616Input-output virtualization technique - Methods, systems, apparatuses and program products are disclosed for managing device virtualization in hypervisor and hypervisor-related environment which include both pass-thru I/O and emulated I/O.06-03-2010
20080250211Cache control method, cache device, and microcomputer - when a non-subsequent read occurs which is a read from a non-subsequent address not consecutive to the previous read address, a first cache memory sequentially caches respective data of the non-subsequent address and n addresses following the non-subsequent address, where n is an integer of one or greater, while the cached data of the n addresses are stored into a second cache memory, and subsequently, until the next non-subsequent read is performed, data of addresses following the last one of the n addresses are sequentially read from a memory, not via the first cache memory and stored into the second cache memory. In response to subsequent reads following the non-subsequent read, the second cache memory outputs the data of read addresses specified by the subsequent reads.10-09-2008
20080276055SYSTEMS AND METHODS FOR ALLOCATING CONTROL OF STORAGE MEDIA IN A NETWORK ENVIRONMENT - A method for dynamically allocating control of a storage device, the method comprising receiving an access request from a first computer requesting access to a storage device; directing, based upon the access request, a first storage controller computer to assume an inactive state with respect to control of the storage device; and directing, based upon the access request, a second storage controller computer to assume an active state with respect to control of the storage device.11-06-2008
20080276053Portable Device and Method for Controlling Deep Power Down Mode of Shared Memory - The memory device may include a first determination unit for determining whether entry into a DPD mode is to be made by interpreting signals received from a first processor, and generating and outputting a corresponding first DPD entry signal; a second determination unit for determining whether entry into the DPD mode is to be made by interpreting signals received from a second processor, and generating and outputting a corresponding second DPD entry signal; and a DPD determination unit for performing control for operation in the DPD mode only when the first DPD entry signal and the second DPD entry signal are respectively received from the first determination unit and the second determination unit. In accordance with the present invention, a single piece of memory operates in the DPD mode even when a plurality of processors shares the memory, so that power consumption can be minimized.11-06-2008
20080276050ERASE HANDLING METHOD FOR NON-VOLATILE MEMORY AND ELECTRONIC APPARATUS THEREOF - For an electronic apparatus with a sleep mode and an operation mode, an erasing command is issued to a memory controller that controls a non-volatile memory device before the electronic apparatus is entering the sleeping mode. Preferably, an estimated sleeping time is compared with a predetermined threshold for determining whether to activate erase operations to release space from the non-volatile memory device. Further, when the electronic apparatus returns from the sleep mode to the operation mode, the erase operations are checked whether they are complete. If the erase operations are not completed, another erase command is issued to the memory controller next time when the electronic apparatus is going to the sleep mode again.11-06-2008
20080235464System for conversion of update blocks based on comparison with a threshold size - A non-volatile memory storage system is provided. The non-volatile memory storage system comprises a non-volatile memory cell array and a processor in communication with the non-volatile memory cell array. The processor is configured to receive a write command to write data following a previous write command. Here, the write command and the previous write command have a discontinuity in logical addresses, where the discontinuity in logical addresses defines a gap between a logical address of the write command and a logical address of the previous write command. A sequential update block and preexisting data associated with the sequential update block are provided. The processor is further configured to compare the gap with a threshold size and write the data to the sequential update block if the gap is less than the threshold size.09-25-2008
20080235463Methods for conversion of update blocks based on comparison with a threshold size - A method for operating a memory system is provided. In this method, a write command is received to write data following a previous write command. The write command and the previous write command have a discontinuity in logical addresses and the discontinuity in logical addresses defines a gap between a logical address of the write command and a logical address of the previous write command. Here, a sequential update block and preexisting data associated with the sequential update block are provided. The gap is compared with a threshold size and the data are written to the sequential update block if the gap is less than the threshold size.09-25-2008
20090265515Information Processing Apparatus, Information Processing Method, and Computer Program - An information processing apparatus having a multi-processor unit including a plurality of processors. The multi-processor unit includes: a main-processor element including a main processor; and at least one sub-processor element having a sub-processor, a local memory corresponding to each of the processors, and a memory flow controller (MFC) executing data input from and data output to the local memory by DMA (Direct Memory Access), wherein the memory flow controller (MFC) inputs data from the outside of the multi-processor unit, stores the data into the local memory by DMA processing, and further outputs the data stored in the local memory to an external memory of the multi-processor unit or a device by DMA processing.10-22-2009
20090265514Efficiency of cache memory operations - A processing system 10-22-2009
20080209138File Blocking Mitigation - Embodiments are described for blocking the opening of a file. Some embodiments include receiving a request to open a file. In response, a portion of the file's data is examined to determine a true file format for the file. A determination is then made as to whether the true file format of the file has been set as blocked. Based on the determination that the file format is blocked from opening, the file is prevented from being loaded into memory and from being accessed. A message is then displayed to a user indicating that the file has been blocked from opening.08-28-2008
20090157984Avoiding use of an inter-unit network in a storage system having multiple storage control units - A storage system provides virtual ports, and is able to transfer the virtual ports among physical ports located on multiple storage control units making up the storage system. The storage system is able to manage logical volumes and/or virtual volumes and virtual ports as a group when considering whether to move logical/virtual volumes and/or virtual ports to another storage control unit in the storage system. When the storage system is instructed to transfer volumes, virtual ports, or a group of volumes and virtual ports among the storage control units, the storage system determines whether an inter-unit network will be required to be used following the transfer. When the storage system determines that the inter-unit network will be required if the transfer takes place, the storage system determines and presents an alternate storage control unit for the transfer to avoid use of the inter-unit network, thereby avoiding degraded performance.06-18-2009
20090313442CIRCULAR BUFFER SUPPORT IN A SINGLE INSTRUCTION MULTIPLE DATA (SIMD) DATA PROCESSSOR - A method is provided for generating a control vector. The method comprising: providing a circular buffer having a plurality of storage elements that are arranged sequentially from a designated first storage element to a designated last storage element, and when the designated last storage element of the plurality of storage elements is accessed, the access continuing in a sequential order continuing with the designated first storage element; determining a beginning storage element of the plurality of storage elements to be accessed; and generating a control vector, the control vector comprising a plurality of index values, each of the plurality of index values corresponding to one of the plurality of storage elements of the circular buffer to be accessed in the sequential order from the beginning storage element to an ending storage element.12-17-2009
20080229034DATA MANAGEMENT FOR IMAGE PROCESSING - An image processing system includes a memory for storing data associated with pixels of images, with the pixels having spatial coordinates in an image coordinate system having first and second axes; a processing device including a processor which processes the associated data; and an interface device which accesses in memory addresses associated with pixels of a block of pixels. In the interface device, access information is received indicating a base memory address, information regarding the dimensions of the block along the axes of the image coordinate system, and a storage method. At least one access rule is selected from multiple rules as a function of the storage method. The memory is accessed at the addresses associated with the pixels in the block, by applying the selected rule starting from the base address and taking into account the dimensions of the block.09-18-2008
20080294854Data management interface with plugins - A method and apparatus for managing data. A request to perform a data operation is received from an application, the request identifying data on which to perform the data operation. The request is delegated to one or more of a plurality of plugins based on the requested data operation, each of the plurality of plugins being associated with at least one distinct data operation. The one or more plugins perform the requested data operation.11-27-2008
20080215828System for Reading and Writing Data - A system for writing and reading data includes a controller accessible to at least one or more computing systems, a plurality of microprocessor units accessible to the controller, and a plurality of memory device configurations each having one dedicated bus connection to individual ones or multiples of the microprocessor units. The controller receives write and read requests from the one or more computing systems and selects which of the plurality of microprocessor units will write or read data associated with the requests.09-04-2008
20090119465Dynamic Loading of Virtual Volume Data in a Virtual Tape Server - Disclosed are a system, a method, and article of manufacture to provide for obtaining data storage device specific information from a data storage device using standard read/write commands. This method uses a host application to write a unique sequence of records to a logical volume of the data storage device. The data storage device detects the unique sequence of records for the logical volume and writes device specific information to the logical volume allowing the host application the ability to read the data storage device specific information using a read command for the logical volume.05-07-2009
20080276051Configurable Memory Protection - A method can include receiving a signal associated with an attempted access to data that is stored at a specific location in memory; obtaining a selection value that selects which memory protection register of multiple alternative memory protection registers is to provide a memory protection attribute for the specific location in memory; obtaining, from the selected memory protection register, a memory protection attribute; and controlling access to the specific location in memory based on the obtained memory protection attribute.11-06-2008
20120144132MANAGEMENT OF PERSISTENT MEMORY IN A MULTI-NODE COMPUTER SYSTEM - A method and apparatus creates and manages persistent memory (PM) in a multi-node computing system. A PM Manager in the service node creates and manages pools of nodes with various sizes of PM. A node manager uses the pools of nodes to load applications to the nodes according to the size of the available PM. The PM Manager can dynamically adjust the size of the PM according to the needs of the applications based on historical use or as determined by a system administrator. The PM Manager works with an operating system kernel on the nodes to provide persistent memory for application data and system metadata. The PM Manager uses the persistent memory to load applications to preserve data from one application to the next. Also, the data preserved in persistent memory may be system metadata such as file system data that will be available to subsequent applications.06-07-2012
20100146220EFFICIENT PROGRAM INSTRUMENTATION FOR MEMORY PROFILING - A system and method for performing efficient program instrumentation for memory profiling. A computing system comprises a memory profiler comprising a static binary instrumentation (SBI) tool and a dynamic binary analysis (DBA) tool. The profiler is configured to selectively instrument memory access operations of a software application. Instrumentation may be bypassed completely for an instruction if the instruction satisfies some predetermined conditions. Some sample conditions include the instruction accesses an address within a predetermined read-only area, the instruction accesses an address within a user-specified address range, and/or the instruction is a load instruction accessing a memory location determined from a data flow graph to store an initialized value. An instrumented memory access instruction may have memory checking analysis performed only upon an initial execution of the instruction in response to determining during initial execution that a read data value of the instruction is initialized. Both unnecessary instrumentation and memory checking analysis may be reduced.06-10-2010
20100146226Integrating Content-Laden Storage Media with Storage System - Integrating content into a storage system with substantially immediate access to that content. Providing high reliability and relatively easy operation with a storage system using redundant information for error correction. Having the storage system perform a “virtual write,” including substantially all steps associated with writing to the media to be integrated, except for the step of actually writing data to that media, including rewriting information relating to used disk blocks, and including rewriting any redundant information maintained by the storage system. Integrating the new physical media into the storage system, including accessing content already present on that media, free space already present on that media, and reading and writing that media. Recovering from errors during integration.06-10-2010
20110208923STORAGE METHOD AND SYSTEM, TERMINAL SERVICE BOARD, CONTROL BOARD AND STORAGE CHANNEL BOARD - A storage method and system, a terminal service board, a control board, and a storage channel board are provided. The system includes a terminal service board, a control board, and a storage channel board, where the terminal service board is configured to be connected with a terminal and the control board, process a request from the terminal, and send a processing result to the control board; the control board is configured to encapsulate data required to be stored onto a storage apparatus into a command according to the processing result, and submit the command to the storage channel board; the storage channel board is configured to be connected with the storage apparatus and the control board, and according to the command, store onto the storage apparatus the data required to be stored onto the storage apparatus. The control board becomes more focused on the storage processing, so that the efficiency of use for the control board is improved. Furthermore, as the influence of the interface card protocol to the control board is reduced significantly, the design of the control board is simplified.08-25-2011
20100005251Memory control circuit and integrated circuit - The memory unit is compatible with a plurality of operation modes. The plurality of operation modes include the normal mode allowing access and the standby mode consuming a lower power than the normal mode. The branch detection section detects a branch instruction from an instruction fetched from the memory unit by the CPU. The mode control section changes an operation mode of the memory unit according to a detection result by the branch detection section.01-07-2010
20100005250SIZE AND RETRY PROGRAMMABLE MULTI-SYNCHRONOUS FIFO - A size and retry programmable multi-synchronous FIFO. In one embodiment, a multi-synchronous FIFO memory generally comprises a selectable number of addressable memory locations for storing information; read control means synchronized by a read clock for controlling pop transactions configured to read from one or more of the selected number of addressable memory locations; write control means synchronized by a write clock asynchronous to the read clock for controlling push transactions to write to one or more of the selected number of addressable memory locations; and selectable transaction retry control means configured to cause read control means to repeat selected pop transactions and/or cause write control means to repeat selected push transactions. In another embodiment a method of retrying a transaction in a multi-synchronous FIFO having a selectable number of addressable memory locations generally comprises the steps of receiving a transaction request; storing the starting address of the transaction register in a start register; executing the transaction; incrementing the starting address in the transaction register after comparing the incremented address to the selected number of addressable memory locations; receiving a retry request; and retrying the transaction.01-07-2010
20090089514Implementing Asynchronous Request for Forcing Dynamic Memory into Self Refresh - In some embodiments a memory controller receives a signal indicating a power condition of a system. In response to the received signal the memory controller controls a clock enable signal to a memory, allows only already issued memory controller signals to finish, and forces the memory into a self refresh. A transition is made such that power is only provided to the memory controller and to the memory, and no power is provided to any other components in the system. Other embodiments are described and claimed.04-02-2009
20090031091CONTINUOUS TIMING CALIBRATED MEMORY INTERFACE - A system that adjusts the timing of write operations at a memory controller is described. This system operates by observing timing drift for read data at the memory controller, and then adjusting the timing of write operations at the memory controller based on the observed timing drift for the read data.01-29-2009
20090049254MEMORY CONTROLLER AND PROCESSOR SYSTEM - A memory controller includes a memory diagnosing part for controlling access from a CPU to a memory, and accessing and diagnosing the memory, an information setting part for setting cycle information according to a loaded condition of the CPU, and a cycle adjusting part for adjusting a cycle for the memory diagnosing part to access the memory based on the cycle information of the information setting part.02-19-2009
20120198184MEMORY MANAGEMENT METHOD, COMPUTER SYSTEM AND COMPUTER READABLE MEDIUM - It is provided a memory management method for releasing an unnecessary area in a memory area used by a program stored in the memory and executed by the computing device. The memory management method including the step of: setting in the memory, a first memory area which is used to execute the program; setting in the memory, a second memory area which can be operated by the program; setting a utilized area in the second memory area based on an instruction from the program; storing objects including data in the utilized area of the second memory area based on an instruction from the program; determining whether the program uses the objects stored in the utilized area within the second memory area; and releasing, by the computing device, the utilized area occupied by an object that is not used by the program among the objects stored in the utilized area.08-02-2012
20120198181System and Method for Managing a Memory as a Circular Buffer - System and method for facilitating data transfer between logic systems and a memory according to various conditions. Embodiments include systems and methods for facilitating and improving throughput of data transfers using a shared non-deterministic bus, a system and method for managing a memory as a circular buffer, and a system and method for facilitating data transfer between a first clock domain and a second clock domain. Embodiments may be implemented individually or in combination.08-02-2012
20080320245Method for writing data of an atomic transaction to a memory device - A method for writing data to a memory device is disclosed. In one embodiment, data of an atomic transaction is written to a first memory in a memory device. A determination is made regarding whether all of the data of the atomic transaction was written to the first memory. The data of the atomic transaction is read from the first memory and written to a second memory in the memory device only if it is determined that all of the data of the atomic transaction was written to the first memory.12-25-2008
20090083498Programmable processor and method with wide operations - A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are substantially larger than the data path width of the processor by using the contents of a general purpose register to specify a memory address at which a plurality of data path widths of data can be read or written, as well as the size and shape of the operand. In addition, several instructions and apparatus for implementing these instructions are described which obtain performance advantages if the operands are not limited to the width and accessible number of general purpose registers.03-26-2009
20090177848METHODS AND SYSTEMS FOR CLASSIFYING STORAGE SYSTEMS USING FIXED STATIC-IP ADDRESSES - A storage system for exchanging data with a host system, the storage system including a plurality of storage devices, each of the storage devices including: a non-volatile memory, wherein a fixed static-IP address resides in the non-volatile memory, the fixed static-IP address being common to two or more of the plurality of storage devices, and the fixed static-IP address providing enablement of a storage-device functionality of the storage device; a physical interface for operationally connecting the storage device with the host system; and a memory controller for: controlling the respective non-volatile memory; and exchanging data, using a communication protocol, via the respective fixed static-IP address. For at least one of the storage devices, the respective fixed static-IP address may be pre-loaded into the respective non-volatile memory during manufacture, or installed in the respective non-volatile memory after manufacture.07-09-2009
20100205387APPARATUS UTILIZING EFFICIENT HARDWARE IMPLEMENTATION OF SHADOW REGISTERS AND METHOD THEREOF - Embodiments of a processor architecture efficiently implement shadow registers in hardware. A register system in a processor includes a set of physical data registers coupled to register renaming logic. The register renaming logic stores data in and retrieves data from the set of physical registers when the processor is in a first processor state. The register renaming logic identifies ones of the set of physical registers that have a first operational state as a first group of registers and identifies the remaining ones of the set of physical registers as a second group of registers in response to an indication that the processor is to enter a second processor state from the first processor state. The register renaming logic stores data in and retrieves data from the second group of registers but not the first group of registers when the processor is in the second processor state.08-12-2010
20090049252REPLICATION ENGINE COMMUNICATING WITH A SPLITTER TO SPLIT WRITES BETWEEN A STORAGE CONTROLLER AND REPLICATION ENGINE - Provided are a method, system, and article of manufacture for a replication engine communicating with a splitter to split writes between a storage controller and replication engine. Communication is initiated with the splitter implemented in a storage controller managing access to primary volumes. A command is sent to the splitter to copy writes to one primary volume to the replication engine. Write data is received from the splitter to one of the primary volumes following the splitter receiving the command to copy the writes to the replication engine. A determination is made of a copy services function to use for the received data. The determined copy services function is invoked to transfer the received data to a secondary storage volume.02-19-2009
20090177849SYSTEM AND METHODS FOR MEMORY EXPANSION - This document discusses, among other things, an example system and methods for memory expansion. An example embodiment includes receiving a memory request from a memory controller over a channel. Based on the memory request, the example embodiment includes selecting a location in memory to couple to a sub-channel of the channel and configuring the set of field effect transistors to couple the channel with the sub-channel. In the example embodiment, data may be allowed to flow between the memory controller and the location in the memory over the channel and the sub-channel.07-09-2009
20090019240Information processing device, information processing method, and computer program - An information processing apparatus and method for enabling efficient content download and transfer processing operations are provided. In downloading content, a content identifier thereof is acquired, a particular piece of content subject to transfer to an external device is identified on the basis of the acquired content identifier, the identified content is retrieved from a data storage block, and the retrieved content is transferred to the external device or written to an information recording medium, so that the processing of content downloading, the processing of content transfer to an external device and content writing to an information recording medium such as CD can be executed as a sequence of processing operations, thereby providing significantly efficient content download and content transfer or content write processing operations.01-15-2009
20090063790Method and apparatus for managing configuration memory of reconfigurable hardware - Provided is a method of managing a configuration memory of reconfigurable hardware which can reconfigure hardware according to hardware configuration information. The method includes: determining at least one slot capable of currently storing the hardware configuration information on the basis of the states of a plurality of slots of the configuration memory; and storing hardware configuration information, which is stored in an external memory, in the determined at least one slot capable of currently storing the hardware configuration information. Accordingly, memory utilization can be improved even in dynamic environment such as data dependent control flow or multi-tasking.03-05-2009
20090055603MODIFIED COMPUTER ARCHITECTURE FOR A COMPUTER TO OPERATE IN A MULTIPLE COMPUTER SYSTEM - A modified computer architecture (02-26-2009
20090144511Enhanced Microprocessor or Microcontroller - An n-bit microprocessor device has an n-bit central processing unit (CPU); a plurality of special function registers and general purpose registers which are memory-mapped to a plurality of banks, with at least two 16-bit indirect memory address registers which are accessible by the CPU across all banks; a bank access unit for coupling the CPU with one of the plurality of banks; a data memory coupled with the CPU; and a program memory coupled with the CPU, wherein the indirect address registers are operable to access the data memory or program memory and wherein a bit in each of the indirect memory address registers indicates an access to the data memory or to the program memory.06-04-2009
20090144512MEMORY ACCESS CONTROL DEVICE, CONTROL METHOD, AND PROGRAM - A data conversion unit divides data to be written to, for example, a non-volatile memory having a limited number of times of rewriting including erasure of a memory device into divided write data having a predetermined bit width and subjects each of the divided write data to conversion to conversion data in which the update frequency from bit 06-04-2009
20090024806STORAGE DEVICE, STORAGE CONTROLLER, SYSTEM, METHOD OF STORING DATA, METHOD OF READING DATA AND FILE SYSTEM - A storage device comprises a storage location, an interface coupled to the storage location, and a data conversion circuit coupled to the storage location and to the interface. The interface is configured for an exchange of data between the storage device and external circuitry coupled to the interface. The data conversion circuit is configured for converting data from a first data format to a second data format. The data conversion circuit is configured to convert at least one of data read from the storage location before they are transferred to the interface, and data received via the interface before they are written to the storage location.01-22-2009
20110145518Systems and methods for using pre-computed parameters to execute processes represented by workflow models - Systems and methods consistent with the invention may include initiating an execution of the business process, the business process being represented by a workflow model that includes a synchronization point, retrieving, from a memory device of the computer system, a pre-computed parameter corresponding to the workflow model, and executing, using a processor of the computer system, the business process by using the pre-computed parameter, wherein the pre-computed parameter represents a configuration of the workflow model in which the synchronization point is activated.06-16-2011
20090198924Memory System Topologies Including A Buffer Device And An Integrated Circuit Memory Device - Systems, among other embodiments, include topologies (data and/or control/address information) between an integrated circuit buffer device (that may be coupled to a master, such as a memory controller) and a plurality of integrated circuit memory devices. For example, data may be provided between the plurality of integrated circuit memory devices and the integrated circuit buffer device using separate segmented (or point-to-point link) signal paths in response to control/address information provided from the integrated circuit buffer device to the plurality of integrated circuit buffer devices using a single fly-by (or bus) signal path. An integrated circuit buffer device enables configurable effective memory organization of the plurality of integrated circuit memory devices. The memory organization represented by the integrated circuit buffer device to a memory controller may be different than the actual memory organization behind or coupled to the integrated circuit buffer device. The buffer device segments and merges the data transferred between the memory controller that expects a particular memory organization and actual memory organization.08-06-2009
20090198922FILE-COPYING APPARATUS OF PORTABLE STORAGE MEDIA - The present invention provides a portable file-copying apparatus which includes a first connecting unit, a second connecting unit, and a control unit. The first connecting unit can receive a first portable storage media which includes an original file. The second connecting unit can receive a second portable storage media. Furthermore, the control unit is connected to the first connecting unit, the second connecting unit, and a memory. The control unit is applied for storing the original file in the memory, and copying the file to the second portable storage media in accordance with a control signal.08-06-2009
20090198920Processing Units Within a Multiprocessor System Adapted to Support Memory Locks - A processing unit within a multiprocessor system adapted to support memory locks is disclosed. In response to a request for accessing a data block being denied when a lock control section of the data block has been set by a memory controller, a timer countdown is started within a processing unit within a multiprocessor system. The requesting processing unit can relinquish the access request once the timer countdown has reached a timeout period.08-06-2009
20090198919A Non-Volatile Memory Device, and Method of Accessing a Non-Volatile Memory Device - A non-volatile memory device, and a method for accessing the non-volatile memory device are provided. The non-volatile memory device is connected to a host via a bus. The non-volatile memory device comprises an MCU. By independently processing the particular commands using only the auxiliary circuit, the MCU can cease to operate, thus saving power. By setting the bus into power saving mode when the non-volatile memory device is busy, the host and the non-volatile memory device would not communicate mutually, thus, saving power.08-06-2009
20090049253Program and erase diabling control of WPCAM by double controls - The present invention provides a semiconductor device and a method for controlling the semiconductor device, the semiconductor device including memory regions that include nonvolatile memory cells; program prohibition information units, the program prohibition information units storing program prohibition information to be used for determining whether to prohibit or allow programming in a plurality of memory regions corresponding to the program prohibition information units; a first prohibition information control circuit that prohibits a change of the program prohibition information from a program prohibiting state to a program allowing state with respect a memory region, the memory region is one of the plurality of corresponding memory regions, based on first prohibition information to be used for determining whether to prohibit a change of the program prohibition information from a program prohibiting state to a program allowing state with respect to the corresponding memory region; and a second prohibition information control circuit that prohibits a change of the program prohibition information from a program allowing state to a program prohibiting state with respect to the corresponding memory region, based on second prohibition information to be used for determining whether to prohibit a change of the program prohibition information from a program allowing state to a program prohibiting state with respect to the corresponding memory region02-19-2009
20090049251SPLITTING WRITES BETWEEN A STORAGE CONTROLLER AND REPLICATION ENGINE - Provided are a method, system, and article of manufacture for splitting writes between a storage controller and replication engine. A splitter executing in a storage controller manages access to primary volumes. An initialization command is received to communicate with a replication engine. A replication command is received for one primary volume and the primary volume is indicated as subject to replication. A write request is received to write data to a target primary volume of the primary volumes that is indicated as subject to the replication. The data in the write request is written to the target primary volume. The data in the write request is sent to the replication engine. The replication engine executes a copy services function associated with the target primary volume to write the data to a replication engine volume.02-19-2009
20090043975MEMORY DEVICE TRIMS - Methods and apparatus are provided. A memory device has a memory array, base trim circuitry adapted to store base control parameter values common to the memory array, and a reference trim circuit corresponding to a portion of the memory array. The reference trim circuit is adapted to store one or more reference control parameter values for respectively correcting one or more of the base control parameter values of the base trim circuitry for application to the portion of the memory array. The memory device may include an index circuit corresponding to the reference trim circuit. The index circuit is adapted to store one or more index parameter values for respectively selecting the one or more base control parameter values of the base trim circuitry for correction by the one or more reference control parameter values of the reference trim circuit.02-12-2009
20120144133METHOD AND SYSTEM FOR STORAGE AND EVALUATION OF DATA, ESPECIALLY VITAL DATA - A method for evaluation and aggregating storage of data, especially multivariate time series, such as sensor and vital data, the data being acquired via at least one sensor (06-07-2012
20090063789ENHANCED PERFORMANCE MEMORY SYSTEMS AND METHODS - Digital memory devices and systems, including memory systems and methods for operating such memory systems are disclosed. In the embodiments, a memory system may include a processor and a memory controller communicatively coupled to the processor. A memory bus communicates with at least two memory units through the memory bus. At least one divider unit may be interposed between the memory bus and the at least two memory units that is configured to approximately equally divide levels of received signals while matching an impedance of the memory bus to an impedance of the memory units.03-05-2009
20090063791COMPUTER SYSTEM, CONTROL METHOD THEREOF AND DATA PROCESSING APPARATUS - A computer system and a method of controlling a computer system, the computer system including: a first memory corresponding to a first channel and a second memory corresponding to a second channel; a data processor to process the data of the first and second channels in a time division manner; and a controller to inactivate the second channel if an amount of the data processed by the data processor is less than or equal to a predetermined value.03-05-2009
20090055602METHOD AND APPARATUS FOR EMBEDDED MEMORY SECURITY - A method and apparatus for embedded memory security is disclosed. One embodiment protects data in a memory block from unauthorized reading. When writing or reading data to or from the memory block an error correction code is used to calculate an ECC value, wherein the calculation of the ECC value is based on a combination of the data and a access identifier provided to the memory block prior to reading. The access identifier identifies the requesting program. A read error is signalled in case the calculated ECC value does not match a stored value thus indicating an access violation.02-26-2009
20110231617PORTABLE ELECTRONIC APPARATUS AND METHOD OF CONTROLLING A PORTABLE ELECTRONIC APPARATUS - According to one embodiment, a portable electronic apparatus executing performing process based on command input from an external apparatus, and storing a plurality of TLV data objects, the apparatus includes, a storage unit configured to store the data class and data character of each TLV data object, respectively in two storage areas spaced apart from each other, and to store addresses of a fixed length, representing the positions of the data characters, in association with the each data classes.09-22-2011
20090083500MEMORY CONTROLLER AND METHOD FOR COUPLING A NETWORK AND A MEMORY - A memory controller (SMC) is provided the for coupling a memory (MEM) to a network (N). The network (N) comprises at least one network interface (PCIEI) having network interface buffers (TPB, FCB) for implementing a flow control across the network (N). The memory controller (SMC) comprises a buffer managing unit (BMU) for managing the buffering of data from the network (N) to exchange data with the memory (MEM) in bursts. The buffer managing unit (BMU) furthermore monitors the network interface buffers (TPB, FCB) in order to determine whether sufficient data is present in the network interface buffers (FCB) such that a burst of data can be written to the memory (MEM) and whether sufficient space is available in the network interface buffers (TPB) such that a burst of data from the memory (MEM) can be buffered in the network interface buffers (TPB). The buffer managing unit (BMU) controls the access to the memory (MEM) according to according to the data and/or space in the network interface buffers (FCB, TPB).03-26-2009
20080263291METHOD OF DOING PACK ASCII Z SERIES INSTRUCTIONS - Emulation methods are provided for two PACK instructions, one for Unicode data and the other for ASCII coded data in which processing is carried out in a block-by-block fashion as opposed to a byte-by-byte fashion as a way to provide superior performance in the face of the usual challenges facing the execution of emulated data processing machine instructions as opposed to native instructions.10-23-2008
20080263290MEMORY CONTROL APPARATUS AND MEMORY CONTROL METHOD - According to one embodiment, a memory control apparatus controls a memory having a plurality of banks. This memory control apparatus has an access control section controlling such that a second access request issued from a second access unit is accepted after a first access request issued from a first access unit is accepted. This access control section controls so as to accept an access request to a non-access bank which is different from a bank accessed by the first access request and having low possibility of being accessed by the first access unit continuously, among the second access requests.10-23-2008
20080263289Storage controller and storage control method - Provided are a storage controller and a storage control method capable of improving the transaction performance. This storage controller includes a disk controller for receiving a read command and a write command from a host computer, and an external disk controller and an internal disk device for sending and receiving data to and from the disk controller. A storage device of the external disk controller or the internal disk controller processes the access from the disk controller in physical sub-block units. When the disk controller is to access the storage device of the external disk controller or the internal disk device in logical sub-block units in which an additional code containing a guarantee code is added to user data, it makes such access in minimum common multiple units of logical sub-blocks and physical sub-blocks, and changes the guarantee code length.10-23-2008
20110231618OPTICAL INTERCONNECT IN HIGH-SPEED MEMORY SYSTEMS - A optical link for achieving electrical isolation between a controller and a memory device is disclosed. The optical link increases the noise immunity of electrical interconnections, and allows the memory device to be placed a greater distance from the processor than is conventional without power-consuming I/O buffers.09-22-2011
20110231619METHOD AND SYSTEM FOR TRANSFORMATION OF LOGICAL DATA OBJECTS FOR STORAGE - Systems capable of transformation of logical data objects for storage and methods of operating thereof are provided. One method includes identifying among a plurality of requests addressed to the storage device two or more “write” requests addressed to the same logical data object, deriving data chunks corresponding to identified “write” requests and transforming the derived data chunks, grouping the transformed data chunks in accordance with the order the requests have been received and in accordance with a predefined criteria, generating a grouped “write” request to the storage device, and providing mapping in a manner facilitating one-to-one relationship between the data in the obtained data chunks and the data to be read from the transformed logical object. The method further includes obtaining an acknowledging response from the storage device, multiplying the obtained acknowledging response, and sending respective acknowledgements to each source that initiated each respective “write” request.09-22-2011
20110231620MEMORY CONTROLLER, PCB, COMPUTER SYSTEM AND MEMORY ADJUSTING METHOD - A memory controller, a PCB and a computer system employing the memory controller, and a memory adjusting method using the memory controller. The memory controller interfaces data reading from and writing to a memory and includes: a characteristic estimating part estimating a characteristic of a memory output signal outputted from the memory for the data reading and writing; and a characteristic adjusting part controlling the memory so that the characteristic of the memory output signal is within a predetermined reference range if the characteristic of the memory output signal estimated by the characteristic estimating part is beyond the predetermined reference range.09-22-2011
20090083499Ordered Storage Structure Providing Enhanced Access to Stored Items - An ordered storage structure implemented based on a content addressable memory (CAM). In an embodiment, a set of identifiers are formed with an order matching a desired access order for items. Each item is stored with a corresponding identifier in an entry of the CAM, with the identifiers being stored in the searchable fields/columns of the CAM. Thus, the items can be retrieved in the desired access order by providing the identifiers as search key inputs to the CAM in the desired access order.03-26-2009
20090198921DATA PROCESSING SYSTEM, PROCESSOR AND METHOD OF DATA PROCESSING HAVING REDUCED ALIASING IN BRANCH LOGIC - In at least one embodiment, an indexed table circuit includes a plurality of banks for storing data to be accessed and a split index array. The indexed table circuit is organized in a plurality of entries each corresponding to a respective one of a plurality of different entry indices, where each entry includes a storage location in the plurality of banks and the split index array. The indexed table circuit further includes selection logic that, responsive to read access of an entry among the plurality of entries utilizing an entry index of a bit string, utilizes a split index read from the split index array to select a set of one or more bits of a tag of the bit string, utilizes the selected set of one or more bits to select data read from one of the plurality of banks, and outputs the selected data.08-06-2009
20110225376MEMORY MANAGER FOR A NETWORK COMMUNICATIONS PROCESSOR ARCHITECTURE - Described embodiments provide a memory manager for a network processor having a plurality of processing modules and a shared memory. The memory manager allocates blocks of the shared memory to requesting ones of the plurality of processing modules. A free block list tracks availability of memory blocks of the shared memory. A reference counter maintains, for each allocated memory block, a reference count indicating a number of access requests to the memory block by ones of the plurality of processing modules. The reference count is located with data at the allocated memory block. For subsequent access requests to a given memory block concurrent with processing of a prior access request to the memory block, a memory access accumulator (i) accumulates an incremental value corresponding to the subsequent access requests, (ii) updates the reference count associated with the memory block, and (iii) updates the memory block with the accumulated result.09-15-2011
20090210638ADDRESS MAPPING OF PROGRAM CODE AND DATA IN MEMORY - A system for mapping information addresses in a memory. The system includes a memory wherein each byte is mapped to a plurality of unique addresses and a microprocessor for assigning at least one of the unique addresses to the information. The information can be program code fragments and/or data. Also disclosed is a method for mapping information addresses in a memory utilizing such a system. The method includes mapping each byte of memory into a plurality of unique addresses and assigning at least one of the unique addresses to the information.08-20-2009
20090254718Local Memories with Permutation Functionality for Digital Signal Processors - A digital signal processor (DSP) co-processor according to a clustered architecture with local memories. Each cluster in the architecture includes multiple sub-clusters, each sub-cluster capable of executing one or two instructions that may be specifically directed to a particular DSP operation. The sub-clusters in each cluster communicate with global memory resources by way of a crossbar switch in the cluster. One or more of the sub-clusters has a dedicated local memory that can be accessed in a random access manner, in a vector access manner, or in a streaming or stack manner. The local memory is arranged as a plurality of banks. In response to certain vector access instructions, the input data may be permuted among the banks prior to a write, or permuted after being read from the banks, according to a permutation pattern stored in a register.10-08-2009
20120198183SUCCESSIVE APPROXIMATION RESISTOR DETECTION - An apparatus comprises a connector configured to receive an electrical contact of an accessory device that is electrically coupled to a resistor of the accessory device, a current source configured to apply a specified current to the resistor to generate a resulting voltage, a comparator configured to receive and compare the resulting voltage to a reference voltage, and a controller configured to store an outcome of the comparison as a bit in a register, to adjust the applied current using the outcome of the comparison, and to determine a resistance value for the resistor using the bit stored in the register.08-02-2012
20120198180NONVOLATILE MEMORY SYSTEM AND FLAG DATA INPUT/OUTPUT METHOD FOR THE SAME - Various embodiments of a nonvolatile memory system and related methods are disclosed. In one exemplary embodiment, the memory system may include: a memory area including a main memory area and a flag memory area; and an input/output controller configured to receive main data through a main data input line and provide the received main data to a page buffer circuit in response to a main data input control signal. The input/output controller may be further configured to receive flag data through the main data input line and provide the received flag data to the page buffer circuit in response to a flag data input control signal.08-02-2012
20090240898Storage System and Method of Taking Over Logical Unit in Storage System - A storage apparatus includes a drive unit in which a logical unit is formed, and a controller unit for accessing the logical unit by controlling the drive unit according to an access request sent from a host apparatus. The storage apparatus issues a logical unit takeover request to the other storage apparatuses, allocates a logical unit of another storage apparatus that will accept the transfer of the logical volume to its own logical unit according to a takeover approval sent from other storage apparatuses in response to the takeover request, and thereafter migrates data of the own logical unit to a logical unit of another storage apparatus. Subsequently, the path is switched so that the access request from the host apparatus is given to one of the other storage apparatuses.09-24-2009
20090248995ALLOCATION CONTROL APPARATUS AND METHOD THEREOF - An allocation control apparatus may access an address table storing addresses of slice areas allocated in a storage area for an entire storage system having a plurality of storage devices and addresses that do not correspond to allocated slice areas. The allocation control apparatus includes a reception unit receiving a request for allocating an arbitrary storage capacity an allocation unit allocating, by referring to the address table, an address that does not correspond to the allocated slice area for at least a part of the requested storage capacity and allocates an address for the slice area to the remaining storage capacity when the reception unit receives the allocation request, and a transmission unit transmitting the result allocated by the allocation unit to a requesting source of the allocation request.10-01-2009
20090254716COORDINATED REMOTE AND LOCAL MACHINE CONFIGURATION - A method, system, and computer program product for coordinating the configuration of local and remote storage subsystems for a local client is provided. A command sender is configured on a local storage subsystem to create remote command objects based on commands received from the local client, and deliver the remote command objects to a remote storage subsystem for execution. A command receiver is configured on the remote storage subsystem, the command receiver service having an interface to receive the remote command objects. A remote connection bucket is configured to manage at least one connection between the local storage subsystem and the remote storage subsystem.10-08-2009
20090254719SWITCH APPARATUS - A method for controlling a switch apparatus connected to a first and a second storage apparatus, and a host, the switch apparatus managing a virtual storage area maintained by the first and second storage apparatuses, the host accessible to the virtual storage area by transmitting a command for identifying a subarea of the virtual storage area, the second storage apparatus allowable to an access faster than the first storage apparatus does, the method includes: receiving a command; determining which of the first and second storage apparatuses maintains the subarea to be accessed; accessing the subarea corresponding to the command; detecting a frequency of access to each of the subareas; and moving data stored in the first storage apparatus and having higher frequency of access than data stored in the second storage apparatus into the subareas maintained in the second storage apparatus.10-08-2009
20090254717STORAGE SYSTEM AND METHOD THEREOF - A storage system and a method thereof. The storage system comprises first and second storage devices, first and second analog front ends, and a controller. The first and second analog front ends, coupled to the first and second storage devices, receive first and second analog data from the first and second drive devices for conversion to first and second digital data. The controller, coupled to the first and second analog front ends, comprises a signal processor and a common memory. The signal processor receives the first and second digital data to perform first and second digital signal processing and access the common memory. The common memory is coupled to the signal processor to be accessed thereby.10-08-2009
20090254720SYSTEM FOR REBUILDING DISPERSED DATA - A digital data file storage system is disclosed in which original data files to be stored are dispersed using some form of information dispersal algorithm into a number of file “slices” or subsets in such a manner that the data in each file share is less usable or less recognizable or completely unusable or completely unrecognizable by itself except when combined with some or all of the other file shares. These file shares are stored on separate digital data storage devices as a way of increasing privacy and security. As dispersed file shares are being transferred to or stored on a grid of distributed storage locations, various grid resources may become non-operational or may operate below at a less than optimal level. When dispersed file shares are being written to a dispersed storage grid which not available, the grid clients designates the dispersed data shares that could not be written at that time on a Rebuild List. In addition when grid resources already storing dispersed data become non-available, a process within the dispersed storage grid designates the dispersed data shares that need to be recreated on the Rebuild List. At other points in time a separate process reads the set of Rebuild Lists used to create the corresponding dispersed data and stores that data on available grid resources.10-08-2009
20090157987System and Method for Creating Self-Authenticating Documents Including Unique Content Identifiers - One embodiment of a method for creating a self-authenticating document includes receiving a request to retrieve a data element identified by a content identifier, identifying a storage location associated with the content identifier, retrieving a data element stored at the storage location, calculating a second content identifier of the retrieved data element, comparing the content identifier and the second content identifier, if the content identifier and the second content identifier match, creating an image of the retrieved data element, creating a representation of the stored content identifier, creating a representation of metadata associated with the retrieved data element, and creating a document that includes the image of the retrieved data element, the representation of the stored content identifier, and the representation of metadata. The representation of the stored content identifier may be an alphanumeric string or a graphical representation derived from the stored content identifier.06-18-2009
20100180087METHOD FOR ACCELERATING INTERNET SMALL COMPUTER SYSTEM INTERFACE DATA AND PROCESSING SYSTEM THEREOF - A communication method for accelerating Internet small computer system interface data and a processing system thereof are used for sending a plurality of data packets to a plurality of storage devices by a target of the Internet small computer system interface. The communication method includes the following steps. An access request for accessing the storage devices is received by the target. A plurality of small computer interface commands is generated according to the access request. The small computer interface commands are read by an egress packet generator in the target. An address resolving procedure is performed by the egress packet generator for converting the small computer interface commands to a plurality of network packets. A first check code is generated according to a storage content in each network packet. The first check codes are added to the network packets.07-15-2010
20100161916METHOD AND APPARATUS FOR REBUILDING DATA IN A DISPERSED DATA STORAGE NETWORK - A method begins by identifying a data slice requiring rebuilding to produce an identified data slice, wherein the identified data slice is one of a plurality of data slices that constitute a data segment and wherein each of the plurality of data slices is assigned for storage by a corresponding one of a plurality of data slice servers. The method continues by retrieving at least m number of data slices from at least m number of the plurality of data slice servers, wherein m data slices of the plurality of data slices enable reconstruction of the data segment, and wherein the at least m number of data slices does not include the identified data slice. The method continues by reconstructing the identified data slice from the at least m number of data slices to produce a rebuilt data slice. The method continues by writing the rebuilt data slice to the corresponding one of the plurality of data slice servers or to a new slice server.06-24-2010
20090259814MEMORY CONTROL APPARATUS AND METHOD FOR CONTROLLING THE SAME - Disclosed herein is a memory control apparatus including: a plurality of buffers configured to store data; a plurality of input ports configured to input the data to be written into the buffers; a plurality of output ports configured to output the data read from the buffers; a write control circuit configured to write the data inputted via each of the input ports into an unused one of the buffers; and a read control circuit configured to read the data written into the unused buffer, and supply the read data to a particular one of the output ports corresponding to a destination of the data.10-15-2009
20080307171SYSTEM AND METHOD FOR INTRUSION PROTECTION OF NETWORK STORAGE - Protection mechanism is provided for data stored in logical volumes, especially during the time the corresponding host computer is off line. Additionally, integrity check mechanism is provided for logical volume when the host computer is started, so that host computer can detect unauthorized access to its assigned logical volume during off-line period, and execute security check.12-11-2008
20100153662FACILITATING GATED STORES WITHOUT DATA BYPASS - One embodiment of the present invention provides a system that facilitates precise exception semantics for a virtual machine. During operation, the system executes a program in the virtual machine using a processor that includes a gated store buffer that stores values to be written to a memory. This gated store buffer is configured to delay a store to the memory until after a speculatively-optimized region of the program commits. The processor signals an exception when it detects that a load following the store is attempting to access the same memory region being written by the store prior to the commitment of the speculatively-optimized region.06-17-2010
20120246419CONCURRENT MEMORY BANK ACCESS AND REFRESH REQUEST QUEUING - An apparatus and system associated with memory are disclosed herein. In various embodiments, an apparatus may include first circuitry configured to queue pending refresh requests for a plurality of memory banks; and second circuitry coupled to the first circuitry and configured to set a refresh flag in response to a determination that a number of queued pending refresh requests for a memory bank from the plurality of memory banks exceeds a predetermined number. Other embodiments may be disclosed and/or claimed.09-27-2012
20120246418MEMORY ARCHITECTURE FOR DISPLAY DEVICE AND CONTROL METHOD THEREOF - A memory architecture for a display device and a control method thereof are provided. The memory architecture includes a display data memory and a memory controller. The display data memory includes N sub-memories and N×M arbiters, wherein N is a positive integer and M is a positive integer equal to or greater than 2. Each sub-memory includes M memory blocks divided by an address. Each M arbiters are coupled to the M memory blocks of each sub-memory. The memory controller, coupled to the N×M arbiters, generates N×M sets of request signals and output address signals according to a set of an input request signal and an input address signal, and transmits to the N×M arbiters to sequentially control the N×M arbiters.09-27-2012
20120246414LOCK-FREE RELEASE OF SHADOW PAGES IN A DATA STORAGE APPLICATION - Storage pages in a data storage application can be designated as having one of a used status, a free status, and a shadow status. The storage pages having the shadow status remain in use but available for conversion to the free status after completion of a savepoint. The storage pages designated to the shadow status can be assigned among at least a first group and a second group. A first savepoint can be invoked during which the storage pages designated to the shadow status and assigned to the first group are converted to the free status, and a second savepoint can be invoked during which the storage pages designated to the shadow status and assigned to the second group are converted to the free status. In this manner, locking of the system during a savepoint is not required. Related methods, systems, and articles of manufacture are also disclosed.09-27-2012
20120246420INTERACTING WITH DATA IN HIDDEN STORAGE - Unused storage space within a data storage is utilized to store data while effectively making it appear to the operating system, other programs, and the user that the space is still available or unused. The space used to store the hidden data remains available for use by the operating system, other programs and uses upon a request. File system requests are monitored such that the hidden storage area remains hidden from unauthorized processes as well as to restrict operations within the hidden storage area that are attempted by unauthorized processes.09-27-2012
20120246417INFORMATION PROCESSING SYSTEM, INFORMATION PROCESSING METHOD, AND NON-TRANSITORY COMPUTER READABLE MEDIUM STORING PROGRAM - An information processing system includes: a storage device that stores information including settings information which is configured to an information processing apparatus, attribute management information indicating whether each settings information item is limited information with an update limit to the settings information or non-limited information without an update limit to the settings information, and apparatus specification information for specifying the information processing apparatus; and an information processing apparatus including an input unit that reads information from the storage device when the storage device is connected, a determining unit that compares the apparatus specification information read by the input unit with the apparatus specification information for specifying the information processing apparatus which is stored in a storage unit and determines whether the apparatus settings information read by the input unit is identical to the apparatus settings information of the information processing apparatus, and an update unit that updates the settings information.09-27-2012
20130219134WRITE DATA MASK METHOD AND SYSTEM - A method and system for performing byte-writes are described, where byte-writes involve writing only particular bytes of a multiple byte write operation. Embodiments include mask data that indicates which bytes are to be written in a byte-write operation. No dedicated mask pin(s) or dedicated mask line(s) are used. In one embodiment, the mask data is transmitted on data lines and store in response to a write_mask command. In one embodiment, the mask data is transmitted as part of the write command.08-22-2013
20130219133INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING SYSTEM, AND NON-TRANSITORY COMPUTER READABLE MEDIUM STORING INFORMATION PROCESSING PROGRAM - An information processing apparatus includes a detecting unit that detects a capacity of a free space of a non-volatile storage device in an apparatus including the non-volatile storage device and a volatile storage device, a determining unit that determines whether the setting of notification destination information to the non-volatile storage device is available on the basis of the detected capacity, an information setting unit that sets the notification destination information to the volatile storage device when the determining unit determines that the setting of the notification destination information to the non-volatile storage device is not available, and an interval setting unit that sets an interval of communication for management with the apparatus to be shorter than that set when it is determined that the setting of the notification destination information is available, if the determining unit determines that the setting of the notification destination information is not available.08-22-2013
20100161915METHOD AND SYSTEM CONTROLLING PAGE OPEN TIME FOR MEMORY DEVICE - A method and apparatus adaptively controlling a page open time for a memory device are disclosed. The method includes determining a page open maintenance time of an access-requested page based on system information and intellectual property (IP) request information; and controlling closing of an open page based on the determined page open maintenance time.06-24-2010
20100161914AUTONOMOUS MEMORY SUBSYSTEMS IN COMPUTING PLATFORMS - Embodiments of the invention are generally directed to systems, methods, and apparatuses for autonomous memory subsystems in computing platforms. In some embodiments, the autonomous memory mechanism includes one or more autonomous memory logic instances (AMLs) and a transaction protocol to control the AMLs. The autonomous memory mechanism can be employed to accelerate bulk memory operations. Other embodiments are described and claimed.06-24-2010
20100262789Methods and Devices for Accessing a Memory and a Central Processing Unit Using the Same - A memory accessing method including the following steps is provided. Firstly, two instructions are fetched. Next, the two instructions are respectively decoded to obtain two operation fields and two address fields. The two operation fields indicate the type of operation in accessing the memory. One of the address fields includes a first upper address corresponding to the first memory block and a first lower address corresponding to a first memory unit of the first memory block. The other one of the two address fields includes a second upper address corresponding to the second memory block and a second lower address corresponding to a second memory unit of the second memory block. Then, whether two instructions are performing the same type of operation on the same memory block is determined. If yes, the type of operation indicated by the two operation fields is performed on the corresponding memory block parallelly.10-14-2010
20100191924METHOD AND SYSTEM FOR CONTROLLING MEMORY ACCESSES TO MEMORY MODULES HAVING AMEMORY HUB ARCHITECTURE - A computer system includes a memory hub controller coupled to a plurality of memory modules. The memory hub controller includes a memory request queue that couples memory requests and corresponding request identifier to the memory modules. Each of the memory modules accesses memory devices based on the memory requests and generates response status signals from the request identifier when the corresponding memory request is serviced. These response status signals are coupled from the memory modules to the memory hub controller along with or separate from any read data. The memory hub controller uses the response status signal to control the coupling of memory requests to the memory modules and thereby control the number of outstanding memory requests in each of the memory modules.07-29-2010
20100191922DATA STORAGE PERFORMANCE ENHANCEMENT THROUGH A WRITE ACTIVITY LEVEL METRIC RECORDED IN HIGH PERFORMANCE BLOCK STORAGE METADATA - A sequence of fixed-size blocks defines a page (e.g., in a server system, storage subsystem, DASD, etc.). Each fixed-size block includes a data block and a footer. A high performance block storage metadata unit associated with the page is created from a confluence of the footers. The confluence of footers has space available for application metadata. In an embodiment, the metadata space is utilized to record a “write activity level” metric, and a timestamp. The metric indicates the write frequency or “hotness” of the page, and its value changes over time as the activity level changes. Storage subsystem performance may be enhanced by mapping frequently accessed pages to higher performance physical disks and mapping infrequently accessed pages to lower power physical disks. This approach is advantageous in that the metric is recorded on a non-volatile basis and may be readily communicated between system components (e.g., between a host computer and a storage subsystem).07-29-2010
20080320251METHOD AND SYSTEM FOR CENTRALIZED MEMORY MANAGEMENT IN WIRELESS TERMINAL DEVICES - Methods and systems for controlling centralized memory management in wireless terminal devices. Memory management scripts associated with a wireless application are stored in a registry accessible through a data network for on-demand download and execution. A memory management kernel in each terminal device monitors a memory utilization of the terminal device. Based on the memory utilization, the memory management kernel interacts with an application gateway hosting the terminal device to download and execute one or more of the memory management scripts.12-25-2008
20100262791SOFTWARE REFRESHED MEMORY DEVICE AND METHOD - A software refreshed memory device comprises a plurality of memory cells that must be periodically refreshed to avoid losing data. Preferably, the memory cells can avoid losing data even though the time interval between successive memory refresh operations is relatively long, as compared to the time interval between successive memory refresh operations in a conventional volatile memory device, such as a DRAM. A processor can perform periodic memory refresh operations by executing a set of memory refresh instructions implemented in software, rather than in hardware. Accordingly, the memory device can advantageously be simplified, because the need for memory refresh circuitry and for a unique refresh control signal are advantageously eliminated. Moreover, the processor executing the memory refresh instructions can typically perform more sophisticated algorithms, as compared to memory refresh circuitry implemented in hardware, for determining when to perform a memory refresh operation. For example, the processor can determine whether each individual memory cell needs to be refreshed, thereby advantageously avoiding performing unnecessary refresh operations on memory cells that do not need to be refreshed.10-14-2010
20100191923Data Processing In A Computing Environment - Methods, apparatus, and products for data processing in a computing environment including allocating, by an operating system for an application, a virtual address spaces with each virtual address space mapped to a same physical address space and each virtual address space associated with an operation; receiving, from the application, an instruction to store a value in a specific virtual address, the specific virtual address contained within one of the allocated virtual address spaces; identifying a physical address associated with the specific virtual address; performing, with the value and the contents of the identified physical address, the operation associated with the virtual address space containing the specific virtual address; and storing a result of the operation in the identified physical address.07-29-2010
20120198182MULTI-CORE SYSTEM AND METHOD FOR PROCESSING DATA IN PARALLEL IN MULTI-CORE SYSTEM - A multi-core system and a method for processing data in parallel in the multi-core system are provided. In the multi-core system, partitioning and allocating of data may be dynamically controlled based on local memory information. Thus, it is possible to increase an availability of a Central Processing Unit (CPU) and a local memory, and is possible to improve a performance of data parallel processing.08-02-2012
20100180088Memory Dispatching Method Applied to Real-time Data ETL System - As for the memory dispatching method applied to real-time data ETL system, the main ETL dispatching program executes one task according to preset sequence. In the execution, some key information are memorized by dispatching engine, such as lscycle (latest successful data cycle), curcycle (current processing data cycle), and endcycle (processing end data cycle), etc., are transferred to the called program. After the execution of the called program, the dispatching engine records and keeps the updated dispatching information; in the data re-extraction, memory dispatching method is adopted for the automatic re-extraction of some tasks and some cycles therein. Memory dispatching method (state-based dispatching method) solves the defect in stateless of traditional ETL dispatching program, simplifies the tasks of the called program, makes the called program focus on its own business logic through the memory state, wins plentiful development time for the real-time data ETL field, and greatly enhances the efficiency of project implementation.07-15-2010
20090077327Method and apparatus for enabling a NAS system to utilize thin provisioning - A NAS (network attached storage) controller managing file system data is configured for use in a storage system having thin provisioning capability. Physical storage capacity is used efficiently by making it possible for the NAS controller to identify to a disk array system having thin provisioning capability which segments of a thin provisioned volume are no longer in use. File system blocks or block groups no longer in use by the NAS controller are identified by the NAS controller. The NAS controller sends a release request to the disk array system specifying thin provisioning segments that correspond to the identified FS blocks or block groups. The release request instructs the disk array system to release chunks of physical storage capacity assigned to the specified thin provisioning segments so that the physical storage capacity can be made available for reuse in the disk array storage system.03-19-2009
20090077328Methods and apparatuses for heat management in storage systems - An information system includes a storage system having a controller in communication with a plurality of storage devices. In some embodiments, the storage devices are divided into at least a first group and a second group, with a first temperature sensor sensing a temperature condition for the first group, and a second temperature sensor for sensing a temperature condition for the second group. A heat distribution rule designates the first groups to be high temperature groups and the second groups to be low temperature groups. The heat distribution rule is implemented by designating a higher load of input/output (I/O) operations to the high temperature groups than to the low temperature groups, such as by migrating volumes having high I/O loads to the high temperature groups. In other embodiments, there are multiple storage systems, and each storage system is designated as a high temperature system or a low temperature system.03-19-2009
20100241816OPTIMIZED TRANSFER OF PACKETS IN A RESOURCE CONSTRAINED OPERATING ENVIRONMENT - An apparatus includes first and second components, a memory, and an allocator configured to allocate a portion of the memory to the first component, wherein the first component is configured to access the allocated portion of the memory and to send information to the second component to provide the second component with access to the allocated portion of the memory.09-23-2010
20100153663MEMORY ACCESS SYSTEM AND METHOD - A memory access system has a first memory for storing data, a second memory for storing data, a processor for processing data, the processor including a first memory controller for reading out data from or writing data into the first memory, a second memory controller connected to the processor, for reading out data from or writing data into the first memory and the second memory, and a selector for selecting either the first memory controller or the second memory controller, and enabling either the first and the second memory controllers to read out data from or write data into the first memory.06-17-2010
20100228928MEMORY BLOCK SELECTION - The present disclosure includes methods and devices for memory block selection. In one or more embodiments, a memory controller includes control circuitry coupled to one or more memory devices having multiple Groups of planes associated therewith, each Group including at least two planes of physical blocks organized into Super Blocks, with each Super Block including a physical block from each of the at least two planes. The control circuitry is configured to receive a first unassigned logical block address (LBA) associated with a write operation and determine a particular free Super Block within a selected one of the multiple Groups to receive data associated with the write operation.09-09-2010
20100228931MANAGEMENT APPARATUS, SYSTEM, CONTROL METHOD, AND RECORDING MEDIUM - The present invention provides a management apparatus that can control a connection of each image forming apparatus to a network so as to maintain a function (capacity) of a big box formed by a plurality of image forming apparatuses.09-09-2010
20100228927STM WITH MULTIPLE GLOBAL VERSION COUNTERS - A software transactional memory system is provided with multiple global version counters. The system assigns an affinity to one of the global version counters for each thread that executes transactions. Each thread maintains a local copy of the global version counters for use in validating read accesses of transactions. Each thread uses a corresponding affinitized global version counter to store version numbers of write accesses of executed transactions. The system adaptively changes the affinities of threads when data conflict or global version counter conflict is detected between threads.09-09-2010
20100217942USB host controller and controlling method for USB host controller - The present invention aims to provide a USB host controller capable of reducing time for a data transfer between storage devices. A USB host controller according to the present invention includes a buffer memory for USB pipe having a first buffer memory region and a second buffer memory region, and a buffer memory controller configured to control a data transfer between the buffer memory for USB pipe and each of first and second devices. The buffer memory controller stores data from the first device in the first buffer memory region, swaps address information corresponding to the first buffer memory region and address information corresponding to the second buffer memory region, and transfers data stored in the first buffer memory region to the second device, on the basis of the address information corresponding to the first buffer memory region after the swapping.08-26-2010
20100217941IMPROVING THE EFFICIENCY OF FILES SEVER REQUESTS IN A COMPUTING DEVICE - A computing system is operated such that its file server is arranged not to block a client application and distinguishes between synchronous devices, which respond to requests immediately, and asynchronous devices, which do not. For asynchronous devices, it also distinguishes between synchronous operations, which complete immediately, and asynchronous operations, which take time to complete. The device drivers for the computing system only pass file server requests to separate drive threads when they involve asynchronous operations made on asynchronous devices.08-26-2010
20100228929EXPEDITED COMPLETION OF A TRANSACTION IN STM - A software transactional memory system is provided that provides privatization safety. The system identifies situations where the completion of a transaction may be expedited because a privatization artifact will not occur. The system determines whether a privatization artifact may occur using a read and write set intersection test, transactional variables, pessimistic locks, or declared privatizing transactions. If a privatization artifact will not occur for a transaction, then the system may allow the transaction to complete prior to one or more earlier transactions.09-09-2010
20090043974SOLID-STATE IMAGING DEVICE DRIVING APPARATUS AND IMAGING APPARATUS - A solid-state imaging device driving apparatus for generating a driving pulse for a solid-state imaging device includes: a horizontal synchronization-related memory 02-12-2009
20090043972Memory Updating - There is provided a method for updating an internal memory on a semiconductor device from an external memory. The external memory is arranged in a plurality of data portions. The method comprises the steps of writing a first data portion from the external memory to the internal memory, processing the first data portion and, while the first data portion is being processed, once a selected data item is processed, starting to write a second data portion from the external memory to the internal memory. The method may be applied to the processing of software by an embedded processor on a semiconductor device. There is also provided a semiconductor device and a hardware module for the semiconductor device.02-12-2009
20090043973Phase change memory device - A phase change memory device comprises a cell array unit including a phase change resistance cell disposed in a region where a word line and a bit line are crossed, a sense amplifier configured to sense and amplify data of the phase change resistance cell, a write driving unit configured to supply a write voltage corresponding to data to be written in the cell array unit in response to an enabling signal, and a write verifying control unit controlled by an activation control signal and configured to compare data read through the sense amplifier with the data to be written so as to output the enabling signal.02-12-2009
20100250869VIRTUALIZATION SYSTEM USING HARDWARE ASSISTANCE FOR SHADOW PAGE TABLE COHERENCE - One embodiment of the present invention includes a method for maintaining a shadow page table in at least partial correspondence with guest page mappings of a guest computation. The method marking with a traced write indication at least those entries of the shadow page table that map physical memory locations which themselves encode the guest page mappings, the marking identifying, for a hardware facility, a subset of memory access targets for which updates are to be recorded in a guest write buffer accessible to the virtualization system. Responsive to a coherency-inducing operation of the guest computation, the method reads from the guest write buffer and introduces corresponding updates into the shadow page table.09-30-2010
20100250868VIRTUAL NON-UNIFORM MEMORY ARCHITECTURE FOR VIRTUAL MACHINES - Techniques for effectuating a virtual NUMA architecture for virtual machines and adjusting memory in virtual NUMA nodes are described herein.09-30-2010
20100250871REPRODUCING DEVICE AND REPRODUCING METHOD - A reproducing device (09-30-2010
20100250872INTERFACE, MEMORY SYSTEM, AND ACCESS CONTROL METHOD - An interface includes a controller that divides a burst access command into a plurality of command cycles and supplies the plurality of command cycles to a storage device including a plurality of blocks, and a block address converter that outputs an address at a first command cycle of the plurality of command cycles. The address is obtained by shifting at least one bit of an external block address input in response to the burst access command. The address is supplied to the storage device at the first command cycle, and the external block address is supplied to the storage device at a command cycle other than the first command cycle.09-30-2010
20100250870METHOD AND APPARATUS FOR TRACKING ENREGISTERED MEMORY LOCATIONS - One embodiment of the present invention provides a system that tracks enregistered memory locations. During operation, the system receives program object code that enregisters a memory location (e.g., a set of data at a given memory address). Next, the system executes this program object code using a thread. After enregistering the memory location, the system tracks the associated memory address and a thread identifier for the thread in a table that identifies enregistered memory locations. The system checks this table during memory accesses to ensure that other threads attempting to access an enregistered memory location receive a current value for the enregistered memory location.09-30-2010
20100250873MANAGEMENT APPARATUS FOR MANAGING STORAGE APPARATUS - A management includes an acquiring unit for acquiring information of specifying a target virtual storage in a target storage pool and an expansion storage capacity to be acquired from another storage pool other than the target storage pool, and a determining unit for determining the real storage to be used for the expansion storage capacity of the target virtual storage from candidate one of the real storages in the another storage pool, which are under the control of the controller in charge of the real storage that the target virtual storage is defined, on the basis of an occupied storage capacity defined as the virtual storage on the real storage in the another storage pool and a free storage capacity of the real storage in the another storage pool.09-30-2010
20100228930ACCESS CONTROL DEVICE, INFORMATION PROCESSING DEVICE, ACCESS CONTROL PROGRAM AND ACCESS CONTROL METHOD - An access control device which writes data to each of predetermined storage block sets in a storage device of which a storage area has been divided into a plurality of storage blocks. The control device includes a management information storage section and an access processing section. The management information storage section stores, for each of said storage blocks, record enable/disable information indicating whether said storage block is a non-defective block in which the data can be recorded or a defective block in which the data cannot be recorded. If the data is written to each of said storage block sets, the access processing section writes the data only to non-defective blocks in said storage block set based on the record enable/disable information stored in said management information storage section.09-09-2010
20100146225ACYCLIC DATA TRANSFER VIA A FIELD BUS COUPLER - A field bus coupler, a system with a field bus coupler, a transmission method for acyclic data via a field bus coupler and a computer program product are provided. The field bus coupler is configured to transmit acyclic data. The field bus coupler possesses a first and a second network side, each network side possessing an interface for connecting a field bus. On the first network side an output module is provided for receiving an output data record of a first field bus. The data record is mirrored from the first to the second network side and buffered in a memory. The mirrored data record is thus provided via an input module on the second network side to a second field bus as an input data record.06-10-2010
20100146221Method For Protecting Memory Data - A method for protecting memory data is provided, by extracting bad block addresses stored in the bad block information obtained during the memory scanning testing as memory label, and using an algorithm to compute an identification based on the memory label so that the memory will check the identification and whether the blocks pointed by memory label being bad blocks when an external device request data reading so as to prevent the unauthorized data from being read and achieve the object of protecting memory data.06-10-2010
20100153660Ruggedized memory device - A non-volatile storage device with built-in ruggedized features is disclosed. The device processes a write command to a logical block address by writing the data from the command to a non-volatile memory within the non-volatile storage device and conditionally associating the data received from the command with its corresponding logical block address. Two or more received write commands define a set of commands associated with an atomic transaction. When an end of set command is received, the device unconditionally associates the received data with each write command with its corresponding logical block address. If a power loss interrupts the reception of a set of commands, the non-volatile storage device may recover the last consistent data state before the atomic transaction was started. A write command transaction identifier allows the device to associate the command with a thread of commands that define an atomic transaction in a multithreaded system.06-17-2010
20110113204MEMORY CONTROLLER WITH EXTERNAL REFRESH MECHANISM - The invention relates to a memory controller for use in a System-on-Chip, wherein the System-on-Chip comprises a plurality of agents and an off-chip volatile memory. The memory controller comprises a first port (CBP) for receiving low-priority requests (CBR) for access to the volatile memory from a first-subset of the plurality of agents and a second port (LLP) for receiving high-priority requests (LLR) for access to the volatile memory from a second-subset of the plurality of agents, wherein the memory controller is configured for arbitrating between the high-priority requests (LLR) and the low-priority requests (CBR), wherein the memory controller is configured for receiving refresh requests (RFR) for the volatile memory via the first port (CBP), wherein the refresh requests (RFR) are time-multiplexed with the low-priority requests (CBR), wherein the memory controller is configured for treating the low-priority requests (CBR) and the refresh requests (RFR) the same. The effect is that the arbitration between the different requests is rendered less complex. In embodiments of the memory controller there is also an average latency reduction for the high-priority requests. The invention further relates to a System-on-Chip comprising the memory controller, to a method of a refresh request generator for use in such System-on-Chip. The invention also relates to a method of controlling access of a System-on-Chip to a volatile memory, wherein the System-on-Chip comprises a plurality of agents which need access to the volatile memory, and to a computer program product comprising instructions for causing a processor to perform such method.05-12-2011
20100211751Program Execution Apparatus, Program Execution Method, and Program - According to one embodiment, a program execution apparatus includes a first memory configured to store a first program, a second memory configured to store a partial program loaded from the first memory or a second program loaded from one other memory, and a controller configured to perform first correspondence to cause a first storage region of the first program in the first memory to correspond to a first virtual region of a virtual memory, execute the first program stored in the first memory on the basis of the first correspondence according to a request for the execution of the first program.08-19-2010
20100211750Data Storage Control Apparatus and Data Storage Control Method - According to one embodiment, a data storage control method, which is applied to a virtual memory that controls access to the data stored in each of the physical memory regions by the corresponding one of the virtual addresses on the basis of an address management table that manages the correspondence relationship between a plurality of virtual addresses corresponding to a plurality of virtual memory regions and a plurality of physical addresses corresponding to a plurality of physical memory regions of a first memory, includes writing the data stored in a specific number of nonconsecutive physical memory regions made to correspond to a specific number of virtual memory regions on the basis of the address management table to a specific number of consecutive physical memory regions.08-19-2010
20100211749METHOD OF STORING DATA, METHOD OF LOADING DATA AND SIGNAL PROCESSOR - A method for storing a vector of process data elements (D08-19-2010
20090006778METHODS AND APPARATUS FOR H-ARQ PROCESS MEMORY MANAGEMENT - Methods and apparatus are presented for H-ARQ process dynamic memory management. A method for dynamically managing memory for storing data associated with H-ARQ processes is presented, which includes receiving a packet associated with a H-ARQ process, determining if a free memory location is available in a H-ARQ buffer, assigning the packet to the free memory location, determining if the packet was successfully decoded, and retaining the packet in the assigned memory location for combination with a subsequent packet retransmission if the packet was not successfully decoded. Also presented are apparatus having logic configured to perform the presented methods.01-01-2009
20100205385METHOD, SYSTEM, AND APPARATUS FOR SUPPORTING LIMITED ADDRESS MODE MEMORY ACCESS - Supporting limited address mode memory access involves receiving a write request from the processor targeted to a first predetermined address. A data portion of the write request includes a target address of the system memory. In response to determining the write request is targeted to the first predetermined address, the target address is sent via a system interface to be stored in a configuration register of the processor director. A memory access request targeted to a second predetermined address is received from the processor. In response to determining the memory access request is targeted to the second predetermined address, the target address is retrieved from the configuration register of the processor director. The memory access is serviced using the target address retrieved from the configuration register.08-12-2010
20100138617METHOD FOR INITIALIZING A MEMORY - A method for initializing a control device of a memory, the control device executing commands for accessing the memory transmitted to the memory by a control signal, the method comprising steps of detecting the switching on of the memory and of at least partially initializing the control device following the switching on of the memory. According to one embodiment of the present invention, the method comprises steps of detecting a specific event in the control signal, and of at least partially initializing the control device following the detection of the specific event.06-03-2010
20120144131SEMICONDUCTOR MEMORY ASYNCHRONOUS PIPELINE - An asynchronously pipelined SDRAM has separate pipeline stages that are controlled by asynchronous signals. Rather than using a clock signal to synchronize data at each stage, an asynchronous signal is used to latch data at every stage. The asynchronous control signals are generated within the chip and are optimized to the different latency stages. Longer latency stages require larger delays elements, while shorter latency states require shorter delay elements. The data is synchronized to the clock at the end of the read data path before being read out of the chip. Because the data has been latched at each pipeline stage, it suffers from less skew than would be seen in a conventional wave pipeline architecture. Furthermore, since the stages are independent of the system clock, the read data path can be run at any CAS latency as long as the re-synchronizing output is built to support it.06-07-2012
20120144130Optimizing Output Vector Data Generation Using A Formatted Matrix Data Structure - A computer system retrieves a packet that includes non-zero elements that correspond to sparse-matrix rows. Within the packet, the non-zero elements are stored in predefined fields that each correspond to one of the sparse-matrix rows. The computer system computes output values to correspond with each of the sparse-matrix rows using the non-zero elements and corresponding input values. In turn, the computer system stores the computed output values in consecutive locations within an output buffer and processes the output values accordingly.06-07-2012
20130219131LOW ACCESS TIME INDIRECT MEMORY ACCESSES - An apparatus having a memory and a controller is disclosed. The controller may be configured to (i) receive a read request from a processor, the read request comprising a first value and a second value, (ii) where the read request is an indirect memory access, (a) generate a first address in response to the first value, (b) read data stored in the memory at the first address and (c) generate a second address in response to the second value and the data, (iii) where the read request is a direct memory access, generate the second address in response to the second value and (iv) read a requested data stored in the memory at the second address.08-22-2013
20130219132STORAGE MEDIUM STORING INFORMATION PROCESSING PROGRAM, INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, AND INFORMATION PROCESSING SYSTEM - An information processing apparatus 08-22-2013
20100199052INFORMATION PROCESSING APPARATUS, EXECUTION ENVIRONMENT TRANSFERRING METHOD AND PROGRAM THEREOF - Provided is an information processing device which enables transfer of an execution environment in a short time period without degrading basic performance of an execution environment and without requiring a large amount of memory.08-05-2010
20100082912SYSTEMS AND METHODS FOR RESOURCE ACCESS - Systems and methods are provided to manage access to computing resources. More specifically, certain embodiments are described in which a resource or resource consumer can engage access controls or request that access controls be engaged if the age of a request exceeds one or more thresholds. For example, a requester may, after the age of a request meets or exceeds a threshold, indicate to a destination that a control should be engaged.04-01-2010
20090327618Method for Self Optimizing Value Based Data Allocation Across A Multi-Tier Storage System - A method, apparatus, and article of manufacture are provided to support dynamic assignment of data from a continuous stream of data to one or more storage devices in a storage network. The storage network is configured with one or more tiers in a hierarchy, with at least one storage device in each tier. Similarly, the storage network is in communication with both a storage manager and a data manager. The storage manager sorts the storage devices, maintains a demand function of each device, and calculates a burn rate for each storage device. The data manager is in communication with the storage manager and assigns data from the received stream of data to at least one of the storage devices.12-31-2009
20090327621VIRTUAL MEMORY COMPACTION AND COMPRESSION USING COLLABORATION BETWEEN A VIRTUAL MEMORY MANAGER AND A MEMORY MANAGER - Enhanced performance and functionality in virtual memory is possible when a virtual memory manager and a memory manager are configured to collaborate.12-31-2009
20090327619Access Speculation Predictor with Predictions Based on Memory Region Prior Requestor Tag Information - An access speculation predictor may predict whether to perform speculative retrieval of data for a data request from a main memory based on whether or not a current requestor tag matches a previous requestor tag. In particular, a first address and a first requester tag may be extracted from a first data request and a finite state machine (FSM) of a memory controller may be selected whose memory region includes the first address. A second requester tag, that identifies a previous requester that attempted to access the memory region association with the selected FSM, may be retrieved from a register associated with the selected FSM and compared to the first requester tag. Speculatively retrieving the data for the first data request from a main memory may be controlled based on results of the comparison of the first requester tag to the second requester tag.12-31-2009
20090327623COMMAND REORDERABLE MEMORY CONTROLLER - A memory controller includes a plurality of bus interfaces and a memory controller core configured to control a command and data issued from the plurality of bus interfaces and to write or read the command and the data into and from the memory. The memory controller core includes a command control unit configured to receive a plurality of commands issued from the plurality of bus interfaces and to reorder and store the plurality of commands and a write data control unit configured to receive a plurality of pieces of write data issued from the plurality of bus interfaces in a sequence that the command control unit receives the write commands and to output the write data based on the reordered result of the command control unit. Accordingly, latency can be minimized between the memory controller and the memory and downsizing of a circuit of the memory controller can be achieved.12-31-2009
20090327622Method and Apparatus for Computer Memory Traversal - A method, apparatus and computer program product is provided for traversing computer memory. In one example embodiment, a method comprises determining whether a next cluster associated with a file is located in contiguous memory and obtaining a location of a next cluster from a file allocation table when the next cluster associated with the file is not located in contiguous memory. For example, the determining step may comprise reading from a cluster descriptor that is associated with the file wherein the cluster descriptor comprises an indication that a contiguous cluster in a data region is associated with the file. In one embodiment, the file allocation table is located in a first memory and the cluster descriptor is located in a second memory.12-31-2009
20090172308Storage controller for flash memory including a crossbar switch connecting a plurality of processors with a plurality of internal memories - A controller designed for use with a flash memory storage module, including a crossbar switch designed to connect a plurality of internal processors with various internal resources, including a plurality of internal memories. The memories contain work lists for the processors. In one embodiment, the processors communicate by using the crossbar switch to place tasks on the work lists of other processors.07-02-2009
20090319730MEMORY SYSTEM, ACCESS CONTROL METHOD THEREFOR, AND COMPUTER PROGRAM - A memory system includes: a memory that has plural banks; a memory controller that includes a request queue and a bank monitor and controls access to the memory; a master group including plural masters that can request access to the memory; and a system bus which is connected between the memory controller and the master group and in which an arbiter is arranged, wherein the request queue has a scheduling function for receiving access requests issued from the master group through the system bus and appropriately rearranging the received access requests and provides the arbiter with queue information, the bank monitor monitors information concerning respective banks of the memory and provides the arbiter with the bank information, and the arbiter arbitrates requests issued in parallel from the masters of the master group on the basis of the queue information and the bank information provided thereto and transmits the information to the memory controller as access control information.12-24-2009
20090319729Method of accessing stored information in multi-framed data transmissions. - The present invention discloses a method of accessing stored information in multi-framed data transmissions, comprising at least one control interface and at least one elastic store, wherein the control interface accesses the elastic store through a mailbox communications method. The control interface accesses the elastic store via the mailbox communications method, which comprises: (a) setting a address for a data location within said elastic store; (b) setting a request to read from, or write to, said data location within said elastic store; (c) issuing a “GO_” signal to retrieve data information from said data location within said elastic store, by writing said “GO_” signal to said microprocessor, which causes a circuit to read from said requested data location within said elastic store; (d) waiting for a possible, but not to be expected, de-assertion of a busy signal to be issued from said data location within said elastic store, and then; and then (e) reading back the value of said data information to said control interface. Where a busy signal occurs, the microprocessor must wait and issue a subsequent “GO_” signal to retrieve the data information from the data location; where a busy signal does not occur the “GO_” signal causes the circuit to read from the requested data location and send the data information back to the microprocessor, where the data information is stored in a user-accessible register.12-24-2009
20090006782APPARATUS AND METHOD FOR ACCESSING A MEMORY DEVICE - An apparatus and a corresponding method for coupling a memory device being addressable by means of an address space to a processing unit, the apparatus consisting: 01-01-2009
20100223433Configurable object graph traversal with redirection for garbage collection - A configurable object graph traversal component with redirection capability for use in garbage collectors and other related applications. The component may be implemented in either hardware or in software, and provides an interface that allows reuse of the same component for the various traversal tasks performed during garbage collection. The interface supports redirecting traversal to new copies of moved objects, updating referring cells, performing cycle detection efficiently, and in some embodiments also supports selecting the direction of traversal, handling exits from the traversed memory region specially, and providing access to the old address of copied cells.09-02-2010
20090150623SEMICONDUCTOR DEVICE AND TEST MODE CONTROL CIRCUIT - The present invention provides a semiconductor device which sufficiently ensures the security and prevents the decline of the yield even when the failure or the like causes a bit change in the data of the test mode control flag stored in the nonvolatile memory. The semiconductor device of the present invention includes: a nonvolatile memory which stores a test mode control code in a predetermined address; a generation unit which generates a fixed value indicating permission for or prohibition of a test mode; and a Hamming distance determination circuit which controls switching to the test mode depending on whether or not a Hamming distance between the control code and the fixed value is equal to or less than a predetermined number.06-11-2009
20090113147ACCESS CONTROL APPARATUS AND ACCESS CONTROL METHOD - An access control apparatus includes a memory and a command executor executing an access process on a command with the command completion time limit. An address of an inaccessible recording area is stored in the memory. Data attempted to be written on the inaccessible recording area is obtained. The data is stored in association with the address in the memory. An automated alternate processor executes the automated alternate process of the inaccessible recording area in a predefined period of time after the process executed by the command executor is completed. A memory updater deletes the address of the inaccessible recording area whose automated alternate process has succeeded and the data attempted to be written in the recording area at the address.04-30-2009
20090113146SECURE PIPELINE MANAGER - A method for data storage includes supplying data to and from a host to a storage memory via a secure data path. A first CPU is employed to control operation of the storage memory, and a second CPU is employed to control operation of the secure data path.04-30-2009
20090113145DATA TRANSFER - An apparatus, for connection to a storage device, comprising: a module for communication with a software application and operable to receive instructions to copy data to the storage device; a chunking and identifier generation module operable to receive the data, to process the data into one or more chunks, to generate a first chunk identifier, representative of the identity of a first of the or each chunk of data and, upon processing of the data, to initiate the issuance of a confirmation signal to the software application indicating that the data has been copied to the storage device; and an interface for communication with the storage device, wherein the interface is operable to send the first chunk identifier to the storage device, and to send the first chunk of data to the storage device upon receipt of a transfer instruction from the storage device.04-30-2009
20090113143SYSTEMS AND METHODS FOR MANAGING LOCAL AND REMOTE MEMORY ACCESS - A memory management unit (MMU) in an information handling system includes a translation module operable to receive a memory request identifying a memory address, and determine whether the identified memory address corresponds to a local memory resource associated with the information handling system or a remote memory resource coupled to the information handling system via a network. The MMU also includes at least one local memory access module operable to facilitate access to local memory resources if the memory address corresponds to a local memory resource, and at least one remote memory access module operable to facilitate access to remote memory resources via the network if the memory address corresponds to a remote memory resource.04-30-2009
20100223434Dummy Write Operations - A dummy write operation is disclosed that mimics an actual write operation to a memory array. In some implementations, a dummy write operation mimics an actual write operation by starting a charge pump, selecting a correct data line in the memory array, and by following the sequencing of an actual write operation. By mimicking an actual write operation, an attacker cannot use power analysis to distinguish between dummy and actual write operations. For example, PIN comparison operations would present the same or substantially the same power trace for both positive and negative comparisons, making it difficult for an attacker to determine if a retry count was written to NVM.09-02-2010
20090106511Methods and systems for fragments retrieval from a type based push to storage system - Methods and systems for fragments retrieval from a type based push to storage system. One method includes the steps of receiving fragment-to-type association information and type-to-physical-address association information of a content comprising a plurality of content fragments distributed among a plurality of storage-and-computing elements; and providing at least one storage-and-computing element physical address for each of the content fragments to be retrieved.04-23-2009
20090106507Memory System and Method for Using a Memory System with Virtual Address Translation Capabilities - A memory system comprises a first memory having associated therewith a first local memory access controller configured to access the first local memory using physical memory addresses and a second memory having associated therewith a second local memory access controller configured to access the second local memory using physical memory addresses. A global controller coupled to the first and second local controllers is configured to communicate virtual memory addresses to the first and second local memory controllers.04-23-2009
20090049255System And Method To Reduce Disk Access Time During Predictable Loading Sequences - A method, software, and system for loading data from disk include comparing a current sequence of disk I/O requests to data indicative of a previous disk I/O request sequence. Responsive to detecting a match between the current disk I/O sequence and the previous disk I/O sequence, a copy of data blocks accessed during the I/O sequence is stored in a contiguous portion of the disk. Responsive to a subsequent request to data in the disk sequence, the request is mapped to and serviced from the sequential portion of the disk. In one embodiment, the disk sequence represents a boot sequence of the system.02-19-2009
20090106510Controlling Replication of Data Among Storage Devices - A control apparatus connected to different types of storage devices include a performance-information storing section that stores performance information on the storage devices; a list storing section that stores a list of data on the storage devices; a monitoring section that monitors the load statuses of the storage devices and the control apparatus; a detecting section; an estimating section; and a determining section.04-23-2009
20090106509MEMORY SYSTEM AND METHOD OF DRIVING THE SAME - Provided are a memory system and a method of driving the same. The method includes setting microcodes in a top control sequencer and multiple channel control sequencers, and executing the microcode set in the top control sequencer. The method may further include checking execution results of the microcode.04-23-2009
20090106508DIGITAL MEMORY WITH CONTROLLABLE INPUT/OUTPUT TERMINALS - Methods and apparatus for controlling an input/output (I/O) driver of an I/O terminal based at least in part on the values being provided to the I/O terminal is disclosed. In various embodiments, a detector is employed. The detector shuts off power to the I/O driver if the digital value being presented is the same as a previously presented digital value.04-23-2009
20090106505DIGITAL MEMORY WITH FINE GRAIN WRITE OPERATION - Methods, systems, and apparatus for operating digital memory including determining, by a controller, a bit to be written to the digital memory and writing, by the controller, the bit. The bit may be part of a data word comprising a plurality of bits and both the determining and the writing may be performed at a granularity level finer than a data word. In embodiments, the bit to be written may be determined by error correction.04-23-2009
20130132689MEMORY REGISTER ENCODING APPARATUS AND METHODS - Apparatus, systems, and methods are disclosed that operate to encode register bits to generate encoded bits such that, for pairs of addresses, an encoded it to be coupled to a first address in a memory device may be exchanged with an encoded bit to be coupled to a second address in the memory device. Apparatus, systems, and methods are disclosed that operate to invert encoded bits in logic circuits in the memory device if original bits were inverted. Additional apparatus, systems, and methods are disclosed.05-23-2013
20110107037Information Processing Apparatus and Memory Control Method - According to one embodiment, an information processing apparatus includes memory modules, a measuring module, a determination module, and a controller. The measuring module initializes the memory modules when the apparatus has been booted and an operating system of the information processing apparatus has not yet been started, measures a temperature of the memory modules at a time of the initialization, and measures a maximum temperature of each of the memory modules when the operating system is running. The determination module determines a first memory module, which has the least difference between the temperature at the time of the initialization and the maximum temperature at the time when the operating system is running, and a second memory module which has the lowest temperature at the time of the initialization. The controller maps memory addresses allocated to the first memory module in the second memory module, based on the temperatures.05-05-2011
20110107036DISTRIBUTED STORAGE REVISION ROLLBACKS - Multiple revisions of an encoded data slice can be stored in a distributed storage unit. Before writing a new revision of an encoded data slice to storage, the distributed storage unit can invoke a write lock for all encoded data slices having the same slice name as the slice being currently written. The slice being currently written can be stored in temporary storage, and a rollback timer started. If a commit command is received before expiration of the rollback timer, the currently written slice can be permanently stored and made accessible for read requests. If the rollback timer expires prior to the storage unit receiving a commit command, however, a previously stored revision will be used.05-05-2011
20100306482NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile memory having a non-power of two memory capacity is disclosed. The nonvolatile memory device includes at least one plane. The plane includes a plurality of blocks with each of the blocks divided into a number of pages and each of the blocks defined along a first dimension by a first number of memory cells for storing data, and along a second dimension of by a second number of memory cells for storing data. The nonvolatile memory has a non-power of two capacity proportionally related to a total number of memory cells in said plane. The nonvolatile memory also includes a plurality of row decoders. An at least substantially one-to-one relationship exists, in the memory device, for number of row decoders to number of pages. Each of the row decoders is configured to facilitate a read operation on an associated page of the memory device.12-02-2010
20100306481DECENTRALIZED PROCESSING NETWORK - A free-space, decentralized, distributed computing network may comprise at least one free-space dynamic memory unit, at least one free-space processing unit, at least one free-space static memory unit, and at least one free-space communications link. The free-space dynamic memory unit may store data. The free-space processing unit may process the data, stored by the free-space dynamic memory unit, into information. The free-space static memory unit may provide operational instructions to the free-space dynamic memory unit and to the free-space processing unit. The free-space communications link may connect in the free-space the free-space dynamic memory unit, the free-space processing unit, and the free-space static memory unit. The free-space dynamic memory unit, the free-space processing unit, and the free-space static memory unit may each comprise at least one tracking device, and a transducer, transmitter, and/or receiver.12-02-2010
20100318751Multiple error management in a multiprocessor computer system - An error message handling buffer comprises a first buffer and a second buffer. A first index is associated with the first buffer and a second index is associated with the second buffer. A buffer controller is operable to write and read messages in the buffer, such that messages are written to the buffer of the first and second buffers that has a buffer index value lesser than the buffer size, and read from the other of the first and second buffers, the other buffer having an index value greater than or equal to the buffer size.12-16-2010
20100312974INFORMATION PROCESSING APPARATUS, DATA ACCESS SYSTEM, AND CONTROL METHOD FOR THE SAME - A data storage apparatus acquires rule information that is used by the external device when performing data access and that defines a relation between the type of access operation and a data read condition, and status information including information for specifying data currently displayed on the external device, and indicates a current display status of the external device. Then, the data storage apparatus determines data to be pre-read from a storage medium and stored in a temporary data storage unit based on the rule information and the status information, and reads the determined data from the storage medium, and stores the read data in a temporary data storage unit. In the case where a data access request is received from the external device, if the requested data is stored in the temporary data storage unit, the requested data is read from the temporary data storage unit, and is output.12-09-2010
20100312973METHODS FOR CONTROLLING HOST MEMORY ACCESS WITH MEMORY DEVICES AND SYSTEMS - The present disclosure includes methods for controlling host memory access with a memory device, systems, host controllers and memory devices. One embodiment for controlling host memory access with a memory device includes receiving at least one command from a host and controlling execution of the at least one command with the memory device.12-09-2010
20130138897METHOD AND APPARATUS FOR DYNAMICALLY CONTROLLING DEPTH AND POWER CONSUMPTION OF FIFO MEMORY - A method and apparatus are described for controlling depth and power consumption of a first-in first-out (FIFO) memory including a data storage, a FIFO top register, a FIFO bottom register and control logic. The data storage may be segmented into a plurality of data storage segments. The FIFO top register may be configured to generate a first value indicating where a first entry in the data storage is stored. The FIFO bottom register may be configured to generate a second value indicating where a last entry in the data storage is stored. The control logic may be configured to determine which of the data storage segments to activate or deactivate based at least in part on the first and second values, and to monitor an available capacity and a write/read rate of the FIFO memory as data is read from and written to the activated data storage segments.05-30-2013
20130138899MANAGEMENT METHOD AND MANAGEMENT SYSTEM FOR COMPUTER SYSTEM - The present invention provides a technique to efficiently rearrange data in actual regions. A management system acquires load lumped region variation information (access distribution variation amount) indicative of a variation in the position of a virtual region in a virtual volume in a storage subsystem which region corresponds to a hot spot. Then, based on the load lumped region variation information, the management system determines a load position unvaried hour(s) indicative of a hour(s) in which the position of the virtual region corresponding to the hot spot is almost or perfectly unvaried (the hour(s) in which the position of the hot spot is stable). The management system then displays the load position unvaried hour(s) on a display device.05-30-2013
20100325373Duplexing Apparatus and Duplexing Control Method - According to one embodiment, a duplexing apparatus includes a controller configured to write data in first storage module when the data is transferred from a host computer, to read the data from the first storage module when the notice has been transmitted to the host computer, the notice showing that the data is written in the first storage module and a second storage module, and to write the data read from the first storage module in the second storage module, and a transmission module configured to transmit the notice to the host computer when the data is written in the first storage module.12-23-2010
20100332773NONVOLATILE MEMORY DEVICE AND READ METHOD THEREOF - A nonvolatile memory device comprises includes a program unit configured to generate program data, information about the number of program data, and digital sum value information (hereinafter referred to as ‘DSVi’) of the program data, a memory unit configured to store or read the program data, the information about the number of program data, and the DSVi the program data, and a data read control circuit configured to read program data programmed into the memory unit, generate digital sum value information (hereinafter referred to as ‘DSVo’) of the read program data, and generate a read voltage control signal using the DSVi of the program data, the DSVo of the read program data, and the information about the number of program data.12-30-2010
20110010510Method for updating a program section - A method for updating a program section is disclosed; the method is used for an electronic system. The electronic system comprises a control unit and a storage device; the control unit is electrically connected with the storage device; the storage device comprises a program section; the program section comprises an application section and a boot section; the application section comprises a first bootloader and application information, wherein the first bootloader comprises a first driver. The method comprises the following steps of: connecting a data source device, wherein the data source device comprises update data; determining whether the first driver is able to drive the data source device or not; and if the first driver is able to drive the data source device, the first driver performs an updating procedure according to the update data.01-13-2011
20110016279SIMULTANEOUS READ AND WRITE DATA TRANSFER - A controller for an arrangement of memory devices may issue a write command without waiting for the receipt of a previously issued read command. An addressed memory device may read data out onto the data bus according to a read command while, simultaneously, writing data according to a write command received subsequent to the read command.01-20-2011
20120246416COMMUNICATION DEVICE AND CONTROL METHOD THEREOF - According to one embodiment, a communication device includes a first interface, a wireless communication unit, and a memory unit. The memory unit includes a first region used for first access from the first interface and a second region used for second access from the wireless communication unit. Writing to the second region by the first access and writing to the first region by the second access are inhibited.09-27-2012
20110029742COMPUTING SYSTEM UTILIZING DISPERSED STORAGE - A computing system comprises at least a processing module, a main memory, a memory controller, and a plurality of memory components. A method begins by the memory controller receiving a memory access request regarding a data segment. The method continues with the memory controller interpreting the memory access request to determine whether an error encoding dispersal function of the data segment is applicable. The method continues with the memory controller identifying at least a threshold number of memories based on the memory access request, wherein the threshold number of memories includes at least one of the main memory and/or one or more of the plurality of memory components, when the error encoding dispersal function is applicable. The method continues with the memory controller addressing the at least a threshold number of memories to facilitate the memory access request.02-03-2011
20110029741DATA MANAGEMENT METHOD AND MEMORY DEIVCE - The invention provides a data management method for a memory device. In one embodiment, the memory device comprises a plurality of memories for data storage. First, write data and a write logical address is received from a host. The write logical address is then converted to a write physical address. A target memory corresponding to the write physical address is then determined. Whether the target memory is in a busy state is then checked. When the target memory is in the busy state, the write data is written to a buffer area of a substitute memory of the target memory.02-03-2011
20110029740COMMUNICATING METHOD APPLIED FOR STORAGE DEVICE - A communicating method between a storage device and an application program includes the following steps: the application program dynamically selects a block address in the storage device as a predetermined block address; and the application program performs a command write-in or state read-out process via the predetermined block address to communicate with the storage device.02-03-2011
20110029746RECONFIGURABLE MEMORY MODULE AND METHOD - A computer system includes a controller coupled to a plurality of memory modules each of which includes a memory hub and a plurality of memory devices divided into a plurality of ranks. The memory hub is operable to configure the memory module to simultaneously address any number of ranks to operate in a high bandwidth mode, a high memory depth mode, or any combination of such modes.02-03-2011
20110029739Storage system and control method for the same, and program - The present invention provides a criterion for determining whether or not to apply de-duplication processing. That is, by setting a reduction effect threshold to control switching the de-duplication between ON and OFF, the present invention allows operation such that the de-duplication is applied for a volume for which a high capacity-reduction effect is provided by the de-duplication processing, and in contrast, the de-duplication is not applied to maintain performance for a volume for which a low capacity-reduction effect is provided by the de-duplication processing.02-03-2011
20110029743COMPUTING CORE APPLICATION ACCESS UTILIZING DISPERSED STORAGE - A computing core application access method begins by a processing module detecting selection of an application. The method continues with at least one of a memory controller and the processing module addressing a distributed application memory to retrieve a plurality of error coded program data slices and a plurality of error coded configuration data slices. The method continues with the at least one of a memory controller and the processing module reconstructing a data segment of a program from the plurality of error coded program data slices using an error coding dispersal function. The method continues with the at least one of a memory controller and the processing module reconstructing a data segment of a configuration information from the plurality of error coded configuration data slices using a second error coding dispersal function. The method continues with the at least one of a memory controller and the processing module storing the data segment of the program and the data segment of the configuration information in a main memory of the computing core.02-03-2011
20110035557FRAGMENTATION REDUCTION USING VIRTUAL SECTORS FOR STATIC DATA - A system for facilitating enhanced storage efficiency. Operational scenarios that include, for example, many distinct files that are smaller than a read/write block size in an apparatus may result in large portions of unused memory. Sectors that would have normally fallen within a block occupied by a small file may be replaced by “virtual” sectors. The virtual sectors may be mapped in an intermediate control level so that small files may still be read using a standard block size without wasting actual physical memory space. The physical sectors that were previously virtualized may then, for example, be used to “extend” the available memory.02-10-2011
20110035558METHOD AND SYSTEM TO LOCATE A STORAGE DEVICE - A method of locating a storage device of a number of storage devices is provided. A request for a data item is received. The request includes a globally unique identifier (GUID) that is associated with a user. A start number is generated based on the GUID, and the storage device that stores the data item is located based on the start number. The data item is then read from the located storage device. Other techniques for locating a storage device are also described.02-10-2011
20110035559MEMORY CONTROLLER, MEMORY SYSTEM, SEMICONDUCTOR INTEGRATED CIRCUIT, AND MEMORY CONTROL METHOD - A memory controller (02-10-2011
20110213937Methods and Apparatus for Address Translation Functions - Techniques are described for efficient reordering of data and performing data exchanges within a register tile or memory, or in general, any device storing data that is accessible through a set of addressable locations. In one technique, an address translator is placed in the path of all or a selected set of address busses to a storage device to provide a programmable and selectable means of translating the storage device addresses. An effect of this translation is that the data stored in one pattern may be accessed and stored in another pattern or accessed, processed and stored in another pattern. The address translation operation may be carried out in a single cycle, does not involve the physical movement of data in swap operations, allows data to effectively be ordered more efficiently for algorithmic processing and therefore saves power. Address translation functions are shown to be useful for vector operations and a new type of storage unit using built in address translation functions is presented.09-01-2011
20110145522MEMORY COMMAND DELAY BALANCING IN A DAISY-CHAINED MEMORY TOPOLOGY - A methodology for a daisy-chained memory topology wherein, in addition to the prediction of the timing of receipt of a response from a memory module (DIMM), the memory controller can effectively predict when a command sent by it will be executed by the addressee DIMM. By programming DIMM-specific command delay in the DIMM's command delay unit, the command delay balancing methodology according to the present disclosure “normalizes” or “synchronizes” the execution of the command signal across all DIMMs in the memory channel. With such ability to predict command execution timing, the memory controller can efficiently control power profile of all the DRAM devices (or memory modules) on a daisy-chained memory channel. A separate DIMM-specific response delay unit in the DIMM may also be programmed to provide DIMM-specific delay compensation in the response path, further allowing the memory controller to accurately ascertain the timing of receipt of a response thereat, and, hence, to better manage further processing of the response.06-16-2011
20110145521DATA PROCESSING SEMICONDUCTOR DEVICE - To improve the reliability of controlling overwriting of a nonvolatile memory in a data processing semiconductor device.06-16-2011
20110145520AUDIO SIGNAL PROCESSING APPARATUS AND METHOD, AND COMMUNICATION TERMINAL APPARATUS - A signal processing technology achieved in a signal processing module, which is physically separate from a control module for controlling overall operations of a signal processing apparatus, is provided. Input of new data to a system memory is recognized. Upon the recognition of the input of the new data, the new data is read from the system memory. The new data read from the system memory is written to a local memory. Data sharing between software and hardware is effectively achieved in a system for performing a wideband codec processing using a dedicated hardware.06-16-2011
20110145519DATA WRITING APPARATUS AND DATA WRITING METHOD - According to one embodiment, a data writing apparatus includes a memory and write module. The memory includes a storage area including a physical block having a data area and redundancy area. The write module is configured to write a data block obtained by dividing data, in the data area of the physical block. In addition, the write module is configured to write a first data block in a first data area which is the data area of a first physical block, write a second data block as a data block to be read before the first data block when reading the data, in a second data area which is the data area of a second physical block, and write information indicating the first physical block in the redundancy area of the second physical block.06-16-2011
20110145517DYNAMIC REUSE AND RECONFIGURATION OF LOGICAL DATA OBJECTS IN A VIRTUAL TAPE SYSTEM - An embodiment of the invention comprises a virtual tape system supporting at least one Write Once Read Many (WORM) logical tape and at least one read-write logical tape, comprising a processor configured to a first task and/or a second task. The first task initializes a new logical data object from a single pool of at least two logical data objects, with the new logical data object bound with a member of a media type group consisting of a WORM data object or a read-write data object. The second task reuses one of the logical data objects without manual ejection and reinsertion. The reuse may include the processor configured to cycle the logical data object through a scratch pool as a selected scratch logical data object and mount the selected scratch logical data object with a write from beginning of tape command to bind at least one data attribute to the WORM data object.06-16-2011
20080235465Systems for conversion of update blocks based on association with host file management data structures - A non-volatile memory storage system is provided. The non-volatile memory storage system comprises a non-volatile memory cell array and a processor in communication with the non-volatile memory cell array. Here, the processor is configured to receive a write command to write data, where the write command comprises a logical address associated with the data. The processor is further configured to allocate a chaotic update block if the logical address is associated with a host file management data structure. After the allocation, the data are written to the chaotic update block.09-25-2008
20100169585Dynamic updating of thresholds in accordance with operating conditons - In some embodiments, a memory control device includes a sensor positioned remotely from a memory device, a register to store an offset value, the offset value corresponding to a difference between a temperature reading of the sensor and an estimated actual temperature of the memory device, and a controller to control an operation of the memory device, wherein the controller is configured to read the offset value from the register and control the operation of the memory device in accordance with the offset value. The controller may be configured to dynamically update the offset value during an operation of the memory device. Other embodiments are disclosed and claimed.07-01-2010
20110078391INFORMATION RECORDING APPARATUS, INFORMATION RECORDING METHOD, AND COMPUTER-READABLE MEDIUM - A recording area of an information recording medium is divided into a plurality of management areas. In the case where one of the management areas is selected and first file data are requested to be written, the scalability of file data that are lastly written in the selected management area is determined. If the scalability is high, the file data are written in the next management area, and, if the scalability is low, the first file data are written in succession to the file data.03-31-2011
20100235591COMPUTER SYSTEM AND SNAPSHOT CREATION METHOD THEREOF, DELAYING SNAPSHOT CREATION UNTIL PENDING TRANSFER BETWEEN VOLUMES IS COMPLETE - A storage system and snapshot method wherein after a first processor transfers data stored in a first data area to a second storage system, the first processor transfers a first marker stored in a first marker area to a second storage system so that the first marker is stored in a second marker area of a second volume, wherein a second processor checks whether the first marker stored in the second storage area of the second volume corresponds to a second marker designated, and wherein, if the first marker stored in the second storage are of the second volume is a second marker designated, the second processor creates a snapshot of the data that is stored in the second data area, in a third storage volume.09-16-2010
20110093669Memory System and Method for Two Step Memory Write Operations - A method of operating a memory component that includes a memory core includes receiving, from external control lines, a write command that specifies a write operation. The write command is stored for a first time period after receiving the write command. After the first time period, the write operation is initiated in response to the write command. During the write operation, unmasked portions of received data are written to the memory core, where the unmasked portions of the data are bits of the data that are identified by received mask information as not being masked.04-21-2011
20110082985DATA MANAGEMENT IN A DATA STORAGE SYSTEM - The present disclosure provides a method in a data storage system. The method includes defining a plurality of jobs for a command received from a host. Each of the plurality of jobs is associated with one or more of a plurality of data storage resources of the data storage system. The plurality of jobs have a defined order that is a function of addresses of data in the plurality of data storage resources. The method also includes issuing the plurality of jobs to the associated data storage resources and receiving information from the data storage resources for the plurality of jobs. The information is received by a controller of the data storage system for the jobs in an order that is different than the defined order. The method includes transmitting the received information to the host for the plurality of jobs in the defined order.04-07-2011
20110078388FACILITATING MEMORY ACCESSES - In computing environments that use virtual addresses (or other indirectly usable addresses) to access memory, the virtual addresses are translated to absolute addresses (or other directly usable addresses) prior to accessing memory. To facilitate memory access, however, address translation is omitted in certain circumstances, including when the data to be accessed is within the same unit of memory as the instruction accessing the data. In this case, the absolute address of the data is derived from the absolute address of the instruction, thus avoiding address translation for the data. Further, in some circumstances, access checking for the data is also omitted.03-31-2011
20110078390INFORMATION PROCESSING APPARATUS AND SEMICONDUCTOR STORAGE DEVICE - An information processing apparatus includes: a processor configured to perform a computation processing; a storage device configured to store first data in a first number of physical blocks and store second data in a second number of physical blocks, wherein the second data are read more frequently than the first data, and the second number is larger than the first number; and a read control module configured to read the second data from the storage device and send the second data to the processor, wherein when the processor reads the second data N times as much as the second number, N being a positive integer, the same number of the second data are read from each of the second number of physical blocks.03-31-2011
20110078387WRITING TO MEMORY USING SHARED ADDRESS BUSES - Techniques for writing to memory using shared address buses. A memory device that includes a plurality of memory arrays connected to a common address bus, the common address bus used to broadcast memory addresses simultaneously to the plurality of memory arrays. Each memory array includes a plurality of memory locations and circuitry for: receiving the broadcasted memory addresses from the address bus; selecting a memory address in the memory array from a list of most recent memory addresses received from the address bus; and performing a memory access at the selected memory address, such that at a given point in time at least two of the memory arrays perform the memory access at a different broadcasted address when the memory access is a write.03-31-2011
20110179235DRIVING DEVICE AND METHOD OF ACCESSING DATA BY USING THE SAME - A driving device and a method of accessing data are provided. The driving device includes a bridge and a driver. The bridge includes a first controller. The driver includes a storage unit and a second controller. The first controller is for outputting a command according to an operating event. The second controller is for obtaining a corresponding data from the storage unit according to the command and uploading the data to the first controller.07-21-2011
20100131722APPARATUS AND METHOD FOR BUFFER MANAGEMENT FOR A MEMORY OPERATING - The invention provides a buffer management apparatus coupled between a memory and a plurality of circuit blocks accessing the memory. In one embodiment, the buffer management apparatus comprises an arbiter, a plurality of buffers, and a multiplexer. The arbiter selects a plurality of owners for the buffers from the circuit blocks, passes a plurality of access request signals generated by the owners to the corresponding buffers, and delivers a plurality of access response signals retrieved from the corresponding buffers to the owners in reply to the access request signals. The multiplexer alternately retrieves the access request signals from the buffers to generate a memory access signal delivered to a memory controller of the memory, receives a memory response signal generated by the memory controller in reply to the memory access signal, and distributes the memory response signal to the buffers as the access response signals.05-27-2010
20110087848METHODS AND SYSTEMS FOR IMPLEMENTING A VIRTUAL STORAGE NETWORK - Embodiments of the invention provide systems and methods for implementing a virtual Storage Area Network (SAN) in software. According to one embodiment, a method for implementing a virtual SAN can comprise defining an application for accessing a computing grid for storing information wherein defining the application for accessing the computing grid for storing the information comprises defining a resource and defining one or more state objects for the resource, wherein the one or more state objects are handled independent from the resource. For example, the computing grid can comprise an Oracle Coherence grid. Such a computing grid can maintain a primary copy and a backup copy of the information and provides the backup of the information if the primary copy is unavailable. The information stored on the computing grid can be accessed via the application.04-14-2011
20100131721MANAGING MEMORY TO SUPPORT LARGE-SCALE INTERPROCEDURAL STATIC ANALYSIS FOR SECURITY PROBLEMS - Embodiments of the invention describe systems and methods for application level management of virtual address space. A static analysis application can model and analyze a large and complex source code listing to determine whether it has vulnerabilities without exhausting the virtual memory resources provided to it by the operating system. In one embodiment of the invention, the method includes analyzing the source code listing to create a call graph model to represent the expected sequences of routine calls as a result of the inherent control flow of the source code listing. The method also includes monitoring the amount of virtual memory resources consumed by the dynamic state, and swapping out to a storage medium a portion of the dynamic state. The method includes reusing the virtual memory resources corresponding to the swapped out portion of the dynamic state to continue analyzing the source code listing.05-27-2010
20100030976CONTROL DEVICE - A control device is connected to a processor, a memory module, and a specification information storage memory for storing specification information indicating specifications of the memory module. The control device includes: a readout unit that reads the specification information from the specification information storage memory when power is turned on to the control device; a storage unit that stores the specification information read from the specification information storage memory; and a transfer unit that receives a specification information read instruction from the processor, and that transfers the specification information stored in the storage unit to the processor.a02-04-2010
20090307446DYNAMICALLY SETTING BURST LENGTH OF A DOUBLE DATA RATE MEMORY DEVICE - One or more external control pins and/or addressing pins on a memory device are used to set one or both of a burst length and burst type of the memory device.12-10-2009
20100070719SLAVE AND A MASTER DEVICE, A SYSTEM INCORPORATING THE DEVICES, AND A METHOD OF OPERATING THE SLAVE DEVICE - The electronic slave device (03-18-2010
20090037673External Memory Controller Node - A memory controller to provide memory access services in an adaptive computing engine is provided. The controller comprises: a network interface configured to receive a memory request from a programmable network; and a memory interface configured to access a memory to fulfill the memory request from the programmable network, wherein the memory interface receives and provides data for the memory request to the network interface, the network interface configured to send data to and receive data from the programmable network.02-05-2009
20090037671HARDWARE DEVICE DATA BUFFER - One embodiment includes a system comprising a processor configured to read and write data packets via a data bus to and from at least one additional hardware device. The system also comprises a data buffer configured to store a plurality of consecutive related flits associated with at least one of the data packets in one of a plurality of addressable locations of the data buffer. The system further comprises a pointer memory configured to store a respective pointer associated with each of the plurality of addressable locations of the data buffer.02-05-2009
20100037029HARDWARE TASK MANAGER - A hardware task manager for managing operations in an adaptive computing system. The task manager indicates when input and output buffer resources are sufficient to allow a task to execute. The task can require an arbitrary number of input values from one or more other (or the same) tasks. Likewise, a number of output buffers must also be available before the task can start to execute and store results in the output buffers. The hardware task manager maintains a counter in association with each input and output buffer. For input buffers, a negative value for the counter means that there is no data in the buffer and, hence, the respective input buffer is not ready or available. Thus, the associated task can not run. Predetermined numbers of bytes, or “units,” are stored into the input buffer and an associated counter is incremented. When the counter value transitions from a negative value to a zero the high-order bit of the counter is cleared, thereby indicating the input buffer has sufficient data and is available to be processed by a task.02-11-2010
20100037028Buffer Management Structure with Selective Flush - A buffer management structure for processing systems is described. In one embodiment, the buffer management structure includes a storage module and a control module. The storage module includes a read position and can store a bit indicating a valid state of a transaction request in a write entry. The control module can receive an invalidation request and modify the bit to indicate an invalid state for the transaction request and discard the transaction request when the transaction request is in the read position.02-11-2010
20090216964VIRTUAL MEMORY INTERFACE - The embodiments that are described herein provide random access to individual data storage locations of a group of buffers, which may be scattered in the memory. These embodiments provide a virtual memory interface that applies virtual addresses in a flat memory linear addressing space as indices into the physical memory addresses that are ordered into a sequence in accordance with the group of buffers. In this way, these embodiments enable a device (e.g., a processor) to directly and sequentially access all of the scattered physical memory locations of a fragmented data item, such as a packet, without having to perform any memory segmentation or paging processes. In some embodiments, these accesses include both read and write accesses to the scattered data storage locations.08-27-2009
20100070720MEMORY ACCESS METHOD - The memory access method of the present invention comprises preparing upper addresses separately from the address width of the Pseudo SRAM (03-18-2010
20110179236Memory Block Reclaiming Judging Apparatus and Memory Block Managing System - A memory block reclaiming judging apparatus and a memory block managing system are disclosed in the present invention. The memory block reclaiming judging apparatus comprises a peripheral information accessing unit, a data packet information recording unit, a data calculating unit, and a comparing and judging unit, wherein the data calculating unit is configured to calculate remaining scheduling times of a data packet-and write the remaining scheduling times of the data packet into the data packet information recording unit, and meanwhile set a flag for indicating acquirement of information of the required scheduling times as valid; the comparing and judging unit is configured to generate a memory block reclaiming instruction, reset the remaining scheduling times of the data packet in the data packet information recording unit to an initial value, and set the flag for indicating acquirement of information of the required scheduling times as invalid.07-21-2011
20110179234STORAGE DEVICE AND A METHOD FOR EXPANDING THE SAME - In a storage device expandable through serially coupling two or more additional enclosures, each including a first additional controller and a second additional controller, to a controller enclosure, including a first controller and a second controller, a first route is formed by serially coupling the first controller of the controller enclosure to the first additional controllers of the additional enclosures in the order of adding the additional enclosures and a second route is formed by serially coupling the second controller of the controller enclosure to the second additional controllers of the additional enclosures in an order different from that of adding the additional enclosures.07-21-2011
20110179232METHOD AND SYSTEM FOR ALLOCATING DATA OBJECTS FOR EFFICIENT READS IN A MASS STORAGE SUBSYSTEM - A system and method for allocating data objects across multiple physical storage devices in a mass storage subsystem first determines a set of physical properties associated with the physical storage devices. The system assigns portions of the mass storage subsystem to a first division or a second division based on the physical properties, such that read operations directed to logically related data stored in the first division can be executed more efficiently than read operations directed to data stored in the second division. During operation, the system stores data objects with a low SLR in the second division, which may be allocated according to any well-known file system. If a write request is for a new data object with a high SLR, the system stores the new data object in a set of neighboring primary data chunks in the first division. For subsequent write requests that modify a stored data object, the system stores the modified data in a spillover data chunk located in proximity to the primary data chunk.07-21-2011
20100064110METHOD FOR READING OUT DATA FROM A STORAGE MEDIUM - A method for reading out data from a storage medium which stores the data in such a way that they are distributed in sectors, each sector being assigned a sector identifier as a function of the datum respectively stored in the sector. The method includes the following steps: a) assigning a data identifier corresponding to the datum to be read out; b) grouping the data identifiers into at least one group; and c) carrying out a search algorithm in which the sector identifier in each sector is compared by sector and by group to the data identifiers contained in the group, and when one of the data identifiers corresponds to a sector identifier the particular datum is read out from the sector.03-11-2010
20100058004Method of manufacturing a limited use data storing device - Embodiments of methods and systems for controlling access to information stored on memory or data storage devices are disclosed. In various embodiments, methods of retrieving information from a data storage device previously deactivated by modification or degradation of at least a portion of the data storage device are disclosed.03-04-2010
20110099340MEMORY ACCESS CONTROL DEVICE AND METHOD THEREOF - A memory access control device and method is provided with a cache memory having a plurality of cache areas, each for storing image data of one macroblock, and a cache table having a plurality of table areas, corresponding to the plurality of cache areas, each for storing a scheduled access counter that counts the number of scheduled accesses to a corresponding cache area and an in-frame address of image data of one macroblock stored in the corresponding cache area. A data request processor receives a data request including specification of an in-frame occupation region of the requested image data from the image processor, determines target image data of at least one macroblock required to process requested image data based on the in-frame occupation region of the requested image data, acquires the target image data from the cache memory, processes the image data requested by the data request using the acquired image data, and outputs the processed image data to the image processor.04-28-2011
20100268899MEMORY CONTROLLER, NONVOLATILE STORAGE DEVICE, DATA PROCESSING DEVICE, NONVOLATILE STORAGE DEVICE SYSTEM, AND METHOD - A memory controller (10-21-2010
20110153961STORAGE DEVICE WITH FUNCTION OF VOLTAGE ABNORMAL PROTECTION AND OPERATION METHOD THEREOF - The present invention discloses a storage device and an operation method thereof. The storage device includes a non-volatile memory for storing data, a control unit coupled to the non-volatile memory, a power supply unit coupled to an external power source and converting the external power source to a suitable voltage for the non-volatile memory and the control unit, and a power monitor unit for monitoring the external power source. When the external power source falls below a low voltage threshold of the non-volatile memory, a control signal is transmitted into the control unit so as to stop accessing the non-volatile memory. The non-volatile memory finishes the last processing procedure according to the last programming instruction sent by the control unit before the control signal for protecting the data stored in the non-volatile memory.06-23-2011
20110153960TRANSACTIONAL MEMORY IN OUT-OF-ORDER PROCESSORS WITH XABORT HAVING IMMEDIATE ARGUMENT - Methods, systems, and apparatuses to provide an XABORT in a transactional memory access system are described. In one embodiment, the stored value is a context value indicating the context in which a transactional memory execution was aborted. A fallback handler may use the context value to perform a series of operations particular to the context in which the abort occurred.06-23-2011
20080229032CELL PROCESSOR ATOMIC OPERATION - A method is disclosed for atomic operation in a processor system comprising a main memory and a power processor element (PPE) including a power processor unit (PPU) and an external cache. A processor system and processor readable medium for implementing the method are also disclosed.09-18-2008
20110072221METHOD FOR WRITING AND READING DATA IN A NONVOLATILE MEMORY, BY MEANS OF METADATA - A method for writing and reading data in memory cells, comprises the steps of: defining a virtual memory, defining write commands and read commands of data (DT) in the virtual memory, providing a first nonvolatile physical memory zone (A03-24-2011
20120303910Detecting Potential Access Errors In A Multi-Threaded Application - In one embodiment, a method includes maintaining thread analysis metadata for a multi-threaded application. The metadata may include a thread vector clock for threads of the application and a synchronization vector clock for synchronization objects of the application. In addition, an initialization log and an access log can be generated and maintained for memory accesses occurring during execution of the application. From this metadata, it may be determined if an access to a memory element by a thread is a potential invalid access for a different scheduling of the application. Other embodiments are described and claimed.11-29-2012
20120303909IMPLEMENTING STORAGE ADAPTER PERFORMANCE OPTIMIZATION WITH ENHANCED HARDWARE AND SOFTWARE INTERFACE - A method and controller for implementing storage adapter performance optimization with chained hardware operations and an enhanced hardware (HW) and firmware (FW) interface minimizing hardware and firmware interactions, and a design structure on which the subject controller circuit resides are provided. The controller includes a plurality of hardware engines; and a processor. A data store is configured to store a plurality of control blocks. A global work queue includes a plurality of the control blocks selectively arranged in a predefined chain to define sequences of hardware operations. The global work queue includes a queue input coupled to the processor and the hardware engines and an output coupled to the hardware engines. The control blocks are arranged in respective engine work queues designed to control hardware operations of the respective hardware engines and respective control blocks are arranged in an event queue to provide completion results to the processor.11-29-2012
20110078386BUFFERING IN MEDIA AND PIPELINED PROCESSING COMPONENTS - Methods and apparatus relating to buffering in media and pipelined processing components are described. In one embodiment, a buffer may include an arbiter to receive data structure information from a producer, a memory to store the information, and an address generator to indicate a location in the memory to store the data structure information. Other embodiments are also disclosed.03-31-2011
20110252205Managing Access Commands By Multiple Level Caching - Apparatus and associated method concerning managing access commands with a main storage space, a volatile buffer, and a nonvolatile buffer. The volatile buffer is configured to store a plurality of command nodes that are associated with data access commands received from a remote device and directed to the main storage space. The apparatus also has command prioritizing logic configured for using a prescribed rule in repeatedly identifying two or more candidate command nodes of the plurality that are at least individually favored for execution with respect to the main storage space, for selecting one of the candidate command nodes for the execution, and for transferring a nonselected one of the candidate command nodes from the volatile buffer to the nonvolatile buffer where the nonselected command node continues to be considered for execution with respect to the main storage space but is no longer considered by the prescribed rule when identifying subsequent candidate command nodes in the volatile buffer.10-13-2011
20120203982FIFO BUFFER AND METHOD OF CONTROLLING FIFO BUFFER - A first-in first-out buffer includes: a memory set capable of writing and reading data within one cycle by combining a plurality of memories, each memory performing any one of writing and reading of data within one cycle; an output unit that outputs a first signal indicating a memory included in the memory set, the memory being capable of writing data; a writing control unit that performs writing control of data to be written to the memory indicated by the first signal when the data to be written is inputted; and a first holding unit that, in accordance with an instruction from the writing control unit, holds the first signal that is outputted from the output unit and indicates the memory in which head data of the data to be written is written.08-09-2012
20120203981Method and apparatus for executing software applications - Consumer electronic devices, such as e.g. high-definition movie players for removable storage media such as optical discs, may provide possibilities for advanced interactivity for the user, implemented as software applications. A question arising generally with such software applications is what the life cycle of such an application is, and who may control it. The invention provides a method for executing software applications within a playback device for audio-video data, wherein data from a first removable storage medium are read for a software application to be executed within said playback device, and the data comprise an indication defining a termination condition for the application. Based on said termination code and depending on how the medium holding the application is ejected, the application is terminated or may survive.08-09-2012
20120203979Architecture Support for Debugging Multithreaded Code - Mechanisms are provided for debugging application code using a content addressable memory. The mechanisms receive an instruction in a hardware unit of a processor of the data processing system, the instruction having a target memory address that the instruction is attempting to access. A content addressable memory (CAM) associated with the hardware unit is searched for an entry in the CAM corresponding to the target memory address. In response to an entry in the CAM corresponding to the target memory address being found, a determination is made as to whether information in the entry identifies the instruction as an instruction of interest. In response to the entry identifying the instruction as an instruction of interest, an exception is generated and sent to one of an exception handler or a debugger application. In this way, debugging of multithreaded applications may be performed in an efficient manner.08-09-2012
20120203977Page Mode Access by Non-page Mode Device - A method is provided for accessing a memory device having pages by a memory interface that does not directly support page accesses. A first memory space of the memory interface is configured with a first set of timing parameters and a second memory space of the memory interface is configured with a second set of timing parameters. A page mode access is initiated to a page of the memory device using the first memory space of the memory interface for at least a first data transfer and continued using the second memory space of the memory interface for a plurality of data transfers.08-09-2012
20110029744DISPERSED STORAGE NETWORK VIRTUAL ADDRESS SPACE - A dispersed storage network utilizes a virtual address space to store data. The dispersed storage network includes a processing unit operable to slice a data segment of a data object into data slices and create a slice name for each of the data slices. The slice name includes an identifier of the data object and a virtual memory address of a virtual memory associated with the dispersed storage network. The processing unit further outputs each of the data slices and the respective slice names to a corresponding storage unit for storage of the data slices therein.02-03-2011
20110258400PARALLEL MEMORY DEVICE RANK SELECTION - A translator circuit translates a memory access conforming to a native FB-DIMM (Fully Buffered Dual In-Line Memory Module) protocol to a memory access for addressing more than two ranks of parallel memory devices. The parallel memory devices are distributed among plural non-fully-buffered DIMMs (Dual In-Line Memory Modules).10-20-2011
20100115211BEHAVIORAL MONITORING OF STORAGE ACCESS PATTERNS - A storage control system monitors storage operations directed to storage blocks in a storage device. The storage control system uses arrays of counters to track a number of the storage operations, sizes of the storage operations, types of transitions between the storage operations, and time durations between different types of successive storage operations. The storage blocks are classified into different behavioral groups based on the access pattern history of the individual blocks. The behavioral group classifications are then used by the storage control system to determine when to access the storage blocks from the storage device, when to load the storage blocks into a tiering media, or when to time out the storage blocks from the tiering media.05-06-2010
20100262790Memory Controllers, Methods, and Systems Supporting Multiple Memory Modes - A memory system includes a memory controller with a plurality N of memory-controller blocks, each of which conveys independent transaction requests over external request ports. The request ports are coupled, via point-to-point connections, to from one to N memory devices, each of which includes N independently addressable memory blocks. All of the external request ports are connected to respective external request ports on the memory device or devices used in a given configuration. The number of request ports per memory device and the data width of each memory device changes with the number of memory devices such that the ratio of the request-access granularity to the data granularity remains constant irrespective of the number of memory devices.10-14-2010
20100082910SKIP BASED CONTROL LOGIC FOR FIRST IN FIRST OUT BUFFER - A system and method of a skip based control logic for a first in first out (FIFO) buffer is disclosed. In one embodiment, a FIFO buffer system includes a storage for storing data, a write pointer for pointing to a write address of the storage for a write operation, and a read pointer for pointing to a read address of the storage for a read operation. Further, the FIFO buffer system includes a control logic for incrementing the read pointer based on a skip parameter of a skip register. The skip parameter is used to characterize a validity of the data for the read operation.04-01-2010
20100005252STORAGE CONTROL SYSTEM - A storage control system includes a storage device and a UPS electrically connected to and communicating with the storage device. The storage device has a write back process and a write through process for writing data into the storage device, and includes a monitoring module. The UPS includes a control chip. The control chip of the UPS sends state signals to the storage device. The monitoring module receives the state signals and selects one of the write back process and the write through process to replace the other one of the write back process and the write through process for writing data into the storage device, depending on the state signals.01-07-2010
20090327620CIRCUIT STRUCTURE AND METHOD FOR DIGITAL INTEGRATED CIRCUIT PERFORMANCE SCREENING - Disclosed is a semiconductor chip with a digital integrated circuit, such as a memory device (e.g., static random access memory (SRAM) arrays, dynamic random access memory (DRAM) arrays, content addressable memory (CAM) arrays, etc), that can be selectively operated in either a functional mode or in a performance screening mode. In the functional mode, a first signal supplied by an external signal generator is used to activate a first device in the circuit and, in response, a second device in the circuit outputs a data output signal. In the performance screening mode, a second signal is internally generated by an internal signal generator based on the data output signal. This second signal is then used to activate the first device in the circuit and, in response, the second device outputs the data output signal. Thus, in the performance screening mode, the digital integrated circuit is effectively converted into a performance screen ring oscillator (PSRO), the output of which can be monitored to determine whether performance criteria for the digital integrated circuit are met.12-31-2009
20090240899Storage device and method of controlling same - A storage device having a volume for storing data sent from a host computer and transferring the data stored in the volume to a sub storage device via a network, comprises: a retrieval unit for retrieving a snapshot retaining change data generated in the volume during a time period between a given time and another given time, and a maximum transfer size of the network between the storage device and the sub storage device; and a control unit for controlling so as to store data exceeding a maximum transfer size in the area of another snapshot, when the size of a created snapshot exceeds the maximum transfer size.09-24-2009
20090216965Storage device and access instruction sending method - A storage device for storing data sent from a host apparatus comprises a plurality of processors sending to a cache memory controller an access instruction relating to transmission of the data, based on an access request relating to the transmission of the data, the access request being sent from the host apparatus; and an access instruction sending unit exclusively sending to the cache memory the access instruction sent from the plurality of processors, wherein the access instruction sending unit includes a plurality of storage units for storing an access instruction which requires a response, and wherein when the access instruction which requires a response is stored in all of the storage units, the access instruction sending unit sends only an access instruction which requires a response to the cache memory controller.08-27-2009
20080320250WIRELESSLY CONFIGURABLE MEMORY DEVICE - A configurable memory includes an interface section, a plurality of memory modules, and an internal configuration section. The interface section includes a millimeter wave (MMW) transceiver and interfaces with one or more external components. Each the plurality of memory modules includes a memory MMW transceiver and a plurality of memory cells. The internal configuration section includes a memory management unit and a memory management MMW transceiver. The memory management unit is operable to determine configuration of at least some of the plurality of memory modules to form a memory block, identify an interface MMW transceiver to provide a wireless link to the memory block, and generate a configuration signal based on the determined configuration and the identified interface MMW transceiver. The memory management MMW transmits the MMW configuration signal to the identified interface MMW transceiver and the MMW transceivers of the memory modules.12-25-2008
20080320246Methods and apparatus for compiling instructions for a data processor - Methods and apparatus optimized for compiling instructions in a data processor are disclosed. In one aspect, a method of address calculation is disclosed, comprising operating a compiler to generate at least one instruction; canonicalizing the address calculation in a plurality of different approaches: in one exemplary embodiment, the first approach comprises canonicalizing the “regular” 32-bit instruction addressing modes, and the second for the “compressed” 16-bit instruction addressing modes. In another aspect, a plurality of functions (up to and including all available functions) are called indirectly to allow addresses to be placed in a constant pool. Improved methods for instruction selection, register allocation and spilling, and instruction compression are provided. An improved SoC integrated circuit device having an optimized 32-bit/16-bit processor core implementing at least one of the foregoing improvements is also disclosed.12-25-2008
20080320249FULLY BUFFERED DIMM READ DATA SUBSTITUTION FOR WRITE ACKNOWLEDGEMENT - A memory controller uses a scheme to retire two entries from a replay queue due to a single non-error response. Advantageously, entries in a replay queue may be retired earlier than conventional systems, minimizing the size of the replay queue.12-25-2008
20110258403MEMORY HUB WITH INTEGRATED NON-VOLATILE MEMORY - A method for initializing a memory sub-system is provided. The method includes loading configuration registers of a plurality of memory hubs with the configuration information provided by a respective one of a plurality of embedded non-volatile memories integrated in the respective memory hub. The non-VOLATILE memory is accessed through a first configuration path from a memory controller of the memory sub-system to the non-VOLATILE memory.10-20-2011
20110258396DATA ACCESS AND MANAGEMENT SYSTEM AS WELL AS A METHOD FOR DATA ACCESS AND DATA MANAGEMENT FOR A COMPUTER SYSTEM - The present invention permits improved data access and improved data management in a computer system. To this end, data are divided into individual partial data (F) and stored in cells (Z) of storage devices (C) in such a way that the partial data (F) being accessed and managed are present in the computer system in a redundant manner. Computer units (CL) are able to access the redundantly stored data The fact that they are stored in the storage devices (C) ensures that the computer units (CL) accessing said data are supplied more rapidly. This is achieved in particular owing to the fact that the redundantly stored data are accessed in accordance with parameters of data transmissions between the computer units (CL) and the data storage devices (C) and that, in accordance with said data transmission parameters, the redundantly stored data are moved to and from the data storage devices (C) by corresponding copy and delete operations.10-20-2011
20110179233ELECTRONIC DATA STORE - A method of, and apparatus for, predicting the performance of a data storage resource forming part of a networked electronic data store. The method includes representing the data storage resource as a plurality of separate virtual storage components, each virtual storage component representing a part of the data storage resource and having at least one operational state selectable from a pool of operational states. The method further includes obtaining resource profile data from the data storage resource, and modelling the performance of the data storage resource by assigning, from the pool, an operational state to each virtual storage component to fit the resource profile data. By providing such a method, the data storage resource can be represented as a collection of virtual storage components, each having a dynamically-assignable operational state. This enables the modelling of the performance of the data storage resource to be simplified significantly because each virtual storage component can only have a finite number of operational states, simplifying the modelling of access patterns on, and interactions between, the virtual storage components.07-21-2011
20080229033Method For Processing Data in a Memory Arrangement, Memory Arrangement and Computer System - A method processes data in a memory arrangement. The method includes receiving and transmitting the data from the memory arrangement in the form of data packets according to a predefined protocol. The method includes distributing each received data packet to at least two separate data packet processing units. Each data packet processing unit is coupled to a portion of memory cells of the memory arrangement. The method includes processing, at each data packet processing unit, parts of the received data packets that relate to the portion of the memory cells the data packet processing unit is coupled to. The method includes generating a data packet to be transmitted including setting up, with each data packet processing unit, a part of the data packet to be transmitted.09-18-2008
20120203978COMPUTER SYSTEM AND ITS CONTROL METHOD - A computer system and its control method capable of allocating resources to a plurality of users in a balanced manner and ensuring information security between the users even when the plurality of users are made to extensively manage a storage system are provided.08-09-2012
20120203984PAGE INVALIDATION PROCESSING WITH SETTING OF STORAGE KEY TO PREDEFINED VALUE - A method is provided for facilitating processing within a multiprocessor computer system by: setting, in association with invalidate page table entry processing, a storage key at a matching location in central storage of a multiprocessor computer system to a predefined value; and subsequently executing a request to update the storage key to a new storage key, the subsequently executing including determining whether the predefined value is an allowed stale value, and if so, replacing in central storage the storage key of predefined value with the new storage key without requiring purging or updating of the storage key in any local processor cache of the multiprocessor computer system, thus minimizing interprocessor communication pursuant to processing of the request to update the storage key to the new storage key.08-09-2012
20080256308Storage system, method for managing the same, and storage controller - A storage system includes one or more host computers; and a storage controller that provides each of the one or more host computers with a plurality of logical volumes, each including a storage area for reading/writing data from/to, and also being either allocated or not allocated to one or more of the host computers, the storage controller including: an identification unit that identifies function information relating to a logical volume from among the plurality of logical volumes included in information relating to the plurality of logical volumes based on a command from a host computer from among the one or more host computers; and an execution unit that executes processing on the logical volume in accordance with an identification result of the identification unit.10-16-2008
20110055497Alignment and Ordering of Vector Elements for Single Instruction Multiple Data Processing - The present invention provides alignment and ordering of vector elements for SIMD processing. In the alignment of vector elements for SIMD processing, one vector is loaded from a memory unit into a first register and another vector is loaded from the memory unit into a second register. The first vector contains a first byte of an aligned vector to be generated. Then, a starting byte specifying the first byte of an aligned vector is determined. Next, a vector is extracted from the first register and the second register beginning from the first bit in the first byte of the first register continuing through the bits in the second register. Finally, the extracted vector is replicated into a third register such that the third register contains a plurality of elements aligned for SIMD processing. In the ordering of vector elements for SIMD processing, a first vector is loaded from a memory unit into a first register and a second vector is loaded from the memory unit into a second register. Then, a subset of elements are selected from the first register and the second register. The elements from the subset are then replicated into the elements in the third register in a particular order suitable for subsequent SIMD vector processing.03-03-2011
20110055496SIGNAL PROCESSOR, TRANSMISSION APPARATUS, AND METHOD FOR PROCESSING SIGNAL - A signal processor includes a processor that counts the number of input data pieces or a size of each of the input data pieces; a first memory that stores a result of the counting by the processor; and a second memory that records whether the result of the counting exceeds a capacity of the first memory.03-03-2011
20110055495Memory Controller Page Management Devices, Systems, and Methods - Memory controller page management devices, systems, and methods are disclosed. In one embodiment, a memory controller is configured to access memory in response to a memory access request. The memory controller is configured to apply a page management policy to either leave open or close a memory page based on at least identification information of a requestor. In this manner, a memory page management policy can be applied by the memory controller to optimize memory access times and reduce latency based on the identification of the requestor. For example, the requestor may be associated with sequential or series of memory access requests to the same memory such that a leave open page management policy would be optimal for reduced memory access times. As another example, the requestor may be associated with memory access requests to random memory pages such that a close page management policy would be optimal for reduced memory access times.03-03-2011
20110055494METHOD FOR DISTRIBUTED DIRECT OBJECT ACCESS STORAGE - Methods and apparatus are described for a horizontally scalable high performance object storage architecture. Metadata are completely decoupled from object storage. Instead of file names, users are given a locator when the object is uploaded and committed. Users can store the locator along with their own metadata or embed it directly in the static content. Clients can choose which storage nodes to store data on based on dynamic measures of node performance. Since there is no coupling among storage servers, performance can scale horizontally by adding more nodes. The decoupling also allows the front end services and storage to scale independently. High service availability is achieved by object-level synchronous replication and having no single point of failure. Failed nodes are rebuilt using copies of data in other nodes without taking the cluster offline. In addition to the replication, the ability to add or remove nodes on-line reduces maintenance-related service downtime.03-03-2011
20110258402COMPUTER SYSTEM OR PERFORMANCE MANAGEMENT METHOD OF COMPUTER SYSTEM - This invention provides a system including a computer and a storage-subsystem comprising at least either a first storage area for storing data sent from the computer or a second storage area to be associated with the first storage area, for storing replicated data of data stored in the first storage area. This system includes a replication processing status referral unit for referring to a replication processing status of data of the first storage area and the second storage area to be associated, and an output unit for outputting first performance information concerning data I/O stored in the first storage area, and outputting second performance information concerning data I/O stored in the second storage area together with the first performance information when the replicated data is being subject to replication processing from the first storage area to the second storage area as a result of referring to the replication processing status.10-20-2011
20110258401Queuing of conflicted remotely received transactions - Queuing of received transactions that have a resource conflict is disclosed. A first node receives a first transaction from a second node, where the first transaction relates to a resource of the first node. The transaction may be a request relating to a memory line of the first node, for instance. It is determined that a second transaction that relates to this resource of the first node is already being processed by the first node. Therefore, the first transaction is enqueued in a conflict queue within the first node. The queuing may be a linked list, a priority queue, or another type of queue. Once the second transaction has been processed, the first transaction is restarted for processing by the first node. The first transaction is then processed by the first node.10-20-2011
20110258398METHODS AND SYSTEMS FOR VECTORED DATA DE-DUPLICATION - The present invention is directed toward methods and systems for data de-duplication. More particularly, in various embodiments, the present invention provides systems and methods for data de-duplication that may utilize a vectoring method for data de-duplication wherein a stream of data is divided into “data sets” or blocks. For each block, a code, such as a hash or cyclic redundancy code may be calculated and stored. The first block of the set may be written normally and its address and hash can be stored and noted. Subsequent block hashes may be compared with previously written block hashes.10-20-2011
20110258397METHOD OF PROTECTION OF DATA DURING THE EXECUTION OF A SOFTWARE CODE IN AN ELECTRONIC DEVICE - The invention is a method of protecting a data intended to be accessed by an operating system embedded in an electronic device. The operating system is intended to manage an object comprising a header and a body. The data is stored in the body. The object is recorded in a memory of the electronic device. The electronic device comprises a memory manager able to provide access to the memory. The memory manager forbids the operating system to access the body as long as a preset action has not been successfully performed.10-20-2011
20080201539DATA STORAGE DEVICE AND METHOD OF OPERATING THE SAME - A data storage device and a method of operating the same include firmware recognizing that the data storage device has a smaller than normal capacity or includes a routine in the firmware when the number of bad blocks exceeds the maximum. Therefore, even if the number of bad blocks exceeds the maximum, the data storage device having a capacity smaller than the normal capacity can be used.08-21-2008
20080201538MEMORY CONTROL METHOD AND MEMORY SYSTEM - Error-tolerant code conversion is carried out on original data including a large amount of binary data which is apt to be unintentionally rewritten, to produce converted data including a smaller amount of binary data which is apt to be unintentionally rewritten, and the converted data is written into a memory. While a host system is processing the original data, the memory reads out the converted data and the code inverse transformation part carries out inverse transformation of error-tolerant code conversion on the converted data, to output reproduced data which is identical to the original data, to the host system. As a result, it is possible to avoid or suppress the possibility that data is unintentionally rewritten due to repeated readout of the same data.08-21-2008
20080201536Near instantaneous backup and restore of disc partitions - An apparatus comprises a data storage medium including first and second partitions, wherein individual physical blocks in the first partition are paired with individual physical blocks in the second partition, a status flag for each of the pairs of physical blocks, and a controller for performing read and write operations on the physical blocks in accordance with the status flags. A method performed by the apparatus is also provided.08-21-2008
20110264869CONCLUSIVE WRITE OPERATION DISPERSED STORAGE NETWORK FRAME - A method begins by a processing module generating a payload of a dispersed storage network frame regarding a conclusive write request operation by generating one or more slice name fields of a payload to include one or more slice names corresponding to one or more write commit responses of a write request operation, wherein the conclusive write request operation is a conclusive phase of the write request operation. The method continues with the processing module generating one or more slice revision numbering fields of the payload, wherein each slice revision numbering field includes a slice revision number corresponding to an associated slice name of the one or more slice names. The method continues with the processing module generating a protocol header of the DSN frame by generating a payload length field of the protocol header to include a payload length and generating remaining fields of the protocol header.10-27-2011
20110264871SYSTEMS AND METHODS FOR TRANSFORMATION OF LOGICAL DATA OBJECTS FOR STORAGE - Systems and methods for transforming a logical data object for storage in a storage device operable with at least one storage protocol, creating, reading, writing, optimization and restoring thereof. Transforming the logical data object comprises creating in the storage device a transformed logical data object comprising one or more allocated storage sections with a predefined size; transforming one or more sequentially obtained chunks of obtained data corresponding to the transforming logical data object; and sequentially storing the processed data chunks into said storage sections in accordance with a receive order of said chunks, wherein said storage sections serve as atomic elements of transformation/de-transformation operations during input/output transactions on the logical data object. The processing may comprise two or more data transformation techniques coordinated in time, concurrently executing autonomous sets of instructions, and provided in a manner preserving the sequence of processing and storing the processed data chunks.10-27-2011
20110078389MANAGING AND IMPLEMENTING METADATA IN CENTRAL PROCESSING UNIT USING REGISTER EXTENSIONS - A set of default registers of a processor are expanded into metadata registers on the processor of a computer system. The default registers having stored thereon data, while metadata which is related to the data is stored separately on the metadata registers.03-31-2011
20100293345NETWORK COMMUNICATIONS PROCESSOR ARCHITECTURE WITH MEMORY LOAD BALANCING - Described embodiments provide a memory system including a plurality of addressable memory arrays. Data in the arrays is accessed by receiving a logical address of data in the addressable memory array and computing a hash value based on at least a part of the logical address. One of the addressable memory arrays is selected based on the hash value. Data in the selected addressable memory array is accessed using a physical address based on at least part of the logical address not used to compute the hash value. The hash value is generated by a hash function to provide essentially random selection of each of the addressable memory arrays.11-18-2010
20100293343SCHEDULING BASED ON TURNAROUND EVENT - Transmission of a signal is scheduled to avoid sending the signal during a designated event associated with another signal. For example, the time at which a signal is transmitted may be scheduled to avoid a turnaround time period of a bidirectional signal path. This technique may be employed, for example, in a memory system where a memory controller communicates with one or more memory devices or memory modules. Here, the memory system may be configured to avoid sending memory request signals during a driver turnaround window corresponding to when a bidirectional memory data interface switches from being driven by the memory controller to being driven by a memory device/module, or vice versa.11-18-2010
20100293341Wake-and-Go Mechanism with Exclusive System Bus Response - A wake-and-go mechanism is configured to issue a look-ahead load command on a system bus to read a data value from a target address and perform a comparison operation to determine whether the data value at the target address indicates that an event for which a thread is waiting has occurred. In response to the comparison resulting in a determination that the event has not occurred, the wake-and-go engine populates the wake-and-go storage array with the target address. In response to the comparison resulting in a determination that the event has occurred, the wake-and-go engine issues a load command on the system bus to read the data value from the target address with data exclusivity and determines whether the wake-and-go engine obtains a lock for the target address. Responsive to obtaining the lock for the target address, the wake-and-go engine holds the lock for the thread.11-18-2010
20110119455METHODS OF UTILIZING ADDRESS MAPPING TABLE TO MANAGE DATA ACCESS OF STORAGE MEDIUM WITHOUT PHYSICALLY ACCESSING STORAGE MEDIUM AND RELATED STORAGE CONTROLLERS THEREOF - A method of managing data access of a storage medium includes establishing an address mapping table to record a physical address of a first data stored in the storage medium, where the physical address of the first data is mapped to a logical address of the first data; and when receiving a command for handling the first data stored in the storage medium internally, processing the address mapping table to serve the command without physically accessing the first data stored in the storage medium.05-19-2011
20120151159INTERFACE METHODS AND APPARATUS FOR MEMORY DEVICES - A disclosed example apparatus includes an interface (06-14-2012
20120151157METHOD AND SYSTEM FOR HIJACKING WRITES TO A NON-VOLATILE MEMORY - A method and system for accessing enhanced functionality on a storage device is disclosed. A hijack command is sent to the storage device that includes an identifier (such as a signature or an address). The storage device determines whether to hijack one or more subsequently commands by analyzing the subsequently commands using the identifier. For example, the storage device may analyze the subsequently received commands to determine whether the signature is in the payload of the subsequently received commands. As another example, the storage device may compare the address in the subsequently received commands with the address in the hijack command to determine whether to hijack the subsequently received commands.06-14-2012
20100100691Indirect Register Access Method and System - Systems and methods are provided for managing access to registers. In one embodiment, a system may include a processor and a plurality of registers. The processor and the plurality of registers may be integrated into a single device, or may be in separate devices. The plurality of registers may include a first set of registers that are directly accessible by the processor, and a second set of registers that are not directly accessible by the processor. The second set of registers may, however, be accessed indirectly by the processor via the first set of registers. In one embodiment, the first set of registers may include a register for selecting a register bank from the second set of registers, and a register for selecting a particular address within the register bank, to allow indirect access by the processor to the registers of the second set.04-22-2010
20120311275STORAGE SUBSYSTEM AND LOAD DISTRIBUTION METHOD - Even if abnormality occurs in part of a plurality of data processing resources, data processing is executed by using a normal resource(s).12-06-2012
20110258399APPARATUS AND METHOD FOR IDENTIFYING DEVICE TYPES OF SERIES-CONNECTED DEVICES OF MIXED TYPE - A memory controller is unaware of device types (DTs) of a plurality (N) of series-connected memory devices in an interconnection configuration. Possible DTs include, e.g., random access memories and Flash memories. First, the memory controller sends a specific DT (“don't care”) and an initial number of binary code to the first device of the interconnection configuration and the binary code is propagated through the devices. Each device performs a “+1” calculation regardless of the DT. The last device provides the memory controller with Nד+1” from which the memory controller can obtain the number N of devices in the interconnection configuration. Thereafter, the memory controller sends a search number (SN) of binary code and a search DT for DT matching that propagate through the devices. Each device performs DT match determination of “previous match”, “present match” and “don't care match”. Based on the match determination, the SN and search DT are or not modified. The modified or non-modified SN and DT are propagated through the devices. Such processes are repeated. From the propagated SN and DT and the previously recognized number of the devices, the memory controller can identify the DT of each device in the interconnection configuration.10-20-2011
20110138136STORAGE SYSTEM AND CONTROLLING METHODS FOR THE SAME - For the purpose of optimizing the performance separation according to the usage status of the protocol and the storage system performance, in a storage system 06-09-2011
20110029745ELECTRONIC DEVICE AND CONTROL METHOD THEREOF - An electronic device comprises: a mounting unit in which a first storage medium to be mounted; an acquiring unit configured to acquire attribute information of a mounted storage medium; a first determining unit configured to determine whether or not the mounted storage medium is a storage medium having a function other than a storage function based on the attribute information; a transmitting unit configured to transmit a command that can be used in a function other than a storage function to the mounted storage medium, in a case where it is determined that the storage medium is not a storage medium having the function other than the storage function; and a second determining unit configured to determine whether or not the mounted storage medium has the function other than the storage function based on whether or not there is a response to the transmitted command.02-03-2011
20100122046Memory Micro-Tiling - According to one embodiment, a memory controller is disclosed. The memory controller includes assignment logic and a transaction assembler. The assignment logic receives a request to access a memory channel. The transaction assembler combines the request into one or more additional requests to access two or more independently addressable subchannels within the channel.05-13-2010
20100122045Method for processing data using triple buffering - The present invention relates to a method for processing data. A data block to be processed is written to a memory area in a first interval of time. The data block is processed in the same memory area (A, B, C) in a second interval of time. The processed data block is returned from the same memory area in a third interval of time.05-13-2010
20100122043MEMORY AND METHOD APPLIED IN ONE PROGRAM COMMAND FOR THE MEMORY - A memory and a method applied in one program command for the memory are provided. The memory includes a buffer and at least one program unit. The method includes the following steps. First, enter the program command to the memory. Next, enter user data to the buffer. Read the data of the program unit. Determine whether the user data fill the buffer. Fill the part of the buffer unoccupied by the user data with the data of the program unit if the user data do not fill the buffer. Erase the program unit if the program unit is not empty. Finally, program the data of the buffer into the program unit.05-13-2010
20100122042Multi-windows color adjustment system and method - The invention provides a multi-windows color adjustment system and method that divides the picture frame of a display screen into three or more windows so that the user can compare the color tones of the windows and then select the preferred window. The multi-windows color adjustment system includes a memory read/write controller coupled to an image data input for temporarily storing an input image data and executing read/write control, a window control unit coupled to the memory read/write controller for executing size, data flow and color tone controls of the windows, a line buffer coupled to the memory read/write controller and the window control unit for storing a line data, and a color adjustment unit coupled to the window control unit and the line buffer for executing the processing of color adjustment of the image data in the windows subject to the control of the window control unit.05-13-2010
20110093667INFORMATION PROCESSING APPARATUS, METHOD AND COMPUTER PROGRAM - An information processing apparatus for processing input data using multiple items of reference data in succession is provided. The apparatus includes a secondary storage unit configured to store the reference data; a primary storage unit accessible at a speed higher than that of the secondary storage unit; a read-out unit configured to read out the reference data from the secondary storage unit to the primary storage unit; an execution unit configured to execute processing of the input data using the reference data in the primary storage unit; a determination unit configured to determine, based upon at least one of a probability that reference data scheduled for use by the execution unit will change and quantity of the scheduled reference data, whether the scheduled reference data is to be prefetched; and a control unit configured to control prefetch based on the result of determination of the determination unit.04-21-2011
20110093668Thin Film Memory System - An electronic system includes at least one reduced-complexity integrated circuit memory coupled to a memory controller. By reducing the complexity of each integrated circuit memory and concentrating the complexity within the memory controller, overall system costs may be greatly reduced and reliability improved.04-21-2011
20110093666NUMERICAL CONTROLLER CAPABLE OF DIVIDING AND COMBINING MEMORY AREAS TO STORE MACHINING PROGRAMS AND BINARY DATA - A memory other than a non-volatile memory in a numerical controller is divided into a plurality of memory areas in response to a command from a computer connected to the numerical controller. Whether a machining program has been stored in each of the divided memory areas is decided before a machining program stored on a hard disk in the computer is transferred to the memory other than the non-volatile memory. The machining program stored on the hard disk is then written to an area for which it is determined that no machining program is stored.04-21-2011
20110093665MEMORY HAVING INTERNAL PROCESSORS AND METHODS OF CONTROLLING MEMORY ACCESS - Memories having internal processors and methods of data communication within such memories are provided. One such memory may include a fetch unit configured to substantially control performing commands on a memory array based on the availability of banks to be accessed. The fetch unit may receive instructions including commands indicating whether data is to be read from or written to a bank, and the address of the data to be read from or written to the bank. The fetch unit may perform the commands based on the availability of the bank. In one embodiment, control logic communicates with the fetch unit when an activated bank is available. In another implementation, the fetch unit may wait for a bank to become available based on timers set to when a previous command in the activated bank has been performed.04-21-2011
20110093663ATOMIC COMPARE AND WRITE MEMORY - A microcontroller system may include a microcontroller having a processor and a first memory, a memory bus and a second memory in communication with the microcontroller via the memory bus. The first memory may include instructions for accessing a first data set from a contiguous memory block in the second memory. The first data set may include a first word having a first value and a plurality of first other words. The first memory may include instructions for receiving a write instruction including a second data set to be written to the contiguous memory block. The first memory may include instructions for determining whether the first value equals the second value. If so, the first memory may include instructions for writing the second data set to the contiguous memory block and updating the first value.04-21-2011
20110093664DATA DE-DUPLICATION BY PREDICTING THE LOCATIONS OF SUB-BLOCKS WITHIN THE REPOSITORY - A computer-enabled method of storing an input dataset in a storage medium includes storing a copy for each of a plurality of repeatable blocks of data in an input dataset in a storage medium. The process further includes finding a location in the storage medium of the copy of a block of data in the input dataset. Finding the location includes determining a most likely location in the storage medium of the copy of the block of data from one or more blocks of data preceding the block of data based on statistics of past stored data. Finding the location further includes if the determined most likely location contains a block of data that matches with the actual block of data, retrieving the location in the storage medium of the copy of the block of data. The process also includes storing the location of the copy of the block of data.04-21-2011
20120151158MEMORY STORAGE DEVICE, MEMORY CONTROLLER THEREOF, AND METHOD FOR PROGRAMMING DATA THEREOF - A memory storage device, a memory controller thereof, and a method for programming data thereof are provided. The memory storage device comprises a rewritable non-volatile memory chip having a plurality of rewritable non-volatile memory modules, and each rewritable non-volatile memory module comprises a plurality of physical blocks. The method includes receiving a write command from a host system, and a logical address corresponding to the write command belongs to a predetermined logical address range. The method also includes determining whether a suitable memory module has not stored any data belonging to the predetermined logical address range exists in all rewritable non-volatile memory modules. The method further includes writing a writing data corresponding to the write command into the suitable memory module if it is existent.06-14-2012
20120151156VECTOR GATHER BUFFER FOR MULTIPLE ADDRESS VECTOR LOADS - A dedicated vector gather buffer (VGB) that stores multiple cache lines read from a memory hierarchy in one or more Logical Units (LUs) each having multiple buffer entries and performs parallel operations on vector registers. Once loaded with data, an LU is read using a single port. The VGB initiates prefetch events that keep it full in response to the demand created by ‘gather’ instructions. The VGB includes one or more write ports for receiving data from the memory hierarchy and a read port capable of reading data from the columns of the LU to be loaded into a vector register. Data is extracted from the VGB by (1) using a separate port for each item read, (2) implementing each VGB entry as a shift register and shifting an appropriate amount until all entries are aligned, or (3) enforcing a uniform offset for all items.06-14-2012
20090300296Communication apparatus with data discard functions and control method therefor - In a communication apparatus, a write controller writes received data in a temporary memory which serves as short-time storage. A read controller reads data out of the temporary memory. A discard controller controls discard operation of the data read out of the temporary memory.12-03-2009
20090282202Technique to perform memory disambiguation - A memory access management technique. More particularly, at least one embodiment of the invention relates to a technique to issue loads to a memory ahead of older store operations corresponding to the same target address.11-12-2009
20090282201STORAGE DEVICE CONTROL METHOD AND COMPUTER SYSTEM - A storage device control method for operating a logical volume to which a control command cannot be issued directly from a host computer is provided. The host computer manages a storage device. The storage device includes a disk device which provides logical volumes and a disk control device which controls the disk device. The host computer issues a control command to a recognized volume in the disk control device. The disk control device operates a recognized volume which is an issue destination of the control command or an unrecognized volume contained in the control command. A logical volume to which the control command is to be issued from the host computer is determined by using definition information (a disk information table, a copy pair information table, or a copy group information table) concerning copy operation retained by storage control software which operates on the host computer.11-12-2009
20110197034MEMORY CONTROLLER, NONVOLATILE STORAGE MODULE, ACCESS MODULE AND NONVOLATILE STORAGE SYSTEM - When a write command is issued, new data is written into a free physical block of a nonvolatile memory (08-11-2011
20100030977REGISTER CONTROL CIRCUIT AND REGISTER CONTROL METHOD - A register control circuit that controls a register specified by an inputted address includes a signal output that outputs a first control signal and a second control signal based on the inputted address, a selector that selects data of a register specified by the first control signal outputted from the signal output, a logical operator that performs a logical operation of write data outputted from a processor and the data selected by the selector to output an operation result, and a storage that stores data in the register specified by the first control signal by selecting one of the write data and the operation results as the data based on the second control signal outputted from the signal output.02-04-2010
20100023710SYSTEMS, METHODS, AND APPARATUS FOR SUBDIVIDING DATA FOR STORAGE IN A DISPERSED DATA STORAGE GRID - An efficient method for breaking source data into smaller data subsets and storing those subsets along with coded information about some of the other data subsets on different storage nodes such that the original data can be recreated from a portion of those data subsets in an efficient manner.01-28-2010
20100023708VARIABLE-LENGTH CODE (VLC) BITSTREAM PARSING IN A MULTI-CORE PROCESSOR WITH BUFFER OVERLAP REGIONS - An information handling system includes a multi-core processor that processes variable-length code (VLC) bitstream data. The bitstream data includes multiple codewords that the processor organizes into functionally common subsets. The processor includes a general purpose processor (GPU) and one or more special purpose processor (SPUs). An SPU of the processor may includes two SPU buffers. The processor first transfers bitstream data into GPU buffer memory and then populates the SPU buffers one after another with bitstream data. The SPU buffers may each include an overlap region that the SPU populates with the same bitstream data. The SPU parses the bitstream data in the SPU buffers in alternating fashion. The SPU may shift parsing from the one SPU buffer to the other SPU buffer when parsing reaches a subset boundary within an overlap region.01-28-2010
20100023709ASYMMETRIC DOUBLE BUFFERING OF BITSTREAM DATA IN A MULTI-CORE PROCESSOR - An information handling system includes a multi-core processor that processes variable-length code (VLC) bitstream data. The bitstream data includes multiple codewords for interpretation. The processor includes a general purpose unit (GPU) and a special purpose unit (SPU). The GPU includes GPU buffers and the SPU includes SPU buffers. After populating one GPU buffer with bitstream data, the processor populates another GPU buffer with subsequent bitstream data. The processor may populate the GPU buffers in alternating fashion. The processor populates one SPU buffer with bitstream data while parsing bitstream data in the other SPU buffer. The GPU of the processor populates the SPU buffers in alternating fashion. The size of the GPU buffers may be a multiple of the size of the SPU buffers. After the SPU buffers consume the bitstream data from one GPU buffer, the other GPU buffer transfers its bitstream data to the SPU buffers for parsing.01-28-2010
20080320248Computer system architecture and operating method for the operating system thereof - In order to develop a mobile operating system for a computer, first the mobile operating system must be independent from the computer hardware device. Therefore, the present invention discloses a new computer system architecture which loads a Transient Resident Operating System (TROS) from an external device and provides a predefined hardware device driver to the operating system, and then the TROS can be stored into a portable memory storage device to be a Mobile Operating System (MOS). By applying the technique disclosed in the present invention, the TROS can work beyond the Intrinsic Operating System (IOS) of the computer without the mutual interference from each other, such that a computer environment with a Parasitic Operating System (POS) is created.12-25-2008
20110307670ENCODING DATA INTO CONSTRAINED MEMORY - Encoding data into constrained memory using a method for writing data that includes receiving write data to be encoded into a write word, receiving constraints on symbol values associated with the write word, encoding the write data into the write word, and writing the write word to a memory. The encoding includes: representing the write data and the constraints as a first linear system in a first field of a first size; embedding the first linear system into a second linear system in a second field of a second size, the second size larger than the first size; solving the second linear system in the second field resulting in a solution; and collapsing the solution into the first field resulting in the write word, the write word satisfying the constraints on symbol values associated with the write word.12-15-2011
20110307671Training a Memory Controller and a Memory Device Using Multiple Read and Write Operations - Systems and methods to set a voltage value associated with a communication bus that includes memory controller coupled to a memory device are disclosed. A particular method may include performing a first calibration operation associated with first data written from a memory controller to a memory device. A second calibration operation may be associated with second data read at the memory controller from the memory device. The operating parameter may be set based on a result of at least one of the first and the second calibration operations at the memory device or the memory controller.12-15-2011
20110314234MULTI-CHIP PACKAGE SEMICONDUCTOR MEMORY DEVICE - An MCP type semiconductor memory device having a defective cell remedy function, which enables easy design and manufacture while minimizing chip area increase, is provided. The semiconductor memory device includes memory chips and a memory controller chip that designates an address of a memory chip according to an access request received from outside and controls access to the designated address. Each memory chip includes first and second storage regions and an information holder that holds address information representing associations between addresses in the first and second storage regions. The memory controller chip includes an address translating part that performs, upon receiving a request to access a specific address in the first storage region indicated by the address information, address designation by translating the specific address in the first storage region to an address in the second storage region corresponding to the specific address based on the associations represented by the address information.12-22-2011
20120042138STORAGE SUBSYSTEM AND PERFORMANCE TUNING METHOD - The storage system includes a first storage system and a second storage system. The first storage system, which is coupled to a computer and the second storage system, includes a first storage control device and a plurality of first storage units. The second storage system includes a plurality of second storage units. The first storage control device provides the computer with a logical unit assigned to at least one of the second storage units, receives a first access request from the computer and sends a second access request to one of plurality of the second storage units, obtains performance information relating to the second access request, and moves data stored in at least one of the plurality of second storage units to at least one of the first storage units according to the performance information.02-16-2012
20120042137INFORMATION PROCESSING APPARATUS AND INTERRUPT CONTROL METHOD - A memory stores therein a program status word containing an address of data that is to be read when an interrupt process is executed. a processor determines whether or not the program status word stored in the memory is available, controls the memory to stores a determination result in the memory in association with the program status word, acquires the program status word and the determination result from the memory when the interrupt process occurs, and reads data on the basis of the address contained in the acquired program status word when the acquired determination result indicates that the program status word is available.02-16-2012
20120042136Alignment control - A data processing system 02-16-2012
20120042135Flexible Microprocessor Register File - Architectures and methods for viewing data in multiple formats within a register file. Various disclosed embodiments allow a plurality of consecutive registers within one register file to appear to be temporarily transposed by one instruction, such that each transposed register contains one byte or word from multiple consecutive registers. A program can arbitrarily reorganize the bytes within a register by swapping the value stored in any byte within the register with the value stored in any other byte within the same register. Indirect register access is also provided, without additional scoreboarding hardware, as an apparent move from one register to another. The functionality of a hardware data FIFO at the I/O is also provided, without the power consumption of register-to-register transfers. However, the size of the FIFO can be changed under program control.02-16-2012
20090172312ELECTRONIC DEVICE WITH SERIAL ATA INTERFACE AND POWER SAVING METHOD FOR SERIAL ATA BUSES - In an electronic device with a serial ATA interface, upon detection of the issue or reception of a preset command, a confirmation device, such as a CPU, confirms the completion of execution of the command. Upon confirming the completion of execution of the command, a controller, which may also be the CPU, controls shifting of the serial ATA interface to a power saving mode.07-02-2009
20090172311APPARATUS FOR TESTING MEMORY DEVICE - Embodiments relate to an apparatus that may test a memory device. According to embodiments, a period of memory development may be reduced in a manner of testing a delay of a major part in a memory by adding a simple circuit without using expensive equipment and by which a memory development cost can be lowered. According to embodiments, a memory device may include a memory array and a redundancy memory. According to embodiments, a device may include a programmable redundancy decoder determining a drive force to corresponding to a selection signal, the programmable redundancy decoder outputting the determined drive force to a word line of the redundancy memory and a delay difference generating unit generating a delay difference signal corresponding to a delay difference between first and second word line signals outputted from the redundancy memory.07-02-2009
20090172307STORAGE DEVICE WITH TRANSACTION INDEXING CAPABILITY - In one aspect, a system for indexing transactions over a plurality of communication lines is described. In various embodiments, the system includes a host controller and a plurality of storage devices in communication with one another. Each of the storage devices is configured to store data. The communication lines facilitate communications between the host controller and the plurality of storage devices. A selected one of the storage devices is configured to function as a transaction indexer to monitor the communication lines and index and store selected transaction information associated with operations that occur over the communication lines. While the host controller may be arranged to configure the transaction indexer, the transaction monitoring, indexing and storing are performed substantially automatically by the transaction indexer without requiring further instructions from the host controller.07-02-2009
20090172304Obscuring Memory Access Patterns in Conjunction with Deadlock Detection or Avoidance - Methods, apparatus and systems for memory access obscuration are provided. A first embodiment provides memory access obscuration in conjunction with deadlock avoidance. Such embodiment utilizes processor features including an instruction to enable monitoring of specified cache lines and an instruction that sets a status bit responsive to any foreign access (e.g., write or eviction due to a read) to the specified lines. A second embodiment provides memory access obscuration in conjunction with deadlock detection. Such embodiment utilizes the monitoring feature, as well as handler registration. A user-level handler may be asynchronously invoked responsive to a foreign write to any of the specified lines. Invocation of the handler more frequently than expected indicates that a deadlock may have been encountered. In such case, a deadlock policy may be enforced. Other embodiments are also described and claimed.07-02-2009
20090172302Information Processing Apparatus, Information Processing Method, and Program - The present invention relates to an information processing apparatus, an information processing method, and a program capable of simplifying an interrupt processing and reducing a time necessary to the interrupt processing. An interrupt generation unit 07-02-2009
20120151160VIRTUAL STORAGE SYSTEM AND CONTROL METHOD THEREOF - A virtual storage system is equipped with a plurality of storage systems and a virtualization device for virtualizing the plurality of storage systems logically into a single storage resource provided to a host computer. When one of the storage systems receives a command from the host computer, in the event that the storage system itself is not in possession of a function corresponding to the command, the storage system retrieves a storage system in possession of a function corresponding to the command and transfers this command to the storage system in possession of the function corresponding to the command.06-14-2012
20120047336METHOD OF VERIFYING SYSTEM PERFORMANCE AND PERFORMANCE MEASUREMENT APPARATUS - A computer-readable, non-transitory medium storing a program for measuring a performance in a system including a storage unit and a plurality of control units for controlling an access to the storage unit, the program causing a computer to execute a procedure, the procedure includes estimating a specification area in address information including an address area in which an address of an access target of the storage unit is set and the specification area in which specification information for specifying a control unit for controlling an access to the access target is set, and verifying a reliability of the system by accessing the storage unit on the basis of a specification information in the specification area.02-23-2012
20120047335LOGIC VERIFYING APPARATUS, AND COMPUTER-READABLE RECORDING MEDIUM IN WHICH LOGIC VERIFYING PROGRAM IS STORED - A logic verifying apparatus includes a second processor corresponding to a first processor to be verified; and one or more second controllers corresponding to first controllers to be verified, the number of which is less than that of the first controllers, control a second access to a memory, the access being made by the second processor, the second processor and the second controllers serving as elements in the verification model. The second processor includes a storing unit that stores information that assigns one or more of the second controllers that is to be used as the verification model; and a converting unit that converts a first address into a second address, the first address indicating an entity that the second processor is to access through the one second controller assigned by the information stored in the storing unit such that the second processor access to the memory.02-23-2012
20120210080Data Protection Technique that Protects Illicit Copying of Data Maintained in Data Storage - A data protection program for protecting data to be processed by an application, and a computer including volatile storage means and nonvolatile storage means performs a volatile file unpack function of writing, to the nonvolatile storage means, data corresponding to a data file to be read or written by the application so that the data is associated with the data file; and a volatile file repackage function of outputting the data file corresponding to the data written to the volatile storage means.08-16-2012
20120210081Optimizing Output Vector Data Generation Using A Formatted Matrix Data Structure - A computer system retrieves a packet that includes non-zero elements that correspond to sparse-matrix rows. Within the packet, the non-zero elements are stored in predefined fields that each correspond to one of the sparse-matrix rows. The computer system computes output values to correspond with each of the sparse-matrix rows using the non-zero elements and corresponding input values. In turn, the computer system stores the computed output values in consecutive locations within an output buffer and processes the output values accordingly.08-16-2012
20120210079SEMICONDUCTOR MEMORY DEVICE FOR TRANSFERRING DATA AT HIGH SPEED - A semiconductor memory device includes: a data multiplexing unit configured to output one of a data training pattern and data transferred through a first global input/output line in response to a training control signal; and a latch unit configured to latch an output of the data multiplexing unit to apply and maintain the latched output to a second global input/output line.08-16-2012
20120210075MEMORY MANAGEMENT METHOD, MEMORY CONTROLLER AND MEMORY STORAGE APPARATUS - A memory management method for managing physical units of a rewritable non-volatile memory module is provided. In the method, the physical units are grouped into at least a data area and a free area. The method includes obtaining empty physical units from the free area to configure a first global random area and obtaining empty physical units from the data area to configure a second global random area. The method further includes using the physical units of the first global random area to write updated data, and using the physical units of the second global random area to write other updated data after the physical units of the first global random area are written full of the updated data. Accordingly, the method can increase the storage space of a global random area, and thereby reduces data merging operations and shortens the time for executing a write command.08-16-2012
20120005437Memory Controller for Controlling Write Signaling - A memory controller has an interface to convey, over a first set of interconnect resources: a first command that specifies activation of a row of memory cells, a second command that specifies a write operation directed to the row of memory cells, a bit that specifies whether precharging will occur in connection with the write operation, a code that specifies whether data mask information will be issued in connection with the write operation, and if the code specifies that data mask information will be issued, data mask information that specifies whether to selectively write portions of write data associated with the write operation. The memory controller interface further conveys, over a second set of interconnect resources, separate from the first set of interconnect resource, the write data.01-05-2012
20120005436CONTROL DEVICE, CONTROLLER MODULE, AND CONTROL METHOD - A control device including: a storage device that includes a first storage area including a plurality of blocks into which data can be written more than once and a second storage area into which data can be written only once, wherein the first storage area further stores a flag for each of the blocks, the flag indicating whether or not the block is allowed to be used; a flag management information creation unit configured to create, on the basis of the flag, a flag management information for managing whether or not data can be stored in each block of the storage device; and a management information controller configured to cause the flag management information to be stored in the second storage area.01-05-2012
20120005435MANAGEMENT SYSTEM AND METHODS OF STORAGE SYSTEM COMPRISING POOL CONFIGURED OF ACTUAL AREA GROUPS OF DIFFERENT PERFORMANCES - A storage system comprises multiple virtual volumes (VVOLs) and multiple pools. Each pool is configured of multiple actual area groups of different performances. The storage system accesses actual areas assigned to virtual areas identified by access commands from an access source. A controller manages pool condition information which is the information showing which actual area is assigned to which virtual area and the access load related to the virtual areas. The management system of the storage system comprises management information showing a performance requirement and a performance for each VVOL. The performance of a VVOL is the performance identified with reference to the pool condition information. The management system, with reference to the management information, identifies a VVOL whose condition is inappropriate and, for changing the condition of the identified VVOL from inappropriate to appropriate, performs migration procedure related to the pool made to correspond to the above-mentioned identified VVOL.01-05-2012
20110167230Selecting Storage Locations For Storing Data Based on Storage Location Attributes and Data Usage Statistics - A method for selecting physical storage locations for storing data is provided. The method involves selecting physical storage locations for storing data storage by matching the attributes of the physical storage locations with the usage statistics of the data.07-07-2011
20110167229BALANCED DATA-INTENSIVE COMPUTING - A computing device including a processor operable to process data at a processing speed and a storage device in communication with the processor operable to retrieve stored data at a data transfer rate, where the data transfer rate matches the processing speed.07-07-2011
20110167227Systems and Methods for Updating Detector Parameters in a Data Processing Circuit - Various embodiments of the present invention provide systems and methods for updating detector parameters in a data processing circuit. For example, a data processing circuit is disclosed that includes a first detector circuit, a second detector circuit, and a calibration circuit. The first detector circuit is operable to receive a first data set and to apply a data detection algorithm to the first data set, and the second detector circuit is operable to receive a second data set and to apply the data detection algorithm to the second data set. The calibration circuit is operable to calculate a data detection parameter based upon a third data set. The data detection parameter is used by the first detector circuit in applying the data detection algorithm to the first data set during a period that the data detection parameter is used by the second detector circuit in applying the data detection algorithm to the second data set.07-07-2011
20110167228MEMORY DEVICE AND MEMORY DEVICE CONTROL METHOD - A memory device (07-07-2011
20120011332DATA PROCESSING APPARATUS, METHOD FOR CONTROLLING DATA PROCESSING APPARATUS AND MEMORY CONTROL APPARATUS - A data processing apparatus includes a first memory that has first storage areas, a capacity of each first storage area being variable, a second memory that has second storage areas, a capacity of each second storage area being variable, and each second storage area is redundant to a first storage area corresponding to a second storage area, a memory controller that stores data stored in each first storage area to the corresponding second storage area, and writes data stored in a second storage area to the corresponding varied first storage area and writes data stored in a first storage area to the corresponding varied second storage area when capacities of the first storage area and the second storage areas are varied.01-12-2012
20120011334SSD CONTROLLER, AND METHOD FOR OPERATING AN SSD CONTROLLER - A Solid State Drive (SSD) controller is disclosed. When a data read command is transmitted by a host, the SSD controller may select a representative pointer from at least one first pointer by checking a point in time when data writing is completed in a buffer by at least one memory, read the data from the buffer by referring to a second pointer, and transmit the read data to the host, based on the representative pointer.01-12-2012
20120011333Storage System Construction Managing Device And Construction Management Method - The device of the present invention manages changes in the construction of a storage system in a unified manner, and optimally disposes resources. The servers are logically divided into a plurality of virtual servers, the switches are logically divided into a plurality of zones, and the storage devices are logically divided into a plurality of virtual storage devices. The respective logical devices are respectively managed by respective managing parts. These respective managing parts are connected to a managing device via a network used for management. The managing device re-disposes resources in application program units on the basis o the load states of the respective resources in the storage system.01-12-2012
20120011328ADVANCED FUNCTION MONITORING ON A STORAGE CONTROLLER - An apparatus, system, and method for advanced function monitoring. One embodiment of the apparatus includes an identification module, a detection module, and a monitoring module. The identification module identifies one or more advanced functions for a storage controller. The one or more advanced functions include optional storage functions beyond a standard function set. The detection module detects use of a particular advanced function of the one or more identified advanced functions. The monitoring module monitors the detected use of the particular advanced function on the storage controller according to a monitoring routine.01-12-2012
20120011331MEMORY SYSTEM, CONTROLLER AND DEVICE THAT SUPPORTS A MERGED MEMORY COMMAND PROTOCOL - The present embodiments provide a memory system which is configured to send a request from a memory controller to a memory device, wherein the request includes independent activate and precharge commands. The activate command is associated with a row address, which identifies a first row for the activate command. In response to the activate command, the system activates the first row in a first bank in the memory device. Similarly, in response to the precharge command, the system precharges a second bank in the memory device.01-12-2012
20120011330MEMORY MANAGEMENT APPARATUS, MEMORY MANAGEMENT METHOD, PROGRAM THEREFOR - Provided is a memory management apparatus including a determiner configured to determine whether or not a pattern of writing data being data to be a target of an instruction of writing in a memory is a frequently-appearing pattern, and a setting unit configured to set a shared reference with respect to the writing data having the frequently-appearing pattern in a case where it is determined by the determiner that the pattern of the writing data is the frequently-appearing pattern and data of the frequently-appearing pattern has already been held in the memory.01-12-2012
20120011327MEMORY CHIPS AND MEMORY DEVICES USING THE SAME - A memory chip is provided and includes a control unit, a wait controller, and a wait receiver. When the memory chip operates in an active mode and the control unit determines that the memory chip will be changed to operate in an inactive mode according to an input address signal, the wait controller changes a state of a wait signal at a wait pad from a de-asserted state to an asserted state. When the memory chip operates in an inactive mode and the wait receiver detects that the state of the wait signal has been changed from the de-asserted state to the asserted state, the control unit determines whether the memory chip will be changed to operate in the active mode or a word-line boundary crossing operation will be performed to another memory chip.01-12-2012
20120017051ISOLATION-FREE IN-CIRCUIT PROGRAMMING SYSTEM - Disclosed is an isolation-free in-circuit programming system including an in-circuit programmer and an application board connected to the in-circuit programmer through a peripheral interface bus and having a bus controller and a memory, wherein the bus controller is connected to the memory through a system bus, in which the in-circuit programmer includes a leakage current discharging circuit connected to the bus controller for detouring a leakage current flowing from the memory or the in-circuit programmer to the bus controller to flow therethrough. The in-circuit programmer also includes an input level shifter for receiving data signals from the memory and adjusting the high-level input voltage of the in-circuit programmer to decode any weak high-level output voltage from the memory, thereby allowing the high-level output voltage of the memory to be higher than the high-level input voltage of the in-circuit programmer.01-19-2012
20120017054STORAGE SUB-SYSTEM AND METHOD FOR CONTROLLING THE SAME - The present invention provides means for effectively reducing the amount of data by means of de-duplication in a disk array apparatus having a data guarantee code. A control means for the disk array apparatus that adds a data guarantee code to each logical data block and checks the data guarantee code when reading data has a de-duplication performing function and control means for: generating LA substitution information for a function checking the data guarantee code or read data location address substitution information when performing the de-duplication and storing data; performing the de-duplication using the above-mentioned information when reading data; and thereby avoiding false diagnosis of the data guarantee code check.01-19-2012
20120017053NONVOLATILE MEMORY APPARATUS FOR PERFORMING WEAR-LEVELING AND METHOD FOR CONTROLLING THE SAME - Various embodiments of a nonvolatile memory apparatus are disclosed. In one exemplary embodiment, the nonvolatile memory apparatus may include: a host interface; a memory controller coupled to the host interface; and a memory area including a plurality of chips controlled by the memory controller. The memory controller may be configured to assign logical addresses to the plurality of chips to form a plurality of virtual logical groups, set a plurality of threshold values and a plurality of scan ranges depending on the total erase count (TEC) of each logical group, and perform wear-leveling in stages.01-19-2012
20120017052Information Handling System Universal Memory Wear Leveling System and Method - An information handling system universal memory architecture assigns memory blocks to information handling system functions, such as a persistent storage function and a working storage function, that have different relative rates of writes of information. The blocks are periodically analyzed for remaining memory life to reassign blocks to functions that result in wear leveling across the blocks. For example, blocks having relatively low life remaining that are assigned to functions having a relatively high number of writes have their function switched with blocks that have a relatively high life remaining that are assigned to functions having a relatively low number of writes. In addition, wear leveling performed within a block ensures even wear of the memory cells within the block.01-19-2012
20120023299CONTROLLING APPARATUS AND DATA TRANSMITTING SYSTEM APPLYING THE CONTROLLING APPARATUS AND METHOD THEREOF - A controlling apparatus includes: a storage device arranged for storing at least one Byte Enable property compatible to a processing device; and a controlling circuit coupled to the storage device for generating at least one Byte Enable signal to the processing device according to the Byte Enable property compatible with the processing device.01-26-2012
20120023297USING AN ADD-ON STORAGE DEVICE FOR EXTENDING THE STORAGE CAPACITY OF A STORAGE DEVICE - A storage device with a memory, a controller, a storage device interface and a host interface, and a method of data transfer to and from a storage device are provided. The storage device is operative to connect with a host device and the storage device interface is operative to couple with an add-on memory. When the host interface is connected to a host device, the controller is configured to receive a data transfer command specifying a memory address from the host interface; and if the memory address is beyond the address space of the memory, to route the data transfer command to the storage device interface for access to the add-on memory. The address space of the memory and an address space of the add-on memory are addressed as one integral address space transparently to the host.01-26-2012
20120060004SYSTEM FOR VIRTUAL DISKS VERSION CONTROL03-08-2012
20120060003MEMORY CONTROL CIRCUIT, MEMORY CONTROL METHOD, AND INTEGRATED CIRCUIT - Each of a plurality of memories includes a terminating resistor for preventing signal reflection, and a memory control circuit includes an ODT control circuit for driving the terminating resistor of each memory, and a selector for selecting, from memories except for a memory to be accessed, at least one memory for which driving of the terminating resistor is to be suppressed, in accordance with the memory to be accessed.03-08-2012
20120060000SYSTEM AND METHOD FOR FLEXIBLY STORING, DISTRIBUTING, READING, AND SHARING ELECTRONIC BOOKS - An electronic book card includes a communication interface that can communicate with a host reading device having a display device configured to display images in a display configuration. The communication interface can receive the display configuration from the host reading device. A non-volatile memory can store content of an electronic book. A data processing unit can generate page images in accordance with the display configuration of the display device. The page images incorporate the content of the electronic book.03-08-2012
20120059999METHODS AND SYSTEMS FOR STORING VARIABLE WIDTH STACK ELEMENTS IN A SINGLE MEMORY STACK - A system and method for storing variable width stack elements in a single memory stack is disclosed. In one example embodiment a first variable width stack element is split into one or more sub-elements. The width of the sub-elements may be less than or equal to a width of the single memory stack. A first memory pointer is created for providing an address of a first read pointer in the single memory stack. The first read pointer may provide an address corresponding to a first sub-element of the first variable width stack element. The first sub-element is written in a first available location in the single memory stack. A write pointer of the single memory stack is incremented when the first sub-element is written to the first available location on the single memory stack. The steps of writing and incrementing are repeated for a next sub-element until all of the sub-elements are stored in the single memory stack.03-08-2012
20080276052METHOD FOR ACCESSING MEMORY - A method for accessing a memory is provided. The method includes entering a memory accessing mode for updating a top of low memory (TOLM) value stored in a TOLM register in a chipset of a system with a highest memory address when a memory accessing command is received. The memory accessing command requests the utilization of a memory block in a memory of the system corresponding to an address space occupied by a memory-mapped input output (MMIO) function. The system then accesses the corresponding memory block in the memory according to the address space recorded in the memory accessing command. After the access is completed, the memory accessing mode is closed and the original TOLM value is written back to the TOLM register. Therefore, the present invention can access the “MMIO memory block” to prevent a waste of the memory.11-06-2008
20120117338METHOD AND SYSTEM FOR SYNCHRONIZING ADDRESS AND CONTROL SIGNALS IN THREADED MEMORY MODULES - A memory system includes a memory module which further includes a set of memory devices. The set of memory devices includes a first subset of memory devices and a second subset of memory devices. An address bus is disposed on the memory module, wherein the address bus includes a first segment coupled to the first subset and a second segment coupled to the second subset. An address signal traverses the set of memory devices in sequence. The memory system also includes a memory controller which is coupled to the memory module. The memory controller includes a first circuit to output a first control signal that controls the first subset, such that the first control signal and the address signal arrive at a memory device in the first subset at substantially the same time. The memory controller additionally includes a second circuit to output a second control signal that controls the second subset, such that the second control signal and the address signal arrive at a memory device in the second subset at substantially the same time.05-10-2012
20120117337SEMICONDUCTOR INTEGRATED CIRCUIT AND EXPONENT CALCULATION METHOD - Provided is a semiconductor integrated circuit and an exponent calculation method that, when normalizing a plurality of data by a common exponent, speed up exponent calculation and reduce circuit scale and power consumption. When normalizing a plurality of data by a common exponent, a semiconductor integrated circuit calculates the exponent of the plurality of data. Included is a bit string generator that generates a second bit string containing bits having a transition value indicating that values of adjacent bits are different or a non-transition value indicating that values of adjacent bits are not different for each pair of adjacent bits of a first bit string constituting the data, and an exponent calculator that calculates the exponent of the plurality of data based on bit position of the transition value of a plurality of second bit strings generated from a plurality of first bit strings respectively constituting the plurality of data.05-10-2012
20120117336CIRCUITS AND METHODS FOR PROVIDING DATA TO AND FROM ARRAYS OF MEMORY CELLS - A memory device uses a global input/output line or a pair of complementary global input/output lines to couple write data signals and read data signals to and from a memory array. The same input/output line or pairs of complementary global input/output lines may be used for coupling both write data signals and read data signals.05-10-2012
20120060001MEMORY LIFETIME GAUGING SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT - Techniques are taught for reducing writes, and estimating and displaying estimated remaining lifetime of non-volatile memories. The write reducing is optionally via determining a difference between write operation results and data stored in the non-volatile memories. The estimated remaining lifetime is optionally based at least in part on a previous lifetime. The displaying is optionally via a gauge.03-08-2012
20120059998BIT MASK EXTRACT AND PACK FOR BOUNDARY CROSSING DATA - An apparatus having a first circuit and a second circuit is disclosed. The first circuit may be configured to generate a plurality of packed items by extracting-and-packing a plurality of input data words based on a bit mask. The second circuit may be configured to (i) receive the packed items from the first circuit, (ii) sequentially buffer the packed items in a plurality of registers, at least one of the packed items crossing a boundary between a current one of the registers and a next one of the registers, and (iii) write the packed items in the current register to a memory in response to the current register becoming full.03-08-2012
20120060002SYSTEM AND METHOD FOR PROVIDING DATA REDUNDANCY AFTER REDUCING MEMORY WRITES - A storage subsystem receives writes from a computer via a standard storage subsystem interface. The storage subsystem reduces a number of the writes. A single drive of the storage subsystem has primary and redundant storage devices with storage device interfaces. A disk controller of the single drive implements a data redundancy scheme by storing data associated with the reduced number of writes in the primary storage devices and by storing computed redundancy information in the redundant storage devices. The disk controller is operable without a loss of data in the presence of at least a single failure of any of the storage devices. Optionally the storage devices are flash memory devices. Optionally the disk controller is operable without a loss of data in the presence of at least two failures of any of the storage devices when a number of the redundant storage devices is at least two.03-08-2012
20120159093METHOD AND APPARATUS FOR DATA TRANSFER - A method and apparatus for data transfer includes receiving a first data packet across a first bi-directional bus and receiving a second data packet across a second bi-directional bus. Next, the first data packet is written to a first register operably coupled to the first bi-directional bus and the second bi-directional bus. The second data packet is written to a second register operably coupled to the first bi-directional bus and the second bi-directional bus. The second data packet is then transferred across the first bi-directional bus and the first data packet is transferred across the second bi-directional bus, thereby providing data transfer across a plurality of bi-directional buses and providing for data to be transferred across those buses to be stored at an intermediate register so that the data may be transferred in the next clock cycle, overcoming any latency requirements.06-21-2012
20120159091DIRECTED GRAPHS PERTAINING TO READ/WRITE OPERATIONS - A system comprises a processor and storage containing software executable by the processor. The storage also contains a trace log that contains information pertaining to read and write operations and, for each read and write operation, the information is indicative of a start time, a completion time, and a value targeted by the read or write operation, Based on the trace log, the software causes the processor to construct a directed graph comprising nodes as well as edges interconnecting at least some of the nodes, each node representing a read or write operation and determine whether the constructed directed graph has a cycle. At least one edge is at least one of a data edge representing a data precedence between operations and a time edge representing a time precedence between operations, and at least one edge is a hybrid edge representing both time and data precedence between operations.06-21-2012
20120210077RECORDING SYSTEM, RECORDING METHOD AND COMPUTER PROGRAM - A recording system includes a controller configured to write content data on at least first and second storage media, in parallel with each other. If there is a period in which the content data has failed to be written on the first storage medium but has been written successfully on the second storage medium, the controller finds, on the first storage medium, a storage space, of which the size is equal to or greater than that of partial data that is the content data that has been written successfully on the second storage medium during the period, and writes recovery information on one or more storage media other than the first storage medium. The recovery information includes some pieces of information to identify the first storage medium, to specify the storage space, and to define an area on the second storage medium on which the partial data has been written.08-16-2012
20120210078ARBITER, STORAGE DEVICE, INFORMATION PROCESSING DEVICE AND COMPUTER PROGRAM PRODUCT - According to an embodiment, an arbiter is for arbitrating accesses to a first memory and a second memory from a first device having a cache memory for temporarily storing data and a second device. The arbiter includes a first writing unit configured to write data requested to be written by the second device into the second memory; and a notifying unit configured to notify the first device of completion of writing the data into the second memory.08-16-2012
20120210076USER DEVICE PERFORMING DATA RETENTION OPERATION, STORAGE DEVICE AND DATA RETENTION METHOD - Disclosed is a method of operating a data storage device. The method includes; causing the data storage device to transition from an off-line state to an on-line state, receiving a current global time as communicated from a host during the on-line state, and during the on-line state, refreshing data stored in the data storage device in response to the current global time using at least one normal data retention operation.08-16-2012
20120072679Reordering in the Memory Controller - In an embodiment, a memory controller includes multiple ports. Each port may be dedicated to a different type of traffic. In an embodiment, quality of service (QoS) parameters may be defined for the traffic types, and different traffic types may have different QoS parameter definitions. The memory controller may be configured to scheduled operations received on the different ports based on the QoS parameters. In an embodiment, the memory controller may support upgrade of the QoS parameters when subsequent operations are received that have higher QoS parameters, via sideband request, and/or via aging of operations. In an embodiment, the memory controller is configured to reduce emphasis on QoS parameters and increase emphasis on memory bandwidth optimization as operations flow through the memory controller pipeline.03-22-2012
20120072678Dynamic QoS upgrading - In an embodiment, a memory controller includes multiple ports. Each port may be dedicated to a different type of traffic. In an embodiment, quality of service (QoS) parameters may be defined for the traffic types, and different traffic types may have different QoS parameter definitions. The memory controller may be configured to scheduled operations received on the different ports based on the QoS parameters. In an embodiment, the memory controller may support upgrade of the QoS parameters when subsequent operations are received that have higher QoS parameters, via sideband request, and/or via aging of operations. In an embodiment, the memory controller is configured to reduce emphasis on QoS parameters and increase emphasis on memory bandwidth optimization as operations flow through the memory controller pipeline.03-22-2012
20120072682DETECTION CIRCUIT FOR MIXED ASYNCHRONOUS AND SYNCHRONOUS MEMORY OPERATION - A memory access mode detection circuit and method for detecting and initiating memory access modes for a memory device The memory access mode detection circuit receives the memory address signals, the control signals, and the clock signal and generates a first mode detection signal in response to receipt of the memory address signals or a first combination of control signals. An first mode initiation signal is generated a time delay subsequent to the detection signal to initiate the first mode memory access operation. In response to receipt of a second combination of control signals and an active clock signal, the memory access mode detection circuit further generates a second mode detection signal to initiate a second mode memory access operation and to suppress generation of the first mode detection signal, thereby canceling the first mode memory access operation.03-22-2012
20120110284DATA PROCESSING APPARATUS, DATA PROCESSING METHOD, AND PROGRAM - The present invention relates to a data processing apparatus, a data processing method, and a program that are configured to prevent (or lower) the increase in scale and cost of the apparatus.05-03-2012
20120072680SEMICONDUCTOR MEMORY CONTROLLING DEVICE - According to one embodiment, a semiconductor memory controlling device includes a write control unit that writes a predetermined number of pieces of first data and redundant information calculated by using the predetermined number of pieces of the first data and used for correcting an error in the first data into different semiconductor storage drives, respectively; a constructing unit that constructs a storage area for storing therein a table by using driver information, the table showing an association between a logical address and a physical address of the first data and identification information for associating the predetermined number of pieces of first data with the redundant information; and a table controlling unit that stores, into the storage area, the table associated with the identification information, the physical address and the logical address of the predetermined number of pieces of the first data, and a physical address of the redundant information.03-22-2012
20110066816NON-VOLATILE MEMORY DEVICE ADAPTED TO IDENTIFY ITSELF AS A BOOT MEMORY - Non-volatile memory devices and methods of their operation are provided. One such non-volatile memory device has an interface and a control circuit. The non-volatile memory device is adapted to identify itself as a boot memory in response to receiving an interrogation request on the interface.03-17-2011
20110066815MEMORY ACCESS CONTROL DEVICE AND MEMORY ACCESS CONTROL METHOD - A memory access control device includes an input data control unit, a processing unit, and an output data control unit. The input data control unit inputs image data from a memory. The processing unit subjects the input image data to a preset process. The output data control unit outputs the processed image data to the memory.03-17-2011
20120110280OUT-OF-ORDER LOAD/STORE QUEUE STRUCTURE - The present invention provides a method and apparatus for supporting embodiments of an out-of-order load/store queue structure. One embodiment of the apparatus includes a first queue for storing memory operations adapted to be executed out-of-order with respect to other memory operations. The apparatus also includes one or more additional queues for storing memory operation in response to completion of a memory operation. The embodiment of the apparatus is configured to remove the memory operation from the first queue in response to the completion.05-03-2012
20110107039METHODS FOR IMPLEMENTATION OF DATA FORMATS ON A REMOVABLE DISK DRIVE STORAGE SYSTEM - An archiving system including one or more removable disk drives embedded in removable disk cartridges, referred to simply as removable disk drives. The removable disk drives allow for expandability and replacement such that the archiving system need not be duplicated to add new or more storage capacity. In embodiments, the removable disk drives store metadata that contain information about the data stored on the removable disk drive. The metadata allows the system to retrieve the correct data from the random access memory and establishes controls on the data stored on the removable disk drive. In embodiments, the metadata is stored in two locations, such that, if the metadata in one location is corrupted, the second copy of the metadata may be retrieved.05-05-2011
20110107038MEMORY MANAGEMENT PROGRAM AND APPARATUS - A memory management apparatus includes: a memory space including a memory area serving as a heap area and a non-heap-area memory area; and memory management unit which add a header for an object to a memory area other than heap-area to treat the non-heap-area memory area as a mock object in order to treat a plurality of heap areas divided by the non-heap-area memory area as a single continuous heap area.05-05-2011
20100095073System for Controlling Performance Aspects of a Data Storage and Access Routine - A system for controlling one or more aspects of a data storage and access routine incorporates a filter driver residing on a digital storage medium internal to or accessible to a host computing system; and a configuration interface residing on the digital storage medium. The interface enables reservation of an amount of memory for accelerating processes of data access and data storage and wherein the filter driver monitors data read and data write requests and processes those requests allowed through configuration and according to configured parameters.04-15-2010
20110099339INFORMATION PROCESSING APPARATUS, METHOD FOR CONTROLLING INFORMATION PROCESSING APPARATUS AND STORAGE MEDIUM - The information processing apparatus of the present invention comprises a control unit configured to control such that part of a storage region of the second storage unit is used as a virtual storage region for the first storage unit when the information processing apparatus is operating in the first mode, and part of a storage region of the third storage unit is used as the virtual storage region for the first storage unit when the information processing apparatus is operating in the second mode.04-28-2011
20110099338DATA MANAGEMENT SYSTEM AND METHOD - The present invention relates to a data management system and method for storing a plurality of data records (04-28-2011
20090132770Data Cache Architecture and Cache Algorithm Used Therein - The present invention provides a data cache architecture interposed between a host and a flash memory, the data cache architecture comprising: a buffer memory, receiving data from the host; a memory controller, deploying the data in the buffer memory; and a data cache memory, controlled by the memory controller according to a cache algorithm. The data cache architecture and the cache algorithm used in the data cache architecture can be used to minimize the program/erase count of the NAND type flash device.05-21-2009
20120124303METHOD AND SYSTEM FOR TRANSFORMATION OF LOGICAL DATA OBJECTS FOR STORAGE - There are provided a method of transforming a non-transformed stored logical data object (LO) device into a transformed LO and system thereof. The method comprises: a) in response to a respective transformation request, logically dividing the non-transformed LO in a first segment and one or more non-transformed subsequent segments, the segments having predefined size; b) generating a header for the respective transformed LO; c) processing said first segment; d) overwriting said first segment by said generated header and said transformed first segment; e) indexing said first transformed segment and said one or more non-transformed subsequent segments as constituting a part of said transformed LO; f) generating at least one index section; and g) updating the indication in the header to point that the non-transformed LO has been transformed in the transformed LO comprising said generated header, said first transformed segment, said one or more subsequent segments comprising data in non-transformed form and said at least one index section.05-17-2012
20120124302SOLID STATE STORAGE SYSTEM FOR UNIFORMLY USING MEMORY AREA AND METHOD CONTROLLING THE SAME - A solid state storage system includes a memory area having a plurality of pages and is capable of storing program information about each page. The memory area stores the number of pulse counts applied to each page. A main memory controller receives the program information from the memory area and determines whether to program pages according to the program information. The main memory controller determines whether the program information for a page is at a predetermined amount and if the corresponding page should be programmed again or not.05-17-2012
20120124301Buffer store with a main store and an auxiliary store - A loop buffer is provided with a main store 05-17-2012
20120124300Apparatus and method for predicting target storage unit - A data processing apparatus comprises processing circuitry and a plurality of storage units. When the processing circuitry executes a data access instruction, then a storage controller identifies based on a target storage address of the data access instruction, which of the storage units includes the target storage location identified by the target storage address. Prediction circuitry is provided to predict a predicted storage unit predicted to include the target storage location, so that retrieval of the data value from the predicted storage unit can be initiated before the storage controller has identified the target storage unit. The prediction circuitry makes the prediction based on the type of the data access instruction executed by the processing circuitry.05-17-2012
20120166741DATA BUS FOR LOW POWER TAG - A power supply and communication system comprising a single-wire data bus, itself having comprising a source end and a termination end, the termination end being connected to ground through a resistance of less than 10Ω. A circuit is connected at the termination end, between the single-wire data bus and ground, and the circuit comprises means for deriving its supply voltage and receiving input data from a time-variant signal applied to the single-wire data bus.06-28-2012
20120317377DUAL FLASH TRANSLATION LAYER - A method for operating a memory includes receiving memory access commands associated with respective target logical addresses, for execution in a memory. The target logical addresses are translated into respective intermediate logical addresses, in accordance with a first mapping having a first granularity of a first data unit size. The intermediate logical addresses are translated into respective physical storage locations in the memory, in accordance with a second mapping having a second granularity of a second data unit size, larger than the first data unit size. The memory access commands are executed in the memory in accordance with the respective physical storage locations.12-13-2012
20120221808SHARED SINGLE-ACCESS MEMORY WITH MANAGEMENT OF MULTIPLE PARALLEL REQUESTS - A memory is used by concurrent threads in a multithreaded processor. Any addressable storage location is accessible by any of the concurrent threads, but only one location at a time is accessible. The memory is coupled to parallel processing engines that generate a group of parallel memory access requests, each specifying a target address that might be the same or different for different requests. Serialization logic selects one of the target addresses and determines which of the requests specify the selected target address. All such requests are allowed to proceed in parallel, while other requests are deferred. Deferred requests may be regenerated and processed through the serialization logic so that a group of requests can be satisfied by accessing each different target address in the group exactly once.08-30-2012
20120221806INFORMATION PROCESSING APPARATUS, METHOD FOR CONTROLLING SAME - An information processing apparatus processes data to be processed while accessing data to be processed that is stored in a memory or a HDD. The information processing apparatus determines the process content and calculates the access number to the HDD based on the determined process content and the content of data to be processed. The information processing apparatus also decides to store data to be processed in the memory when the access number is more than or equal to a threshold value. The information processing apparatus decides to store data to be processed in the HDD when the access number is less than the threshold value.08-30-2012
20120221807DATA CONTROL SYSTEMS FOR VIRTUAL ENVIRONMENTS - A data control system comprises a communication interface, a processing system, and a storage system. The communication interface is configured to receive a request to retrieve data from a primary storage volume that includes a secondary storage volume. The storage system is configured to store the primary storage volume that includes the secondary storage volume. The processing system is configured to identify changed segments of a plurality of segments in the primary storage volume and identify allocated segments of the changed segments. The communication interface is further configured to transfer the allocated segments in response to the request.08-30-2012
20120221805Method for managing physical memory of a data storage and data storage management system - A method is provided managing physical memory of a data storage, for example, a heap. The method includes requesting a memory portion having a memory portion size and identifying a pool. The pool is provided for storing at least one access information indicative of an address of a memory block of the data storage. The memory block has a memory block size equal to or larger than the memory portion size. The method further includes determining whether the access information is stored in the pool. If the access information is stored in the pool, address data of the memory block is returned, wherein the address data are based on the access information, and access information is removed from the pool. If the access information is not stored in the pool, the access information is created, and address data of the memory block is returned.08-30-2012
20120221803HIGH PERFORMANCE DATA STORAGE USING OBSERVABLE CLIENT-SIDE MEMORY ACCESS - In one example, a system is provided that performs memory access operations on a storage volume stored in memory and identifies the memory access operations performed. A request to perform a memory access operation may be received at a communication interface. The request may comply with a memory access protocol. The memory access operation may be performed on a portion of the memory in response to the request, where the portion of the memory is included in the storage volume. One or more attributes of the memory access operation may be identified. An action related to the memory access operation may be performed based on the attribute of the memory access operation.08-30-2012
20120131288Reconfigurable Integrated Circuit Architecture With On-Chip Configuration and Reconfiguration - The exemplary embodiments provide a reconfigurable integrated circuit capable of on-chip configuration and reconfiguration, comprising: a plurality of configurable composite circuit elements; a configuration and control bus; a memory; and a sequential processor. Each composite circuit element comprises: a configurable circuit; and an element interface and control circuit, the element interface and control circuit comprising an element controller and at least one configuration and control register to store one or more configuration and control words. The configuration and control bus is coupled to the plurality of configurable composite circuit elements, and comprises a plurality of address and control lines and a plurality of data lines. The sequential processor can write configurations to the configuration and control registers of an addressed configurable composite circuit element to configure or reconfigure the configurable circuit.05-24-2012
20120131287STORAGE CONTROL APPARATUS AND LOGICAL VOLUME SIZE SETTING METHOD - The present invention efficiently changes a volume size while maintaining a copy pair as-is. A PVOL and a SVOL #05-24-2012
20120131286DYNAMIC DETECTION AND REDUCTION OF UNALIGNED I/O OPERATIONS - Detection and reduction of unaligned input/output (“I/O”) requests is implemented by a storage server determining an alignment value for data stored by the server within a storage system on behalf of a first client, writing the alignment value to a portion of the volume that stores the data for the first client, but not to a portion of the volume that stores data for a second client, and changing a location of data within the portion of the volume that stores the data for the first client, but not a location of data in the portion of the volume that stores data for the second client, to an alignment corresponding to the alignment value. The alignment value is applied to I/O requests directed to the portion of the volume that stores the data blocks for the first client after the location of the data blocks has been changed.05-24-2012
20120166743DETERMINING AN END OF VALID LOG IN A LOG OF WRITE RECORDS - Provided are a method, computer program product and system for determining an end of valid log in a log of write records. Records are written to a log in a storage device in a sequential order, wherein the records include a next pointer addressing a next record in a write order and a far ahead pointer addressing a far ahead record in the write order following the record. The far ahead pointer and the next pointer in a plurality of records are used to determine an end of valid log from which to start writing further records.06-28-2012
20120166742System and Method for Contention-Free Memory Access - A memory control unit of a turbo code decoder includes a buffer having a plurality of storage slots, a buffer control operatively coupled to the buffer, a router operatively coupled to the buffer control and to a plurality of data sources, and a conflict detection unit operatively coupled to the router, to the buffer control, and to the plurality of data sources. The buffer temporarily stores information intended for storage in a memory bank. The buffer control determines a number of available storage slots in the buffer. The router routes data from the data sources to the buffer control. The conflict detection unit initiates a temporary halt of some of the data sources when the number of available storage slots is insufficient to store all of the data from data sources attempting to access the memory bank.06-28-2012
20120166740DATA WRITING METHOD, MEMORY CONTROLLER, AND MEMORY STORAGE APPARATUS - A data writing method for a rewritable non-volatile memory module is provided. The method includes receiving at least one update data, wherein the update data belongs to at least one logical page of a first logical block, and the first logical block is mapped to a first physical block. The method also includes when a physical page of a second physical block that is corresponding to the logical page already stores data, selecting a third physical block from a free area, writing the update data into the third physical block, serving the third physical block as the child physical block of the first physical block, and executing an erasing operation on the second physical block, wherein the second physical block is currently a child physical block of the first physical block. Thereby, the method can effectively reduce the number of operations for merging data and increase the data writing speed.06-28-2012
20100241815Hybrid Storage Device - In one embodiment, a hybrid storage device including a persistent memory, a volatile memory, a processor, a memory loader module that enables the processor to load a first set of information from the persistent memory device to the volatile memory device, to organize the first set of information according to a predetermined format, and a storage drive interface controller that enables the processor to receive information access requests from a host computer, to provide a second set of information from the volatile memory device to the host computer, and to provide a metadata descriptive of the first set of information to the host computer is disclosed. A host computer is enabled to access the first set of information using metadata provided by the storage drive interface controller without having the first set of information in a local memory of the host computer. The time required to access the first set of information is reduced by having the first set of information in volatile memory in the hybrid storage device. Other embodiments include, a system having a host computer and a hybrid storage device and methods using a hybrid storage device in a host computer.09-23-2010
20120317375STORE STORAGE CLASS MEMORY INFORMATION COMMAND - An abstraction for storage class memory is provided that hides the details of the implementation of storage class memory from a program, and provides a standard channel programming interface for performing certain actions, such as controlling movement of data between main storage and storage class memory or managing storage class memory.12-13-2012
20120317373STORAGE APPARATUS AND METHOD OF CONTROLLING STORAGE APPARATUS - Efficient data processing is implemented by using the functions of an external storage apparatus which is connected to the virtual storage apparatus.12-13-2012
20120215996WRITE DATA MASK METHOD AND SYSTEM - In various embodiments, dedicated mask pins are eliminated by sending a data mask on address lines of the interface. A memory controller receives a request for a memory write operation from a memory client and determines the granularity of the write data from a write data mask sent by the client. Granularity, as used herein, indicates a quantity of write data to which each bit of the received write data mask applies. In an embodiment, the memory controller generates a particular write command and a particular write data mask based on the granularity of the write data. The write command generated is typically the most efficient of several write commands available, but embodiments are not so limited. The write command is transmitted on command lines of the interface, and the write data mask is transmitted on address lines of the interface.08-23-2012
20120215992Sorting - Systems and techniques are disclosed that include in one aspect a computer implemented method storing a received stream of data elements in a buffer, applying a boundary condition to the data elements stored in the buffer after receiving each individual data element of the stream of data elements, and producing one or more data elements from the buffer based on the boundary condition as an output stream of data elements sorted according to a predetermined order.08-23-2012
20120215995PREEMPTIVE IN-PIPELINE STORE COMPARE RESOLUTION - A computer-implemented method that includes receiving a plurality of stores in a store queue, via a processor, comparing a fetch request against the store queue to search for a target store having a same memory address as the fetch request, determining whether the target store is ahead of the fetch request in a same pipeline, and processing the fetch request when it is determined that the target store is ahead of the fetch request.08-23-2012
20120215994STORAGE MANAGEMENT SYSTEM FOR PRESERVING CONSISTENCY OF REMOTE COPY DATA - A storage control system adapted to operate as a remote copy pair by communicating between a primary and a secondary of the remote copy pair comprises a selector for selecting writes to be placed in a batch based on one or more criteria, a sequence number requester for requesting a sequence number for the batch, and a sequence number granter for granting a sequence number for the batch. The storage control system also comprises a batch transmitter for transmitting the batch to the secondary, a permission receiver for receiving a permission to write the batch from the secondary, and a write component responsive to the permission receiver to write the batch to completion, wherein the secondary is responsive to the completion to grant a further permission to write for a further batch.08-23-2012
20120215993INFORMATION PROCESSING APPARATUS AND METHOD OF CONTROLLING THE SAME - A first nonvolatile storage device has a higher access speed in a continuous access than a random access and a second nonvolatile storage device has a higher access speed in the random access than the continuous access. The information processing apparatus selects a first storage method in which an amount of continuous data is larger than an amount of random data if data stored in a volatile storage device is saved in the first nonvolatile storage device, and selects a second storage method in which an amount of random data is larger than an amount of continuous data if the data stored in the volatile storage device is saved in the second nonvolatile storage device, and saves the data stored in the volatile storage device into the specified nonvolatile storage device using the selected storage method when a predetermined condition is satisfied.08-23-2012
20100205386Memory controller and memory control method - In order to provide a memory controller capable of calibrating a memory access timing even in a case where an application has no blanking interval, the memory controller includes: a delay circuit (08-12-2010
20100205384Store Hit Load Predictor - In one embodiment, a processor implements a store hit load predictor. The store hit load predictor is configured to monitor fetched ops in the processor, and is configured to detect stores that may have previously caused store hit load events. The store hit load predictor is configured to predict that the store will cause a store hit load event again, and is further configured to monitor subsequent fetched ops for the load. The store hit load predictor may locate the load using, e.g., an offset from the store to the load in the code sequence. In response to locating the load, the store hit load predictor may create a dependency of the load on the store, preventing the load from executing out of order with respect to the store. A store hit load event may be avoided in this fashion, at least in some cases.08-12-2010
20100205388METHOD AND SYSTEM FOR SCALABLE VIDEO DATA WIDTH - Processing data samples may comprise partitioning the data samples in a first set of data bits and a second set of data bits and utilizing at least some of the first and second set of data bits while operating under a first condition. Only at least some of the first set of data bits may be utilized while operating under a second condition. The first condition may be a normal operating condition, while the second condition may be a performance restricted condition. The first set of data bits may be more significant bits and the second set of bits may be less significant bits. At least some of the first and second set of data bits may be utilized while bandwidth is available. Under the second condition, other values may be substituted for the data values from the second set that were not read in a read operation.08-12-2010
20120137086NON-TRANSITORY MEDIUM, ACCESS CONTROL METHOD, AND INFORMATION PROCESSING APPARATUS - A file server has a conversion table that stores therein, in a corresponding manner, logical addresses specified by a higher-level layer and physical addresses specified by a disk driver that are address information indicative of a storage area in a disk device. The file server accesses the disk device with a storage area indicated by a physical address as an access destination and counts up the number of access requests to each storage area in a given period of time for each of the logical addresses. The file server then updates the conversion table such that the physical addresses are lined up in a descending order of the logical addresses of a higher number of the access requests counted. Thereafter, the file server changes storage areas of data stored in the storage device based on the conversion table updated.05-31-2012
20120137084SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR MEMORY SYSTEM INCLUDING THE SAME - A semiconductor memory device includes: an internal clock signal generation unit configured to generate an internal clock signal in response to an external clock signal; an internal data strobe signal generation unit configured to generate an internal data strobe signal in response to an external data strobe signal; a phase comparison unit configured to compare phases of the internal clock signal and the internal data strobe signal that are used in an enabled write path in response to an internal dummy write command with each other; and an output unit configured to output an output signal of the phase comparison unit.05-31-2012
20120137088ELECTRONIC COMPONENT - An electronic component is provided having a plurality of functionalities. The electronic component comprises a control logic, and a non-volatile storage element. The control logic is coupled to the non-volatile storage element and is adapted for storing values in the non-volatile storage element based on an external input signal to the electronic component, each value being indicative for one or more functionalities of the plurality of functionalities. The control logic is adapted for controlling the availability of the plurality of functionalities based on one or more values stored in the non-volatile storage element and for outputting a confirmation signal being indicative for the availability of the plurality of functionalities.05-31-2012
20120137087STORAGE AREA MANAGEMENT APPARATUS FOR MANAGING STORAGE AREAS PROVIDED FROM UPPER APPARATUSES, AND CONTROL METHOD AND STORAGE MEDIUM THEREFOR - A storage area management apparatus capable of preventing a particular one or ones of storage units of upper apparatuses from being concentratedly accessed, thereby equalizing remaining lifetimes of the storage units. The management apparatus is connected to upper apparatuses through a network, computes lifetime values representing lifetimes of provided areas respectively provided from the storage units of the upper apparatuses, and controls the upper apparatuses based on the computed lifetime values such that provided areas having longer remaining lifetimes are used for data storage with higher priorities.05-31-2012
20110185132METHOD AND SYSTEM FOR STORING MEMORY COMPRESSED DATA ONTO MEMORY COMPRESSED DISKS - In a computer system supporting memory compression and wherein data is stored on a disk in a different compressed format, and wherein an IOA (input/output adaptor)/IOP (input/output processor) selectively reads from and writes to a main memory through a direct memory access (DMA) operation, a method for transmitting compressed data from the IOA/IOP to the main memory includes reserving a set of free memory sectors to contain the data in said main memory, sending to the IOA/IOP addresses of said memory sectors, copying the data from the IOA/IOP to said memory sectors using said DMA operation, constructing at the IOA/IOP compressed memory directory information defining how and where the data is stored in memory, sending the memory directory information to a memory controller, and storing the memory directory information in the compressed memory directory structure.07-28-2011
20110185131RECORDING CONTROL DEVICE - A recording control device includes: an interface unit 07-28-2011
20110185130COMPUTER SYSTEM AND STORAGE CONSOLIDATION MANAGEMENT METHOD - In order to properly use resources according to the application or search for available resources in an environment in which a block storage apparatus and a file storage apparatus coexist, knowledge and experience of applications and storage apparatuses, as well manpower were required. Thus, a policy pre-defined with a preferred type of interface and a preferred type of storage area for each type of application that is loaded in the host computers is predetermined, configuration information is collected from each storage apparatus, each intermediate storage apparatus and each host computer, respectively, a combination of a storage apparatus, an intermediate storage apparatus and a host computer that is suitable for the type of application designated by a user is detected based on the collected configuration information of each storage apparatus, each intermediate storage apparatus and each host computer, the policy, and the type of application designated by the user, and the detected combination is presented to the user.07-28-2011
20100174876MEMORY MANAGEMENT METHOD, INFORMATION PROCESSING DEVICE, PROGRAM CREATION METHOD, AND PROGRAM - Provided is a method for managing a memory storage region used by a processor. The processor is connected to the memory that stores data accessed while a task is being executed. The memory management method including the steps of: dividing the memory area of the memory into blocks having a plurality of different sizes; selecting a block having a size matching a size of the data accessed while the task is being executed; and storing the data accessed while the task is being executed in the selected block.07-08-2010
20120221802Multiplex Restore Using Next Relative Addressing - According to one embodiment of the present disclosure, a method for multiplex restore using next relative address may be provided. The method may include identifying an address of a first data chunk of a file stored on a storage device. The first data chunk may be read by accessing the storage device at the address of the first data chunk. A next relative address appended to the first data chunk may be identified. The next relative address may indicate a position of a next chunk. The next chunk may comprise a next data chunk of the file or an empty chunk associated with the file. The method may further include reading the next chunk by accessing the storage device at the position indicated by the next relative address.08-30-2012
20120254558MEMORY SYSTEM INCLUDING VARIABLE WRITE COMMAND SCHEDULING - A system includes a host device that may be configured to initiate memory requests to a system memory. The system also includes a memory controller that may be configured receive the memory requests and to format the memory requests into memory transactions that are conveyed to the memory device via a memory interface. The memory transactions include a plurality of memory write command types. Each memory write command type corresponds to a different respective schedule for conveying a corresponding data payload.10-04-2012
20120254557MOBILE TERMINAL, MEMORY CARD SOCKET AND METHOD OF WRITING PROTECTION FOR MEMORY CARD IN THE MOBILE TERMINAL - The present invention provides a mobile terminal, a memory card socket and a method of writing protection for a memory card in the mobile terminal. The mobile terminal comprising a memory card socket accommodating a pluggable memory card, the memory card socket externally provided with a metal shielding structure; the mobile terminal further comprising: a touch capacitance sensor connected to the metal shielding structure of the memory card socket and configured to sense a capacitance via the metal shielding structure; and a write control unit configured to determine whether the metal shielding structure is touched by a finger based on the capacitance sensed by the touch capacitance sensor, and prohibit data being written into the memory card when it is determined that the metal shielding structure is touched by a finger. The present invention ensures that the data can be safely written into the memory card.10-04-2012
20120317374SRAM Multiplexing Apparatus - An SRAM multiplexing apparatus comprise a plurality of local multiplexers and a global multiplexer. Each local multiplexer is coupled to a memory bank. The global multiplexer has a plurality of inputs, each of which is coupled to a corresponding output of the plurality of local multiplexers. In response to a decoded address in a read operation, an input of a local multiplexer is forwarded to a corresponding input of the global multiplexer. Similarly, the decoded address allows the global multiplexer to forward the input signal to a data out port via a buffer.12-13-2012
20120173827APPARATUS, SYSTEM, AND METHOD FOR USING MULTI-LEVEL CELL STORAGE IN A SINGLE-LEVEL CELL MODE - A controller is used for an electronic memory device which has multi-level cell (MLC) memory elements. Each MLC memory element is capable of storing at least two bits. The controller includes a physical interface to couple the controller to the electronic memory device. The controller also includes a processing unit coupled to the physical interface. The processing unit operates the electronic memory device in a single-level cell (SLC) mode using a restricted number of programming states for a single data bit. The restricted number of programming states includes a first state which is an erase state. The restricted number of programming states also includes a second state, other than the erase state, which is closest to a natural threshold voltage of the MLC memory elements.07-05-2012
20120254554COMPUTER SYSTEM AND COMPUTER SYSTEM MANAGEMENT METHOD - A computer system in which one or more host computers 10-04-2012
20120221801STORAGE CONTROL APPARATUS AND OPERATING MODE CONTROL METHOD OF STORAGE CONTROL APPARATUS - It is an object to improve a reliability of a data protection for a storage control apparatus that is provided with a redundant configuration that is made of a plurality of clusters. A memory unit in each of the clusters C08-30-2012
20090172301INTELLIGENT NETWORK INTERFACE CARD (NIC) OPTIMIZATIONS - Intelligent NIC optimizations includes system and methods for Token Table Posting, use of a Master Completion Queue, Notification Request Area (NRA) associated with completion queues, preferably in the Network Interface Card (NIC) for providing notification of request completions, and what we call Lazy Memory Deregistration which allows non-critical memory deregistration processing to occur during non-busy times. These intelligent NIC optimizations which can be applied outside the scope of VIA (e.g. iWARP and the like), but also support VIA.07-02-2009
20100299488DYNAMIC MEMORY ACCESS METHOD AND MEMORY CONTROLLER - A dynamic memory access method includes following steps. First, many data access commands are received. Each of the data access commands accesses a dynamic memory according to a page address and a bank address. Next, whether an access data to be accessed by the corresponding data access command is an instantaneous data or a non-instantaneous data is determined. Then, the page and bank addresses of each of the data access commands are respectively compared with a previously page and bank addresses at a previous time used for accessing the dynamic memory, such that an address hit status is obtained. Next, a service sequence is generated according to whether each of the data access commands is an instantaneous or instantaneous data and the address hit status of the commands. Finally, each of the data access commands is executed to access the dynamic memory sequentially according to the service sequence.11-25-2010
20100274979STORAGE CONTROLLERS WITH DYNAMIC WWN STORAGE MODULES AND METHODS FOR MANAGING DATA AND CONNECTIONS BETWEEN A HOST AND A STORAGE DEVICE - A method and system for transferring data between a host and a Serial Attached Small Computer Interface (“SAS”) device using a storage controller is provided. The storage controller includes, a World Wide Name (“WWN”) module that includes a table having plural entries, wherein each row includes a WWN address, an initiator tag value field, an input/output counter value that tracks plural commands for a connection. A WWN index value represents the address of a row having plural entries. The method includes, comparing frame elements of incoming frames, including a unique WWN address with the WWN module entries; and if there is a match, updating a counter value for a connection between the storage controller and a device sending frames. The counter value is increased when a command frame is received and decreased when a command is executed and a response is sent to the device.10-28-2010
20100274978IMAGING APPARATUS - By connecting to or mounting a first storage medium that stores image data as a retrieval object (e.g. first memory card 10-28-2010
20100274977Data Accessing Method And Apparatus For Performing The Same - The present invention discloses a data accessing method and an apparatus for performing the method. Through a newly-defined host logical unit (HLUN), a unique HLUN number is given to each LUN-to-LD/Partition mapping relationship, and the HLUN is present to external hosts. Therefore, all of the hosts in the same storage system may recognize different logical units (i.e., HLUN). Hence, when processing an Input/Output (IO) request issued from any one host, a storage virtualization controller (SVC) can correctly find the corresponding LD/Partition for accessing data without identifying the identity of the host.10-28-2010
20100274976Method of operating data storage device and device thereof - The method of operating the data storage device includes performing channel distribution non-sequentially based on a logical address included in a data signal and outputting a channel address, and at least one of writing data to and reading stored data from a memory connected to one of a plurality of channels based on the channel address.10-28-2010
20090013135UNORDERED LOAD/STORE QUEUE - A method and processor for providing full load/store queue functionality to an unordered load/store queue for a processor with out-of-order execution. Load and store instructions are inserted in a load/store queue in execution order. Each entry in the load/store queue includes an identification corresponding to a program order. Conflict detection in such an unordered load/store queue may be performed by searching a first CAM for all addresses that are the same or overlap with the address of the load or store instruction to be executed. A further search may be performed in a second CAM to identify those entries that are associated with younger or older instructions with respect to the sequence number of the load or store instruction to be executed. The output results of the Address CAM and Age CAM are logically ANDed.01-08-2009
20100011173Downgrade Memory Apparatus, and Method for Accessing a Downgrade Memory - A method for accessing a downgrade memory and a downgrade memory apparatus are provided. The downgrade memory apparatus comprises at least one management unit and a controller. The management unit comprises a plurality of blocks, each block having a plurality of pages, and each page having a plurality of sectors, the downgrade memory having a plurality of non-accessible sectors. The controller is configured to parse a write command corresponding to a special block, to select at least one accessible sector according to a status information of the special block and to program the write command to the special block, wherein the status information indicates at least one non-accessible sector in the special block. Thereby the method and the apparatus of downgrade memory may as well omit the non-accessible sectors as enhance the usage memory capacity in accordance with the status information.01-14-2010
20100011175SEMICONDUCTOR INTEGRATED CIRCUIT AND ACCESS CONTROLLING METHOD OF SEMICONDUCTOR MEMORY - An area detection unit detects a main rectangular area to which an access start address indicated by one-dimensional access information is included among main rectangular areas corresponding to two-dimensional access information. An address conversion unit divides the detected main rectangular area into sub rectangular areas, detects a sub rectangular area to which the access start address indicated by the one-dimensional access information is included, and converts the one-dimensional access information into first two-dimensional access information based on a relative position of the sub rectangular area being detected. A memory controller receives the first and second two-dimensional access information, and converts the two-dimensional access information into an access address. Accordingly, a modification of a memory controller accessing a semiconductor memory by receiving the two-dimensional access information becomes unnecessary. As a result, existing design properties can be effectively utilized, and a development period of a system can be reduced.01-14-2010
20100011174MIXED DATA RATES IN MEMORY DEVICES AND SYSTEMS - Mixed data rates in a memory system is disclosed. The system includes at least one semiconductor memory device and another device defining a ring topology. The semiconductor memory device includes input circuitry for receiving a clock signal having a frequency at least substantially equal to a frequency x. A first set of circuit elements are each clocked by a same or respective first internal signal having a frequency at least substantially equal to the frequency x. A second set of circuit elements are each clocked by a same or a respective second internal signal having a frequency at least substantially double that of the frequency x.01-14-2010
20120233415METHOD AND APPARATUS FOR SEARCHING FOR DATA IN MEMORY, AND MEMORY - The invention provides a method and apparatus for searching for data in a memory. The memory includes at least two storage areas, each storage area includes at least two storage blocks, and storage blocks in each storage area are corresponding to each other. The method includes: determining whether a hit storage block that matches with data to be searched for exists in a current storage area; and if it is determined that the hit storage block exists, searching for a storage block corresponding to the hit storage block in a next storage area, so as to determine whether a hit storage block further exists. Accordingly, a storage block corresponding to a missed storage block may execute no operation, thus reducing power consumption.09-13-2012
20120233413METHODS OF ACCESSING MEMORY CELLS, METHODS OF DISTRIBUTING MEMORY REQUESTS, SYSTEMS, AND MEMORY CONTROLLERS - Methods of accessing memory cells, methods of distributing memory requests, systems, and memory controllers are described. In one such method, where memory cells are divided into at least a first region of memory cells and a second region of memory cells, memory cells in the first region are accessed according to a first address definition and memory cells in the second region are accessed according to a second address definition that is different from the first address definition. Additional embodiments are described.09-13-2012
20110107040Adaptable External Drive - In one embodiment a network attached storage device comprises a detection module to detect, in the network attached storage device, the connection of an external storage media to the network attached storage device, a format module to initiate, in the network attached storage device, a format utility, and configure the external storage media with at least a primary partition and a secondary partition.05-05-2011
20120254561INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, AND PROGRAM - An information processing apparatus (10-04-2012
20120254560SYSTEM AND METHOD FOR STORING AND RETRIEVING EQUIPMENT INSPECTION AND MAINTENANCE DATA - An inspection and maintenance data storage and retrieval system features memory buttons each mounted in association with an equipment item, with each memory button having a read-write memory and an associated unique identifier. Inspection and maintenance data relating to the equipment item is stored in a remote central database. A memory button probe is used in conjunction with a portable computer to write data to and to read data from the memory buttons' read-write memories. The portable computer transfers data from the memory button probe to the central database at the point of inspection or maintenance, and vice versa. Information relating to each inspection and maintenance task may be downloaded to the central database computer via the portable computer. The central database computer may be a network server providing authorized users with access to current maintenance and operational status information for the equipment items supported by the system.10-04-2012
20120317376ROW BUFFER REGISTER FILE - A memory controller of a device stores data from each of a plurality of row buffers of a multiple-bank memory device in a corresponding entry of a row buffer register file (RBRF) provided in a logic/interface layer of the memory device. The memory controller serves a first memory request from an entry in the RBRF responsive to determining that the entry stores data from a first row buffer associated with the first memory request.12-13-2012
20100293342DATA PROCESSING APPARATUS - Apparatus comprises a processor configured for operation under a sequence of instructions from an instruction set, wherein said processor comprises: means for conditionally inhibiting at least one type of trap, interrupt or exception (TIE) event, wherein, when operating under a sequence of instructions, said inhibition means is inaccessible by said instructions to inhibit the or each type of TIE event, without interrupting said sequence. A data processing apparatus includes a processor adapted to operate under control of program code comprising instructions selected from an instruction set, the apparatus comprising: a predefined memory space providing a predefined addressable memory for storing program code and data, a larger memory space providing a larger addressable memory, means for accessing program code and data within the predefined memory space, and means for controlling the access means so as to enable the access means to access program code located within the larger memory space.11-18-2010
20120185654SEMICONDUCTOR APPARATUS AND SEMICONDUCTOR SYSTEM INCLUDING RANDOM CODE GENERATION CIRCUIT, AND DATA PROGRAMMING METHOD - A semiconductor apparatus includes a plurality of linear feedback shift registers configured to receive a plurality of seed codes as initial values and generate respective random codes under a control of a clock signal, a code combination section configured to logically combine the plurality of random codes generated by the plurality of linear feedback shift registers and generate a final random code, and a data conversion unit configured to convert input data based on the final random code and output conversion data.07-19-2012
20120226875STORAGE CONTROL APPARATUS - A storage unit is provided with a plurality of sub storage units configured to include a plurality of hard disk drives, an enclosure, a printed wiring board, a power supply device, and a cable holder. The sub storage units each operate separately. The enclosure is provided in the array of the hard disk drives so that the distance can be shorter between the enclosure and each of the hard disk drives. With the provision of the cable holder, communications cables can be both brought closer to the printed wiring board. With such a configuration, the coupling point among the communications cables and the printed wiring board, and the enclosure can be favorably reduced. The resulting storage control apparatus can be mounted with a larger number of storage devices, thereby being able to maintain good signal quality.09-06-2012
20120260048REPRODUCING DEVICE AND REPRODUCING METHOD - A reproducing device includes: a storage unit in which data is accumulated; a program control unit controlling first and second programs respectively generating an acquisition request of the data accumulated in the storage unit and generating the acquisition request of the data, which is different from the first program; and a read control unit managing the data on a file basis, selecting one of first and second algorithms in which the file is read using a method suitable for reading the data by the first program and in which the file is read using a method suitable for reading the data by the second program based on storage position information of the file designated in the data acquisition request when the data acquisition request is inputted from the program control unit, and performing readout of the data from the storage unit based on the selected first or second algorithm.10-11-2012
20120260047GENERALIZED POSITIONAL ORDERING - Implementations described and claimed herein provide a method and system for managing execution of commands for a storage device, the method comprising determining a plurality of commands to be executed for the storage device and while a storage device is executing at least one command, determining an execution order for at least two of the plurality of commands. Alternate implementation described and claimed herein provide a computer readable memory for storing a data structure, the data structure comprising a cost table comprising a number of cells, each cell containing one or more cost values related to one of a plurality of traversals between two locations on a storage device wherein each of the plurality of traversals is related to completion of one of a plurality of commands and a benefit array comprising a number of cells, each cell containing a benefit value related to completion of one of the plurality of commands.10-11-2012
20120239887METHOD AND APPARATUS FOR MEMORY CONTROL - A method is provided for issuing subcommands to a memory module using unassigned bits in a memory control protocol. A buffer component within the memory module receives the subcommands and modifies a state of the memory module accordingly. This allows, for example, selectively powering down individual ranks of the memory module (e.g., an LRDIMM memory module). Unassigned bits in a JEDEC-compliant ZQ calibration command set may be used for implementing such subcommands.09-20-2012
20090019241STORAGE MEDIA STORING STORAGE CONTROL PROGRAM, STORAGE CONTROLLER, AND STORAGE CONTROL METHOD - A computer to runs access control to a plurality of storage areas by;01-15-2009
20120233414SHORT POINTERS - A digital processor stores pointers of different sizes in memory. The processor, specifically, executes instructions to store a long or short pointer. Long pointers reference any address in the memory's logical address space, while short pointers merely reference any address in a subset of that space. However, short pointers are smaller in size as stored in memory than long pointers. Long pointers thus support relatively large address range capabilities, while short pointers use less memory. The processor also executes instructions to load a long or short pointer into the register file, and does so in a way that does not require the processor to distinguish between the different pointers when executing other instructions. Specifically, the processor converts long and short pointers into a common format for loading into the register file, and converts pointers in the common format back into long or short pointers for storing in the memory.09-13-2012
20080301382Storage system construction managing device and construction management method - The device of the present invention manages changes in the construction of a storage system in a unified manner, and optimally disposes resources. The servers are logically divided into a plurality of virtual servers, the switches are logically divided into a plurality of zones, and the storage devices are logically divided into a plurality of virtual storage devices. The respective logical devices are respectively managed by respective managing parts. These respective managing parts are connected to a managing device via a network used for management. The managing device re-disposes resources in application program units on the basis of the load states of the respective resources in the storage system.12-04-2008
20080301381DEVICE AND METHOD FOR CONTROLLING COMMANDS USED FOR FLASH MEMORY - A method and device for controlling commands used for a flash memory are provided. The method includes, substantially reducing usage of a central processing unit (CPU) and a bus, when controlling the flash memory, by receiving information on at least one command currently stored in a system memory, receiving a command represented by the received information from the system memory, and generating an interrupt representing that all the commands are received, when receiving of substantially all the commands represented by the received information is completed.12-04-2008
20120265949SEMICONDUCTOR MEMORY SYSTEM - According to one embodiment, a semiconductor memory system includes semiconductor memories, and a memory controller configured to control the semiconductor memories. Each of the semiconductor memories is configured to execute an internal sequence including operations and have a wait period after an end of each of the operations, to notify, during the wait period, a status signal, which notifies in advance a start of a next operation, to the memory controller, and to start the next operation upon receiving a restart instruction of the internal sequence from the memory controller.10-18-2012
20120265948EMULATING A SKIP READ COMMAND - In an embodiment, a skip read command is received that requests transfer of a requested block from a storage device and that requests non-transfer of a skipped block from the storage device. The skip read command specifies a skip mask that comprises an identification of a location of the requested block relative to a location of the skipped block at the storage device. In response to the skip read command, the requested block and the skipped block are transferred from the storage device by creating a read command that requests transfer of the requested block and the skipped block and sending the read command to the storage device. In various embodiments, the skipped block is transferred to a temporary buffer and not transferred to a destination buffer, or the skipped block is transferred to the destination buffer, but overwritten by a transfer of the requested block to the destination buffer.10-18-2012
20120265947LIGHTWEIGHT RANDOM MEMORY ALLOCATION - In response to a memory allocation request received from an application thread, a random number is obtained (e.g., from a random number list previously populated with multiple random numbers). A starting location in at least a portion of a bitmap associated with a region including multiple blocks of the memory is determined based on the random number. A portion of the bitmap is scanned, beginning at the starting location, to identify a location in the bitmap corresponding to an available block of the multiple blocks, and an indication of this available block is returned to the application thread.10-18-2012
20120265946BYPASSING USER MODE REDIRECTION - In one embodiment, a non-transitory processor-readable medium stores code associated with a function module included in a resource library. The code can represent instructions that when executed cause a processor to define, in response to a function hook associated with the function module, a copy of the resource library, the copy of the resource library including an unhooked copy of the function module. The code can further represent instructions that when executed cause the processor to execute the unhooked copy of the function module based on at least one policy from a plurality of policies.10-18-2012
20120265950Storage Card Socket, Mobile Terminal and Method for Protecting the Storage Card - A storage card socket, mobile terminal and method for protecting the storage card, the storage card socket comprising: a first contact point on the base of the storage card socket; a second contact point on the base of the storage card socket, the second contact point electrically connected to the first contact point after the upper lid of the storage card socket is closed; and a guide slot on the base of the storage card socket, the guide slot being positioned at a side of a connecting part connecting the base and the upper lid, the connecting part being positioned in the guide slot so that the upper lid is slidable along the guide slot.10-18-2012
20120265951WIDE BANDWIDTH READ AND WRITE MEMORY SYSTEM AND METHOD - A memory device includes a first memory array, a first read port, a second read port, and a control input port. The first memory array contains a plurality of memory cells arranged in an array configuration. The first read port is configured to read first data from a single memory cell during a single read cycle, and the second read port is configured to read second data from a group of memory cells controlled by a common word line. Further, the control input is configured to receive a mode signal indicating a functional mode for the memory device including a first read mode and a second read mode. When the mode signal indicates the first read mode, the first read port is used to read the first data. When the mode signal indicates the second read mode, the first read port is used to read out the first data and the second read port is used to read the second data.10-18-2012
20110131384SYSTEMS AND METHODS FOR INTEGRATING STORAGE RESOURCES FROM STORAGE AREA NETWORK IN MACHINE PROVISIONING PLATFORM - Embodiments relate to systems and methods for integrating storage resources from a storage area network in a machine provisioning platform. A provisioning platform can communicate generate and maintain a provisioning profile encoding the software, hardware, and/or other resources to be provisioned to a target physical and/or virtual machine. The provisioning profile can include a set of storage allocations for each target machine to be provisioned by the platform, indicating the high-level amounts, types, availability, so forth to be associated with each target. The provisioning profile can likewise include a set of storage specifications indicating specific disk types, manufacturers, and specific sources or pools in the set of storage resources available to the storage area network to transparently fulfill the storage allocations. The target(s) can be assigned an alias to identify them to the SAN, and the provisioning platform can mount the corresponding storage resources during the provisioning or updating process.06-02-2011
20120239889METHOD AND APPARATUS FOR WRITING DATA IN MEMORY SYSTEM - A method of writing data in a memory system comprises determining a characteristic of write data and generating characteristic information according to the determined characteristic, generating a write command corresponding to the write data, and sending the write command, the characteristic information, and the write data to the memory system.09-20-2012
20120239888STORAGE APPARATUS AND CONTROLLING METHOD OF STORAGE APPARATUS - A storage apparatus including: a first controller that generates an access to a storage device; the first controller includes: a first relay unit configured to relay the access to the storage device; and an access control unit configured to be activated after activation of the first relay unit and to relay the access to the storage device via a second relay unit; and a second controller that includes the second relay unit and generates the access to the storage device, wherein when the first relay unit receives a connection request for an access path between the first relay unit and the storage device from the second controller, the first relay unit establishes the access path to the storage device irrespective of an activation state of the access control unit.09-20-2012
20120265952DATA COMMUNICATING APPARATUS AND METHOD FOR MANAGING MEMORY OF DATA COMMUNICATING APPARATUS - An IC card has a mechanism to securely manage information for each of a plurality of service providers in a memory area of the IC card. The IC card is shared by the plurality of service providers.10-18-2012
20110047338SELF-LEARNING MAP ON BASIS ON ENVIRONMENT SENSORS - A self-learning map or a device for creating and storing a digital map for a transport unit on the basis of environmental sensors, vehicle-to-X communication and satellite navigation systems. The self-learning map and device create and store the digital map without the use of data from navigation maps. The obtained digital map is iteratively improved and can be used for the validity check of an existing digital map for a driver assistance system.02-24-2011
20110047337METHOD AND DEVICE FOR DETECTING A STATISTICAL CHARACTERISTIC OF A LIGHTING DEVICE - The present invention relates to a method for detecting a static index of a lighting device (02-24-2011
20120272019SCHEDULING READ OPERATIONS DURING DRIVE RECONSTRUCTION IN AN ARRAY OF REDUNDANT DISK DRIVES - Some embodiments of the present invention provide a system that schedules read operations for disk drives in a set of disk drives. During operation, the system monitors a write rate for write operations to a given disk drive in the set of disk drives, wherein vibrations generated by the read operations directed to disk drives in the set of disk drives are transmitted to the given disk drive. Then, the read operations for disk drives in the set of disk drives are scheduled based on the write rate for the given disk drive, thereby limiting interference between the write operations and the vibrations generated by the read operations.10-25-2012
20120272018STORAGE DEVICE, HOST APPARATUS, CIRCUIT SUBSTRATE, LIQUID CONTAINER, AND SYSTEM - A storage device includes a control unit that performs a process of communicating with a host apparatus which is connected to the storage device through a bus, a storage unit into which data transmitted from the host apparatus are written, and a storage control unit that performs access control on the storage unit. The control unit receives an ID information item from the host apparatus after the end of a period of writing data from the host apparatus to m (m is an integer equal to or greater than 1) storage devices of a plurality of the storage devices connected to the bus, and returns an acknowledgement to the host apparatus if the data transmitted from the host apparatus have been successfully written to the storage unit of the storage device.10-25-2012
20120272017NONVOLATILE MEMORY DEVICE AND NONVOLATILE MEMORY SYSTEM AND RANDOM DATA READ METHOD THEREOF - A random data reading method of a nonvolatile memory device includes receiving an initial seed corresponding to a selected page of the nonvolatile memory device and relative location information of read-requested random data in the selected page. The method further includes generating a seed for randomizing the random data by subjecting the initial seed and the location information to a finite field arithmetic operation, and de-randomizing the random data based on a random sequence generated from the seed.10-25-2012
20120272016MEMORY AFFINITIZATION IN MULTITHREADED ENVIRONMENTS - A method, system, and computer program product for memory affinitization in a multithreaded environment are provided in the illustrative embodiments. A first affinity domain formed in a computer receives from a second thread executing in a second affinity domain a request to access a unit of memory in the first affinity domain. The computer determines whether to migrate the unit of memory to the second affinity domain. The computer migrates, responsive the determining being affirmative, the unit of memory to the second affinity domain, thereby affinitizing the unit of memory with the second thread.10-25-2012
20120324177APPARATUS AND METHOD FOR ACCESSING NETWORK MEMORY - In one embodiment, the apparatus includes a media access control (MAC) processor and a memory controller. The MAC processor is connected to a physical layer of the network, parses a frame received from the physical layer, and outputs a memory command. The memory controller outputs first data received from the network to the network memory or second data output from the network memory to the network according to the memory command.12-20-2012
20120324178DATA STORAGE SYSTEM HAVING MULTI-BIT MEMORY DEVICE AND ON-CHIP BUFFER PROGRAM METHOD THEREOF - Disclosed is an on-chip buffer program method for a data storage device which comprises a multi-bit memory device and a memory controller. The on-chip buffer program method includes measuring a performance of the data storage device, judging whether the measured performance satisfies a target performance of the data storage device, and selecting one of a plurality of scheduling manners as an on-chip buffer program scheduling manner of the data storage device according to the judgment result.12-20-2012
20120324174Multi-Port Register File with an Input Pipelined Architecture and Asynchronous Read Data Forwarding - In an embodiment of the invention, a multi-port register file includes write port inputs (e.g. write address, write enable, data input) that are pipelined and synchronous and read port inputs (e.g. read address) that are asynchronous and are not pipelined. Because the write port inputs are pipelined, they are stored in pipelined registers. When data is written to the multi-port register file, data is first written to the pipelined registers during a first clock cycle. On the next clock cycle, data is read from the pipelined registers and written into memory array registers. When the read address is identical to the write address stored in the pipelined memory, the result of a bit-wise ANDing of data stored in pipelined synchronous data registers and data stored in pipelined synchronous bit-wise registers is presented at the output of the multi-port register file.12-20-2012
20110161605Memory devices and methods of operating the same - A memory device includes a memory cell. The memory cell includes: a bipolar memory element and a bidirectional switching element. The bidirectional switching element is connected to ends of the bipolar memory element, and has a bidirectional switching characteristic. The bidirectional switching element includes: a first switching element and a second switching element. The first switching element is connected to a first end of the bipolar memory element and has a first switching direction. The second switching element is connected to a second end of the bipolar memory element and has a second switching direction. The second switching direction is opposite to the first switching direction.06-30-2011
20120324176STORAGE ALLOCATION BASED ON DATA SET SIZE - An approach to allocating storage that has track managed storage and cylinder managed storage. The approach involves receiving a request to allocate a data set for new data and determining if the size of the new data exceeds a breakpoint value. The size of the new data may be determined by allocating a buffer data set that is the size of the breakpoint value, and writing the new data to the buffer data set. If the new data only partially fills the buffer data set, then the size of the new data is smaller than the breakpoint value. If the new data overfills the buffer data set, then the size of the new data set is larger than the breakpoint value. New data that is larger than the breakpoint value is automatically stored in cylinder managed storage, while new data that is smaller than the breakpoint value is automatically stored in track managed storage.12-20-2012
20120324175Multi-Port Register File with an Input Pipelined Architecture with Asynchronous Reads and Localized Feedback - In an embodiment of the invention, a multi-port register file includes write port inputs (e.g. write address, write enable, data input) that are pipelined and synchronous and read port inputs (e.g. read address) that are asynchronous and are not pipelined. Because the write port inputs are pipelined, they are stored in pipelined registers. When data is written to the multi-port register file, data is first written to the pipelined registers during a first clock cycle. On the next clock cycle, data is read from the pipelined registers and written into memory array registers. Which bits of data from a pipelined synchronous data register are written into the multi-port register file is determined by a pipelined synchronous bit-write register. The output of the pipelined synchronous bit-write register selects which inputs of multiplexers contained in registers in the multi-port register file are stored.12-20-2012
20110238933MEMORY DEVICE AND CONTROLLING METHOD OF THE SAME - A memory device includes a memory which has memory areas, and a controller has a first mode and a second mode. Upon receipt of write data, the controller writes data in the memory areas while managing correspondence between logical addresses of write data and memory areas which store corresponding write data. A plurality of the memory areas constitutes a management unit. The controller in the first mode is able to write pieces of data in respective memory areas and configured to maintain data in memory areas in one management unit which contains data to be updated. The controller in the second mode writes pieces of data in respective memory areas in the ascending order of logical addresses of the pieces of data and invalidates data in memory areas in one management unit which contains updated data.09-29-2011
20110238932CONTROLLER AND METHOD FOR OPERATING A CONTROLLER, COMPUTER PROGRAM, COMPUTER PROGRAM PRODUCT - In a controller, a method for operating a controller, a computer program, and a computer program product, data are saved in a memory, a setpoint is defined, an actual value is identified, the actual value is compared with the setpoint, and the data is saved as a function of the comparison result.09-29-2011
20110238931MEMORY DEVICE, MEMORY SYSTEM AND MICROCONTROLLER INCLUDING MEMORY DEVICE, AND MEMORY CONTROL DEVICE - A memory device includes: a plurality of word lines and bit lines specifying addresses to be accessed; and a plurality of memory cells of consecutive addresses arranged to correspond to each of the word lines. The plurality of memory cells of the consecutive addresses are accessible in parallel by the plurality of bit lines each corresponding to one of the memory cells. Among the plurality of word lines, a first word line and a second word line that specifies an address next to that of the first word line have an overlapping address range, and a first memory cell connected to the first word line and a second memory cell connected to the second word line are assigned in dual fashion to a same address.09-29-2011
20110238929LIBRARY APPAPRATUS AND METHOD FOR CONTROLLING THE SAME - A library apparatus includes a medium name storage unit that stores medium name conversion information in which a virtual medium name specifying a storage medium in a read/write request from a host is related to a real medium name specifying the storage medium in the library apparatus, a conveying mechanism unit that conveys the storage medium, a drive that reads/writes data from/to the storage medium conveyed by the conveying mechanism unit in response to the received read/write request, a conversion unit that converts the virtual medium name included in the received read/write request to the real medium name on the basis of the medium name conversion information stored in the medium name storage unit, and a conveying mechanism control unit that controls the conveying mechanism unit to convey the storage medium having the real medium name converted by the conversion unit to the drive.09-29-2011
20120278563MEMORY DEVICE AND MEMORY SYSTEM - A memory device having at least one memory including a first memory. The first memory includes a core area having a data storage unit that is non-volatile and a peripheral circuit area having an input/output circuit. The data storage unit of the first memory stores setting information about a memory controller corresponding to the first memory.11-01-2012
20120278562BRANCH CIRCUIT MONITOR WITH PAGING REGISTER - The quantity of data stored in a branch circuit monitor and accessible by a data processing network is increased by logically dividing the monitor's memory into a plurality of registers each comprising a plurality of pages and addressing a page containing the desired data with an address corresponding to the identity of a page number stored in a page register and the identity of the register.11-01-2012
20120278561COMPUTER SYSTEM AND CONTROL METHOD OF THE COMPUTER SYSTEM - To create one pool by using a plurality of storage apparatuses and to provide virtual volumes common to each of the storage apparatuses to the server.11-01-2012
20120089792EFFICIENT IMPLEMENTATION OF ARRAYS OF STRUCTURES ON SIMT AND SIMD ARCHITECTURES - One embodiment of the present invention sets forth a technique providing an optimized way to allocate and access memory across a plurality of thread/data lanes. Specifically, the device driver receives an instruction targeted to a memory set up as an array of structures of arrays. The device driver computes an address within the memory using information about the number of thread/data lanes and parameters from the instruction itself. The result is a memory allocation and access approach where the device driver properly computes the target address in the memory. Advantageously, processing efficiency is improved where memory in a parallel processing subsystem is internally stored and accessed as an array of structures of arrays, proportional to the SIMT/SIMD group width (the number of threads or lanes per execution group).04-12-2012
20120089791HANDLING STORAGE PAGES IN A DATABASE SYSTEM - An operation is disclosed for handling storage pages in a database system. The database system may include a management component and a storage component. The storage component may include storage locations with different hierarchical levels. Each storage page of the storage pages may include a number of records. The operation may include copying a storage page from the storage component to a buffer pool controlled by the management component, monitoring which records of the storage page in the buffer pool are being accessed, and setting information indicating access for each record accessed. The operation may also include determining, based on the information indicating access, whether to split the storage page into at least two resulting storage pages. The operation may also include writing the at least two resulting storage pages to the storage component at storage locations, where the at least two resulting storage pages have different hierarchy levels.04-12-2012
20120089790STORAGE DEVICE AND METHOD FOR ACCESSING DATA USING THE SAME - A method for accessing data using a storage device determines if a data writing request is received from a first data processing device by a first interface of the storage device, and stores a document corresponding to the data writing request into a storage area of the storage device when the data writing request is received by the first interface.04-12-2012
20120089789Memory Controllers, Systems and Methods for Applying Page Management Policies Based on Stream Transaction Information - Memory controllers, systems, methods, and computer-readable mediums for applying a page management policy(ies) based on stream transaction information are disclosed. In one embodiment, a memory controller is provided and configured to receive memory access requests for stream transactions. The memory controller is configured to perform a memory access to a memory page(s) in memory included in the stream transaction. The controller is further configured to apply a page management policy(ies) to the memory page(s) in memory based on information related to the stream transactions. In this manner, the page management policy(ies) can be configured to utilize page open policies for efficiency that stream transactions may facilitate, but while also recognizing and taking into consideration in the page management policy latency issues that can arise when the memory controller is handling memory access requests from different devices.04-12-2012
20110276768I/0 COMMAND HANDLING IN BACKUP - Systems and methods for input/output command management. In some cases of a write command received from a host, a maximum capacity limit relating to primary memory may be disregarded because data relating to the write command is written to backup memory prior to acknowledging the write command. In some of these cases, timeout is less likely than if the maximum capacity limit had been respected.11-10-2011
20110276767Rate Matching and De-Rate Matching on Digital Signal Processors - Provided are systems and methods for rate matching and de-rate matching on digital signal processors. For example, there is a system for rate matching and de-rate matching, where the system includes a memory configured to contain a plurality of blocks of data, and a digital signal processor configured to pre-compute permutation parameters common to the plurality of blocks, wherein the plurality of blocks are subject to a set of given puncturing parameters. The digital signal processor is configured to process each block in the plurality of blocks by computing a block signature from pre-computed puncturing thresholds, matching the block signature to one of a set of pre-computed zone signatures, deriving a zone index corresponding to the one matched pre-computed zone signature, and applying pre-computed permutation and puncturing transformations corresponding to the zone index to the block.11-10-2011
20120331245Virtualizing Storage for WPAR Clients - Systems, methods and media for providing to a plurality of WPARs private access to physical storage connected to a server through a VIOS are disclosed. In one embodiment, a server is logically partitioned to form a working partition comprising a WPAR manager and individual WPARs. Each WPAR is assigned to a different port. The virtual ports are created by using NPIV protocol between the WPAR and VIOS. Thereby, each WPAR has private access to the physical storage connected to the VIOS.12-27-2012
20120331246Virtualizing Storage for WPAR Clients Using Node Port ID Virtualization - Systems, methods and media for providing to a plurality of WPARs private access to physical storage connected to a server through a VIOS are disclosed. In one embodiment, a server is logically partitioned to form a working partition comprising a WPAR manager and individual WPARs. Each WPAR is assigned to a different virtual port. The virtual ports are created by using NPIV protocol between the WPAR and VIOS. Thereby, each WPAR has private access to the physical storage connected to the VIOS.12-27-2012
20090089515Memory Controller for Performing Memory Block Initialization and Copy - A memory controller and methods for performing memory block initialization and copy functions with reduced bus traffic are disclosed. The memory controller can perform the memory initialization by receiving a start address of a memory, an end address of the memory and a fill value. The fill value is then written from the memory controller to the memory in a fill range of arbitrary length defined by the start address and end address.04-02-2009
20110320750INFORMATION PROCESSING SYSTEM AND METHOD - The present invention provides information storage system and method capable of changing an information storage format to a format suitable for the data utilization form. There are provided a means that records history information of information processing on data, a plurality of information storing means that store information in mutually different information storage formats, and an information storage format control means that changes an information storage format of data, on the basis of a history of processing relating to the data.12-29-2011
20110320749PAGE FAULT PREDICTION FOR PROCESSING VECTOR INSTRUCTIONS - The described embodiments comprise a processor that handles a TLB miss while executing a vector read instruction in a processor. In the described embodiments, the processor performs a lookup in a TLB for addresses in active elements in the vector read instruction. The processor then determines that a TLB miss occurred for the address from an active element other than a first active element. Upon predicting that a page table walk for the vector read instruction will result in a page fault, the processor sets a bit in a corresponding bit position in an FSR. In the described embodiments, a set bit in a bit position in FSR indicates that data in a corresponding element of the vector read instruction is invalid. The processor then immediately performs memory reads for at least one of the first active element and other active elements for which TLB misses did not occur.12-29-2011
20110320748DATA PROCESSING APPARATUS AND DATA PROCESSING METHOD OF DATA PROCESSING APPARATUS - When one of a plurality of storage units is not available, execution of operation modes can be switched according to an option status. A data processing apparatus that can respectively store data to a first storage unit and a second storage unit, includes a control unit configured to execute a first operation mode for limiting data processing using the second storage unit and enabling data processing using the first storage unit in a case where the second storage unit is not available and an option for storing encrypted data in the second storage unit is not used, and execute a second operation mode for limiting the data processing using the first storage unit and the data processing using the second storage unit, in a case where the second storage unit is not available and the option is used.12-29-2011
20110320746HANDLING CONTENT ASSOCIATED WITH CONTENT IDENTIFIERS - Apparatus having at least one processor and at least one memory having computer-readable code stored thereon which when executed controls the at least one processor: to cause a content identifier associated with content to be displayed; to cause a first indicator and a second indicator to be displayed in association with the content identifier; to cause the first indicator to indicate whether or not the some or all of the content is stored in a first memory; to cause the second indicator to indicate whether or not some or all of the content is stored in a second memory; and to be responsive, when the first indicator indicates that none of the content is stored in the first memory and the second indicator indicates that some or all of the content is stored in the second memory, to selection of the first indicator to cause the content associated with the first content identifier to be copied from the second memory into the first memory.12-29-2011
20110320744DIAGNOSTIC DATA COLLECTION AND STORAGE PUT-AWAY STATION IN A MULTIPROCESSOR SYSTEM - A computer-implemented method for collecting diagnostic data within a multiprocessor system that includes capturing diagnostic data via a plurality of collection points disposed at a source location within the multiprocessor system, routing the captured diagnostic data to a data collection station at the source location, providing a plurality of buffers within the data collection station, and temporarily storing the captured diagnostic data on at least one of the plurality of buffers, and transferring the captured diagnostic data to a target storage location on a same chip as the source location or another storage location on a same node.12-29-2011
20110320743MEMORY ORDERED STORE SYSTEM IN A MULTIPROCESSOR COMPUTER SYSTEM - A system and computer implemented method for storing of data in the memory of a computer system in order at a fast rate is provided. The method includes launching a first store to memory. A wait counter is initiated. A second store to memory is speculatively launched when the wait counter expires. The second store to memory is cancelled when the second store achieves coherency prior to the first store to memory.12-29-2011
20110320742METHOD, APPARATUS AND SYSTEM FOR GENERATING ACCESS INFORMATION FROM AN LRU TRACKING LIST - Techniques for generating access information indicating a least recently used (LRU) memory region in a set of memory regions. In an embodiment, data is stored in an entry of an LRU tracking list (LTL) based on a touch message indicating when a memory group has been touched—e.g. read from, written to and/or associated with a memory region. The data stored in an LTL entry may include an identifier of a memory group and/or validity data specifying whether that LTL entry stores a set of default data. In another embodiment, access information may be generated based on the memory group identifier and the validity data.12-29-2011
20120102277DATA STORAGE DEVICE AND WRITE METHOD THEREOF - A write method of a data storage device including a storage media includes compressing data to be stored in the storage media; determining compressed data start positions of a physical unit of the storage media in which the compressed data is to be stored; and storing the compressed data from the determined compressed data start positions of the physical unit, respectively.04-26-2012
20120102276Storing Corresponding Data Units in a Common Storage Unit - A storage device controller may segregate data units that are typically accessed together to a common storage unit. In one example, a storage device includes a control unit configured to receive a plurality of logical blocks to be stored in the storage device, wherein a first set of addresses comprises logical block addresses (LBAs) of the plurality of logical blocks, and a non-volatile memory configured to store logical blocks in a plurality of storage units, wherein one of the plurality of storage units includes logical blocks corresponding to a second set of addresses. The control unit may determine an intersection of the first set of addresses with the second set of addresses and to store each of the logical blocks having LBAs in the determined intersection of addresses in a common storage unit of the storage device, wherein the common storage unit comprises one of the plurality of storage units.04-26-2012
20120102275MEMORIES AND METHODS FOR PERFORMING ATOMIC MEMORY OPERATIONS IN ACCORDANCE WITH CONFIGURATION INFORMATION - Memories and methods for performing an atomic memory operation are disclosed, including a memory having a memory store, operation logic, and a command decoder. Operation logic can be configured to receive data and perform operations thereon in accordance with internal control signals. A command decoder can be configured to receive command packets having at least a memory command portion in which a memory command is provided and data configuration portion in which configuration information related to data associated with a command packet is provided. The command decoder is further configured to generate a command control signal based at least in part on the memory command and further configured to generate control signal based at least in part on the configuration information.04-26-2012
20120331241Adaptive Control For Efficient HARQ Memory Usage - There is determined an amount of available memory that is allocated for automatic repeat-request data. Then for each of a plurality of received data transmissions, an n12-27-2012
20120331244CONFIGURABLE CIRCUIT ARRAY - A method and system are provided for configurable computation and data processing. A logical processor includes an array of logic elements. The processor may be a combinatorial circuit that can be applied to modify computational aspects of an array of reconfigurable circuits. A memory stores a plurality of instructions, each instruction including an instruction-fetch data portion and an output data transfer data portion. One or more memory controllers are coupled to the memory and receive instructions and/or output data from the memory. A back buffer is coupled with the memory controller and receives instructions from the memory controller. The back buffer sequentially asserts each received instruction upon one or more memory controllers. The memory controllers transfer data received from the memory to a target, such as an array of reconfigurable logic circuits that are optionally coupled to the memory, the back buffer, and one or more additional memory controllers.12-27-2012
20120331243Remote Direct Memory Access ('RDMA') In A Parallel Computer - Remote direct memory access (‘RDMA’) in a parallel computer, the parallel computer including a plurality of nodes, each node including a messaging unit, including: receiving an RDMA read operation request that includes a virtual address representing a memory region at which to receive data to be transferred from a second node to the first node; responsive to the RDMA read operation request: translating the virtual address to a physical address; creating a local RDMA object that includes a counter set to the size of the memory region; sending a message that includes an DMA write operation request, the physical address of the memory region on the first node, the physical address of the local RDMA object on the first node, and a remote virtual address on the second node; and receiving the data to be transferred from the second node.12-27-2012
20120331242CONSISTENT UNMAPPING OF APPLICATION DATA IN PRESENCE OF CONCURRENT, UNQUIESCED WRITERS AND READERS - Free storage blocks previously allocated to a logical block device are released back to an underlying storage system supporting the logical block device in a manner that does not conflict with write operations that may be issued to the free storage blocks at about the same time. According to a first technique, write operations on the same storage blocks to be released are paused until the underlying storage system has completed the releasing operation or, if the write operations are issued earlier than when the underlying storage system actually performs the releasing operation, such storage blocks are not released. According to a second technique, a special file is allocated the free storage blocks, which are then made available for safe releasing.12-27-2012
20120137085COMPUTER SYSTEM AND ITS CONTROL METHOD - Provided is a computer system capable of migrating processing authority for accessing a logical volume between multiple storage apparatuses without causing any overhead in the performance of the path between the multiple storage apparatuses.05-31-2012
20130013870DIFFERENTIAL VECTOR STORAGE FOR NON-VOLATILE MEMORY - A method is disclosed for storing information on non-volatile memory which can rewrite memory cells multiple times before a block needs to be erased. The information to be stored is transformed into a suitable form which has better robustness properties with respect to common sources of error, such as leakage of charge, or imperfect read/write units.01-10-2013
20100131724SEMICONDUCTOR DEVICE - The present invention has an object of providing a high-speed, low-cost, and user-friendly information processing system that can ensure scalability of memory capacity. The information processing system is configured to include an information processing device, a volatile memory, and a nonvolatile memory. By serially connecting the information processing device, the volatile memory, and the nonvolatile memory and reducing the number of connection signals, processing speed is increased while maintaining the scalability of memory capacity. When transferring data of the nonvolatile memory to the volatile memory, error correction is performed, thereby improving reliability. The information processing system including the plurality of chips is configured as an information-processing system module in which the chips are alternately stacked and arranged, and wired by a ball grid array (BGA) or by bonding between the chips.05-27-2010
20100131723ACCESS CONTROL APPARATUS, ACCESS CONTROL METHOD, AND STORAGE APPARATUS - According to one embodiment, an access control apparatus is configured to convert a logical address into position information of a physical sector to control access to a storage medium. The access control apparatus includes an access mode specifying command processing module and an access processing module. The access mode specifying command processing module receives an access mode specifying command specifying an access mode that defines a relationship between the logical address and the physical sector, and stores the access mode in an access mode storage module. The access processing module refers to the access mode storage module to determine an access mode for accessing the storage medium.05-27-2010
20130019072APPARATUS, SYSTEM, AND METHOD FOR MANAGING OUT-OF-SERVICE CONDITIONS - An adaptive logical storage element comprises a plurality of solid-state storage elements accessible in parallel. The logical storage element includes logical storage units, which may include logical page, logical storage divisions (erase blocks), and so on. Each logical storage unit comprises a plurality of physical storage units. A logical storage unit may include one or more physical storage units that are out-of-service (OOS). The OOS status of logical storage units is tracked by OOS metadata. When data is stored on the logical storage element, padding data is provided to physical storage units that are OOS, and valid and/or parity data is provided to in-service physical storage units. A write data pipeline accesses the OOS metadata to insert padding data, and a read data pipeline accesses the OOS metadata to strip padding data.01-17-2013
20130019070CONSOLIDATING CONTROL AREASAANM Lehr; Douglas L.AACI AustinAAST TXAACO USAAGP Lehr; Douglas L. Austin TX USAANM McCune; Franklin E.AACI TucsonAAST AZAACO USAAGP McCune; Franklin E. Tucson AZ USAANM Reed; David C.AACI TucsonAAST AZAACO USAAGP Reed; David C. Tucson AZ USAANM Smith; Max D.AACI TucsonAAST AZAACO USAAGP Smith; Max D. Tucson AZ US - A detection module selects logically adjacent first and second control areas of a cluster. The detection module further determines that the first and second control areas satisfy a migration test wherein the first control area has free space exceeding a free threshold, the free space is at least equal to a space requirement for each second control area control interval, and the second control area has fewer control intervals than a control interval threshold. In addition, a copy module copies each second control area control interval to the first control area in response to determining that the first and second control areas satisfy the migration test.01-17-2013
20130019071DYNAMICALLY MANAGING AVAILABLE DATA STORAGE WITHIN AN AUTOMATED DATA STORAGE SYSTEMAANM Lewis; Cecilia C.AACI San JoseAAST CAAACO USAAGP Lewis; Cecilia C. San Jose CA USAANM Dearing; Gerard M.AACI San JoseAAST CAAACO USAAGP Dearing; Gerard M. San Jose CA USAANM Koester; Michael J.AACI HollisterAAST CAAACO USAAGP Koester; Michael J. Hollister CA US - In one embodiment, a computer program product includes a computer readable storage medium having computer readable program code embodied therewith, the computer readable program code being configured to: assign volume(s) to either a storage group or a reserve storage pool group, designate each of the volume(s) assigned to the storage group as a storage volume, designate each of the volume(s) assigned to the reserve storage pool group as a reserve storage volume, receive policy attributes for the storage group including a storage utilization goal and a default reserve storage pool assignment, monitor a storage utilization level for the storage group, detect when the storage utilization level for the storage group falls outside of the ideal storage utilization range, and adjust an available storage amount for the storage group to bring the storage utilization level within the ideal storage utilization range.01-17-2013
20130024633METHOD FOR OUTPUTTING AUDIO-VISUAL MEDIA CONTENTS ON A MOBILE ELECTRONIC DEVICE, AND MOBILE ELECTRONIC DEVICE - A method for outputting an audio-visual media content on a mobile electronic device, the mobile electronic device storing the media content in at least a compressed format in a memory of the mobile electronic device, is provided. The method may include receiving a request for the output of the media content; checking of whether the requested media content is stored in an uncompressed format in the memory; outputting the requested media content in the stored uncompressed format if the requested media content is stored in the uncompressed format in the memory, and outputting the requested media content in the stored compressed format if the requested media content is not stored in the uncompressed format in the memory.01-24-2013
20130024632METHOD AND SYSTEM FOR TRANSFORMATION OF LOGICAL DATA OBJECTS FOR STORAGE - There are provided a method of transforming a non-transformed stored logical data object (LO) device into a transformed LO and system thereof. The method comprises: a) in response to a respective transformation request, logically dividing the non-transformed LO in a first segment and one or more non-transformed subsequent segments, the segments having predefined size; b) generating a header for the respective transformed LO; c) processing said first segment; d) overwriting said first segment by said generated header and said transformed first segment; e) indexing said first transformed segment and said one or more non-transformed subsequent segments as constituting a part of said transformed LO; f) generating at least one index section; and g) updating the indication in the header to point that the non-transformed LO has been transformed in the transformed LO comprising said generated header, said first transformed segment, said one or more subsequent segments comprising data in non-transformed form and said at least one index section.01-24-2013
20130024631METHOD AND APPARATUS FOR REALTIME DETECTION OF HEAP MEMORY CORRUPTION BY BUFFER OVERRUNS - One embodiment of the present invention relates to a heap overflow detection system that includes an arithmetic logic unit, a datapath, and address violation detection logic. The arithmetic logic unit is configured to receive an instruction having an opcode and an operand and to generate a final address and to generate a compare signal on the opcode indicating a heap memory access related instruction. The datapath is configured to provide the opcode and the operand to the arithmetic logic unit. The address violation detection logic determines whether a heap memory access is a violation according to the operand and the final address on receiving the compare signal from the arithmetic logic unit.01-24-2013
20080256307STORAGE SUBSYSTEM, STORAGE SYSTEM, AND METHOD OF CONTROLLING POWER SUPPLY TO THE STORAGE SUBSYSTEM - Provided is storage subsystem including: a storage unit containing multiple disk groups; and a control device for controlling the storage unit. The storage unit includes at least one redundant disk group composed of at least a first disk group and a second disk group for redundancy. The control device is configured to: put the first disk group into a power-on state; put the second disk group into a power-off state; read/write data stored in the first disk group; turns on power of the second disk group at a predetermined timing; write, in the second disk group, data that has been written in the first disk group while the second disk group has been in the power-off state; and put one of the first and second disk group into the power-on state and the other one of the first and second disk group into the power-off state after the writing.10-16-2008
20080276054MONITORING PERFORMANCE OF A STORAGE AREA NETWORK - A performance monitor reports SAN performance so that issues within the SAN are not masked from the client. Accesses to the SAN may be grouped into the categories of SAN logical or SAN physical. In one specific embodiment, the ranges of service times for accesses to the SAN are determined by monitoring service times of accesses to the SAN from the client perspective. In another specific embodiment, the ranges of service times for the SAN are determined by the SAN returning data with each request that indicates the service time from the SAN perspective. This allows reporting not only SAN logical and SAN physical accesses, but also allows reporting SAN service time. By specifying SAN service time, the client is able to better determine network delays. In yet another embodiment, information is returned by the SAN to indicate whether the access is SAN logical or SAN physical.11-06-2008
20080235468HYBRID DENSITY MEMORY STORAGE DEVICE - The present invention discloses a hybrid density memory storage device configured to store data responsive to a host and a file system thereof. The hybrid density memory storage device includes a non-volatile memory, a hot data buffer and a control unit. The non-volatile memory includes a high density storage space and a low density storage space. The control unit is coupled between the host, the non-volatile memory, and the hot data buffer. The control unit has a hot list used for recording a plurality of logical locations of hot data, and the control unit is capable of accessing data in/out the hot data buffer in accordance with the hot list.09-25-2008
20080235466Methods for storing memory operations in a queue - A method for operating a non-volatile memory storage system is provided. In this method, a queue that is configured to store memory operations associated with two or more types of memory operations. Here, memory operations are associated with the maintenance of the non-volatile memory storage system. A memory operation is scheduled for execution in response to an event and the memory operation is stored in the queue.09-25-2008
20130173871Memory Systems and Methods for Dividing Physical Memory Locations Into Temporal Memory Locations - Described are memory modules that support dynamic point-to-point extensibility using fixed-width memory die. The memory modules include data-width translators that allow the modules to vary the effective width of their external memory interfaces without varying the width of the internal memory interfaces extending between the translators and associated fixed-width dies. The data-width translators use a data-mask signal to selectively prevent memory accesses to subsets of physical addresses. This data masking divides the physical address locations into two or more temporal subsets of the physical address locations, effectively increasing the number of uniquely addressable locations in a given module. Reading temporal addresses in write order can introduce undesirable read latency. Some embodiments reorder read data to reduce this latency.07-04-2013
20130173872Abstracting Programmatic Representation of Data Storage Systems - Providing for a paradigm shift in block-level abstraction for storage devices is described herein. At a block-level, storage is characterized as a variable size data record, rather than a fixed size sector. In some aspects, the variable size data record can comprise a variable binary key-data pair, for addressing and identifying a variable size block of data, and for dynamically specifying the size of such block in terms of data storage. By changing the key or data values, the location, identity or size of block-level storage can be modified. Data records can be passed to and from the storage device to facilitate operational commands over ranges of such records. Block-level data compression, space management and transactional operations are provided, mitigating a need of higher level systems to characterize underlying data storage for implementation of such operations.07-04-2013
20130173873Method and Apparatus for Performing Mapping Within a Data Processing System Having Virtual Machines - In an environment in which a processor operates a hypervisor and multiple guest partitions operating under the hypervisor's control, it is desirable to allow a guest partition access to a physical memory device without decreasing system performance. Accordingly, a conversion instruction for converting a logical address to a real address, i.e., an LTOR instruction, executable from a guest partition, is added to the processor. Upon the guest partition's execution of the conversion instruction with the logical address specified, the processor converts the logical address to an encrypted real address, and returns it to the guest partition. The guest partition is then able to pass the encrypted real address to an accelerator that converts the encrypted real address to a real address in order to access the memory device using the real address.07-04-2013
20110246729METHODS, CIRCUITS, AND SYSTEMS TO SELECT MEMORY REGIONS - Embodiments for selecting regions of memory are described. For example, in one embodiment a memory device having an array of memory cells includes an array selection block. The array selection block receives an input signal indicative of a region in the array of memory cells. The array selection block generates a selection signal to map the region to at least one physical location in the array of memory cells, based on the detection of the number of defects in that location.10-06-2011
20110246728Memory Management Device - A second memory stores data in units of segments. An assignment control circuit sets up a buffer space as a logical address space. A buffer space is formed as a set of at least one segment. A state storage circuit stores association between a buffer space and segments as segment assignment information. An address conversion circuit refers to segment assignment information to convert a logical address into a physical address. A segment queue stores a free segment and a buffer queue stores a free buffer. The state storage circuit includes a plurality of register groups each of which includes a plurality of segment registers. A register group is associated with one of the plurality of buffer spaces. A range number identifying a range of logical addresses in the associated buffer space is set up in a segment register.10-06-2011
20110264868METHOD OF CONTROLLING TOTAL CAPACITY OF VIRTUAL VOLUMES ASSOCIATED WITH POOL AND STORAGE APPARATUS - The statuses of an actual area are (1) a first status which indicates that [the actual area] is already initialized and can be assigned to a virtual area, (2) a second status which indicates that [the actual area] is already assigned to a virtual area, and (3) a third status which indicates that [the actual area] cannot be assigned to a virtual area and initialization which is specified data write is to be performed. The storage controller limits the total virtual volume capacity which is the total capacity of one or more virtual volumes which are associated with the pool, in accordance with whether the pool comprises an actual page in the third status or not, to the capacity of the pool or smaller.10-27-2011
20080222371Method for Managing Memory Access and Task Distribution on a Multi-Processor Storage Device - In a system for reading and writing data, the system including a controller, multiple microprocessor units accessible to the controller, and multiple memory device configurations, each having one dedicated bus connection to individual ones or multiples of the microprocessor units, a method for managing access to one or more of the memory device configurations includes the steps, (a) receiving a request at the controller requiring access of at least one of the memory device configurations, (b) determining at the controller, which microprocessor unit or units will handle the request, (c) handing the request to the selected microprocessor unit or units, (d) determining at the microprocessor unit or units, the tasks specified in the request for that microprocessor unit or units and (e) determining a memory address or addresses in one or more of the memory device configurations and accessing the memory device configuration or configurations to satisfy the request.09-11-2008
20080222370METHOD AND APPARATUS FOR DATA STREAM MANAGEMENT - A method and apparatus of managing data stream, the method comprising archiving received data in a circular buffer; utilizing a breakpoint in realizing the archived received data continuity, wherein the breakpoint is set to the last data portion of the archived received data; when the archiving of the received data approaches the end of the circular buffer, stitching the last portion of the archived received data to the start of the circular buffer; and setting the breakpoint to the updated last data portion of the archived data.09-11-2008
20130179646STORAGE CONTROL DEVICE, STORAGE DEVICE, AND CONTROL METHOD FOR CONTROLLING STORAGE CONTROL DEVICE - A storage control device is disclosed including a write block and a read block. The write block establishes a high-speed access data count. If a plurality of data are to be written to high- and low-speed access storage blocks, the write block writes as many data as the high-speed access data count from among the plurality of data to the high-speed access storage block as high-speed access data while writing the remaining data to the low-speed access storage block as low-speed access data. If the plurality of data written to the low- and high-speed access storage blocks are to be read, the read block issues a request to the high-speed access storage block to read the high-speed access data and a request to the low-speed access storage block to start reading the low-speed access data after the high-speed access data have been read.07-11-2013
20130179647STORAGE DEVICE AND DATA MANAGEMENT METHOD THEREOF - Disclosed is a data managing method of a storage device which includes at least one nonvolatile memory device and a controller controlling the nonvolatile memory device. The data managing method includes receiving an input/output request and generating a section directing logical addresses based on the input/output request. The section is managed using section information, and the section information includes a start logical address corresponding to the input/output request, spatial locality information having the number of the directed logical addresses, and historical request information.07-11-2013
20130173870BIDIRECTIONAL SHIFT REGISTER AND THE DRIVING METHOD THEREOF - A bidirectional shift register includes a first register circuit and a second register circuit. The first register circuit includes a first register stage and a first output buffer stage with n numbers of scanning signal output ends. The first register stage is electrically coupled to a third voltage source. The first output buffer stage is electrically coupled to a second voltage source and a first voltage source. The second register circuit has a similar circuit structure to the first register circuit; wherein the first register circuit and the second register circuit each use n+1 numbers clock signal lines, and the n is a positive integer.07-04-2013
20120254559Method and Apparatus For Detecting The Presence of Subblocks in a Reduced Redundancy Storing System - This application concerns determining whether a particular subblock of data is present in a reduced-redundancy storage system. One embodiment achieves this by hashing subblocks in the storage system into a bitfilter that contains ‘1’ bit for each position to which at least one subblock hashes. This bitfilter provides a fast way to determine whether a subblock is in the storage system. In another embodiment, index entries for new subblocks may be buffered in a subblock index write buffer to convert a large number of random access read and write operations into a single sequential read and a single sequential write operation. The combination of the bitfilter and the write buffer yields a reduced-redundancy storage system that uses significantly less high speed random access memory than other systems that store the entire subblock index in memory.10-04-2012
20120254556CONTROL APPARATUS, STORAGE SYSTEM, AND CONTROL METHOD - In a storage system, a storage unit of a control apparatus stores first connection information indicating a device connected to a subordinate of the control apparatus. A controller acquires second connection information, created by a relay device, indicating a device connected to the relay device, compares the acquired second connection information and the first connection information stored in the storage unit, and transmits a reset instruction on the second connection information to the relay device based on a comparison result.10-04-2012
20120254555COMPUTER SYSTEM AND DATA MANAGEMENT METHOD - The storage apparatus comprises a storage unit for storing data to be read and written by the host computer; and a control unit for controlling the writing of data into the storage unit, wherein the control unit deletes an entity of the data replicated to the archive apparatus from the storage unit and stubs the data; calls the stubbed data from the archive apparatus and temporarily stores the entity of the data according to a request from the host apparatus; and if an area where the entity of the stubbed data is stored in the storage unit among data storage areas of the storage unit is a predetermined capacity or less, migrates stub information concerning the stubbed data to a storage unit of another storage apparatus.10-04-2012
20120254553ZONE GROUP REASSIGNMENT USING STORAGE DEVICE SIGNATURES - A method and apparatus for assigning zone groups to a storage enclosure is disclosed. When a storage enclosure is added to a switch in a fabric, a signature of the storage enclosure will be created from the storage devices loaded in that enclosure. The signature will then be compared against the signature from a storage enclosure that is offline. When the signature matches the signature of the offline storage enclosure, the zone groups from the offline storage enclosure will be copied to the storage enclosure that was added to the fabric.10-04-2012
20120254552Memory access remapping - A data processing system is provided comprising a bus master coupled to a bus slave via a bus system. The bus master is configured to access the bus slave by issuing an access request, the access request being routed by the bus system to the bus slave.10-04-2012
20110271063SEMICONDUCTOR MEMORY APPARATUS AND DATA INPUT AND OUTPUT METHOD THEREOF - A semiconductor memory apparatus includes an input data bus inversion unit configured to determine whether or not to invert a plurality of input data depending upon levels of the plurality of input data, and generate a plurality of conversion data; data input lines configured to transmit the plurality of conversion data; a data recovery unit configured to receive the plurality of conversion data and generate a plurality of storage data; and a memory bank configured to store the plurality of storage data.11-03-2011
20080215826DETERMINISTIC MEMORY MANAGEMENT IN A COMPUTING ENVIRONMENT - Systems and methods for memory management in a computing environment are provided. The method comprises uniquely identifying a first object associated with a first task for an application executed in a computing environment, wherein a first area of memory is allocated to the first object; determining a first execution scope for the first task according to a first execution context associated with the first task, wherein the first context defines a first life expectancy for the first task within the execution environment hierarchy; determining a change in execution scope of the first task, in response to monitoring the first execution context; and deallocating the first area of memory, in response to determining that the first task is no longer executed within the first execution scope.09-04-2008
20130138898MEMORY MODULE INCLUDING PLURAL MEMORY DEVICES AND COMMAND ADDRESS REGISTER BUFFER - Disclosed herein is a memory module that includes a plurality of command address connectors formed on the module substrate, a plurality of memory devices mounted on the module substrate, and a plurality of command address register buffers mounted on the module substrate. The command address connectors receive a command address signal from outside. The memory devices include a plurality of first memory devices and a plurality of second memory devices. The command address register buffers include a first command address register buffer that supplies the command address signal to the first memory devices and a second command address register buffer that supplies the command address signal to the second memory devices.05-30-2013
20130097396METHOD AND SYSTEM FOR ENCODING DATA FOR STORAGE IN A MEMORY ARRAY - A method of storing data into a memory array converts an input string into a first binary array with (m−1) rows and (n−1) columns. A second binary array with m rows and n columns in an encoded bit pattern is then generated from the first binary array. The second binary array in the encoded bit pattern has at most n/2 1's in each row and at most m/2 1's in each column, and the m-th row and an n-th column contain information for decoding other entries of the second binary array. The encoded bit pattern of the second binary array is then stored into corresponding memory devices of the memory array.04-18-2013
20130097395METHOD AND APPARATUS FOR SENDING DATA FROM MULTIPLE SOURCES OVER A COMMUNICATIONS BUS - In a memory system, multiple memory modules communicate over a bus. Each memory module may include a hub and at least one memory storage unit. The hub receives local data from the memory storage units, and downstream data from one or more other memory modules. The hub assembles data to be sent over the bus within a data block structure, which is divided into multiple lanes. An indication is made of where, within the data block structure, a breakpoint will occur in the data being placed on the bus by a first source (e.g., the local or downstream data). Based on the indication, data from a second source (e.g., the downstream or local data) is placed in the remainder of the data block, thus reducing gaps on the bus. Additional apparatus, systems, and methods are disclosed.04-18-2013
20130097394MEMORY CONTROLLER AND METHODS - A memory controller that allows shared access to a memory device via a plurality of write ports and read ports. A write port includes a data buffer that allows data to be written to a first number of its storage locations at a pre-determined time. A write arbiter is able to read data from a second number of storage locations of a data buffer of a write port at a pre-determined time and write the read data to a memory device. A read port is configured to respond to requests to read data and includes a data buffer. A read arbiter is able to read, at a pre-determined time, data from the memory device on behalf of one of the read ports, and to write the read data into a second number of storage locations of the data buffer of the read port on whose behalf the data was read.04-18-2013
20110314235DATA STORAGE DEVICE AND WRITE METHOD THEREOF - A data storage device that includes a storage media, and a controller to compress raw data to be stored in the storage media, wherein the controller can add header and/or footer information to the compressed data. The controller of the data storage device can further change stored, compressed data by retrieving all or only some of the compressed stored data, uncompressing it, adding or changing the now uncompressed data, and then re-compressing it before adding either or both of header and footer to the compressed data. The storage media can be solid state devices, and can be used with a controller in a computer or a server, that can be part of any one or a multitude of types of networks, including, for example, an internet.12-22-2011
20110314233MULTI-CORE QUERY PROCESSING USING ASYNCHRONOUS BUFFERS - A system may include a buffer monitor configured to monitor buffer content of a buffer being used during processing of a query workflow in which write tasks of the query workflow write data to the buffer and read tasks of the query workflow read data from the buffer, the buffer having a buffer capacity. The system may include a threshold manager configured to compare the buffer content to a low threshold and to a high threshold that are defined relative to the buffer capacity, and a speed controller configured to control a number of the write tasks relative to a number of the read tasks that are currently executing the query workflow, to thereby maintain the buffer content between the low threshold and the high threshold.12-22-2011
20110314231BANDWIDTH ADAPTIVE MEMORY COMPRESSION - Data is retrieved from system memory in compressed mode if a determination is made that the memory bus is bandwidth limited and in uncompressed mode if the memory bus is not bandwidth limited. Determination of the existence of the bandwidth limited condition may be based on memory bus utilization or according to a depth of a queue of memory access requests.12-22-2011
20110314230ACTION FRAMEWORK IN SOFTWARE TRANSACTIONAL MEMORY - A software transactional memory system implements a lightweight key-based action framework. The framework includes a set of unified application programming interfaces (APIs) exposed by an STM library that allow clients to implement actions that can be registered, queried, and updated using specific keys by transactions or transaction nests in STM code. Each action includes a key, state information, and a set of one or more callbacks that can be hooked to the validation, commit, abort, and/or re-execution phases of transaction execution. The actions extend the built-in concurrency controls of the STM system with customized control logics, support transaction nesting semantics, and enable integration with garbage collection systems.12-22-2011
20130103914APPARATUS, METHOD, AND STORAGE MEDIUM FOR SAMPLING DATA - A data sampling apparatus includes a plurality of first-in first-out memories and a processor that executes a procedure. The procedure includes classifying received data signals in accordance with types of the data signals; storing the classified data signals in the corresponding memories; calculating a sampling rate based on a ratio between a total traffic volume of the received data signals per given time and a traffic volume of data signals stored in each of the memories per given time; and sampling the data signals stored in each of the memories based on the corresponding calculated sampling rate.04-25-2013
20130103913SEMICONDUCTOR STORAGE DEVICE, SYSTEM, AND METHOD - A semiconductor storage system includes: a difference determining circuit configured to determine a difference between the number of first state values of sample data written to a memory and the number of first state values of read data read from the memory; and a compensation value determining circuit configured to determine a read voltage level compensation value corresponding to a difference between the number of the first state values of the sample data written to the memory and the number of the first state values of the read data read from the memory.04-25-2013
20130124806DYNAMIC RAM PHY INTERFACE WITH CONFIGURABLE POWER STATES - A physical memory interface (Phy) and method of operating is disclosed. The Phy interface includes command and status registers (CSRs) configured to receive a first power context and second power context. Selection circuitry is configured to switch between the first and second power contexts. A plurality of adjustable delay elements are provided, each having a delay time responsive to the selected power context. A first set of CSRs configured may store the first power context and a second set of CSRs configured may store the second power context. The Phy interface may also include a plurality of drivers each having a selectable drive strength responsive to the selected power context. The Phy interface may also include a plurality of receivers each having a selectable termination impedance responsive to the selected power context. Switching between power contexts may result in adjusting of the delay elements, drive strength and/or termination impedance of one or more drivers/receivers.05-16-2013
20130132688Parallel Read Functional Unit for Microprocessors - A functional unit is provided which allows for fast, parallel data read, write, and manipulation operations. The functional unit includes first and second source registers for receiving first and second data items to be processed by the functional unit, a plurality of memory tables, a combinational logic circuit, and a decoder. Each of the tables is indexed by an index comprising a portion of the first data item received by the first source register. The combinational logic circuit receives lookup results, and processes the lookup results and the second data item in the second source register to produce a result data item. The decoder circuit extracts an operational code from an instruction supplied to the functional unit, decodes the operational code, and controls the combinational logic circuit in accordance with the operational code.05-23-2013
20130132687METHOD FOR STORING DATA AS WELL AS A TRANSPONDER, A READ/WRITE-DEVICE, A COMPUTER READABLE MEDIUM INCLUDING A PROGRAM ELEMENT AND SUCH A PROGRAM ELEMENT ADAPTED TO PERFORM THIS METHOD - A method for storing or reading data in a memory array of a transponder and a corresponding transponder, read/write device and program element is described. Therein, a data file system for storing data within the memory array is defined by a predetermined protocol. The method for storing additional data includes checking whether a memory size of the application data file is larger than the memory size indicated by the application data length indicator; and storing second application data in a partial memory area of the application data file not occupied by the first application data. Thereby, memory areas which, according to the predetermined protocol, are not used can be used for new applications, data can be hidden in these areas such that they can not be read by protocol compliant reader devices and the data structure read or written by the method of the invention is compatible with the former predetermined protocol.05-23-2013
20130132686Data Rewrite System For Vehicle, In-Vehicle Apparatus And Rewrite Apparatus - A data rewrite system including an in-vehicle apparatus and a rewrite apparatus is disclosed. The in-vehicle apparatus stores multiple operation data units in multiple storage areas and outputs version informations of the operation data wilts and information about the storage areas to the rewrite apparatus. The rewrite apparatus selects a target storage area, which is a target for data update, from the storage areas of the in-vehicle apparatus by comparing the versions informations of the operation data units with version informations of update data units. The rewrite apparatus updates the selected target storage area with the update data unit that corresponds to the operation data unit in the target storage area.05-23-2013
20130132685MEMORY CONTROLLER AND MEMORY DEVICE COMMAND PROTOCOL - Embodiments generally relate to a command protocol and/or related circuits and apparatus for communication between a memory device and a memory controller. In one embodiment, the memory controller includes an interface for transmitting commands to the memory device, wherein the memory device includes bitline multiplexers, and accessing of memory cells within the memory device is carried out by a command protocol sequence that includes a wordline selection, followed by bitline selections by the bitline multiplexers. In another embodiment, a memory device includes bitline multiplexers and further includes an interface for receiving a command protocol sequence that specifies a wordline selection followed by bitline selections by the bitline multiplexers.05-23-2013
20080201537Memory Controller and Method for Coupling a Network and a Memory - A memory controller (SMC) is provided for coupling a memory (MEM) to a network (N; IM). The memory controller (SMC) comprises a first interface (PI) for connecting the memory controller (SMC) to the network (N; IM). The first interface (PI) is arranged for receiving and transmitting data streams (ST08-21-2008
20110225377DATA STORAGE APPARATUS, DATA MANAGEMENT APPARATUS AND CONTROL METHOD THEREOF - A data storage apparatus, connected to an information processing apparatus, includes a library unit, a storage unit, and a control unit. The storage unit is configured to store a plurality of data including first and second data received from the information processing apparatus, and the control unit is configured to perform control, when performing processing to write the plurality of data from the storage unit to a recording medium in the library unit. If an update request for updating the second data specified to be written later than the first data is received from the information processing apparatus, the second data is written to the recording medium in the library unit before the first data is written.09-15-2011
20130185527Asymmetrically-Arranged Memories having Reduced Current Leakage and/or Latency, and Related Systems and Methods - Asymmetrically-arranged memories having reduced current leakage and/or latency, and related systems and methods are disclosed. In one embodiment, a memory comprises a memory access interface (MAI). The memory further comprises a first memory portion(s) accessible by the MAI. The first memory portion(s) has a first latency and a first current leakage. The memory further comprises a second memory portion(s) accessible by the MAI. To provide an asymmetrical memory arrangement, the first latency of the first memory portion(s) is increased such that the second memory portion(s) has a second latency greater than or equal to the first latency and a second current leakage greater than the first current leakage. Accordingly, the overall current leakage of the memory is reduced while not increasing overall latency of the memory. The first and second memory portion(s) may each be comprised of one or more memory sub-bank(s) and/or one or more memory bank(s).07-18-2013
20130185528RUNTIME DYNAMIC PERFORMANCE SKEW ELIMINATION - For runtime dynamic performance skew elimination in a computer environment, an exemplary computer environment is configured for calculating a rank heats by utilizing a plurality of fine-grained statistics collected at an extent granularity, including considering bandwidth (BW) and input/outputs per second (IOPS) metrics. An adaptive data placement plan is generated to relocate the data.07-18-2013
20110238930TRANSMISSION APPARATUS AND CONTROL DATA PROCESSING METHOD AND PROGRAM - A transmission apparatus includes a memory and a circuit. The memory store control data included in a frame received from outside the apparatus and state information indicating a state of the control data in the transmission apparatus in association with each other. The circuit records the control data included in the frame to the memory. The circuit changes the state information to information indicating that the recording of the control data is completed. The circuit determines whether or not the control data stored in the memory is to be rewritten. The circuit rewrites the control data stored in the memory, upon determining that the control data is rewritten. The circuit changes the state information to information indicating that the rewriting of the control data is completed. The circuit reads the control data stored in the memory.09-29-2011
20130151796SYSTEM AND METHOD FOR CALIBRATION OF SERIAL LINKS USING A SERIAL-TO-PARALLEL LOOPBACK - A system and method for calibration of serial links using serial-to-parallel loopback. Embodiments of the present invention are operable for calibrating serial links using parallel links thereby reducing the number of links that need calibration. The method includes sending serialized data over a serial interface and receiving parallel data via a parallel interface. The serialized data is looped back via the parallel interface. The method further includes comparing the parallel data and the serialized data for a match thereof and calibrating the serial interface by adjusting the sending of the serialized data until the comparing detects the match. The adjusting of the sending is operable to calibrate the sending of the serialized data over the serial interface.06-13-2013
20130151797METHOD AND APPARATUS FOR CENTRALIZED TIMESTAMP PROCESSING - Method and apparatus for centralized timestamp processing is described herein. A graphics processing system includes multiple graphics engines and a timestamp module. For each task, a graphics driver assigns the task to a graphics engine and writes a task command packet to a memory buffer associated with the graphics engine. The graphics driver also writes a timestamp command packet for each task to a timestamp module memory buffer. A command processor associated with the graphics engine signals the timestamp module memory buffer upon completion of the task. If the read pointer is at the appropriate position in the timestamp module memory buffer, the timestamp module/timestamp module memory buffer executes the timestamp command packet and writes the timestamp to a timestamp memory. The timestamp memory is accessible by the graphics driver.06-13-2013
20130151798Expedited Module Unloading For Kernel Modules That Execute Read-Copy Update Callback Processing Code - A technique for expediting the unloading of an operating system kernel module that executes read-copy update (RCU) callback processing code in a computing system having one or more processors. According to embodiments of the disclosed technique, an RCU callback is enqueued so that it can be processed by the kernel module's callback processing code following completion of a grace period in which each of the one or more processors has passed through a quiescent state. An expediting operation is performed to expedite processing of the RCU callback. The RCU callback is then processed and the kernel module is unloaded.06-13-2013
20100293346Storage System Construction Managing Device And Construction Management Method - The device of the present invention manages changes in the construction of a storage system in a unified manner, and optimally disposes resources. The servers are logically divided into a plurality of virtual servers, the switches are logically divided into a plurality of zones, and the storage devices are logically divided into a plurality of virtual storage devices. The respective logical devices are respectively managed by respective managing parts. These respective managing parts are connected to a managing device via a network used for management. The managing device re-disposes resources in application program units on the basis of the load states of the respective resources in the storage system.11-18-2010
20100293344APPARATUS AND METHOD FOR SELECTING A POSITION WHERE DATA IS STORED - An apparatus and method are provided for selecting a specific position from a plurality of positions in a memory to which data elements are cyclically written. A specific data element is stored in the plurality of positions. The apparatus comprises a determination unit for determining whether the plurality of positions include any position in a specific area of the memory to which data elements are written in a current cycle. The apparatus further comprises a selection unit for selecting at least one position in the specific area out of the plurality of positions as the specific position if the determination unit determines that the plurality of positions include any position in the specific area, and for selecting at least one position out of the plurality of positions as the specific position if the determination unit determines that the plurality of positions do not include any position in the specific area.11-18-2010
20090094420DATA ACCESS METHOD AND MEMORY USING THE SAME - A data access method and a memory using the same are provided in the present invention. In the data access method, a central processing unit (CPU) write command and a display read command are directly input to a memory in order to optimize the operation time.04-09-2009
20100318752Event Triggered Memory Mapped Access - In one or more embodiments, a data processing system can include at least one core capable of executing instructions of an instruction set architecture and a triggered memory map access (tMMA) system coupled to the at least one core. The tMMA system can receive one or more events and, in response, perform one or more actions. For example, the actions can include transactions which can include a write to a an address of the memory map, a read from an address of the memory map, a read followed by write to two respective addresses of the memory map, and/or a fetch transaction. A result of a transaction (e.g., data read, data written, error, etc.) can be used in generating a trace message. For example, the tMMA system can generate a trace message that includes the result of the transaction and send the trace message to a trace message bus.12-16-2010
20120284468STORAGE CONTROL DEVICE - A storage control device includes: a memory where a data file is temporarily stored; a read-out unit that sequentially reads out divided data segments of the data file; a storage medium that includes data storage areas having small areas and data management areas each corresponding to the small area, so as to store each of the data segments into small areas and store at least one of first link information and second link information into the data management areas; a first instruction unit that issues an instruction for procuring consecutive data management areas corresponding to a data size of data segments; a second instruction unit that issues an instruction for writing the first link information into the data management areas excluding a trailing-end data management area; and a third instruction unit that issues an instruction for sequentially writing the data segment into the data storage areas.11-08-2012
20120284467EXTENDED LOGICAL WORM DATA INTEGRITY PROTECTION WITH UNIQUE WORM IDENTIFIER IN HEADER AND DATABASE - A data storage system stores logical data object(s), each identified by a logical identifier. A control is configured to assign a unique WORM (Write Once Read Many) identifier to the logical data object, and stores the unique WORM identifier as associated with the logical identifier, in a database maintained by the control so as to be persistent. Data storage is configured to write the logical data object with a header with the unique WORM identifier. The control, in order to allow the logical data object to be accessed externally to the control, requires matching the unique WORM identifier in the header of a logical data object to the unique WORM identifier of the persistent database for the logical object. The unique WORM identifier is formed of a checksum hash value related to nonce fields comprising at least the logical identifier of the logical data object, and an incrementing token.11-08-2012
20120284466METHODS FOR CONTROLLING HOST MEMORY ACCESS WITH MEMORY DEVICES AND SYSTEMS - The present disclosure includes methods for controlling host memory access with a memory device, systems, host controllers and memory devices. One embodiment for controlling host memory access with a memory device includes receiving at least one command from a host and controlling execution of the at least one command with the memory device.11-08-2012
20120284465Operating System Management of Address-Translation-Related Data Structures and Hardware Lookasides - An approach is provided in a hypervised computer system where a page table request is at an operating system running in the hypervised computer system. The operating system determines whether the page table request requires the hypervisor to process. If the determination reveals that the page table request requires the hypervisor, then the hypervisor is used to handle the request. However, if the determination reveals that the page table request does not require the hypervisor, then an indicator included in a page table entry corresponding to the request is read to determine if the page table entry is controlled by the operating system or the hypervisor. The operating system is able to update the page table entry if the indicator identifies the page table entry as being operating system controlled.11-08-2012
20120284464Zero Overhead Block Floating Point Implementation in CPU's - A system for computing a block floating point scaling factor by detecting a dynamic range of an input signal in a central processing unit without additional overhead cycles is provided. The system includes a dynamic range monitoring unit that detects the dynamic range of the input signal by snooping outgoing write data and incoming memory read data of the input signal. The dynamic range monitoring unit includes a running maximum count unit that stores a least value of a count of leading zeros and leading ones, and a running minimum count that stores a least value of the count of trailing zeros. The dynamic range is detected based on the least value of the count of leading zeros and leading ones and the count of trailing zeros. The system further includes a scaling factor computation module that computes the block floating point (BFP) scaling factor based on the dynamic range.11-08-2012
20130159637SYSTEM AND METHOD FOR OPTIMALLY CREATING STORAGE OBJECTS IN A STORAGE SYSTEM - Systems and methods that enable the optimal creation of a storage object within a virtual storage system are disclosed. In accordance with embodiments, an optimal location with the storage system is determined in response to receiving an indication that a storage object is to be created within the storage system. The system and method prioritize physical storage resources in which to create the storage object, prioritize components to be provided access to the created storage object, and prioritize the interface between the physical storage resources and the accessing component. The storage object is optimally created within the storage system based on the priorities and based, at least in part, on other created storage objects.06-20-2013
20130159638INFORMATION PROCESSING APPARATUS AND MEMORY ACCESS METHOD - A node includes a first converting unit that performs conversion between a logical address and a physical address. The node includes a second converting unit that performs conversion between the physical address and processor identification information for identifying a processor included in a each of a plurality of nodes. The node includes a transmitting unit that transmits transmission data including the physical address and the processor identification information for accessing a storing area indicated by the physical address. The node includes a local determining unit that determines whether an access, indicated by the transmission data received from another nodes, is an access to a local area or an access to a shared area based on the physical address included in the transmission data received by the receiving unit.06-20-2013
20130159639Optimizing for Page Sharing in Virtualized Java Virtual Machines - Methods, systems, and computer programs manage memory of a runtime environment executing on a virtual machine. A runtime environment, such as a Java Virtual Machine, may deterministically arrange immutable data within memory such that a hypervisor may perform page sharing on the immutable data. The runtime environment may page-align the immutable data within memory. The runtime environment may further store the immutable within memory using self-referenced or self-relative pointers.06-20-2013
20130159640SYSTEM AND METHOD OF READING AND WRITING OPERATING PARAMETERS AND DATA FOR A CONTROL DEVICE - The present disclosure provides a system for reading and writing operating parameters and real-time data for a control device. The system includes a power source, and a read/write device powered by the power source, the read/write device configured to conduct modulation of the power supply voltage based on a predetermined encoding mode. The system also includes a control device powered by the read/write device, wherein operating parameters and data information are exchanged between the control device and the read/write device, and the control device is configured to conduct demodulation of an output voltage transmitted by the read/write device. The system further includes power lines electrically connecting the power source to the read/write device and the read/write device to the control device.06-20-2013
20130159641NON-VOLATILE MEMORY STORAGE APPARATUS, MEMORY CONTROLLER AND DATA STORING METHOD - A non-volatile memory storage apparatus having a connector, an energy storage circuit, a power regulator and supply circuit, a non-volatile memory module, a memory controller and a buffer memory is provided. The power regulator and supply circuit is configured for transforming an output voltage from the energy storage circuit into a first voltage used for the non-volatile memory module and a second voltage used for the memory controller and the buffer memory. The memory controller is configured for writing data stored temporarily in the buffer memory into the non-volatile memory module with a special writing mode when receiving a detecting signal indicating that an input voltage is continuously smaller than a predetermined voltage for a predetermined period or receiving a detecting signal indicating that an inactive status of the connector or receiving a suspend mode signal, a warm reset signal or a hot reset signal from a host system.06-20-2013
20130185526SYSTEM FOR INCREASING UTILIZATION OF STORAGE MEDIA - A storage system creates an abstraction of flash Solid State Device (SSD) media allowing random write operations of arbitrary size by a user while performing large sequential write operations of a uniform size to an SSD array. This reduces the number of random write operations performed in the SSD array and as a result increases performance of the SSD array. A control element determines when blocks from different buffers should be combined together or discarded based on fragmentation and read activity. This optimization scheme increases memory capacity and improves memory utilization and performance.07-18-2013
20130185529AUTOMATED DEPLOYMENT OF SOFTWARE FOR MANAGED HARDWARE IN A STORAGE AREA NETWORK - In one aspect of the present description, a systems manager based upon a common model of information protocol or standard includes automated storage area network (SAN) expansion management which permits additional provider modules to be automatically installed if needed in response to devices being added to the SAN. In addition, the automated SAN expansion management permits installed provider modules to be automatically configured in response to devices being added to the SAN. Still further, in another aspect, the automated SAN expansion management can automatically determine if a suitable host processor exists to host installation of a new provider module and if not, the automated SAN expansion management can automatically deploy a suitable host processor such as a virtual server to host installation of a new provider module. Other features and aspects may be realized, depending upon the particular application.07-18-2013
20110296119Stored Data Reading Apparatus, Method and Computer Apparatus - The present invention proposes a stored data reading device, comprising a first storage module for storing first data, the first storage module has a first reading speed, a second storage module for storing second data, the second data being the same with at least a part of the first data, the second storage module having a second reading speed, and the second reading speed being greater than the first reading speed, a request acquiring module for acquiring a reading request for third data, the third data being the same with at least a part of the first data. With the stored data reading device of the invention, the data access speed can be accelerated while the production cost can be significantly lowered.12-01-2011
20110314229Error Detection for Files - Aspects of the subject matter described herein relate to error detection for files. In aspects, before allowing updates to a clean file, a flag marking the file as dirty is written to non-volatile storage. Thereafter, the file may be updated as long as desired. Periodically or at some other time, the file may be marked as clean after all outstanding updates to the file and error codes associated with the file are written to storage. While waiting for outstanding updates and error codes to be written to storage, if additional requests to update the file are received, the file may be marked as dirty again prior to allowing the additional requests to update the file. The request to write a clean flag regarding the file may be done lazily.12-22-2011
20110320747IDENTIFYING REPLACEMENT MEMORY PAGES FROM THREE PAGE RECORD LISTS - A replacement memory page is identified by accessing a first list of page records, and if the first list is not empty, identifying a replacement page from a next page record indicator of the first list. A second list of page records is accessed if the first list is empty, and if the second list is not empty, the replacement page is identified from a next page record indicator of the second list. A third list of page records is accessed if the first and second lists are empty, and the replacement page is identified from a next page record indicator of the third list.12-29-2011
20110320745DATA-SCOPED DYNAMIC DATA RACE DETECTION - A dynamic shared-memory data race detection tool with data-scoping capabilities to reduce runtime overheads is disclosed. The tool allows users to restrict analysis of memory locations to heap and/or stack variables that are of interest to them using explicit calls to functions provided in a library that is part of the race detection tool. The application code is instrumented to insert probes at all memory instructions and linked with the data race detection library to perform data-scoped race detection.12-29-2011
20120011329STORAGE APPARATUS AND STORAGE MANAGEMENT METHOD - Pages and files are placed in appropriate storage tiers by comprehensively judging the significance of the pages and files.01-12-2012
20120023298USING AN ADD-ON STORAGE DEVICE FOR EXTENDING THE STORAGE CAPACITY OF A STORAGE DEVICE IN A HOST DEVICE - A storage device with a memory, a controller, a storage device interface and a host interface, and a method of data transfer to and from a storage device are provided. The storage device is operative to connect with a host device and the storage device interface is operative to couple with an add-on memory. When the host interface is connected to a host device, the controller is configured to receive a data transfer command specifying a memory address from the host interface; and if the memory address is beyond the address space of the memory, to route the data transfer command to the storage device interface for access to the add-on memory. The address space of the memory and an address space of the add-on memory are addressed as one integral address space transparently to the host.01-26-2012
20120030435MEMORY DEVICE, MEMORY MANAGEMENT DEVICE, AND MEMORY MANAGEMENT METHOD - Disclosed is a memory device which receives a check command and check information from a Central Processing Unit (CPU), reads data written in a predetermined area of a memory based on the check information in response to the check command, and checks a data pattern of the data read based on the check information.02-02-2012
20120030434Memory Device - A memory device includes a memory array and a memory controller for altering a performance characteristic of the memory array to increase a rate at which the memory device writes data in response to the memory device experiencing a demand for bandwidth above a threshold. A method for adjusting the performance characteristics of a memory device includes altering a performance characteristic of the memory device in response to the memory device experiencing a demand for bandwidth above a threshold. Altering the performance characteristic increases a rate at which the memory device writes data.02-02-2012
20130198463RETRIEVAL OF INFORMATION FROM AN IMPLANTABLE MEDICAL DEVICE - Techniques for retrieving information from an implantable medical device (IMD) having a depleted internal energy source such as a non-rechargeable battery are disclosed. The IMD is powered by and communicates with an external interrogation device to access a memory location of the IMD and for transfer of the information in the memory location to the external interrogation device subsequent to depletion of the internal energy source. In an embodiment, the memory location is included in a non-volatile memory component of the IMD to maintain the information stored in the memory component.08-01-2013
20120297151MEMORY MANAGEMENT APPARATUS, MEMORY MANAGEMENT METHOD AND CONTROL PROGRAM - If it is determined in step S11-22-2012
20120042134METHOD AND SYSTEM FOR CIRCUMVENTING USAGE PROTECTION APPLICABLE TO ELECTRONIC MEDIA - A method for bypassing a compliance mechanism assertion of a usage restriction applicable to electronic media accessible in a computer system is described. The method includes a hardware device for causing the computer system to bypass the usage restriction, the hardware device communicatively coupled with the computer system and appropriate for reading from and writing to the storage device upon which the electronic media is disposed, the computer system having the compliance mechanism communicatively coupled to and operable therewith, the compliance mechanism for asserting the usage restriction. An application causing the computer system to bypass the usage restriction asserted by the compliance mechanism; and activating a presentation mechanism causing the computer system to present the electronic media in an unrestricted manner, the compliance mechanism unable to assert the usage restriction upon the presentation mechanism and the computer system.02-16-2012
20120066461MEMORY ARBITRATION SYSTEM AND METHOD HAVING AN ARBITRATION PACKET PROTOCOL - A memory hub and method for transmitting a read response on a data path of a memory hub interposed between a transmitting memory hub and a receiving memory hub. An arbitration packet including data indicative of a data path configuration for an associated read response is received at the memory hub. The arbitration packet is decoded, and the data path is configured in accordance with the data of the arbitration packet. The associated read response is received at the memory hub and the associated read response is coupled to the configured data path for transmitting the same to the receiving memory hub.03-15-2012
20120066460SYSTEM AND METHOD FOR PROVIDING SCATTER/GATHER DATA PROCESSING IN A MIDDLEWARE ENVIRONMENT - Systems and methods are provided for providing scatter/gather data processing. In accordance with an embodiment, a such a system can include a cluster of one or more high performance computing systems, each including one or more processors and a high performance memory. The cluster communicates over an InfiniBand network. The system can also include a middleware environment, executing on the cluster, that includes one or more application server instances. The system can further include a plurality of muxers. Each application server instance includes at least one muxer, and each muxer is operable to collect data from a plurality of locations in the high performance memory, and transfer the data in bulk.03-15-2012
20120066459SYSTEM AND METHOD FOR ZERO BUFFER COPYING IN A MIDDLEWARE ENVIRONMENT - Systems and methods are provided for zero buffer copying. In accordance with an embodiment, such a system can include one or more high performance computing systems, each including one or more processors and a high performance memory. The system can further include a user space, which includes a Java virtual machine (JVM) and one or more application server instances. Additionally, the system can include a plurality of byte buffers accesible to the JVM and the one or more application server instances. When a request is received by a first application server instance data associated with the request is stored in a heap space associated with the JVM, and the JVM pins the portion of the heap space where the data is stored. The data is pushed to a first byte buffer where it is accessed by the first application server instance. A response is generated by the first application server using the data, and the response is sent by the first application server.03-15-2012
20120066458STORAGE SYSTEM AND DATA TRANSFER METHOD OF STORAGE SYSTEM - A storage system comprises a storage apparatus that stores therein data used by an external apparatus, first and second temporary data storage units that temporarily store therein data to be written to the storage apparatus from the external apparatus or data read from the storage apparatus, a first data transfer controller communicatively coupled with the external apparatus, and the first and second temporary data storage units, and controls data transfer between the external apparatus, and the first and second temporary data storage units, a second data transfer controller communicatively coupled with the first and second temporary data storage units, and the storage apparatus, and controls data transfer between the first and second temporary data storage units, and the storage apparatus, a third data transfer controller communicatively coupled with the first and second temporary data storage units, that controls data transfer between the first and second temporary storage units, and performs a data processing function not included in the first and second data transfer controllers, and a data transfer control management unit that causes any one of a first data transfer process and a second data transfer process to be performed upon receipt of a data I/O request from the external apparatus, the first data transfer process executing data transfer between the external apparatus and the storage apparatus via the first temporary data storage unit under control of the first and second data transfer controllers, and the second data transfer process executing data transfer between the external apparatus or the storage apparatus and the second temporary data storage unit under control of the first and second data transfer controllers and executing data transfer between the first temporary data storage unit and the second temporary data storage unit under control of the third data transfer controller.03-15-2012
20130205104Finite State Machine for System Management - Implementations relate to a hybrid finite state machine that is based on a micro-coded processor and the use of look-up tables to implement combinational logic. Micro-coding is used to describe the state transitions of the FSM and look-up tables are used to determine the conditions for state transitions and to generate the outputs as a function of the state.08-08-2013
20130205105DMA CONTROLLER AND DATA READOUT DEVICE - A DMA controller comprises a reading start address register storing a reading start address from which reading starts; a reading data size register storing the size of data to be read in a single reading operation; an offset value register storing an offset value for updating the reading start address after the reading operation ends; a repetition upper limit value register storing the upper limit value of the number of times of repetition of the reading operation; and a repetition counter register storing the number of times of repetition of the reading operation. The controller of the DMA controller outputs an interrupt signal indicating that the processing of the DMA controller ends when the value stored in the repetition counter register reaches the value stored in the repetition upper limit value register.08-08-2013
20130205101DYNAMIC REAL STORAGE USAGE CONTROL - Provided are techniques for managing an amount of real storage used by a database management system. A value of a real storage management parameter is received, wherein the real storage management parameter indicates conditions under which one or more virtual storage pages are analyzed to identify one or more unused, virtual storage pages that are to be discarded. The database management system and consumption of real storage and auxiliary storage is monitored. In response to determining that the value of the real storage management parameter is set to on, the one or more unused virtual storage pages are discarded. In response to determining that the value of the real storage management parameter is set to auto and that paging has occurred, the one or more unused, virtual storage pages are discarded. Health values are recorded.08-08-2013
20130205103Computation Apparatus with Coordination of the Access to an Internal Memory and Operating Method - A programmable logic controller (PLC) with changing memory access times is intended to interact with a subordinate system, i.e., a discontinuous virtualized system, wherein a computation apparatus is provided, in which the PLC is implemented and in which the system that is subordinate to the PLC with respect to an operation to access the memory access is implemented. A memory to which a component of the PLC has access is integrated in the PLC. Also implemented in the computation apparatus is a proxy device that coordinates access to the memory of the PLC by the subordinate system such that simultaneous access by the component of the PLC has priority over access by the subordinate system and it is thus possible to ensure that the PLC always complies with a predefined cycle time of the PLC.08-08-2013
20130205102STORAGE CONTROL SYSTEM WITH ERASE BLOCK MECHANISM AND METHOD OF OPERATION THEREOF - A method of operation of a storage control system includes: partitioning memory channels with memory devices; selecting a super device with one of the memory devices from one of the memory channels, the super device having a super chip select connected to chip selects of the memory devices; and selecting a super block associated with the super device.08-08-2013
20120072681MEMORY CONTROL APPARATUS AND MEMORY CONTROL METHOD - Memory accesses to a memory device that is in a power saving mode depend on the order of the issuance thereof. Thus, a period of time during which the memory is placed in the power saving mode is sometimes shortened, resulting in less effective power savings. A memory control apparatus, which is connected with a plurality of masters and a plurality of memories having a power saving mode, arbitrates memory accesses from the plurality of the masters, monitors whether each of the plurality of the memories is in the power saving state, and determines the priorities of the memory accesses according to the result of the detection of the power saving mode.03-22-2012
20130212340PARTITION AWARE QUALITY OF SERVICE FEATURE - A method for providing a partition aware quality of service feature may include receiving an indication of data to be stored in a distributed memory grid, determining a quality of service policy rule to be applied in relation to storage of the data in the memory grid based on the indication, and initiating storage of data blocks of the data in the memory grid. The data blocks may be provided with corresponding partition identifiers that facilitate retrieval of the data by indicating a location of storage of respective ones of the data blocks within the memory grid. The method may further include providing a quality of service token in association with the partition identifier based on the quality of service policy rule.08-15-2013
20130212341MIX BUFFERS AND COMMAND QUEUES FOR AUDIO BLOCKS - The subject disclosure is directed towards a technology that may be used in an audio processing environment. Nodes of an audio flow graph are associated with virtual mix buffers. As the flow graph is processed, commands and virtual mix buffer data are provided to audio fixed-function processing blocks. Each virtual mix buffer is mapped to a physical mix buffer, and the associated command is executed with respect to the physical mix buffer. One physical mix buffer mix buffer may be used as an input data buffer for the audio fixed-function processing block, and another physical mix buffer as an output data buffer, for example.08-15-2013