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Dynamic random access memory

Subclass of:

711 - Electrical computers and digital processing systems: memory

711100000 - STORAGE ACCESSING AND CONTROL

711101000 - Specific memory composition

711104000 - Solid-state random access memory (RAM)

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Class / Patent application numberDescriptionNumber of patent applications / Date published
711106000 Refresh scheduling 75
Entries
DocumentTitleDate
20110208906SEMICONDUCTOR MEMORY DEVICE WITH PLURAL MEMORY DIE AND CONTROLLER DIE - A semiconductor memory device including a plurality of memory die and a controller die. The controller die is connected to an internal control bus. The controller die is configured to provide to a selected one of the memory die an internal read command responsive to an external read command. The selected memory die is configured to provide read data to the controller in response to the internal read command; wherein latency between receipt by the controller die of the external read command and receipt of the read data from the selected memory die differs for at least two of the memory die when selected as the selected memory die.08-25-2011
20120173810Method and Apparatus for Indicating Mask Information - An apparatus for controlling a dynamic random access memory (DRAM), the apparatus comprising an interface to transmit, over a first plurality of wires, to the DRAM a first code to indicate that first data is to be written to the DRAM and a column address to indicate a column location of a memory core in the DRAM where the first data is to be written. The interface is further to transmit a second code to indicate whether mask information for the first data will be sent to the DRAM. If the second code indicates that mask information will be sent, a portion of the column address and a portion of the mask information are sent after the second code is sent. The interface is further to transmit to the DRAM, over a second plurality of wires separate from the first plurality of wires, the first data.07-05-2012
20130185493MANAGING CACHING OF EXTENTS OF TRACKS IN A FIRST CACHE, SECOND CACHE AND STORAGE - Provided are a computer program product, system, and method for managing caching of extents of tracks in a first cache, second cache and storage device. A determination is made of an eligible track in a first cache eligible for demotion to a second cache, wherein the tracks are stored in extents configured in a storage device, wherein each extent is comprised of a plurality of tracks. A determination is made of an extent including the eligible track and whether second cache caching for the determined extent is enabled or disabled. The eligible track is demoted from the first cache to the second cache in response to determining that the second cache caching for the determined extent is enabled. Selection is made not to demote the eligible track in response to determining that the second cache caching for the determined extent is disabled.07-18-2013
20110202713Semiconductor Memory Asynchronous Pipeline - An asynchronously pipelined SDRAM has separate pipeline stages that are controlled by asynchronous signals. Rather than using a clock signal to synchronize data at each stage, an asynchronous signal is used to latch data at every stage. The asynchronous control signals are generated within the chip and are optimized to the different latency stages. Longer latency stages require larger delays elements, while shorter latency states require shorter delay elements. The data is synchronized to the clock at the end of the read data path before being read out of the chip. Because the data has been latched at each pipeline stage, it suffers from less skew than would be seen in a conventional wave pipeline architecture. Furthermore, since the stages are independent of the system clock, the read data path can be run at any CAS latency as long as the re-synchronizing output is built to support it.08-18-2011
20120246401IN-MEMORY PROCESSOR - A memory device includes at least two memory banks storing data and an internal processor. The at least two memory banks are accessible by a host processor. The internal processor receives a timeslot from the host processor and processes a portion of the data from an indicated one of the at least two banks of the memory array during the timeslot while the remaining banks are available to the host processor during the timeslot. A method of operating a memory device having banks storing data includes a host processor issuing per bank timeslots to an internal processor of a memory device, the internal processor operating on an indicated bank of the memory device during the timeslot and the host processor not accessing the indicated bank during the timeslot.09-27-2012
20100077139MULTI-PORT DRAM ARCHITECTURE - Embodiments of the invention provide a memory device that may be accessed by a plurality of controllers or processor cores via respective ports of the memory device. Each controller may be coupled to a respective port of the memory device via a data bus. Each port of the memory device may be associated a predefined section of memory, thereby giving each controller access to a distinct section of memory without interference from other controllers. A common command/address bus may couple the plurality of controllers to the memory device. Each controller may assert an active signal on a memory access control bus to gain access to the command/address bus to initiate a memory access.03-25-2010
20130080693HYBRID MEMORY DEVICE, COMPUTER SYSTEM INCLUDING THE SAME, AND METHOD OF READING AND WRITING DATA IN THE HYBRID MEMORY DEVICE - A hybrid memory device includes a DRAM and a non-volatile memory. When a program is executed for the first time by a central processing unit (CPU), and data is copied to the DRAM from an external memory device, the data is also copied to the non-volatile memory. The non-volatile memory is configured to directly output data stored therein to an exterior without passing through the DRAM.03-28-2013
20130086315DIRECT MEMORY ACCESS WITHOUT MAIN MEMORY IN A SEMICONDUCTOR STORAGE DEVICE-BASED SYSTEM - In general, embodiments of the present invention provide an approach for direct memory access (DMA) without main memory for a semiconductor storage device (SSD)-based system. Specifically, in a typical embodiment, an input/output hub (IOH) is provided with an inter-DMA engine. The IOH is coupled to a central processing unit (CPU), a set of double data rate (DDR) SSD memory disk units, and a graphics card. The graphics card can comprise a cache memory unit or other type of memory unit. Among other things, this embodiment provides one or more of the following features: interchangeability of hardware; resource allocation for DMA in the CPU utilizes inter-DMA resources; direct data transfer to the graphics card/processor; and/or no need to depend on a main memory comment needed in previous approaches.04-04-2013
20130036264MULTI-RANK MEMORY MODULE THAT EMULATES A MEMORY MODULE HAVING A DIFFERENT NUMBER OF RANKS - A transparent four rank memory module has a front side and a back side. The front side has a third memory rank stacked on a first memory rank. The back side has a fourth memory rank stacked on a second memory rank. An emulator coupled to the memory module activates and controls one individual memory rank from either the first memory rank, the second memory rank, the third memory rank, or the fourth memory rank based on the signals received from a memory controller.02-07-2013
20130036263SOLID STATE STORAGE DEVICE USING VOLATILE MEMORY - A solid state storage device using volatile memory comprises a first transmission interface, a memory controller, a memory module and a backup memory module. The memory module is comprised of a plurality of volatile memories. The backup memory module is comprised of a plurality of non-volatile memories. A plurality of volatile memories and a plurality of non-volatile memories are electrically coupled with the memory controller via memory connecting sockets. Before power failure, the memory controller controls the memory module to save internal data backup to the backup memory module. In addition, the memory controller controls memory module to save internal backup data back to the backup memory module when required.02-07-2013
20130042059PAGE MERGING FOR BUFFER EFFICIENCY IN HYBRID MEMORY SYSTEMS - In a first embodiment of the present invention, a method for managing memory in a hybrid memory system is provided, wherein the hybrid memory system has a first memory and a second memory, wherein the first memory is smaller than the second memory and the first and second memories are of different types, the method comprising: identifying two or more pages in the first memory that are compatible with each other based at least in part on a prediction of when individual blocks within each of the two or more pages will be accessed; merging the two or more compatible pages, producing a merged page; and storing the merged page in the first memory.02-14-2013
20090172270DEVICE, SYSTEM, AND METHOD OF MEMORY ALLOCATION - Device, system, and method of memory allocation. For example, an apparatus includes: a Dual In-line Memory Module (DIMM) including a plurality of Dynamic Random Access Memory (DRAM) units to store data, wherein each DRAM unit includes a plurality of banks and each bank is divided into a plurality of sub-banks; and a memory management unit to allocate a set of interleaved sub-banks of said DIMM to a memory page of an Operating System, wherein a combined memory size of the set of interleaved sub-banks is equal to a size of the memory page of the Operating System.07-02-2009
20100042779Implementing Vector Memory Operations - In one embodiment, the present invention includes an apparatus having a register file to store vector data, an address generator coupled to the register file to generate addresses for a vector memory operation, and a controller to generate an output slice from one or more slices each including multiple addresses, where the output slice includes addresses each corresponding to a separately addressable portion of a memory. Other embodiments are described and claimed.02-18-2010
20100042778Memory System Such as a Dual-Inline Memory Module (DIMm) and Computer System Using the Memory System - A memory system (02-18-2010
20100106900Semiconductor memory device and method thereof - A semiconductor memory device and method thereof are provided. The example method may be directed to performing a memory operation in a semiconductor memory device, and may include receiving data and a data masking signal corresponding to at least a portion of the received data, the received data scheduled to be written into memory in response to a write command and the data masking signal configured to block the at least a portion of the received data from being written into the memory and configuring timing parameters differently for each of the received data and the data masking signal so as to execute the write command without writing the at least a portion of the received data into the memory.04-29-2010
20080282029STRUCTURE FOR DYNAMIC OPTIMIZATION OF DYNAMIC RANDOM ACCESS MEMORY (DRAM) CONTROLLER PAGE POLICY - A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design for dynamic optimization of DRAM controller page policy is provided. The design structure can include a memory module, which can include multiple different memories, each including a memory controller coupled to a memory array of memory pages. Each of the memory pages in turn can include a corresponding locality tendency state. A memory bank can be coupled to a sense amplifier and configured to latch selected ones of the memory pages responsive to the memory controller. Finally, the module can include open page policy management logic coupled to the memory controller. The logic can include program code enabled to granularly change open page policy management of the memory bank responsive to identifying a locality tendency state for a page loaded in the memory bank.11-13-2008
20130046925Mechanisms To Accelerate Transactions Using Buffered Stores - In one embodiment, the present invention includes a method for executing a transactional memory (TM) transaction in a first thread, buffering a block of data in a first buffer of a cache memory of a processor, and acquiring a write monitor on the block to obtain ownership of the block at an encounter time in which data at a location of the block in the first buffer is updated. Other embodiments are described and claimed.02-21-2013
20130046924Mechanisms To Accelerate Transactions Using Buffered Stores - In one embodiment, the present invention includes a method for executing a transactional memory (TM) transaction in a first thread, buffering a block of data in a first buffer of a cache memory of a processor, and acquiring a write monitor on the block to obtain ownership of the block at an encounter time in which data at a location of the block in the first buffer is updated. Other embodiments are described and claimed.02-21-2013
20130046923MEMORY SYSTEM AND METHOD FOR PASSING CONFIGURATION COMMANDS - A memory system is provided. In the system, there are first and second sets of dynamic random access memories (DRAMs) and a system register. Each DRAM has at least a first and a second addressable mode register, where the binary address of the second mode register is the inverted binary address of the first mode register. The system register has an input configured to be coupled to a controller, an output coupled to the first set of DRAMs via first address lines and an inverted output coupled to the second set of DRAMs via second address lines. The system register is configured to receive mode register set commands including address bits and configuration bits at the input and to output the mode register set commands non-inverted via the output to the first set of DRAMs and in inverted form via the inverted output to the second set of DRAMs.02-21-2013
20090043955Configurable high-speed memory interface subsystem - A memory interface subsystem including a write logic and a read logic. The write logic may be configured to communicate data from a memory controller to a memory. The read logic may be configured to communicate data from the memory to the memory controller. The read logic may comprise a plurality of physical read datapaths. Each of the physical read datapaths may be configured to receive (i) a respective portion of read data signals from the memory, (ii) a respective read data strobe signal associated with the respective portion of the received read data signals, (iii) a gating signal, (iv) a base delay signal and (v) an offset delay signal.02-12-2009
20090043953MEMORY CONTROL METHODS CAPABLE OF DYNAMICALLY ADJUSTING SAMPLING POINTS, AND RELATED CIRCUITS - A memory control method for adjusting sampling points utilized by a memory control circuit receiving a data signal and an original data strobe signal of a memory includes: utilizing at least one delay unit to provide a plurality of sampling points according to the original data strobe signal; sampling according to the data signal by utilizing the plurality of sampling points; and analyzing sampling results to dynamically determine a delay amount for delaying the original data strobe signal, whereby a sampling point corresponding to the delayed data strobe signal is kept centered at data carried by the data signal.02-12-2009
20090307418Multi-channel hybrid density memory storage device and control method thereof - The present invention discloses a control method of a multi-channel hybrid density memory storage device for access a user data. The storage device includes a plurality of low density memories (LDM) and high density memories (HDM). The steps of the method comprises: first, determining where the user data transmitted; then, using one of two error correction circuits which have different error correction capability to encode or decode the user data.12-10-2009
20090307417INTEGRATED BUFFER DEVICE - An integrated buffer device. One embodiment provides a receiving unit and a logic unit to control the operation of the buffer device based on a setting signal.12-10-2009
20120191907SYSTEMS, METHODS, AND APPARATUSES FOR IN-BAND DATA MASK BIT TRANSMISSION - Embodiments of the invention are generally directed to systems, methods, and apparatuses for in-band data mask bit transmission. In some embodiments, one or more data mask bits are integrated into a partial write frame and are transferred to a memory device via the data bus. Since the data mask bits are transferred via the data bus, the system does not need (costly) data mask pin(s). In some embodiments, a mechanism is provided to enable a memory device (e.g., a DRAM) to check for valid data mask bits before completing the partial write to the DRAM array.07-26-2012
20130060997MITIGATING BUSY TIME IN A HIGH PERFORMANCE CACHE - Various embodiments of the present invention mitigate busy time in a hierarchical store-through memory cache structure. In one embodiment, a cache directory associated with a memory cache is divided into a plurality of portions each associated with a portion memory cache. Simultaneous cache lookup operations and cache write operations between the plurality of portions of the cache directory are supported. Two or more store commands are simultaneously processed in a shared cache pipeline communicatively coupled to the plurality of portions of the cache directory.03-07-2013
20130060996System and Method for Controller Independent Faulty Memory Replacement - In accordance with the present disclosure, a system and method for controller independent faulty memory replacement is described. The system includes a system memory component with a system memory component architecture. The system also includes a memory buffer coupled to the system memory component. The memory buffer may include at least one spare memory location corresponding to a faulty memory location of the system memory component. Additionally, the system memory component architecture may receive a read command directed to an address of the system memory component containing the faulty memory location and output, in response to the read command, data corresponding to the address from both the system memory component and the at least one spare memory component.03-07-2013
20120226852CONTROL METHOD AND CONTROLLER FOR DRAM - A DRAM controller including a judging module, a determination module, and a transmission module is provided. The judging module judges an address content difference between a first command and a third command. The determination module determines a plurality of buffering address contents, asoociated with at least one second command, according to the address content difference. The transmission module then sequentially transmits the first command, the at least one second command, and the third command to the DRAM.09-06-2012
20130067157SEMICONDUCTOR STORAGE DEVICE HAVING MULTIPLE HOST INTERFACE UNITS FOR INCREASED BANDWIDITH - Embodiments of the present invention provide a semiconductor storage device (SSD)-based storage system. Specifically, in a typical embodiment, the system comprises a SSD memory disk unit having (among other components) a plurality of host interface units coupled to a host interface controller. The plurality of host interface units communicate with a plurality of physical interface units of a device driver (e.g., on a one-to-one or one-to-multiple basis). The device driver also comprises a logical interface coupled to the plurality of physical interface units. Among other things, this allows the system to connect to multiple hosts. In addition, this design provides increased bandwidth.03-14-2013
20130067156DOUBLE DATA RATE CONTROLLER HAVING SHARED ADDRESS AND SEPARATE DATA ERROR CORRECTION - In general, embodiments of the present invention provide a double data rate (DDR) controller having a shared address and separate data error direction for DDR3 direct memory access (DMA). In a typical embodiment, the architecture described herein comprises a fields programmable gate array (FPGA) having a single memory controller coupled to a data multiplexer (MUX). Groups/sets of memory having individual dual inline memory modules (DIMMs) are coupled to the memory controller and the data MUX. Data flows between the DIMMs and the data multiplexer, while address and control information flows between the DIMMs and the memory controller.03-14-2013
20120117318HETEROGENEOUS COMPUTING SYSTEM COMPRISING A SWITCH/NETWORK ADAPTER PORT INTERFACE UTILIZING LOAD-REDUCED DUAL IN-LINE MEMORY MODULES (LR-DIMMS) INCORPORATING ISOLATION MEMORY BUFFERS - A heterogeneous computing system comprising a switch/network adapter port interface utilizing load-reduced dual in-line memory modules (LR-DIMMs) incorporating isolation memory buffers. In a particular embodiment of the present invention the computer system comprises at least one dense logic device and a controller coupling it to a memory bus. A plurality of memory slots are coupled to the memory bus and an adaptor port is associated with some number of the plurality of memory slots, each of the adapter ports including associated memory resources. A direct execution logic element is coupled to at least one of the adapter ports. The memory resources are selectively accessible by the at least one dense logic device and the direct execution logic element.05-10-2012
20090235019SECURING SAFETY-CRITICAL VARIABLES - A system comprises a general-purpose memory, a lockable memory, a memory management unit, and a processor. The general-purpose memory includes data for a first set of addresses. The lockable memory includes data for a second set of addresses. The memory management unit selectively writes data to one of the general-purpose memory and the lockable memory and selectively locks the lockable memory by preventing writes to the lockable memory. The processor instructs the memory management unit to unlock the lockable memory before requesting a write to one of the second set of addresses.09-17-2009
20090006730DATA EYE MONITOR METHOD AND APPARATUS - An apparatus and method for providing a data eye monitor. The data eye monitor apparatus utilizes an inverter/latch string circuit and a set of latches to save the data eye for providing an infinite persistent data eye. In operation, incoming read data signals are adjusted in the first stage individually and latched to provide the read data to the requesting unit. The data is also simultaneously fed into a balanced XOR tree to combine the transitions of all incoming read data signals into a single signal. This signal is passed along a delay chain and tapped at constant intervals. The tap points are fed into latches, capturing the transitions at a delay element interval resolution. Using XORs, differences between adjacent taps and therefore transitions are detected. The eye is defined by segments that show no transitions over a series of samples. The eye size and position can be used to readjust the delay of incoming signals and/or to control environment parameters like voltage, clock speed and temperature.01-01-2009
20130166836CONFIGURABLE MEMORY CONTROLLER/MEMORY MODULE COMMUNICATION SYSTEM - A memory system includes a first memory module and a second memory module. A memory controller is coupled to the first and second memory modules and reads configuration information from the first and second memory modules using a memory channel. The controller also configures a switch coupled between the controller and one of the memory modules to communicate using either a chip select line or a memory address line.06-27-2013
20130166834SUB PAGE AND PAGE MEMORY MANAGEMENT APPARATUS AND METHOD - A method and apparatus for managing a virtual address to physical address translation utilize a subpage level fault detecting and access. The method and apparatus may also use an additional subpage and page store Non-Volatile Store (NVS). The method and apparatus determines whether a page fault occurs or whether a subpage fault occurs to effect an address translation and also operates such that if a subpage fault had occurred, a subpage is loaded corresponding to the fault from a NVS to a DRAM, such as DRAM or any other suitable volatile memory historically referred to as main memory. The method and apparatus, if a page fault has occurred, determines if a page fault has occurred without operating system assistance and is a hardware page fault detection system that loads a page corresponding to the fault from NVS to DRAM.06-27-2013
20130166835ARITHMETIC PROCESSING SYSTEM AND METHOD, AND NON-TRANSITORY COMPUTER READABLE MEDIUM - An arithmetic processing system includes the following elements. Plural storage media, which are physically independent, having storage regions are provided. Plural processors execute processing by using the storage regions of the plural storage media. An allocating unit allocates the storage regions of the plural storage media to the plural processors. A determining unit determines whether a total value of storage amounts necessary for the plural processors to execute processing is equal to or smaller than a value obtained by subtracting a storage capacity of one of the storage media from a total capacity of the plural storage media. A reallocating unit reallocates the allocated storage regions to the plural processors when the above-described determination result is positive. A discontinuing unit discontinues an operation performed by a storage medium which does not contain any of the storage regions reallocated to the plural processors as a result of reallocating the storage regions.06-27-2013
20080294841APPARATUS FOR IMPLEMENTING ENHANCED VERTICAL ECC STORAGE IN A DYNAMIC RANDOM ACCESS MEMORY - A method and apparatus are provided for implementing enhanced vertical ECC storage in a dynamic random access memory. A dynamic random access memory (DRAM) is split into a plurality of groups. Each group resides inside a DRAM row address strobe (RAS) page so that multiple locations inside a group can be accessed without incurring an additional RAS access penalty. Each group is logically split into a plurality of segments for storing data with at least one segment for storing ECC for the data segments. For a write operation, data are written in a data segment and then ECC for the data are written in an ECC segment. For a read operation, ECC are read from an ECC segment, then data are read from the data segment.11-27-2008
20080294840READ/WRITE CHANNEL CODING AND METHODS FOR USE THEREWITH - A write channel includes a pre-encoding module that encodes write data to produce pre-encoded data. An error correcting code (ECC) module generates ECC data based on the pre-encoded data. A post-encoding module encodes the ECC data to produce post-encoded data. A combining module combines the pre-encoded data and the post-encoded data for writing to the storage medium.11-27-2008
20090031078Rank sparing system and method - A system, and a corresponding method, are used to implement rank sparing. The system includes a memory controller and one or more DIMM channels coupled to the memory controller, where each DIMM channel includes one or more DIMMS, and where each of the one or more DIMMs includes at least one rank of DRAM devices. The memory controller is loaded with programming to test the DIMMs to designate at least one specific rank of DRAM devices as a spare rank.01-29-2009
20110302367Write Buffer for Improved DRAM Write Access Patterns - The present invention relates to a method and respective system for operating a DRAM main memory. One buffer line is provided for multiple pages. When writing data to the buffer it is decided which to which buffer-line the data is written to based on its destination main memory address. A tuple consisting of lower memory address and data is stored. Data entered into the buffer-line will be sorted by page in case the line is flushed to the main memory. Sorting the buffer entries results in less page openings and closings, since the data is re-arranged by memory address and therefore in logical order. By using one line for multiple pages only a fraction of memory of a common set-associative cache is needed, thus decreasing the amount of overhead significantly.12-08-2011
20110289268FACILITATING COMMUNICATION BETWEEN MEMORY DEVICES AND CPUS - According to one embodiment, an apparatus comprises one or more memory devices and one or more processors coupled to a circuit board. The memory devices are configured according to a second memory technology. The processors are configured to receive messages conforming to a first memory technology, translate the messages from the first memory technology to the second memory technology, and send the translated messages to the memory devices.11-24-2011
20110289269MEMORY SYSTEM AND METHOD HAVING POINT-TO-POINT LINK - A memory system includes a controller for generating a control signal and a primary memory for receiving the control signal from the controller. A secondary memory is coupled to the primary memory, the secondary memory being adapted to receive the control signal from the primary memory. The control signal defines a background operation to be performed by one of the primary and secondary memories and a foreground operation to be performed by the other of the primary and secondary memories. The primary memory and the secondary memory are connected by a point-to-point link. At least one of the links between the primary and secondary memories can be an at least partially serialized link. At least one of the primary and secondary memories can include an on-board internal cache memory.11-24-2011
20110296096Method And Apparatus For Virtualized Microcode Sequencing - In one embodiment, the present invention includes a processor having multiple cores and an uncore. The uncore may include a microcode read only memory to store microcode to be executed in the cores (that themselves do not include such memory). The cores can include a microcode sequencer to sequence a plurality of micro-instructions (uops) of microcode that corresponds to a macro-instruction to be executed in an execution unit of the corresponding core. Other embodiments are described and claimed.12-01-2011
20110296095DATA MOVEMENT ENGINE AND MEMORY CONTROL METHODS THEREOF - A data movement engine (DME) for an electronic device is disclosed. The DME has an address generating module and a direct memory access (DMA) module. When the memory is switched to a lower power consumption state, a refresh area of a memory of the electronic device is refreshed and a non-refresh area of the memory is not refreshed. The address generating module obtains at least one source address of data in the non-refresh area, and generates at least one destination address for moving data from the non-refresh area to the refresh area and thereby a source-to-destination mapping table is generated. The DMA module performs a first data movement to move data from the non-refresh area to the refresh area according to the source-to-destination mapping table and independently of a microprocessor of the electronic device.12-01-2011
20090119451Redriven/Retimed Registered Dual Inline Memory Module - A memory module may include a plurality of dynamic random access memory (DRAM) chips, each of which may have one or more data input/output (D/Q) terminals. The memory module may include data redriving/retiming circuits connected to the D/Q terminals of the plurality of DRAM chips. The data redriving/retiming circuits may provide isolation between a system memory bus and the D/Q terminals of the DRAM chips.05-07-2009
20100169562PROCESSING SYSTEM AND ELECTRONIC DEVICE WITH SAME - A processing system for use in an electronic device is disclosed. The processing system includes a memory unit, an application processor connected to the memory unit, and a baseband processor connected to the memory unit and the application processor. The memory unit is configured for storing information of the electronic device. The application processor is configured for handling applications of the electronic device. The baseband processor is configured for providing communication capabilities for the electronic device. The application processor includes a temperature detector configured for detecting the temperature of the application processor. When the sensed temperature of the application processor is higher than a predetermined temperature, the baseband processor is instructed by the application processor to share workload of the application processor.07-01-2010
20100274959METHODS FOR MAIN MEMORY WITH NON-VOLATILE TYPE MEMORY MODULES - A computing system is disclosed that includes a memory controller in a processor socket normally reserved for a processor. A plurality of non-volatile memory modules may be plugged into memory sockets normally reserved for DRAM memory modules. The non-volatile memory modules may be accessed using a data communication protocol to access the non-volatile memory modules. The memory controller controls read and write accesses to the non-volatile memory modules. The memory sockets are coupled to the processor socket by printed circuit board traces. The data communication protocol to access the non-volatile memory modules is communicated over the printed circuit board traces and through the sockets normally used to access DRAM type memory modules.10-28-2010
20090150602MEMORY POWER CONTROL - In a memory device to store information, the device includes a memory core to store information, a memory controller to control storage and retrieval of the information, and a regulator coupled to the memory controller and the memory core, wherein the regulator is operable to adjust an internal voltage to the memory core in response to commands from the memory controller.06-11-2009
20120110255METHOD AND APPARATUS FOR SENDING DATA FROM MULTIPLE SOURCES OVER A COMMUNICATIONS BUS - In a memory system, multiple memory modules communicate over a bus. Each memory module may include a hub and at least one memory storage unit. The hub receives local data from the memory storage units, and downstream data from one or more other memory modules. The hub assembles data to be sent over the bus within a data block structure, which is divided into multiple lanes. An indication is made of where, within the data block structure, a breakpoint will occur in the data being placed on the bus by a first source (e.g., the local or downstream data). Based on the indication, data from a second source (e.g., the downstream or local data) is placed in the remainder of the data block, thus reducing gaps on the bus. Additional apparatus, systems, and methods are disclosed.05-03-2012
20100037013MEMORY ACCESS METHOD - A memory access method intended for a memory required to provide an interval of a predetermined number of clock cycles or longer between successive occurrences of access when the same bank is successively accessed, and that eliminates an idle time between successive occurrences of access to allow for improved performance. Pieces of data are written into 0th, the first, the second, and the third banks, respectively. No idle time is caused between successive occurrences of access because different banks are successively accessed. Since a burst length of each of the pieces of data is eight, an interval of 16 cycles which is longer than 15 cycles is provided between a start of writing of first data and a start of second writing of data. Accordingly, no idle time is caused also between completion of writing of the first data and start of writing of the second data.02-11-2010
20120036315Morphing Memory Architecture - A memory circuit comprises a memory array including a plurality of memory cells, multiple word lines, and at least one bit line. Each of the memory cells is coupled to a unique pair of a bit line and a word line for selectively accessing the memory cells. The memory circuit further includes at least one control circuit coupled to the word lines and operative to selectively change an operation of the memory array between a first data storage mode and at least a second data storage mode as a function of at least one control signal supplied to the control circuit. In the first data storage mode, each of the memory cells is allocated to a corresponding stored logic bit, and in the second data storage mode, at least two memory cells are allocated to a corresponding stored logic bit.02-09-2012
20100082894COMMUNICATION SYSTEM AND METHOS BETWEEN PROCESSORS - A system communicating processors is provided. The system comprises a first processor, a second processor, a SRAM and a DMA unit. The DMA unit further comprises a detection unit to determine whether the SRAM is accessed by the second processor, wherein when the SRAM is not accessed by the second processor, the access control of the SRAM is transferred to the DMA unit, and data communication between the first processor and the second processor is transmitted by the DMA unit.04-01-2010
20100100670Out of Order Dram Sequencer - Memory access requests are successively received in a memory request queue of a memory controller. Any conflicts or potential delays between temporally proximate requests that would occur if the memory access requests were to be executed in the received order are detected, and the received order of the memory access requests is rearranged to avoid or minimize the conflicts or delays and to optimize the flow of data to and from the memory data bus. The memory access requests are executed in the reordered sequence, while the originally received order of the requests is tracked. After execution, data read from the memory device by the execution of the read-type memory access requests are transferred to the respective requestors in the order in which the read requests were originally received.04-22-2010
20080313394MOTHERBOARD AND MEMORY DEVICE THEREOF - A memory device can be directly mounted on a motherboard supporting DDR3 SDRAM, and then the memory device have advantages of the fly-by bus topology and the T branch topology established by the joint electron device engineering council (JEDEC). Thus, the system performance of a desktop computer in a unit interval can be enhanced.12-18-2008
20090089493SEMICONDUCTOR MEMORY, OPERATING METHOD OF SEMICONDUCTOR MEMORY, AND SYSTEM - Operation control circuits start a first operation of any of memory cores in response to a first operation command, start a second operation of any of the memory cores in response to a second operation command, and terminate the first operation and continue the second operation in response to a termination command to terminate operations of the plurality of memory cores. For example, the semiconductor memory is mounted on a system together with a controller accessing the semiconductor memory. The termination of the operation in response to the termination command is judged in accordance with an operation state of the memory core. Accordingly, it is possible to terminate the operation of the memory core requiring the termination of operation without specifying the memory core from outside.04-02-2009
20080209118MAGNETIC RANDOM ACCESS MEMORY AND MANUFACTURING METHOD THEREOF - A magnetic random access memory includes a semiconductor substrate in which a step portion having a side surface and a top face is formed, a gate electrode formed on the side surface of the step portion through a gate insulating film, a drain diffusion layer formed in the top face of the step portion, a source diffusion layer formed in the semiconductor substrate below the drain diffusion layer to be separated from the drain diffusion layer, a magnetoresistive effect element which is connected with the drain diffusion layer, and has a fixed layer, a recording layer and a non-magnetic layer, the magnetization directions of the fixed layer and the recording layer entering a parallel state or an antiparallel state in accordance with a direction of a current flowing through a space between the fixed layer and the recording layer, and a bit line connected with the magnetoresistive effect element.08-28-2008
20110173385Methods And Apparatus For Demand-Based Memory Mirroring - A method includes determining an amount of memory space in a memory device available for memory mirroring. The method further includes presenting the available memory space to an operating system. The method further includes selecting at least a portion of the amount of memory space to be used for memory mirroring with the operating system. The method further includes adding a non-selected portion of the available memory to memory space available to the operating system during operation. An associated system and machine readable medium are also disclosed.07-14-2011
20120297131Scheduling-Policy-Aware DRAM Page Management Mechanism - Memory controller page management devices, systems, and methods are disclosed in which a memory controller is configured to access memory in response to a memory access request by applying a scheduler-aware page management policy to at least one memory page based in the memory based on row buffer status information for the pending memory access requests scheduled in a current cycles.11-22-2012
20100146199Memory System Topologies Including A Buffer Device And An Integrated Circuit Memory Device - Systems, among other embodiments, include topologies (data and/or control/address information) between an integrated circuit buffer device (that may be coupled to a master, such as a memory controller) and a plurality of integrated circuit memory devices. For example, data may be provided between the plurality of integrated circuit memory devices and the integrated circuit buffer device using separate segmented (or point-to-point link) signal paths in response to control/address information provided from the integrated circuit buffer device to the plurality of integrated circuit buffer devices using a single fly-by (or bus) signal path. An integrated circuit buffer device enables configurable effective memory organization of the plurality of integrated circuit memory devices. The memory organization represented by the integrated circuit buffer device to a memory controller may be different than the actual memory organization behind or coupled to the integrated circuit buffer device. The buffer device segments and merges the data transferred between the memory controller that expects a particular memory organization and actual memory organization.06-10-2010
20100138597Information Processing System, System Controller, and Memory Control Method - According to one embodiment, an extreme data rate DRAM is a DRAM resetting data thereof in response to a reset signal. When power is initially supplied to a system, a system controller outputs the reset signal to the extreme data rate DRAM in response to a reset signal input from a memory controller through a level shifter. When shutting down power of a system while suspending data stored in the extreme data rate DRAM, the system controller shuts down power of the memory controller while maintaining supply of power to the extreme data rate DRAM in response to the reset signal input from the memory controller through the level shifter.06-03-2010
20090265509MEMORY SYSTEM AND METHOD HAVING VOLATILE AND NON-VOLATILE MEMORY DEVICES AT SAME HIERARCHICAL LEVEL - A processor-based system includes a processor coupled to core logic through a processor bus. This includes a dynamic random access memory (“DRAM”) memory buffer controller. The DRAM memory buffer controller is coupled through a memory bus to a plurality of a dynamic random access memory (“DRAM”) modules and a flash memory module, which are at the same hierarchical level from the processor. Each of the DRAM modules includes a memory buffer to the memory bus and to a plurality of dynamic random access memory devices. The flash memory module includes a flash memory buffer coupled to the memory bus and to at least one flash memory device. The flash memory buffer includes a DRAM-to-flash memory converter operable to convert the DRAM memory requests to flash memory requests, which are then applied to the flash memory device.10-22-2009
20080282028DYNAMIC OPTIMIZATION OF DYNAMIC RANDOM ACCESS MEMORY (DRAM) CONTROLLER PAGE POLICY - Embodiments of the present invention address deficiencies of the art in respect to memory management and provide a method, system and computer program product for dynamic optimization of DRAM controller page policy. In one embodiment of the invention, a memory module can include multiple different memories, each including a memory controller coupled to a memory array of memory pages. Each of the memory pages in turn can include a corresponding locality tendency state. A memory bank can be coupled to a sense amplifier and configured to latch selected ones of the memory pages responsive to the memory controller. Finally, the module can include open page policy management logic coupled to the memory controller. The logic can include program code enabled to granularly change open page policy management of the memory bank responsive to identifying a locality tendency state for a page loaded in the memory bank.11-13-2008
20080235444SYSTEM AND METHOD FOR PROVIDING SYNCHRONOUS DYNAMIC RANDOM ACCESS MEMORY (SDRAM) MODE REGISTER SHADOWING IN A MEMORY SYSTEM - A system and method for providing SDRAM mode register shadowing in a memory system. A system includes a memory interface device adapted for use in a memory system. The memory interface device includes an interface to one or more ranks of memory devices, and each memory device includes one or more types of mode registers. The memory interface device also includes an interface to a memory bus for receiving commands from a memory controller. The commands include a mode register set command specifying a new mode register setting for one or more ranks of memory devices and a mode register type. The memory interface device further includes a mode register shadow module to capture settings applied to the mode registers. The module includes a shadow register for each type of mode register and a shadow log for each type of mode register. The module also includes mode register shadow logic to detect a mode register set command, to store the new mode register setting in the shadow register corresponding to the specified mode register type, and to set one or more bits in the shadow log corresponding to the specified mode register type to indicate which of the ranks of memory devices have been programmed with the new mode register setting.09-25-2008
20100005234Enabling functional dependency in a multi-function device - In one embodiment, the present invention includes a method for reading configuration information from a multi-function device (MFD), building a dependency tree of a functional dependency of functions performed by the MFD based on the configuration information, which indicates that the MFD is capable of performing at least one function dependent upon another function, and loading software associated with the functions in order based at least in part on the indicated functional dependency. Other embodiments are described and claimed.01-07-2010
20100146200NON-SNOOP READ/WRITE OPERATIONS IN A SYSTEM SUPPORTING SNOOPING - Techniques that may utilize generic tracker structures to provide data coherency in a multi-node system that supports non-snoop read and write operations. The trackers may be organized as a two-dimensional queue structure that may be utilized to resolve conflicting read and/or write operations. Multiple queues having differing associated priorities may be utilized.06-10-2010
20090031077INTEGRATED CIRCUIT INCLUDING MULTIPLE MEMORY DEVICES - An integrated circuit includes a data bus and a first memory device coupled to the data bus. The first memory device is configured to provide a first signal in response to completing a power-up sequence of the first memory device. The integrated circuit includes a second memory device coupled to the data bus. The second memory device is configured to provide a second signal in response to completing a power-up sequence of the second memory device. The integrated circuit includes a controller configured to access the first memory device and the second memory device based on the first signal and the second signal.01-29-2009
20110125961DRAM Control Method and the DRAM Controller Utilizing the Same - A Dynamic Random Access Memory (DRAM) controller for controlling read and write operations of a DRAM includes a storage unit and a control unit. The storage unit stores a first predetermined size of data including data written into the DRAM in response to a previous partial write request, and stores the corresponding store addresses of the first predetermined size of data in the DRAM. The control unit, in response to a read request, determines whether there exists any address in the store addresses equal to a read address of the read request, and read data corresponding to the read address from the storage unit when there exists same address in the store addresses equal to the read address.05-26-2011
20120036316EMBEDDED-DRAM PROCESSING APPARATUS AND METHODS - An embedded-DRAM processor architecture includes a DRAM array, a set of register files, set of functional units, and a data assembly unit. The data assembly unit includes a set of row-address registers and is responsive to commands to activate and deactivate DRAM rows and to control the movement of data throughout the system. A pipelined data assembly approach allowing the functional units to perform register-to-register operations, and allowing the data assembly unit to perform all load/store operations using wide data busses. Data masking and switching hardware allows individual data words or groups of words to be transferred between the registers and memory. Other aspects of the disclosure include a memory and logic structure and an associated method to extract data blocks from memory to accelerate, for example, operations related to image compression and decompression.02-09-2012
20110208907Protected Cache Architecture And Secure Programming Paradigm To Protect Applications - Embodiments of the present invention provide a secure programming paradigm, and a protected cache that enable a processor to handle secret/private information while preventing, at the hardware level, malicious applications from accessing this information by circumventing the other protection mechanisms. A protected cache may be used as a building block to enhance the security of applications trying to create, manage and protect secure data. Other embodiments are described and claimed.08-25-2011
20130219115DELAY CIRCUIT, DELAY CONTROLLER, MEMORY CONTROLLER, AND INFORMATION TERMINAL - A delay circuit of the present disclosure includes a first delay unit and a second delay unit which are connected in series and delay an input signal to generate a delayed signal. The first delay unit includes a first signaling pathway, and changes, based on a first delay control value, a first amount of delay to be provided to the input signal by switching signaling pathways for transmitting the input signal that are within the first pathway. The second delay unit includes a second signaling pathway, and changes, based on a second delay control value, a second amount of delay to be provided to the input signal without switching the second signaling pathway for transmitting the input signal.08-22-2013
20090187704METHOD AND SYSTEM FOR SECURE CODE ENCRYPTION FOR PC-SLAVE DEVICES - A PC-slave device may securely load and decrypt an execution code and/or data, which may be stored, encrypted, in a PC hard-drive. The PC-slave device may utilize a dedicated memory, which may be partitioned into an accessible region and a restricted region that may only be accessible by the PC-slave device. The encrypted execution code and/or may be loaded into the accessible region of the dedicated memory; the PC-slave device may decrypt the execution code and/or data, internally, and store the decrypted execution code and/or data into the restricted region of the dedicated memory. The decrypted execution code and/or data may be validated, and may be utilized from the restricted region. The partitioning of the dedicated memory, into accessible and restricted regions, may be performed dynamically during secure code loading. The PC-slave device may comprise a dedicated secure processor that may perform and/or manage secure code loading.07-23-2009
20110225354ELECTRONIC APPARATUS - An electronic apparatus includes a memory control circuit that controls a first memory and a second memory, the first memory is connected to the memory control circuit through a first data bus, the second memory is connected to the memory control circuit through the first data bus and a second data bus, and a sum of bus widths of the first data bus and the second data bus is larger than the bus width of the first data bus by a times. When the memory control circuit receives an access request for the second memory, the memory control circuit generates a command for accessing the second memory b times on the basis of an address of the access request point and accesses the second memory.09-15-2011
20090024790MEMORY CIRCUIT SYSTEM AND METHOD - A memory circuit system and method are provided in the context of various embodiments. In one embodiment, an interface circuit remains in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for performing various functionality (e.g. power management, simulation/emulation, etc.).01-22-2009
20090024789MEMORY CIRCUIT SYSTEM AND METHOD - A memory circuit system and method are provided in the context of various embodiments. In one embodiment, an interface circuit remains in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for performing various functionality (e.g. power management, simulation/emulation, etc.).01-22-2009
20090063761 Buffered Memory Module Supporting Two Independent Memory Channels - A memory system is provided that enhances the memory bandwidth available through a memory module. The memory system includes a memory controller and a memory module coupled to the memory controller. In the memory system, the memory controller is coupled to the memory module via at least two independent memory channels. In the memory system, the at least two independent memory channels are coupled to one or more memory hub devices of the memory module.03-05-2009
20120144104Partitioning of Memory Device for Multi-Client Computing System - A method, computer program product, and system are provided for accessing a memory device. For instance, the method can include partitioning one or more memory banks of the memory device into a first and a second set of memory banks. The method also can allocate a first plurality of memory cells within the first set of memory banks to a first memory operation of a first client device and a second plurality of memory cells within the second set of memory banks to a second memory operation of a second client device. This memory allocation can allow access to the first and second sets of memory banks when a first and a second memory operation are requested by the first and second client devices, respectively. Further, access to a data bus between the first client device, or the second client device, and the memory device can also be controlled based on whether the first memory address or the second memory address is accessed to execute the first or second memory operation.06-07-2012
20110231601PROVIDING HARDWARE RESOURCES HAVING DIFFERENT RELIABILITIES FOR USE BY AN APPLICATION - Power management functionality is described for implementing an application in an energy-efficient manner, without substantially degrading overall performance of the application. The functionality operates by identifying at least first data and second data associated with the application. The first data is considered to have a greater potential impact on performance of the application compared to the second data. The functionality then instructs a first set of hardware-level resources to handle the first data and a second set of hardware-level resources to handle the second data. The first set of hardware-level resources has a higher reliability compared to the second set of hardware-level resources. In one case, the first and second hardware-level resources comprise DRAM memory units. Here, the first set of hardware-level resources achieves greater reliability than the second set of hardware-level resources by being refreshed at a higher rate than the second set of hardware-level resources.09-22-2011
20090204752MEMORY DEVICE AND REFRESH ADJUSTING METHOD - When a single error of data is detected by an ECC circuit, a cycle adjusting unit provided on a memory board shortens a refresh cycle T08-13-2009
20090254700DRAM CONTROLLER FOR GRAPHICS PROCESSING OPERABLE TO ENABLE/DISABLE BURST TRANSFER - An interface unit 10-08-2009
20090248970DUAL EDGE COMMAND - A technique to increase transfer rate of command and address signals via a given number of command and address pins in each of one or more integrated circuit memory devices during a clock cycle of a clock signal. In one example embodiment, the command and address signals are sent on both rising and falling edges of a clock cycle of a clock signal to increase the transfer rate and essentially reduce the number of required command and address pins in each integrated circuit memory device.10-01-2009
20090248971System and Dynamic Random Access Memory Device Having a Receiver - A dynamic random access memory device (DRAM) receiver circuit includes an input to receive a data signal, and also includes decision circuitry to make a decision about the received data signal based on a present sampled data signal and a coefficient value corresponding to at least one of a previously sampled data signals.10-01-2009
20090254699Synchronous dynamic random access memory interface and method - A memory interface allows access to SDRAM by receiving a column address for a data read or write of a burst of data units. Each data unit in the burst has an expected bit size. The interface generates n (n>1) column memory addresses from the received column address. The interface accesses the synchronous dynamic memory to read or write n bursts of data at the n column memory addresses. Preferably, the SDRAM is clocked at n times the rate of the interconnected memory accessing device, and the memory units. The data units in the n bursts preferably have one n10-08-2009
20090254697MEMORY WITH EMBEDDED ASSOCIATIVE SECTION FOR COMPUTATIONS - An integrated circuit device includes a semiconductor substrate and an array of random access memory (RAM) cells, which are arranged on the substrate in first columns and are configured to store data. A computational section in the device includes associative memory cells, which are arranged on the substrate in second columns, which are aligned with respective first columns of the RAM cells and are in communication with the respective first columns so as to receive the data from the array of the RAM cells and to perform an associative computation on the data.10-08-2009
20100037014MEMORY DEVICE, MEMORY SYSTEM AND DUAL PORT MEMORY DEVICE WITH SELF-COPY FUNCTION - A memory device with a self-copy function includes a memory cell array having first and second banks, and a memory interface. The memory interface reads data from a memory area of the first bank corresponding to a source address contained in previously set self-copy information and writes the read data to a memory area of the second bank corresponding to a destination address contained in the self-copy information via a self-copy data path when a self-copy signal is activated by an external self-copy start request.02-11-2010
20090248969REGISTERED DIMM MEMORY SYSTEM - A Registered DIMM (RDIMM) system with reduced electrical loading on the data bus for increases memory capacity and operation frequency. In one embodiment, the data bus is buffered on the DIMM. In another embodiment, the data bus is selectively coupled to a group of memory chips via switches.10-01-2009
20090259809MEMORY ACCESS APPARATUS AND DISPLAY USING THE SAME - A memory access apparatus and a display using the same are provided. The memory access apparatus includes a dynamic memory, a plurality of clients and a memory management unit. The dynamic memory is used to store a plurality of memory data. The clients access the dynamic memory and each client has a priority. The memory management unit executes an access action of the clients for the dynamic memory respectively according to the priorities thereof. Besides, the memory management unit has at least one buffer area built therein. The buffer area is used to temporarily store a plurality of buffer data generated while the access action is performed.10-15-2009
20100153636CONTROL SYSTEM AND METHOD FOR MEMORY ACCESS - A control system for memory access includes a system memory access command buffer, a memory access command parallel processor, a DRAM command controller and a read data buffer. The system memory access command buffer stores plural system memory access commands. The memory access command parallel processor is connected to the system memory access command buffer for fetching and decoding the system memory access commands to plural DRAM access commands, storing the DRAM access commands in DRAM bank command FIFOs, and performing priority setting according to a DRAM bank priority table. The DRAM command controller is connected to the memory access command parallel processor and a DRAM for receiving the DRAM access commands, and sending control commands to the DRAM. The read data buffer is connected to the DRAM command controller and the system bus for storing the read data and rearranging a sequence of the read data.06-17-2010
20100153637Arbitration for memory device with commands - A plurality of masters arbitrate for access to a shared memory device, such as a SDRAM (synchronous dynamic random access memory), amongst themselves using software and arbitration interfaces. The masters generate additional commands upon arbitration, such as MRS and PALL commands, for prevention of collision of commands, refresh starvation, and/or a missing pre-charge operation in the shared memory device.06-17-2010
20080229007Enhancements to an XDR Memory Controller to Allow for Conversion to DDR2 - A memory control apparatus includes a data stream format converter and a physical layer converter. The data stream format converter is configured to convert an incoming data stream that has a data stream format corresponding to a first memory type into a format-converted data stream that has a data stream format corresponding to a second memory type. The second memory type is different from the first memory type. The physical layer converter is configured to convert the format-converted data stream into a physical-layer-converted data stream that has at least one physical parameter corresponding to the second memory type. The format-converted data stream has at least one physical parameter corresponding to the first memory type.09-18-2008
20120303885MULTIPLE PROCESSOR SYSTEM AND METHOD INCLUDING MULTIPLE MEMORY HUB MODULES - A processor-based electronic system includes several memory modules arranged in first and second ranks. The memory modules in the first rank are directly accessed by any of several processors, and the memory modules in the second rank are accessed by the processors through the memory modules in the first rank. The data bandwidth between the processors and the memory modules in the second rank is varied by varying the number of memory modules in the first rank that are used to access the memory module in the second set. Each of the memory modules includes several memory devices coupled to a memory hub. The memory hub includes a memory controller coupled to each memory device, a link interface coupled to a respective processor or memory module, and a cross bar switch coupling any of the memory controllers to any of the link interfaces.11-29-2012
20100185810IN-DRAM CYCLE-BASED LEVELIZATION - Systems and methods are provided for in-DRAM cycle-based levelization. In a multi-rank, multi-lane memory system, an in-DRAM cycle-based levelization mechanism couples to a memory device in a rank and individually controls additive write latency and/or additive read latency for the memory device. The in-DRAM levelization mechanism ensures that a distribution of relative total write or read latencies across the lanes in the rank is substantially similar to that in another rank.07-22-2010
20120198144DYNAMICALLY SETTING BURST LENGTH OF DOUBLE DATA RATE MEMORY DEVICE BY APPLYING SIGNAL TO AT LEAST ONE EXTERNAL PIN DURING A READ OR WRITE TRANSACTION - A microprocessor system having a microprocessor and a double data rate memory device having separate groups of external pins adapted to receive addressing, data, and control information and a memory controller adapted to set a burst type of the double data rate memory to interleaved or sequential by sending a signal through one of the external pins of the double data rate memory device, such that when a read command is sent by the controller, depending on the burst type set, the double data rate memory device returns interleaved or sequentially output data to the memory controller.08-02-2012
20100217928Semiconductor Memory Asynchronous Pipeline - An asynchronously pipelined SDRAM has separate pipeline stages that are controlled by asynchronous signals. Rather than using a clock signal to synchronize data at each stage, an asynchronous signal is used to latch data at every stage. The asynchronous control signals are generated within the chip and are optimized to the different latency stages. Longer latency stages require larger delays elements, while shorter latency states require shorter delay elements. The data is synchronized to the clock at the end of the read data path before being read out of the chip. Because the data has been latched at each pipeline stage, it suffers from less skew than would be seen in a conventional wave pipeline architecture. Furthermore, since the stages are independent of the system clock, the read data path can be run at any CAS latency as long as the re-synchronizing output is built to support it.08-26-2010
20100228910Single-Port SRAM and Method of Accessing the Same - A system and method for resolving request collision in a single-port static random access memory (SRAM) are disclosed. A first SRAM part and a second SRAM part of the single-port SRAM are accessed in turn. When request collision occurs, data is temporarily stored in a first or second shadow bank associated with the first or the second SRAM part which is under access. The temporarily stored data is then transferred, at a later time, to an associated one of the first/second SRAM parts while the other one of the first/second SRAM parts is being accessed.09-09-2010
20090043954Information Recording/Playback Apparatus and Memory Control Method - This information recording/playback apparatus has a memory for storing data and which includes a plurality of storage cells configured from a capacitor for accumulating charge. When an issue interval time for issuing a read/write command to an arbitrary storage cell is shorter than a threshold time for retaining a charge amount for the arbitrary storage cell to read correct data, a dummy read command for simulatively reading data stored in storage cells other than the arbitrary storage cell is issued to storage cells other than the arbitrary storage cell, and dummy read processing is executed for replenishing charge in the capacitor configuring storage cells other than the arbitrary storage cell.02-12-2009
20100250841Memory controlling device - A memory controlling device includes: a request generating section; a row selecting information retaining section; a column selecting information retaining section; a memory bank information managing section; a command generating section; and a command aligning section.09-30-2010
20100211728APPARATUS AND METHOD FOR BUFFERING DATA BETWEEN MEMORY CONTROLLER AND DRAM - A apparatus is provided for buffering data between a memory controller and a DRAM. The apparatus includes a phase locked loop (PLL), a phase interpolator for aligning a phase of an output clock signal in response to a phase aligning control word, and a non-volatile storage location permanently storing the phase aligning control word. The phase aligning control word is determined through an initial training procedure of the device under predetermined training conditions of at least a supply voltage level and a temperature, and the predetermined training conditions are set so as to optimize the phase alignment of an edge of the output clock signal with respect to the buffered data signal.08-19-2010
20100199034METHOD AND APPARATUS FOR ADDRESS FIFO FOR HIGH BANDWIDTH COMMAND/ADDRESS BUSSES IN DIGITAL STORAGE SYSTEM - A method of buffering a data stream in an electronic device using a first-in first-out (FIFO) buffer system wherein a first read latch signal does not change a pointer location of a read pointer. A dynamic random access memory (DRAM) and system are also disclosed in accordance with the invention to include a FIFO buffer system to buffer memory addresses and commands within the DRAM until corresponding data is available.08-05-2010
20090327596MEMORY CONTROLLER USING TIME-STAGGERED LOCKSTEP SUB-CHANNELS WITH BUFFERED MEMORY - Memory control techniques for dual channel lockstep configurations are disclosed. In accordance with one example embodiment, a memory controller issues two burst-length 4 DRAM commands to two double-data-rate (DDR) DRAM sub-channels behind a memory buffer (e.g., FB-DIMM or buffer-on-board). The two commands are in time-staggered lockstep. The time-stagger allows data coming back from the two back-side DDR sub-channels to flow naturally on the host channel without conflict. Multiple DIMMs can be used to obtain chip-fail ECC capabilities and to reclaim at least some of the lost performance imposed by the burst-length of 4 s typically associated with dual channel lockstep memory controllers. The techniques can be implemented, for instance, with a buffered memory solution such as fully buffered DIMM (FB-DIMM) or buffer-on-board configurations.12-31-2009
20110113189MULTIPLE PROCESSOR SYSTEM AND METHOD INCLUDING MULTIPLE MEMORY HUB MODULES - A processor-based electronic system includes several memory modules arranged in first and second ranks. The memory modules in the first rank are directly accessed by any of several processors, and the memory modules in the second rank are accessed by the processors through the memory modules in the first rank. The data bandwidth between the processors and the memory modules in the second rank is varied by varying the number of memory modules in the first rank that are used to access the memory module in the second set. Each of the memory modules includes several memory devices coupled to a memory hub. The memory hub includes a memory controller coupled to each memory device, a link interface coupled to a respective processor or memory module, and a cross bar switch coupling any of the memory controllers to any of the link interfaces.05-12-2011
20080313393Device for writing data into memory - A device for writing data into a memory and a method thereof. The memory comprises a plurality of memory arrays. Each of the memory arrays comprises a plurality of memory cells. The data are divided into a plurality of segments. The segments are written into first memory cells of the memory cells of the memory arrays in sequence. The segments start being written into the second memory cells of the memory cells of the memory arrays when the first memory cells of the memory cells of the memory arrays are full, and so forth, till the operation of writing the segments into the memory is completed.12-18-2008
20120198145MEMORY ACCESS APPARATUS AND DISPLAY USING THE SAME - A memory access apparatus and a display using the same are provided. The memory access apparatus includes a dynamic memory, a plurality of clients and a memory management unit. The dynamic memory is used to store a plurality of memory data. The clients access the dynamic memory and each client has a priority. The memory management unit executes an access action of the clients for the dynamic memory respectively according to the priorities thereof. Besides, the memory management unit has at least one buffer area built therein. The buffer area is used to temporarily store a plurality of buffer data generated while the access action is performed.08-02-2012
20120198143Memory Package Utilizing At Least Two Types of Memories - A memory package and methods for writing data to and reading data from the memory package are presented. The memory package includes a volatile memory and a high-density memory. Data is written to the memory package at a bandwidth and latency associated with the volatile memory. A directory map associates a volatile memory address with data in the high-density memory. A copy of the directory map is stored in the high-density memory. The methods allow writing to and reading from the memory package using a first memory read/write interface (e.g. DRAM interface, etc.), though data is stored in a device of a different memory type (e.g. FLASH, etc.).08-02-2012
20100223426Variable-width memory - Described is a memory system in which the memory core organization changes with device width. The number of physical memory banks accessed reduces with device width, resulting in reduced power usage for relatively narrow memory configurations. Increasing the number of logic memory banks for narrow memory widths reduces the likelihood of bank conflicts, and consequently improves speed performance.09-02-2010
20100306461MEMORY SYSTEM AND METHOD HAVING VOLATILE AND NON-VOLATILE MEMORY DEVICES AT SAME HIERARCHICAL LEVEL - A processor-based system includes a processor coupled to core logic through a processor bus. This includes a dynamic random access memory (“DRAM”) memory buffer controller. The DRAM memory buffer controller is coupled through a memory bus to a plurality of a dynamic random access memory (“DRAM”) modules and a flash memory module, which are at the same hierarchical level from the processor. Each of the DRAM modules includes a memory buffer to the memory bus and to a plurality of dynamic random access memory devices. The flash memory module includes a flash memory buffer coupled to the memory bus and to at least one flash memory device. The flash memory buffer includes a DRAM-to-flash memory converter operable to convert the DRAM memory requests to flash memory requests, which are then applied to the flash memory device.12-02-2010
20100306460MEMORY CONTROLLER, SYSTEM, AND METHOD FOR ACCESSING SEMICONDUCTOR MEMORY - A memory controller includes a sorting determination circuit which activates a sorting signal when an access request address for wrapping access to at least one memory block of a semiconductor memory is different from a first leading address of the at least one memory block, an address conversion circuit which sets the first leading address to an access starting address when the sorting signal is activated, a first data sorting circuit which sorts, when the sorting signal is activated, data sequentially read from the semiconductor memory in accordance with the access starting address starting from data corresponding to the access request address and a first output circuit which outputs the sorted data to an external bus.12-02-2010
20090070524NON-SNOOP READ/WRITE OPERATIONS IN A SYSTEM SUPPORTING SNOOPING - Techniques that may utilize generic tracker structures to provide data coherency in a multi-node system that supports non-snoop read and write operations. The trackers may be organized as a two-dimensional queue structure that may be utilized to resolve conflicting read and/or write operations. Multiple queues having differing associated priorities may be utilized.03-12-2009
20100306459Memory Controllers - Techniques pertaining the designs of memory controller are disclosed. According to one aspect of the present invention, a memory controller reduces delays in a data strobe signal of a DDR memory relative to a clock signal of a memory controller thereof. In one embodiment, the memory controller employs four IO ports, two inverters, six edge triggers and a multiplexer. By feeding back an inverted clock signal and utilizing the rising and filing edges of the clock signal, the delays in a data strobe signal of a DDR memory relative to a clock signal of a memory controller are considerably reduced or minimized.12-02-2010
20100312955MEMORY SYSTEM AND METHOD OF MANAGING THE SAME - A memory system to manage a memory using a virtual memory is provided. The memory system may use an asymmetric memory as a swap storage of a dynamic random access memory (DRAM). The asymmetric memory may access on a byte basis, allowing a process to directly access a page swapped out to the asymmetric memory through direct mapping.12-09-2010
20130138877METHOD AND APPARATUS FOR DISTRIBUTED DIRECT MEMORY ACCESS FOR SYSTEMS ON CHIP - A distributed direct memory access (DMA) method, apparatus, and system is provided within a system on chip (SOC). DMA controller units are distributed to various functional modules desiring direct memory access. The functional modules interface to a systems bus over which the direct memory access occurs. A global buffer memory, to which the direct memory access is desired, is coupled to the system bus. Bus arbitrators are utilized to arbitrate which functional modules have access to the system bus to perform the direct memory access. Once a functional module is selected by the bus arbitrator to have access to the system bus, it can establish a DMA routine with the global buffer memory.05-30-2013
20100332743SYSTEM AND METHOD FOR WRITING CACHE DATA AND SYSTEM AND METHOD FOR READING CACHE DATA - A system and a method for writing cache data and a system and a method for reading cache data are disclosed. The system for writing the cache data includes: an on-chip memory device, configured to cache received write requests and write data associated with the write requests and sort the write requests; a request judging device, configured to extract the sorted write requests and the write data associated with the write requests according to write time sequence restriction information of an off-chip memory device; and an off-chip memory device controller, configured to write the write data extracted by the request judging device in the off-chip memory device. With a combination of the on-chip and off-chip memory devices, a large-capacity data storage space and a high-speed read and write efficiency is achieved.12-30-2010
20110010494MEMORY CONTROL CIRCUIT AND MEMORY CONTROL METHOD - The memory control circuit has an access count setting circuit and a DRAM access control circuit. The access count setting circuit receives a minimum activation interval time for different rows in the same bank of the SDRAM, an operating speed, and the number of banks, and calculates an optimal number of readings or writings to each bank. The DRAM access control circuit generates a command sequence and an address for reading or writing a image signal to the SDRAM.01-13-2011
20110016270RAPID STARTUP COMPUTER SYSTEM AND METHOD - A computer system includes a north bridge chipset, a south bridge chipset, a memory, and a rapid startup apparatus. The rapid startup apparatus includes a DRAM module to install application programs or operation system programs, a battery, a control chip to control data reading and writing for the DRAM module, a PCI-E interface, and a switch circuit. The application programs or the operation system programs are loaded into the memory via the PCI-E interface, the south bridge chipset, and the north bridge chipset in series. The switch circuit processes voltage of the battery or the PCI-E interface and supply power to the DRAM module.01-20-2011
20110035544MULTI-PATH ACCESSIBLE SEMICONDUCTOR MEMORY DEVICE HAVING MAILBOX AREAS AND MAILBOX ACCESS CONTROL METHOD THEREOF - A multipath accessible semiconductor memory device having a mailbox area and a mailbox access control method thereof are provided. The semiconductor memory device includes N number of ports, at least one shared memory area allocated in a memory cell array, and N number of mailbox areas for message communication. The at least one shared memory area is operationally connected to the N number of ports, and is accessible through a plurality of data input/output lines to form a data access path between the at least one shared memory area and one port, having an access right to the at least one memory area, among the N number of ports. The N number of mailbox areas are provided in one-to-one correspondence with the N number of ports and are accessible through the plurality of data input/output lines when an address of a predetermined area of the at least one shared memory area is applied to the semiconductor memory device. An efficient layout of mailboxes and an efficient message access path can be obtained.02-10-2011
20110119440DYNAMIC PROGRAMMABLE INTELLIGENT SEARCH MEMORY - Memory architecture provides capabilities for high performance content search. The architecture creates an innovative memory derived using randomly accessible dynamic memory circuits that can be programmed with content search rules which are used by the memory to evaluate presented content for matching with the programmed rules. When the content being searched matches any of the rules programmed in the dynamic Programmable Intelligent Search Memory (PRISM) action(s) associated with the matched rule(s) are taken. Content search rules comprise of regular expressions which are converted to finite state automata and then programmed in dynamic PRISM for evaluating content with the search rules.05-19-2011
20110145493Independently Controlled Virtual Memory Devices In Memory Modules - Various embodiments of the present invention are directed a multi-core memory modules. In one embodiment, a memory module (06-16-2011
20110145492POLYMORPHOUS SIGNAL INTERFACE BETWEEN PROCESSING UNITS - A single interconnect is provided between a first processor and a second processor, such that the first processor may access a common memory through the second processor while the second processor can be mostly powered off. The first processor accesses the memory through a memory controller using a standard dynamic random access memory (DRAM) bus protocol. Instead of the memory controller directly connecting to the memory, the access path is through the second processor to the memory. Additionally, a bidirectional communication protocol bus is mapped to the existing DRAM bus signals. When both the first processor and the second processor are active, the bus protocol between the processors switches from the DRAM protocol to the bidirectional communication protocol. This enables the necessary chip-to-chip transaction semantics without requiring the additional cost burden of a dedicated interface for the bidirectional communication protocol.06-16-2011
20100138598MEMORY DEVICES WITH BUFFERED COMMAND ADDRESS BUS - Circuits and methods are provided that alleviate overloading of the command address bus and limit decreases in command address bus bandwidth to allow increased numbers of memory modules to be included in a computer system. A plurality of switches is coupled between the command address bus (which is coupled to the memory controller) and a respective plurality of memory modules. Each switch provides command address bus data only to its respective memory module. Preferably, only one switch does so at a time, limiting the loading seen by the memory controller.06-03-2010
20110082971INFORMATION HANDLING SYSTEM MEMORY MODULE OPTIMIZATION - A memory system includes a first memory module and a second memory module. A memory controller is coupled to the first and second memory modules and reads configuration information from the first and second memory modules using a memory channel. The controller also configures a switch coupled between the controller and one of the memory modules to communicate using either a chip select line or a memory address line.04-07-2011
20110087834Memory Package Utilizing At Least Two Types of Memories - A memory system and methods for memory manage are presented. The memory system includes a volatile memory electrically connected to a high-density memory; a memory controller that expects data to be written or read to or from the memory system at a bandwidth and a latency associated with the volatile memory; a directory within the volatile memory that associates a volatile memory address with data stored in the high-density memory; and redundant storage in the high-density memory that stores a copy of the association between the volatile memory address and the data stored in the high-density memory. The methods for memory management allow writing to and reading from the memory system using a first memory read/write interface (e.g. DRAM interface, etc.), though data is stored in a device of a different memory type (e.g. FLASH, etc.).04-14-2011
20090210616MEMORY MODULES FOR TWO-DIMENSIONAL MAIN MEMORY - In one embodiment of the invention, a memory module is disclosed including a printed circuit board with an edge connector; an address controller coupled to the printed circuit board; and a plurality of memory slices. Each of the plurality of memory slices of the memory module includes one or more memory integrated circuits coupled to the printed circuit board, and a slave memory controller coupled to the printed circuit board and the one or more memory integrated circuits. The slave memory controller receives memory access requests for the memory module from the address controller. The slave memory controller selectively activates one or more of the one or more memory integrated circuits in the respective memory slice in response to the address received from the address controller to read data from or write data into selected memory locations in the memory integrated circuits.08-20-2009
20090327597DUAL INTERFACE MEMORY ARRANGEMENT AND METHOD - The present invention provides for a dual interface memory arrangement employing the checkered memory mapping formed from combined vertically and horizontally sliced memory mapping, and including 2D access means arranged for access to the mapping memory wherein the said to the access means is arranged such that the access overlaps memory mapped to both interfaces both horizontally and vertically, and which arrangement preferably provides for two DTL channels for each interface wherein a highly efficient unified memory arrangement can be achieved for all processing aspects such as CPU, audio, video and gfx processing.12-31-2009
20100037015MEMORY CONTROL UNIT AND MEMORY CONTROL METHOD - An object of the invention is to provide a memory control unit and a memory control method capable of making the operation setting of SDRAM without intentionally stopping access to the SDRAM.02-11-2010
20100064099INPUT-OUTPUT MODULE, PROCESSING PLATFORM AND METHOD FOR EXTENDING A MEMORY INTERFACE FOR INPUT-OUTPUT OPERATIONS - Embodiments of an I/O module, processing platform, and method for extending a memory interface are generally described herein. In some embodiments, the I/O module may be configured to operate in a memory module socket, such as a DIMM socket, to provide increased I/O functionality in a host system. Some system management bus address lines and some unused system clock signal lines may be reconfigured as serial data lines for serial data communications between the I/O module and a PCIe switch of the host system.03-11-2010
20090216939Emulation of abstracted DIMMs using abstracted DRAMs - One embodiment of the present invention sets forth an abstracted memory subsystem comprising abstracted memories, which each may be configured to present memory-related characteristics onto a memory system interface. The characteristics can be presented on the memory system interface via logic signals or protocol exchanges, and the characteristics may include any one or more of, an address space, a protocol, a memory type, a power management rule, a number of pipeline stages, a number of banks, a mapping to physical banks, a number of ranks, a timing characteristic, an address decoding option, a bus turnaround time parameter, an additional signal assertion, a sub-rank, a number of planes, or other memory-related characteristics. Some embodiments include an intelligent register device and/or, an intelligent buffer device. One advantage of the disclosed subsystem is that memory performance may be optimized regardless of the specific protocols used by the underlying memory hardware devices.08-27-2009
20100070697Memory Controller Circuit, Electronic Apparatus Controller Device and Multifunction Apparatus - A memory controller circuit configured to control an SDRAM is provided. The memory controller circuit includes a first unit configured to accept an access request provided by one of a plurality of masters for access to a page included in the SDRAM. The memory controller circuit includes a second unit configured to record an access request period of each of the masters. The memory controller circuit includes a third unit configured to set an open period of the page on the basis of the access request period recorded in the second unit in accordance with the master having provided the access request. The third unit is configured to open the page requested to be accessed for the open period having been set.03-18-2010
20110179221MEMORY REGISTER ENCODING SYSTEMS AND METHODS - Apparatus, systems, and methods are disclosed that operate to encode register bits to generate encoded bits such that, for pairs of addresses, an encoded bit to be coupled to a first address in a memory device may be exchanged with an encoded bit to be coupled to a second address in the memory device. Apparatus, systems, and methods are disclosed that operate to invert encoded bits in logic circuits in the memory device if original bits were inverted. Additional apparatus, systems, and methods are disclosed.07-21-2011
20100064100SYSTEMS, METHODS, AND APPARATUSES FOR IN-BAND DATA MASK BIT TRANSMISSION - Embodiments of the invention are generally directed to systems, methods, and apparatuses for in-band data mask bit transmission. In some embodiments, one or more data mask bits are integrated into a partial write frame and are transferred to a memory device via the data bus. Since the data mask bits are transferred via the data bus, the system does not need (costly) data mask pin(s). In some embodiments, a mechanism is provided to enable a memory device (e.g., a DRAM) to check for valid data mask bits before completing the partial write to the DRAM array.03-11-2010
20100070696System and Method for Packaged Memory - In one embodiment, a memory system is disclosed. The memory system has at least one memory chip having an address and data interface coupled to an internal address and data bus, and a memory controller and interface chip also having a an address and data interface coupled to the address and data interface of the at least one memory chip via an internal address and data bus. The at least one memory chip, the memory controller and interface chip and the internal address and data bus are disposed within a common chip package. The memory controller and interface chip has an external interface configured to be coupled to a standard memory bus via external contacts of the common chip package.03-18-2010
20110252191METHOD OF DYNAMICALLY SWITCHING PARTITIONS, MEMORY CARD CONTROLLER AND MEMORY CARD STORAGE SYSTEM - A method of dynamically switching partitions for a memory card having a plurality of physical blocks is provided. The method includes configuring logical blocks for mapping to at least a portion of the physical blocks and dividing the logical blocks into first and second partitions; coupling the memory card to a host system and setting CSD corresponding to the memory card as a first default value corresponding to the first partition, wherein the host system requests the CSD to obtain the first default value and accesses the first partition according to the first default value; and setting the CSD corresponding to the memory card as a second default value corresponding to the second partition in response to a switch command from the host system, wherein the host system re-requests the CSD to obtain the second default value and accesses the second partition according to the second default value.10-13-2011
20110153925MEMORY CONTROLLER FUNCTIONALITIES TO SUPPORT DATA SWIZZLING - A memory controller that can determine a swizzling pattern between the memory controller and memory devices. The memory controller generates a swizzling map based on the determined swizzling pattern. The memory controller may internally swizzle data using the swizzling map before writing the data to memory so that the data appears in the correct order at the pins of the memory chip(s). On reads, the controller can internally de-swizzle the data before performing the error correction operations using the swizzling map.06-23-2011
20120303884IMPLEMENTING ENHANCED UPDATES FOR INDIRECTION TABLES - A method and a storage system are provided for implementing indirection tables and providing enhanced updates of the indirection tables for persistent media or disk drives, such as shingled perpendicular magnetic recording (SMR) indirection tables. A plurality of memory pools are used to store indirection data. An exception pointer table provides a pointer to an exception list for an I-Track. The exception list includes predetermined-size exception entries sorted by an offset from a start of the I-Track. An insert exception entry is provided for a new host write and merged to an updated exception list using an offset of the insert exception entry.11-29-2012
20120303883IMPLEMENTING STORAGE ADAPTER PERFORMANCE OPTIMIZATION WITH CACHE DATA/DIRECTORY MIRRORING - A method and controller for implementing storage adapter performance optimization with cache data and cache directory mirroring between dual adapters minimizing firmware operations, and a design structure on which the subject controller circuit resides are provided. One of the first controller or the second controller operates in a first initiator mode includes firmware to set up an initiator write operation building a data frame for transferring data and a respective cache line (CL) for each page index to the other controller operating in a second target mode. Respective initiator hardware engines transfers data, reading CLs from an initiator control store, and writing updated CLs to an initiator data store, and simultaneously sends data and updated CLs to the other controller. Respective target hardware engines write data and updated CLs to the target data store, eliminating firmware operations of the controller operating in the second target mode.11-29-2012
20110078370MEMORY LINK INITIALIZATION - Link initialization techniques to decouple the read training from the write training. Read training may be accomplished in a robust manner before write training is performed. These techniques may provide significantly improved link initialization times. A user-programmable register within a dynamic random access memory (DRAM) module may be utilized by the decoupled read training and write training processes. The decoupling may result in shorter and more robust training segments that may support faster training and/or increased link speeds.03-31-2011
20110072205MEMORY DEVICE AND MEMORY SYSTEM COMPRISING SAME - A memory device comprises a memory cell array comprising a plurality of memory blocks each comprising a plurality of memory cells and a control setting circuit. The control setting circuit divides the memory blocks into at least first and second groups based on whether each of the memory blocks comprises at least one substandard memory cell, and sets individually control parameters of the first and second groups. The substandard memory cells are identified based on test results of the memory cells with respect to at least one of the control parameters. Each memory block in the first group comprises at least one substandard memory cell, and each memory block in the second group comprises no substandard memory cell.03-24-2011
20120124281APPARATUS AND METHOD FOR POWER MANAGEMENT OF MEMORY CIRCUITS BY A SYSTEM OR COMPONENT THEREOF - An apparatus and method are provided for communicating with a plurality of physical memory circuits. In use, at least one virtual memory circuit is simulated where at least one aspect (e.g. power-related aspect, etc.) of such virtual memory circuit(s) is different from at least one aspect of at least one of the physical memory circuits. Further, in various embodiments, such simulation may be carried out by a system (or component thereof), an interface circuit, etc.05-17-2012
20110016268PHASE CHANGE MEMORY IN A DUAL INLINE MEMORY MODULE - Subject matter disclosed herein relates to management of a memory device.01-20-2011
20110016269SYSTEM AND METHOD OF INCREASING ADDRESSABLE MEMORY SPACE ON A MEMORY BOARD - A load-reducing memory module includes a plurality of memory components such as DRAMs. The memory components are organized into sets or ranks such that they can be accessed simultaneously for the full data bit-width of the memory module. A plurality of load reducing switching circuits is used to drive data bits from a memory controller to the plurality of memory components. The load reducing switching circuits are also used to multiplex the data lines from the memory components and drive the data bits to the memory controller.01-20-2011
20100306458Memory device having integral instruction buffer - A dynamic random access memory integrated circuit includes an interface to a serial interconnect, where the interface is configured to receive a plurality of memory access instructions over the serial interconnect, and a buffer configured to store the plurality of memory access instructions prior to execution of the buffered memory access instructions by the dynamic random access memory integrated circuit. The memory access instructions are received over at least one serial link that forms the serial interconnect, and the at least one serial link may be a shared bi-directional serial link or a uni-directional serial link.12-02-2010
20110153926Controlling Access To A Cache Memory Using Privilege Level Information - In one embodiment, a cache memory includes entries each to store a ring level identifier, which may indicate a privilege level of information stored in the entry. This identifier may be used in performing read accesses to the cache memory. As an example, a logic coupled to the cache memory may filter an access to one or more ways of a selected set of the cache memory based at least in part on a current privilege level of a processor and the ring level identifier of the one or more ways. Other embodiments are described and claimed.06-23-2011
20110252192EFFICIENT FLASH MEMORY-BASED OBJECT STORE - Approaches for an object store implemented, at least in part, on one or more solid state devices. The object store may store objects on a plurality of solid state devices. The object store may include a transaction model means for ensuring that the object store performs transactions in compliance with atomicity, concurrency, isolation, and durability (ACID) properties. The object store may include means for providing parallel flushing in a write cache maintained on each of the solid state devices. The object store may include means for maintaining one or more double-write buffers, for the object store, at a location other than the solid state devices. The object store may optionally comprise means for maintaining one or more circular transaction logs, for the object store, at a location other than the solid state devices. The object store may operate to minimize write operations performed on the solid state devices.10-13-2011
20100057983METHOD AND APPARATUS FOR AN ACTIVE LOW POWER MODE OF A PORTABLE COMPUTING DEVICE - The present invention discloses a portable computing device (03-04-2010
20100005235COMPUTER SYSTEM - A computer system includes a CPU and a system on chip (SoC) processor electronically connected with the CPU in the computer system. The CPU and the SoC processor do not work simultaneously. The CPU processes work and a service when the computer system is powered on. The SoC processor continues processing the work and the service that are unfinished after the computer system is shut down.01-07-2010
20100005233STORAGE REGION ALLOCATION SYSTEM, STORAGE REGION ALLOCATION METHOD, AND CONTROL APPARATUS - There are provided a memory space allocation method and a memory space allocation device that aim at higher-speed accesses when a memory is shared by a plurality of circuits. In this memory, one data is accessed by issuing addresses a plurality of times. Memory allocation is performed so that high-order addresses of memory spaces of an external memory 01-07-2010
20120203961HIGH SPEED INTERFACE FOR DYNAMIC RANDOM ACCESS MEMORY (DRAM) - An interface for a dynamic random access memory (DRAM) includes an interface element coupled to a DRAM chip using a first attachment structure, a first portion of the first attachment structure being used to form a wide bandwidth, low speed, parallel interface, a second portion of the first attachment structure, a routing element and a through silicon via (TSV) associated with the DRAM chip being used to form a narrow bandwidth, high speed, serial interface, the interface element configured to convert parallel information to serial information and configured to convert serial information to parallel information.08-09-2012
20090254698MULTI PORT MEMORY DEVICE WITH SHARED MEMORY AREA USING LATCH TYPE MEMORY CELLS AND DRIVING METHOD - A multiport semiconductor memory device includes; first and second port units respectively coupled to first and second processors, first and second dedicated memory area accessed by first and second processors, respectively and implemented using DRAM cells, a shared memory area commonly accessed by the first and second processors via respective first and second port units and implemented using memory cells different from the DRAM cells implementing the first and second dedicated memory areas, and a port connection control unit controlling data path configuration between the shared memory area and the first and second port units to enable data communication between the first and second processors through the shared memory area.10-08-2009
20110153924CORE SNOOP HANDLING DURING PERFORMANCE STATE AND POWER STATE TRANSITIONS IN A DISTRIBUTED CACHING AGENT - A method and apparatus may provide for detecting a performance state transition in a processor core and bouncing a core snoop message on a shared interconnect ring in response to detecting the performance state transition. The core snoop message may be associated with the processor core, wherein a plurality of processor cores may be coupled to the shared interconnect ring via a distributed last level cache controller.06-23-2011
20090240874FRAMEWORK FOR USER-LEVEL PACKET PROCESSING - A method of processing network packets can include allocating a first portion of a physical memory device to kernel-space control and allocating a second portion of the physical memory device to direct user-space process control. Network packets can be received from a computer network, and the received network packets can be written to the second portion of the physical memory without writing the received packets to the first portion of the physical memory. The network packets can be processed with a user-space application program that directly accesses the packets that have been written to the second portion of physical memory, and the processed packets can be sent over the computer network09-24-2009
20080244168METHOD AND APPARATUS FOR A PRIMARY OPERATING SYSTEM AND AN APPLIANCE OPERATING SYSTEM - One embodiment includes a personal computer device comprising at least one machine to execute a primary user operating system, a first physical memory to be used by the primary user operating system, at least one appliance operating system that is independent from the primary user operating system, a second physical memory to be sequestered from the primary user operating system and an access violation monitor to restrict access from the at least one appliance operating system to the second physical memory, wherein the access violation monitor is to run only when the at least one appliance operating system is invoked and at least one appliance operating system is to be invoked only after the primary user operating system has been suspended to a standby state.10-02-2008
20080320215Semiconductor memory device and method for operating semiconductor memory device - A semiconductor memory device includes a memory array section configured to serve as an information storage area and an interface section configured to interface between an external memory controller and the memory array section, the memory array section and the interface section being sealed in a package. The interface section includes a plurality of interface modules configured to correspond to a plurality of memory types on a one-to-one basis, and a clock generation section configured to generate a plurality of clock signals based on a system clock signal supplied by the external memory controller. The generated clock signals are used by the plurality of interface modules. The interface section further includes a mode interpretation section configured to interpret an input mode designation signal as indicative of one of the memory types in order to output a mode signal denoting the interpreted memory type.12-25-2008
20080270683SYSTEMS AND METHODS FOR A DRAM CONCURRENT REFRESH ENGINE WITH PROCESSOR INTERFACE - Systems and methods for a DRAM concurrent refresh engine with processor interface. In exemplary embodiments, memory cells requiring periodic refresh at least once each for a specified refresh interval and words of an array organized banks in which the banks are selected for access by a bank-enable signal, each bank having a word decoder accepting one of two refresh word addresses, one refresh word address for a normal access, and the other for a refresh access, one of the word addresses selected by two separate enable signals, provided by on-macro refresh logic, which includes instructions to select one bank for refresh when no normal access occurs and select one bank for refresh concurrently with a normal access having no bank conflicts, the refresh logic maintaining the refresh status, timing of the refresh interval, and insuring all memory cells are refreshed within the refresh interval.10-30-2008
20110161577DATA STORAGE SYSTEM, ELECTRONIC SYSTEM, AND TELECOMMUNICATIONS SYSTEM - A data storage system comprising a plurality of buffers configured to store data, a read pointer to indicate a particular one of the plurality of buffers from which data should be read, and a write pointer to indicate a particular one of the plurality of buffers to which data should be written is disclosed. The write pointer points at least one buffer ahead of the buffer to which the read pointer is pointing. An electronic system and a telecommunication system are further disclosed.06-30-2011
20110161576MEMORY MODULE AND MEMORY SYSTEM COMPRISING MEMORY MODULE - A memory module comprises a plurality of semiconductor memory devices each having a termination circuit for a command/address bus. The semiconductor memory devices are formed in a substrate of the memory module, and they operate in response to a command/address signal, a data signal, and a termination resistance control signal.06-30-2011
20110055469Providing State Storage In A Processor For System Management Mode - In one embodiment, the present invention includes a processor that has an on-die storage such as a static random access memory to store an architectural state of one or more threads that are swapped out of architectural state storage of the processor on entry to a system management mode (SMM). In this way communication of this state information to a system management memory can be avoided, reducing latency associated with entry into SMM. Embodiments may also enable the processor to update a status of executing agents that are either in a long instruction flow or in a system management interrupt (SMI) blocked state, in order to provide an indication to agents inside the SMM. Other embodiments are described and claimed.03-03-2011
20110022791High speed memory systems and methods for designing hierarchical memory systems - A system and method for designing and constructing hierarchical memory systems is disclosed. A plurality of different algorithmic memory blocks are disclosed. Each algorithmic memory block includes a memory controller that implements a specific storage algorithm and a set of lower level memory components. Each of those lower level memory components may be constructed with another algorithmic memory block or with a fundamental memory block. By organizing algorithmic memory blocks in various different hierarchical organizations, may different complex memory systems that provide new features may be created.01-27-2011
20110119439Spacing Periodic Commands to a Volatile Memory for Increased Performance and Decreased Collision - A periodic command spacing mechanism is provided for spacing periodic commands (e.g., refresh commands, ZQ calibration, etc.) to a volatile memory (e.g., SDRAM, DRAM, EDRAM, etc.) for increased performance and decreased collision. In one embodiment, periodic command requests are monitored and if a collision is detected between two or more of the requests, the colliding requests are spaced with respect to one another by a timer offset applied on a chip select basis. The periodic command spacing mechanism may be used in conjunction with command arbitration to make sure the periodic commands are executed without significantly impacting performance (e.g., Reads and Writes are allowed to flow). Preferably, the periodic command requests are initialized by generating an initial sequence of individual requests, each successive request in the initial sequence being generated spaced apart with respect to the previous request by a timer offset applied on a chip select basis.05-19-2011
20120311251Coordinating Memory Operations Using Memory-Device Generated Reference Signals - A memory system includes a memory controller coupled to multiple memory devices. Each memory device includes an oscillator that generates an internal reference signal that oscillates at a frequency that is a function of physical device structures within the memory device. The frequencies of the internal reference signals are thus device specific. Each memory device develops a shared reference signal from its internal reference signal and communicates the shared reference signal to the common memory controller. The memory controller uses the shared reference signals to recover device-specific frequency information from each memory device, and then communicates with each memory device at a frequency compatible with the corresponding internal reference signal.12-06-2012
20120311250ARCHITECTURE AND ACCESS METHOD OF HETEROGENEOUS MEMORIES - A heterogeneous memory architecture includes a first memory, a second memory and a memory controller. The first memory has a first memory space. The second memory has a second memory space larger than the first memory space. The memory controller is used for accessing common address space of the first memory and the second memory in a 2X-bit bandwidth, and for disabling the first memory and accessing non-common address space of the second memory in opposite to the first memory in a X-bit bandwidth, X being a positive integer.12-06-2012
20120311249MEMORY SYSTEM, MEMORY CONTROL METHOD, AND RECORDING MEDIUM STORING MEMORY CONTROL PROGRAM - A memory system includes a dual inline memory module (DIMM) connector to which a DIMM is connected, which is selected from a Joint Electron Device Engineering Council (JEDEC) standard DIMM in compliance with JEDEC standards and a customized DIMM not in compliance with JEDEC standard, and a memory controller to determine whether the DIMM being connected is the JEDEC standard DIMM or the customized DIMM to generate a determination result, and to control access to the DIMM based on the determination result and SPD information obtained from a SPD of the DIMM being connected.12-06-2012
20120311248CACHE LINE LOCK FOR PROVIDING DYNAMIC SPARING - A system that includes a memory, a cache, a purge mechanism, and a memory interface mechanism. The memory includes a failing memory element at a failing memory location. The cache is configured for storing corrected contents of the failing memory element in a locked state, with the corrected contents stored in a first cache line. The purge mechanism is configured for selecting and removing cache lines that are not in the locked state from the cache to make room for new cache allocations. The memory interface mechanism is configured for receiving a request to access the failing memory location, determining that corrected contents of the failing memory location are stored in first cache line in the cache, and accessing the first cache line in the cache.12-06-2012
20110093654Memory control - A data processing apparatus 04-21-2011
20110179220Memory Controller - A memory controller 07-21-2011
20090300278Embedded Programmable Component for Memory Device Training - A system and method by which a memory device can adapt or retrain itself in response to changes in its inputs or operating environment. The memory device, such as a DRAM, includes in its interface an embedded programmable component. The programmable component can be, for example and without limitation, a microprocessor, a microcontroller, or a microsequencer. A programmable component is programmed to make changes to the operation of the interface of the memory device, in response to changes in the environment of the memory device.12-03-2009
20110191532PROTOCOL ENGINE FOR PROCESSING DATA IN A WIRELESS TRANSMIT/RECEIVE UNIT - A protocol engine (PE) for processing data within a protocol stack in a wireless transmit/receive unit (WTRU) is disclosed. The protocol stack executes decision and control operations. The data processing and re-formatting which was performed in a conventional protocol stack is removed from the protocol stack and performed by the PE. The protocol stack issues a control word for processing data and the PE processes the data based on the control word. Preferably, the WTRU includes a shared memory and a second memory. The shared memory is used as a data block place holder to transfer the data amongst processing entities. For transmit processing, the PE retrieves source data from the second memory and processes the data while moving the data to the shared memory based on the control word. For receive processing, the PE retrieves received data from the shared memory and processes it while moving the data to the second memory.08-04-2011
20100030955MASK KEY SELECTION BASED ON DEFINED SELECTION CRITERIA - An improved data system permits power efficient mask key write operations. A mask key selector implements criteria-based selection of mask keys for mask key write operations on blocks data. In one embodiment, a first set of mask keys is compared to data bytes of a data block that will be written to memory. The comparison culls keys from the list of candidates that match unmasked data bytes, that is, values that will be written to memory as “changed” data. A mask key is selected from the resulting set of candidates so a memory write operation consumes less power (relative to selection of other keys), or so that the operation minimizes switching noise. The selected mask key is then substituted by a controller into masked data values, and a modified data block is transmitted to memory, with the memory detecting masked data by identifying mask keys in the modified data block.02-04-2010
20110307653CACHE COHERENCE PROTOCOL FOR PERSISTENT MEMORIES - Subject matter disclosed herein relates to cache coherence of a processor system that includes persistent memory.12-15-2011
20110307652HYBRID STORAGE SYSTEM WITH MID-PLANE - The present invention relates to semiconductor storage systems (SSDs). Specifically, the present invention relates to a hybrid storage system with a mid-plane. In a typical embodiment, a mid-plane is provided. Coupled to one side of the mid-plane is a system control board and a communications module having a set (at least one) of ports. Coupled to a second side of the mid-plane is (among other components) a first RAID controller, which itself is coupled to a double data rate semiconductor storage device (DDR SSD) module having a set of DDR SSD units. Also coupled to the second side of the mid-plane is a second RAID controller, which itself is coupled to a hard disk drive (HDD) module having a set of HDD/Flash SDD units.12-15-2011
20120042121Scatter-Gather Intelligent Memory Architecture For Unstructured Streaming Data On Multiprocessor Systems - A scatter/gather technique optimizes unstructured streaming memory accesses, providing off-chip bandwidth efficiency by accessing only useful data at a fine granularity, and off-loading memory access overhead by supporting address calculation, data shuffling, and format conversion.02-16-2012
20090172271SYSTEM AND METHOD FOR EXECUTING FULL AND PARTIAL WRITES TO DRAM IN A DIMM CONFIGURATION - In an embodiment of the invention, a host or other controller writing to multiple DRAMs in a DIMM configuration determines whether there is full write request to at least one of the multiple DRAM's and a partial write request to at least another one of the multiple DRAM's. If so, then the host parses data associated with the full write request into a first portion and a second portion. The host then outputs a first partial write command associated with the first portion and a second partial write command associated with the second portion to the DIMM. Other embodiments are described.07-02-2009
20120210055Controlling latency and power consumption in a memory - Memory circuitry, a data processing apparatus and a method of storing data are disclosed. The memory circuitry comprises: a memory for storing the data; and control circuitry for controlling power consumption of the memory by controlling a rate of access to the memory such that an average access delay between adjacent accesses is maintained at or above a predetermined value; wherein the control circuitry is configured to determine a priority of an access request to the memory and to maintain the average access delay at or above the predetermined value by delaying at least some accesses from access requests having a lower priority for longer than at least some accesses from access requests having a higher priority.08-16-2012
20120005421MEMORY CONTROLLER AND DATA PROCESSING SYSTEM - A memory controller and data processor have their operation mode switched from the page-on mode for high-speed access to a same page to the page-off mode in response to consecutive events of access to different pages, so that the memory access is performed at a high speed and low power consumption.01-05-2012
20120005419System Architecture For Integrated Hierarchical Query Processing For Key/Value Stores - A key/value store comprising a first tier storage device configured to store information about a plurality of keys for a plurality of values without the values, and a second tier storage device coupled to the first tier storage device and configured to store the values associated with the keys without the keys, wherein the first tier storage device has lower latency and higher throughput than the second tier storage device, and wherein the second tier storage device has higher capacity than the first tier storage device. Also disclosed is a method comprising receiving a key/value operation request at a first tier storage device, mapping a key in the key/value operation request to a locator stored in a second tier storage device if the key/value operation request is valid, and mapping the locator to a value in a third tier storage device if the key has a corresponding locator.01-05-2012
20120005420DYNAMICALLY SETTING BURST LENGTH OF DOUBLE DATA RATE MEMORY DEVICE BY APPLYING SIGNAL TO AT LEAST ONE EXTERNAL PIN DURING A READ OR WRITE TRANSACTION - One or more external control pins and/or addressing pins on a memory device are used to set one or both of a burst length and burst type of the memory device.01-05-2012
20130185497MANAGING CACHING OF EXTENTS OF TRACKS IN A FIRST CACHE, SECOND CACHE AND STORAGE - Provided are a computer program product, system, and method for managing caching of extents of tracks in a first cache, second cache and storage device. A determination is made of an eligible track in a first cache eligible for demotion to a second cache, wherein the tracks are stored in extents configured in a storage device, wherein each extent is comprised of a plurality of tracks. A determination is made of an extent including the eligible track and whether second cache caching for the determined extent is enabled or disabled. The eligible track is demoted from the first cache to the second cache in response to determining that the second cache caching for the determined extent is enabled. Selection is made not to demote the eligible track in response to determining that the second cache caching for the determined extent is disabled.07-18-2013
20110167211DRAM CONTROLLER FOR VIDEO SIGNAL PROCESSING OPERABLE TO ENABLE/DISABLE BURST TRANSFER - An interface unit 07-07-2011
20110167210SEMICONDUCTOR DEVICE AND SYSTEM COMPRISING MEMORIES ACCESSIBLE THROUGH DRAM INTERFACE AND SHARED MEMORY REGION - A semiconductor device comprises a nonvolatile memory device, a memory device that processes data according to a DRAM protocol, and an ASIC that converts data output from the memory device into a format compatible with a nonvolatile memory device or a hard disk and outputs the converted data to the nonvolatile memory device or the hard disk.07-07-2011
20120011310SIMULATING A MEMORY STANDARD - An apparatus includes multiple first memory circuits, each first memory circuit being associated with a first memory standard, where the first memory standard defines a first set of control signals that each first memory circuit circuits is operable to accept and defines a first version of a protocol. The apparatus also includes an interface circuit coupled to the first memory circuits, in which the interface circuit is operable to emulate at least one second memory circuit, each second memory circuit being associated with a second different memory standard. The second different memory standard defines a second set of control signals that the emulated second memory circuit is operable to accept and defines a second different version of a protocol. Both the first version of the protocol and the second different version of the protocol are associated either with DDR2 dynamic random access memory (DRAM) or with DDR3 DRAM.01-12-2012
20120017039CACHING USING VIRTUAL MEMORY - In a first embodiment of the present invention, a method for caching in a processor system having virtual memory is provided, the method comprising: monitoring slow memory in the processor system to determine frequently accessed pages; for a frequently accessed page in slow memory: copy the frequently accessed page from slow memory to a location in fast memory; and update virtual address page tables to reflect the location of the frequently accessed page in fast memory.01-19-2012
20120059983PREDICTOR-BASED MANAGEMENT OF DRAM ROW-BUFFERS - A method for managing memory includes storing a history of accesses to a memory page, and determining whether to keep the memory page open or to close the memory page based on the stored history. A memory system includes a plurality of memory cells arranged in rows and columns, a row buffer, and a memory controller configured to manage the row buffer at a per-page level using a history-based predictor. A non-transitory computer readable medium is also provided containing instructions therein, wherein the instructions include storing an access history of a memory page in a lookup table, and determining an optimal closing policy for the memory page based on the stored histories. The histories can include access numbers or access durations.03-08-2012
20120159061Memory Module With Reduced Access Granularity - A memory module having reduced access granularity. The memory module includes a substrate having signal lines thereon that form a control path and first and second data paths, and further includes first and second memory devices coupled in common to the control path and coupled respectively to the first and second data paths. The first and second memory devices include control circuitry to receive respective first and second memory access commands via the control path and to effect concurrent data transfer on the first and second data paths in response to the first and second memory access commands.06-21-2012
20120159060POWER ISOLATION FOR MEMORY BACKUP - Disclosed is a power isolation and backup system. When a power fail condition is detected, temporary storage is flushed to an SDRAM. After the flush, interfaces are halted, and power is removed from most of the chip except the SDRAM subsystem. The SDRAM subsystem copies data from an SDRAM to a flash memory. On the way, the data may be encrypted, and/or a data integrity signature calculated. To restore data, the SDRAM subsystem copies data from the flash memory to the SDRAM. On the way, the data being restored may be decrypted, and/or a data integrity signature checked.06-21-2012
20120159059MEMORY INTERFACE SIGNAL REDUCTION - In some embodiments a controller includes a memory activate pin, one or more combined memory command/address signal pins, and a selection circuit adapted to select in response to the memory activate pin as each of the one or more combined memory command/address signal pins either a memory command signal or a memory address signal. Other embodiments are described and claimed.06-21-2012
20110066797MEMORY SYSTEM - A memory system according to the present invention includes a bus connected to process units, a first DRAM which has a first storage area and a second storage area and which is controlled in operation by a DRAM control signal, a second DRAM which has the same bit width as that of the first DRAM, which has a third storage area having the same address space as that of the first storage area and having a capacity equal to that of the first storage area, and which is controlled in operation by the DRAM control signal, and a controller which is provided with a read command and a logical address from the process units via the bus, which controls operation of the first DRAM and the second DRAM according to the read command and the logical address, and thereby outputs data read from the first DRAM or the second DRAM to the process units via the bus.03-17-2011
20110066796AUTONOMOUS SUBSYSTEM ARCHITECTURE - An autonomous sub-system receives a database downloaded from a host controller. A controller monitors bus traffic and/or allocated resources in the subsystem and re-allocates resources based on the monitored results to dynamically improve system performance.03-17-2011
20090132759Information processing apparatus and method for controlling information processing apparatus - Disclosed herein is an information processing apparatus including: a dynamic random access memory; a memory controller that manages accesses to the dynamic random access memory on a bank basis; a cache memory that is connected to the memory controller via a bus and which caches data stored in the dynamic random access memory; and an information processing block that performs a read access to the dynamic random access memory via the cache memory. The cache memory includes: a refill request generation section configured to generate a refill request for caching the data stored in the dynamic random access memory in response to a cache miss for the read access; and a read access section configured to, when the refill requests have been accumulated for a predetermined number of banks, perform a read access to the dynamic random access memory while combining the refill requests for the predetermined number of banks.05-21-2009
20120124280Memory controller with emulative internal memory buffer - The present application discloses a memory controller for accessing an external memory device. The memory controller comprises a bus interface and an internal memory buffer capable of accessing the bus interface. The internal memory buffer operates as an on-chip storage. In various embodiments of the disclosure, the internal memory buffer operates during a testing of a chip containing the memory controller. For example, the internal memory buffer may emulate the external memory device in response to an input signal. Moreover, in various embodiments of the disclosure, the external memory device may be a dynamic random access memory (DRAM), while the to internal memory buffer may be a static random access memory (SRAM). The memory controller may be adapted to automated test equipment (ATE). Moreover, the memory controller may be incorporated onto a system-on-a-chip (SOC) along with one or more agents.05-17-2012
20120317351INFORMATION PROCESSING APPARATUS AND INFORMATION PROCESSING METHOD - There is provided with an information processing apparatus comprising a DRAM, a memory controller configured to access the DRAM, and a bus master configured to send, to the memory controller, an access request to the DRAM, the bus master comprises a transmission unit configured to transmit, to the memory controller, using a signal indicating a type of burst access which is requested of the memory controller by the bus master, an instruction to designate that an auto-precharge operation is not to be performed after accessing the first address, and an instruction to designate that an auto-precharge operation is to be performed after accessing the first address.12-13-2012
20120221785Polymorphic Stacked DRAM Memory Architecture - A 3D stacked processor device is described which includes a processor chip and a stacked polymorphic DRAM memory chip connected to the processor chip through a plurality of through-silicon-via structures, where the stacked DRAM memory chip includes a memory with an adjustable memory portion and an adjustable cache portion such that memory can operate simultaneously in both memory and cache modes.08-30-2012
20120166722APPARATUS AND METHOD FOR CONTROLLING THE ACCESS OPERATION BY A PLURALITY OF DATA PROCESSING DEVICES TO A MEMORY - In an apparatus for controlling the access operation by a plurality of data processing devices to a memory, each data processing device is assigned a respective address region which indicates the part of the addresses of the memory which the respective data processing device can access. A control device blocks an access operation by a data processing device to the memory if the access operation address is not located in the address region which is assigned to the respective data processing device.06-28-2012
20120137060Multi-stage TCAM search - A method to divide a database of TCAM rules includes selecting a rule of the database having multiple don't care values and selecting a bit of the rule having a don't care value, generating two distributor rules based on the selected rule, where the selected bit has a 1 value in one of the distributor rules and a 0 in the other of the distributor rules, associating rules of the database which match each of the distributor rules with the distributor rule they match thereby to create associated databases, and repeating the steps of selecting, generating and associating on the database and the associated databases until the average number of rules in each associated database is at or below a predefined amount. A search unit includes a distributor TCAM and a DRAM search unit having a DRAM storage unit and an associated DRAM search logic unit. The DRAM storage unit has a section for each associated database, where each section is pointed to by a different distributor rule. The DRAM search unit matches the input key to one of the rules in the section pointed to by the matched distributor rule.05-31-2012
20100185811Data processing system and method - A data processing system including a non-volatile memory and a processor controlling an operation of the non-volatile memory is provided. The processor transmits and receives a first type of data to and from an outside through a first path through which a first command and a first address, which are used to write/read the first data to/from the non-volatile memory, are transmitted. The processor also transmits and receives a second type of data to and from the outside through a second path different from the first path through which a second command and a second address, which are used to write/read the second data to/from the non-volatile memory, are transmitted.07-22-2010
20100174858EXTRA HIGH BANDWIDTH MEMORY DIE STACK - A system includes a central processing unit (CPU); a memory device in communication with the CPU, and a direct memory access (DMA) controller in communication with the CPU and the memory device. The memory device includes a plurality of vertically stacked chips and a plurality of input/output (I/O) ports. Each of the I/O ports connected to at least one of the plurality of chips through a through silicon via. The DMA controller is configured to manage to transfer of data to and from the memory device.07-08-2010
20120173811Method and Apparatus for Delaying Write Operations - An apparatus for controlling a dynamic random access memory (DRAM), the apparatus comprising an interface to transmit to the DRAM a first code to indicate that first data is to be written to the DRAM. The first code is to be sampled by the DRAM and held by the DRAM for a first period of time before it is issued inside the DRAM. The interface is further to transmit the first data that is to be sampled by the DRAM after a second period of time has elapsed from when the first code is sampled by the DRAM. The interface is further to transmit a second code, different from the first code, to indicate that second data is to be read from the DRAM. The second code is to be sampled by the DRAM on one or more edges of the external clock signal.07-05-2012
20120173809Memory Device Having DRAM Cache and System Including the Memory Device - The present disclosure relates to a memory device and a system including the memory device. The memory device may include a non-volatile memory, a dynamic random access memory (DRAM) cache, a DRAM, and a control circuit. The control circuit may perform interfacing between the DRAM and a host, between the DRAM cache and the host, and between the non-volatile memory and the DRAM cache. The memory device may have a high operating speed and may be incorporated in a simple package, such as a multi-chip package.07-05-2012
20120215975Dynamic Management of Random Access Memory - The invention proposes a method for managing random access memory in a computer system, with said computer system comprising a processor, a first static random access memory, and a second dynamic random access memory, the method comprising the steps of:—receiving at least one instruction to be executed by the processor,—determining a priority level for the execution of the instruction by the processor, and—loading the instruction into the first memory for its execution by the processor if its priority level indicates that it is a high priority instruction, or if not—loading the instruction into the second memory for its execution by the processor.08-23-2012
20100049911Circuit and Method for Generating Data Input Buffer Control Signal - A data input buffer control signal generating device is capable of preventing unnecessary operation and current consumption of blocks and thus stabilizing an internal operation of DRAM by generating a control signal which controls an enabling timing of a data input buffer not to be conflicted with an output data. The data input buffer control signal generating device includes a write-related control unit configured to generate a data input buffer reference signal generated on the basis of a write latency by a write command, a read-related control unit configured to replicate a delay through a data output path, delay an end command for a data output termination and generate a delayed end command, wherein the end command is generated by a read command, and an output unit configured to output a data input buffer control signal by combining the data input buffer reference signal and the output of the delayed end command.02-25-2010
20120179866Memory Component Having Write Operation with Multiple Time Periods - A method for storing data in a memory chip that includes a memory core having dynamic random access memory cells, is performed by a memory controller chip. The method includes sending a write command to a first interface of the memory chip, wherein the write command specifies a write operation. After sending the write command, the memory controller chip waits for a first time period corresponding to a time period during which the write command is stored by the memory chip, and sends data associated with the write operation to a second interface of the memory chip, wherein the sending of the data occurs after a second time period transpires, the second time period following the first time period, such that sending the write command and sending the data are separated by a first predetermined delay time that includes both the first time period and the second time period.07-12-2012
20120254530MICROPROCESSOR AND MEMORY ACCESS METHOD - A microprocessor according to the present invention includes instruction execution unit that executes an instruction to output an access request to a memory according to a first protocol; memory control unit that converts the access request according to the first protocol to an access request according to a second protocol to perform an access control to an external memory to output the access request; selection unit that selects whether to access the external memory using the memory control unit; and interface unit that externally outputs one of the access request according to the first protocol and the access request according to the second protocol based on the selection result in the selection unit.10-04-2012
20120254529MOTHERBOARD WITH DDR MEMORY DEVICES - A motherboard includes a central processing unit (CPU) with a reset signal output pin, a buffer circuit, and at least one memory device. The buffer circuit includes an input terminal connected to the reset signal output pin of the CPU and at least one output terminal. The input terminal and the at least one output terminal have the same voltage level. The at least one memory device has a reset signal receiving terminal connected to the at least one output terminal of the buffer circuit.10-04-2012
20120254528MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME - A memory device includes a first bank group, a second bank group, where the first and second bank groups are each configured to output multi-bit data in parallel in response to a read command, a data transferor configured to receive the multi-bit data outputted in parallel from the first bank group or the second bank group and output the multi-bit data at a time interval corresponding to an operation mode, first global data buses configured to transfer the multi-bit data outputted from the first bank group to the data transferor, second global data buses configured to transfer the multi-bit data outputted from the second bank group to the data transferor, and a parallel-to-serial converter configured to convert the multi-bit data outputted from the data transferor into serial data according to the operation mode.10-04-2012
20120254527DYNAMIC RANDOM ACCESS MEMORY FOR A SEMICONDUCTOR STORAGE DEVICE-BASED SYSTEM - Embodiments of the present invention provide an approach for dynamic random access memory (DRAM)/SSD-based memory to improve memory usage. Specifically, embodiments of the present invention provide a field programmable gate array (FPGA) (SSD controller) that comprises a PCI-express interface for receiving and converting serial data to 64 bit data; a data/bit converter coupled to the interface for converting the 64 bit data to 128 bit data; and a memory controller coupled to the data converter for receiving and storing the 128 bit data in a set of DRAM units coupled to the memory controller. In general, the data converter comprises an input address buffer for receiving and buffering address information; an address matching component coupled to the input address buffer for analyzing the address information and determining a matching address based on the address information; an output address buffer coupled to the address matching component for buffering and outputting the matching address; an input data buffer for receiving and buffering 64 bit data; a data matching component coupled to the input data buffer for matching the 64 bit data with a corresponding address; and an output data buffer coupled to the data matching component for buffering and outputting the 128 bit data based on output of the data matching component.10-04-2012
20100293325MEMORY DEVICES AND SYSTEMS INCLUDING MULTI-SPEED ACCESS OF MEMORY MODULES - A system, comprising: a plurality of modules, each module comprising a plurality of integrated circuits devices coupled to a module bus and a channel interface that communicates with a memory controller, at least a first module having a portion of its total module address space composed of first type memory cells having a first maximum access speed, and at least a second module having a portion of its total module address space composed of second type memory cells having a second maximum access speed slower than the first access speed.11-18-2010
20120084498TRACKING WRITTEN ADDRESSES OF A SHARED MEMORY OF A MULTI-CORE PROCESSOR - Described embodiments provide a method of controlling processing flow in a network processor having one or more processing modules. A given one of the processing modules loads a script into a compute engine. The script includes instructions for the compute engine. The given one of the processing modules loads a register file into the compute engine. The register file includes operands for the instructions of the loaded script. A tracking vector of the compute engine is initialized to a default value, and the compute engine executes the instructions of the loaded script based on the operands of the loaded register file. The compute engine updates corresponding portions of the register file with updated data corresponding to the executed script. The tracking vector tracks the updated portions of the register file. The compute engine provides the tracking vector and the updated register file to the given one of the processing modules.04-05-2012
20120084497Instruction Prefetching Using Cache Line History - An apparatus of an aspect includes a prefetch cache line address predictor to receive a cache line address and to predict a next cache line address to be prefetched. The next cache line address may indicate a cache line having at least 64-bytes of instructions. The prefetch cache line address predictor may have a cache line target history storage to store a cache line target history for each of multiple most recent corresponding cache lines. Each cache line target history may indicate whether the corresponding cache line had a sequential cache line target or a non-sequential cache line target. The cache line address predictor may also have a cache line target history predictor. The cache line target history predictor may predict whether the next cache line address is a sequential cache line address or a non-sequential cache line address, based on the cache line target history for the most recent cache lines.04-05-2012
20090019219Compressing address communications between processors - In one embodiment, the present invention includes a method for determining if data of a memory request by a first agent is in a memory region represented by a region indicator of a region table of the first agent, and transmitting a compressed address for the memory request to other agents of a system if the memory region is represented by the region indicator, otherwise transmitting a full address. Other embodiments are described and claimed.01-15-2009
20120260032SYSTEMS AND METHODS FOR USING MEMORY COMMANDS - Systems and methods for using memory commands are described. The systems include a memory controller. The memory controller receives a plurality of user transactions. The memory controller converts each user transaction into one or more row and column memory commands. The memory controller reorders the memory commands associated with the plurality of user transactions before sending the memory commands to a memory device.10-11-2012
20120233395EMULATION OF ABSTRACTED DIMMS USING ABSTRACTED DRAMS - One embodiment of the present invention sets forth an abstracted memory subsystem comprising abstracted memories, which each may be configured to present memory related characteristics onto a memory system interface. The characteristics can be presented on the memory system interface via logic signals or protocol exchanges, and the characteristics may include any one or more of, an address space, a protocol, a memory type, a power management rule, a number of pipeline stages, a number of banks, a mapping to physical banks, a number of ranks, a timing characteristic, an address decoding option, a bus turnaround time parameter, an additional signal assertion, a sub-rank, a number of planes, or other memory-related characteristics. Some embodiments include an intelligent register device and/or, an intelligent buffer device. One advantage of the disclosed subsystem is that memory performance may be optimized regardless of the specific protocols used by the underlying memory hardware devices.09-13-2012
20120233394MEMORY CONTROLLER AND A CONTROLLING METHOD ADAPTABLE TO DRAM - A memory controller and controlling method adaptable to a dynamic random access memory (DRAM) are disclosed. A DRAM controller is configured to manage flow of data to and from the DRAM. A write buffer is controlled by the DRAM controller to temporarily store an entry of data to be written to the DRAM. The data to be written is stored in the write buffer if the write buffer is empty, and the stored data and a succeeding data to be written are both written to the DRAM.09-13-2012
20120233393Scheduling Workloads Based On Cache Asymmetry - In one embodiment, a processor includes a first cache and a second cache, a first core associated with the first cache and a second core associated with the second cache. The caches are of asymmetric sizes, and a scheduler can intelligently schedule threads to the cores based at least in part on awareness of this asymmetry and resulting cache performance information obtained during a training phase of at least one of the threads.09-13-2012
20120265930CONTROLLING ON-DIE TERMINATION IN A DYNAMIC RANDOM ACCESS MEMORY DEVICE - An integrated circuit device transmits, to a dynamic random access memory device (DRAM), a write command indicating that write data is to be sampled by a data interface of the DRAM, and a plurality of commands that specify programming a plurality of control values into a plurality of corresponding registers in the DRAM. The plurality of control values include first and second control values that indicate respective first and second terminations that the DRAM is to apply to the data interface during a time interval that begins a predetermined amount of time after the DRAM receives the write command, the first termination to be applied during a first portion of the time interval while the data interface is sampling the write data and the second termination to be applied during a second portion of the time interval after the write data is sampled.10-18-2012
20110131370DISABLING OUTBOUND DRIVERS FOR A LAST MEMORY BUFFER ON A MEMORY CHANNEL - Memory apparatus and methods utilizing multiple bit lanes may redirect one or more signals on the bit lanes. A memory agent may include a redrive circuit having a plurality of bit lanes, a memory device or interface, and a fail-over circuit coupled between the plurality of bit lanes and the memory device or interface.06-02-2011
20120239873Memory access system and method for optimizing SDRAM bandwidth - A memory access system for optimizing SDRAM bandwidth includes a memory command processor, and an SDRAM interface and protocol controller. The memory command processor is connected to a memory bus arbiter and data switch circuit for receiving memory access commands outputted by the memory bus arbiter and data switch circuit and converting the memory access commands into reordered SDRAM commands. The SDRAM interface and protocol controller is connected to the memory command processor for receiving and executing the reordered SDRAM commands based on protocol and timing of SDRAM. The memory command processor decodes the memory access commands into general SDRAM commands or alternative SDRAM commands. The memory access commands decoded into alternative SDRAM commands are generated by a specific bus master.09-20-2012
20120239874METHOD AND SYSTEM FOR RESOLVING INTEROPERABILITY OF MULTIPLE TYPES OF DUAL IN-LINE MEMORY MODULES - Systems and methods are described for resolving certain interoperability issues among multiple types of memory modules in the same memory subsystem. The system provides a single data load DIMM for constructing a high density and high speed memory subsystem that supports the standard JEDEC RDIMM interface while presenting a single load to the memory controller. At least one memory module includes one or more DRAM, a bi-directional data buffer and an interface bridge with a conflict resolution block. The interface bridge translates the CAS latency (CL) programming value that a memory controller sends to program the DRAMs, modifies the latency value, and is used for resolving command conflicts between the DRAMs and the memory controller to insure proper operation of the memory subsystem.09-20-2012
20120089772DEVICE, SYSTEM, AND METHOD OF MEMORY ALLOCATION - Device, system, and method of memory allocation. For example, an apparatus includes: a Dual In-line Memory Module (DIMM) including a plurality of Dynamic Random Access Memory (DRAM) units to store data, wherein each DRAM unit includes a plurality of banks and each bank is divided into a plurality of sub-banks; and a memory management unit to allocate a set of interleaved sub-banks of said DIMM to a memory page of an Operating System, wherein a combined memory size of the set of interleaved sub-banks is equal to a size of the memory page of the Operating System.04-12-2012
20120089771Data Processing Apparatus - A data processing apparatus reduces the number of the buffer SRAMs to decrease chip area. The data processing apparatus includes an SDRAM address allocation register that holds information indicating which region of the SDRAM will be allocated to each of the IPs, and a buffer SRAM address allocation register that holds information indicating which region of the first and second buffer SRAMs will be allocated to each of the IPs. The bus I/F stores the data read from the SDRAM into the second buffer SRAM with reference to the SDRAM address allocation register and the buffer SRAM address allocation register. Therefore, it is not necessary to provide each of the IPs with a buffer SRAM, which allows integration into a small number of buffer SRAMs.04-12-2012
20110276751INTEGRATED MEMORY CONTROL APPARATUS AND METHOD THEREOF - An integrated memory control apparatus including a first interface decoder, a second interface decoder and an interface controller is provided. Wherein, the first interface decoder is coupled to a control chip through a first serial peripheral interface (SPI), the second interface decoder is coupled to a micro-processor unit through a general transmission interface, and the interface controller is coupled to a memory through a second SPI. When the interface controller receives the request signals from the control chip and the micro-processor unit, the control chip may correctly read data from the memory through the first and second SPI. On the other hand, the micro-processor unit may stop reading data from the memory through the general transmission interface. Therefore, the control chip and the micro-processor unit may share the same memory.11-10-2011
20120331219EXTENDED-HEIGHT DIMM - An extended-height DIMM for use in a memory system having slots designed to receive DIMMs that comply with a JEDEC standard that specifies a maximum height for the DIMM and a maximum number of devices allowed to reside on the DIMM. The DIMM comprises a PCB having an edge connector designed to mate with a memory system slot and a height which is greater than the maximum height specified in the applicable standard, a plurality of memory devices which exceeds the maximum number of devices specified in the applicable standard, and a memory buffer which operates as an interface between a host controller's data and command/address busses and the memory devices. This arrangement enables the extended-height DIMM to provide greater memory capacity than would a DIMM which complies with the maximum height and maximum number of devices limits.12-27-2012
20110307654WRITE OPERATIONS IN A FLASH MEMORY-BASED OBJECT STORE - Approaches for improving writing to solid state devices. An object cache or store, maintained on one or more flash storage devices, comprises two or more slabs. A slab is an allocated amount of memory for storing objects of a particular size. A request to write requested data to a slab is received. The size of the requested data is less than the maximum capacity of objects stored in the slab. After writing the requested data to the slab, unrequested data is written up to the maximum capacity of an object in the slab in the same write operation. Writing the unrequested data to the particular slab is performed for purposes of reducing the time required to write the requested data to the SSD.12-15-2011
20110320698Multi-Channel Multi-Port Memory - A multi-channel multi-port memory is disclosed. In a particular embodiment, the multi-channel memory includes a plurality of channels responsive to a plurality of memory controllers. The multi-channel memory may also include a first multi-port multi-bank structure accessible to a first set of the plurality of channels and a second multi-port multi-bank structure accessible to a second set of the plurality of channels.12-29-2011
20110320697DYNAMICALLY SUPPORTING VARIABLE CACHE ARRAY BUSY AND ACCESS TIMES - Various embodiments of the present invention manage access to a cache memory. In or more embodiments a request for a targeted interleave within a cache memory is received. The request is associated with an operation of a given type. The target is determined to be available. The request is granted in response to the determining that the target is available. A first interleave availability table associated with a first busy time associated with the cache memory is updated based on the operation associated with the request in response to granting the request. A second interleave availability table associated with a second busy time associated with the cache memory is updated based on the operation associated with the request in response to granting the request.12-29-2011
20110320696EDRAM REFRESH IN A HIGH PERFORMANCE CACHE ARCHITECTURE - A memory refresh requestor, a memory request interpreter, a cache memory, and a cache controller on a single chip. The cache controller configured to receive a memory access request, the memory access request for a memory address range in the cache memory, detect that the cache memory located at the memory address range is available, and send the memory access request to the memory request interpreter when the memory address range is available. The memory request interpreter configured to receive the memory access request from the cache controller, determine if the memory access request is a request to refresh a contents of the memory address range, and refresh data in the memory address range when the memory access request is a request to refresh memory.12-29-2011
20110320695MITIGATING BUSY TIME IN A HIGH PERFORMANCE CACHE - Various embodiments of the present invention mitigate busy time in a hierarchical store-through memory cache structure. In one embodiment, a cache directory associated with a memory cache is divided into a plurality of portions each associated with a portion memory cache. Simultaneous cache lookup operations and cache write operations between the plurality of portions of the cache directory are supported. Two or more store commands are simultaneously processed in a shared cache pipeline communicatively coupled to the plurality of portions of the cache directory.12-29-2011
20110320694CACHED LATENCY REDUCTION UTILIZING EARLY ACCESS TO A SHARED PIPELINE - A method of performing operations in a shared cache coupled to a first requestor and a second requestor includes receiving at the shared cache a first request from the second requester; assigning the request to a state machine; transmitting a first pipe pass request from the state machine to an arbiter; providing a first instruction from the first pipe pass request to a cache pipeline, the first instruction causing a first pipe pass; and providing a second pipe pass request to the arbiter before the first pipe pass is completed.12-29-2011
20120137061PRE-CACHE SIMILARITY-BASED DELTA COMPRESSION FOR USE IN A DATA STORAGE SYSTEM - A data storage caching architecture supports using native local memory such as host-based RAM, and if available, Solid State Disk (SSD) memory for storing pre-cache delta-compression based delta, reference, and independent data by exploiting content locality, temporal locality, and spatial locality of data accesses to primary (e.g. disk-based) storage. The architecture makes excellent use of the physical properties of the different types of memory available (fast r/w RAM, low cost fast read SSD, etc) by applying algorithms to determine what types of data to store in each type of memory. Algorithms include similarity detection, delta compression, least popularly used cache management, conservative insertion and promotion cache replacement, and the like.05-31-2012
20080256290METHOD AND SYSTEM OF RANDOMIZING MEMORY LOCATIONS - A memory system that disperses memory addresses of stings of data throughout a memory is provided. The memory system includes a memory, a central processing unit (CPU) and an address randomizer. The memory is configured to store stings of data. The CPU is configured to direct the storing and retrieving of the strings of data from the memory at select memory addresses. The address randomizer is coupled between the CPU and the memory. Moreover, the address randomizer is configured to disburse the strings of data throughout locations of the memory by changing the select memory addresses directed by the CPU.10-16-2008
20080250196Data Sequence Sample and Hold Method, Apparatus and Semiconductor Integrated Circuit - To provide a sample-and-hold method which can limit the storage capacity of storage media needed to a bare minimum and can independently manage a series of data contained in a predetermined interval before the arrival time of a trigger signal and a series of data contained in a predetermined interval after the arrival time of the trigger signal by separating them clearly.10-09-2008
20110246712METHOD AND APPARATUS FOR INTERFACING WITH HETEROGENEOUS DUAL IN-LINE MEMORY MODULES - Described herein is a method and apparatus to interface a processor with a heterogeneous dual in-line memory module (DIMM). The method comprises determining an identity of a DIMM having data lanes; mapping the data lanes based on the determining of the identity of the DIMM; training input-output (I/O) transceivers in response to the mapping of the data lanes; and transferring data to and from the DIMM after training the I/O transceivers.10-06-2011
20130179633SCATTER-GATHER INTELLIGENT MEMORY ARCHITECTURE FOR UNSTRUCTURED STREAMING DATA ON MULTIPROCESSOR SYSTEMS - A scatter/gather technique optimizes unstructured streaming memory accesses, providing off-chip bandwidth efficiency by accessing only useful data at a fine granularity, and off-loading memory access overhead by supporting address calculation, data shuffling, and format conversion.07-11-2013
20130179632METHODS, SYSTEMS, AND COMPUTER READABLE MEDIA FOR OPTIMIZATION OF HOST SEQUENTIAL READS OR WRITES BASED ON VOLUME OF DATA TRANSFER - A method for optimization of host sequential reads based on volume of data includes, at a mass data storage device, pre-fetching a first volume of predicted data associated with an identified read data stream from a data store into a buffer memory different from the data store. A request for data from the read data stream is received from a host. In response, the requested data is provided to the host from the buffer memory. While providing the requested data to the host from the buffer memory, it is determined whether a threshold volume of data has been provided to the host from the data buffer memory. If so, a second volume of predicted data associated with the identified read data stream is pre-fetched from the data store and into the buffer memory. If not, additional predicted data is not pre-fetched from the data store.07-11-2013
20130097371DISABLING OUTBOUND DRIVERS FOR A LAST MEMORY BUFFER ON A MEMORY CHANNEL - Memory apparatus and methods utilizing multiple bit lanes may redirect one or more signals on the bit lanes. A memory agent may include a redrive circuit having a plurality of bit lanes, a memory device or interface, and a fail-over circuit coupled between the plurality of bit lanes and the memory device or interface.04-18-2013
20130103899SYSTEM ON CHIP WITH RECONFIGURABLE SRAM - A system on chip includes electrical components and a first memory including memory blocks. A method of operating the system on chip includes generating an assignment of the memory blocks to the electrical components. The generating includes, initially, during a development phase of the system on chip, generating the assignment so that selected memory blocks of the memory blocks are assigned to first selected electrical components of the electrical components as emulated read-only memory. The generating includes, subsequently, during an operational phase of the system on chip, modifying the assignment so that one or more of the selected memory blocks are re-assigned to second selected electrical components of the electrical components as cache memory. The method also includes, according to the assignment, dynamically creating electrical connectivity between the memory blocks and the electrical components.04-25-2013
20130103896MEMORY MODULE WITH MEMORY STACK AND INTERFACE WITH ENHANCED CAPABILITES - A memory module, which includes at least one memory stack, comprises a plurality of DRAM integrated circuits and an interface circuit. The interface circuit interfaces the memory stack to a host system so as to operate the memory stack as a single DRAM integrated circuit. In other embodiments, a memory module includes at least one memory stack and a buffer integrated circuit. The buffer integrated circuit, coupled to a host system, interfaces the memory stack to the host system so to operate the memory stack as at least two DRAM integrated circuits. In yet other embodiments, the buffer circuit interfaces the memory stack to the host system for transforming one or more physical parameters between the DRAM integrated circuits and the host system.04-25-2013
20130103897SYSTEM AND METHOD FOR TRANSLATING AN ADDRESS ASSOCIATED WITH A COMMAND COMMUNICATED BETWEEN A SYSTEM AND MEMORY CIRCUITS - A memory circuit system and method are provided. An interface circuit is capable of communication with a plurality of memory circuits and a system. In use, the interface circuit is operable to translate an address associated with a command communicated between the system and the memory circuits.04-25-2013
20130132660DATA READ/WRITE SYSTEM - The present invention provides a data read/write system. The data read/write system includes a memory controller and a memory module. The memory controller includes a first control circuit, a data output circuit, and a data receiving circuit. The memory module includes a memory buffer and at least two memory chips. The memory buffer includes a second control circuit, a write circuit, and a read circuit. The advantage of the present invention is that, when data is read or written into the memory chip, especially a DDR4 X4 memory chip, low power consumption of interface data transmission can be achieved through a data bus inversion control line DBI.05-23-2013
20130103898DRIVER FOR DDR2/3 MEMORY INTERFACES - An apparatus is described that includes a combined drive and termination circuit programmable to interface to DDR2 and DDR3 memory modules. In an exemplary embodiment the apparatus includes a combined output/termination driver, an input driver and a calibration subsystem. The combined output/termination driver includes a number of pull-up circuits and a number of pull-down circuits. One of the pull-up circuits presents a fixed output impedance. The rest of the pull-up circuits have an impedance programmable between two desired impedance values. One of the pull-down circuits presents a fixed output impedance. The rest of the pull-down circuits have an impedance programmable between two desired impedance values. The necessary number of pull-up circuits and pull-down circuits is activated in order to provide a desired driving and termination circuit such as to interface to specific impedance values as defined by the DDR2 and DDR3 interface protocol.04-25-2013
20080209119METHODS AND SYSTEMS FOR GENERATING ERROR CORRECTION CODES - Methods and systems for generating ECC encode a data block to generate corresponding error correction codes. A first buffer sequentially stores a first section and a second section of the data block, wherein each of the first and second sections is composed of X data rows and Y data columns of the data block, and Y is greater than or equal to 2. A second buffer stores Y partial-parity columns. An encoder is used for encoding the first section read from the first buffer to generate the partial-parity columns, and then storing the partial-parity columns in the second buffer. The second section read from the first buffer and the partial-parity columns read from the second buffer are encoded to generate updated partial-parity columns. Next, the partial-parity columns in the second buffer are updated by storing the updated partial-parity columns.08-28-2008
20130185496Vector Processing System - A vector processing system provides high performance vector processing using a System-On-a-Chip (SOC) implementation technique. One or more scalar processors (or cores) operate in conjunction with a vector processor, and the processors collectively share access to a plurality of memory interfaces coupled to Dynamic Random Access read/write Memories (DRAMs). In typical embodiments the vector processor operates as a slave to the scalar processors, executing computationally intensive Single Instruction Multiple Data (SIMD) codes in response to commands received from the scalar processors. The vector processor implements a vector processing Instruction Set Architecture (ISA) including machine state, instruction set, exception model, and memory model.07-18-2013
20130151767MEMORY CONTROLLER-INDEPENDENT MEMORY MIRRORING - A method of memory controller-independent memory mirroring includes providing a mirroring association between a first memory segment and a second memory segment that is independent of a memory controller. A memory buffer receives data from the memory controller that is directed to a first memory location in the first memory segment. The memory buffer writes the data, independent of the memory controller, to both the first memory segment and the second memory segment according to the mirroring association. The memory buffer receives a plurality of read commands from the memory controller that are directed to the first memory location in the first memory segment and, in response, reads data from an alternating one of the first memory segment and the second memory segment and stores both first data from the first memory segment and second data from the second memory segment.06-13-2013
20130151766CONVERGENCE OF MEMORY AND STORAGE INPUT/OUTPUT IN DIGITAL SYSTEMS - Embodiments of the present invention relate to CPU and/or digital memory architecture. Specifically, embodiments of the present invention relate to various approaches for adapting current designs to provide connection of a storage unit to a CPU via a memory unit through the use of controllers. This allows for system data to flow from the CPU to the memory unit to the storage unit. Such a configuration is enabled by the use of an extended memory access scheme that comprises a plurality of row address strobes (RAS) and a column address strobe (CAS) (and, optionally, one or more data bit line DQs).06-13-2013
20100312956Load reduced memory module - A memory module includes a plurality of memory chips and a plurality of data register buffers mounted on the module substrate. At least two memory chips are allocated to each of the data register buffers. Each of the data register buffers includes M input/output terminals (M is a positive integer equal to or larger than 1) that are connected to the data connectors via a first data line and N input/output terminals (N is a positive integer equal to or larger than 2M) that are connected to corresponding memory chips via second and third data lines, so that the number of the second and third data lines is N/M times the number of the first data lines. According to the present invention, because the load capacities of the second and third data lines are reduced by a considerable amount, it is possible to realize a considerably high data transfer rate.12-09-2010
20100318732DATA PROCESSOR - The data processor enhances the bus throughput or data throughput of an external memory, when there are frequent continuous reads with a smaller data size than the data bus width of the external memory. The data processor includes a memory control unit being capable of controlling in response to a clock an external memory having plural banks that are individually independently controllable, plural buses connected to the memory control unit, and circuit modules capable of commanding memory accesses, which are provided in correspondence with each of the buses. The memory control unit contains bank caches each corresponding to the banks of the external memory. Thereby, the data processor enhances the bus throughput or data throughput of the external memory, since the data processor stores the data read out from the external memory temporarily in the bank caches and to use the stored data without invalidating them, when performing a continuous data read with a smaller data size than the data bus width of the external memory.12-16-2010
20130159616SELF TERMINATED DYNAMIC RANDOM ACCESS MEMORY - A method for operating a memory system and a memory buffer device. The method includes receiving an external clock signal from a clock device of a CPU of a host computer to a buffer device, and receiving an ODT signal from the CPU to a command port of the buffer device. Buffer device provides the self-termination information internally to the common data bus by automatically detecting the read or write command on the common command bus and adjust the termination resistor array in a pre-determined value and timing fashion so that information can be read from or write to a data line of only one of the plurality of DIMM devices coupled together through a common data bus interface. All DIMM devices other than the DIMM device being read can be maintained in a termination state to prevent any signal from traversing to the common the common data bus interface.06-20-2013
20130159615DDR RECEIVER ENABLE CYCLE TRAINING - A method is provided for sampling a data strobe signal of a memory cycle and determining a receiver enable phase based upon the data strobe signal. The method also includes performing a memory write cycle and a subsequent read cycle and training a read data strobe cycle at a one-quarter memory clock periodic offset. The method also includes determining a correct receiver enable delay in response to a successful read data strobe training cycle. Computer readable storage media are also provided. An apparatus is provided that includes a communication interface portion that is coupled to a memory portion and to a processing device. The apparatus also includes a first circuit portion, coupled to the communication interface portion. The first circuit portion monitors memory cycles on the communication interface portion, determines a receiver enable cycle phase and train a receiver enable cycle without using receiver enable seed.06-20-2013
20130185492Memory Watch - A method can include receiving memory configuration information that specifies a memory configuration; receiving memory usage information for the memory configuration; analyzing the received memory usage information for a period of time; and, responsive to the analyzing, controlling notification circuitry configured to display a graphical user interface that presents information for physically altering a specified memory configuration. Various other apparatuses, systems, methods, etc., are also disclosed.07-18-2013
20130185494POPULATING A FIRST STRIDE OF TRACKS FROM A FIRST CACHE TO WRITE TO A SECOND STRIDE IN A SECOND CACHE - Provided are a computer program product, system, and method for managing data in a cache system comprising a first cache, a second cache, and a storage system. A determination is made of tracks stored in the storage system to demote from the first cache. A first stride is formed including the determined tracks to demote. A determination is made of a second stride in the second cache in which to include the tracks in the first stride. The tracks from the first stride are added to the second stride in the second cache. A determination is made of tracks in strides in the second cache to demote from the second cache. The determined tracks to demote from the second cache are demoted.07-18-2013
20130185495DEMOTING TRACKS FROM A FIRST CACHE TO A SECOND CACHE BY USING A STRIDE NUMBER ORDERING OF STRIDES IN THE SECOND CACHE TO CONSOLIDATE STRIDES IN THE SECOND CACHE - Information on strides configured in the second cache includes information indicating a number of valid tracks in the strides, wherein a stride has at least one of valid tracks and free tracks not including valid data. A determination is made of tracks to demote from the first cache. A first stride is formed including the determined tracks to demote. The tracks from the first stride are added to a second stride in the second cache that has no valid tracks. A target stride in the second cache is selected based on a stride most recently used to consolidate strides from at least two strides into one stride. Data from the valid tracks is copied from at least two source strides in the second cache to the target stride.07-18-2013
20110302366Memory expansion using rank aggregation - In one embodiment, a method includes receiving from a memory controller, a request to access memory stored at memory modules, the request directed to one of a plurality of logical ranks, mapping at a rank aggregator, the logical rank to one of a plurality of physical ranks at the memory modules, and forwarding the request to one of the memory modules according to the mapping. Two or more of the memory modules are combined to represent the number of logical ranks at the memory controller such that there is a one-to-one mapping between the logical ranks and the physical ranks. An apparatus for rank aggregation is also disclosed.12-08-2011
20110314213PROCESSOR SYSTEM USING SYNCHRONOUS DYNAMIC MEMORY - A processor system including: a processor having a processor core and a controller core; and a plurality of synchronous memory chips, wherein the processor and the plurality of synchronous memory chips are connected via an external bus; wherein the processor core and the controller core are connected via an internal bus; wherein the plurality of synchronous memory chips are operated according to a clock signal; wherein the controller core comprises a mode register selected by an address signal from the processor core and written with an information by a data signal from the processor core to select the operation mode of the plurality of synchronous memory chips, and a control unit to prescribe the operate mode to the plurality of synchronous memory chips based on the information written in the mode register, wherein the controller core outputs a mode setting signal based on the information written in the mode register or an access address signal from the processor core to the plurality of synchronous memory chips via the external bus selectively; and wherein the clock signal is commonly supplied to the plurality of synchronous memory chips.12-22-2011
20110314212MANAGING IN-LINE STORE THROUGHPUT REDUCTION - Various embodiments of the present invention manage a hierarchical store-through memory cache structure. A store request queue is associated with a processing core in multiple processing cores. At least one blocking condition is determined to have occurred at the store request queue. Multiple non-store requests and a set of store requests associated with a remaining set of processing cores in the multiple processing cores are dynamically blocked from accessing a memory cache in response to the blocking condition having occurred.12-22-2011
20110314211RECOVER STORE DATA MERGING - Various embodiments of the present invention merge data in a cache memory. In one embodiment a set of store data is received from a processing core. A store merge command and a merge mask from are also received from the processing core. A portion of the store data to perform a merging operation thereon is identified based on the store merge command. A sub-portion of the portion of the store data to be merged with a corresponding set of data from a cache memory is identified based on the merge mask. The sub-portion is merged with the corresponding set of data from the cache memory.12-22-2011
20110314210LEVERAGING CHIP VARIABILITY - Embodiments are described that leverage variability of a chip. Different areas of a chip vary in terms of reliability under a same operating condition. The variability may be captured by measuring errors over different areas of the chip. A physical factor that affects or controls the likelihood of an error on the chip can be varied. For example, the voltage supplied to a chip may be provided at different levels. At each level of the physical factor, the chip is tested for errors within the regions. Some indication of the error statistics for the regions is stored and then used to adjust power used by the chip, to adjust reliability behavior of the chip, to allow applications to control how the chip is used, to compute a signature uniquely identifying the chip, etc.12-22-2011
20130191587MEMORY CONTROL DEVICE, CONTROL METHOD, AND INFORMATION PROCESSING APPARATUS - A memory control device includes a first memory, a second memory, a third memory longer in a delay time since start-up until an actual data access, and a control unit. The second memory stores at least a part of data from each data string among multiple data strings with a given number of data as a unit. The third memory stores all of data within the plurality of data strings therein. If a cache miss occurs in the first memory, the control unit conducts hit determination of a cache in the second memory, and starts an access to the third memory. If the result of the hit determination is a cache hit, the control unit reads the part of data falling under the cache hit from the second memory as leading data, reads data other than the part of data, of a data string to which the part of data belongs, from the third memory, and makes a response as subsequent data to the leading data.07-25-2013
20130191586METHOD FOR OPERATING MEMORY CONTROLLER AND SYSTEM INCLUDING THE SAME - Methods of operating a memory controller include requesting data from each of a plurality of separate memory devices in response to an in-order multi-memory read request and then reading the requested data from the plurality of separate memory devices. The data read from the plurality of separate memory devices is then transmitted to a system bus along with at least one indication signal that identifies a relationship between an ordering of the requested data according to memory device and an ordering of the transmitted data according to memory device.07-25-2013
20130191585SIMULATING A MEMORY STANDARD - An apparatus includes multiple first memory circuits, each first memory circuit being associated with a first memory standard, where the first memory standard defines a first set of control signals that each first memory circuit circuits is operable to accept.07-25-2013
20130191584DETERMINISTIC HIGH INTEGRITY MULTI-PROCESSOR SYSTEM ON A CHIP - Systems integrated into a single electronic chip are provided for. The systems include a primary shared bus, a secondary shared bus and an embedded dynamic random access memory (eDRAM) including a first port and a second port. The systems also include a primary processor in operable communication with the eDRAM via the first port; and a secondary processor in operable communication with the eDRAM via the secondary bus and the second port, wherein the primary and secondary processors are operating in synchronization.07-25-2013
20120030418MEMORY CONTROLLER - A method for configuring a memory controller including determining whether a serial number of at least one memory module matches a stored serial number corresponding to at least one of the memory module and utilizing a stored timing data to configure the memory controller when the serial number matches the stored serial number corresponding to at least one of the memory module.02-02-2012
20120030417RAID CONTROLLER HAVING MULTI PCI BUS SWITCHING - Embodiments of the present invention provide a RAID controller with multi PCI bus switching for a storage device of a PCI-Express (PCI-e) type that supports a low-speed data processing speed for a host. Specifically, embodiments of this invention provide a RAID controller having multiple (e.g., two or more) sets of RAID circuitry that are interconnected/coupled to on another via a PCI bus. Each set of RAID circuitry is coupled to a one or more (i.e., a set of) semiconductor storage device (SSD) memory disk units. Among other things, the SSD memory disk units and/or HDD/Flash memory units adjust a synchronization of a data signal transmitted/received between the host and a memory disk during data communications between the host and the memory disk through a PCI-Express interface and simultaneously support a high-speed data processing speed for the memory disk, thereby supporting the performance of the memory to enable high-speed processing in an existing interface environment at the maximum.02-02-2012
20120297132MOTHERBOARD OF COMPUTING DEVICE - A motherboard of a computing device includes a dual inline memory module (DIMM), a processor socket, a platform controller hub (PCH), a switch, and a switch controller. The DIMM is connected to the processor socket or the PCH through the switch controller. The switch is connected to the switch controller, and generates a signal when the switch is operated. The switch controller controls the DIMM to connect either to the processor socket or to the PCH according to the signal, so that a solid state disk (SSD) or a memory that is connected to the DIMM can be supported appropriately by the motherboard.11-22-2012
20120066444Resolution Enhancement of Video Stream Based on Spatial and Temporal Correlation - A method, computer program product, and system are provided for associating one or more memory buffers in a computing system with a plurality of memory channels. The method can include associating a first memory buffer to a first plurality of memory banks, where the first plurality of memory banks spans over a first set of one or more memory channels. Similarly, the method can include associating a second memory buffer to a second plurality of memory banks, where the second plurality of memory banks spans over a second set of one or more memory channels. The method can also include associating a first sequence identifier and a second sequence identifier with the first memory buffer and the second memory buffer, respectively. Further, the method can include accessing the first and second memory buffers based on the first and second sequence identifiers.03-15-2012
20130205080APPARATUS AND METHOD FOR CONTROLLING REFRESHING OF DATA IN A DRAM - An apparatus comprises a dynamic random-access memory (DRAM) for storing data. Refresh control circuitry is provided to control the DRAM to periodically perform a refresh cycle for refreshing the data stored in each memory location of the DRAM. A refresh address sequence generator generates a refresh address sequence of addresses identifying the order in which memory locations of the DRAM are refreshed during the refresh cycle. To deter differential power analysis attacks on secure data stored in the DRAM, the refresh address sequence is generated with the addresses of at least a portion of the memory locations in a random order which varies from refresh cycle to refresh cycle.08-08-2013
20120079181TRANSLATING MEMORY MODULES FOR MAIN MEMORY - A translating memory module is disclosed including a printed circuit board, at least one memory integrated circuit coupled to the printed board, and at least one support chip coupled to the printed circuit board and coupled between the edge connector and the at least one memory integrated circuit. The at least one support chip includes a bi-directional translator to translate between a first memory communication protocol for the at least one memory integrated circuit and a second memory communication protocol for a memory channel differing from the first memory communication protocol. The second memory communication protocol to communicate data, address, and control signals over the memory channel bus to read and write data into the memory of the translating memory module.03-29-2012
20120079180DRAM Controller and a method for command controlling - A memory controller and a command control method are disclosed. When there is a need to access an unactivated bank in an external DRAM, an ACT command and an access command of a low rate are generated in parallel for the bank, and the parallel ACT and access commands of the low rate are sequentially output to a bus of the external DRAM in serial at a high rate.03-29-2012
20120079179Processor and method thereof - A processor and an operating method are described. By diversifying an L1 memory being accessed, based on an execution mode of the processor, an operating performance of the processor may be enhanced. By disposing a local/stack section in a system dynamic random access memory (DRAM) located external to the processor, a size of a scratch pad memory may be reduced without deteriorating a performance. While a core of the processor is performing in a very long instruction word (VLIW) mode, the core may data-access a cache memory and thus, a bottleneck may not occur with respect to the scratch pad memory even though a memory access occurs with respect to the scratch pad memory by an external component.03-29-2012
20130212329ELECTRONIC APPARATUS AND METHOD FOR MEMORY CONTROL - An electronic apparatus having plural memories of different performances such as bus widths facilitates achievement of its potential as a system. The electronic apparatus has a first memory and a memory controller configured to control the first memory. Upon a second memory being detected, the memory controller compares bus widths of the first memory and the second memory with each other. Upon the bus width of the second memory being broader than the bus width of the first memory, the memory controller makes a setting such that access to the second memory precedes access to the first memory.08-15-2013
20130212328High Throughput Interleaver/De-Interleaver - Systems and methods for performing high-speed multi-channel forward error correction using external DDR SDRAM is provided. According to one exemplary aspect, an interleaver/deinterleaver performs both read and write accesses to the DDR SDRAM that are burst-oriented by hiding active and precharge cycles in order to achieve high data rate operations. The interleaver/deinterleaver accesses data in the DDR SDRAM as read blocks and write blocks. Each block includes two data sequences. Each data sequence further includes a predetermined number of data words to be interleaved/deinterleaved. The PRECHARGE and ACTIVE command for one data sequence is issued when a preceding data sequence is being processed. Data in one read/write data sequence has the same row address within the same bank of the DDR SDRAM.08-15-2013

Patent applications in class Dynamic random access memory

Patent applications in all subclasses Dynamic random access memory