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Solid-state random access memory (RAM)

Subclass of:

711 - Electrical computers and digital processing systems: memory


711101000 - Specific memory composition

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Class / Patent application numberDescriptionNumber of patent applications / Date published
711105000 Dynamic random access memory 339
20090006728VIRTUAL MACHINE STATE SNAPSHOTS - Saving state of Random Access Memory (RAM) in use by guest operating system software is accomplished using state saving software that starts a plurality of compression threads for compressing RAM data blocks used by the guest. Each compression thread determines a compression level for a RAM data block based on a size of a queue of data to be written to disk, then compresses the RAM data block, and places the compressed block in the queue.01-01-2009
20130031304DATA STORAGE IN NONVOLATILE MEMORY - A method for data storage in a nonvolatile memory device includes compressing current data. The compressed current data is written to a space of the nonvolatile memory device that does not include a most recently written data. If the compressed current data is successfully written, identification data is stored on the nonvolatile memory device. The identification data identifies the written compressed current data as a currently valid version.01-31-2013
20120246400METHOD AND APPARATUS FOR PACKET SWITICHING - A method for performing packet lookups is provided. Packets (which each have a body and a header) are received and parsed to parsing headers. A hash function is applied to each header, and each hashed header is compared with a plurality of binary rules stored within a primary table, where each binary rule is a binary version of at least one ternary rule from a first set of ternary rules. For each match failure with the plurality of rules, a secondary table is searched using the header associated with each match failure, where the secondary table includes a second set of ternary rules.09-27-2012
20100077138Write Protection Method and Device for At Least One Random Access Memory Device - In a write protection method for at least one random access memory device, the inherent problems of such memory devices with regard to data integrity and security with respect to hacker attacks, such that they can also be used for secure archiving in particular of a large volume of data, are avoided by virtue of the fact that commands directed to the at least one memory device are received by a write protection device connected upstream of the at least one memory device before said commands are forwarded to the at least one memory device, wherein commands received in the write protection device are compared with a positive list of permitted commands previously stored in the write protection device, wherein in one case, where the comparison determines that a permitted command is present, said command is forwarded to the at least one memory device, and in the other case, where the comparison determines that no permitted command is present, said command is not forwarded to the at least one memory device.03-25-2010
20100106899Global address space management - Methods, systems and computer program products for global address space management are described herein. A System on Chip (SOC) unit configured for a global address space is provided. The SOC includes an on-chip memory, a first controller and a second controller. The first controller is enabled to decode addresses that map to memory locations in the on-chip memory and the second controller is enabled to decode addresses that map to memory locations in an off-chip memory.04-29-2010
20130046922CONTENT ADDRESSABLE MEMORY AND METHOD OF SEARCHING DATA THEREOF - The present invention discloses a content addressable memory and a method of searching data thereof. The method includes generating a hash index data item from a received input data item; searching the cache for presence of a row tag of the RAM data row corresponding to the data item of hash index; in response to presence, searching the RAM for a RAM data item corresponding to the input data item according to the corresponding row tag of the RAM data row; in response to absence, searching the RAM for a RAM data item corresponding to the input data item by using the data item of hash index; and in response to finding a RAM data item corresponding to the input data item in the RAM, outputting data corresponding to the RAM data item. The method can accelerate data search in the CAM.02-21-2013
20130073803COMBINED PARALLEL/SERIAL STATUS REGISTER READ - Methods and devices are disclosed, such as those involving a solid state memory device that includes a status register configured to be read with a combined parallel and serial read scheme. One such solid state memory includes a status register configured to store a plurality of bits indicative of status information of the memory. One such method of providing status information in the memory device includes providing the status information of a memory device in a parallel form. The method also includes providing the status information in a serial form after providing the status information in a parallel form in response to receiving at least one read command.03-21-2013
20130073802Methods and Apparatus for Transferring Data Between Memory Modules - A computer-implemented method for transferring data from a computer system programmed to perform the method includes receiving in a memory buffer in a first memory module hosted by the computer system, a request for data stored in RAM of the first memory module from a host controller of the computer system, retrieving with the memory buffer, the data from the RAM, in response to the request, formatting with the memory buffer, the data from the RAM into formatted data in response to a defined software transport protocol, and initiating with the memory buffer, transfer of the formatted data to a storage destination external to the first memory module via an auxiliary interface of the memory buffer, bypassing the host controller of the computer system.03-21-2013
20130067155Memory Type-Specific Access Control Of A Field Of A Record - A computing system includes computer memory of a number of different memory types. An application program compiled for execution on the computing system controls access to a field of a record in the computer memory of the computing system by defining a record that includes one or more fields, the one or more fields including a restricted field having a specification of restricted accessibility when the restricted field is allocated in a particular memory type; allocating an instance of the record in memory of the particular memory type; and denying each attempted access of the restricted field while the record is allocated in the particular memory type.03-14-2013
20110022790SYSTEMS AND METHODS FOR PROVIDING NONLINEAR JOURNALING - In one embodiment, systems and methods are provided for nonlinear journaling. In one embodiment, groups of data designated for storage in a data storage unit are journaled into persistent storage. In one embodiment, the journal data is recorded nonlinearly. In one embodiment, a linked data structure records data and data descriptors in persistent storage.01-27-2011
20090006729CACHE FOR A MULTI THREAD AND MULTI CORE SYSTEM AND METHODS THEREOF - According to one embodiment, the present disclosure generally provides a method for improving the performance of a cache of a processor. The method may include storing a plurality of data in a data Random Access Memory (RAM). The method may further include holding information for all outstanding requests forwarded to a next-level memory subsystem. The method may also include clearing information associated with a serviced request after the request has been fulfilled. The method may additionally include determining if a subsequent request matches an address supplied to one or more requests already in-flight to the next-level memory subsystem. The method may further include matching fulfilled requests serviced by the next-level memory subsystem to at least one requester who issued requests while an original request was in-flight to the next level memory subsystem. The method may also include storing information specific to each request, the information including a set attribute and a way attribute, the set and way attributes configured to identify where the returned data should be held in the data RAM once the data is returned, the information specific to each request further including at least one of thread ID, instruction queue position and color. The method may additionally include scheduling hit and miss data returns. Of course, various alternative embodiments are also within the scope of the present disclosure.01-01-2009
20130166833ELECTRONIC APPARATUS WITH A SAFE CONDITIONAL ACCESS SYSTEM (CAS) AND CONTROL METHOD THEREOF - An electronic apparatus is provided, which includes a central processing unit (CPU), a first memory unit which performs communication with the CPU, and a second memory unit which stores therein conditional access system (CAS) software and platform software. According to the method of controlling the apparatus, upon booting, the CPU copies the CAS software to an internal memory area which may be within the CPU, copies the platform software to the first memory unit and executes the CAS and platform software, and executes CAS operations through communication between the CAS software and the platform software.06-27-2013
20080294839System and method for dumping memory in computer systems - A method and system for dumping computer memory includes receiving an instruction to perform a dump of memory in a partitioned computer system where each partition has at least one processor and associated memory. The associated memory having a first portion and a second portion where the first portion is normally actively used for user application program or data storage. After receipt of the dump request, the source memory content is protected against corruption or contention from other program sources and copied into the second portion of memory. Preferably, the first and second portions are co-located RAM to provide speedy transfers of information. Access to the first portion of memory is then permitted by removing the protections and the user may have full access to run applications. The dump image is then transferred to any location as a background I/O task as the user executes his applications.11-27-2008
20110283059TECHNIQUES FOR ACCELERATING COMPUTATIONS USING FIELD PROGRAMMABLE GATE ARRAY PROCESSORS - Various embodiments are disclosed for accelerating computations using field programmable gate arrays (FPGA). Various tree traversal techniques, architectures, and hardware implementations are disclosed. Various disclosed embodiments comprise hybrid architectures comprising a central processing unit (CPU), a graphics processor unit (GPU), a field programmable gate array (FPGA), and variations or combinations thereof, to implement raytracing techniques. Additional disclosed embodiments comprise depth-breadth search tree tracing techniques, blocking tree branch traversal techniques to avoid data explosion, compact data structure representations for ray and node representations, and multiplexed processing of multiple rays in a programming element (PE) to leverage pipeline bubble.11-17-2011
20110302365STORAGE SYSTEM USING A RAPID STORAGE DEVICE AS A CACHE - Provided is a storage system using a high speed storage device as a cache. The storage system includes a large-volume of first storage device, a high speed second storage device, and a Random Access Memory (RAM). The large-volume of first storage device corresponds to a Hard Disk Drive (HDD), and the high speed second storage device corresponds to a Solid State Drive (SSD). Also, the high speed second drive is used as a cache. The first storage device manages content files super block by super block, and the second storage device manages cache files block by block.12-08-2011
20090138655METHOD AND TERMINAL FOR DEMAND PAGING AT LEAST ONE OF CODE AND DATA REQUIRING REAL-TIME RESPONSE - A method and terminal for demand paging at least one of code and data requiring a real-time response is provided. The method includes splitting and compressing at least one of code and data requiring a real-time response to a size of a paging buffer and storing the compressed at least one of code and data in a physical storage medium, if there is a request for demand paging for the at least one of code and data requiring the real-time response, classifying the at least one of code and data requiring the real-time response as an object of Random Access Memory (RAM) paging that pages from the physical storage medium to a paging buffer, and loading the classified at least one of code and data into the paging buffer.05-28-2009
20110219181PRE-FETCHING DATA INTO A MEMORY - Systems and methods for pre-fetching of data in a memory are provided. By pre-fetching stored data from a slower memory into a faster memory, the amount of time required for data retrieval and/or processing may be reduced. First, data is received and pre-scanned to generate a sample fingerprint. Fingerprints stored in a faster memory that are similar to the sample fingerprint are identified. Data stored in the slower memory associated with the identified stored fingerprints is copied into the faster memory. The copied data may be compared to the received data. Various embodiments may be included in a network memory architecture to allow for faster data matching and instruction generation in a central appliance.09-08-2011
20100115195HARDWARE MEMORY LOCKS - Methods, systems and computer program products to implement hardware memory locks are described herein. A system to implement hardware memory locks is provided. The system comprises an off-chip memory coupled to a SOC unit that includes a controller and an on-chip memory. Upon receiving a request from a requester to access a first memory location in the off-chip memory, the controller is enabled to grant access to modify the first memory location based on an entry stored in a second memory location of the on-chip memory. In an embodiment, the on-chip memory is Static Random Access Memory (SRAM) and the off-chip memory is Random Access Memory (RAM).05-06-2010
20120110254OBJECT PERSISTENCY - There is provided a method and computer system for object persistency that includes: running a program; storing an object of the program into a random access memory in response to determining that the object is a non-persistent object; and storing the object into a phase change memory in response to determining that the object is a persistent object. The method and computer system of the present disclosure do not need separate persistency layers, such that the programming model is light weighted, the persistency of object data is more simple and fast, and implicit transaction process is supported, thereby a great deal of development and runtime costs are saved.05-03-2012
20100088467MEMORY DEVICE AND OPERATING METHOD OF MEMORY DEVICE - A memory device may include a non-volatile memory and non-volatile RAM. The non-volatile memory may include a data block and a metadata block. Metadata information with respect to the data block may be included in the metadata block. A portion of metadata with respect to the data block or the metadata with respect to the metadata block may be stored in the non-volatile RAM.04-08-2010
20090235018Increased Magnetic Damping for Toggle MRAM - Magnetic random access memory (MRAM) devices and techniques for use thereof are provided. In one aspect, a magnetic memory cell is provided. The magnetic memory cell comprises at least one fixed magnetic layer; at least one first free magnetic layer separated from the fixed magnetic layer by at least one barrier layer; at least one second free magnetic layer separated from the first free magnetic layer by at least one spacer layer; and at least one capping layer over a side of the second free magnetic layer opposite the spacer layer. One or more of the first free magnetic layer and the second free magnetic layer comprise at least one rare earth element, such that the at least one rare earth element makes up between about one percent and about 10 percent of one or more of the first free magnetic layer and the second free magnetic layer.09-17-2009
20080282027SECURE AND SCALABLE SOLID STATE DISK SYSTEM - A solid state disk system is disclosed. The system comprises a user token and at least one level secure virtual storage controller, coupled to the host system. The system includes a plurality of virtual storage devices coupled to at least one secure virtual storage controller. A system and method in accordance with the present invention could be utilized in flash based storage, disk storage systems, portable storage devices, corporate storage systems, PCs, servers, wireless storage, and multimedia storage systems.11-13-2008
20110173384Internet-Safe Computer - The present invention eliminates the possibility of problems with viruses, worms, identity theft, and other hazards that may result from the connection of a computer to the Internet. It does so by creating a new configuration of components within the computer. In addition to commonly used components, two new components are added. These are a secondary hard drive and a secondary random access memory. When the computer is connected to the Internet these secondary components are used in place of their primary counterparts. The primary hard drive is electronically isolated from the Internet, thus preventing Internet contamination of the primary hard drive.07-14-2011
20100146198OPTIMAL POWER USAGE IN DECODING A CONTENT STREAM STORED IN A SECONDARY STORAGE - Decoding a content of interest with optimal power usage. In an embodiment, a central processing unit (CPU) retrieves the frames of a data stream of interest from a secondary storage and stores them in a random access memory (RAM). The CPU forms an index table indicating the locations at which each of the frames is stored. The index table is provided to a decoder, which processes the frames in sequence to recover the original data from the encoded data. By using the index information, the power usage is reduced at least in an embodiment when the decoding is performed by an auxiliary processor.06-10-2010
20080244167Electronic device and method for installing software - A peripheral for a computer and a method of using the peripheral is for installing software onto the computer using Direct Memory Access. The peripheral comprises a computer accessible medium and a program product. The program product has codes to read and write to the Random Access Memory of the computer; and to bypass restrictions of the host computer Operating System that prevent the peripheral from gaining full access to all portions of the host computer's Random Access Memory. The preferred methods of using the peripheral automatically install software on a computer or copies forensic data from the computer's Random Access Memory once the peripheral is connected to the computer.10-02-2008
20080288719Memory Tracing in an Emulation Environment - A system and method are disclosed to trace memory in a hardware emulator. In one aspect, a first Random Access Memory is used to store data associated with a user design during emulation. At any desired point in time, the contents of the first Random Access Memory are captured in a second Random Access Memory. After the capturing, the contents of the second Random Access Memory are copied to a visibility system. During the copying, the user design may modify the data in the first Random Access Memory while the captured contents within the second Random Access Memory remain unmodifiable so that the captured contents are not compromised. In another aspect, different size memories are in the emulator to emulate the user model. Larger memories have their ports monitored to reconstruct the contents of the memories, while smaller memories are captured in a snapshot RAM. Together the two different modes of tracing memory are used to provide visibility to the user of the entire user memory.11-20-2008
20080288718METHOD AND APPARATUS FOR MANAGING MEMORY FOR DYNAMIC PROMOTION OF VIRTUAL MEMORY PAGE SIZES - A computer implemented method, apparatus, and computer usable program code for managing real memory. In response to a request for a page to be moved into real memory, a contiguous range of real memory is reserved for the page corresponding to a contiguous virtual memory range to form a reservation within a plurality of reservations for the real memory. This reservation enables efficient promotion of pages to a larger page size. The page only occupies a portion of the contiguous range of real memory for the reservation. In response to a need for real memory, a selected reservation is released within the plurality of reservations based on an age of the selected reservation within the plurality of reservations.11-20-2008
20120297130STACK PROCESSOR USING A FERROELECTRIC RANDOM ACCESS MEMORY (F-RAM) FOR BOTH CODE AND DATA SPACE - A stack processor using a ferroelectric random access memory (F-RAM) for both code and data space which presents the advantages of easy stack pointer management inasmuch as the stack pointer is itself a memory address. Further, the time for saving all critical registers to memory is also minimized in that all registers are already maintained in non-volatile F-RAM per se.11-22-2012
20080209117Nonvolatile RAM - A nonvolatile RAM allows a read/write operation to be performed in a random manner with respect to a memory area, which is divided into a plurality of memory arrays each including a plurality of memory cells. Upon detection of an initialization signal, initialization is performed on at least one memory array, which is selected in advance. In addition, a disconnection control signal occurs so as to disconnect an access by an external device during a prescribed period for performing the initialization. The nonvolatile RAM is capable of protecting data from being irregularly read, modified, and reloaded with respect to at least one memory array, which is selected in advance, even when the nonvolatile RAM is frequently accessed by a prescribed application.08-28-2008
20100138596INFORMATION PROCESSOR AND INFORMATION PROCESSING METHOD - According to one embodiment, an information processor includes a connector, a determination module, a recognition module, and a cache control module. The connector connects a storage device to the information processor. The storage device is used as a cache by an operating system which controls the information processor. The determination module determines whether to use the storage device connected to the information processor as a data readable and writable storage area. The recognition module causes the operating system to recognize the storage device as a storage area when the determination module determines to use the storage device as a storage area. The cache controller controls the operating system to use the storage device as a cache when the determination module determines not to use the storage device as a storage area.06-03-2010
20090157954CACHE MEMORY UNIT WITH EARLY WRITE-BACK CAPABILITY AND METHOD OF EARLY WRITE BACK FOR CACHE MEMORY UNIT - A cache memory unit includes: a cache memory; an early write-back condition checking unit for checking whether an early write-back condition has been satisfied; and an early write-back execution unit for monitoring a memory bus connecting the cache memory unit and an external memory unit, and in response to the memory bus being idle and the early write-back condition being satisfied, for causing dirty data in the cache memory to be written back to the external memory unit using the memory bus.06-18-2009
20110125960FPGA Co-Processor For Accelerated Computation - A co-processor module for accelerating computational performance includes a Field Programmable Gate Array (“FPGA”) and a Programmable Logic Device (“PLD”) coupled to the FPGA and configured to control start-up configuration of the FPGA. A non-volatile memory is coupled to the PLD and configured to store a start-up bitstream for the start-up configuration of the FPGA. A mechanical and electrical interface is for being plugged into a microprocessor socket of a motherboard for direct communication with at least one microprocessor capable of being coupled to the motherboard. After completion of a start-up cycle, the FPGA is configured for direct communication with the at least one microprocessor via a microprocessor bus to which the microprocessor socket is coupled.05-26-2011
20120072656MULTI-TIER CACHING - A method for maintaining an index in multi-tier data structure includes providing a plurality of a storage devices forming the multi-tier data structure, caching an index of key-value pairs across the multi-tier data structure, wherein each of the key-value pairs includes a key, and one of a data value and a data pointer, the key-value pairs stored in the multi-tier data structure, providing a journal for interfacing with the multi-tier data structure, providing a plurality of zone allocators recording which zones of the multi-tier data structure are in used, and providing a plurality of zone managers for controlling access to cache lines of the multi-tier data structure through the journal and zone allocators, wherein each zone manager maintains a header object pointing to data to be stored in an allocated zone.03-22-2012
20090063760Systems, devices, and/or methods to access synchronous RAM in an asynchronous manner - Certain exemplary embodiments can provide a method, which can comprise, via a state machine implemented as an application specific integrated circuit, responsive to an automatically detected asynchronous RAM interface signal, automatically transmitting a corresponding synchronous RAM interface signal. The state machine can be communicatively coupled to a programmable logic controller.03-05-2009
20100205363MEMORY DEVICE AND WEAR LEVELING METHOD THEREOF - Disclosed is a memory device including a NVRAM and a page table, and a wear leveling method therefor. The page table includes mapping information which maps virtual addresses of the NVRAM with physical addresses of the NVRAM. A page table entry includes aging information which indicates the wear of a corresponding page. The aging information may be a remaining number of write operations allowed to the page. Whenever data is written in a page, a value indicating a remaining number of write operations allowed to that page is decremented.08-12-2010
20090055580MULTI-LEVEL DRAM CONTROLLER TO MANAGE ACCESS TO DRAM - Providing for multi-tiered RAM control is provided herein. As an example, a RAM access management system can include multiple input controllers each having a request buffer and request scheduler. Furthermore, a request buffer associated with a controller can vary in size with respect to other buffers. Additionally, request schedulers can vary in complexity and can be optimized at least for a particular request buffer size. As a further example, a first controller can have a large memory buffer and simple scheduling algorithm optimized for scalability. A second controller can have a small memory buffer and a complex scheduler, optimized for efficiency and high RAM performance. Generally, RAM management systems described herein can increase memory system scalability for multi-core parallel processing devices while providing an efficient and high bandwidth RAM interface.02-26-2009
20080263268Digital signal processor - A digital signal processor is adapted to a working RAM, which is capable of storing a plurality of data in a rewritable manner and whose storage area is divided into a plurality of sub-areas that are designated by addresses in read/write operations, wherein an operation circuit performs calculations on the data of the working RAM in accordance with a program, and wherein upon detection of a non-access event in which the program does not need to access the working RAM, a write circuit compulsorily writes ‘0’ into the working RAM with regard to each of the prescribed addresses of the prescribed sub-areas subjected to initialization, which are designated by address data. Thus, it is possible to actualize the selective initialization on the prescribed sub-areas within the working RAM without increasing the scale of the peripheral circuitry, without requiring complicated controls, and without increasing the overall processing time therefor.10-23-2008
20080263267SYSTEM ON CHIP WITH RECONFIGURABLE SRAM - A system on chip comprises N components, where N is an integer greater than one, and a storage module. The storage module comprises a first memory, a control module, and a connection module. The first memory includes M blocks of static random access memory, where M is an integer greater than one. The control module generates a first assignment of the M blocks to the N components during a first period and generates a second assignment of the M blocks to the N components during a second period. The first and second assignments are different. The connection module dynamically connects the M blocks to the N components based on the first and second assignments.10-23-2008
20090222620MEMORY DEVICE, INFORMATION PROCESSING APPARATUS, AND ELECTRIC POWER CONTROLLING METHOD - A memory device includes a memory unit that is nonvolatile and is made up of a plurality of memory areas; first retaining units each of which is provided in correspondence with a different one of the memory areas and each of which retains first setting information that defines whether a corresponding one of the memory areas is in an active state or a stop state; and an electric power-source controlling unit that supplies electric power to one or more of the memory areas that correspond to the first setting information defining the memory areas to be in the active state, and stops electric power supply to one or more of the memory areas that correspond to the first setting information defining the memory areas to be in the stop state.09-03-2009
20090204751MULTIPROCESSOR SYSTEM AND PORTABLE TERMINAL USING THE SAME - [PROBLEMS] To provide a portable terminal designated for speeding up the startup time of a multiprocessor system which is configured to be started up by a program being transferred from a specific processor to another processor. [MEANS OF SOLVING PROBLEMS] As a storing pattern of a program to a memory (ROM) transferred to another processor, a header is given to each code section. The header stores information as to whether or not the section needs to be transferred in each startup mode and size information of the corresponding code section. The startup time for each mode is shortened by enabling to transfer only the necessary portion from the transfer source processor to the transfer destination processor for each startup mode.08-13-2009
20090248968REDUCTION OF LATENCY IN STORE AND FORWARD ARCHITECTURES UTILIZING MULTIPLE INTERNAL BUS PROTOCOLS - Disclosed is a store and forward device that reduces latency. The store and forward device allows front end devices having various transfer protocols to be connected in a single path through a RAM, while reducing latency. Front end devices that transfer data on a piecemeal basis are required to transfer all of the data to a RAM prior to downloading data to a back end. Front end devices that transfer data in a single download begin the transfer of data out of a RAM as soon as a threshold value is reached. Hence, the latency associated with downloading all of the data into a RAM 10-01-2009
20100153633PC architecture using fast NV RAM in main memory - Systems and methods for a PC or server architecture have been disclosed. The architecture is characterized by using non-volatile RAM modules, such as MRAM modules, for at least a part of the main memory, thus accelerating the power-on sequence of the computer. Components, which were stored in prior art either in battery backed CMOS Modules or in flash memory have been deployed in the non-volatile part of the main memory. Such components can be power-on self test codes, system configuration information, device drivers, a portion of the Operating system, and a portion or all of application programs and related application data.06-17-2010
20100161893DISK SYSTEM USING MEMORY CONTROL SIGNAL OF PROCESSOR - The disk system of the present invention decreases defects of a volume restriction and a volatile characteristic of a RAM disk using a memory control signal of a host. The preset invention provides a disk system including a central control unit generating a memory control signal corresponding to a RAM memory and an external instruction and controlling the RAM memory, and wherein the RAM memory including a RAM disk constituted by RAMs and storing a system program and data; and a control signal processing unit converting the memory control signal into first and second memory control signals based on access information included in the memory control signal and controlling the RAM disk to access to the system program and the data by the second memory control signal.06-24-2010
20110107020HIBERNATION SOLUTION FOR EMBEDDED DEVICES AND SYSTEMS - An embedded device is hibernated by storing state data of the embedded device to a non-volatile data storage medium, and powering off the embedded device. The embedded device is later woken up in response to the detection of a wakeup event from a wakeup source. The state data stored in the RAM of the embedded device comprises data in one or more registers of a Central Processing Unit (CPU) of the embedded device, one or more registers of a system-on-chip (SOC) of the embedded device, and the system and applications code and data. Waking the embedded device comprises loading, from the non-volatile data storage medium, initial memory sections that are used to run a kernel of the embedded device. State data that is stored in the RAM of a system may be compressed by dividing the RAM into a plurality of sections and independently choosing, for each section in the plurality of sections, a corresponding compression arithmetic.05-05-2011
20100191904SYSTEM AND METHOD OF IMAGING A MEMORY MODULE WHILE IN FUNCTIONAL OPERATION - A memory module (e.g. a hard drive, an optical drive, a flash drive, etc.) associated with a computer system may be imaged without substantial interruption to the operation of the overall system. The imaging may include applying an image to the memory module while execution of one or more operations and/or algorithms that require at least intermittent access to information stored initially in the memory module is ongoing. This may enable a system associated with the memory module to continue with normal, or substantially normal, operation while the image is being applied to the memory module. The image applied to the memory module may, for example, update the system, restore the system to a previous state (e.g., to its state at a previous point in time), or otherwise modify the system with which it is associated.07-29-2010
20090144490METHOD, APPARATUS AND COMPUTER PROGRAM PRODUCT FOR PROVIDING IMPROVED MEMORY USAGE - An apparatus for providing improved memory usage may include a processor. The processor may be configured to receive media content data, direct storage of up to a predetermined amount of a most recently received portion of the media content data into a first memory reservoir, and, in response to storing the predetermined amount in the first memory reservoir, transfer oldest portions of the received media content from the first memory reservoir to a second memory reservoir to maintain the storage in the first memory reservoir at the predetermined amount.06-04-2009
20100241799MODULAR MASS STORAGE SYSGTEM AND METHOD THEREFOR - A modular mass storage system and method that enables cableless mounting of ATA and/or similar high speed interface-based mass storage devices in a computer system. The system includes a printed circuit board, a system expansion slot interface on the printed circuit board and comprising power and data pins, a host bus controller on the printed circuit board and electrically connected to the system expansion slot interface, docking connectors connected with the host bus controller to receive power and exchange data therewith and adapted to electrically couple with industry-standard non-volatile memory devices without cabling therebetween, and features on the printed circuit board for securing the memory devices thereto once coupled to the docking connectors.09-23-2010
20100153635Storage device with expandable solid-state memory capacity - In a particular embodiment, a circuit device is disclosed that includes a first interface to a high speed data bus of a host system and a second interface coupled to a first data storage device. The circuit device further includes a solid-state storage device having a first solid-state data storage medium and having at least one expansion slot to receive at least one second solid-state data storage medium to expand a memory capacity of the solid-state storage device. The circuit device also includes a control circuit adapted to receive data from the host system via the first interface and to selectively write the received data to one of the first data storage device and the solid-state storage device.06-17-2010
20100223425Monitoring Module - A system and associated method for monitoring the execution of software on one or more computers by receiving traffic from within the monitored computer(s). The monitoring may take place passively, such that the operation of the monitored computer or computers is completely unaffected by the monitoring. More intensive monitoring, such as maintenance of a shadow copy of the RAM of the monitored computer, may be initiated upon recognition of a pattern in the data received from the monitored computer. The execution of software on the monitored computer may be halted by the monitoring module. The monitoring module may also read from or write to the memories of the monitored computer.09-02-2010
20100211727 INTEGRATED CIRCUIT BOARD WITH SECURED INPUT/OUTPUT BUFFER - An integrated circuit card including a processor unit associated with RAM and with data exchange means for exchanging data with an external device, the RAM including a memory zone dedicated to exchanged data, and the processor unit being arranged to secure the dedicated memory zone and to store the exchanged data in said zone, and a method of managing the RAM of such a card.08-19-2010
20100161892PSEUDO DUAL-PORTED SRAM - A memory is described which includes a main memory array made up of multiple single-ported memory banks connected by parallel read and write buses, and a sideband memory equivalent to a single dual-ported memory bank. Control logic and tags state facilitates a pattern of access to the main memory and the sideband memory such that the memory performs like a fully provisioned dual-ported memory capable of reading and writing any two arbitrary addresses on the same cycle.06-24-2010
20120144103Two-Port Memory Implemented With Single-Port Memory Blocks - A two-port memory having a read port, a write port and a plurality of identical single-port RAM banks. The capacity of one of the single-port RAM banks is used to resolve collisions between simultaneous read and write accesses to the same single-port RAM bank. A read mapping memory stores instance information that maps logical banks and a spare bank to the single-port RAM banks for read accesses. Similarly, a write mapping memory stores write instance information that maps logical banks and a spare bank to the single-port RAM banks for write accesses. If simultaneous read and write accesses are not mapped to the same single-port RAM bank, read and write are performed simultaneously. However, if a collision exists, the write access is re-mapped to a spare bank identified by the write instance information, allowing simultaneous read and write. Both read and write mapping memories are updated to reflect any re-mapping.06-07-2012
20100057982Hypervisor security using SMM - Methods, systems, apparatuses and program products are disclosed for protecting computers and similar equipment from undesirable occurrences, especially attacks by malware. Invariant information, such as pure code and some data tables may be enrolled for later revalidation by code operating outside the normal context. For example, a periodic interrupt may invoked a system management mode interrupt service routine to discover whether code regions accessible to Protected Mode programs have become corrupted or otherwise changed, such as by tampering from untrusted or untrustworthy programs that have easy access only to protected mode operation.03-04-2010
20100199033SOLID-STATE DRIVE COMMAND GROUPING - A method and other embodiments associated with solid-state drive command grouping are described. In one embodiment, a first command and a second command are grouped into a command pack, where the first command and the second command do not share a common channel for execution. A solid-state drive is controlled to execute the command pack on the solid-state drive, where executing the command pack causes the first command and the second command to execute concurrently on separate channels.08-05-2010
20090210615OVERLAY MANAGEMENT IN A FLASH MEMORY STORAGE DEVICE - The operating firmware of a portable flash memory storage device is stored in the relatively large file storage memory, which is non executable. It is logically parsed into overlays to fit into an executable memory. The overlays can be of differing sizes to organize function calls efficiently while minimizing dead space or unnecessarily separating functions that should be within one or a group of frequently accessed overlays. Eviction of the overlays is preferably carried out on a least recently loaded basis. These features minimize latency caused by calling overlays unnecessarily and minimize fragmentation of the random access memory used for the overlays.08-20-2009
20080301360Random Access Memory for Use in an Emulation Environment - A Random Access Memory (RAM) and method of using the same are disclosed. The RAM includes a plurality of memory cells arranged in columns and in rows with each memory cell coupled to at least one word line and at least one bit line. The RAM includes a plurality of switches with at least one of the switches coupled between two of the memory cells to allow data to be copied from one of the two memory cells to the other of the two memory cells. In another aspect, the two memory cells can be considered a dual bit cell that contains a copying mechanism. There are two interleaved memory planes, assembled from bit cells that contain two bits of information. One bit is the primary bit that corresponds to the normal RAM bit. The second bit is able to receive a copy and hold the primary value. When the copying mechanism is over, the two memory planes may act as two completely independent structures.12-04-2008
20100318731OVERRIDE BOOT SEQUENCE BY PRESENCE OF FILE ON USB MEMORY STICK - Consistent with embodiments of the present invention, systems and methods are disclosed for operating an override boot sequence. In some embodiments, a system may comprise a computing device. The computing device may contain client software configured to boot the computing device to a normal state. The computing device may further contain a first memory, wherein the client software may be stored on the first memory. The system may further comprise an interface capable of communicating with a portable memory. The portable memory may contain an override application. The system may further comprise a bootloader program associated with the computing device, wherein the bootloader device may be configured to detect the presence of a connection of the portable memory and the interface. The bootloader program may further be configured to copy the override application to a second memory associated with the computing device and execute the override application instead of the client software.12-16-2010
20100306457Microcontroller with CAN Module - A microcontroller has a random access memory, and a Controller Area Network (CAN) controller with a control unit receiving an assembled CAN message. The control unit generates a buffer descriptor table entry using the assembled CAN message and stores the buffer descriptor table entry in the random access memory, and the buffer descriptor table entry has at least a message identifier and load data from the CAN message and information of a following buffer descriptor table entry.12-02-2010
20130138876COMPUTER SYSTEM WITH MEMORY AGING FOR HIGH PERFORMANCE - A memory manager in a computer system that ages memory for high performance. The efficiency of operation of the computer system can be improved by dynamically setting an aging schedule based on a predicted time for trimming pages from a working set. An aging schedule that generates aging information that better discriminates among pages in a working set based on activity level enables selection of pages to trim that are less likely to be accessed following trimming. As a result of being able to identify and trim less active pages, inefficiencies arising from restoring trimmed pages to the working set are avoided.05-30-2013
20110040933Secure Zero-Touch Provisioning of Remote Management Controller - Embodiments enable secure zero-touch remote provisioning/management of a computer system. A computer system is shipped to end customers with its remote management controller enabled but not provisioned. During automatic testing, for example, provisioning authentication data is embedded into the remote management controller. The computer system vendor harvests the provisioning authentication data or derivative data therefrom from the remote management controller and stores it in a database. Upon sale of the computer system, the computer system vendor provides to the end-customer the harvested data of the computer system's remote management controller. The end-customer can then remotely authenticate a remote provisioning/management console to the remote management controller. Once successfully authenticated, the remote provisioning/management console can provision the remote management controller with one or more user accounts/roles with corresponding authentication details, authenticate as one of the provisioned user accounts, and perform computer system provisioning using remote manageability functions as desired.02-17-2011
20100153634SYSTEM AND METHOD FOR DATA MIGRATION BETWEEN COMPUTER CLUSTER ARCHITECTURE AND DATA STORAGE DEVICES - An improved duty cycle, increased effective bandwidth, and minimized power consumption are attained in a system for data migration between a compute cluster and disk drives by inclusion of a buffer node coupled to the compute cluster to store data received therefrom in a random fashion. The buffer node signals the computer nodes to promptly return from the I/O cycle to the computing state to improve the duty cycle of the device. The system further includes a storage controller which is coupled between the buffer node and the disk drives to schedule data transfer activity between them in an optimal orderly manner. The data transfers are actuated in the sequence determined based on minimization of seeking time and tier usage, and harvest priority, when the buffer node either reaches a predetermined storage space minimal level or a predetermined time has elapsed since the previous I/O cycle. The storage controller deactivates the disk drives which are not needed for the data transfer. Since the writing on the disk drives is conducted in the orderly manner, the system avoids the usage of excessive number of disk drives.06-17-2010
20110119437Sequentially Written Journal in a Data Store - Systems, methods, and computer storage media for storing and retrieving data from a data store in a distributed computing environment are provided. An embodiment includes receiving data at a data store comprising a sequential journal store, RAM, and a non-sequential target store. When RAM utilization is below a threshold, received data is stored to the RAM as a write cache for the target store and the journal store. But, when the utilization is above the threshold, the data is stored to the journal store without write-caching to the RAM for the target store. When the RAM utilization falls below a threshold, data committed to the journal store, but not write-cached to the RAM for the target store, is later read from the journal store and write-cached to the RAM for a target store.05-19-2011
20110145491METHOD FOR CONTROLLING ACCESS TO REGIONS OF A MEMORY FROM A PLURALITY OF PROCESSES AND A COMMUNICATION MODULE HAVING A MESSAGE MEMORY FOR IMPLEMENTING THE METHOD - A method for controlling access to regions of a memory from a plurality of processes. In order to allow a plurality of processes to access the most recent data packets stored in the memory without any loss of data and without a waiting period, according to the present invention a first one of the processes controls part of an address bus using which another one of the processes accesses the memory, the first process influencing which memory region is accessed by the other process by controlling the part of the address bus.06-16-2011
20110087833LOCAL NONVOLATILE WRITE-THROUGH CACHE FOR A DATA SERVER HAVING NETWORK-BASED DATA STORAGE, AND RELATED OPERATING METHODS - A data server, a host adapter system for the data server, and related operating methods facilitate data write and read operations for network-based data storage that is remotely coupled to the data server and for non-network-based data storage in a locally attached cache device. The host adapter system includes a local storage controller module and a network storage controller module. The local storage controller module is utilized for a locally attached, nonvolatile, write-through cache device of the data server. The network storage controller module is utilized for a network-based data storage architecture of the data server. The storage controller modules support concurrent writing of data to the local cache storage and the network-based storage architecture. The storage controller modules also support reading of server-maintained data from the local cache storage and the network-based storage architecture.04-14-2011
20110082970SYSTEM FOR DISTRIBUTING AVAILABLE MEMORY RESOURCE - A system for distributing available memory resource comprising at least two random access memory (RAM) elements and RAM routing logic. The RAM routing logic comprises configuration logic to dynamically distribute the available memory resource into a first memory area providing redundant memory storage and a second memory area providing non-redundant memory storage.04-07-2011
20110078368EFFICIENT CLOCKING SCHEME FOR A BIDIRECTIONAL DATA LINK - A method for communication via a bidirectional data link between a processing device and a memory device. The memory device includes a clock source to generate a clock signal for driving a latching at the memory device of data to and/or from the bidirectional data link. The memory device provides the clock signal to the processing device for driving a latching at the processing device of data to and/or from the bidirectional data link.03-31-2011
20100070695POWER-EFFICIENT MEMORY MANAGEMENT FOR EMBEDDED SYSTEMS - Embodiments of the invention provide a memory allocation module that adopts memory-pool based allocation and is aware of the physical configuration of the memory blocks in order to manage the memory allocation intelligently while exploiting statistical characters of packet traffic. The memory-pool based allocation makes it easy to find empty memory blocks. Packet traffic characteristics are used to maximize the number of empty memory blocks.03-18-2010
20110099327SYSTEM AND METHOD FOR LAUNCHING AN APPLICATION PROGRAMMING UTILIZING A HYBRID VERSION OF DEMAND PAGING - A system and method for launching a computer application program stored in a nonvolatile medium, wherein by reusing a page load scheme from a standard demand page based launch. The system and method includes launching a computer application program one or more times using demand paging to load memory pages of the nonvolatile medium associated with the computer application into a volatile memory for execution of the computer application program. Memory address information corresponding to the pages of the nonvolatile medium corresponding to portions of the computer application program accessed during use of the computer application program are stored in a launch record. The computer application program is launched using the address information stored in the launch record to read nonvolatile medium addresses stored in the launch record in a single or consecutive read step.04-28-2011
20110153923HIGH SPEED MEMORY SYSTEM - A high speed memory system includes a plurality of memory devices; a plurality of buffers; and a memory controller. The plurality of buffers is respectively coupled to the plurality of memory devices. The memory controller is coupled to the plurality of buffers, for generating a plurality of control signal to the plurality of buffers and sequentially controlling access to the plurality of memory devices in a time-sharing manner according to a clock.06-23-2011
20110078369Systems and Methods for Using a Page Table in an Information Handling System Comprising a Semiconductor Storage Device - Systems and methods for using a page table in an information handling system including a semiconductor storage device are disclosed. A page table in an information handling system may be provided. The information handling system may include a memory, and the memory may include a semiconductor storage device. NonDRAM tag data may be stored in the page table. The nonDRAM tag data may indicate one or more attributes of one or more pages in the semiconductor storage device.03-31-2011
20110078367CONFIGURABLE CACHE FOR MULTIPLE CLIENTS - One embodiment of the present invention sets forth a technique for providing a L1 cache that is a central storage resource. The L1 cache services multiple clients with diverse latency and bandwidth requirements. The L1 cache may be reconfigured to create multiple storage spaces enabling the L1 cache may replace dedicated buffers, caches, and FIFOs in previous architectures. A “direct mapped” storage region that is configured within the L1 cache may replace dedicated buffers, FIFOs, and interface paths, allowing clients of the L1 cache to exchange attribute and primitive data. The direct mapped storage region may used as a global register file. A “local and global cache” storage region configured within the L1 cache may be used to support load/store memory requests to multiple spaces. These spaces include global, local, and call-return stack (CRS) memory.03-31-2011
20100070694COMPUTER SYSTEM HAVING RAM SLOTS WITH DIFFERENT SPECIFICATIONS - A computer system is able to adopt a RAM module belonged to a first specification with a RAM slot belonged to a second specification. The computer system comprises: a RAM module belonged to the first specification, a RAM sot belonged to the second specification, and a RAM controller connected to the RAM slot. The data, derived from the RAM module and only existed in the first specification, is transmitted to the RAM controller via the N/A pins of the RAM slot when the RAM module is plugged in the RAM slot.03-18-2010
20120072657SYSTEM AND METHOD TO WRITE DATA USING PHASE-CHANGE RAM - A data recording system includes a file system configured to manage block-based input/output of data, a phase-change random access memory (PRAM) configured to write first data among the data in units of sub blocks, and a block abstract layer configured to receive a write command of the first data to a first particular block in the PRAM from the file system and log changed data information to a second particular block in the PRAM in units of sub blocks, and a method to provide the same.03-22-2012
20120072658PROGRAM, CONTROL METHOD, AND CONTROL DEVICE - Provided is a program, control method, and control device that can shorten start-up time. Page table entry is rewritten for a Memory Management Unit (MMU) table, on a computer system equipped with an MMU, so that a page fault will occur at every page, for all the pages necessary for the operation of a software program. Upon start-up, the stored memory image is loaded in page units for page faults that have occurred on the RAM to be accessed. Loading of unnecessary pages will not be executed, because such loading was executed, and the start-up time can be shortened worth that time. This program, control method, and control device can be applied to personal computers, and electronic devices equipped with built-in type computers.03-22-2012
20090063759SYSTEM AND METHOD FOR PROVIDING CONSTRAINED TRANSMISSION AND STORAGE IN A RANDOM ACCESS MEMORY - A system and method for providing constrained transmission and storage in a random access memory. A system includes a memory device for providing constrained transmission and storage. The memory device includes an interface to a data bus, the data bus having a previous state. The memory device also includes an interface to an address and command bus for receiving a request to read data at an address, and a mechanism for initiating a programmable mode. The programmable mode facilitates retrieving data at the address, and executing an exclusive or (XOR) using the retrieved data and the previous state of the data bus as input. The result of the XOR operation is transmitted to the requester via the data bus.03-05-2009
20090055581DATA STORAGE DEVICE AND DATA PROVIDING METHOD THEREIN - A data storage device, the data storage device may include: a data storage unit; a system data storage unit that stores an application program, an operating system (OS), and management information related to a processing of the stored data; a system control unit that performs an initialization, a control, and a system setting of the device; a central processing unit (CPU) that performs data processing including data read and data write and processes an instruction word; a random access memory (RAM) that loads the data from the data storage unit and the system data storage unit, loads the instruction word of the CPU, and temporarily stores a data processing result of the processed instruction word; and an output determination unit that determines to output at least one of the data stored in the data storage unit, the application program, and the data processing result.02-26-2009
20080229006High Bandwidth Low-Latency Semaphore Mapped Protocol (SMP) For Multi-Core Systems On Chips - A system and method for dynamically managing movement of semaphore data within the system. The system includes, but is no limited to, a plurality of functional units communicating over the network, a memory device communication with the plurality of functional units over the network, and at least one semaphore storage unit communicating with the plurality of functional unites and the memory device over the network. The plurality of functional units include a plurality of functional unit memory locations. The memory device includes a plurality of memory device memory locations. The at least one semaphore storage unit includes a plurality of semaphore storage unit memory locations. The at least one semaphore storage unit controls dynamic movement of the semaphore data among the plurality of functional unit memory locations, the plurality of memory device memory locations, the plurality of semaphore storage unit memory locations, and any combinations therof.09-18-2008
20110161574SETTING CONTROL APPARATUS AND METHOD FOR OPERATING SETTING CONTROL APPARATUS - A setting control apparatus includes a setting control part, a special register, and a read-out control part. The setting control part makes stored in a temporary storage part a control value used in a processing circuit, in response to an input of the control value. The special register is electrically connected to the processing circuit and serving as a storage element capable of storing the control value. The read-out control part controls a read-out operation for reading out the control value from the temporary storage part into the special register. The read-out control part performs the read-out operation at a predetermined timing after storing of the control value in the temporary storage part is completed.06-30-2011
20110161575MICROCODE REFACTORING AND CACHING - Methods and apparatus relating to microcode refactoring and/or caching are described. In some embodiments, an off-chip structure that stores microcode is shared by multiple processor cores. Other embodiments are also described and claimed.06-30-2011
20110258374METHOD FOR OPTIMIZING THE MEMORY USAGE AND PERFORMANCE OF DATA DEDUPLICATION STORAGE SYSTEMS - A method and system of optimizing the memory usage and performance of data deduplication storage systems includes organizing the metadata of data blocks needed by deduplicating storage systems. A three level hierarchy is used. Level 1 stores the metadata on disk along with the user data. Level 2 uses low latency storage (e.g. RAM and Solid State Disks) to cache the on-disk meta data for faster direct access. Level 3 organizes the fingerprints using a Trie and is entirely resident in RAM. Thus, the search, to determine whether a data block is unique or not and a candidate for transfer, can be more efficiency executed and to ensure that the meta data is transactionally secure.10-20-2011
20110264853Signal control device and signal control method - A signal control device includes: a dual port RAM from or to which data signals are read and written at predetermined operation timings by first and second CPUs connected to two ports, respectively; an address collision detection unit detecting collision between addresses in which the first and second CPUs respectively read and write the data signal from and to the dual port RAM; a first storage unit storing the data signal read by the first CPU; a second storage unit storing the data signal read from the address in which the second CPU writes the data signal to the dual port RAM when the collision between the addresses is detected; and a switching unit switching a reading source outputting the data signal to the port to which the first CPU is connected and outputting the read data signal to the first CPU entering a readable state.10-27-2011
20110119438FLASH MEMORY FILE SYSTEM - Apparatus having corresponding methods and computer-readable media comprise: a plurality of flash modules, wherein each of the flash modules comprises a cache memory; a flash memory; and a flash controller in communication with the cache memory and the flash memory; wherein the flash controller of a first one of the flash modules is configured to operate the cache memories together as a global cache; wherein the flash controller of a second one of the flash modules is configured to operate a second one of the flash modules as a directory controller for the flash memories.05-19-2011
20100185809Control System and Control Method of Virtual Memory - A control method of a virtual memory is adapted for using in a computer. The control method includes the following steps. First, a plurality of application programs executed in the computer are monitored. Second, the application programs are compared with at least a predetermined program, respectively. Third, the virtual memory of a solid state disk (SSD) is controlled to be turned on or turned off according to a comparing result. Herein, the virtual memory of the SSD is controlled to be turned on or turned off to enhance both lifetime of the SSD and operation efficiency of the computer.07-22-2010
20100122023PORTABLE ELECTRONIC DEVICE AND METHOD FOR PROTECTING DATA OF THE PORTABLE ELECTRONIC DEVICE - A portable electronic device includes a random access memory, a non-volatile random access memory, a detecting unit, and a processing unit. The detecting unit is configured to detect an acceleration of the portable electronic device. The processing unit is configured to compare a value of the acceleration of the portable electronic device with a predetermined parameter. If the value of the acceleration is greater or equal to the predetermined parameter, data is copied from the random access memory to the non-volatile random access memory.05-13-2010
20100057981METHODS AND DEVICES FOR EXECUTING DECOMPRESSED OPTION MEMORY IN SHADOW MEMORY - Methods and systems for executing a decompressed portion of an option memory in a shadow memory. An area of system memory is allocated and a portion of the option memory is decompressed using the allocated area. The decompressed portion is stored in the shadow memory so the decompressed portion can be executed in shadow memory.03-04-2010
20090300277DEVICES AND METHODS FOR OPERATING A SOLID STATE DRIVE - The present disclosure includes methods and devices for operating a solid state drive. One method embodiment includes receiving an indication of a desired number of write input/output operations (IOPs) per unit time performed by the solid state drive. The method can also include managing the number of write IOPs performed by the solid state drive at least partially based on the desired number of write IOPs per unit time, a number of spare blocks in the solid state drive, and a desired operational life for the solid state drive.12-03-2009
20100030954INFORMATION PROCESSING SYSTEM AND SEMICONDUCTOR STORAGE DEVICE - A random access memory includes a data signal line, a data-synchronization signal line for a data synchronization signal which provides a synchronization signal when data is transmitted to the data signal line, and a setting module. The setting module determines whether the data signal line is set to be a data signal line for common input/output use, a data signal line for output-only use, or a data signal line for input-only use, and further determines whether the data-synchronization signal line is set to be a data-synchronization signal line for common input/output use, a data-synchronization signal line for output-only use, or a data-synchronization signal line for input-only use.02-04-2010
20100030953HIGH-SPEED SOLID STATE STORAGE SYSTEM HAVING A NON-VOLATILE RAM FOR RAPIDLY STORING ADDRESS MAPPING INFORMATION - A solid state storage system incorporating a non-volatile randome access memory (NVRAM) that exhibits a reduced storage time is presented. The solid state storage system includes a memory area, a controller, and an information storage area. The controller is configured to control the memory area. The information storage area controlled by the controller and is configured to store logical address mapping information and physical address mapping information of the memory area.02-04-2010
20090193185Method for accessing the physical memory of an operating system - A method for accessing the physical memory with an operating system, providing for mapping the physical address to the linear address of the memory in the operating system. Thus to access the user-space of the memory with an operating system is practically to read and write data in the kernel-space of the memory to achieve quick access of the physical memory.07-30-2009
20120059982INTEGRATED CIRCUIT FOR EXECUTING EXTERNAL PROGRAM CODES AND METHOD THEREOF - An integrated circuit for executing external program codes comprises a processor, a read only memory for storing program codes of a first routine and a second routine, and a random access memory comprising a first memory block and a second memory block. The processor executes the first routine and uses a plurality of first memory units in the first memory block for accessing data. The processor executes the second routine and uses a plurality of second memory units in the first memory block for accessing data. The first and second memory units comprise one or more common memory units. The processor executes a third routine stored in an external read only memory and accesses the data of the third routine in the second memory block.03-08-2012
20120159058MEMORY SYSTEM AND METHOD FOR WRITING DATA INTO MEMORY SYSTEM - A memory system of one embodiment includes: a nonvolatile memory including a plurality of word lines each connected to memory cells, each one of the memory cells being capable storing two bits, the memory cells connected to one of the plurality of word lines constituting an upper page and a lower page, each one of the pages being a unit of data programming; a random access memory configured to store an address translation table indicating relationships between logical addresses designated by a host and physical addresses in the nonvolatile memory. The memory system of the embodiment further includes a memory controller which execute data fixing for saving the address translation table from the random access memory to the nonvolatile memory; and write dummy data to at least one page subsequent to the page in which valid data has been written in the nonvolatile memory before executing the data fixing.06-21-2012
20120159056POWER FILTER IN DATA TRANSLATION LOOK-ASIDE BUFFER BASED ON AN INPUT LINEAR ADDRESS - A method and an apparatus for power filtering in a Translation Look-aside Buffer (TLB) are described. In the method and apparatus, power consumption reduction is achieved by suppressing physical address (PA) reads from random access memory (RAM) if the previously translated linear address (LA), or virtual address (VA), is the same as the currently requested LA. To provide the correct translation, the output of the TLB is maintained if the previously translated LA and the LA currently requested for translation are the same.06-21-2012
20120159057MEMORY POWER TOKENS - Techniques are described for controlling availability of memory. As memory write operations are processed, the contents of memory targeted by the write operations are read and compared to the data to be written. The availability of the memory for subsequent write operations is controlled based on the outcomes of the comparing. How many concurrent write operations are being executed may vary according to the comparing. In one implementation, a pool of tokens is maintained based on the comparing. The tokens represent units of power. When write operations require more power, for example when they will alter the values of more cells in PCM memory, they draw (and eventually return) more tokens. The token pool can act as a memory-availability mechanism in that tokens must be obtained for a write operation to be executed. When and how many tokens are reserved or recycled can vary according to implementation.06-21-2012
20110066795STREAM CONTEXT CACHE SYSTEM - The present invention is directed to a stream context cache system, which primarily includes a cache and a mapping table. The cache stores plural stream contexts, and the mapping table stores associated stream context addresses in a system memory. Consequently, a host may, according to the content of the mapping table, directly retrieve the stream context that is pre-fetched and stored in the cache, rather than read the stream context from the system memory.03-17-2011
20110107021Column Oriented In-Memory Page Caching - A one-dimensional array is allocated in an in-memory cache for each column in a set of tabular data. The data type of each one-dimensional array is set to be the same as the data type of the corresponding column in the tabular data. Once the one-dimensional arrays have been allocated in memory, a portion of the data from each column in the tabular data is stored in a corresponding one-dimensional array. The tabular data stored in the one-dimensional arrays in the cache may then be utilized to generate an on-screen display of a portion of the tabular data.05-05-2011
20110107019APP (A PRIORI PROBABILITY) STORAGE DESIGN FOR LTE TURBO DECODER WITH QUADRATIC PERMUTATION POLYNOMIAL INTERLEAVER - Systems and methodologies are described that facilitate ensuring contention and/or collision free memory within a turbo decoder. A Posteriori Probability (APP) Random Access Memory (RAM) can be segmented or partitioned into two or more files with an interleaving sub-group within each file. This enables parallel operation in a turbo decoder and allows a turbo decoder to access multiple files simultaneously without memory access contention.05-05-2011
20120317350USING EXTENDED ASYNCHRONOUS DATA MOVER INDIRECT DATA ADDRESS WORDS - An abstraction for storage class memory is provided that hides the details of the implementation of storage class memory from a program, and provides a standard channel programming interface for performing certain actions, such as controlling movement of data between main storage and storage class memory or managing storage class memory.12-13-2012
20100095057NON-VOLATILE RESISTIVE SENSE MEMORY ON-CHIP CACHE - Various embodiments of the present invention are generally directed to an apparatus and associated method for a non-volatile resistive sense memory on-chip cache. In accordance with some embodiments, a processing circuit is formed on a first semiconductor substrate. A second semiconductor substrate is affixed to the first semiconductor substrate to form an encapsulated integrated chip package, wherein a non-volatile storage array of resistive sense memory (RSM) cells is formed on the second semiconductor substrate to cache data used by the processing circuit.04-15-2010
20100095056RAM Control Device and Memory Device Using The Same - In a RAM control device, an arbiter circuit (04-15-2010
20120166721SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, METHOD OF CONTROLLING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, AND CACHE DEVICE - There are provided a semiconductor integrated circuit device, a method of controlling a semiconductor integrated circuit device, and a cache device capable of efficiently implementing power saving, wherein the cache device includes a low-voltage operation enabling cache (06-28-2012
20120137059CONTENT LOCALITY-BASED CACHING IN A DATA STORAGE SYSTEM - A data storage caching architecture supports using native local memory such as host-based RAM, and if available, Solid State Disk (SSD) memory for storing pre-cache delta-compression based delta, reference, and independent data by exploiting content locality, temporal locality, and spatial locality of data accesses to primary (e.g. disk-based) storage. The architecture makes excellent use of the physical properties of the different types of memory available (fast r/w RAM, low cost fast read SSD, etc) by applying algorithms to determine what types of data to store in each type of memory. Algorithms include similarity detection, delta compression, least popularly used cache management, conservative insertion and promotion cache replacement, and the like.05-31-2012
20120254526ROUTING, SECURITY AND STORAGE OF SENSITIVE DATA IN RANDOM ACCESS MEMORY (RAM) - A method and apparatus for securely storing and accessing processor state information in random access memory (RAM) at a time when the processor enters an inactive power state.10-04-2012
20120084496VALIDATING PERSISTENT MEMORY CONTENT FOR PROCESSOR MAIN MEMORY - Subject matter disclosed herein relates to validating memory content in persistent main memory of a processor.04-05-2012
20120260031ENHANCED PIPELINING AND MULTI-BUFFER ARCHITECTURE FOR LEVEL TWO CACHE CONTROLLER TO MINIMIZE HAZARD STALLS AND OPTIMIZE PERFORMANCE - This invention is a data processing system including a central processing unit, an external interface, a level one cache, level two memory including level two unified cache and directly addressable memory. A level two memory controller includes a directly addressable memory read pipeline, a central processing unit write pipeline, an external cacheable pipeline and an external non-cacheable pipeline.10-11-2012
20080301361Dedicated flow manager between the processor and the random access memory - The invention proposes a flow manager between the main processor and the random access memory that improves performances and security with a memory access management interface processor positioned in interface between the main processor and the random access memory, this memory access management interface processor selecting the relevant flow characteristics with which it feeds an interface dedicated storage unit, the interface dedicated storage unit being only accessible by the memory access management interface processor, the embodiment of this invention may be either hardware or logic.12-04-2008
20120239872PRE-FETCHING DATA INTO A MEMORY - Systems and methods for pre-fetching of data in a memory are provided. By pre-fetching stored data from a slower memory into a faster memory, the amount of time required for data retrieval and/or processing may be reduced. First, data is received and pre-scanned to generate a sample fingerprint. Fingerprints stored in a faster memory that are similar to the sample fingerprint are identified. Data stored in the slower memory associated with the identified stored fingerprints is copied into the faster memory. The copied data may be compared to the received data. Various embodiments may be included in a network memory architecture to allow for faster data matching and instruction generation in a central appliance.09-20-2012
20120239871VIRTUAL ADDRESS PAGER AND METHOD FOR USE WITH A BULK ERASE MEMORY - A virtual address pager and method for use with a bulk erase memory is disclosed. The virtual address pager includes a page protection controller configured with a heap manager interface configured to receive only bulk erase memory-backed page requests for a plurality of memory pages. A RAM object cache controller is configured to store and bulk write data for a portion of the bulk erase memory. The page protection controller may have an operating system interface configured to generate a page memory access permission for each of the plurality of memory pages. The page protection controller may be configured to receive a virtual memory allocation request and generate the page memory access permission based on the virtual memory allocation request.09-20-2012
20120239870FIFO APPARATUS FOR THE BOUNDARY OF CLOCK TREES AND METHOD THEREOF - A FIFO apparatus uses a first clock signal in a first clock domain to receive an input signal and uses a second clock signal in a second clock domain to output an output signal. An example apparatus includes: at least three write registers belonging to the first clock domain for receiving the input signal. Each of the write registers has a first output. A first controller belonging to the first clock domain enables the registers, in accordance with an order, to generate an initial signal. A multiplexer receives the first outputs. A second controller belonging to the second clock domain, receives the initial signal through an asynchronous interface and controls the multiplexer to output the first outputs in accordance with the order to be the output signal, wherein the second clock domain is a clock tree generated based on the first clock domain.09-20-2012
20120324156METHOD AND SYSTEM OF ORGANIZING A HETEROGENEOUS MEMORY ARCHITECTURE - An exemplary embodiment of the present invention may build data blocks in non-volatile memory. The corresponding parity blocks may be built in a fast, high endurance memory.12-20-2012
20120278547Method and system for hierarchically managing storage resources - The disclosure discloses a method for hierarchically managing storage resources, which comprises: planning a storage space, establishing an address management index, and storing or reading data according to the index and a type of the data. The disclosure further discloses a system for hierarchically managing storage resources. Through the method and system of the disclosure, space can be better saved, storage requirements of data of different sizes can be met, and the storage space can be flexibly recorded and released.11-01-2012
20110320693Method For Paramaterized Application Specific Integrated Circuit (ASIC)/Field Programmable Gate Array (FPGA) Memory-Based Ternary Content Addressable Memory (TCAM) - A method and apparatus for providing TCAM functionality in a custom integrated circuit (IC) is presented. An incoming key is broken into a predefined number of sub-keys. Each sub-key is sued to address a Random Access Memory (RAM), one RAM for each sub-key. An output of the RAM is collected for each sub-key, each output comprising a Partial Match Vector (PMV). The PMVs are bitwise ANDed to obtain a value which is provided to a priority encoder to obtain an index. The index is used to access a result RAM to return a result value for the key.12-29-2011
20120290780Multithreaded Operation of A Microprocessor Cache - A method of fetching data from a cache begins by preparing to fetch a first set of cache ways for a first data word of a first cache line a using a first thread. Next, in parallel, a second set cache ways for a first data word of a second cache line is prepared to be fetched using a second thread, and data associated with each cache way of the first set of cache ways are fetched using the first thread. Also performed in parallel, data associated with each cache way of the second set of cache ways is fetched using the second thread and a third set of cache ways for a second data word of the first cache line is prepared to be fetched using the first thread based on a selected cache way, the selected cache way selected from the first set of cache ways.11-15-2012
20120290781NONVOLATILE MEMORY DEVICE WITH INCREASED ENDURANCE AND METHOD OF OPERATING THE SAME - A non-volatile memory device including a memory unit configured to store user data and metadata and a memory controller unit. The memory controller unit is configured to access the memory unit in response to a request from an external host, create metadata which is to be recorded in the memory unit, and convert a format of the metadata based on a result of counting the number of times the memory unit is accessed.11-15-2012
20080222351HIGH-SPEED OPTICAL CONNECTION BETWEEN CENTRAL PROCESSING UNIT AND REMOTELY LOCATED RANDOM ACCESS MEMORY - A data transmission assembly includes a first connection terminal coupled to a processing unit and a second connection terminal coupled to a random access memory (RAM) resource. The data transmission assembly also includes a first electrical/optical (EO) signal converter and a second EO signal converter. The first EO signal converter is coupled to the first connection terminal and the second EO signal converter is coupled to the second connection terminal. The data transmission assembly also includes an optical signal propagation medium with a first end and a second end. The first end is attached to the first EO signal converter, and the second end is attached to the second EO signal converter. The signal propagation medium carries signals between the first connection terminal and the second connection terminal to support memory accesses performed by the processing unit to access data at memory locations within the RAM resource.09-11-2008
20130091324DATA PROCESSING APPARATUS AND VALIDITY VERIFICATION METHOD - A data processing apparatus includes an auxiliary storage device having target verification data stored therein, a program memory having a validity verification program stored therein, a first RAM (Random Access Memory), a second RAM, and an execution unit configured to execute a validity verification process in accordance with the validity verification program stored in the program memory. The execution unit is configured to copy the target verification data from the auxiliary storage device into the first RAM, execute the validity verification process on the copied target verification data in the first RAM, and use the second RAM as a work area in a case of executing the validity verification process.04-11-2013
20130132658Device For Executing Program Instructions and System For Caching Instructions - The system of the present invention includes an instruction fetch unit 05-23-2013
20130132659MICROCONTROLLER AND METHOD OF CONTROLLING MICROCONTROLLER - A microcontroller includes a RAM control unit configured to: perform a RAM access operation when an address designated by a CPU is within a range of a designated area; and read a program from a Flash EEPROM when the address is out of the range of the designated area. As the RAM access operation, the RAM control unit is configured to: read the program from the Flash EEPROM, store the read program into the RAM, and change valid bit information into a valid state, when the valid bit information indicates an invalid state; and output the program stored in the RAM to the CPU when the valid bit information indicates the valid state.05-23-2013
20110213922PHASE CHANGE RANDOM ACCESS MEMORY DEVICE AND RELATED METHODS OF OPERATION - A method of operating a phase change random access memory (PRAM) device includes performing a program operation to store data in selected PRAM cells of the device, wherein the program operation comprises a plurality of sequential program loops. The method further comprises suspending the program operation in the middle of the program operation, and after suspending the program operation, resuming the program operation in response to a resume command.09-01-2011
20130159614PAGE BUFFERING IN A VIRTUALIZED, MEMORY SHARING CONFIGURATION - An apparatus includes a processor and a volatile memory that is configured to be accessible in an active memory sharing configuration. The apparatus includes a machine-readable encoded with instructions executable by the processor. The instructions including first virtual machine instructions configured to access the volatile memory with a first virtual machine. The instructions including second virtual machine instructions configured to access the volatile memory with a second virtual machine. The instructions including virtual machine monitor instructions configured to page data out from a shared memory to a reserved memory section in the volatile memory responsive to the first virtual machine or the second virtual machine paging the data out from the shared memory or paging the data in to the shared memory. The shared memory is shared across the first virtual machine and the second virtual machine. The volatile memory includes the shared memory.06-20-2013
20130185491MEMORY CONTROLLER AND A METHOD THEREOF - A memory controller includes a mixed buffer and an arbiter. The mixed buffer includes at least one single-port buffer and at least one multi-port buffer for managing data flow between a host and a storage device. The arbiter determines an order of access to the mixed buffer among a plurality of masters. The data to be written or read are partitioned into at least two parts, which are then moved to the single-port buffer and the multi-port buffer, respectively.07-18-2013
20110314209DIGITAL SIGNAL PROCESSING ARCHITECTURE SUPPORTING EFFICIENT CODING OF MEMORY ACCESS INFORMATION - A digital signal processing architecture supporting efficient coding of memory access information is provided. In an example embodiment, a digital signal processor includes an adjustment value register to store an initial adjustment value and a succeeding adjustment value. The digital signal processor may also include an address generator circuit to retrieve an instruction including a memory address value that is greater than N, and a further instruction including a further memory address value that is less than or equal to N. In addition, the digital signal processor may include a memory, which includes a high bank address space defined by memory locations that are uniquely identified with memory address values greater than N. The address generator circuit may access the high bank address space, using initial adjustment value and the memory address value, or using the succeeding adjustment value and the further memory address value.12-22-2011

Patent applications in class Solid-state random access memory (RAM)

Patent applications in all subclasses Solid-state random access memory (RAM)