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Programmable read only memory (PROM, EEPROM, etc.)

Subclass of:

711 - Electrical computers and digital processing systems: memory

711100000 - STORAGE ACCESSING AND CONTROL

711101000 - Specific memory composition

711102000 - Solid-state read only memory (ROM)

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DocumentTitleDate
20110179219HYBRID STORAGE DEVICE - A hybrid storage device comprises both solid-state disk (SDD) and at least one hard disk drive (HDD). The hybrid storage device has at least two operational modes: concatenation and safe. According to one aspect, the total capacity of hybrid storage device is the sum of SSD and at least one HDD in a concatenation or big mode, while the total capacity is the capacity of the HDD in a safe mode. In one embodiment, HDD is configured for storing a copy of the SSD's contents in a reserved area. In another, SSD comprises more than one identical flash memory devices controlled by a RAID controller.07-21-2011
20090216935Memory device for a user profile - A memory device for a user profile of a plurality of electronic devices or functional units in a motor vehicle is used for providing data corresponding to the user profile in the vehicle without a user having to make corresponding settings. As a result of being stored in the memory device, the user profile can be used in different vehicles.08-27-2009
20110208904SEMICONDUCTOR DEVICE - The semiconductor device includes a nonvolatile memory, having a memory array containing 1-bit twin cells, each composed of electrically rewritable first and second storage devices, the first and second storage devices holding binary data according to difference of their threshold voltages, and having different retention characteristics depending on difference of the binary data thereof; a read circuit for differentially amplifying complementary data output from the first and second storage devices of the twin cell selected for read, and judging information stored in the twin cell; and a control circuit. Two memory cells constituting a twin cell are arranged to hold different data. Therefore, even when the retention performance of one memory cell deteriorates, the difference between data held by the two memory cells can be maintained. Hence, differential amplification of such difference enables acquisition of proper stored information. Thus, retention performance of an electrically rewritable nonvolatile memory cell is improved.08-25-2011
20090138654FATIGUE MANAGEMENT SYSTEM AND METHOD FOR HYBRID NONVOLATILE SOLID STATE MEMORY SYSTEM - A solid state memory system comprises a first nonvolatile semiconductor memory having a first write cycle lifetime and a first set of physical addresses, and a second nonvolatile semiconductor memory having a second write cycle lifetime and a second set of physical addresses. The first write cycle lifetime is greater than the second write cycle lifetime. The system further comprises a fatigue management module to generate a write frequency ranking for a plurality of logical addresses. The fatigue management module maps each of the plurality of logical addresses to a physical address of the first set of physical addresses or the second set of physical addresses based on the write frequency rankings.05-28-2009
20120173797METHOD FOR PERFORMING BLOCK MANAGEMENT/FLASH MEMORY MANAGEMENT, AND ASSOCIATED MEMORY DEVICE AND CONTROLLER THEREOF - A method for performing block management is provided. The method is applied to a controller of a Flash memory having multiple channels. The Flash memory includes a plurality of blocks respectively corresponding to the channels. The method includes: selecting at least one meta block having at least one valid page as at least one candidate meta block for being cleaned, and accumulating respective valid page counts of blocks respectively corresponding to the channels within the at least one candidate meta block, in order to generate a plurality of accumulated values respectively corresponding to the channels; and when it is detected that all of the accumulated values reach a threshold value, triggering a cleaning operation with regard to all candidate meta blocks, in order to simultaneously move/copy valid data respectively corresponding to the channels during the cleaning operation. An associated memory device and a controller thereof are also provided.07-05-2012
20130185490SEMICONDUCTOR MEMORY SYSTEM HAVING A SNAPSHOT FUNCTION - In a semiconductor memory computer equipped with a flash memory, use of backed-up data is enabled. The semiconductor memory computer includes an address conversion table for detecting physical addresses of at least two pages storing data by designating a logical address from one of logical addresses to be designated by a reading request. The semiconductor memory computer includes a page status register for detecting one page status allocated to each page, and page statuses to be detected include the at least following four statuses: (1) a latest data storage status, (2) a not latest data storage status, (3) an invalid data storage status, and (4) an unwritten status. By using the address conversion table and the page status register, at least two data s (latest data and past data) can be read for one designated logical address from a host computer.07-18-2013
20100088465CONTROL DEVICE OF A STORAGE SYSTEM COMPRISING STORAGE DEVICES OF A PLURALITY OF TYPES - A control device of a storage system including a CPU which receives input information including at least a size and an archive deadline of data which is stored in storage devices; wherein data management information includes a write threshold value regarding one type of storage devices, the write threshold value indicating a write limit number to the one type of storage devices, wherein the CPU: selects a storage device which stores data corresponding to the information which is input to an input device, based on the information which is input to the input device and the data management information which is stored in the memory; CPU stores to the selected storage device, the data corresponding to the information which is input to the input device; and, registers to the data management information in the memory, at least one of the information which is input to the input device.04-08-2010
20100088458OPERATION METHOD OF MEMORY - An operation method of a memory includes the steps of calculating an offset of sequential write commands and the beginning of pages of a block of a non-volatile memory; shifting the block by the offset; and directly writing data from a host to the pages except the first and last pages of the block by the sequential write commands. In an embodiment, the pages are logical pages providing optimal writing efficiency and are determined before calculating the offset. The step of shifting the block by the offset is to increase corresponding logical block addresses (LBA) in the pages by the offset.04-08-2010
20090125669PREVENTING DATA LOSS IN A STORAGE SYSTEM - Storage servers use a fast, non-volatile or persistent memory to store data until it can be written to slower mass storage devices such as disk drives. If the server crashes before a write can complete, the data remains safely stored in non-volatile memory. If the data cannot be committed to disk when the server reboots (e.g. because the destination mass storage device is unavailable), it is stored in a file. When the disk reappears, the data in the file may be used to restore a file or file system on the disk to a consistent state.05-14-2009
20100023682Flash-Memory System with Enhanced Smart-Storage Switch and Packed Meta-Data Cache for Mitigating Write Amplification by Delaying and Merging Writes until a Host Read - A flash memory solid-state-drive (SSD) has a smart storage switch that reduces write acceleration that occurs when more data is written to flash memory than is received from the host. Page mapping rather than block mapping reduces write acceleration. Host commands are loaded into a Logical-Block-Address (LBA) range FIFO. Entries are sub-divided and portions invalidated when a new command overlaps an older command in the FIFO. Host data is aligned to page boundaries with pre- and post-fetched data filling in to the boundaries. Repeated data patterns are detected and encoded by compressed meta-data codes that are stored in meta-pattern entries in a meta-pattern cache of a meta-pattern flash block. The sector data is not written to flash. The meta-pattern entries are located using a meta-data mapping table. Storing host CRC's for comparison to incoming host data can detect identical data writes that can be skipped, avoiding a write to flash.01-28-2010
20090164701PORTABLE IMAGE INDEXING DEVICE - A portable image-indexing device that includes a port adapter for connecting to a personal computer and a port adapter for receiving a camera card. The device includes memory for storing a plurality of image and video files and for storing image indexing application programs. A processor performs image indexing on images and/or videos and includes a power source.06-25-2009
20090164708MEMORY CHIP WITH EXTENDED INPUT/OUTPUT INTERFACE - A memory chip (06-25-2009
20110191522Managing Metadata and Page Replacement in a Persistent Cache in Flash Memory - A persistent cache is implemented in a flash memory that includes a journal section that stores metadata and a low frequency section and a high frequency section that store data entries. Writing new metadata to the persistent cache includes sequentially advancing to a next sector containing an invalid metadata entry, saving a working copy of the sector in RAM, writing metadata corresponding to one or more new data entries in the working copy, and overwriting the sector in the flash memory containing the invalid entry with the working copy. Writes to the low frequency and high frequency sections occur sequentially in the current locations of a low frequency section pointer and a high frequency section pointer, respectively. In a persistent cache, the reconstruction of a non-persistent cache utilizes the metadata entry that has the most recent timestamp.08-04-2011
20110191521FLASH MEMORY DEVICE - A controller in a flash memory device manages erase count of each physical block and manages the erase frequency of each logical block. The controller allocates a logical block whose erase frequency is high to one or more physical blocks whose erase count is low.08-04-2011
20090083474FILE ALLOCATION TABLE MANAGEMENT - In one embodiment, a storage controller comprises a first port that provides an interface to a host computer, a second port that provides an interface a storage device, a processor, and a flash memory module communicatively connected to the processor and comprising logic instructions which, when executed by the processor, configure the processor to receive, in a file allocation table manager, a signal indicative of a request to perform a first update of a file allocation table stored in a memory module, locate, in the memory module, a first memory sector corresponding to a first entry in the file allocation table having an active status, write, in the memory module, a second file allocation table entry, set a status flag associated with the second entry to an active state, and set a status flag associated with the first entry to a standby state.03-26-2009
20090193182INFORMATION STORAGE DEVICE AND CONTROL METHOD THEREOF - According to one embodiment, an information storage device includes a non-volatile storage medium, a non-volatile memory configured to store specific data blocks to be read for a host device and write data to be written to the non-volatile storage medium, a buffer configured to temporarily store write data transmitted from the host device, and a controller. The controller is configured to delete synchronized data the same data block as which exists on the non-volatile storage medium among the specific data blocks stored in the non-volatile memory if the free space of the non-volatile memory is smaller than a given data size, and to write the write data stored in the buffer to the non-volatile memory.07-30-2009
20090193181Control Unit, Image Processing Apparatus and Computer-Readable Storage Medium - A memory information storage control method is executed by a control unit which carries out a memory information storage process to generate memory information related to a program being executed by the control unit and to store the memory information. The memory information storage control method includes an interface process to register a storage location of the memory information generated by the memory information storage process, a registering process to register a portable storage device as the storage location of the memory information using the interface process, and an executing process to confirm coupling of the portable storage device to the control unit and to register the storage location of the memory information in the detachably coupled portable storage device by the registering process.07-30-2009
20090193180SEMICONDUCTOR MEMORY DEVICE AND CONTROL METHOD FOR SEMICONDUCTOR MEMORY DEVICE - A memory card capable of connecting to a host device includes a flash memory, a host interface unit which transfers data between a host device and the memory card, and a transfer mode control unit which changes a data transfer mode based on a command from the host device. The transfer mode control unit outputs status data containing an error code to the host device if a transfer mode change command is inputted from the host device, instructing the memory card to change to a transfer mode not supported by the host interface unit of the memory card.07-30-2009
20090193177Virtual Processor Based Security For On-Chip Memory, and Applications Thereof - A processor-based method, system and apparatus to comprise a method, system and apparatus to access a memory location in an on-chip memory based on a virtual processing element identification associated with an instruction. The system comprises multiple virtual processing elements, an access list and a comparator coupled to the memory and the access list. In response to an instruction from a virtual processing element to access a memory location in the memory, the comparator compares a first virtual processing identification associated with the instruction to a second virtual processing identification stored in the access list and grants access to the virtual processing element to read from or write to the memory location if the first virtual processing element identification is equal to the second virtual processing element identification. The data in the memory is allocated and de-allocated by software. In one embodiment, the access list is instantiated in hardware and cannot be read from or written to by software. A virtual processing element comprises multiple hardware thread contexts with each thread context being associated with a distinct register file.07-30-2009
20090193176Data storage device having a built-in display - A data storage device for an electronic device includes a hard disk for storing a plurality of pieces of data, a nonvolatile memory for storing a plurality of file names corresponding to the pieces of data, a display, and a controller connected electrically to the hard disk, the nonvolatile memory and the display unit, and operable so as to permit viewing of the file names stored in the nonvolatile memory by displaying a viewing result including a viewed one of the file names on the display.07-30-2009
20130031300NON-VOLATILE MEMORY DEVICE, METHOD OF OPERATING THE SAME, AND MEMORY SYSTEM HAVING THE NON-VOLATILE MEMORY DEVICE - According to an aspect of the inventive concepts, there is provided a non-volatile memory device including a memory array with at least one stripe. The at least one stripe includes at least one parity page and at least one data page. The non-volatile memory device further includes a chip controller. The chip controller includes an operation module configured to perform an operation on data input from the outside of the memory device, to store a result of the performing, and to program the result of the performing into the at least one parity page. The chip controller further includes a data buffer configured to store the input data and to program the input data into the at least one data page.01-31-2013
20130031303STACKED MEMORY DEVICES, SYSTEMS, AND METHODS - Memory requests for information from a processor are received in an interface device, and the interface device is coupled to a stack including two or more memory devices. The interface device is operated to select a memory device from a number of memory devices including the stack, and to retrieve some or all of the information from the selected memory device for the processor. Additional apparatus, systems and methods are disclosed.01-31-2013
20130031302SYSTEMS AND METHODS FOR DETERMINING THE STATUS OF MEMORY LOCATIONS IN A NON-VOLATILE MEMORY - Systems and methods are provided for storing data in a portion of a non-volatile memory (“NVM”) such that the status of the NVM portion can be determined with high probability on a subsequent read. An NVM interface, which may receive write commands to store user data in the NVM, can store a fixed predetermined sequence (“FPS”) with the user data. The FPS may ensure that a successful read operation on a NVM portion is not misinterpreted as a failed read operation or as an erased NVM portion. For example, if the NVM returns an all-zero vector when a read request fails, the FPS can include at least one “1” or one “0”, as appropriate, to differentiate between successful and unsuccessful read operations. In some embodiments, the FPS may also be used to differentiate between disturbed data, which passes an error correction check, and correct data.01-31-2013
20130031298INCLUDING PERFORMANCE-RELATED HINTS IN REQUESTS TO COMPOSITE MEMORY - A composite memory device that includes different types of non-volatile memory devices, which have different performance characteristics, is described. This composite memory device may receive requests, a given one of which includes a command, a logical address for at least a block of data associated with the command, and a hint associated with the command. For the given request, the composite memory device executes the command on the block of data at the logical address in at least one of the types of non-volatile memory devices. Furthermore, the composite memory device conditionally executes the hint based on one or more criteria, such as: available memory in the types of non-volatile memory devices, traffic through an interface circuit in the composite memory device, operational states of the types of non-volatile memory devices, a target performance characteristic of the composite memory device, and an environmental condition of the composite memory device.01-31-2013
20130031297ADAPTIVE RECORD CACHING FOR SOLID STATE DISKS - A storage controller receives a request that corresponds to an access of a track. A determination is made as to whether the track corresponds to data stored in a solid state disk. Record staging to a cache from the solid state disk is performed, in response to determining that the track corresponds to data stored in the solid state disk, wherein each track is comprised of a plurality of records.01-31-2013
20130086311METHOD OF DIRECT CONNECTING AHCI OR NVMe BASED SSD SYSTEM TO COMPUTER SYSTEM MEMORY BUS - A SSD system directly connected to the system memory bus includes at least one system memory bus interface unit, one storage controller with associated data buffer/cache, one data interconnect unit, one nonvolatile memory (NVM) module, and flexible association between storage commands and the NVM module. A logical device interface, the Advanced Host Controller Interface (AHCI) or NVM Express (NVMe), is used for the SSD system programming. The SSD system appears to the computer system physically as a dual-inline-memory module (DIMM) attached to the system memory controller, and logically as an AHCI device or an NVMe device. The SSD system may sit in a DIMM socket and scaling with the number of DIMM sockets available to the SSD applications. The invention moves the SSD system from I/O domain to the system memory domain.04-04-2013
20110202709OPTIMIZING STORAGE OF COMMON PATTERNS IN FLASH MEMORY - One embodiment of the present invention provides a method of operation within a flash memory system. During operation, the system receives write data and a corresponding logical address. The system then determines whether the write data matches a predetermined data pattern. If the write data does match the predetermined data pattern, instead of writing the data, the system records an indication that the predetermined data pattern corresponds to the logical address.08-18-2011
20110202712STORAGE DEVICE INCLUDING FLASH MEMORY AND CAPABLE OF PREDICTING STORAGE DEVICE PERFORMANCE - A storage device includes a semiconductor memory storing data. A controller instructs to write data to the semiconductor memory in accordance with a request the controller receives. A register holds performance class information showing one performance class required to allow the storage device to demonstrate best performance which the storage device supports, of performance classes specified in accordance with performance.08-18-2011
20110202711ADAPTIVE READ AND WRITE SYSTEMS AND METHODS FOR MEMORY CELLS - An apparatus including: a plurality of multi-level memory cells configured to store data, wherein one or more of the multi-level memory cells are designated as pilot memory cells, and wherein each pilot memory cell is configured to store known, pre-determined data; an estimation block configured to, based on the known, pre-determined data, determine (i) estimated mean values of level distributions of the multi-level memory cells and (ii) estimated standard deviation values of level distributions of the multi-level memory cells; and a computation block configured to compute at least optimal or near optimal detection threshold values of level distributions of the multi-level memory cells based, at least in part, on (i) the estimated mean values and (ii) the estimated standard deviation values, wherein the optimal or near optimal detection threshold values are to be used in order to facilitate reading of the data stored in the multi-level memory cells.08-18-2011
20110202710PROTECTION AGAINST DATA CORRUPTION FOR MULTI-LEVEL MEMORY CELL (MLC) FLASH MEMORY - Apparatus having corresponding methods and non-transitory computer-readable media comprise a flash controller configured to control a multi-level memory cell (MLC) flash memory, wherein the MLC flash memory includes a plurality of memory blocks, wherein each memory block includes a plurality of memory cells defining a plurality of pages, wherein each memory cell spans a group of the pages in one of the memory blocks, and wherein the flash controller comprises circuitry configured to receive data to be written to the MLC flash memory, select only one page, from each group of the pages, in one or to more of the memory blocks, and write the data only to the selected pages.08-18-2011
20110202708Integrating A Flash Cache Into Large Storage Systems - An I/O enclosure module is provided with one or more I/O enclosures having a plurality of slots for receiving electronic devices. A host adapter is connected a first slot of the I/O enclosure module and is configured to connect a host to the I/O enclosure. A device adapter is connected to a second slot of the I/O enclosure module and is configured to connect a storage device to the I/O enclosure module. A flash cache is connected to a third slot of the I/O enclosure module and includes a flash-based memory configured to cache data associated with data requests handled through the I/O enclosure module. A primary processor complex manages data requests handled through the I/O enclosure module by communicating with the host adapter, device adapter, and flash cache to manage to the data requests.08-18-2011
20110202707NVMHCI ATTACHED HYBRID DATA STORAGE - A hybrid data storage device includes a solid-state memory device, a disc-type memory device and a hybrid data storage device controller in communication with the solid-state memory device and the disc-type memory device. The hybrid data storage device controller is configured to receive Non-Volatile Memory Host Controller Interface (NVMHCI) commands from a host and use logic to make decisions for the optimization and efficient performance of the solid-state memory device and the disc-type memory device.08-18-2011
20130086310NON-TRANSITORY STORAGE MEDIUM ENCODED WITH COMPUTER READABLE PROGRAM, INFORMATION PROCESSING SYSTEM, INFORMATION PROCESSING APPARATUS, AND INFORMATION PROCESSING METHOD - An exemplary embodiment provides a non-transitory storage medium encoded with a computer readable program executable by the computer, for writing data in a semiconductor storage device capable of storing a plurality of bits in one memory cell. The program causes the computer to perform an allocation step of allocating a first area for storing first data in a storage area of a semiconductor storage device and a writing step of writing the first data only in an area of use, with a prescribed size from a boundary of the first area being defined as a protection area and a remaining area being defined as the area of use in response to a request for writing the first data.04-04-2013
20130086303APPARATUS, SYSTEM, AND METHOD FOR A PERSISTENT OBJECT STORE - An apparatus, system, and method are disclosed for persistently storing data objects. An object store index module maintains an object store. The object store associates each data object of a plurality of data objects with a unique key value. A storage module persists object store data defining the object store to a logical block address of the solid-state storage device in response to an update event. The logical block address is a member of a restricted set of logical block addresses. The logical block address is mapped to a location of the object store data on the solid-state storage device. A read module provides a requested data object from the plurality of data objects to a requesting client in response to receiving a read request for the requested data object from the requesting client. The read request comprises the key value associated with the requested data object.04-04-2013
20130086305NONVOLATILE SEMICONDUCTOR STORAGE SYSTEM - A nonvolatile semiconductor storage system has multiple nonvolatile semiconductor storage media, a control circuit having a media interface group (one or more interface devices) coupled to the multiple nonvolatile semiconductor storage media, and multiple switches. The media interface group and the multiple switches are coupled via data buses, and each switch and each of two or more nonvolatile chips are coupled via a data bus. The switch is configured so as to switch a coupling between a data bus coupled to the media interface group and a data bus coupled to any of multiple nonvolatile chips that are coupled to this switch. The control circuit partitions write-target data into multiple data elements, switches a coupling by controlling the multiple switches, and distributively sends the multiple data elements to multiple nonvolatile chips.04-04-2013
20130086304STORAGE SYSTEM COMPRISING NONVOLATILE SEMICONDUCTOR STORAGE MEDIA - Logical-physical translation information comprises information denoting the corresponding relationships between multiple logical pages and multiple logical chunks forming a logical address space of a nonvolatile semiconductor storage medium, and information denoting the corresponding relationships between the multiple logical chunks and multiple physical storage areas. Each logical page is a logical storage area conforming to a logical address range. Each logical chunk is allocated to two or more logical pages of multiple logical pages. Two or more physical storage areas of multiple physical storage areas are allocated to each logical chunk. A controller adjusts the number of physical storage areas to be allocated to each logical chunk.04-04-2013
20130086302Enabling Throttling on Average Write Throughput for Solid State Storage Devices - A mechanism is provided for enabling throttling on average write throughput instead of peak write throughput for solid-state storage devices. The mechanism assures an average write throughput within a range but allows excursions of high throughput with periods of low throughput offsetting against those of heavy usage. The mechanism periodically determines average throughput and determines whether average throughput exceeds a high throughput threshold for a certain amount of time without being offset by periods of low throughput.04-04-2013
20120179862System For Accessing Non-Volatile Memory - Accessing a non-volatile memory array is described, including receiving a first data and a memory address associated with the first data, writing the first data to the non-volatile memory array at the memory address of the first data without erasing a second data stored in the non-volatile memory array at the memory address of the first data before writing the first data.07-12-2012
20090172251Memory Sanitization - Apparatus and method for memory sanitization is disclosed, including a memory, the memory including—in whole or in part—multiple layers of memory, and control logic configured to perform a sanitize operation on a portion of the memory. In one example, a third dimensional memory array can constitute at least a portion of the multiple layers of memory. The multiple layers of memory may include non-volatile two-terminal cross-point memory arrays. Each non-volatile two-terminal cross-point memory array can include a plurality of two-terminal memory elements that store data as a plurality of conductivity profiles that can be non-destructively determined by applying a read voltage across the terminals of the two-terminal memory element. The two-terminal memory elements retain stored data in the absence of power. The non-volatile two-terminal cross-point memory arrays can be vertically stacked upon one another and may be positioned on top of a logic plane that includes active circuitry.07-02-2009
20120246399Storage Device and Memory Controller - Disclosed is a storage device using non-volatile semiconductor memory that achieves high performance and long life for the device. When managing the non-volatile semiconductor memory (09-27-2012
20120246397STORAGE DEVICE MANAGEMENT DEVICE AND METHOD FOR MANAGING STORAGE DEVICE - According to one embodiment, a storage device management device is connected to a random access memory and a first storage device. When the random access memory includes a free region sufficient to store write data, the write data is stored onto the random access memory. Data on the random access memory selected in the descending order of elapsed time from the last access is sequentially copied onto the first storage device, and a region in the random access memory which has stored the copied data is released. When stored on the random access memory, the read data is read from the random access memory to the processor. When stored on the first storage device, the read data is copied onto the random access memory and read from the random access memory to the processor.09-27-2012
20120246396NON-VOLATILE MEMORY DEVICE HAVING ASSIGNABLE NETWORK IDENTIFICATION - Memory devices and methods disclosed such as a memory device having a plurality of memory dies where each die includes a network identification that uniquely identifies the memory die on a bus. Access for each memory die to the bus can be scheduled by a bus controller.09-27-2012
20120246394Flash Memory Device and Data Writing Method for a Flash Memory - A data writing method for a flash memory. First, a plurality of blocks of a flash memory is classified into a plurality of block groups according to the erase counts of the blocks. A logical address range of a host is then divided into a plurality of logical address sections respectively corresponding to the block groups. Write data is then received from the host. A target logical address section to which the logical address of the write data belongs is then determined. A target block group corresponding to the target logical address section is then determined. A target block is then selected from the blocks of the target block group. The write data is then written to the target block.09-27-2012
20120246393MEMORY SYSTEM AND CONTROL METHOD OF THE MEMORY SYSTEM - A memory system of a embodiments includes a first storing area having physical blocks and a second storing area recording a logical to physical translation table and an erasure count table keeping data erasure count in physical blocks. The memory system of the embodiments includes a controller which, when a logical address for deletion is notified, obtains data erasure count of a deletion physical block including a deletion area specified by the physical address corresponding to the logical address, and when a physical block having a small erasure count not more than a predetermined rate of the data erasure count exists in the erasure count table, reads out valid data for the memory system in the physical block having a small erasure count onto the second storing area, writes the above data into the deletion area, and invalidates the valid data in the physical block having a small erasure count.09-27-2012
20120246392STORAGE DEVICE WITH BUFFER MEMORY INCLUDING NON-VOLATILE RAM AND VOLATILE RAM - A storage device includes a flash memory, a buffer memory and a memory controller. The buffer memory is configured to temporarily store write data to be written in the flash memory, the buffer memory including volatile RAM and non-volatile RAM. The memory controller is configured to select one of the volatile RAM and the non-volatile RAM to temporally store the write data based on a write pattern of the write data, and to transmit a host command complete signal to a host when the write data is stored in the non-volatile RAM.09-27-2012
20120246390INFORMATION PROCESSING APPARATUS, PROGRAM PRODUCT, AND DATA WRITING METHOD - According to one embodiment, an information processing apparatus includes an auxiliary storage unit, a non-volatile main storage unit, a secondary cell, a first writing unit, and a second writing unit. The non-volatile main storage unit includes a cache area to temporarily store therein data that is to be stored in the auxiliary storage unit. The first writing unit writes the data into the cache area. The second writing unit writes the data written in the cache area into the auxiliary storage unit when an amount of power in the secondary cell is greater than a predetermined first threshold.09-27-2012
20120246389NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM - According to one embodiment, a nonvolatile semiconductor memory device includes a nonvolatile memory, and a controller having a first mode to perform data transfer in response to one of a rising edge and falling edge of a first control signal and a second mode to perform data transfer in response to both of a rising edge and falling edge of a second control signal. The controller switches the first and second modes in data input and data output.09-27-2012
20120246388MEMORY SYSTEM, NONVOLATILE STORAGE DEVICE, CONTROL METHOD, AND MEDIUM - According to one embodiment, a memory system includes a nonvolatile storage device and an information processing apparatus. The information processing apparatus includes a first control circuit configured to send a delete notification to the nonvolatile storage device to invalidate data in a first logical address area when read data corresponding to the first logical address area is the same as data expressed by a first function. The nonvolatile storage device include a nonvolatile storage medium, a management table configured to associate a logical address corresponding to valid data for the nonvolatile storage device with a physical address, and a second control circuit configured to update the management table to invalidate a logical address designated by the delete notification, and to send the data expressed by the first function to the information processing apparatus when a logical address included in a read instruction received from the information processing apparatus is invalid.09-27-2012
20120246385EMULATING SPI OR 12C PROM/EPROM/EEPROM USING FLASH MEMORY OF MICROCONTROLLER - In one aspect, a microcontroller is disclosed. In one embodiment, the microcontroller includes a system memory that has an erasable memory of a first type, with a first storage partition and a second, different storage partition. The system memory also has a random access memory (RAM). The microcontroller further includes a network interface that is configured to communicate management commands over a communications link, and a programmable processor that is operatively connected to the system memory and the network interface. The communications link includes an interface bus and is configured for one or more of I2C, SPI, and system management bus communications. The programmable processor is programmed to perform functions that include receiving a first management command configured for the erasable memory of the first type, causing the second storage partition of the erasable memory of the first type to emulate a second type of erasable memory, and receiving a second management command configured for the second type of erasable memory.09-27-2012
20100077137METHOD FOR CATALOGING AND STORING DATA IN A CONTROL SYSTEM - A method includes receiving a data input file, the data input file defining a first set of data fields to be included in a database and including a set of data elements to be included in the database. The method also includes identifying a second set of data fields in the data input file that are designated to contain a Boolean element, said second set of data fields being a subset of the first set of data fields. The method further includes defining at least one new data field, each new data field collectively storing a plurality of the Boolean elements. The first set of data fields are modified to eliminate the second set of data fields. The method also includes storing in a catalog data that defines an arrangement of the first set of data fields, wherein the arrangement includes the at least one new data field for collectively storing the Boolean elements.03-25-2010
20100077136Memory System Supporting Nonvolatile Physical Memory - A memory system includes nonvolatile physical memory, such as flash memory, that exhibits a wear mechanism asymmetrically associated with write operations. A relatively small cache of volatile memory reduces the number of writes, and wear-leveling memory access methods distribute writes evenly over the nonvolatile memory.03-25-2010
20100077135MEMORY WEAR LEVELING METHOD, SYSTEM AND DEVICE - A wear leveling method for a non-volatile memory is provided. The non-volatile memory includes a plurality of data blocks, each corresponding to a time value. The data blocks are arranged according to a sequence of the time values corresponding thereto. The arranged blocks form a key table. An erase operation is determined whether to be executed for the data blocks. When the erase operation is executed for the data blocks, the corresponding data block is erased according to a sequence of the time values of the data blocks in the key table.03-25-2010
20100077134FLASH DEVICE AND METHOD FOR IMPROVING PERFORMANCE OF FLASH DEVICE - The invention provides a flash device. In one embodiment, the flash device comprises a first NAND flash integrated circuit, a second NAND flash integrated circuit, and a control integrated circuit. The control integrated circuit generates a plurality of first access signals with first timings to access the first NAND flash IC, and generates a plurality of second access signals with second timings to access the second NAND flash IC, wherein the first timings are different from the second timings. The first NAND flash integrated circuit then accesses data stored therein according to the first access signals. The second NAND flash integrated circuit then accesses data stored therein according to the second access signals.03-25-2010
20100077133Flash Memory Integrated Circuit with Compression/Decompression CODEC - Provided is a flash memory integrated circuit with a compression codec. The flash memory integrated circuit may simultaneously include a memory block and a compression codec circuit. The compression codec circuit may compress input data. A controller circuit may store the compressed input data in at least one page that is included in the memory block. Through this, it is possible to enhance a usage efficiency of a flash memory.03-25-2010
20100077132MEMORY DEVICES AND ACCESS METHODS THEREOF - Methods and devices capable of erasing a flash memory evenly are provided, in which a flash memory comprises a data region with a plurality of data blocks and a spare region with a plurality of spare blocks, and a controller retrieves a corresponding data with a check code from a first data block of the flash memory according to a read command from a host, performs a predetermined check to the corresponding data by the check code, determines whether an error is correctable when a check result of the predetermined check represents that the error has occurred, and increases an erase count of the first data block by a predetermined value when the error is correctable.03-25-2010
20100077131UPDATING CONTROL INFORMATION IN NON-VOLATILE MEMORY TO CONTROL SELECTION OF CONTENT - To control selection of content in a non-volatile memory, control information is stored in the non-volatile memory, where the control information is to control selection of content in the non-volatile memory. An algorithm is used to update the control information in the non-volatile memory to cause different content in the non-volatile memory to be selected, wherein the algorithm sets the control information to an initial value that enhances use of programming of the non-volatile memory to update the control information, and reduces use of erasing of the non-volatile memory to update control information.03-25-2010
20100115186FLASH MEMORY DEVICE WITH WEAR-LEVELING MECHANISM AND CONTROLLING METHOD THEREOF - A flash memory device with a wear-levelining mechanism includes at least one flash memory, a hot list, a bitmap, a source pointer, and a controller. The controller obtains a physical memory block with high erase count through the hot list, an erase count of the physical memory block, and an overall average erase count of the flash memory device. The controller further finds out a physical memory block which stores static data through managing the bitmap and the source pointer. The controller moves the static data to the physical memory block with high erase count, and releases the physical memory block which stores the static data to avoid the physical memory block with high erase count being worn down increasingly more seriously.05-06-2010
20100115184FLASH MEMORY STORAGE SYSTEM AND CONTROLLER AND DATA PROTECTION METHOD THEREOF - A flash memory storage system including a controller and a flash memory chip is provided, wherein the controller is disposed with a rewritable non-volatile memory. When the controller writes a security data into the flash memory chip, the controller randomly generates a data token and generates a message digest according to the security data and the data token by using a one-way hash function, wherein the data token and the message digest are respectively stored in the rewritable non-volatile memory and the flash memory chip. Subsequently, when the controller reads the security data from the flash memory chip, the controller determinates whether the security data is falsified according to the data token and the message digest respectively stored in the rewritable non-volatile memory and the flash memory chip. Thereby, the security data in the flash memory chip can be effectively protected.05-06-2010
20100115183Storage Apparatus and Method of Managing Data Storage Area - Disclosed is a storage apparatus that extends endurance and reduces bit cost. A storage apparatus includes a controller and a semiconductor storage media that has a plurality of storage devices. The plurality of storage devices include a first storage device and a second storage device having an upper limit of an erase count of data smaller than that of the first storage device. Area conversion information includes correspondence of a first address to be specified as a data storage destination and a second address of an area in which data is to be stored. A rewrite frequency of stored data is recorded for each area. The controller selects an area corresponding to the first address, determines whether or not the rewrite frequency of the selected area is equal to or larger than a first threshold value, when the rewrite frequency is equal to or larger than the threshold value, selects an area to be provided by the first storage device, and when the rewrite frequency is smaller than the threshold value, selects an area to be provided by the second storage device and maps the address of the selected area to the first address.05-06-2010
20100115175Method of managing a large array of non-volatile memories - The present invention provides a non-volatile flash memory management system and method that provides the ability to efficiently manage a large array of flash devices and allocate flash memory use in a way that improves reliability and longevity, while maintaining excellent performance. The invention mainly comprises of a processor, an array of flash memories that are modularly organized, an array of module flash controllers and DRAM caching. The processor manages the above mention large array of flash devices with caching memory through mainly two tables: Virtual Zone Table and Physical Zone Table, a number of queues: Cache Line Queue, Evict Queue, Erase Queue, Free Block Queue, and a number of lists: Spare Block List and Bad Block List.05-06-2010
20130086301Direct Memory Address for Solid-State Drives - A storage device is provided for direct memory access. A controller of the storage device performs a mapping of a window of memory addresses to a logical block addressing (LBA) range of the storage device. Responsive to receiving from a host a write request specifying a write address within the window of memory addresses, the controller initializes a first memory butler in the storage device and associates the first memory buffer with a first address range within the window of memory addresses such that the write address of the request is within the first address range. The controller writes to the first memory buffer based on the write address. Responsive to the buffer being full, the controller persists contents of the first memory buffer to the storage device using logical block addressing based on the mapping.04-04-2013
20130086307INFORMATION PROCESSING APPARATUS, HYBRID STORAGE APPARATUS, AND CACHE METHOD - According to one embodiment, an information processing apparatus includes a determination module and a cache module. The determination module is configured to determine whether an access request from a host to the hard disk drive is a request for accessing a preset number of or more consecutive sectors in a hard disk drive. The cache module is configured to use a storage apparatus as a cache for the hard disk drive, and the cache module is configured not to use the storage apparatus as the cache when it is determined that the access request is the request for accessing the preset number of or more consecutive sectors.04-04-2013
20130086306INFORMATION PROCESSOR AND MEMORY MANAGEMENT METHOD - According to one embodiment, an information processor includes: a controller, a volatile storage module, a non-volatile storage module, and a reader. The volatile storage module is configured to be allocated with a storage area which can be accessed by the controller. The non-volatile storage module is configured to save data stored in the storage area of the volatile storage module at transition to a power-off state. The reader is configured to read, if a state just prior to the transition to the power-off state is to be recovered, the data stored in the non-volatile storage module by each page, and to load the read data to the storage area in the volatile storage module. The page is configured by a plurality of memory cells.04-04-2013
20130031301BACKEND ORGANIZATION OF STORED DATA - A data units received from a host system are divided and/or redistributed among a plurality of data payloads, wherein boundaries of the data units are not aligned with boundaries of the data payloads. The plurality of data payloads are encoded into a respective plurality of codewords, and the plurality of codewords stored in the flash memory. Boundaries of the codewords are aligned with boundaries of the pages in the flash memory.01-31-2013
20130086312Semiconductor Device - An object of the present invention is to realize a highly reliable long-life information processor capable of high-speed operation and easy to handle. The processor includes a semiconductor device comprising a nonvolatile memory device including a plurality of overwritable memory cells, and a control circuit device for controlling access to the nonvolatile memory device. The control circuit device sets assignments of second addresses to the nonvolatile memory device independently of first addresses externally supplied, such that the physical disposition of part of the memory cells used for writing of first data to be written externally supplied is one of the first to (N+1)th of every (N+1) memory cells (N: a natural number) at least in one direction.04-04-2013
20130086313METHODS TO SECURELY BIND AN ENCRYPTION KEY TO A STORAGE DEVICE - Embodiments of methods to securely bind a disk cache encryption key to a cache device are generally described herein. Other embodiments may be described and claimed.04-04-2013
20130086314STORAGE SYSTEM, STORAGE DEVICE, AND CONTROL METHOD THEREOF - A storage system including a storage device which includes media for storing data from a host computer, a medium controller for controlling the media, a plurality of channel controllers for connecting to the host computer through a channel and a cache memory for temporarily storing data from the host computer, wherein the media have a restriction on a number of writing times. The storage device includes a bus for directly transferring data from the medium controller to the channel controller.04-04-2013
20130080690METHOD TO EMULATE EEPROM USING FLASH MEMORY - Methods of using FLASH memory to emulate EEROM are disclosed. The present method uses two pages of FLASH memory, where each page is one or more separately erasable blocks. One page is referred to as the current page, while the other is the next page. Tokens, which are data structures containing a data element, are written in successive locations in the current page. When the current page is nearly completely filled, the write operation starts writing the new tokens to the next page. In some embodiments, to equalize the execution time of the write routine, the write routine also copies one token from the current page to the next page after a new token is written to the next page. Once all tokens have been copied to the next page, the current page can be erased. At this point, the next page becomes the current page.03-28-2013
20130080687SOLID STATE DISK EMPLOYING FLASH AND MAGNETIC RANDOM ACCESS MEMORY (MRAM) - A central processing unit (CPU) subsystem is disclosed to include a MRAM used among other things for storing tables used for flash block management. In one embodiment all flash management tables are in MRAM and in an alternate embodiment tables are maintained in DRAM and are near periodically saved in flash and the parts of the tables that are updated since last save are additionally maintained in MRAM.03-28-2013
20130080689DATA STORAGE DEVICE AND RELATED DATA MANAGEMENT METHOD - A storage device performs data management for a nonvolatile memory device by detecting an allocation order of a first memory block, assigning page data of the first memory block to a second memory block or a third memory block having different erase counts based on the allocation order.03-28-2013
20130080686DATA MANAGEMENT METHOD FOR NONVOLATILE MEMORY - A method of managing data in a system comprising a nonvolatile memory comprises storing a root object of application data, and at least one sub object referenced by the root object in the nonvolatile memory, and mapping virtual addresses of the root object and sub object to physical addresses of the nonvolatile memory respectively, in a page unit. The root object stored in the nonvolatile memory comprises a pointer that references the sub object stored in the nonvolatile memory.03-28-2013
20130080688DATA STORAGE DEVICE AND METHOD OF WRITING DATA IN THE SAME - A method is provided for writing data in a storage device, including a nonvolatile memory. The method includes receiving a pre-write command including a logical address and size information of write data, performing a pre-operation for optimization of a write operation based on the pre-write command, and writing the write data in the nonvolatile memory after the pre-operation is completed.03-28-2013
20130080685STORAGE DEVICES AND METHODS OF DRIVING STORAGE DEVICES - A storage device includes a data storage having first and second storage areas corresponding to different physical addresses. First data are stored in the first storage area. The storage device further includes a first memory that stores a reference count associated with the first data, and a controller that rearranges the first data from the first storage area to the second storage area in response to a change in the reference count of the first data.03-28-2013
20130080683MEMORY SYSTEM PROVIDED WITH NAND FLASH MEMORY AND METHOD OF CONTROLLING THE SAME - According to one embodiment, a memory system includes first, and second districts, and control section. Each of the first and second districts includes a memory cell array. The control section receives a write command to simultaneously write first data to the first, and second districts, and addresses, and simultaneously writes the first data to the first and second districts.03-28-2013
20130080682RECLAIMING SPACE OCCUPIED BY AN EXPIRED VARIABLE RECORD IN A NON-VOLATILE RECORD STORAGE - In a method for reclaiming space occupied by an expired variable record in a non-volatile record storage, a reclaim state data that includes a state of a reclaim operation is maintained. In addition, the state of the reclaim operation is marked to indicate a progress of the reclaim operation at a plurality of stages of the reclaim operation. The reclaim operation is implemented by sliding, one section at a time, the data in a first direction along the plurality of sections and by sliding, one section at a time, the variable records, excluding the expired variable record, in a second direction along the plurality of sections, to thereby remove the expired variable record.03-28-2013
20130080684ADAPTER HAVING HIGH SPEED STORAGE DEVICE - An adapter, providing a selective connection between a host and mass storage device, includes a high-speed storage device, a host interface and a device interface. The high-speed storage device is provided on a front surface of a printed circuit board (PCB), and includes multiple nonvolatile memory devices and a controller configured to control operations of the nonvolatile memory devices. The host interface is on a back surface of the PCB, and is configured to interface between the high-speed storage device and the host. The device interface is on the back surface of the PCB, and is configured to interface between the high-speed storage device and the mass storage device.03-28-2013
20130086309FLASH-DRAM HYBRID MEMORY MODULE - A memory module that is couplable to a memory controller hub (MCH) of a host system includes a non-volatile memory subsystem, a data manager coupled to the non-volatile memory subsystem, a volatile memory subsystem coupled to the data manager and operable to exchange data with the non-volatile memory subsystem by way of the data manager, and a controller operable to receive read/write commands from the MCH and to direct transfer of data between any two or more of the MCH, the volatile memory subsystem, and the non-volatile memory subsystem based on the commands.04-04-2013
20130086308STORAGE DEVICE AND METHOD OF ACCESSING COPY DESTINATION DATA - A storage device copies copy source data stored in a copy source volume to a copy destination volume and manages copied data in units of generations. The storage device includes a first storing unit, a second storing unit, and a processor. The first storing unit stores information representing presence/no-presence of a copy in association with a logical address of the copy destination volume in units of generations. The second storing unit stores a physical address of the copy destination volume in units of generations. The processor determines, when receiving an access request for a copy destination volume, presence/non-presence of a copy of a logical address for which the access request is made by using information in the first storing unit, and to access a physical address of the copy destination volume acquired from the second storing unit for a generation designated by a result of the determination.04-04-2013
20130036262APPARATUS, SYSTEM, AND METHOD FOR TESTING PHYSICAL REGIONS IN A SOLID-STATE STORAGE DEVICE - An apparatus, system, and method are disclosed for testing physical regions in a solid-state storage device. The method includes defining a physical storage region on solid-state storage media of a solid-state storage device. The physical storage region includes a subset of storage capacity of the solid-state storage media. The method includes implementing the physical storage region definition on a storage controller such that memory operations are bounded to the physical storage region. The method includes testing wear of solid-state storage media associated with the physical storage region using memory operations bounded to the physical storage region.02-07-2013
20130036261METHOD FOR OPERATING MEMORY CONTROLLER, AND MEMORY SYSTEM INCLUDING THE SAME - A method for operating a memory controller capable of controlling a maximum count of a read retry operation is disclosed. The method includes programming a first real time clock (RTC) value indicating a time-of-day when a program operation is performed when the program operation for programming a data to a storage region of a non-volatile memory, obtaining information for the storage region by using the first RTC value read from the non-volatile memory and a second RTC value indicating a time-of-day when a read operation is performed, when the read operation for the data programmed to the storage region is performed, and decreasing a maximum count of a read retry operation by using the information, when the read retry operation is performed for the storage region.02-07-2013
20130036260INFORMATION PROCESSING APPARATUS AND CACHE METHOD - According to one embodiment, an information processing apparatus includes a controller and a cache module. The controller is configured to issue commands for a first storage device and a second storage device, and thereby perform data transmission. The cache module is configured to use the first storage device as a read cache of the second storage device, the cache module withholding issuance of a write command to write cache data in the first storage device to the controller, when commands issued by the controller to the first storage device exceed a preset number, until the issued commands becomes equal to or less than the preset number.02-07-2013
20130036259SOLID STATE DRIVE AND DATA STORING METHOD THEREOF - A solid state drive includes a plurality of dies. The dies are divided into first-portion dies and second-portion dies. The first-portion dies are located at a user area. The second-portion dies are located at a reserved area. The solid state drive is in communication with a host. The data storing method of the solid state drive includes the following steps. Firstly, if the host generates a plurality of write data to the solid state drive, the plurality of write data are stored into the reserved area. If there is not accessing action between the host and the solid state drive and if the write data are in the reserved area, the write data are stored into the user area. Afterwards, error correction codes corresponding to the write data in the user area are calculated and stored into the reserved area.02-07-2013
20130036258MEMORY STORAGE DEVICE, MEMORY CONTROLLER THEREOF, AND METHOD FOR PROGRAMMING DATA THEREOF - A memory storage device, a memory controller thereof, and a method for programming data thereof are provided. The memory storage device includes a buffer memory and a rewritable non-volatile memory chip, wherein the rewritable non-volatile memory chip includes a buffer unit and a plurality of physical blocks. The method includes storing first data received from a host system into the buffer memory, and generating a writing complete message for replying to the host system after the first data stored in the buffer memory is transmitted to the buffer unit by using a first data transmitting command. The method further includes programming the first data to a first physical block of the physical blocks. Meanwhile, if a data program failure is detected, the method also includes programming the first data maintained in the buffer unit to a second physical block by using a second data transmitting command.02-07-2013
20130036257MEMORY SYSTEM WHICH CAN AVOID UNAVAILABILITY DUE TO OPERATION ERROR BY USER - According to one embodiment, a memory system includes a nonvolatile semiconductor storage device and controller. The nonvolatile semiconductor storage device has a file system area including a file allocation table (FAT), a data write-once area including a plurality of clusters, and a management information area which stores a pointer indicating a rewrite inhibition area of the clusters. The controller reads the FAT from the file system area of the nonvolatile semiconductor storage device, and sets the pointer based on a cluster use status recorded in the FAT.02-07-2013
20130036256METHOD AND APPARATUS OF SANITIZING STORAGE DEVICE - Systems and methods directed to erasing data and/or the sanitization of storage systems. In storage systems that utilize storage devices such as Flash Memory Devices or Hard Disk Drives (HDDs), systems and methods utilize the initializing function of the storage device to erase the data. Storage devices within the storage systems may have an initializing function that erases all blocks of the storage device. Systems and methods further check for the initializing function and the media type to determine if the initializing function is available to determine the optimal sanitizing process for the device.02-07-2013
20130036255TESTING MEMORY SUBSYSTEM CONNECTIVITY - In one implementation, a memory subsystem includes a plurality of non-volatile memory dies, a memory controller that is communicatively connected to each of the non-volatile memory dies over one or more first busses, a host interface through which the memory controller communicates with a host over a second bus, and a joint test action group (JTAG) interface through which the host performs a boundary scan of the memory subsystem including, at least, the non-volatile memory dies and the memory controller. The memory subsystem can be configured to be a subunit of a board-level memory device that includes the host.02-07-2013
20130036254DEBUGGING A MEMORY SUBSYSTEM - In one implementation, a memory subsystem includes non-volatile memory, a memory controller that is communicatively connected to the non-volatile memory over a first bus, a host interface through which the memory controller communicates with a host controller over a second bus, and a joint test action group (JTAG) interface that provides the host controller with access to state information associated with the memory controller. The memory subsystem can be configured to be coupled to a board-level memory device that includes the host controller.02-07-2013
20130036253WEAR LEVELING FOR A MEMORY DEVICE - Memory devices and methods to facilitate wear leveling operations in a memory device. In one such method, particular blocks of memory cells are excluded from experiencing wear leveling operations performed on the memory device. In at least one method, a user selects blocks of memory to be excluded from wear leveling operations performed on the remainder of blocks of the memory device. Selected blocks of memory are excluded from wear leveling operations responsive to a command initiated by a user identifying, either directly or indirectly, the selected blocks to be excluded.02-07-2013
20130036252PRACTICAL CODE LIST CACHE FOR VALUE HELP - Methods and apparatus, including computer program products, are provided for providing value help. In one aspect, there is provided a computer-implemented method. The method may include receiving, at a code list provider, a request from a user interface for code list value help; determining, based on the request, whether to access at least one of a cache and a secondary storage; accessing, by the code list provider, a cache including at least a first code list, the cache implemented in memory, when the determination results in access to the cache; accessing a secondary storage including at least a second code list, when the determination results in access to the secondary storage; and sending, by the code list provider, at least one of the first code list and the second code list to a user interface to enable the user interface to provide code list value help. Related apparatus, systems, methods, and articles are also described.02-07-2013
20130036251METHOD AND SYSTEM OF A TIMER BASED BUFFER USED FOR METROLOGY - Described herein are embodiments of methods and systems of using a timer based memory buffer for metrology. One embodiment of the method comprises receiving metrology data from one or more metrology sensors; writing at least part of the metrology data to a volatile memory; incrementing a write pointer to indicate the metrology data contained within the volatile memory; and repeating the above until a timer expires, then reading at least a portion of the metrology data from the volatile memory.02-07-2013
20120265925SEMICONDUCTOR DEVICE AND METHOD OF CONTROLLING NON-VOLATILE MEMORY DEVICE - A control circuit of a semiconductor device (memory module) realizes long life and others by a mechanism that suppresses and smoothes variations in use of a memory by equalizing the sizes of data write and data erase with respect to a data write request and sequentially allocating and using addresses of the memory in data write to an overwritable non-volatile memory device without carrying out an overwriting operation even in the case of an overwrite request. The control circuit realizes data write by a set of two types of operations of (a) an operation of erasing data of a first address or an operation of setting a flag value to an invalid state and (b) an operation of writing data to a second address different from the first address or an operation of setting a flag value to a valid state.10-18-2012
20080307157Method and system for updating firmware of microcontroller - A system for updating firmware of a microcontroller includes a serial peripheral interface (SPI), an inter integrated Circuit (I12-11-2008
20130138872APPARATUS WITH A MEMORY CONTROLLER CONFIGURED TO CONTROL ACCESS TO RANDOMLY ACCESSIBLE NON-VOLATILE MEMORY - An apparatus includes a printed circuit board with a plurality of printed circuit board traces, a memory controller mounted on the printed circuit board coupled to one or more of the plurality of printed circuit board traces, a plurality of non-volatile type of memory integrated circuits coupled to the printed circuit board, and a plurality of support integrated circuits coupled between the memory controller and the plurality of non-volatile type of memory integrated circuits.05-30-2013
20100169551MEMORY SYSTEM AND METHOD OF CONTROLLING MEMORY SYSTEM - A forward lookup address translation table and a reverse lookup address translation table stored in a nonvolatile second storing unit are transferred as a master table to a volatile first storing unit at a time of start-up. When an event occurs so that the master table needs to be updated, difference information before and after update of any one of the forward lookup address translation table and the reverse lookup address translation table is recorded in the first storing unit as a log, thereby reducing an amount of the log.07-01-2010
20130080692CONTENT-AWARE DIGITAL MEDIA STORAGE DEVICE AND METHODS OF USING THE SAME - A content-aware digital media storage device includes a host device interface for exchanging digital information with a host device, a memory array for storing digital information received from the host device via the host interface, a peripheral module configured to communicate the digital information stored in the memory array to a receiver located remote from the digital media storage device, and a controller communicatively coupled to the host device interface, the memory array and the peripheral module and configured to interpret directory information associated with the digital information stored in the memory array so as to selectively access said digital information and communicate such accessed digital information to the peripheral module for transmission to the remote receiver. Digital images stored in the memory array may be transmitted to a remote host via a wireless network access point with which the peripheral module of the storage device is associated.03-28-2013
20130080691FLASH MEMORY DEVICE WITH PHYSICAL CELL VALUE DETERIORATION ACCOMMODATION AND METHODS USEFUL IN CONJUNCTION THEREWITH - A method for converting a measured physical level of a cell into a logical value, in an array of memory cells storing physical levels which diminish over time, the method may include: determining extent of deterioration of the physical levels and determining thresholds accordingly for at least an individual cell in the array; and reading the individual cell including reading a physical level in said cell and converting said physical level into a logical value using at least some of said thresholds, wherein said determining extent of deterioration comprises storing predefined physical levels rather than data-determined physical levels in each of a plurality of cells and determining extent of deterioration by computing deterioration of said predefined physical levels.03-28-2013
20130042053Method and Apparatus for Flexible RAID in SSD - A solid state drive (SSD) employing a redundant array of independent disks (RAID) scheme includes a flash memory chip, erasable blocks in the flash memory chip, and a flash controller. The erasable blocks are configured to store flash memory pages. The flash controller is operably coupled to the flash memory chip. The flash controller is also configured to organize certain of the flash memory pages into a RAID line group and to write RAID line group membership information to each of the flash memory pages in the RAID line group.02-14-2013
20130042052LOGICAL SECTOR MAPPING IN A FLASH STORAGE ARRAY - A system and method for efficiently performing user storage virtualization for data stored in a storage system including a plurality of solid-state storage devices. A data storage subsystem supports multiple mapping tables. Records within a mapping table are arranged in multiple levels. Each level stores pairs of a key value and a pointer value. The levels are sorted by time. New records are inserted in a created newest (youngest) level. No edits are performed in-place. All levels other than the youngest may be read only. The system may further include an overlay table which identifies those keys within the mapping table that are invalid.02-14-2013
20130042051PROGRAM METHOD FOR A NON-VOLATILE MEMORY - A program method for a non-volatile memory is disclosed. At least two blocks in the non-volatile memory are configured as 1-bit per cell (1-bpc) blocks. The data of the configured blocks are read and written to a target block in such a way that the data of each said configured block are moved to pages of a same significant bit. In another embodiment, the data of the configured blocks excluding one block are read and written to the excluded block.02-14-2013
20130042050METHOD AND SYSTEM FOR EFFICIENTLY SWAPPING PIECES INTO AND OUT OF DRAM - A system and method for managing swaps of pieces of an address mapping table is disclosed. The method may include a controller of a storage device receiving a stream of requests for accesses to the mapping table, analyzing the stream of requests to determine at least one characteristic of the stream of requests, and determining whether to copy a piece of the mapping table stored in non-volatile memory into the volatile memory based on the determined at least one characteristic. The system may include a storage device with a controller configured to perform the method noted above.02-14-2013
20130042049ENHANCED COPY-ON-WRITE OPERATION FOR SOLID STATE DRIVES - A method for increasing the efficiency of a “copy-on-write” operation performed on an SSD to extend the life of the SSD is disclosed herein. In one embodiment, such a method includes receiving a first logical address specifying a logical location where new data should be written to an SSD. The first logical address maps to a first physical location, storing original data, on the SSD. The method further receives a second logical address specifying a logical location where the original data should be available on the SSD. The second logical address maps to a second physical location on the SSD. To efficiently perform the copy-on-write operation, the method writes the new data to a new physical location on the SSD, maps the first logical address to the new physical location, and maps the second logical address to the first physical location. A corresponding apparatus is also disclosed.02-14-2013
20130042054Methods of Managing Meta Data in a Memory System and Memory Systems Using the Same - A method of managing meta data can be provided by generating log entry information including log data in response to changes to meta data that includes a plurality of groups of the meta data. A group of the meta data can be selected from among the plurality of groups of the meta data to provide a selected group of meta data in response to detecting that a number of pieces of the log entry information is equal to or greater than a particular threshold value. The selected group of the meta data and associated log data can be stored in a non-volatile memory device.02-14-2013
20130042058SOLID STATE MEMORY (SSM), COMPUTER SYSTEM INCLUDING AN SSM, AND METHOD OF OPERATING AN SSM - In one aspect, data is stored in a solid state memory which includes first and second memory layers. A first assessment is executed to determine whether received data is hot data or cold data. Received data which is assessed as hot data during the first assessment is stored in the first memory layer, and received data which is first assessed as cold data during the first assessment is stored in the second memory layer. Further, a second assessment is executed to determine whether the data stored in the first memory layer is hot data or cold data. Data which is then assessed as cold data during the second assessment is migrated from the first memory layer to the second memory layer.02-14-2013
20130042056Cache Management Including Solid State Device Virtualization - A method of caching data is performed by a respective computer having one or more processors storing one or more storage management programs for execution by the one or more processors, non-volatile secondary storage and non-volatile cache memory. The method includes receiving from the non-volatile cache memory information identifying an amount of available storage in the non-volatile cache memory, and identifying a size of the management units in the non-volatile cache memory. The method further includes identifying write requests to write data to the non-volatile cache memory, sequentially writing to the non-volatile cache memory the write data for the identified write requests, to sequentially arranged locations in an address space of the non-volatile cache memory, and storing in memory metadata that maps the addresses or storage offsets of the write data to respective locations in the address space of the non-volatile cache memory.02-14-2013
20090172263Flash storage controller execute loop - In a storage controller connected to a flash memory module, an execute loop used to carry out tasks related to reading or writing data from the module. The loop includes reading a data structure from a queue and carrying out a task specified by the data structure, unless resources required by the task are not available, in which event the loop moves on to another data structure stored in another queue. Data structures bypassed by the loop are periodically revisited, until all tasks required are completed. Data structures store state information that is updated when tasks are completed.07-02-2009
20090172258Flash memory controller garbage collection operations performed independently in multiple flash memory groups - A flash memory controller connected to multiple flash memory groups performs independent garbage collection operations in each group. For each group, the controller independently determines the amount of free space and performs garbage collection operations if the amount falls below a threshold.07-02-2009
20090172255WEAR LEVELING METHOD AND CONTROLLER USING THE SAME - A wear leveling method for a multi level cell (MLC) NAND flash memory is provided. The flash memory includes a first zone and a second zone respectively having a plurality of blocks, wherein each of the blocks includes an upper page and a lower page. The wear leveling method includes: respectively determining whether to start a block swapping operation of a wear leveling process in the first zone and the second zone of the flash memory according to different start-up conditions; and respectively performing the block swapping operation in the first zone and the second zone, wherein the blocks in the first zone are accessed by using only the lower pages, and the blocks in the second zone are accessed by using both the upper pages and the lower pages. Thereby, the lifespan of the flash memory is effectively prolonged and meaningless consumption of system resources is avoided.07-02-2009
20090172254METHOD FOR PREVENTING READ-DISTURB HAPPENED IN NON-VOLATILE MEMORY AND CONTROLLER THEREOF - A method for preventing read-disturb happened in non-volatile memory and a controller thereof are disclosed. The non-volatile memory includes a plurality of blocks, and the blocks are grouped into at least a data group and a spare group, each block includes a plurality of pages. The method includes recording read times of at least a first block of the blocks within the data group and then renewing the original data stored in the first block when the read times of the first block is greater than a predetermined value.07-02-2009
20090172265FLASH MEMORY DEVICE HAVING SECURE FILE DELETION FUNCTION AND METHOD FOR SECURELY DELETING FLASH FILE - Disclosed is a flash memory device having a secure flash file deletion function and a method for securely deleting a flash file. Data and object headers as actual contents of the flash file are separately stored in data blocks and header blocks. At this time, the data is encrypted and stored, and a decryption key is included in an object header and stored in a header block. When the flash file is deleted, the object header is deleted by searching the header block where the object header including the decryption key is stored. In order to search the header block, a binary tree structure is used in which a terminal node indicates an LSB of a file ID. Disclosed may be applied to an embedded system where a flash memory is used as a storage medium. In particular, disclosed is suitable for a NAND flash memory device.07-02-2009
20120210049MEMORY MODULE AND VIDEO CAMERA - According to the embodiments, there are provided semiconductor memories that are mounted individually on two sides of a mounting board; a controller that is mounted either on an obverse side or a reverse side of the mounting board, and performs read and write control of the semiconductor memories; and a connector that is deviated in a lateral direction from the controller so as not to overlap the controller, is mounted either on the obverse side or the reverse side of the mounting board, and transfers a signal exchanged between the controller and outside.08-16-2012
20130042057Hybrid Non-Volatile Memory System - A hybrid non-volatile system uses non-volatile memories based on two or more different non-volatile memory technologies in order to exploit their relative advantages. In an exemplary embodiment, the memory system includes a controller and a flash memory, where the controller has a non-volatile RAM based on an alternate technology such as FeRAM. The flash memory is used for the storage of user data and the non-volatile RAM in the controller is used for system control data. The use of an alternate non-volatile memory technology in the controller allows for a non-volatile copy of the most recent control data to be accessed more quickly as it can be updated on a bit by bit basis. In another exemplary embodiment, the alternate non-volatile memory is used as a cache where data can safely be staged prior to its being written to the memory or read back to the host.02-14-2013
20130042055MEMORY SYSTEM INCLUDING KEY-VALUE STORE - According to one embodiment, a memory system including a key-value store containing key-value data as a pair of a key and a value corresponding to the key, includes a first memory, a control circuit and a second memory. The first memory is configured to contain a data area for storing data, and a table area containing the key-value data. The control circuit is configured to perform write and read to the first memory by addressing, and execute a request based on the key-value store. The second memory is configured to store the key-value data in accordance with an instruction from the control circuit. The control circuit performs a set operation by using the key-value data stored in the first memory, and the key-value data stored in the second memory.02-14-2013
20130042048Techniques to store configuration information in an option read-only memory - Method and apparatus to store configuration information in an option read-only memory are described.02-14-2013
20080201520Flash firmware management - A computing host executes a web browser to access a utility application for managing one or more storage devices connected to the computing host. Management of each storage device may include making queries about the storage spaces and contents of the storage device, updating firmware of the storage device, updating programmable hardware of the storage device, erasing the storage device, sanitizing the storage device, logging events occurring in the storage device, and maintaining statistics on operation of the storage device.08-21-2008
20100042776Method and apparatus for providing enhanced write performance using a buffer cache management scheme based on a buffer replacement rule - An approach is provided for improving write performance using a buffer cache based on a buffer replacement policy. A buffer cache manager is configured to improve address mapping scheme associated with write performance between an application system and a storage device system. The manager selects a victim page to be evicted from a victim block of a buffer cache according to a recently-evicted-first rule. And the victim block is selected associated with a log block of a memory.02-18-2010
20100042775BLOCK MANAGEMENT METHOD FOR FLASH MEMORY, AND STORAGE SYSTEM AND CONTROLLER USING THE SAME - A block management method for managing a flash memory is provided. The method includes dividing the flash memory into a cache area and a storage area and dividing the cache area into a plurality of cache sub-areas, wherein the storage area has a plurality of physical blocks and each cache sub-area contains at least one physical block. The method also includes configuring a plurality of logical blocks for mapping the physical blocks of the storage area, and allocating one of the cache sub-areas for each logical block, wherein when the host writes the data into the logical blocks, the data may be temporarily stored in the cache sub-areas allocated for the logical blocks. Accordingly, it is possible to increase efficiency of the flash storage system and avoid wearing of the physical blocks, so as to prolong a lifetime of the flash storage system.02-18-2010
20100042774BLOCK MANAGEMENT METHOD FOR FLASH MEMORY, AND STORAGE SYSTEM AND CONTROLLER USING THE SAME - A block management method for a flash memory chip having multiple planes is provided, wherein each plane has a plurality of physical blocks. The method includes disposing a plurality of physical units, wherein each physical unit includes a physical block of each plane, and the physical blocks in the physical unit have a simultaneously-operable relationship. The method also includes writing data in a single plane access mode when a host system does not update all the physical blocks in an updated the physical unit. The method further includes writing the data in a multi-planes access mode when the host system updates all the physical blocks in the updated physical unit, wherein the physical blocks for writing the data have the simultaneously-operable relationship.02-18-2010
20100042773FLASH MEMORY STORAGE SYSTEM AND DATA WRITING METHOD THEREOF - A flash memory storage system and a data writing method thereof are provided. The flash memory storage system includes a controller, a connector, a cache memory, a SLC NAND flash memory and a MLC NAND flash memory. When the controller receives data to be written into the MLC NAND flash memory from a host system, the data is temporarily stored in the cache memory first and then is written into the MLC NAND flash memory from the cache memory. And, the controller may backup the data stored in the cache memory to the SLC NAND flash memory. Accordingly, it is possible to reduce a response time for a flush command, thereby improving a performance of the flash memory storage system.02-18-2010
20100042772Method and apparatus for high reliability data storage and retrieval operations in multi-level flash cells - One or more multi-level NAND flash cells are operated so as to store only single-level data, and these operations achieve an increased level of charge separation between the data states of the single-level operation by requiring a write to both the upper and lower pages, even though only one bit of data is being stored. That is, the second write operation increases the difference in floating gate charge between the erased state and the programmed state of the first write operation without changing the data in the flash memory cell. In one embodiment, a controller instructs the flash memory to perform two write operations for storing a single bit of data in an MLC flash cell. In another embodiment, the flash memory recognizes that a single write operation is directed a high reliability memory area and internally generates the required plurality of programming steps to place at least a predetermined amount of charge on the specified floating gate.02-18-2010
20100042777SEMICONDUCTOR DEVICE INCLUDING MEMORY CELL HAVING CHARGE ACCUMULATION LAYER AND CONTROL GATE AND DATA WRITE METHOD FOR THE SAME - A semiconductor device includes a nonvolatile semiconductor memory and a controller. The nonvolatile semiconductor memory includes a first memory block configured to hold at least 2 bits data, and a second memory block configured to hold 1-bit data. The data is programmed into the first and second memory blocks in units of page. Each of the pages in the first memory block is assigned to a corresponding bit of the held data. Time required for write varies depending on the bit. The controller instructs the nonvolatile semiconductor memory to program the write data into the first memory block or the second memory block. The controller instructs the nonvolatile semiconductor memory to program the data on any of the pages in the second memory block if a final page of the write data corresponds to the bit requiring the longest time for the write.02-18-2010
20090157953Data line disturbance free memory block divided flash memory and microcomputer having flash memory therein - A semiconductor device having an electrically erasable and programmable nonvolatile memory, for example, a rewritable nonvolatile memory including memory cells arranged in rows and columns and disposed to facilitate both flash erasure as well as selective erasure of individual units of plural memory cells. The semiconductor device which functions as a microcomputer chip also has a processing unit and includes an input terminal for receiving an operation mode signal for switching the microcomputer between a first operation mode in which the flash memory is rewritten under control of a processing unit and a second operation mode in which the flash memory is rewritten under control of separate writing circuit externally connectable to the microcomputer.06-18-2009
20090157951INFORMATION RECORDING DEVICE AND INFORMATION RECORDING METHOD - An information recording device includes a table showing a physical address in first and second areas and a number of rewriting at the physical address in a correspondence manner, the first area being a writing destination in a recording medium configured to be consumed by rewriting, the second area being not a writing destination in the recording medium, an instructor configured to instruct to change the first and second tables based on the first table and the physical address of the writing destination, a changer configured to change the table based on the instruction, and a writer configured to write data to the recording medium based on the physical address in the first area.06-18-2009
20090157949ADDRESS TRANSLATION BETWEEN A MEMORY CONTROLLER AND AN EXTERNAL MEMORY DEVICE - In one or more embodiments, address translation is performed over a dedicated serial bus between a non-volatile memory controller and a memory device that is external from the non-volatile memory device. The memory controller accesses memory address translation data in the external memory device to determine a physical address that corresponds to a logical memory address. The controller can then use the physical memory address to generate memory signals for the non-volatile memory array.06-18-2009
20090157948INTELLIGENT MEMORY DATA MANAGEMENT - Systems and/or methods that facilitate data management on a memory device are presented. A data management component can log and tag data creating data tags. The data tags can comprise static metadata, dynamic metadata or a combination thereof. The data management component can perform file management to allocate placement of data and data tags to the memory or to erase data from the memory. Allocation and erasure are based in part on the characteristics of the data tags, and can follow embedded rules, an intelligent component or a combination thereof. The data management component can provide a search activity that can utilize the characteristics of the data tags and an intelligent component. The data management component can thereby optimize the useful life, increase operating speed, improve accuracy and precision, improve efficiency of non-volatile (e.g., flash) memory and provide improved functionality to memory devices.06-18-2009
20090157947Memory Apparatus and Method of Evenly Using the Blocks of a Flash Memory - A memory apparatus and a method of evenly using the blocks of a flash memory are provided. The memory apparatus comprises a flash memory and a controller. The flash memory comprises a data region with a plurality of data blocks and a spare region with a plurality of spare blocks. The controller is configured to receive data corresponding to the first data block, select a spare block, program data into the spare block when the erase count corresponding to the spare block is less than the predetermined value or to select a second data block and program data stored in the second data block into the spare block when the erased count corresponding to the spare block reaches the predetermined value. As a result, the blocks of the flash memory are used evenly.06-18-2009
20090157946MEMORY HAVING IMPROVED READ CAPABILITY - In the present invention, a memory, and in particular, a NOR emulating memory comprises a memory controller having a non-volatile memory for storing program code to initiate the operation of the memory controller. The controller has a first bus for receiving address signals from a host device and a second bus for interfacing with a RAM memory, and a third bus for interfacing with a NAND memory. A volatile RAM memory is connected to the second bus. A NAND memory is connected to the third bus. The controller receives commands and a first address from the first bus, and maps the first address to a second address in the NAND memory, and operates the NAND memory in response thereto. The RAM memory serves as cache for data to or from the NAND memory. The controller also maintains data coherence between the data stored in the RAM memory as cache and the data in the NAND memory. The invention further has a first buffer for storing data from the NAND memory in response to a read command to be written to the RAM memory, and a second buffer for storing data from the RAM memory to be written to the NAND memory. In the event of a read operation, if the data from the specified address is in the RAM memory, then the data is read from the RAM memory completing the read operation. In the event of a read operation, and if the data from the specified address is not in the RAM memory, and if there is sufficient space in the RAM memory to store an entire page of data from the NAND memory, then the entire page is read from the NAND memory, stored in the first buffer and then stored in the RAM memory, and from the specified address is read out, completing the read operation. Finally, in the event of a read operation, and if the data from the specified address is not in the RAM memory, and if there is insufficient space in the RAM memory to store an entire page of data from the NAND memory, then an entire page from the RAM memory is first stored in the second buffer, then an entire page is read from the NAND memory, stored in the first buffer, and from the first buffer, stored in the now freed RAM memory and data from the specified address is read out, completing the read operation. The page of data from the second buffer is subsequently stored back into the NAND memory after the completion of the read operation thereby reducing read latency.06-18-2009
20090157952Semiconductor memory system and wear-leveling method thereof - Disclosed is a semiconductor memory system and wear-leveling method thereof. The semiconductor memory system is comprised of a nonvolatile memory including a plurality of logic blocks each of which is divided into a plurality of entries, a file system detecting a type of data to be stored and allocating the logic block or the entry for storing the data in accordance with the data type, and a translation layer leveling wearing degrees over the logic blocks or the entries in accordance with the data type. The semiconductor memory system is improved in performance and lifetime by managing wearing degrees over the logic block or the entries in accordance with the data type.06-18-2009
20090113118MEMORY MODULE AND CONTROL METHOD OF SERIAL PERIPHERAL INTERFACE USING ADDRESS CACHE - A serial peripheral interface memory module using address cache comprises a flash memory array for storing data, a serial/parallel convertor for receiving serial signals and generating a control command, an address and data, an address register, an address accumulator for accumulating the address in the address register and storing the accumulated address back to the address register, and a flash memory controller for controlling the access to the flash memory array. When the control command is a standard command, the serial/parallel controller first stores the address following the control command into the address register and then the flash memory controller accesses data according to the address in the address register. When the control command is a specific command, the flash memory controller directly accesses data according to the address in the address register without waiting for an address update.04-30-2009
20100106898STORAGE AND REPRODUCTION APPARATUS - The storage and reproducing apparatus includes a signal processing block, a memory, a reproduction block, an operation block, and a control block. The signal processing block converts a sound signal entered, into a digital signal. The memory stores a digital signal outputted form the signal processing block and a management data of the digital data. The reproduction block at least converts a digital signal read out from the memory, into a hearable sound for reproduction output. The operation block is provided on an apparatus main body and includes a rotary operation block provided on the apparatus main body in such a manner that the rotary operation block can be rotated around a rotation center and shifted along plane which almost orthogonally intersects the rotation center. The control block, according to an input from the operation block, writes a digital signal and a management data into the memory and reads out a digital signal and a management data stored in the memory. The control block, according to a rotation direction of the rotary operation block, reads out a management data from the memory. When the rotary operation block is shifted along the plane, the control block reads out a digital signal from the memory according to a management information which is being read out from the memory.04-29-2010
20100106897STORAGE DEVICE, DISK DEVICE, WRITE DETERMINING METHOD, AND CONTROL DEVICE - According to one embodiment, a storage device divides and writes into pages a management information table for managing addresses at which data are written. The storage device includes: a writing module configured to write a duplicate of a last page of the management information table after writing the management information table divided into the pages; an acquiring module configured to acquire the last page and the duplicate of the last page written by the writing module; and a determining module configured to determine whether the writing of the management information table has been successful, by comparing the last page and the duplicate of the last page acquired by the acquiring module with each other, or by checking whether the duplicate of the last page has been written by the writing module.04-29-2010
20100106896METHOD FOR WRITING AND READING DATA IN AN ELECTRICALLY ERASABLE AND PROGRAMMABLE NONVOLATILE MEMORY - A method for writing and reading data in a main nonvolatile memory having target pages in which data are to be written and read, the method including providing a nonvolatile buffer having an erased area, providing a volatile cache memory, and receiving a write command to update a target page with updating data the length of which can be lower than the length of a page. The method also includes, in response to the write command, writing the updating data into the erased area of the nonvolatile buffer, together with management data of a first type, and recording an updated version of the target page in the cache memory or updating in the cache memory a previously updated version of the target page.04-29-2010
20100106895Hardware and Operating System Support For Persistent Memory On A Memory Bus - Implementations of a file system that is supported by a non-volatile memory that is directly connected to a memory bus, and placed side by side with a dynamic random access memory (DRAM), are described.04-29-2010
20100106894Method of storing and accessing error correcting code in NAND Flash - A method of storing and accessing an error correcting code in NAND Flash, includes utilizing n pages of a block of the NAND Flash as an extended space of a spare area, n≦1, wherein when writing data, the data is stored in a data area of a sector, and when the error correcting code needs a space which has correcting capability larger than 16 bytes, first 16 bytes of the error correcting code is stored in the 16 bytes spare area, and the remaining of the error correcting code is stored in the extended space of the spare area corresponding to the sector. Therefore, the method develops new storing space for the error correcting code, arranges the error correcting code in sequence of data blocks in sub-space, and loads the error correcting code into system memory for the decoder before reading original data.04-29-2010
20100106893PAGE BUFFER PROGRAM COMMAND AND METHODS TO REPROGRAM PAGES WITHOUT RE-INPUTTING DATA TO A MEMORY DEVICE - A technique for efficiently handling write operation failures in a memory device which communicates with an external host device allows a page of data to be re-written to a memory array from a page buffer. The host provides user data, a first write address and a write command to the memory device. If the write attempt fails, the host provides a re-write command with a new address, without re-sending the user data to the memory device. Additional data can be received at a data cache of the memory device while a re-write from the page buffer is in progress. The re-written data may be obtained in a copy operation in which the data is read out to the host, modified and written back to the memory device. Additional data can be input to the memory device during the copy operation. Page buffer data can also be modified in place.04-29-2010
20100106892Access Methods For Memory Devices And Memory Devices Thereof - An access method for use in a memory device is provided. The memory device comprises a data area having a plurality of data blocks and a spare area having a plurality of spare blocks. First, data from a host is received. A spare block is popped from the spare area and the received data is programmed into the popped spare block accordingly. A data block corresponding to the data is pushed to the spare area. The pushed data block is erased when the memory device is waiting for a specific instruction to be issued from the host.04-29-2010
20100106891Preventing Unintended Permanent Write-Protection - An input voltage range may be established between different voltage levels used for different programming functions of an integrated circuit device, thus implementing a protection zone (“safe zone”) of non-operation to facilitate prevention of an unintended irreversible programming operation, e.g., permanent write protection.04-29-2010
20100106889SOLID STATE DRIVE OPERATION - The present disclosure includes methods and devices for operating a solid state drive. One method embodiment includes mirroring programming operations such that data associated with a programming operation is programmed to two or more locations in memory of the solid state drive. The method also includes ceasing to mirror programming operations upon an occurrence of a particular event.04-29-2010
20100106888Method and System For Device Independence In Storage Device Wear Algorithms - A device, methods and systems that provide device independence in storage device wear algorithms are disclosed. A storage device that provides such device independence includes a device-specific wear algorithm, and may also include an integrated wear algorithm. The device-specific wear algorithm is configured to be loaded into a wear algorithm space and is at least a portion of a wear algorithm. The device-specific wear algorithm is stored in the storage device. The integrated wear algorithm, if employed, is resident in the storage device. A method that provides such device independence is also disclosed. The method includes loading a device-specific wear algorithm from a storage device into a wear algorithm space. The device-specific wear algorithm is configured to be stored in the storage device and loaded into the wear algorithm space. The device-specific wear algorithm is at least a portion of a wear algorithm.04-29-2010
20100106887FLASH PRESENTATION (FLAPRE) AUTHORING TOOL THAT CREATES FLASH PRESENTATIONS INDEPENDENT OF A FLASH SPECIFICATION - A system for authoring a FLASH presentation can include a FLASH-based FLASH presentation (FLAPRE) authoring tool and a launching application. The FLAPRE authoring tool can be configured to create a specialized FLAPRE code file containing a user-created FLASH presentation. The specialized FLAPRE code file can be created without the use of a FLASH specification. The launching application can be configured to present the FLASH-based FLAPRE authoring tool. The launching application can also support the use of FLASH animation.04-29-2010
20120066433Apparatus and method for read preamble disable - A memory device is provided. The memory device includes a preamble disable memory and a memory controller. The preamble disable memory is arranged to store preamble disable data. The preamble disable data includes an indication as to whether a read preamble should be enabled or disabled. In response to a read command, if the preamble disable data includes an indication that the read preamble should be enabled, the memory controller provides the read preamble. Alternatively, in response to the read command, if the preamble disable data includes an indication that the read preamble should be disabled, the memory controller disables the read preamble.03-15-2012
20090132758RANK MODULATION FOR FLASH MEMORIES - We investigate a novel storage technology, Rank Modulation, for flash memories. In this scheme, a set of n cells stores information in the permutation induced by the different charge levels of the individual cells. The resulting scheme eliminates the need for discrete cell levels, and overshoot errors when programming cells (a serious problem that reduces the writing speed), as well as mitigate the problem of asymmetric errors. We present schemes for Gray codes, rewriting and joint coding in the rank modulation paradigm.05-21-2009
20090125671APPARATUS, SYSTEM, AND METHOD FOR STORAGE SPACE RECOVERY AFTER REACHING A READ COUNT LIMIT - An apparatus, system, and method are disclosed for storage space recovery after reaching a read count limit. A read module reads data in a storage division of solid-state storage. A read counter module then increments a read counter corresponding to the storage division. A read counter limit module determines if the read count exceeds a maximum read threshold, and if so, a storage division selection module selects the corresponding storage division for recovery. A data recovery module reads valid data packets from the selected storage division, stores the valid data packets in another storage division of the solid-state storage, and updates a logical index with a new physical address of the valid data.05-14-2009
20090125670ERASE BLOCK MANAGEMENT - An improved Flash memory device with a distributed erase block management (EBM) scheme is detailed that enhances operation and helps minimize write fatigue of the floating gate memory cells of the Flash memory device. The Flash memory device of the invention combines the EBM data in a user data erase block by placing it in an EBM data field of the control data section of the erase block sectors. Therefore distributing the EBM data within the Flash memory erase block structure. This allows the Flash memory to update and/or erase the user data and the EBM data in a single operation, to reduce overhead and speed operation. The Flash memory also reduces the process of EBM data structure write fatigue by allowing the EBM data fields to be load leveled by rotating them with the erase blocks they describe.05-14-2009
20090125673MEMORY CARD AND HOST DEVICE THEREOF - A memory card is attached to a host device, and includes a data control circuit which transfers data with respect to the host device in synchronism with a rise edge and a fall edge of a clock signal.05-14-2009
20100095049HOT MEMORY BLOCK TABLE IN A SOLID STATE STORAGE DEVICE - Solid state storage devices and methods for populating a hot memory block look-up table (HBLT) are disclosed. In one such method, an indication to an accessed page table or memory map of a non-volatile memory block is stored in the HBLT. If the page table or memory map is already present in the HBLT, the priority location of the page table or memory map is increased to the next priority location. If the page table or memory map is not already stored in the HBLT, the page table or memory map is stored in the HBLT at some priority location, such as the mid-point, and the priority location is incremented with each subsequent access to that page table or memory map.04-15-2010
20120166719DATA COPY MANAGEMENT FOR FASTER READS - Multiple copy sets of data are maintained on one or more storage devices. Each copy set includes at least some of the same data units as other sets. Different sets optionally have data units stored in different orders on the storage device(s). A particular one of the sets of data is selected as the set to be accessed in response to detecting a particular scenario.06-28-2012
20120166716METHODS, STORAGE DEVICES, AND SYSTEMS FOR PROMOTING THE ENDURANCE OF NON-VOLATILE SOLID-STATE MEMORY COMPONENTS - Solid-state mass storage devices, host computer systems, and methods of increasing the endurance of non-volatile solid-state memory components used therein. The memory components comprise memory cells organized in functional units that are adapted to receive units of data transferred from the host computer system and correspond to the functional units of the memory component. The level of programming for each cell is reduced by performing an analysis of the bit values of the units of data to be written to at least a first of the functional units of the memory component. Depending on the analysis of “0” and “1” bit values of the units of data to be written, the bit values are inverted before writing the units of data to the first memory component.06-28-2012
20130046917FLASH MEMORY CONTROLLER - A flash memory controller includes a recording medium and a processing circuit. When the amount of stored data in a flash memory module is less than a first threshold, the processing circuit controls a read and write circuit of the flash memory module to program a target data block using program threshold voltages within a first voltage range so as to write data into the target data block. When the amount of stored data in the flash memory module is greater than a second threshold, the processing circuit controls the read and write circuit to program the target data block using program threshold voltages within a second voltage range so as to write data into the target data block, wherein the second threshold is greater than the first threshold and the first voltage range is less than 50% of the second voltage range.02-21-2013
20130046921METHOD OF CONFIGURING NON-VOLATILE MEMORY FOR A HYBRID DISK DRIVE - A system, method and machine-readable medium are provided to configure a non-volatile memory (NVM) including a plurality of NVM modules, in a system having a hard disk drive (HDD) and an operating system (O/S). In response to a user selection of a hybrid drive mode for the NVM, the plurality of NVM modules are ranked according to speed performance. Boot portions of the O/S are copied to a highly ranked NVM module, or a plurality of highly ranked NVM modules, and the HDD and the highly ranked NVM modules are assigned as a logical hybrid drive of the computer system. Ranking each of the plurality of NVM modules can include carrying out a speed performance test. This approach can provide hybrid disk performance using conventional hardware, or enhance performance of an existing hybrid drive, while taking into account relative performance of available NVM modules.02-21-2013
20130046920NONVOLATILE MEMORY SYSTEM WITH MIGRATION MANAGER - Disclosed is a memory system that includes a nonvolatile memory having a main region and a cache region; and a memory controller having migration manager managing a migration operation that moves data from cache region to the main region by referencing a Most Recently Used/Least Recently Used (MRU/LRU) list.02-21-2013
20130046918METHOD WRITING META DATA WITH REDUCED FREQUENCY - A method of writing meta data in a semiconductor storage device in relation to a maximum number of written meta data pages N. The method stores write data in a buffer and loads meta data in a meta memory, writes the write data to the storage medium and updates the meta data. The updated meta data is stored upon determining a number of written meta data pages in an updated meta data region, and only exceeding the maximum number of written meta data pages N, a meta data write operation is performed.02-21-2013
20090119448Memory Apparatus, and Method of Averagely Using Blocks of a Flash Memory - A flash memory controller for averagely using blocks of a flash memory and the method thereof are provided. The flash memory controller is configured to process wear-leveling by allocating frequently updated data in less-erased blocks, and, allocating less-updated data in frequently erased blocks to achieve dynamic uniformity of times of erasion of blocks.05-07-2009
20090119447CONTROLLED BIT LINE DISCHARGE FOR CHANNEL ERASES IN NONVOLATILE MEMORY - Systems and/or methods that facilitate discharging bit lines (BL) associated with memory arrays in nonvolatile memory at a controlled rate are presented. A discharge component facilitates discharging the BL at a desired rate thus preventing the “hot switching” phenomenon from occurring within a y-decoder component(s) associated with the nonvolatile memory. The discharge component can be comprised of, in part, a discharge transistor component that controls the rate of BL discharge wherein the gate voltage of the discharge transistor component can be controlled by a discharge controller component. The rate of BL discharge can be determined by the size of discharge transistor component used in the design, the strength and/or size of the y-decoder component, the number of erase errors that occur for a particular memory device, and/or other factors in order to facilitate preventing hot switching from occurring.05-07-2009
20090119450MEMORY DEVICE, MEMORY MANAGEMENT METHOD, AND PROGRAM - A memory device includes a non-volatile memory which allows data to be written, read, and erased electrically and in which writing and reading are done in units of a page and erasing is done in units of a block including a plurality of pages, and a control section that manages access to the non-volatile memory. The control section performs management of access to the non-volatile memory by performing logical address-physical address translation (logical-physical translation) in translation units (TUs) each being an integer fraction of a size of the block and an integer multiple of a page size.05-07-2009
20090119445COMPUTER MEMORY ACCESSIBLE IN EITHER POWER STATE OF THE COMPUTER - A system on a computer for providing access to data stored on the computer in either power state is provided. The system can include a memory module and an external data interface connector. The system can further include a data interface controller for managing a data interface to the memory module and a data interface to the external data interface connector. The system can further include a multiplexer conductively connecting the data interface controller with the memory module when the computer is powered on, the multiplexer conductively disconnecting the data interface controller from the memory module when the computer is powered off and the multiplexer conductively connecting the external data interface connector with the memory module when the computer is powered on.05-07-2009
20090119444MULTIPLE WRITE CYCLE MEMORY USING REDUNDANT ADDRESSING - The present invention produces a low-cost reliable non-volatile memory with multiple write cycles. The memory circuit trades full configurability for increased reliability and decreased cost by providing a limited number of write or rewrite cycles utilizing an indirectly accessible register set that writes data into fully configurable memory. The circuit is useful for both providing upgrade capability to electronic computational systems and data robustness to logic storage systems. Less configurable non-volatile memory (NVM) block 05-07-2009
20090043951PROGRAMMING SCHEMES FOR MULTI-LEVEL ANALOG MEMORY CELLS - A method for data storage includes storing first data bits in a set of multi-bit analog memory cells at a first time by programming the memory cells to assume respective first programming levels. Second data bits are stored in the set of memory cells at a second time that is later than the first time by programming the memory cells to assume respective second programming levels that depend on the first programming levels and on the second data bits. A storage strategy is selected responsively to a difference between the first and second times. The storage strategy is applied to at least one group of the data bits, selected from among the first data bits and the second data bits.02-12-2009
20090043952MOVING SECTORS WITHIN A BLOCK OF INFORMATION IN A FLASH MEMORY MASS STORAGE ARCHITECTURE - A device is disclosed for storing mapping information for mapping a logical block address identifying a block being accessed by a host to a physical block address, identifying a free area of nonvolatile memory, the block being selectively erasable and having one or more sectors that may be individually moved. The mapping information including a virtual physical block address for identifying an “original” location, within the nonvolatile memory, wherein a block is stored and a moved virtual physical block address for identifying a “moved” location, within the nonvolatile memory, wherein one or more sectors of the stored block are moved. The mapping information further including status information for use of the “original” physical block address and the “moved” physical block address and for providing information regarding “moved” sectors within the block being accessed.02-12-2009
20090043950SEMICONDUCTOR MEMORY STORAGE APPARATUS AND CONTENT DATA MANAGEMENT METHOD - A semiconductor memory storage apparatus includes a packetization unit receiving content data includes a plurality of variable-length frames, and adding management data showing frame data inherent information to frame data of each variable-length frame, and further, packetizing the content data storing the frame data and the management data in each fixed-length packet for every variable-length frame, a buffer temporarily storing the content data at a fixed-length packet unit in write/read operation of the content data packetized at the fixed-length packet unit, a storage unit using a non-volatile memory as an information storage medium, and storing the content data supplied from the buffer, and a controller writing/reading content data packetized at the fixed-length packet unit with respect to the storage unit at a fixed-length packet unit.02-12-2009
20090043948Method and System for Storing Logical Data Blocks Into Flash-Blocks in Multiple Non-Volatile Memories Which Are Connected to At Least One Common Data I/0 Bus - For recording or replaying in real-time digital HDTV signals very fast memories are required. For storage of streaming HD video data NAND flash memory based systems can be used. However, NAND flash memories have a slow write access, and they have unmasked production defects. Write or read operations can be carried out on complete physical data blocks only, and defect data blocks must not be used by the file system. Logical file system blocks are used which are larger than the physical data blocks. According to the invention the error reporting mechanism of the NAND flash memories is exploited. The video data is not only written to the non-volatile flash memories, but is also written to corresponding buffer slots (LFSB) of a volatile SRAM or DRAM memory operating in parallel. The video data are kept in the vola- tile memory until the flash memory holding the respective data has reported that its program or write operation succeeded. Once this has taken place, the data within the volatile memory can be overwritten in order to save memory capacity. If the flash memory has reported an error, the respective block (FSBD) of data is marked bad and will not be overwritten until the end of the entire recorded take has been reached. At this time, the marked video data from the volatile memory are copied to spare flash-blocks within the flash memories.02-12-2009
20090043947MANAGING PROCESSING DELAYS IN AN ISOCHRONOUS SYSTEM - Command cycles incorporate mechanisms to inform a host processor in advance of a need to service the memory so that the host can respond when it suits the host, but in time for the service to be performed before a catastrophic failure. The regular host cycle need not be interrupted for such notification.02-12-2009
20110010492Data Protection for Non-Volatile Semiconductor Memory Using Block Protection Flags - Receiving a request for canceling setting, a control circuit erases data stored in a corresponding block, changes a value of a protection flag, and cancels protection setting. When an overall protection is set for any block, the control circuit prohibits access to all blocks, except when it is an operation mode for activating a memory program contained in the microcomputer. Further, control circuit permits an access to a block M only when partial protection is set, CPU is in the mode for activating a memory program contained in the microcomputer and the access is for reading an instruction code in accordance with an instruction fetch.01-13-2011
20100268864Logical-to-Physical Address Translation for a Removable Data Storage Device - A method for making memory more reliable involves accessing data stored in a removable storage device by translating a logical memory address provided by a host digital device to a physical memory address in the device. A logical memory address is received from the host digital device. The logical memory address corresponds to a location of data stored on the removable storage device. A physical memory address corresponding to the local address is determined by accessing a lookup table corresponding to the logical zone.10-21-2010
20090307416SSD WITH A CONTROLLER ACCELERATOR - In one embodiment, a data storage system includes a solid state data storage device and a memory controller in signal communication with the solid state data storage device. The memory controller includes a processor, a local memory, and an accelerator coupled between the processor and the local memory. The accelerator includes logic circuitry configured to perform data management for the local memory.12-10-2009
20090307415Memory device having multi-layer structure and driving method thereof - A memory device having a multi-layer structure, the memory device includes a first semiconductor layer including at least one memory cell array. The memory cell array includes a plurality of memory cells. A second semiconductor layer is on the first semiconductor layer. The second semiconductor layer includes a bit line and a page buffer connected to the bit line corresponding to the memory cell array. The memory device also includes a contact between the first semiconductor substrate and the second semiconductor substrate to connect the page buffer with the memory cell array.12-10-2009
20090307414MEMORY SYSTEM, MEMORY SYSTEM CONTROL METHOD, AND DRIVE RECORDER APPARATUS - A memory system includes a NAND-type flash memory which includes a plurality of memory cells and can store one-bit, two-bit or more data in one memory cell, and a duplicating-converting circuit configured to duplicate input data by assigning the input data to a predetermined threshold level and another threshold level different from the predetermined threshold level. Moreover, the memory system includes a controller configured to control to store the data duplicated by the duplicating-converting circuit, in the NAND-type flash memory.12-10-2009
20090307412MEMORY MANAGEMENT METHOD FOR NON-VOLATILE MEMORY AND CONTROLLER USING THE SAME - A memory management method for a non-volatile memory and a controller using the same are provided. The non-volatile memory is substantially divided into a plurality of blocks. First, non-erasing information of a plurality of memory units comprising at least one block is recoded and used as a reference to establish an evaluation value. Then, whether to move data of at least one block on the memory units to another memory unit according to the evaluation value is determined. Accordingly, problems of read disturb and data retention due to excessive reading times can be resolved.12-10-2009
20090307411METHOD AND APPARATUS FOR SECURING DIGITAL INFORMATION ON AN INTEGRATED CIRCUIT DURING TEST OPERATING MODES - The embodiments protect an IC against Design-For-Test (DFT) or other test mode attack. Transitory secrets are secured whether stored in registers or latches, RAM, and/or permanent secrets stored in ROM and/or PROM. One embodiment for securing information on an IC includes entering a test mode and resetting each register in response to entering the test mode of operation and prior to receiving a test mode command. An integrated circuit embodiment includes a test control logic operative to configure the integrated circuit into a test mode and to control the integrated circuit while in the test mode, a set of registers, and a functional reset controller coupled to the test control logic and to the set of registers, operative to receive a reset command from the test control logic and provide the reset command to the set of registers in response to a command to enter the test mode.12-10-2009
20120191906FLASH MEMORY MODULE AND STORAGE SYSTEM - A storage controller manages address conversion information denoting the correspondence relationship between a logical address and a physical address of storage area (for example, a physical block) inside a flash memory. The storage controller uses the above-mentioned address conversion information to specify a physical address corresponding to a logical address specified by an I/O request from a higher-level device, and sends an I/O command including I/O-destination information based on the specified physical address to a memory controller inside a flash memory module. The memory controller carries out the I/O with respect to a storage area inside a flash memory specified from the I/O-destination information of the I/O command from the storage controller.07-26-2012
20120191905SEMICONDUCTOR MEMORY CARD ACCESS APPARATUS, A COMPUTER-READABLE RECORDING MEDIUM, AN INITIALIZATION METHOD, AND A SEMICONDUCTOR MEMORY CARD - A predetermined number of erasable blocks positioned at a start of a volume area in a semiconductor memory card are provided so as to include volume management information. A user area following the volume management information includes a plurality of clusters. A data length NOM of an area from a master boot record & partition table sector to a partition boot sector is determined so that the plurality of clusters in the user area are not arranged so as to straddle erasable block boundaries. Since cluster boundaries and erasable block boundaries in the user area are aligned, there is no need to perform wasteful processing in which two erasable blocks are erased to rewrite one cluster.07-26-2012
20120191904SECONDARY CACHE FOR WRITE ACCUMULATION AND COALESCING - A method for efficiently using a large secondary cache is disclosed herein. In certain embodiments, such a method may include accumulating, in a secondary cache, a plurality of data tracks. These data tracks may include modified data and/or unmodified data. The method may determine if a subset of the plurality of data tracks makes up a full stride. In the event the subset makes up a full stride, the method may destage the subset from the secondary cache. By destaging full strides, the method reduces the number of disk operations that are required to destage data from the secondary cache. A corresponding computer program product and apparatus are also disclosed herein.07-26-2012
20120191903STORAGE APPARATUS AND METHOD OF MANAGING DATA STORAGE AREA - To extend endurance and reduce bit cost, a storage apparatus includes a controller and a first storage device and a second storage device having a smaller erase count upper limit than the first storage device. Area conversion information includes correspondence of a first address of a data storage destination and a second address of a data storage area The controller selects an area corresponding to the first address, determines whether a rewrite frequency of the selected area is equal to or larger than a first threshold and, when the rewrite frequency is equal to or larger than the threshold, selects an area of the first storage device, and, when the rewrite frequency is smaller than the threshold, selects an area of the second storage device and maps the address of the selected area to the first address.07-26-2012
20120191902One-Die Flotox-Based Combo Non-Volatile Memory - A memory access apparatus that controls access to at least one memory array has an array of programmable comparison cells that retain a programmed pass code and compare it with an access pass code. When there is a match between the access pass code and the programmed pass code, the memory access apparatus generates a match signal for allowing access to the at least one memory array. If there is no match, the data within the at least one memory array may be corrupted or destroyed. Each nonvolatile comparison cell has a pair of series connected charge retaining transistors. The programmed pass code is stored in the charge retaining transistors. Primary and complementary query pass codes are applied to the charge retaining transistors and are logically compared with the stored pass code and based on the programmed threshold voltage levels determine if the query pass code is correct.07-26-2012
20120191901METHOD AND APPARATUS FOR MEMORY MANAGEMENT - One or more circuits of a device may comprise a memory. A first portion of a first block of the memory may store program code and/or program data, a second portion of the first block may store an index associated with a second block of the memory, and a third portion of the first block may store an indication of a write status of the first portion. Each bit of the third portion of the first block may indicate whether an attempt to write data to a corresponding one or more words of the first portion of the first block has failed since the last erase of the corresponding one or more words of the first portion of the first block. Whether data to be written to a particular virtual address is written to the first block or the second block may depend on the write status of the first block and the second block.07-26-2012
20120191900MEMORY MANAGEMENT DEVICE - A memory management device of an example of the invention controls writing into and reading from a main memory including a nonvolatile semiconductor memory and a volatile semiconductor memory in response to a writing request and a reading request from a processor. The memory management device includes a coloring information storage unit that stores coloring information generated based on a data characteristic of write target data to be written into at least one of the nonvolatile semiconductor memory and the volatile semiconductor memory, and a writing management unit that references the coloring information to determines a region into which the write target data is written from the nonvolatile semiconductor memory and the volatile semiconductor memory.07-26-2012
20120191899Flexible Memory Protection and Translation Unit - A memory management and protection system that manages memory access requests from a number of requestors. Memory accesses are allowed or disallowed based on the privilege level of the requestor, based on a Privilege Identifier that accompanies each memory access request. An extended memory controller selects the appropriate set of segment registers based on the Privilege Identifier to insure that the request is compared to and translated by the segment register associated with the requestor originating the request. A set of mapping registers allow flexible mapping of each Privilege Identifier to the appropriate access permission. The segment registers translate the logical address from the requestor to a physical address within a larger address space.07-26-2012
20120191898DDR FLASH IMPLEMENTATION WITH DIRECT REGISTER ACCESS TO LEGACY FLASH FUNCTIONS - A Double Data Rate (DDR) nonvolatile memory for use with a wireless device. A host processor transfers commands and data through a DDR interface of the nonvolatile memory. The DDR nonvolatile memory implements legacy flash functions while maintaining DDR behavior.07-26-2012
20120191897NON-VOLATILE MEMORY SYSTEM AND MANAGEMENT METHOD THEREOF - A non-volatile memory system includes a memory area including a plurality of non-volatile memory blocks, and a micro control unit configured to manage the memory blocks as a data block and a buffer block. As a write command is input, if no buffer block assigned to the data block exists and a free page exists in the data block, the micro control unit converts the data block to a self-buffer block.07-26-2012
20130073794MEMORY SYSTEM AND CONTROL METHOD THEREOF - According to one embodiment, a memory system includes a storage unit including a buffer and a nonvolatile first memory, and a first controller which includes a processor and a volatile second memory, and in which the processor controls the storage unit based on data stored in the second memory, and issues a first command when switching from a normal state to a standby state. The memory system also includes a second controller which issues a second command for reading data from the first memory to the buffer, based on the first command, and issues a third command for reading the data from the buffer and storing the data in the second memory, when the first controller switches from the standby state to the normal state.03-21-2013
20130073792ELECTRONIC APPARATUS USING NAND FLASH AND MEMORY MANAGEMENT METHOD THEREOF - An electronic apparatus using NAND flash memory and a memory management method thereof are provided. The electronic apparatus uses the NAND flash memory to record data in the system memory. In the present method, when a standby instruction is received, a fast flash standby (FFS) procedure is initiated, and a state of the NAND flash memory is checked to determine whether the NAND flash memory is suitable for recording the data in the system memory. If the state is determined as suitable for recording the data, the data in the system memory is copied to the NAND flash and the operating system of the electronic apparatus is controlled to enter a hibernate mode. On the contrary, if the state is determined as not suitable for recording the data, the operating system of the electronic apparatus is controlled to enter a standby mode.03-21-2013
20130073791MAGNETIC RANDOM ACCESS MEMORY WITH DYNAMIC RANDOM ACCESS MEMORY (DRAM)-LIKE INTERFACE - A memory device includes a magnetic memory unit for storing a burst of data during burst write operations, each burst of data includes, sequential data units with each data unit being received at a clock cycle, and written during a burst write operation, wherein the burst write operation is performed during multiple clock cycles. Further, the memory device includes a mask register coupled to the magnetic memory unit that generates a write mask during the burst write operation to inhibit or enable data units of write data, furthermore the memory device allowing burst write operation to begin while receiving data units of the next burst of data to be written or providing read data.03-21-2013
20130073790MAGNETIC RANDOM ACCESS MEMORY WITH BURST ACCESS - A memory device which includes a magnetic memory unit for storing a burst of data during burst write operations, each burst of data includes, sequential data units with each data unit being received at a clock cycle, and written during a burst write operation, wherein the burst write operation is performed during multiple clock cycles. Further, the memory device includes a mask register coupled to the magnetic memory unit that generates a write mask during the burst write operation to inhibit or enable write of the data units of the burst of data, the memory device allowing a next burst write or read command to begin before the completion of the burst write operation and while receiving data units of the next burst of data to be written or providing read data.03-21-2013
20130073801TECHNIQUES TO STORE CONFIGURATION INFORMATION IN AN OPTION READ-ONLY MEMORY - Method and apparatus to store configuration information in an option read-only memory are described.03-21-2013
20130073800Multipage Preparation Commands For Non-Volatile Memory Systems - Multipage preparation commands for non-volatile memory systems are disclosed. The multipage preparation commands supply data that can be used to prepare a non-volatile memory device for forthcoming multipage program operations. A host controller can use the commands ahead of a multipage program operation to optimize usage of a multipage program command. The non-volatile memory device can use the commands to configure the non-volatile memory in preparation for a subsequent operation, such as changing a command order or using the most optimized command set for the subsequent operation.03-21-2013
20130073789SYSTEMS AND METHODS FOR CONFIGURING NON-VOLATILE MEMORY - Systems and methods are disclosed for configuring a non-volatile memory (“NVM”). In some embodiments, each block of the NVM can include a block table-of-contents (“TOC”), which can be encoded (e.g., run-length encoded) and dynamically-sized. Thus, as user data is being programmed to a block, the size of a block TOC can be concurrently recalculated and increased only if necessary. In some embodiments, the NVM interface can use a weave sequence stored in the context information and at least one weave sequence associated with each page of a block to determine whether to replay across the pages of the block after system boot-up.03-21-2013
20130073799Electronic Control Unit for Vehicle and Method of Writing Data - An electronic control unit for a vehicle including a nonvolatile memory capable of erasing and writing data electrically and two buffers to acquire, by communication, divided data obtained by dividing a program by predetermined size. Then, in parallel with using the two buffers alternately to receive divided data, the electronic control unit for a vehicle uses one buffer that is not used to receive divided data to write the received divided data into the nonvolatile memory.03-21-2013
20130073798FLASH MEMORY DEVICE AND DATA MANAGEMENT METHOD - Disclosed is a data management method for a flash storage device. The method includes collecting cold data stored in the flash memory device with reference to a cold list table, compressing the collected cold data, and then storing the compressed cold data in the flash memory.03-21-2013
20130073795MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME - According to one embodiment, a memory device includes a nonvolatile memory in which data write or data read is executed in units of a plurality of cells, and a controller configured to control the memory and to manage a memory space of the memory by dividing the memory space into a plurality of partitions.03-21-2013
20090094411NAND FLASH CONTROLLER AND DATA EXCHANGE METHOD BETWEEN NAND FLASH MEMORY AND NAND FLASH CONTROLLER - The invention discloses a NAND flash controller, including a command and address data transmission channel adapted to connect the bus timing interface with the channel selector and transmit command and address data, a data buffer region adapted to receive message data from the bus timing interface through system bus, a control register adapted to receive an operation parameter configured through system bus via the bus timing interface, a logic controller adapted to write the data information into or read the data information from the data buffer region according to the operation parameter, a channel selector adapted to connect the DMA data transmission channel or the command and address data transmission channel according to the operation parameter for transmitting data. The invention also discloses a date exchange method between NAND flash controller and NAND flash memory. The invention improves the data transmission efficiency and is compatible with various NAND flash memories.04-09-2009
20090094408MEMORY WRITING DEVICE - After power-on, the start-up of a CPU 04-09-2009
20090094407Non-volatile memory device having assignable network identification - Memory devices and methods disclosed such as memory devices that include a network identification that uniquely identifies the memory device on a network. The memory device can then receive memory commands that include the network identification. The memory device can also generate memory commands, including the network identification, for broadcast over the network.04-09-2009
20110302363NON-VOLATILE MEMORIES, CARDS, AND SYSTEMS INCLUDING SHALLOW TRENCH ISOLATION STRUCTURES WITH BURIED BIT LINES - A non-volatile memory device can include a buried bit line in a substrate of a non-volatile memory device and a self-aligned shallow trench isolation region in the substrate that is self-aligned to the buried bit line.12-08-2011
20130073797MEMORY DEVICE - According to one embodiment, a memory device includes a nonvolatile memory and a command storage module in which a command is stored. The memory device further comprises a memory module in which a type of a background process and an order of priority of the background process are set, in which information of a necessary background process is set, and in which permission or refusal of the background process is set by a host device.03-21-2013
20130073796MEMORY CONTROLLER - According to one embodiment, a memory controller includes a first interface, a second interface, and a control module. The first interface transmits and receives a signal to and from a host. The second interface transmits and receives a signal to and from a nonvolatile semiconductor memory. The control module reserves a spare area in the semiconductor memory in response to a first command received by the first interface and writes update data into the spare area when updating data in the semiconductor memory. Size of the spare area is available according to the first command.03-21-2013
20130073793MEMORY DEVICE - According to one embodiment, a memory device includes a nonvolatile memory which stores data in units of a write unit includes cells, and a controller which controls the memory and partitions memory space of the memory. In response to a request to write write-data to the memory from a host, the controller requests the host to transmit a segment of the write-data with a specified size. The write-data segment has a size of an integral multiple of a size determined to allow for a set of the write-data segment and corresponding additional data to be the largest while smaller than the write unit. Before completion of processing a first command which requests access to a first partition, the controller accepts a second command which requests access to a second partition.03-21-2013
20130073788WEAVE SEQUENCE COUNTER FOR NON-VOLATILE MEMORY SYSTEMS - Systems and methods are disclosed for providing a weave sequence counter (“WSC”) for non-volatile memory (“NVM”) systems. The WSC can identify the sequence in which each page of the NVM is programmed. The “weave” aspect can refer to the fact that multiple blocks can be open for programming at once, thus allowing the pages of these blocks to be programmed in a “woven” manner. Systems and methods are also disclosed for providing a host weave sequence counter (“HWSC”). Each time new data is initially programmed to the NVM, this data can be associated with a particular HWSC. The HWSC associated with the data may not change, even when the data is moved to a new page (e.g., for wear leveling purposes and the like). The WSC and HWSC may aid in, for example, performing rollback, building logical-to-physical mappings, determining static-versus-dynamic page statuses, and performing maintenance operations (e.g., wear leveling).03-21-2013
20130073787FASTER TREE FLATTENING FOR A SYSTEM HAVING NON-VOLATILE MEMORY - Systems and methods are disclosed for efficient buffering for a system having non-volatile memory (“NVM”). A tree can be stored in volatile memory that includes a logical-to-physical mapping between a logical space and physical addresses of the NVM. When the amount of memory available for the tree is below a pre-determined threshold, a system can attempt to reduce the number of data fragments in the NVM, and consequently flatten a portion of the tree. The NVM interface may select an optimal set of entries of the tree to combine. Any suitable approach can be used such as, for example, moving one or more sliding windows across the tree, expanding a sliding window when a condition has been satisfied, using a priority queue while scanning the tree, and/or maintaining a priority queue while the tree is being updated.03-21-2013
20130073786APPARATUS, SYSTEM, AND METHOD FOR IMPROVING READ ENDURANCE FOR A NON-VOLATILE MEMORY - Described are an apparatus, system, and method for improving read endurance for a non-volatile memory (NVM). The method comprises: determining a read count corresponding to a block of NVM; identifying whether the block of NVM is a partially programmed block (PPB); comparing the read count with a first threshold when it is identified that the block is a PPB; and when identified otherwise, comparing the read count with a second threshold, wherein the first threshold is smaller than the second threshold. The method further comprises: identifying a block that is a PPB; determining a first word line corresponding to un-programmed page of the PPB; and sending the first word line to the NVM, wherein the NVM to apply: a first read voltage level to word lines corresponding to the un-programmed pages of the PPB, and a second read voltage level to word lines corresponding to programmed pages of the PPB.03-21-2013
20130073785RETENTION MANAGEMENT FOR PHASE CHANGE MEMORY LIFETIME IMPROVEMENT THROUGH APPLICATION AND HARDWARE PROFILE MATCHING - Methods and systems for managing memory and stress to memory systems. A method for managing memory includes receiving from a software application memory retention requirements for application data. The memory retention requirements include storage duration length and/or criticality of data retention. The method also includes storing the application data in one of a plurality of memory regions in non-volatile memory based on the memory retention requirements and memory retention characteristics of the memory regions. Each memory region may have different memory retention characteristics.03-21-2013
20130073784METHOD AND SYSTEM FOR RANDOM WRITE UNALIGNMENT HANDLING - A method and system are disclosed for handling host write commands associated with both data aligned with physical page boundaries of parallel write increments in non-volatile storage areas in a non-volatile storage device and data unaligned with the physical page boundaries. The method may include a controller of a storage device identifying the aligned and unaligned portions of received data, temporarily storing the aligned and unaligned portions in different queues, and then writing portions from the unaligned data queue or the aligned data queue in parallel to the non-volatile memory areas when one of the queues has been filled with a threshold amount of data or when the controller detects a timeout condition. The system may include a storage device with a controller configured to perform the method noted above, where the non-volatile memory areas may be separate banks and the queues are random access memory.03-21-2013
20130073783HYBRID DATA STORAGE MANAGEMENT TAKING INTO ACCOUNT INPUT/OUTPUT (I/O) PRIORITY - A method uses a record of I/O priorities in a determination of a storage medium of a hybrid storage system in which to store a file. The method maintains the record of I/O priorities by assigning an I/O temperature value to each request for access to the file based upon an I/O priority level of the process making the request. The method marks the file as hot if the file temperature value is greater than a threshold value. The method stores files marked as hot in a lower latency storage medium of the hybrid storage medium.03-21-2013
20100332734FLASH MEMORY DEVICES AND METHODS FOR CONTROLLING A FLASH MEMORY DEVICE - A flash memory device includes a memory array and a memory control circuit. The memory array includes memory modules. Each memory module is located in a memory channel and includes a predetermined number of memory cells. The memory control circuit is coupled to the memory array via an address latch enable (ALE) pin and a command latch enable (CLE) pin. The ALE pin and the CLE pin are coupled to all of the memory cells and shared by all of the memory cells in the memory array.12-30-2010
20100106890METHOD AND APPARATUS FOR ENFORCING A FLASH MEMORY CACHING POLICY - Methods, apparatus and computer medium for enforcing one or more cache management policies are disclosed herein. In some embodiments, a flash memory of a storage device includes a plurality of flash memory dies each flash memory die including a respective cache storage area and a respective main storage area. A determination is made, for data that is received from an external host device to which main storage area the received data is addressed thereby specifying one of the plurality of flash memory dies as a target die for the received data. Whenever the received data is written into a cache storage area before being written into a main storage area, the received data is written into the cache storage area of the specified target die.04-29-2010
20130060993STORAGE DEVICE AND STREAM FILTERING METHOD THEREOF - A storage device may include a main storage part including one or more memories; and a controller configured to control an overall operation of the main storage part. The controller includes a filter manager configured to store data format information and a filtering condition provided from a host; one or more stream filters configured to search and project data stored in the one or more memories in parallel in response to a control of the filter manager to produce searched and projected data; and a merge filter configured to merge the searched and projected data of the one or more stream filters in response to the control of the filter manager.03-07-2013
20130060995MEMORY DEVICE, HOST DEVICE, MEMORY SYSTEM, MEMORY DEVICE CONTROL METHOD, HOST DEVICE CONTROL METHOD AND MEMORY SYSTEM CONTROL METHOD - A memory card 03-07-2013
20130060994NON-VOLATILE MEMORY MANAGEMENT SYSTEM WITH TIME MEASURE MECHANISM AND METHOD OF OPERATION THEREOF - A method of operation of a non-volatile memory management system includes: selecting a specific time period by a unit controller; establishing a first time pool having super blocks written during the specific time period; and promoting to a second time pool, the super blocks from the first time pool, at the lapse of the specific time period.03-07-2013
20130060989APPARATUS, SYSTEM, AND METHOD FOR REFERENCING DATA BLOCK USAGE INFORMATION BY WAY OF AN INTERFACE - An apparatus, system, and method are disclosed for data management. The method includes referencing data block usage information provided by way of an interface operable to communicate with a storage controller managing non-volatile storage media. The method also includes identifying to the storage controller one or more blocks for deallocation by the data block usage information.03-07-2013
20130060992DATA COMPRESSION METHOD - A data compression method includes; generating compressed data from raw data having a normal size, defining a super page for a memory having a super size greater than the normal size, selecting a compressed data set from among the compressed data having a compression ratio less than a reference compression ratio ranging between 0.5 and 1.0, and storing the compressed data set in the memory using the super page.03-07-2013
20130060991SOLID STATE DRIVE AND GARBAGE COLLECTION CONTROL METHOD THEREOF - A garbage collection control method for a solid state drive is provided. The garbage collection control method includes the following steps. Firstly, a total number of releasable spaces in a plurality of data-containing blocks of a flash memory is calculated and defined as A. A total number of spaces in a plurality of blank blocks of the flash memory is calculated and defined as B. If the ratio B/A is smaller than a first threshold value, a garbage collection is performed. During the garbage collection is performed, if the ratio B/A is larger than a second threshold value, the garbage collection is ended. The first threshold value is smaller than the second threshold value.03-07-2013
20130060990DATA MOVING METHOD FOR FLASH MEMORY MODULE, AND MEMORY CONTROLLER AND MEMORY STORAGE APPARATUS USING THE SAME - A method of moving a first portion of data and a second portion of data, which belong to one page data and respectively stored in a second physical page and a third physical page, into a first physical page in a flash memory module is provided. The method includes transmitting a read command for reading page data stored in the second physical page; reading the first portion of data from a buffer area of the rewritable non-volatile memory module into a buffer memory; transmitting a read command for reading page data stored in the third physical page; transmitting the first portion of data from the buffer memory to the buffer area; and transmitting a write command for writing data stored in the buffer area into the first physical page. Accordingly, the method can effectively move one page data dispersedly stored in different physical pages into one physical page.03-07-2013
20130097367APPARATUS, SYSTEM, AND METHOD FOR SOLID-STATE STORAGE AS CACHE FOR HIGH-CAPACITY, NON-VOLATILE STORAGE - An apparatus, system, and method are disclosed for solid-state storage as cache for high-capacity, non-volatile storage. The apparatus, system, and method are provided with a plurality of modules including a cache front-end module and a cache back-end module. The cache front-end module manages data transfers associated with a storage request. The data transfers between a requesting device and solid-state storage function as cache for one or more HCNV storage devices, and the data transfers may include one or more of data, metadata, and metadata indexes. The solid-state storage may include an array of non-volatile, solid-state data storage elements. The cache back-end module manages data transfers between the solid-state storage and the one or more HCNV storage devices.04-18-2013
20090271568FLASH MEMORY SYSTEM AND DATA WRITING METHOD THEREOF - Provided are a flash memory system and a data reading method thereof, the method including serially reading groups of data and parity codes corresponding to each of the respective groups from a page buffer; calculating the parity for each serially read group; checking for errors in each serially read group by comparing each calculated parity with a corresponding serially read parity code, respectively; and providing an output signal indicative of any comparative parity errors detected, wherein the reading of each group of data is followed by the reading of the parity code for the group, and the checking for errors in each group of data is done during the serial reading operation.10-29-2009
20090271566METHOD FOR CONFIGURING OR RE-CONFIGURING PROGRAMMABLE DEVICE AND APPARATUS ASSOCIATED THEREWITH - A method of configuring a programmable device may include connecting an electronic storage medium to a configuration system with user-friendly input/output capabilities to establish configuration information for the programmable device, which may have limited input/output capabilities. The configuration information may be applied to the programmable device when the electronic storage medium is connected to the programmable device. Additional programmable devices may be configured when connected to the electronic storage medium. Further embodiments of the method and apparatus to provide the programmable device configuration service are also provided.10-29-2009
20090271564STORAGE SYSTEM - A storage system has a storage controller and a flash memory module that is coupled to the storage controller. The storage controller manages the status of a storage area in a flash memory chip of the flash memory module. When a portion of the storage area in the flash memory chip becomes unwritable, the storage controller carries out control so as to use a free storage area as an alternate area for the unwritable storage area, and to store data that has been stored in the unwritable storage area, in the alternate area.10-29-2009
20090271563FLASH MEMORY TRANSACTIONING - Providing for improved transactioning for Flash memory is described herein. By way of example, transactioning operations associated with abstract data structures can be bundled into a common layer of a Flash management protocol stack, to reduce transaction redundancy at abstracted layers. In some aspects, the common layer can be a block level layer providing relatively direct access to low level Flash. Thus, a file system or database application, operating at a higher, abstracted layer of the Flash management protocol stack, can offload transactioning operations to a block level process that has access to underlying Flash memory. As a result, increased efficiency, throughput, and added flexibility can be achieved for storage system transactioning.10-29-2009
20090271562Method and system for storage address re-mapping for a multi-bank memory device - A method and system for storage address re-mapping in a multi-bank memory is disclosed. The method includes allocating logical addresses in blocks of clusters and re-mapping logical addresses into storage address space, where short runs of host data dispersed in logical address space are mapped in a contiguous manner into megablocks in storage address space. Independently in each bank, valid data is flushed within each respective bank from blocks having both valid and obsolete data to make new blocks available for receiving data in each bank of the multi-bank memory when an available number of new blocks falls below a desired threshold within a particular bank.10-29-2009
20090271561MEDIUM FOR INTEGRATING STORING CAPACITIES OF MULTIPLE STORAGE DEVICES - A medium for integrating storing capacities of multiple storage devices has multiple memory card connectors, a memory card interface management module, a control module and a communication interface. Each memory card connector is used to connect to a memory card. The memory card interface management module is connected to the memory card connectors. The control module is connected to the memory card interface management module and stores a mount and unmount management process. The control module executes the mount and unmount management process to integrate storing capacities of all connected memory cards into a single storing capacity and unintegrate the storing capacity of the impendingly removed memory cards from the storing capacity of all connected memory cards. The communication interface is used to connect to a computer. Therefore, it is convenient for users to change the storing capacity of the medium based on different requirements.10-29-2009
20090271560Dynamic Fix-Up of Global Variables During System BIOS Execution - A method is described for preserving the flexibility associated with relative memory addressing in programs designed to be stored in read-only memory.10-29-2009
20090271559Method for Storing Individual Data Items of a Low-Voltage Switch - A method is disclosed for storing individual data items of a low-voltage switch provided with a microcontroller triggering unit. According to an embodiment, the ROM cells of a dead microcontroller ROM which are not occupied by a program code memory cells are occupied by the individual data items of the low-voltage switch.10-29-2009
20090070521WRITE ABORT AND ERASE ABORT HANDLING - A portion of a nonvolatile memory array that is likely to contain, partially programmed data may be identified from a high sensitivity read, by applying stricter than usual ECC requirements, or using pointers to programmed sectors. The last programmed data may be treated as likely to be partially programmed data. Data in the identified portion may be copied to another location, or left where it is with an indicator to prohibit further programming to the same cells. To avoid compromising previously stored data during subsequent programming, previously stored data may be backed up. Backing up may be done selectively, for example, only for nonsequential data, or only when the previously stored data contains an earlier version of data being programmed. If a backup copy already exists, another backup copy is not created. Sequential commands are treated as a single command if received within a predetermined time period.03-12-2009
20130067154ELECTRONIC FLASH MEMORY EXTERNAL STORAGE METHOD AND DEVICE - An electronic flash memory external storage method and device for data processing system includes firmware which directly controls the access of electronic storage media and implements standard interface functions, adopts particular reading and writing formats of the external storage media, receives power via USB, externally stores data by flash memory and access control circuit with the cooperation of the firmware and the driver with the operating system, and has write-protection so that the data can be safely transferred. The method according to present invention is highly efficient and all parts involved are assembled as a monolithic piece so that it has large-capacity with small size and high speed. The device operates in static state and is driven by software. It is plug-and-play and adapted to data processing system.03-14-2013
20130067153HARDWARE BASED WEAR LEVELING MECHANISM - A memory system is provided. The system includes a controller that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the controller to regulate read and write access to the one or more FLASH devices. Wear leveling components along with read and write processing components are provided to facilitate efficient operations of the FLASH memory devices.03-14-2013
20130067152STORAGE SYSTEM - The temporary area capacity required to be secured with respect to the whole permanent area is calculated in accordance with the capacity and access frequency of a host computer data permanent area of a disk device contained in the storage system and a disk device of an external storage device that is managed by a storage virtualization function of this storage system. The nonvolatile memory is defined as the temporary area and is used to temporarily store host computer data when a data I/O from the host computer is processed. The required capacity of the temporary area is re-calculated in accordance with an event such as a configuration change in the external storage system.03-14-2013
20130067151METHOD FOR EFFICIENT STORAGE OF METADATA IN FLASH MEMORY - A method includes writing a first portion of received user data to a first page of a block of a memory according to a writing schedule and writing a subsequent portion of the received user data to another page of the block according to the writing schedule. The method includes storing first metadata corresponding to writing the first portion in the memory. The method further includes associating the first metadata with the subsequent portion.03-14-2013
20130067146MEMORY DEVICE, CONTROL METHOD FOR THE MEMORY DEVICE, AND CONTROLLER - During normal power operation, an erased free block is prepared in nonvolatile memory so that at least one erased free block is continuously available as a standby block. If a power failure occurs, volatile data and its address conversion information are written into the standby block in the nonvolatile memory.03-14-2013
20130067150DATA PROCESSOR WITH FLASH MEMORY, AND METHOD FOR ACCESSING FLASH MEMORY - A data processor includes a flash memory, a random access memory (RAM), and a controller that creates free space information of the flash memory, creates record data according to each of a read latest data of the flash memory, and stores the free space information and the record data into the RAM.03-14-2013
20130067149NON-VOLATILE CACHE - A method for managing a storage device including determining whether the storage device includes a non-volatile cache, scanning for a clear cache instruction received from a computing machine, and clearing the non-volatile cache on the storage device in response to authenticating the clear cache instruction.03-14-2013
20130067148INFORMATION PROCESSING APPARATUS AND INFORMATION PROCESSING METHOD - An information processing apparatus includes an assignment unit and a determination unit. The assignment unit evaluates physical properties of each of a plurality of semiconductor memories constituting one storage device as a whole and assigns a usage attribute corresponding to an evaluation result to at least a part of the plurality of semiconductor memories. The determination unit determines a semiconductor memory having an optimal usage attribute as a write destination of data with respect to a write command of the data.03-14-2013
20130067147STORAGE DEVICE, CONTROLLER, AND READ COMMAND EXECUTING METHOD - A storage device of the embodiment includes memory, a control section, a table holding section for managing a table for holding an identifier, a logical address, and a data length based on a read command, an issuing section for issuing the logical address and the data length for each identifier to the control section, a buffer for holding data received from the memory along with the identifier, and an identifier queue for receiving the identifier of a number proportional to a data length when the data of the logical address of the same identifier is received in the buffer. The storage device of the embodiment includes a transfer section for transferring the data corresponding to the identifier received in the buffer to outside when the identifier is held as incomplete readout in the table in order from the identifier at a head of the identifier queue.03-14-2013
20130067144CONTROLLER FOR STORAGE APPARATUS AND CONTROLLING METHOD FOR STORAGE APPARATUS - According to one embodiment, a controller for a storage apparatus is disclosed having interfaces connectable to a host system, a first storage apparatus and a second storage apparatus. A data in the first storage apparatus and a data in the second storage apparatus are duplicates. A status table stores the operating state regarding the first storage apparatus and the second storage apparatus, wherein the operating state indicates among writing, reading, or standing by. A monitor monitors the interfaces and set up the operating state into the status table. A buffer memory buffers the data for writing in the first storage apparatus and the second storage apparatus. A command response unit receives the data for writing and write-in request from a host system, and directs the writing of the data to the first storage apparatus and the second storage apparatus while making the buffer memory buffer the received data.03-14-2013
20130067143MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME - According to one embodiment, a memory device includes a nonvolatile memory, a command storage module in which a command is stored, and a controller which receives the command from a host device, stores the command in the command storage module, executes the command stored in the command storage module, and after having completed the execution of the command, transmits, to the host device, a first signal reporting the completion of the execution of the command.03-14-2013
20130067142FLASH MEMORY STORAGE DEVICE AND METHOD OF JUDGING PROBLEM STORAGE REGIONS THEREOF - A method of judging problem storage regions adapted for a flash memory storage device includes steps of: sending a writing order to a flash memory chip for writing a written data to an appointed storage paging; when the flash memory chip beginning writing the written data to the appointed storage paging, getting the first time; when the flash memory chip finishing writing the written data to the appointed storage paging, getting the second time; calculating a writing time according to the first time and the second time; if the writing time not coincident with a standard value, then labeling the appointed storage paging as a problem storage region and copying the written data to a backup paging; updating a Mapping Table.03-14-2013
20130067141DATA WRITING METHOD, AND MEMORY CONTROLLER AND MEMORY STORAGE APPARATUS USING THE SAME - A data writing method for a rewritable non-volatile memory module is provided. The rewritable non-volatile memory module has a plurality of lower physical pages and a plurality of upper physical pages respectively corresponding to the lower physical pages. The method includes determining whether a physical page is one of the upper physical pages before writing first data into the physical page; determining whether a backup area stores second data written into one of the lower physical pages corresponding to the physical page if the physical page is the upper physical page; reading the second data from the lower physical page corresponding to the physical page and backing up the second data into the backup area before writing the first data into the physical page when the backup area does not store the second data. Accordingly, the method may effectively prevent data loss due to a program failure.03-14-2013
20130067145MEMORY DEVICE, MEMORY SYSTEM, AND METHOD OF STORING DATA USING THE SAME - Provided is a memory device configured to store data having a first characteristic and a second characteristic in a memory region optimized to store data having the first characteristic and the second characteristic. The memory device includes a plurality of memory regions and a region determination unit configured to receive data, select a memory region appropriate for storing the received data, and store the data in the selected memory region. Correspondingly, performance degradation of the memory device may be prevented.03-14-2013
20130067140DATA MODIFICATION BASED ON MATCHING BIT PATTERNS - A data storage device includes a memory and a controller. The controller is configured to identify groups of bits that match any bit pattern in a first set of bit patterns. Each of the groups of bits includes a first bit of first data, a second bit of second data, and a third bit of third data to be stored at the memory. The controller is configured, in response to determining that a count of the identified groups exceeds a threshold, to change multiple bits of the first data. Changing the multiple bits of the first data reduces a number of the groups of bits that match any bit pattern in the first set of bit patterns.03-14-2013
20130067139STORAGE SYSTEM COMPRISING FLASH MEMORY, AND STORAGE CONTROL METHOD - A storage system comprises a plurality of flash packages comprising a plurality of flash chips, and a storage controller for receiving a first write request from a higher-level apparatus and sending a second write request of write data based on data conforming to this first write request to a write-destination flash package, and demonstrates a capacity virtualization function for causing a storage capacity to appear larger than an actual storage capacity for the higher-level apparatus, and for configuring a storage space using page units. The storage system generates a second VOL (logical volume) based on a first VOL, manages a plurality of VOLs comprising the first VOL and one or more second VOLs generated based on the first VOL as a VOL group, and allocates the same page to areas of the same address of the plurality of VOLs configuring the VOL group.03-14-2013
20130067138NON-VOLATILE MEMORY-BASED MASS STORAGE DEVICES AND METHODS FOR WRITING DATA THERETO - A non-volatile solid state memory-based mass storage device having at least one non-volatile memory component and methods of operating the storage device. In one aspect of the invention, the one or more memory components define a memory space partitioned into user memory and over-provisioning pools based on a P/E cycle count stored in a block information record. The storage device transfers the P/E cycle count of erased blocks to a host and the host stores the P/E cycle count in a content addressable memory. During a host write to the storage device, the host issues a low P/E cycle count number as a primary address to the content addressable memory, which returns available block addresses of blocks within the over-provisioning pool as a first dimension in a multidimensional address space. Changed files are preferably updated in append mode and the previous version can be maintained for version control.03-14-2013
20130067137SYSTEMS AND METHODS FOR USING RESERVED SOLID STATE NONVOLATILE MEMORY STORAGE CAPACITY FOR SYSTEM REDUCED POWER STATE - Systems and methods that may be implemented to utilize the same portion of solid state nonvolatile memory for both managing system running data during a system working state and to store previous working state data written from system volatile memory during a low power state when the system volatile memory is depowered. The previous working state information may include data and instructions that may be employed to restore the previous working state of the information handling system prior to entering the low power state and terminating power to the system volatile memory.03-14-2013
20130067136Administering Thermal Distribution Among Memory Modules Of A Computing System - A computing system includes a number of memory modules and temperature sensors. Each temperature sensor measures a temperature of a memory module. In such a computing system a garbage collector during garbage collection, determines whether a temperature measurement of a temperature sensor indicates that a memory module is overheated and, if a temperature measurement of a temperature sensor indicates a memory module is overheated, the garbage collector reallocates one or more active memory regions on the overheated memory module to a non-overheated memory module. Reallocating the active memory regions includes copying contents of the active memory regions from the overheated memory module to the non-overheated memory module.03-14-2013
20120117317ATOMIC MEMORY DEVICE - In an integrated-circuit memory device having a memory core, a first data value is retrieved from an address-specified location within the memory core in response to a memory access command. The first data value is output from the memory device in response to the memory access command, and a second data value is stored in the address-specified location within the memory core in response to the memory access command.05-10-2012
20110022789MEMORY DEVICE, HOST DEVICE, MEMORY SYSTEM, MEMORY DEVICE CONTROL METHOD, HOST DEVICE CONTROL METHOD AND MEMORY SYSTEM CONTROL METHOD - A memory card 01-27-2011
20110022788INTEGRATING DATA FROM SYMMETRIC AND ASYMMETRIC MEMORY - Data stored within symmetric and asymmetric memory components of main memory is integrated by identifying a first data as having access characteristics suitable for storing in an asymmetric memory component. The first data is included among a collection of data to be written to the asymmetric memory component. An amount of data is identified within the collection of data to be written to the asymmetric memory component. The amount of data is compared within the collection of data to a volume threshold to determine whether a block write to the asymmetric memory component is justified by the amount of data. If justified, the collection of data is loaded to the asymmetric memory component.01-27-2011
20110022787DATA WRITING METHOD FOR NON-VOLATILE MEMORY AND CONTROLLER USING THE SAME - A data writing method for a non-volatile memory is provided, wherein the non-volatile memory includes a data area and a spare area. In the data writing method, a plurality of blocks in a substitution area of the non-volatile memory is respectively used for substituting a plurality of blocks in the data area, wherein data to be written into the blocks in the data area is written into the blocks in the substitution area, and the blocks in the substitution area are selected from the spare area of the non-volatile memory. A plurality of temporary blocks of the non-volatile memory is used as a temporary area of the blocks in the substitution area, wherein the temporary area is used for temporarily storing the data to be written into the blocks in the substitution area.01-27-2011
20110022786FLASH MEMORY STORAGE APPARATUS, FLASH MEMORY CONTROLLER, AND SWITCHING METHOD THEREOF - A flash memory storage apparatus including a multi level cell (MLC) NAND flash memory, a flash memory controller, and a host transmission bus is provided. The MLC NAND flash memory includes a plurality of blocks for storing data, wherein each of the blocks has an upper page and a lower page, and the writing speed of the lower page is faster than that of the upper page. The flash memory controller is electrically connected to the MLC NAND flash memory and is used for executing storage mode switching steps. The host transmission bus is electrically connected to the flash memory controller and is used for communicating with a host. The flash memory storage apparatus provided by the present invention can provide multiple storage modes in order to store different data.01-27-2011
20110022785METHOD FOR PROGRAMMING A MEMORY-PROGRAMMABLE CONTROLLER WITH RESISTANT STORAGE OF DATA IN MEMORY - The invention relates to a method for programming and/or diagnosis of a memory-programmable controller, having at least one memory-programmable function component. For programming, a predetermined programming system is used. In the context of this programming system variables are predetermined, and information exchange sequences are used for the programming. Results of the programming are output during at least one programming mode via an output device, and input information is at least in part stored permanently in memory.01-27-2011
20120117316SEMICONDUCTOR DEVICE HAVING STACKED ARRAY STRUCTURE, NAND FLASH MEMORY ARRAY USING THE SAME AND FABRICATION THEREOF - The present invention relates to a semiconductor device, a memory array and a fabrication method thereof, and more particularly to a semiconductor device having a stacked array structure (referred to as a STAR structure: a STacked ARray structure) applicable to not only a switch device but also a memory device, a NAND flash memory array using the same as a memory device and a fabrication method thereof.05-10-2012
20120117315SEMICONDUCTOR MEMORY CARD - According to one embodiment, a semiconductor memory card includes a first pin group which includes a plurality of pins arranged in a line at an end portion on a side of an inserting direction into a connector and part of which is used both in a first and second modes; and a second pin group which includes a plurality of pins including at least two pin pairs for differential signal, is arranged so that a ground is positioned on both sides of each of the pin pairs for differential signal, and is used only in the second mode. In the second mode, among the respective pins configuring the first pin group, any of adjacent two pins are changed to a pin pair for differential clock signal, and a function of remaining pins of the first pin group is stopped.05-10-2012
20120117314MEMORY DEVICES OPERATED WITHIN A COMMUNICATION PROTOCOL STANDARD TIMEOUT REQUIREMENT - The present disclosure includes methods and devices for logical memory blocks. One method for operating a memory device includes receiving a command to operate X pages of the memory device, X being greater than Y, and executing the command by executing multiple subcommands, each subcommand operating on a logical memory block portion of the X pages, each logical memory block including at most Y pages. T is a timeout limit, N is a number of pages comprising a block of memory, and Y is number of pages that can be operated within time T.05-10-2012
20120117313MEMORY DEVICE PROGRAM WINDOW ADJUSTMENT - In one or more embodiments, a memory device is disclosed as having an adjustable programming window having a plurality of programmable levels. The programming window is moved to compensate for changes in reliable program and erase thresholds achievable as the memory device experiences factors such as erase/program cycles that change the program window. The initial programming window is determined prior to an initial erase/program cycle. The programming levels are then moved as the programming window changes, such that the plurality of programmable levels still remain within the program window and are tracked with the program window changes.05-10-2012
20120117312Hybrid Server with Heterogeneous Memory - A method, hybrid server system, and computer program product, for managing access to data stored on the hybrid server system. A memory system residing at a server is partitioned into a first set of memory managed by the server and a second set of memory managed by a set of accelerator systems. The set of accelerator systems are communicatively coupled to the server. The memory system comprises heterogeneous memory types. A data set stored within at least one of the first set of memory and the second set of memory that is associated with at least one accelerator system in the set of accelerator systems is identified. The data set is transformed from a first format to a second format, wherein the second format is a format required by the at least one accelerator system.05-10-2012
20120117311Memory System And Method Of Operating A Memory System - A memory system according to at least one example embodiment stores meta data in a cache register when the memory system enters a standby mode. Therefore, the memory system may reduce power consumption in the standby mode, and/or rapidly perform a mode switch.05-10-2012
20120117310USB FLASH DRIVE AND METHOD FOR SWITCHING FUNCTIONS OF THE USB FLASH DRIVE - A system and a method for switching functions of A Universal Serial Bus (USB) flash drive includes setting a bilateral switch under a first triggered status represents that the USB flash drive is in a boot mode, and under a second triggered status represents that the USB flash drive is in a memory mode. The switching method further includes a determination of whether the USB flash drive is in the boot mode, according to the triggered status of the bilateral switch. The switching method further includes controlling the host controller to access data in a flash memory in the USB flash drive, if the USB flash drive is in the boot mode; or controlling the host controller to access data in a main flash memory section in the flash memory if the USB flash drive is in the boot mode.05-10-2012
20120117309NAND FLASH-BASED SOLID STATE DRIVE AND METHOD OF OPERATION - A solid state drive that uses over-provisioning of NAND flash memory blocks as part of housekeeping functionality, including deduplication and coalescence of data for efficient usage of NAND flash memory devices and maintaining sufficient numbers of erased blocks to promote write performance.05-10-2012
20110022784MEMORY SYSTEM - A memory system according to an embodiment of the present invention comprises: a memory amount required for management table creation is reduced by adopting a nonvolatile semiconductor memory including a plurality of parallel operation elements respectively having a plurality of physical blocks as units of data erasing and a controller that can drive the parallel operation elements in parallel and has a number-of-times-of-erasing managing unit that manages the number of times of erasing in logical block units associated with a plurality of physical blocks driven in parallel.01-27-2011
20110022783FLASH STORAGE WITH INCREASED THROUGHPUT - A flash storage system includes a flash storage controller coupled to storage modules of a flash storage array via universal serial buses. Each storage module includes at least one flash memory device. The flash storage controller receives a programming command of a communication protocol and generates universal serial bus commands based on the programming command. The flash storage controller issues the universal serial bus commands to storage modules in the flash storage array via the universal serial buses. The storage modules process the universal serial bus commands to access data in the flash storage devices of the storage modules.01-27-2011
20110022782FLASH STORAGE WITH ARRAY OF ATTACHED DEVICES - A flash storage system includes a flash storage controller coupled to storage modules of a flash storage array via universal serial buses. Each storage module includes at least one flash memory device. The flash storage controller receives a programming command of a communication protocol and generates universal serial bus commands based on the programming command. The flash storage controller issues the universal serial bus commands to storage modules in the flash storage array via the universal serial buses. The storage modules process the universal serial bus commands to access data in the flash storage devices of the storage modules.01-27-2011
20110022781CONTROLLER FOR OPTIMIZING THROUGHPUT OF READ OPERATIONS - A controller, techniques, systems, and devices for optimizing throughput of read operations in flash memory are disclosed. Various optimizations of throughput for read operations can be performed using a controller. In some implementations, read operations for a multi-die flash memory device or system can be optimized to perform a read request with a highest priority (e.g., an earliest received read request) as soon as the read request is ready. In some implementations, the controller can enable optimized reading from multiple flash memory dies by monitoring a read/busy state for each die and switching between dies when a higher priority read operation is ready to begin.01-27-2011
20110022780RESTORE INDEX PAGE - Techniques for restoring index pages stored in non-volatile memory are disclosed where the index pages map logical sectors into physical pages. Additional data structures in volatile and non-volatile memory can be used by the techniques for restoring index pages. In some implementations, a lookup table associated with data blocks in non-volatile memory can be used to provide information regarding the mapping of logical sectors into physical pages. In some implementations, a lookup table associated with data blocks and a range of logical sectors and/or index pages can be used.01-27-2011
20110022779Skip Operations for Solid State Disks - Described embodiments provide skip operations for transferring data to or from a plurality of non-contiguous sectors of a solid-state memory. A host layer module sends data to, and receives commands from, a communication link. Received commands are one of read requests or write requests, with commands including i) a starting sector address, ii) a skip mask indicating the span of all sector addresses in the request and the sectors to be transferred, iii) a total number of sectors to be transferred; and, for write requests, iv) the data to be written to the sectors. A buffer stores data for transfer to or from the solid-state memory. A buffer layer module i) manages the buffer, ii) segments the span of the request into a plurality of chunks, and iii) determines, based on the skip mask, a number of chunks to be transferred to or from the solid-state memory.01-27-2011
20110022777SYSTEM AND METHOD FOR DIRECT MEMORY ACCESS IN A FLASH STORAGE - A flash storage device provides direct memory access based on a first communication protocol. A host selects the first communication protocol and provides a request to the flash storage device for a direct memory access. Additionally, the host provides data blocks to the flash storage device for the direct memory access. In the first communication protocol, the host need not provide an address to the flash storage device for the direct memory access. The flash storage device stores the data blocks at sequential addresses starting at a predetermined address in the flash storage device. Another host may then select a second communication protocol and transfer the data blocks in the flash storage by using the second communication protocol.01-27-2011
20110022776DATA RELIABILITY IN STORAGE ARCHITECTURES - Among other subject matter, storage architectures are provided that store data reliably in connection with a system. The storage architecture (01-27-2011
20120117308DATA PROTECTION DEVICE AND METHOD THEREOF - A data protection device includes a basic input output system chip and a main control chip. The basic input output system chip stores basic input output system program and includes a write protection pin and a plurality of status registers. The main control chip includes a plurality of general purpose input output pins. One general purpose input output pin is electrically connected to the write protection pin of the basic input output system chip, the voltage level of the general purpose input output pin is controlled by performing different command programs of the basic input output system program, and the status registers and the basic input output system chip are selectable to be in a write protection mode or a writable mode under the control of the voltage level of the write protection pin of the basic input output system chip.05-10-2012
20120117307NON-VOLATILE MEMORY (NVM) ERASE OPERATION WITH BROWNOUT RECOVERY TECHNIQUE - A method for erasing a non-volatile memory includes: performing a first pre-erase program step on the non-volatile memory; determining that the non-volatile memory failed to program correctly during the first pre-erase program step; performing a first soft program step on the non-volatile memory in response to determining that the non-volatile memory failed to program correctly; determining that the non-volatile memory soft programmed correctly; performing a second pre-erase program step on the non-volatile memory in response to determining that the non-volatile memory soft programmed correctly during the first soft program step; and performing an erase step on the non-volatile memory. The method may be performed using a non-volatile memory controller.05-10-2012
20120117306SENSE OPERATION FLAGS IN A MEMORY DEVICE - Memory devices, methods for programming sense flags, methods for sensing flags, and memory systems are disclosed. In one such memory device, the odd bit lines of a flag memory cell array are connected with a short circuit to a dynamic data cache. The even bit lines of the flag memory cell array are disconnected from the dynamic data cache. When an even page of a main memory cell array is read, the odd flag memory cells, comprising flag data, are read at the same time so that it can be determined whether the odd page of the main memory cell array has been programmed. If the flag data indicates that the odd page has not been programmed, threshold voltage windows can be adjusted to determine the states of the sensed even memory cell page.05-10-2012
20120117305Method Of Storing Blocks Of Data In A Plurality Of Memory Devices For High Speed Sequential Read, A Memory Controller And A Memory System - A method for controlling the storage of a plurality of blocks of sequential data in a plurality of independent NAND memory devices, where each NAND memory device can be independently written to or read from in a block of data, with the block as the minimum unit of storage to be written to or read from. The method includes assigning a different NAND memory device to each different block of data received for storage and for storing the plurality of blocks of data in the plurality of different NAND memory devices. Efficiency of readout of sequential blocks of data is improved. The present invention also comprises a memory controller having a processor and a non-volatile memory for storing programming code that can perform the foregoing method. Finally, the present invention is a memory system that has a plurality of NAND memory devices device that can be independently written to or read from in a block of data, with the block as the minimum unit of storage to be written to or read from. The memory system further has a memory controller that has a processor and non-volatile memory for storing programming code that can be executed by the processor in accordance with the foregoing described method.05-10-2012
20090265508Scheduling of Housekeeping Operations in Flash Memory Systems - A re-programmable non-volatile memory system, such as a flash EEPROM system, having its memory cells grouped into blocks of cells that are simultaneously erasable is operated to perform memory system housekeeping operations in the foreground during execution of a host command, wherein the housekeeping operations are unrelated to execution of the host command. Both one or more such housekeeping operations and execution of the host command are performed within a time budget established for executing that particular command. One such command is to write data being received to the memory. One such housekeeping operation is to level out the wear of the individual blocks that accumulates through repetitive erasing and re-programming.10-22-2009
20120198141INTEGRATING DATA FROM SYMMETRIC AND ASYMMETRIC MEMORY - Data stored within symmetric and asymmetric memory components of main memory is integrated by identifying a first data as having access characteristics suitable for storing in an asymmetric memory component. The first data is included among a collection of data to be written to the asymmetric memory component. An amount of data is identified within the collection of data to be written to the asymmetric memory component. The amount of data is compared within the collection of data to a volume threshold to determine whether a block write to the asymmetric memory component is justified by the amount of data. If justified, the collection of data is loaded to the asymmetric memory component.08-02-2012
20120198134MEMORY CONTROL APPARATUS THAT CONTROLS DATA WRITING INTO STORAGE, CONTROL METHOD AND STORAGE MEDIUM THEREFOR, AND IMAGE FORMING APPARATUS - A memory control apparatus capable of preventing the performance from being lowered at the time of data deletion. The memory control apparatus includes a CPU and a storage controller of a main controller and includes a memory controller of an SSD of the main controller. The memory controller selectively performs first write processing to write data into a flash memory of the SSD or second write processing to write data into the flash memory after unnecessary data recorded in the flash memory is deleted. In a case where a deletion mode to delete unnecessary data is set, the CPU causes the memory controller to perform the second write processing, if the capacity of data to be written exceeds a predetermined data capacity.08-02-2012
20120198124METHODS AND SYSTEMS FOR OPTIMIZING READ OPERATIONS IN A NON-VOLATILE MEMORY - Systems and methods are disclosed for increasing efficiency of read operations by selectively re-ordering a sequence in which logical block addresses (“LBAs”) are read out of multi-level cell (“MLC”) non-volatile memory. In one embodiment, the LBAs can correspond to upper and lower pages. Because data stored in lower pages can be retrieved from NVM faster than data stored in upper pages, embodiments disclosed herein can selectively re-order the LBAs such that the first LBA to be read corresponds to a lower page.08-02-2012
20090037649Methods and Systems for Running Multiple Operating Systems in a Single Mobile Device - Methods and systems for running multiple operating systems in a single embedded or mobile device (include PDA, cellular phone and other devices) are disclosed. The invention allows a mobile device that normally can only run a single operating system to run another operating system while preserving the state and data of the original operating system. Guest OS is packaged into special format recognizable by the host OS that still can be executed in place by the system. The Methods include: Change the memory protection bits for the original OS; Fake a reduced physical memory space for guest OS; Use special memory device driver to claim memories of host OS; Backup whole image of the current OS and data to external memory card.02-05-2009
20120271985SEMICONDUCTOR MEMORY SYSTEM SELECTIVELY STORING DATA IN NON-VOLATILE MEMORIES BASED ON DATA CHARACTERSTICS - A semiconductor memory device includes a memory block and memory transmission and reception unit. The memory block includes a first non-volatile memory allocated to a first region having a first address range of physical addresses and a second non-volatile memory allocated to a second region having a second address range different from the first address range, which are mapped to logical addresses of a storing region in a host device. The memory transmission and reception unit performs data input and output operations between the host device and the first non-volatile memory using a first data input and output type, and performs data input and output operations between the host device and the second non-volatile memory using a second data input and output type. The first data input and output type performs the data input and output operations by access units corresponding to the first non-volatile memory.10-25-2012
20120271982INTELLIGENT FLASH REPROGRAMMING - Apparatus, methods, and computer-readable media for programming, reading, and servicing non-volatile storage device to improve data retention time and data density are disclosed. According to one embodiment, a method of managing a non-volatile memory storage device includes generating output values based on an expected pattern of discrete states stored in memory cells of the storage device, comparing output values for the memory cells to expected output values using a pre-selected threshold, and based on the comparing, programming other memory cells of the storage device to refresh the programming of the other memory cells. Methods of performing service and management operations for interrupting a host system coupled a non-volatile memory storage device are also disclosed.10-25-2012
20090259803SYSTEMS, METHODS AND COMPUTER PROGRAM PRODUCTS FOR ENCODING DATA TO BE WRITTEN TO A NONVOLATILE MEMORY BASED ON WEAR-LEVELING INFORMATION - A nonvolatile memory system is operated by providing data to be written to a nonvolatile memory, logically combining the data to be written to the nonvolatile memory with a random pattern to generate encoded data; and programming the encoded data in the nonvolatile memory.10-15-2009
20090271565METHOD OF PROCESSING HARD DISK DRIVE - A method of processing a hard disk drive. The method can include downloading at least two process codes and a main code to a first storage area of the hard disk drive, sequentially performing processes based on the at least two process codes, and installing the main code in a second storage area.10-29-2009
20100011153BLOCK MANAGEMENT METHOD, AND STORAGE SYSTEM AND CONTROLLER USING THE SAME - A block management method for managing a multi level cell (MLC) NAND flash memory is provided, wherein the MLC NAND flash memory has a plurality of physical blocks grouped into at least a data area and a spare area, each of the physical blocks has a plurality of pages divided into a plurality of upper pages, and a plurality of lower pages with a writing speed thereof being greater than that of the upper pages. The block management method includes configuring a plurality of logical blocks for being accessed by a host, recording the logical block belonged to a frequently accessed block and executing a special mode to use the lower pages of at least two physical blocks of the MLC NAND flash memory for storing data of one logical block belonged to the frequently accessed block. Accordingly, it is possible to increase the access speed of a storage system.01-14-2010
20100023678NONVOLATILE MEMORY DEVICE, NONVOLATILE MEMORY SYSTEM, AND ACCESS DEVICE - When an access device accesses a nonvolatile memory device, the nonvolatile memory device or the access device detects or calculates a temperature T of the nonvolatile memory device. A temperature-adaptive control part of the nonvolatile memory device controls an access rate to a nonvolatile memory on the basis of the temperature T. Accordingly, the control part controls the rate so that the temperature T of the nonvolatile memory devices cannot exceed a limit temperature Trisk. In this manner, a nonvolatile memory system can eliminate a risk of a burn when ejecting the semiconductor memory device and can read and write data at a high speed.01-28-2010
20100023680Method for Controlling Non-Volatile Semiconductor Memory System - In a memory system using a storage medium, which is inserted into an electronic apparatus via a connector to add a memory function thereto, the storage medium has a GROUND terminal, a power supply terminal, a control terminal and a data input/output terminal, and the connector has a function of being sequentially connected to each of the terminals. When the storage medium is inserted into the connector, the GROUND terminal and control terminal of the storage medium are connected to corresponding terminals of the connector before the power supply terminal and data input/output terminal of the storage medium are connected to corresponding terminals of the connector. Thus, it is possible to improve the stability when a memory card is inserted into or ejected from the memory system.01-28-2010
20130166821LOW LATENCY AND PERSISTENT DATA STORAGE - Persistent data storage with low latency is provided by a method that includes receiving a low latency store command that includes write data. The write data is written to a first memory device that is implemented by a nonvolatile solid-state memory technology characterized by a first access speed. It is acknowledged that the write data has been successfully written to the first memory device. The write data is written to a second memory device that is implemented by a volatile memory technology. At least a portion of the data in the first memory device is written to a third memory device when a predetermined amount of data has been accumulated in the first memory device. The third memory device is implemented by a nonvolatile solid-state memory technology characterized by a second access speed that is slower than the first access speed.06-27-2013
20130166824BLOCK MANAGEMENT FOR NONVOLATILE MEMORY DEVICE - A method of managing memory blocks in a nonvolatile memory device comprises identifying a full memory block among a plurality of memory blocks in the nonvolatile memory device, determining whether a block life of the full memory block exceeds a threshold value, and upon determining that the block life of the full memory block exceeds the threshold value, selecting the full memory block as a target block for garbage collection.06-27-2013
20130166827WEAR-LEVEL OF CELLS/PAGES/SUB-PAGES/BLOCKS OF A MEMORY - The invention is directed to a method for wear-leveling cells or pages or sub-pages or blocks of a memory such as a flash memory, the method comprising:—receiving (S06-27-2013
20120233385HARD DISK DRIVE WITH OPTIONAL CACHE MEMORY - A computer system includes a hard disk drive, a processor coupled to the hard disk drive, and a cache interface coupled to the processor and detachably connectable to a cache memory. The processor is adapted, subsequent to an initial interrogation of the cache interface, to determine whether the cache memory is connected to the cache interface by inspecting an indication of the presence or the absence of the cache memory, the indication being stored in a register in the processor or in a memory associated with the processor such that the inspecting avoids repeat interrogation of the cache interface, to communicate with the cache memory and the hard disk drive such that the processor has access to the cache memory when the cache memory is connected to the cache interface, and to communicate with the hard disk drive when the cache memory is disconnected from the cache interface.09-13-2012
20090013126METHOD AND DEVICES FOR COMPRESSING DELTA LOG USING FLASH TRANSACTIONS - Each received piece of configuration data is added at a next currently free location in a volatile buffer. The contents of the volatile buffer are compressed after adding each received piece of configuration data. The compression result is stored in a non-volatile flash memory. If the compression result was shorter than a limit, it is allowed to be overwritten in the flash memory by a next compression result. If the compression result was longer than the limit, it is stored in the flash memory and the next compression result is directed to a different location in the flash memory.01-08-2009
20090013125MEMORY CARD - A memory device is provided which is connected to operate with power and clocks supplied from a host apparatus. The memory device includes external terminals, a flash memory chip to store data, an IC chip to process data; and a controller chip connected with the external terminals, the flash memory chip and the IC chip. The flash memory chip, the IC chip and the controller chip are discrete chips. The controller chip writes data inputted from the host apparatus into the flash memory chip or the IC chip and transfers data read from the flash memory chip or the IC chip to the host apparatus, based upon commands from the host apparatus.01-08-2009
20090013124ROM CODE PATCH METHOD - The present invention relates to a method of replacing a sequence of one or more commands from a routine in a ROM of a device using a RAM. The method allows replacing part of a routine, for example a single command, while continuing to use the rest of the commands of the routine from the ROM. In an exemplary embodiment of the invention, a single command is replaced by adding only two additional commands or four additional commands as overhead in the replacement process.01-08-2009
20090013123Storage Bridge and Storage Device and Method Applying the Storage Bridge - A storage bridge includes a flash memory register unit for temporarily storing data and for storing data of a storage unit when a host unit stores data to the storage unit, and a transmission interface control unit coupled to the flash memory register unit for controlling operations of the flash memory register unit.01-08-2009
20090013122Transaction Method for Managing the Storing of Persistent Data in a Transaction Stack - A transaction method manages the storing of persistent data to be stored in at least one memory region of a non-volatile memory device before the execution of update operations that involve portions of the persistent data. Values of the persistent data are stored in a transaction stack that includes a plurality of transaction entries before the beginning of the update operations so that the memory regions involved in such an update are restored in a consistent state if an unexpected event occurs. A push extreme instruction reads from the memory cells a remaining portion of the persistent data that is not involved in the update operation, and stores the remaining portion in a subset of the transaction entries. The push extreme instruction is executed instead of a push instruction when the restoring of the portion of persistent data is not required after the unexpected event. The restoring corresponds to the values that the persistent data had before the beginning of the update operations.01-08-2009
20090006725MEMORY DEVICE - A memory device includes a nonvolatile memory and a controller. The nonvolatile memory includes a storage area having a plurality of memory blocks each including a plurality of nonvolatile memory cells, and a buffer including a plurality of nonvolatile memory cells and configured to temporarily store data, and in which data is erased for each block. If a size of write data related to one write command is not more than a predetermined size, the controller writes the write data to the buffer.01-01-2009
20090006724Method of Storing and Accessing Header Data From Memory - Methods of storing and accessing data using a header portion of a file are disclosed. In an embodiment, a method of storing content in a non-volatile memory is disclosed. The method includes reading a content file including media content and including a trailer, storing information related to the trailer together with secure data in a header portion of a file, and storing the file to a storage element of the non-volatile memory or a memory area of a host device coupled to the non-volatile memory device.01-01-2009
20090006723METHOD FOR COMMUNICATING WITH A NON-VOLATILE MEMORY STORAGE DEVICE - Method for a storage device is provided. The method includes interpreting a command from a host system, wherein a command parser module for a storage device interprets the command; and extracting information regarding an operation from the command, wherein the command parser module extracts the information and interfaces with the host system.01-01-2009
20090006722AUTO START CONFIGURATION WITH PORTABLE MASS STORAGE DEVICE - A portable flash memory storage device such as a memory card can configure a host device upon insertion. The configuration may specify applications or other sequences of operations to be executed by the host upon insertion of the card. Files on the card may be associated with an appropriate application and then automatically opened with the appropriate application. A secure configuration may override a more freely modifiable configuration in certain embodiments.01-01-2009
20090006721METHODS OF AUTO STARTING WITH PORTABLE MASS STORAGE DEVICE - A portable flash memory storage device such as a memory card can configure a host device upon insertion. The configuration may specify applications or other sequences of operations to be executed by the host upon insertion of the card. Files on the card may be associated with an appropriate application and then automatically opened with the appropriate application. A secure configuration may override a more freely modifiable configuration in certain embodiments.01-01-2009
20090006719SCHEDULING METHODS OF PHASED GARBAGE COLLECTION AND HOUSE KEEPING OPERATIONS IN A FLASH MEMORY SYSTEM - An embodiment of a non-volatile memory storage system comprises a memory controller, and a flash memory module. The memory controller manages the storage operations of the flash memory module. The memory controller is configured to assign a priority level to one or more types of house keeping operations that may be higher than a priority level of one or more types of commands received by a host coupled to the storage system, and to service all operations required of the flash memory module according to priority.01-01-2009
20090006718SYSTEM AND METHOD FOR PROGRAMMABLE BANK SELECTION FOR BANKED MEMORY SUBSYSTEMS - A programmable memory system and method for enabling one or more processor devices access to shared memory in a computing environment, the shared memory including one or more memory storage structures having addressable locations for storing data. The system comprises: one or more first logic devices associated with a respective one or more processor devices, each first logic device for receiving physical memory address signals and programmable for generating a respective memory storage structure select signal upon receipt of pre-determined address bit values at selected physical memory address bit locations; and, a second logic device responsive to each the respective select signal for generating an address signal used for selecting a memory storage structure for processor access. The system thus enables each processor device of a computing environment memory storage access distributed across the one or more memory storage structures.01-01-2009
20100082890Method of managing a solid state drive, associated systems and implementations - A solid state drive may include one or more memory cell arrays divided into a plurality of blocks. A first portion of the blocks may be designated for storing user data and a second portion of the blocks may be designated as reserved blocks for replacing defective blocks in the first portion. In one embodiment, the method includes reformatting, by a memory controller, the solid state drive to convert one or more blocks in the first portion into reserved blocks.04-01-2010
20130166831Apparatus, System, and Method for Storing Metadata - Apparatuses, systems, and methods are disclosed for storing metadata. A mapping module is configured to maintain a mapping structure for logical addresses of a non-volatile device. A metadata module is configured to store membership metadata for the logical addresses with logical-to-physical mappings for the logical addresses in the mapping structure.06-27-2013
20130166832METHODS AND ELECTRONIC DEVICES FOR ADJUSTING THE OPERATING FREQUENCY OF A MEMORY - Methods and electronic devices for adjusting an operating frequency of a memory are disclosed. The method includes: transmitting to the memory a first command that instructs the memory to hold the data information in the memory; transmitting to the memory controller a second command that adjusts the first frequency of the memory controller to a second frequency; and transmitting to the memory a third command that instructs the memory to exchange the data information according to the second frequency of the memory controller. According to the disclosure, it is possible to dynamically adjust the frequency of the memory during operation, avoiding the need of the user to turn off and then turn on the electronic device to adjust the frequency of the memory.06-27-2013
20130166826SOLID-STATE DEVICE MANAGEMENT - An embodiment is a method for establishing a correspondence between a first logical address and a first physical address on solid-state storage devices located on a solid-state storage board. The solid-state storage devices include a plurality of physical memory locations identified by physical addresses, and the establishing is by a software module located on a main board that is separate from the solid-state storage board. The correspondence between the first logical address and the first physical address is stored in in a location on a solid-state memory device that is accessible by an address translator module located on the solid-state storage board. The solid-state memory device is located on the solid-state storage board. The first logical address is translated to the first physical address by the address translator module based on the previously established correspondence between the first logical address and the first physical address.06-27-2013
20130166828DATA UPDATE APPARATUS AND METHOD FOR FLASH MEMORY FILE SYSTEM - Disclosed herein are a data update apparatus and method. The apparatus includes an update identification unit, a data storage unit, a block allocation unit, and a data update unit. The update identification unit determines whether the input/output request signal corresponds to an update signal. The data storage unit stores mapping information about the blocks of an arbitrary file in a metadata area. The block allocation unit stores addresses of one or more free blocks, which are selected from among blocks included in the data storage unit and in which data has not been stored. The data update unit acquires the addresses of the free blocks, writes the update data to the free blocks, and updates existing block addresses, which belong to information included in mapping information of the data storage unit and to which the update data has been mapped, with the addresses of the free blocks.06-27-2013
20130166829Fast Block Device and Methodology - A device, method and system is directed to fast data storage on a block storage device. New data is written to an empty write block. A location of the new data is tracked. Meta data associated with the new data is written. A lookup table may be updated based in part on the meta data. The new data may be read based the lookup table configured to map a logical address to a physical address.06-27-2013
20130166830BLOCK MANAGEMENT METHOD FOR FLASH MEMORY AND CONTROLLER AND STORAGE SYSETM USING THE SAME - A block management method for managing a mapping relationship between a plurality of logical blocks and a plurality of physical blocks of a flash memory is provided. The block management method includes: grouping the logical blocks into a plurality of logical zones; recording the mapping relationship between each logical block in each logical zone and all the data physical blocks among the physical blocks in a corresponding logical zone table in unit of the logical zones; and recording all the no-data physical blocks among the physical blocks with a single no-data physical block table. Thereby, the logical blocks can be mapped to all the physical blocks so that frequent access to specific physical blocks can be avoided when a user writes data into a specific logical zone frequently, and accordingly the lifespan of the flash memory can be prolonged.06-27-2013
20130166822SOLID-STATE STORAGE MANAGEMENT - Solid-state storage management for a system that includes a main board and a solid-state storage board separate from the main board is provided. The sold-state storage board includes a solid-state memory device and solid-state storage devices. The system is configured to perform a method that includes a correspondence being established, by a software module located on the main board, between a first logical address and a first physical address on the solid-state storage devices. The correspondence between the first logical address and the first physical address is stored in a location on the solid-state memory device. The method also includes translating the first logical address into the first physical address. The translating is performed by an address translator module located on the solid-state storage board and is based on the previously established correspondence between the first logical address and the first physical address.06-27-2013
20130166823NON-VOLATILE MEMORY DEVICE - A non-volatile memory device includes a plurality of bit lines; a plurality of page buffers corresponding to the bit lines, respectively, and configured to each store a write data; and a control circuit configured to control at least one page buffer of the plurality of page buffers to store the write data of a first logic level and control other ones of the plurality of page buffers to store the write data of a second logic level, wherein the control circuit is further configured to select the at least one page buffer based on an address inputted to the control circuit. Since write data of diverse patterns may be generated within a non-volatile memory device by using a portion of the bits of the address, a test operation of the non-volatile memory device may be performed within a short time.06-27-2013
20130166825Method Of Controlling Non-Volatile Memory, Non-Volatile Memory Controller Therefor, And Memory System Including The Same - A method of controlling a non-volatile memory device having multiple planes including receiving write requests from a host, the write requests each including a logical address, a write command, and a data set; storing the data sets at an address of a buffer; storing the buffer address in a mapping table that maps addresses of the buffer to the multiple planes; sequentially transmitting the data sets stored at respective buffer addresses to page buffers, respectively, of the planes corresponding to the buffer addresses according to the mapping table; and programming in parallel at least two data sets stored in respective page buffers to memory cells of the non-volatile memory device.06-27-2013
20130166817DATA TRANSFER SYSTEMS WITH POWER MANAGEMENT - A controller for transferring data between a host and a storage medium includes a data transfer unit and a control unit. The data transfer unit transfers data according to control commands from the host if the data transfer unit is enabled. The control unit coupled to the data transfer unit receives a status signal indicating whether the storage medium is coupled to a socket of the controller. The control unit provides interruption signals to the host. Power and a clock signal for the control unit are disabled if the status signal indicates that the storage medium is decoupled from the controller.06-27-2013
20130166818MEMORY LOGICAL DEFRAGMENTATION DURING GARBAGE COLLECTION - A method and system defragments data during garbage collection. Garbage collection may be more efficient when the valid data that is aggregated together is related or logically linked. In particular, data from the same file or that is statistically correlated may be combined in the same blocks during garbage collection.06-27-2013
20130166819SYSTEMS AND METHODS OF LOADING DATA FROM A NON-VOLATILE MEMORY TO A VOLATILE MEMORY - A method may be performed in a data storage device that includes a controller, a non-volatile memory, and a volatile memory. The method includes loading a first portion of stored data from the non-volatile memory to the volatile memory according to one or more load priority indicators accessible to the controller. The method further includes, in response to completion of the loading of the first portion of the stored data to the volatile memory and prior to completion of loading a second portion of the stored data to the volatile memory, sending a signal to indicate to a host device operatively coupled to the data storage device that the volatile memory is ready for use by the host device.06-27-2013
20130166820METHODS AND APPRATUSES FOR ATOMIC STORAGE OPERATIONS - A method and apparatus for storing data packets in two different logical erase blocks pursuant to an atomic storage request is disclosed. Each data packet stored in response to the atomic storage request comprises persistent metadata indicating that the data packet pertains to an atomic storage request. In addition, a method and apparatus for restart recovery is disclosed. A data packet preceding an append point is identified as satisfying a failed atomic write criteria, indicating that the data packet pertains to a failed atomic storage request. One or more data packets associated with the failed atomic storage request are identified and excluded from an index of a non-volatile storage media.06-27-2013
20080313390Method and System for Presenting an Executing Status of a Memory Card - A system and a method for presenting an executing status of a memory card are provided. The system comprises a processing apparatus and an access device. The processing apparatus stores an application program having a plurality of icons. The access device connects the memory card and the processing apparatus. The processing apparatus sends a reading command to the memory card via the access device. The memory card sends executing information in reply after receiving the reading command. Finally, the processing apparatus analyzes the executing information of the memory card and presents a corresponding icon through the application program in association with the analytic result.12-18-2008
20120239865STORAGE DEVICE - A storage device realizing an improvement in rewrite endurance of a nonvolatile memory and an improvement in data transfer rate of write and read operations is provided including a nonvolatile memory; a volatile memory for storing file management information of the nonvolatile memory; a controller for controlling the nonvolatile memory and the volatile memory; and a power supply maintaining unit for supplying power to the nonvolatile memory, the volatile memory, or the controller upon power shutdown. The controller reads the file management information in the nonvolatile memory upon power-on and writes the same in the volatile memory, and read and write operations are performed based on the file management information in the volatile memory, and the file management information in the volatile memory is written in the nonvolatile memory upon power shutdown.09-20-2012
20120239852HIGH SPEED INPUT/OUTPUT PERFORMANCE IN SOLID STATE DEVICES - A method of transferring data in a flash storage device comprising a random access memory and a plurality of channels of a flash array is provided. The method comprises receiving a plurality of data segments from a host system, storing the plurality of data segments in the random access memory, allocating the plurality of data segments among the plurality of channels of the flash array, and writing the allocated data segments from the random access memory to the respective channels of the flash array.09-20-2012
20080294837MEMORY CONTROLLER FOR CONTROLLING A NON-VOLATILE SEMICONDUCTOR MEMORY AND MEMORY SYSTEM - A memory controller includes a host interface, a holding circuit and a control circuit. The memory controller controls a semiconductor memory. The semiconductor memory includes memory blocks. The host interface is connectable to a host apparatus and receivable of write data and an address. The holding circuit is capable of holding the address. The control circuit searches information indicating an existence of a parent directory from the write data, and holds the address in the holding circuit when the information is detected. The control circuit successively writes the write data to the same memory block when a new write access is made with respect to the same address as the address held in the holding circuit.11-27-2008
20080294836NAND flash memory system with programmable connections between a NAND flash memory controller and a plurality of NAND flash memory modules and method thereof - A method and related system for programming connections between a NAND flash memory controller and a plurality of NAND flash memory modules includes the NAND flash memory controller generating a switch signal and a swap signal according to a condition of one of the plurality of NAND flash memory modules, a remap module selectively coupling the plurality of NAND flash memory modules to the NAND flash memory controller according to the switch signal, and a swap module selectively coupling the plurality of NAND flash memory modules to the NAND flash memory controller according to the swap signal.11-27-2008
20080294835SOLID STATE STORAGE SUBSYSTEM FOR EMBEDDED APPLICATIONS - A non-volatile storage subsystem solution is provided for embedded applications. The storage subsystem is preferably designed to communicate with the host system using a signal interface, such as a USB or SATA interface, that uses substantially fewer signal lines than the IDE interface traditionally used for embedded applications. Thus, the amount of board real estate used to carry interface signals in the host system is reduced. To further reduce board real estate, the host system may include a processor that includes an integrated controller (e.g., a USB or SATA controller) corresponding to the host-subsystem signal interface. The storage subsystem may plug into, and lock to, an internal connector on a circuit board of the host system.11-27-2008
20080294834SOLID STATE STORAGE SUBSYSTEM FOR EMBEDDED APPLICATIONS - A non-volatile storage subsystem solution is provided for embedded applications. The storage subsystem is preferably designed to communicate with the host system using a signal interface, such as a USB or SATA interface, that uses substantially fewer signal lines than the IDE interface traditionally used for embedded applications. Thus, the amount of board real estate used to carry interface signals in the host system is reduced. To further reduce board real estate, the host system may include a processor that includes an integrated controller (e.g., a USB or SATA controller) corresponding to the host-subsystem signal interface. The storage subsystem may plug into, and lock to, an internal connector on a circuit board of the host system.11-27-2008
20110029719DATA WRITING METHOD FOR FLASH MEMORY AND CONTROL CIRCUIT AND STORAGE SYSTEM USING THE SAME - A data writing method for moving data in a plurality of flash memory modules during a write command of a host system is executed is provided, wherein each of the flash memory modules has a plurality of physical blocks. The present data writing method includes transferring first data received from the host system to one of the flash memory modules and writing the first data into the physical blocks of the flash memory module according to the write command. The present data writing method also includes moving at least one second data in the physical blocks of another one of the flash memory modules during the first data is written. Thereby, when the host system is about to write data into the other flash memory module, the time for executing the write command is effectively reduced.02-03-2011
20130103892COMBINED MEMORY BLOCK AND DATA PROCESSING SYSTEM HAVING THE SAME - A combined memory block includes a first memory unit configured to store data and an additional memory unit that forms a stacked structure with the memory unit, wherein the memory unit and the storage unit together form multi-level cells having variable resistance in storing data.04-25-2013
20110035543MEMORY DRIVE THAT CAN BE OPERATED LIKE OPTICAL DISK DRIVE AND METHOD FOR VIRTUALIZING MEMORY DRIVE AS OPTICAL DISK DRIVE - The present invention relates to a memory drive that can be virtualized as an optical disk drive and a virtualizing method thereof. One embodiment of the present invention discloses a method for virtualizing a memory drive as an optical disk drive, the memory drive comprising a storage memory and a storage memory controller, which reads or writes data from and to the storage memory. Therefore, according to one embodiment of the present invention, a solid-state which comprises a flash memory and a flash memory controller can be used like an optical disk.02-10-2011
20110035541STORAGE DEVICE AND DEDUPLICATION METHOD - This storage device performs deduplication of eliminating duplicated data by storing a logical address of one or more corresponding logical unit memory areas in a prescribed management information storage area of a physical unit memory area defined in the storage area provided by the flash memory chip, and executes a reclamation process of managing a use degree as the total number of the logical addresses used stored in the management information storage area and a duplication degree as the number of valid logical addresses corresponding to the physical unit memory area for each of the physical unit memory areas, and returning the physical unit memory area to an unused status when the difference of the use degree and the duplication degree exceeds a default value in the physical unit memory area.02-10-2011
20110035539STORAGE DEVICE, AND MEMORY CONTROLLER - The memory controller of a storage device includes a scramble pattern generator, a scramble processor, a logical and physical address conversion table, a memory interface, and a controller, in which the physical page is managed by dividing to a data section and a management section. For the data section, the controller controls the scramble pattern generator to generate a scramble pattern on the basis of a logical address specific to the data section, and controls the scramble processor to scramble the data of the data section corresponding to the logical address by using the scramble pattern, and for the management section, the controller controls the scramble pattern generator to generate a scramble pattern on the basis of a physical address as the write destination of the management section, and scrambling the management data by the scramble processor by using the scramble pattern, so that data is written and reading to and from the semiconductor memory.02-10-2011
20110035534Dual-scope directory for a non-volatile memory storage system - A device, system, and method are disclosed. In one embodiment the device includes a non-volatile memory (NVM) storage array to store a plurality of storage elements. The device also includes a dual-scope directory structure having a background space and a foreground space. The structure is capable of storing several entries that each correspond to a location in the NVM storage array storing a storage element. The background space includes entries for storage elements written into the array without any partial overwrites of a previously stored storage element in the background space. The foreground space includes entries for storage elements written into the array with at least one partial overwrite of one or more previously stored storage elements in the background space.02-10-2011
20110238892WEAR LEVELING METHOD OF NON-VOLATILE MEMORY - A method of wear leveling applied to a non-volatile memory is provided. The method comprises steps of: categorizing all blocks within the non-volatile memory to a first group with erased blocks having higher history numbers, a second group with erased blocks having lower history numbers, or a third group with blocks not either assigned to the first group or the second group; selecting a first block which contains a clod data from the third group; selecting a second block from the first group; copying the cold data from the first block into the second block and updating the history number of the second block; and erasing the first block.09-29-2011
20090327591SLC-MLC COMBINATION FLASH STORAGE DEVICE - Flash memory drives and related methods are disclosed that operate to keep frequently written data, which results in frequently erased blocks, in SLC flash, and relatively static data in MLC flash. A flash drive according to the present disclosure keeps track of the number of times that data for each logical block address (LBA) has been written to the flash memory, and determines whether to store newly received data associated with a particular LBA in SLC flash or in MLC flash depending on the number of writes that have occurred for that particular LBA. For each logical block sent to the flash drive, a comparison is made of the write count of the associated LBA to a threshold. If the write count is above the threshold, the logical block is written to SLC flash. If the write count is below the threshold, the logical block is written to MLC flash.12-31-2009
20090106483SECURE PERSONALIZATION OF MEMORY-BASED ELECTRONIC DEVICES - Systems and/or methods that facilitate programming content to a plurality of nonvolatile memory devices are presented. A wafer program component facilitates programming content to a plurality of memory devices contained on a wafer. The wafer program component can interface with the wafer and can employ parallel processes to program the memory devices on the wafer at substantially the same time. The content programmed to the memory devices can be the same content or different content. A portion of the content can be access-restricted where authentication information is to be provided in order to be granted access to such content, where access-restricted content can include content associated with subscriptions or personal information of a user(s).04-23-2009
20110029720Flash Storage Device and Operation Method Thereof - The invention provides a flash storage device. In one embodiment, the flash storage device comprises a flash memory and a controller. The flash memory comprises a plurality of blocks, wherein each of the plurality of blocks comprises a plurality of pages for storing data, and each of the plurality of pages has a physical address. The controller divides a plurality of logical addresses into a plurality of logical address ranges, records a plurality of partial link tables respectively storing a mapping relationship between logical addresses of a corresponding logical address range and corresponding physical addresses, stores the partial link tables in the flash memory, combines the partial link tables to obtain a link table, and converts logical addresses sent by a host to physical addresses according to the link table.02-03-2011
20110040932Efficient Reduction of Read Disturb Errors in NAND FLASH Memory - Methods and apparatuses for reduction of Read Disturb errors in a NAND FLASH memory system comprise a controller configured to organize FLASH memory devices into blocks, each block having a plurality of pages, and each page defining an individually addressable physical memory location. The controller is further configured to accumulate a Block READ Count corresponding to the number of times any pages in a first block of pages have been read since the first block was last erased. Once the READ count reaches a predetermined number, the controller responds to subsequent READ requests for pages within the first block by moving data associated with a requested page to a page in a second, different block without moving data associated with other pages in the first block, and modifying a logical-to-physical translation table to associate the moved data with the physical address of the page in the second block.02-17-2011
20090313424MEMORY DEVICE AND METHOD FOR SECURE READOUT OF PROTECTED DATA - The invention relates to a memory device, preferably a non-volatile memory device, comprising a memory array (12-17-2009
20100005229FLASH MEMORY APPARATUS AND METHOD FOR SECURING A FLASH MEMORY FROM DATA DAMAGE - A method for securing a flash memory from data damage is provided. After writing of data to a plurality of written pages of a first block of a flash memory is completed, a last weak page of the written pages is determined. A first strong page corresponding to the last weak page is then determined. A plurality of strong pages between the first strong page and the last weak page are then determined. Data of the plurality of strong pages is the coped to a backup area of the flash memory for data recovery.01-07-2010
20090049234SOLID STATE MEMORY (SSM), COMPUTER SYSTEM INCLUDING AN SSM, AND METHOD OF OPERATING AN SSM - In one aspect, data is stored in a solid state memory which includes first and second memory layers. A first assessment is executed to determine whether received data is hot data or cold data. Received data which is assessed as hot data during the first assessment is stored in the first memory layer, and received data which is first assessed as cold data during the first assessment is stored in the second memory layer. Further, a second assessment is executed to determine whether the data stored in the first memory layer is hot data or cold data. Data which is then assessed as cold data during the second assessment is migrated from the first memory layer to the second memory layer.02-19-2009
20100049907Memory System and Control Method Thereof - A memory system includes a nonvolatile memory including a plurality of blocks as data erase units, a measuring unit which measures an erase time at which data of each block is erased, and a block controller which writes data supplied from at least an exterior into a first block which is set in a free state and whose erase time is oldest.02-25-2010
20100017554SYSTEM AND METHOD FOR MANAGING A PLUGGED DEVICE - An electronic device is provided including a non-volatile memory, a connection interface, a processor and at least one resource. The at least one resource has at least one configuration. The non-volatile memory stores the configuration for the resource. The processor generates the configuration for the resource. When plugged into the host device through the connection interface, the electronic device receives a request from the host device and performs an operation in the resource using the configuration.01-21-2010
20110219180FLASH MEMORY DEVICE WITH MULTI-LEVEL CELLS AND METHOD OF WRITING DATA THEREIN - In one aspect, a method of writing data in a flash memory system is provided. The flash memory system forms an address mapping pattern according to a log block mapping scheme. The method includes determining a writing pattern of data to be written in a log block, and allocating one of SLC and MLC blocks to the log block in accordance with the writing pattern of the data.09-08-2011
20110167198NON-VOLATILE STORAGE ALTERATION TRACKING - A method for tracking alteration of a non-volatile storage includes receiving a request to modify a tracked region of the non-volatile storage. In response to the request, it is determined whether or not a modification of data stored in a non-erasable one-time programmable (NEOTP) alteration log region has occurred. In response to determining that the modification of the data stored in the NEOTP alteration log region has occurred, the tracked region of non-volatile storage is modified in response to the request. In response to determining that the modification of the data stored in the NEOTP alteration log region has not occurred, the request to modify the tracked region of the non-volatile memory is denied.07-07-2011
20120233388DATA WRITING METHOD FOR NON-VOLATILE MEMORY, AND CONTROLLER AND STORAGE SYSTEM USING THE SAME - A data writing method for writing data from a host system into a plurality of memory dies of a rewritable non-volatile memory storage apparatus is provided. The data writing method includes determining whether the data transmission interface of the host system complies with a first interface standard or a second interface standard. The data writing method also includes using a general mode to write the data into the memory dies when the data transmission interface of the host system complies with the first interface standard and using a power saving mode to write the data into the memory dies when the data transmission interface of the host system complies with the second interface standard. Accordingly, the data writing method can effectively prevent the stability of the rewritable non-volatile memory storage apparatus from reducing due to insufficient power supplied by the data transmission interface.09-13-2012
20110283054NONVOLATILE MEMORY - For a nonvolatile memory permitting electrical writing and erasing of information to be stored, such as a flash memory, the load on the system developer is to be reduced, and it is to be made possible to avoid, even if such important data for the system as management and address translation information are damaged, an abnormal state in which the system becomes unable to operate. The nonvolatile memory is provided with a replacing function to replace a group of memory cells including defective memory cells which are incapable of normal writing or erasion with a group of memory cells including no defective memory cell, a numbers of rewrites averaging function to grasp the number of data rewrites in each group of memory cells and to so perform replacement of memory cell groups that there may arise no substantial difference in the number of rewrites among a plurality of memory cell groups, and an error correcting function to detect and correct any error in data stored in the memory array, wherein first address translation information deriving from the replacing function and second address translation information deriving from the numbers of rewrites averaging function are stored in respectively prescribed areas in the memory array, and the first address translation information and second address translation information concerning the same memory cell group are stored in a plurality of sets in a time series.11-17-2011
20110283046STORAGE DEVICE - The present invention aims to improve the performance of accessing flash memory used as a storage medium in a storage device. In the storage device in accordance with the present invention, a storage controller, before accessing the flash memory, queries a flash controller as to whether the flash memory is accessible (see FIG. 11-17-2011
20110283058STORAGE APPARATUS AND METHOD OF MANAGING DATA STORAGE AREA - To extend endurance and reduce bit cost, a method and a storage apparatus are provided, which storage apparatus includes a controller and a semiconductor storage media that includes a first storage device and a second storage device having an upper limit of an erase count of data smaller than the first storage device. Area conversion information includes correspondence of a first address to be specified as a data storage destination and a second address of an area in which data is to be stored. A rewrite frequency of stored data is recorded for each area. The controller selects an area corresponding to the first address, determines whether or not the rewrite frequency of the selected area is equal to or larger than a first threshold value, when the rewrite frequency is equal to or larger than the threshold value, selects an area to be provided by the first storage device, and when the rewrite frequency is smaller than the threshold value, selects an area to be provided by the second storage device and maps the address of the selected area to the first address.11-17-2011
20110283057Microcontroller Programmable System on a Chip - Embodiments of the present invention are directed to a microcontroller device having a microprocessor, programmable memory components, and programmable analog and digital blocks. The programmable analog and digital blocks are configurable based on programming information stored in the memory components. Programmable interconnect logic, also programmable from the memory components, is used to couple the programmable analog and digital blocks as needed. The advanced microcontroller design also includes programmable input/output blocks for coupling selected signals to external pins. The memory components also include user programs that the embedded microprocessor executes. These programs may include instructions for programming the digital and analog blocks “on-the-fly,” e.g., dynamically. In one implementation, there are a plurality of programmable digital blocks and a plurality of programmable analog blocks.11-17-2011
20110283056INFORMATION MANAGEMENT APPARATUS AND INFORMATION MANAGING METHOD - An information management apparatus for managing data includes a rewritable nonvolatile memory, and a memory controller configured to control inputting information into and outputting information from the nonvolatile memory. The memory controller overwrites a data, which includes a first validity check information, a first data body, a second validity check information, a second data body having the same data as the first data body and a third validity check information arranged in this order, in a designated address area in the nonvolatile memory when the memory controller performs a writing control in which the memory controller writes data in the nonvolatile memory.11-17-2011
20110283049SYSTEM AND METHOD FOR MANAGING GARBAGE COLLECTION IN SOLID-STATE MEMORY - Embodiments of the invention are directed to optimizing the selection of memory blocks for garbage collection to maximize the amount of memory freed by garbage collection operations. The systems and methods disclosed herein provide for the efficient selection of optimal or near-optimal garbage collection candidate blocks, with the most optimal selection defined as block(s) with the most invalid pages. In one embodiment, a controller classifies memory blocks into various invalid block pools by the amount of invalid pages each block contains. When garbage collection is performed, the controller selects a block from a non-empty pool of blocks with the highest minimum amount of invalid pages. The pools facilitate the optimal or near-optimal selection of garbage collection candidate blocks in an efficient manner and the data structure of the pools can be implemented with bitmasks, which take minimal space in memory.11-17-2011
20110283055Exclusive-Option Chips and Methods with All-Options-Active Test Mode - A multi-interface integrated circuit in which, during the chip's lifetime in use, only one interface is active at a time. However, special test logic powers up all of the on-chip interface modules at once, so that a complete test cycle can be performed. All of the interfaces are exercised in one test program. Since some pads are inactive in some interface modes, mask bits are used to select which pads are monitored during which test cycles.11-17-2011
20110283053SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR MEMORY SYSTEM - A semiconductor memory device that stores information includes: a flash memory that is managed by a predetermined file system having a parameter dependent on the semiconductor memory device; a rewrite frequency storage unit that stores a rewrite frequency of the flash memory; an ID detection unit that detects whether or not first identification information associated with the rewrite frequency is stored in the flash memory as the parameter; and a control unit that, when the ID detection unit detects that the first identification information is stored, reflects the rewrite frequency stored in the rewrite frequency storage unit, on a storage area corresponding to the first identification information.11-17-2011
20110283051MOVING EXECUTABLE CODE FROM A FIRST REGION OF A NON-VOLATILE MEMORY TO A SECOND REGION OF THE NON-VOLATILE MEMORY - A data storage device includes a controller and a non-volatile memory coupled to the controller. The non-volatile memory includes executable boot code that is executable by a processor associated with the data storage device. The controller is configured to read a first portion of the executable boot code from a first region of the non-volatile memory, and in response to detecting a condition, move a second portion of the executable boot code in a second region of the non-volatile memory to a third region of the non-volatile memory.11-17-2011
20100268871NON-VOLATILE MEMORY CONTROLLER PROCESSING NEW REQUEST BEFORE COMPLETING CURRENT OPERATION, SYSTEM INCLUDING SAME, AND METHOD - A non-volatile memory controller, system and method capable of processing a next request as an interrupt before completing a current operation are disclosed. The non-volatile memory system includes a first memory storing meta data loaded from a flash memory; a second memory storing the meta data copied from the first memory; and a flash memory controller copying the meta data from the first memory to the second memory, changing the meta data in the second memory, and then re-copying the changed meta data from the second memory to the first memory during a first-type operation that requires changes in the meta data.10-21-2010
20100268865Static Wear Leveling - Methods for extending the service life of a data storage device and devices operable to perform those methods are presented. A master lookup table block may comprise lookup table blocks and store an erase count indicator for each lookup table block. Each lookup table block may be associated with a logical zone of a memory and comprise entries. Each entry may be associated with a logical block and comprise an erase count for a physical block corresponding to that logical block. A physical block erasure may be performed on a first physical block in the memory. The physical block erasure may be tracked by incrementally increasing a first erase count. An actual erase count may be determined for the first physical block. The entry for a logical block corresponding to the first physical block may be exchanged with another entry within a different lookup table block when the actual erase count for the first physical block exceeds a threshold. The different lookup table block may have a lower erase count indicator relative to that of the lookup table block comprising the entry for the logical block corresponding to the first physical block.10-21-2010
20110040924Controller and Method for Detecting a Transmission Error Over a NAND Interface Using Error Detection Code - The embodiments described herein provide a controller and method for detecting a transmission error over a NAND interface using error detection code. In one embodiment, a controller receives a write command, data, and an error detection code associated with the data from a host through a first NAND interface of the controller using a NAND interface protocol. The controller uses the error detection code to detect if a transmission error occurred. In another embodiment, a controller generates an error detection code based on data read from a flash memory device and provides the data and error detection code to a host through a first NAND interface of the controller, so the host can detect if a transmission error occurred.02-17-2011
20110173373NON-VOLATILE MEMORY DEVICE AND METHOD THEREFOR - A method of storing information at a non-volatile memory includes storing a first status bit at a sector header of the memory prior to erasing a sector at the memory. A second status bit is stored after erasing of the sector. Because the erasure of the sector is interleaved with the storage of the status bits, a brownout or other corrupting event during erasure of the record will likely result in a failure to store the second status bit. Therefore, the first and second status bits can be compared to determine if the data was properly erased at the non-volatile memory. Further, multiple status bits can be employed to indicate the status of other memory sectors, so that a difference in the status bits for a particular sector can indicate a brownout or other corrupting event.07-14-2011
20130046919NON-VOLATILE MEMORY SYSTEM - In one embodiment, a memory system includes a memory device with a first memory and a second memory, and a controller configured to control storing of data in the memory device. The controller is configured to control an (N−02-21-2013
20080307154System and Method for Dual-Ported I2C Flash Memory - A method for emulating a dual-port I2C device includes monitoring a bus for I2C traffic. A system receives an I2C interrupt on the bus. The system determines whether the received I2C interrupt is one of either a hardware interrupt or a software interrupt. In the event the received I2C interrupt is a hardware interrupt, the system responds to the hardware interrupt, and accesses a flash memory for read/write operation based on the hardware interrupt. In the event the received I2C interrupt is a software interrupt, the system responds to the software interrupt, and accesses a flash memory for read/write operation based on the software interrupt.12-11-2008
20120297111Non-Volatile Memory And Method With Improved Data Scrambling - A memory device cooperating with a memory controller scrambles each unit of data using a selected scrambling key before storing it in an array of nonvolatile memory cells. This helps to reduce program disturbs, user read disturbs, and floating gate to floating gate coupling that result from repeated and long term storage of specific data patterns. For a given page of data having a logical address and for storing at a physical address, the key is selected from a finite sequence thereof as a function of both the logical address and the physical address. In a block management scheme the memory array is organized into erase blocks, the physical address is the relative page number in each block. When logical address are grouped into logical groups and manipulated as a group and each group is storable into a sub-block, the physical address is the relative page number in the sub-block.11-22-2012
20110302356SCALABLE MEMORY INTERFACE SYSTEM - A memory interface system can include a memory controller configured to operate at a first operating frequency. A physical interface block can be coupled to the memory controller. The physical interface block can be configured to communicate with the memory controller at the first operating frequency and communicate with a memory device at a second operating frequency that is independent of the first operating frequency.12-08-2011
20110302364DATA WRITING METHOD FOR NON-VOLATILE MEMORY AND CONTROLLER USING THE SAME - A data writing method for a non-volatile memory is provided, wherein the non-volatile memory includes a data area and a spare area. In the data writing method, a plurality of blocks in a substitution area of the non-volatile memory is respectively used for substituting a plurality of blocks in the data area, wherein data to be written into the blocks in the data area is written into the blocks in the substitution area, and the blocks in the substitution area are selected from the spare area of the non-volatile memory. A plurality of temporary blocks of the non-volatile memory is used as a temporary area of the blocks in the substitution area, wherein the temporary area is used for temporarily storing the data to be written into the blocks in the substitution area.12-08-2011
20110302361MEMORY SYSTEM AND METHOD OF CONTROLLING MEMORY SYSTEM - A plurality of free-block management lists for respectively managing a logical block with a same bank number, a same chip number, and a same plane number as a free block, and a free block selecting unit that selects a required number of free-block management lists from the free-block management lists to obtain a free block from the selected free-block management lists are provided, thereby improving writing efficiency.12-08-2011
20110302360METHODS AND APPARATUS FOR REALLOCATING ADDRESSABLE SPACES WITHIN MEMORY DEVICES - Integrated circuit systems include a non-volatile memory device (e.g, flash EEPROM device) and a memory processing circuit. The memory processing circuit is electrically coupled to the non-volatile memory device. The memory processing circuit is configured to reallocate addressable space within the non-volatile memory device. This reallocation is performed by increasing a number of physical addresses within the non-volatile memory device that are reserved as redundant memory addresses, in response to a capacity adjust command received by the memory processing circuit.12-08-2011
20110302358Flash-Memory Device with RAID-type Controller - A smart flash drive has one or more levels of smart storage switches and a lower level of single-chip flash devices (SCFD's). A SCFD contains flash memory and controllers that perform low-level bad-block mapping and wear-leveling and logical-to-physical block mapping. The SCFD report their capacity, arrangement, and maximum wear-level count (WLC) and bad block number (BBN) to the upstream smart storage switch, which stores this information in a structure register. The smart storage switch selects the SCFD with the maximum BBN as the target and the SCFD with the lowest maximum WLC as the source of a swap for wear leveling when a WLC exceeds a threshold that rises over time. A top-level smart storage switch receives consolidated capacity, arrangement, WLC, and BBN information from lower-level smart storage switch. Data is striped and optionally scrambled by Redundant Array of Individual Disks (RAID) controllers in all levels of smart storage switches.12-08-2011
20110302359METHOD FOR MANAGING FLASH MEMORIES HAVING MIXED MEMORY TYPES - A method manages a flash memory having a plurality of physical blocks. The blocks of the memory are addressed by logic block addresses which are converted into physical block addresses. In each block a deletion counter is run in which the number of deletions of the block is counted, and two regions having different types of flash chips are present. A first region contains single-level flash chips with a large maximum deletion frequency, and a second region contains multi-level flash chips with a lower maximum deletion frequency. When writing to the memory the address conversion of the logic addresses into physical addresses is carried out such that all blocks of the first region are written, when all blocks of the first region have been written and a further writing process is initiated, the block in the first region having the lowest deletion counter is copied into a blank block in the second region.12-08-2011
20110302357SYSTEMS AND METHODS FOR DYNAMIC MULTI-LINK COMPILATION PARTITIONING - Systems and methods for dynamic multi-link compilation partitioning. In particular, some implementations of the present invention relate to systems and methods for connecting a computer processing unit to a video display through the use of a wide variety of video display connectors. The present invention further relates to a dynamic interface incorporating USB, PCI-express, SATA, I12-08-2011
20110302354SYSTEMS AND METHODS FOR RELIABLE MULTI-LEVEL CELL FLASH STORAGE - Multi-level cell (MLC) flash memory has become widely used due to their capacity to store more information in the same area as a single-level cell (SLC) flash memory. This makes MLC flash memory very attractive for storing media. Flash has also traditionally been used in electronic devices for firmware, but MLC flash is less reliable than SLC flash. For critical memory operations, MLC flash memory can be made as reliable as SLC flash by mapping one binary value to an MLC state corresponding to the highest threshold voltage and the other binary value to the MLC state corresponding the lowest threshold voltage when writing to the MLC flash, and by mapping all MLC states with corresponding threshold voltages above a central cutoff threshold voltage to one binary value and by mapping all MLC states with corresponding threshold voltages below a central cutoff threshold voltage to the other binary value.12-08-2011
20110302355MAPPING AND WRITTING METHOD IN MEMORY DEVICE WITH MULTIPLE MEMORY CHIPS - The invention is directed to a mapping method in a memory device with a plurality of memory chips in a sequence of 0 to K, K≧1. Each of the memory chips has a plurality of data blocks. The mapping method includes setting a block sequence number “(K+1)*n” to the (n+1)12-08-2011
20110302353NON-VOLATILE MEMORY WITH EXTENDED OPERATING TEMPERATURE RANGE - A method and apparatus are described for measuring a temperature within a non-volatile memory and refreshing at least a portion of the non-volatile memory when the temperature exceeds a threshold temperature for an amount of time.12-08-2011
20120005415MEMORY SYSTEM SELECTING WRITE MODE OF DATA BLOCK AND DATA WRITE METHOD THEREOF - A method of performing a write operation in a nonvolatile memory device comprises storing write data in a log block used to update a data block, determining whether a write pattern stored in the log block is a sequential write pattern or a random write pattern, and selecting a new data block for storing merged data in the data block and the log block. The new data block is determined to be a single-level cell block or a multi-level cell block according to the determined write pattern.01-05-2012
20120005402STORAGE SYSTEM HAVING A PLURALITY OF FLASH PACKAGES - A storage system 01-05-2012
20110167208NONVOLATILE MEMORY DEVICE, ACCESS DEVICE, NONVOLATILE MEMORY SYSTEM, AND MEMORY CONTROLLER - The nonvolatile memory device prevents data writing from temporarily slowing down significantly in the middle of writing data to a block when an access device writes all the data in the block in units of a smaller size than the block. The nonvolatile memory device (07-07-2011
20110167199TECHNIQUES FOR PROLONGING A LIFETIME OF MEMORY BY CONTROLLING OPERATIONS THAT AFFECT THE LIFETIME OF THE MEMORY - Techniques are provided for prolonging a lifetime of memory by controlling operations that affect the lifetime of the memory. At least one aspect associated with the memory lifetime is identified and at least one of the operations is delayed, based on the at least one aspect. The operations include a write operation, an erase operation, a program operation, and/or any other operation that is capable of reducing the memory lifetime.07-07-2011
20120159047COMPUTING DEVICE AND METHOD FOR MERGING STORAGE SPACE OF USB FLASH DRIVES - A method for merging storage space of multiple universal serial bus (USB) flash drives is applied in a computing device. The method detects USB flash drives plugged into USB ports of the computing device and checks respective storage capacities, stored files, and available storage space of the USB flash drives. A virtual USB flash drive including all the stored files of the USB flash drives is created. Files of the virtual USB flash drive are related to the USB flash drives. A file may be copied from a data processing device connected to the computing device to the virtual USB flash drive and split for storage between more than one USB flash drive, or a second file may be copied from one or more USB flash drives to the data processing device through the virtual USB flash drive.06-21-2012
20120159042DATA STORAGE DEVICE EXECUTING A UNITARY COMMAND COMPRISING TWO CIPHER KEYS TO ACCESS A SECTOR SPANNING TWO ENCRYPTION ZONES - A data storage device is disclosed comprising a non-volatile memory (NVM) including a plurality of sectors each having a sector size. An access command is received from a host, wherein the access command identifies a plurality of host blocks having a host block size less than the sector size. A plurality of the host blocks are mapped to a target sector. When the target sector spans an encryption zone boundary defined by the host blocks, a NVM command is generated identifying a first key corresponding to a first encryption zone and a second key corresponding to a second encryption zone. The NVM command is executed as a unitary operation to access a first part of the target sector using the first key and access a second part of the target sector using the second key.06-21-2012
20090100217Portable Data Transfer and Mass Storage Device for Removable Memory Modules - A hand-held battery powered device for transferring data between one or more flash memory modules and a mass storage device. The device includes one or more slots to accept a flash memory module into a housing which includes fixed or removable mass storage device and logic circuitry disposed within the housing for transferring data between the flash memory module and mass storage device. Ports are disclosed for transferring data from the resident mass storage device to the user's computer.04-16-2009
20110289262CONTROLLER FOR SOLID STATE DISK, WHICH CONTROLS SIMULTANEOUS SWITCHING OF PADS - Provided is a controller for a solid state disk, to control simultaneous switching of pads. The controller for the solid state disk may control simultaneous switching of a plurality of output pads or a plurality of input pads that correspond to a plurality of channels. In particular, the controller may properly delay signals driven to the output pads or input pads, to reduce power supplied to the pads, and to prevent ground bouncing, as well as, maintain a quality of signals.11-24-2011
20110289267APPARATUS, SYSTEM, AND METHOD FOR SOLID-STATE STORAGE AS CACHE FOR HIGH-CAPACITY, NON-VOLATILE STORAGE - An apparatus, system, and method are disclosed for solid-state storage as cache for high-capacity, non-volatile storage. The apparatus, system, and method are provided with a plurality of modules including a cache front-end module and a cache back-end module. The cache front-end module manages data transfers associated with a storage request. The data transfers between a requesting device and solid-state storage function as cache for one or more HCNV storage devices, and the data transfers may include one or more of data, metadata, and metadata indexes. The solid-state storage may include an array of non-volatile, solid-state data storage elements. The cache back-end module manages data transfers between the solid-state storage and the one or more HCNV storage devices.11-24-2011
20110289264Memory System Having Nonvolatile and Buffer Memories, and Reading Method Thereof - Disclosed is a method for reading data in a memory system including a buffer memory and a nonvolatile memory, the method being comprised of: determining whether an input address in a read request is allocated to the buffer memory; determining whether a size of requested data is larger than a reference unless the input address is allocated to the buffer memory; and conducting a prefetch reading operation from the nonvolatile memory if the requested data size is larger than the reference.11-24-2011
20110289261METHOD AND SYSTEM FOR A STORAGE AREA NETWORK - In a system and method for a storage area network (SAN), a first controller receives a write request for a SAN an communicates with a first nested storage array module (NSAM), the first NSAM manages storage of data onto a shelf and presents the shelf as a logical unit, a buffer stores a portion of a write request from the first controller and aggregates data from the write request for the shelf, from a shelf with a second NSAM, the second NSAM provides a portion of data from the buffer to a third NSAM, the third NSAM manages storage of the portion of data from the buffer to a physical storage unit, and a second controller coupled to the first controller handles requests for the SAN in response to a failure of the first controller.11-24-2011
20110289259MEMORY SYSTEM CAPABLE OF ENHANCING WRITING PROTECTION AND RELATED METHOD - A memory system is disclosed. The memory system includes a memory device, a first control unit, and a second control unit. The memory device is utilized for storing data. The first control unit is coupled to the memory device for prohibiting a data writing process performed on the memory device during a writing protection period. The second control unit is coupled to the memory device for allowing the data writing process to be performed in the memory device according to a writing period after the writing protection period, wherein the writing period is related to the data writing process.11-24-2011
20110289266GARBAGE COLLECTION IN STORAGE DEVICES BASED ON FLASH MEMORIES - A solution for managing a storage device based on a flash memory is proposed. A corresponding method starts with the step for mapping a logical memory space of the storage device (including a plurality of logical blocks) on a physical memory space of the flash memory (including a plurality of physical blocks, which are adapted to be erased individually). The physical blocks include a set of first physical blocks (corresponding to the logical blocks) and a set of second—or spare—physical blocks (for replacing each bad physical block that is unusable). The method continues by detecting each bad physical block. Each bad physical block is then discarded, so to prevent using the bad physical block for mapping the logical memory space.11-24-2011
20110289265STORAGE SYSTEM AND STORAGE MANAGEMENT METHOD FOR CONTROLLING OFF-LINE MODE AND ON-LINE OF FLASH MEMORY - An object of the present invention is to provide a storage system and storage management method, which prevent a problem in the operation of stored data from being caused by unknown states of volume information and life information, when flash memories are placed in off-line mode and again placed in on-line mode. According to the present invention, there is provided a storage system 11-24-2011
20110289260METHOD FOR PERFORMING BLOCK MANAGEMENT USING DYNAMIC THRESHOLD, AND ASSOCIATED MEMORY DEVICE AND CONTROLLER THEREOF - A method for performing block management is provided. The method is applied to a controller of a Flash memory, where the Flash memory includes a plurality of blocks. The method includes: adjusting a dynamic threshold according to at least one condition; and comparing a valid/invalid page count of a specific block of the plurality of blocks with the dynamic threshold to determine whether to erase the specific block. An associated memory device and a controller thereof are also provided, where the memory device includes the Flash memory and the controller. In particular, the controller includes a read only memory (ROM) arranged to store a program code, and further includes a microprocessor arranged to execute the program code to control access to the Flash memory and manage the plurality of blocks, where under control of the microprocessor, the controller operates according to the method.11-24-2011
20120089767STORAGE DEVICE AND RELATED LOCK MODE MANAGEMENT METHOD - A storage device comprises at least one nonvolatile memory and a lock mode management module. The lock mode management module places the storage device in a soft lock mode in which only predetermined writing operations are allowed, upon determining that a number of reserved blocks in a flash memory is less than or equal to a reference value.04-12-2012
20090125668Management of erased blocks in flash memories - The invention relates to a method for managing the erasure process in a memory system comprising individually erasable memory blocks (SB) that can be addressed with the aid of real memory block addresses (SBA). Said memory blocks are sub-divided into a plurality of writable sectors and can be addressed by means of an address conversion that uses an allocator table (ZT) to convert logical block addresses (LBA) into one of the respective memory block addresses (SBA). According to the invention, the allocator table (ZT) is sub-divided into at least one useful data area (NB) and a buffer block area (BB). The invention is characterised in that a first identifier erased (ER), indicating the physical erasure status and a second identifier content erased (CER), indicating the logical erasure status, is set for each memory block (SB) in the allocator table (ZT).05-14-2009
20110296094CIRCULAR WEAR LEVELING - A method for flash memory management comprises providing a head pointer configured to define a first location in a flash memory, and a tail pointer configured to define a second location in a flash memory. The head pointer and tail pointer define a payload data area. Payload data is received from a host, and written to the flash memory in the order it was received. The head pointer and tail pointer are updated such that the payload data area moves in a circular manner within the flash memory.12-01-2011
20110296090Combining Memory Operations - Systems and processes may include a memory coupled to a memory controller. Command signals for performing memory access operations may be received. Attributes of the command signals, such as type, time lapsed since receipt, and relatedness to other command signals, may be determined. Command signals may be sequenced in a sequence of execution based on the attributes. Command signals may be executed in the sequence of execution.12-01-2011
20110296092Storing a Driver for Controlling a Memory - Systems and techniques for accessing a memory, such as a NAND or NOR flash memory, involve storing an operating application for a computing device in a first memory and storing a driver containing software operable to control the first memory in a second memory that is independently accessible from the first memory. By storing the driver in a second memory that is independently accessible from the first memory, changes to the driver and/or the first memory can be made without altering the operating application.12-01-2011
20110296093PROGRAM AND SENSE OPERATIONS IN A NON-VOLATILE MEMORY DEVICE - Methods for programming and sensing in a memory device, a data cache, and a memory device are disclosed. In one such method, all of the bit lines of a memory block are programmed or sensed during the same program or sense operation by alternately multiplexing the odd or even page bit lines to the dynamic data cache. The dynamic data cache comprises dual SDC, PDC, DDC1, and DDC2 circuits such that one set of circuits is coupled to the odd page bit lines and the other set of circuits is coupled to the even page bit lines.12-01-2011
20110296086FLASH MEMORY HAVING TEST MODE FUNCTION AND CONNECTION TEST METHOD FOR FLASH MEMORY - A flash memory including a controller, the controller including: a state machine; a state decoder that determines whether a state of the state machine is in a specified mode; a command decoder that determines whether an input signal received through an external pin specifies a write operation for writing a specific value into a specific address; and a test mode setting circuit that sets a test mode while the specified mode is maintained when the state decoder determines that the state of the state machine is in the specified mode and when the command decoder determines that the input signal received through the external pin specifies a write operation for writing a specific value into a specific address.12-01-2011
20110296091STORAGE SYSTEM WHICH UTILIZES TWO KINDS OF MEMORY DEVICES AS ITS CACHE MEMORY AND METHOD OF CONTROLLING THE STORAGE SYSTEM - Provide is a storage system including one or more disk drives, and one or more cache memories for temporarily storing data read from the disk drives or data to be written to the disk drives, in which: the cache memories includes volatile first memories and non-volatile second memories; and the storage system receives a data write request, stores the requested data in the volatile first memories, selects one of memory areas of the volatile first memories if a total capacity of free memory areas contained in the volatile first memories is less than a predetermined threshold, write data stored in the selected memory area in the non-volatile second memories, and changes the selected memory area to a free memory area. Accordingly, there can be realized capacity enlarging of the cache memory using a non-volatile memory device while realizing a high speed similar to that of a volatile memory device.12-01-2011
20110296089PROGRAMMING METHOD AND DEVICE FOR A BUFFER CACHE IN A SOLID-STATE DISK SYSTEM - Provided are a method and apparatus for programming a buffer cache in a Solid State Disk (SSD) system. The buffer cache programming apparatus in the SSD system may include a buffer cache unit to store pages, a memory unit including a plurality of memory chips, and a control unit to select at least one of the page as a victim page, based on a delay occurring when a page is stored in at least one target memory chip among the plurality of memory chips.12-01-2011
20110296088MEMORY MANAGEMENT STORAGE TO A HOST DEVICE - Systems and methods of memory management storage to a host device are disclosed. A method is performed in a data storage device with a non-volatile memory and a controller operative to manage the non-volatile memory and to generate management data for managing the non-volatile memory. The method includes performing, at a given time, originating at the controller data management transfer to a host device or originating at the controller data management retrieval from the host device.12-01-2011
20110296085CACHE MEMORY MANAGEMENT IN A FLASH CACHE ARCHITECTURE - Provided are a system, method, and computer program product for managing cache memory to cache data units in at least one storage device. A cache controller is coupled to at least two flash bricks, each comprising a flash memory. Metadata indicates a mapping of the data units to the flash bricks caching the data units, wherein the metadata is used to determine the flash bricks on which the cache controller caches received data units. The metadata is updated to indicate the flash brick having the flash memory on which data units are cached.12-01-2011
20110296084DATA STORAGE APPARATUS AND METHOD OF WRITING DATA - According to one embodiment, a data storage apparatus includes a flash memory and a controller for controlling the flash memory. The flash memory is configured to store data is written in units of a prescribed size. In order to write data smaller than the prescribe size, the controller first isolates attribute data from each save data item of the prescribed size, which has been read from any flash memory, and then stores the attribute data to an attribute data memory, and finally transfers the user data contained in the save data, to a save data memory.12-01-2011
20110296083DATA STORAGE APPARATUS AND METHOD OF CALIBRATING MEMORY - According to one embodiment, a data storage apparatus includes an interface module and a controller. The interface module is configured to control rewritable nonvolatile memories provided for the respective channels. The controller is configured to write calibration data to the nonvolatile memories of any channel designated, through the interface module at the same time, in order to perform calibration.12-01-2011
20110296082Method for Improving Service Life of Flash - A method for increasing service life of flash is provided. The method comprises the following steps: reading a data {T} from the flash, calculating and obtaining the corresponding old original data Bi according to the mapping relationship, wherein i is a natural number, j=(n−1)˜0, n is an even number; determining whether the data Bi to be written in is the same as the old original data Bi by comparison, if they are the same, it is not necessary to update the data of this byte in the flash; if the value of the data Bi to be written in is not the same as the value of the old original data Bi, checking whether it is possible to write into the flash directly; if possible, writing into the flash directly; and if it is impossible to write into the flash directly, performing the operation of erasing block.12-01-2011
20090193184Hybrid 2-Level Mapping Tables for Hybrid Block- and Page-Mode Flash-Memory System - A hybrid solid-state disk (SSD) has multi-level-cell (MLC) or single-level-cell (SLC) flash memory, or both. SLC flash may be emulated by MLC that uses fewer cell states. A NVM controller converts logical block addresses (LBA) to physical block addresses (PBA). Most data is block-mapped and stored in MLC flash, but some critical or high-frequency data is page-mapped to reduce block-relocation copying. A hybrid mapping table has a first-level and a second level. Only the first level is used for block-mapped data, but both levels are used for page-mapped data. The first level contains a block-page bit that indicates if the data is block-mapped or page-mapped. A PBA field in the first-level table maps block-mapped data, while a virtual field points to the second-level table where the PBA and page number is stored for page-mapped data. Page-mapped data is identified by a frequency counter or sector count. SRAM space is reduced.07-30-2009
20110296081DATA ACCESSING METHOD AND RELATED CONTROL SYSTEM - A data access method and a related control system are provided according to embodiments of the present invention, which enhances the read/write performance of a data storage unit by performing pre-accessing operations upon the data storage unit. The data access method includes receiving a plurality of access requests and a plurality of corresponding addresses to access a plurality of data corresponding to the plurality of access requests from a storage unit; and performing a pre-accessing operation upon the storage unit according to the uniformity of the plurality of access requests and the continuity between the plurality of addresses.12-01-2011
20110296080Method Of Writing To A NAND Memory Block Based File System With Log Based Buffering - A method of operating a controller for controlling the programming of a NAND memory chip is shown. The NAND memory chip has a plurality of blocks with each block having a certain amount of storage, wherein the amount of storage in each block is the minimum erasable unit. The method comprising storing in a temporary storage a first plurality of groups of data, wherein each of the groups of data is to be stored in a block of the NAND memory chip. Each group of data is indexed to the block with which it is to be stored. Finally, the groups of data associated with the same block are programmed into the same block in the same programming operation.12-01-2011
20110296079System and Method for Emulating Preconditioning of Solid-State Device - Systems and methods for reducing problems and disadvantages associated with traditional approaches to preconditioning solid-state devices are provided. A method may include storing at least one preconditioning status parameter indicative of at least one variable associated with preconditioning emulation of a solid state device (SSD) including a flash memory. The method may also include modifying a mapping table based on the at least one preconditioning status parameter to emulate preconditioning of the SSD, the mapping table including information for translating virtual logical block addresses (LBAs) of the SSD as seen by the processor into physical LBAs of the flash memory.12-01-2011
20090193179Information processing apparatus - A main memory and a hard disk include predetermined serial numbers. A flash memory registers the main memory and hard disk together with their serial numbers. A BIOS reads the serial numbers from the main memory and hard disk. When a read-out serial number is not registered in the flash memory, the BIOS places the information processing apparatus in an unusable state.07-30-2009
20110208895METHODS FOR MEMORY PROGRAMMING DURING PRODUCT ASSEMBLY - A method of writing data to an electronic device during assembly comprises attaching a resident memory element to one or more contact pads of a circuit board using a solder paste; reflowing the solder paste to affix the resident memory element to the contact pads; copying data from an external memory element to the resident memory element; and thereafter combining a device component with the circuit board to at least partially complete assembly of the electronic device.08-25-2011
20110173374SOLID-STATE MEMORY MANAGEMENT - An exemplary method includes performing flash memory operations; receiving a signal from a voltage monitor as being associated with the performed flash memory operations; and, based at least in part on the received signal, setting a limit for performing subsequent flash memory operations. In such a method, the limit can act to avoid resetting flash memory responsive to current demand associated with subsequent flash memory operations. Various other apparatuses, systems, methods, etc., are also disclosed.07-14-2011
20130219107WRITE ABORT RECOVERY THROUGH INTERMEDIATE STATE SHIFTING - A memory system or flash card may include a multi-level cell block with multiple states. Before the upper page is written, an intermediate state may be shifted to prevent or minimize overlapping of the states from the corresponding lower page. A write abort during the writing of the upper page will not result in a loss of data from the corresponding lower page.08-22-2013
20130219111SYSTEM AND METHOD FOR READ-WHILE-WRITE WITH NAND MEMORY DEVICE - System, method, and program to perform simultaneous read and write operations in a NAND-type memory device, including: assigning a first partition in a NAND-type memory device, wherein the first partition is configured to perform read operations on high priority read content; assigning a second partition in the NAND-type memory device, wherein the second partition is configured to perform read operations and write operations, wherein the read operations are performed on non-high priority read content; and controlling the first partition and second partition to operate in a simultaneous manner.08-22-2013
20090125672MEMORY CARD AND HOST DEVICE THEREOF - A memory card is attached to a host device, and includes a data control circuit which transfers data with respect to the host device in synchronism with a rise edge and a fall edge of a clock signal.05-14-2009
20100088464Compression Based Wear Leveling for Non-Volatile Memory - The present disclosure includes systems and techniques relating to non-volatile memory. Systems and techniques can include obtaining information to store in a non-volatile memory, the information including a data segment, compressing data within the data segment, including pad data in one or more portions of the data segment based on a compression result attained by the compression, and writing data of the data segment.04-08-2010
20080270681Non-Volatile Memory with Block Erasable Locations - A main memory (10-30-2008
20100082884MEMORY CELL OPERATION - The present disclosure includes memory devices and systems having memory cells, as well as methods for operating the memory cells. One or more methods for operating memory cells includes determining age information for a portion of the memory cells and communicating a command set for the portion of the memory cells, the command set including the age information.04-01-2010
20090177833Buffering systems methods for accessing multiple layers of memory in integrated circuits - Embodiments of the invention relate generally to data storage and computer memory, and more particularly, to systems, integrated circuits and methods for accessing memory in multiple layers of memory implementing, for example, third dimension memory technology. In a specific embodiment, an integrated circuit is configured to implement write buffers to access multiple layers of memory. For example, the integrated circuit can include memory cells disposed in multiple layers of memory. In one embodiment, the memory cells can be third dimension memory cells. The integrated circuit can also include read buffers that can be sized differently than the write buffers. In at least one embodiment, write buffers can be sized as a function of a write cycle. Each layer of memory can include a plurality of two-terminal memory elements that retain stored data in the absence of power and store data as a plurality of conductivity profiles.07-09-2009
20100153632NON-VOLATILE MEMORY SYSTEM STORING DATA IN SINGLE-LEVEL CELL OR MULTI-LEVEL CELL ACCORDING TO DATA CHARACTERISTICS - Provided is a system storing data received from an application or file system in a non-volatile memory system of single-level cells and multi-level cells in accordance with one or more data characteristics. The non-volatile memory system includes a non-volatile memory cell array having a plurality of multi-level cells forming a MLC area and a plurality of single-level cells forming a SLC area, and an interface unit analyzing a characteristic of the write data and generating a corresponding data characteristic signal. A flash transition layer receives the data characteristic signal, and determines whether the write data should be stored in the MLC area or the SLC area based on whether or not the write data will be accessed by the file, or whether the address associated with the write data is frequently updated or not.06-17-2010
20100153621METHODS, COMPUTER PROGRAM PRODUCTS, AND SYSTEMS FOR PROVIDING AN UPGRADEABLE HARD DISK - Methods, computer program products and systems for providing an upgradeable hard disk. The system includes a plurality of memory card slots and a controller. The controller includes a host interface in communication with a host computer, a memory card interface in communication with one or more memory cards located in one or more of the memory card slots, and a detection mechanism. The detection mechanism monitors the memory card slots for newly added memory cards; and in response to detecting a newly added memory card determines characteristics of the newly added memory card and updates the data placement strategy in response to the characteristics of the newly added memory card. The data placement strategy is utilized by the controller to determine write locations for write data received from the host computer via the host interface.06-17-2010
20110264846SYSTEM OF INTERCONNECTED NONVOLATILE MEMORIES HAVING AUTOMATIC STATUS PACKET - An interconnection arrangement of nonvolatile memory devices is disclosed. In the arrangement, a plurality of memory devices are series-connected. A status of at least one of the plurality of memory devices is provided. The status includes “ready”, “busy”. The memory devices includes nonvolatile memories, such as, for example, flash memories.10-27-2011
20110219174Non-Volatile Memory and Method with Phased Program Failure Handling - In a memory with block management system, program failure in a block during a time-critical memory operation is handled by continuing the programming operation in a breakout block. Later, at a less critical time, the data recorded in the failed block prior to the interruption is transferred to another block, which could also be the breakout block. The failed block can then be discarded. In this way, when a defective block is encountered during programming, it can be handled without loss of data and without exceeding a specified time limit by having to transfer the stored data in the defective block on the spot. This error handling is especially critical for a garbage collection operation so that the entire operation need not be repeated on a fresh block during a critical time. Subsequently, at an opportune time, the data from the defective block can be salvaged by relocation to another block.09-08-2011
20110219171VIRTUAL CHANNEL SUPPORT IN A NONVOLATILE MEMORY CONTROLLER - A controller uses N dedicated ports to receive N signals from N non-volatile memories independent of each other, and uses a bus in a time shared manner to transfer data to and from the N non-volatile memories. The controller receives from a processor, multiple operations to perform data transfers, and stores the operations along with a valid bit set active by the processor. When a signal from a non-volatile memory is active indicating its readiness and when a corresponding operation has a valid bit active, the controller starts performance of the operation. When the readiness signal becomes inactive, the controller internally suspends the operation and starts performing another operation on another non-volatile memory whose readiness signal is active and for which an operation is valid. A suspended operation may be resumed any time after the corresponding readiness signal becomes active and on operation completion the valid bit is set inactive.09-08-2011
20100030950CYCLIC BUFFER MECHANISM FOR RECEIVING WIRELESS DATA UNDER VARYING DATA TRAFFIC CONDITIONS - A method of ensuring that data sent to a handheld wireless communications device is written to non-volatile memory is disclosed. In a device, where data is initially written to a first volatile memory and then written to a second volatile memory before being written from the second volatile memory to a non-volatile memory, software code is implemented that causes the writing of the data to non-volatile memory concurrently with the writing of the data to the second volatile memory. The software code may incorporate operating system commands (such as Windows OS).02-04-2010
20100011156MEMORY DEVICE AND MANAGEMENT METHOD OF MEMORY DEVICE - A memory device includes a plurality of blocks, and the plurality of blocks may include a plurality of pages. The memory device may translate an external physical address into internal physical address using a non-volatile address translation memory. The memory device may access one page of a plurality of pages using the internal physical address.01-14-2010
20110264847Data Writing Method and Data Storage Device - The invention provides a data writing method for a memory. In one embodiment, the memory comprises a data area and a spare area, the data area comprises a plurality of data blocks storing data, and the spare area comprises a plurality of spare blocks having no data stored therein. First, a write command for writing a write data to a first data block of the memory is received from a host. The spare blocks of the spare area are then sorted according to the erase counts of the spare blocks. A first spare block with the least erase counts is then selected from the spare blocks of the spare area. The write data is then written to the first spare block. Data is then erased from the first data block to convert the first data block to a spare block.10-27-2011
20110219179FLASH MEMORY DEVICE AND FLASH MEMORY SYSTEM INCLUDING BUFFER MEMORY - A flash memory device includes a flash memory and a buffer memory. The flash memory is divided into a main region and a spare region. The buffer memory is a random access memory and has the same structure as the flash memory. In addition, the flash memory device further includes control means for mapping an address of the flash memory applied from a host so as to divide a structure of the buffer memory into a main region and a spare region and for controlling the flash memory and the buffer memory to store data of the buffer memory in the flash memory or to store data of the flash memory in the buffer memory.09-08-2011
20110219170Method and Apparatus for Optimizing the Performance of a Storage System - Methods and apparatuses for optimizing the performance of a storage system comprise a FLASH storage system, a hard drive storage system, and a storage controller. The storage controller is adapted to receive READ and WRITE requests from an external host, and is coupled to the FLASH storage system and the hard drive storage system. The storage controller receives a WRITE request from an external host containing data and an address, forwards the received WRITE request to the FLASH storage system and associates the address provided in the WRITE request with a selected alternative address, and provides an alternative WRITE request, including the selected alternative address and the data received in the WRITE request, to the hard drive storage system, wherein the alternative address is selected to promote sequential WRITE operations within the hard drive storage system.09-08-2011
20110219169Buffer Pool Extension for Database Server - Aspects of the subject matter described herein relate to a buffer pool for a database system. In aspects, secondary memory such as solid state storage is used to extend the buffer pool of a database system. Thresholds such as hot, warm, and cold for classifying pages based on access history of the pages may be determined via a sampling algorithm. When a database system needs to free space in a buffer pool in main memory, a page may be evicted to the buffer pool in secondary memory or other storage based on how the page is classified and conditions of the secondary memory or other storage.09-08-2011
20110219168Flash Memory Hash Table - Implementations and techniques for flash memory-type hash tables are generally disclosed.09-08-2011
20090254696SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF OPERATION FOR SEMICONDUCTOR INTEGRATED CIRCUIT - The semiconductor IC has a nonvolatile memory including twin cells, a selector, and a sense circuit. When complementary data are written into a pair of nonvolatile memory cells of each twin cell, the pair of nonvolatile memory cells is set to be in a written state where one cell of the pair is set to one of low and high threshold voltages, and the other is set to the other threshold voltage. When non-complementary data are written into a pair of nonvolatile memory cells, for example, the memory cells both take the low threshold voltage and are made blank. The selector includes switching elements. During the blank-check action, switching elements of the selector are controlled to ON state. Then, the first total current of the twin cells forced to flow into the first input terminal of the sense circuit commonly is compared with the reference signal on the second input terminal, whereby whether the twin cells have been written or blank can be detected at a high speed. As to a semiconductor nonvolatile memory such that complementary data are written into memory cells in memory cell pairs, the blank-check time can be shortened.10-08-2009
20090300269HYBRID MEMORY MANAGEMENT - Methods and apparatus for managing data storage in hybrid memory devices utilizing single level and multi level memory cells. Logical addresses can be distributed between single level and multilevel memory cells based on a frequency of write operations performed. Initial storage of data corresponding to a logical address in memory can be determined by various methods including initially writing all data to single level memory or initially writing all data to multilevel memory. Other methods permit a host to direct logical address writes to single level or multilevel memory cells based on anticipated usage.12-03-2009
20100268872DATA STORAGE SYSTEM COMPRISING MEMORY CONTROLLER AND NONVOLATILE MEMORY - A data storage system comprising a storage device comprising at least one nonvolatile memory, and a controller connected to the storage device through a channel. The memory controller sends part or all of a command, address and data for a next operation to the nonvolatile memory while the nonvolatile memory device is in a busy state. The memory controller then performs a background operation while the nonvolatile memory device remains in the busy state.10-21-2010
20110125954DATA STORAGE METHOD FOR FLASH MEMORY, AND FLASH MEMORY CONTROLLER AND FLASH MEMORY STORAGE SYSTEM USING THE SAME - A data storage method for storing data into a flash memory chip is provided. The flash memory chip has a plurality of physical addresses, and these physical addresses include a plurality of fast physical addresses and a plurality of slow physical addresses. In the data storage method, the usage rate of the physical addresses is monitored. When the usage rate is not larger than a usage rate threshold value, only the fast physical addresses are used for storing the data into the flash memory chip. When the usage rate is larger than the usage rate threshold value, the fast physical addresses and the slow physical addresses are used for storing the data into the flash memory chip. Thereby, the speed of storing data into the flash memory chip is effectively increased.05-26-2011
20100115192WEAR LEVELING METHOD FOR NON-VOLATILE MEMORY DEVICE HAVING SINGLE AND MULTI LEVEL MEMORY CELL BLOCKS - A method of executing a wear leveling operation within a non-volatile memory including a single-level memory cell block (SLC) and a multi-level memory cell block (MLC) is disclosed. The method includes calculating an average erase point in relation to a number of programming/erase (P/E) operations applied to a logical block address (LBA), a SLC mode usage point in relation to a number of the P/E operations applied to the SLC, a MLC mode usage point in relation to a number of the P/E operations applied to the MLC, and a wear value in relation to the average erase point, the SLC mode usage point, and the MLC mode usage point; and then if the wear value exceeds a defined threshold value, performing the wear leveling operation.05-06-2010
20100115189METHOD FOR MANAGING A MEMORY APPARATUS, AND ASSOCIATED MEMORY APPARATUS THEREOF - A method for managing a memory apparatus including at least one non-volatile (NV) memory element includes: providing at least one block of the memory apparatus with at least one local page address linking table within the memory apparatus, wherein the local page address linking table comprises linking relationships between physical page addresses and logical page addresses of a plurality of pages; and building a global page address linking table of the memory apparatus according to the local page address linking table.05-06-2010
20090089484DATA PROTECTION METHOD FOR POWER FAILURE AND CONTROLLER USING THE SAME - A data protection method suitable for a plurality of physical blocks mapped to a logical block in a non-volatile memory is provided. The data protection method includes recording data update information in each of the physical blocks for identifying an update relationship of the physical blocks and re-establishing the update relationship of the physical blocks according to the data update information. The data update information is composed of a plurality of words having a circular relationship, and the number of these words is greater than the number of the physical blocks. The data update information is sequentially recorded in each of the physical blocks according to the update relationship and the circular relationship.04-02-2009
20100070689HYBRID HARD DISK DRIVE TO RAPIDLY READ FILES HAVING SPECIFIED CONDITIONS, METHOD OF CONTROLLING THE HYBRID HARD DISK DRIVE, AND RECORDING MEDIUM FOR THE HYBRID HARD DISK DRIVE - A method of controlling a hybrid hard disk drive. The method includes receiving a read command from a host; searching metadata of a file to be read; determining whether the metadata satisfies a predetermined setup condition; and if the metadata satisfies the setup conditions, copying the file to be read, from a first storage device and storing the file in a second storage device.03-18-2010
20100169561Removable Mother/Daughter Peripheral Card - A peripheral card having a Personal Computer (“PC”) card form factor and removably coupled externally to a host system is further partitioned into a mother card portion and a daughter card portion. The daughter card is removably coupled to the mother card. In the preferred embodiment, a low cost flash “floppy” is accomplished with the daughter card containing only flash EEPROM chips and being controlled by a memory controller residing on the mother card. Other aspects of the invention includes a comprehensive controller on the mother card able to control a predefined set of peripherals on daughter cards connectable to the mother card; relocation of some host resident hardware to the mother card to allow for a minimal host system; a mother card that can accommodate multiple daughter cards; daughter cards that also operates directly with hosts having embedded controllers; daughter cards carrying encoded data and information for decoding it; and daughter cards with security features.07-01-2010
20100169560Methods for Selectively Copying Data Files to Networked Storage and Devices for Initiating the Same - A data backup system comprises a USB flash drive that includes an emulation component and a flash memory. The emulation component is configured to represent the flash memory as if it were an auto-launch device. Accordingly, a data source, such as a personal computer, will interact with the flash memory as if it were the auto-launch device. As some operating systems are configured to recognize auto-launch devices upon connection and automatically execute applications stored thereon, merely connecting the USB flash drive to a data source running such an operating system will cause a backup application stored by the flash memory to automatically execute on the data source. Here, the backup application is configured to selectively back up data files from the data source to a networked storage such as a server of a commercial service provider.07-01-2010
20100169559Removable Mother/Daughter Peripheral Card - A peripheral card having a Personal Computer (“PC”) card form factor and removably coupled externally to a host system is further partitioned into a mother card portion and a daughter card portion. The daughter card is removably coupled to the mother card. In the preferred embodiment, a low cost flash “floppy” is accomplished with the daughter card containing only flash EEPROM chips and being controlled by a memory controller residing on the mother card. Other aspects of the invention includes a comprehensive controller on the mother card able to control a predefined set of peripherals on daughter cards connectable to the mother card; relocation of some host resident hardware to the mother card to allow for a minimal host system; a mother card that can accommodate multiple daughter cards; daughter cards that also operates directly with hosts having embedded controllers; daughter cards carrying encoded data and information for decoding it; and daughter cards with security features.07-01-2010
20100169557USING NON-VOLATILE STORAGE TO TRACK STATUS CHANGES IN OBJECTS - A non-volatile storage device is used to track status changes in one or more items, where it is less costly to set bits in the non-volatile storage device than to reset bits. For each of the items to be tracked, at least two bits of storage space are allocated in the non-volatile storage device. One of the bits is set when the item changes status, and another of the bits is set when the item changes status again.07-01-2010
20100169558NONVOLATILE MEMORY DEVICE AND NONVOLATILE MEMORY SYSTEM - A nonvolatile storage device includes a controller and a nonvolatile memory. The controller has: a logical-physical address conversion part for converting a logical address designated by a host device into a physical address; and a boot code address conversion part for converting boot code address information designated by the host device into a physical address. After the power-on and before the logical-physical address conversion part becomes usable, a boot code is read from a part of region which can be accessed by designating a logical address from the host device by designating the boot code address information from the outside. Thus, it is possible to rapidly start the nonvolatile memory system after the power-on. In the state where the logical-physical address conversion part can be used, data-reading and data-writing are carried out by designating a logical address from the host device.07-01-2010
20100169556NONVOLATILE STORAGE DEVICE, INFORMATION RECORDING SYSTEM, AND INFORMATION RECORDING METHOD - A nonvolatile storage device includes a nonvolatile memory configured to store user data and management information used to manage the user data on a file system, and a medium controller configured to determine whether a command input from a host device is used for the user data or the management information, the command describing content of processing performed for the user data or the management information, and switch between control methods used for the nonvolatile memory on the basis of the determination result.07-01-2010
20100169555METHOD OF WRITING DATA INTO FLASH MEMORY BASED ON FILE SYSTEM - A method of writing data into flash memory based on OS file system is provided. The method includes steps of: obtaining a data start position of a data area in a first partition of a flash memory; converting the data start position into a first block number and a first page number; calculating an offset and adding the offset to the first page number to be an updated first page number when the first page number is not an integer; and, setting the first block number and the updated first page number as a new data start position of the data area and writing a first data according to the new data start position.07-01-2010
20100169554TERMINAL APPARATUS - A terminal apparatus acquires setting information for controlling whether a storage area held by the non-volatile storage medium is to be used or not, from an external apparatus connected via a network, when the terminal apparatus is activated. The terminal apparatus updates area definition information defining the structure of storage areas in the non-volatile storage medium so that the storage area the use of which is restricted is in a state which cannot be recognized by the operating system, if the acquired setting information indicates that the use of the storage area is restricted. The terminal apparatus performs activation processing of the operating system after the update processing of the area definition information ends, if the acquired setting information indicates that the use of the storage area is restricted.07-01-2010
20100169553MEMORY SYSTEM, CONTROLLER, AND METHOD OF CONTROLLING MEMORY SYSTEM - A memory system according to an embodiment of the present invention includes a volatile first storing unit, a nonvolatile second storing unit, a controller that transfers data between a host apparatus and the second storing unit via the first storing unit. The memory system monitors whether data written from the host apparatus in the first storing unit has a specific pattern in management units. When data to be flushed to the second storing unit has the specific pattern, the memory system set an invalid address value that is not in use in the second storing unit to the data.07-01-2010
20100274953DATA STORAGE DEVICE AND INFORMATION PROCESSING SYSTEM INCORPORATING DATA STORAGE DEVICE - A data storage device comprises a plurality of memory devices and a memory controller. The memory controller exchanges data with the memory devices via a plurality of channels. The memory controller decodes an external command to generate a driving power mode and accesses the memory devices according to the driving power mode.10-28-2010
20100169552 REMOVALBLE MULTIMEDIA MEMORY CARD AND METHOD OF USE - A method and system is disclosed for distributing multimedia information. The system and method comprises sending a plurality of multimedia files to at least one server; and recording the plurality of multimedia files on a removable memory device. The removable memory device has a format that includes a predetermined information set that is described and physically stored thereon. The method and system is a complete solution for the commercial multimedia (audio, video, picture, text) distribution. Also, the method and system can be used for commercial distribution of any kind digital data (programs, bank data, documents, control etc). The method and system uses individual unique keycode for customized access to internet and any other electronic devices. All multimedia data files are stored on a removable memory device as a physical, hardware device.07-01-2010
20100169550SEMICONDUCTOR MEMORY DEVICE, DATA TRANSFER DEVICE, AND METHOD OF CONTROLLING SEMICONDUCTOR MEMORY DEVICE - To provide a semiconductor memory device including a first controller that controls a first data transfer in which data are transferred from the first memory to a second memory in predetermined transfer units; a second controller that controls a second data transfer in which data are transferred from the second memory to a host device; and a control unit that outputs to the first controller a read instruction in which an address in the second memory is specified for each of the predetermined transfer units and creates a descriptor in which the addresses in the second memory are specified in order of transfer. The first controller outputs an end notification at each end of the first data transfer, and the second controller executes the second data transfer according to the specification in the descriptor after receiving the end notification.07-01-2010
20100169549MEMORY SYSTEM AND CONTROLLER - A controller sets, out of a data range that is specified in a read request from a host device, a predetermined size of a first data range that follows a top portion of the data range and a predetermined size of a second data range that follows the first data range, and after transfer, to the host device, of data corresponding to the first data range from a second storage unit or a third storage unit having smaller data output latency than the first storage unit in which read/write of data is performed is started, the controller searches for data corresponding to the second data range in the second storage unit or the third storage unit.07-01-2010
20100169548MEMORY CARD AND METHOD FOR CONTROLLING MEMORY CARD - According to one embodiment, a memory card configured to be installed in and removed from a card slot formed in an electronic apparatus, the memory card includes a memory section configured store at least one file, a close-proximity wireless transfer section configured to perform close-proximity wireless transfer, and a controller configured, every time communication between the close-proximity wireless transfer section and a different close-proximity wireless transfer device is enabled, to execute a process for using the close-proximity wireless transfer section to transmit the files stored in the memory section to the different close-proximity wireless transfer device.07-01-2010
20100169547METHOD FOR PREVENTING DATA LOSS DURING SOLDER REFLOW PROCESS AND MEMORY DEVICE USING THE SAME - The invention provides a method for preventing data loss in a flash memory during a solder reflow process. The flash memory includes a plurality of memory blocks and each memory block includes a plurality of strong pages and weak pages. Preloading data is first received and stored into the strong pages of at least one of first memory block within the flash memory. Then, the flash memory is heated for the solder reflow process. Next, the preloading data is reorganized according to a trigger signal and the strong pages and weak pages of at least one of second memory block within the flash memory are provided for storing the reorganized preloading data.07-01-2010
20100169545HOST SYSTEM AND OPERATING METHOD THEREOF - The prevent invention provides a host system and an operating method thereof. The host system comprises: a peripheral device control circuit, for controlling operation of at least a peripheral device, the peripheral device comprising an embedded micro processor; and a host control circuit, coupled to the peripheral device control circuit via a transmission interface, the host control circuit comprising: a storage module, at least storing a firmware of the embedded micro processor; and a control module, coupled to the storage module, for controlling operation of the host control circuit, and the control module transmitting the firmware to the peripheral device control circuit via the transmission interface. The embedded micro processor executes the firmware provided by the host control circuit to control operation of the peripheral device control circuit.07-01-2010
20100169544METHODS FOR DISTRIBUTING LOG BLOCK ASSOCIATIVITY FOR REAL-TIME SYSTEM AND FLASH MEMORY DEVICES PERFORMING THE SAME - A method for distributing log block associativity in log buffer-based flash translation layer (FTL) includes, if write request on page p is generated, checking whether log block associated with corresponding data block that write request is generated exists or not by checking log block mapping table storing mapping information between data blocks and log blocks, wherein the associativity of each log block to data block is set to equal to or less than predetermined value K in advance, and K is a natural number, if log block associated with corresponding data block that write request is generated exists, checking whether associated log block is random log block or sequential log block, and if associated log block is random log block, writing data that write request is generated in first free page of random log block.07-01-2010
20100169543RECOVERY FOR NON-VOLATILE MEMORY AFTER POWER LOSS - Non-volatile memory array can be recovered after a power loss. In one example, pages of a memory array are scanned to find a first free page after the power loss. The first free page is marked as available, and the page marked as available is written to with the next write cycle07-01-2010
20100169542DYNAMIC MAPPING OF LOGICAL RANGES TO WRITE BLOCKS - A method and system writes data to a memory device including dynamic assignment of logical block addresses (LBAs) to physical write blocks. The method includes receiving a request to write data for a logical block address within an LBA range to the memory device. The method assigns the LBA range to a particular write block exclusively or non-exclusively, depending on the existence of previously assigned write blocks and the availability of unwritten blocks. A data structure may be utilized to record the recent usage of blocks for assigning non-exclusive write blocks. An intermediate storage area may be included that implements the dynamic assignment of LBA ranges to physical write blocks. Data in the intermediate storage area may be consolidated and written to the main storage area. Lower fragmentation and write amplification ratios may result by using this method and system.07-01-2010
20100169541METHOD AND APPARATUS FOR RETROACTIVE ADAPTATION OF DATA LOCATION - A method and system for organizing groups of data in a storage device having a non-volatile memory consisting of higher performance or endurance portion and a lower performance or endurance portion are disclosed. The method may include steps of determining a data usage status for a group of data in only one of the two portions, and if a data usage criterion is met, moving the group of data to the other of the two portions of the non-volatile memory. In another implementation, the method may include determining a data usage status of groups of data in both portions of the non-volatile memory and moving a group of data from one portion to the other if an appropriate data usage criterion is met so that groups of data may be maintained in a portion of the non-volatile memory most suited to their usage patterns.07-01-2010
20100169540METHOD AND APPARATUS FOR RELOCATING SELECTED DATA BETWEEN FLASH PARTITIONS IN A MEMORY DEVICE - A method and system for relocating selected groups of data in a storage device having a non-volatile memory consisting partitions with different types of non-volatile memory. The method may include determining whether data received a first partition meets one or more heightened read probability criteria and/or heightened delete probability criteria. If the criteria are not met, the received data is moved to a second partition, where the first partition has a higher endurance than the second partition. The system may include a first non-volatile memory partition and a second non-volatile memory partition having a lower endurance than the first, where a controller in communication with the first and second partitions determines if a heightened read probability and/or a heightened delete probability are present in received data.07-01-2010
20100088461SOLID STATE STORAGE SYSTEM USING GLOBAL WEAR LEVELING AND METHOD OF CONTROLLING THE SOLID STATE STORAGE SYSTEM - A solid state storage system is disclosed including a memory area having a plurality of chips. The solid state storage system includes a micro controller unit (MCU) configured to utilize the number of deletions for logical blocks corresponding to logical block addresses when performing wear leveling on the memory area. The allocation of the logical block addresses can be performed using an interleaving process and a multi-plane method. The solid state storage system performs global wear leveling by which the lifespan of the cells of the chips can be uniformly managed.04-08-2010
20100115177DATA STORAGE DEVICES - A data storage device includes a non-volatile memory array, a user input device, and a host interface adapted to connect the data storage device to a host device and convey data to the host device. In response to a first operation of the user input device, application configuration data is communicated from the data storage device to the host device. The application configuration data is configured to trigger execution by the host device of a configuration application that includes a listing of a plurality of applications for display by the host device allowing a user to identify a selected application. In response to selection of an application, application designation data is generated and stored in the non-volatile memory array. In response to a second operation of the user input device, the application designation data is communicated to the host device to trigger automatic execution by the host device of the selected application.05-06-2010
20100037012Semiconductor Storage Device, Method of Controlling the Same, Controller and Information Processing Apparatus - A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second, third and fourth memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data by a first management unit in the fourth memory area, a third processing for storing data by a second management unit in the third memory area, a fourth processing for moving an area of the third unit from the fourth memory area to the second memory area, a fifth processing for copying data to an area of the third unit and allocating the area to the second memory area, and a sixth processing for copying data to an empty area of the third unit in the second memory area.02-11-2010
20100115182FLASH MEMORY OPERATION - An embodiment is a technique to improve operations of flash memory devices. A plurality of logical block numbers is mapped to a plurality of physical block numbers using a mapper. The physical block numbers are associated with blocks in a flash memory device. A plurality of block statuses of the plurality of free physical block numbers is stored in a replacement table. Each of the block statuses is one of a ready, dirty, and broken status. A destination block in the blocks is written to. The destination block has the ready status. The mapper and the replacement table are updated.05-06-2010
20100115180MEMORY MODULE INCLUDING ENVIRONMENTAL OPTIMIZATION - A memory apparatus enable operation which is adapted to environmental conditions. The memory apparatus includes a memory module that can store and incorporate environment-dependent optimal operating parameters. The memory module comprises a plurality of volatile memory devices and one or more non-volatile memory devices that store a plurality of environment-dependent device parameters for a device selected from the plurality of volatile memory devices. The stored parameters enable the selected device to function optimally in multiple environmental conditions.05-06-2010
20100115179MEMORY MODULE INCLUDING VOLTAGE SENSE MONITORING INTERFACE - Memory devices and systems include a voltage sense line for addressing voltage tolerances across variable loadings. The memory devices and systems comprise a memory module connector with a first plurality of pins coupled to circuitry on a memory module, and a second plurality of pins coupled to power rails on the memory module that enable monitoring of the power rails from external to the memory module.05-06-2010
20100115176DATA TRANSFER AND PROGRAMMING IN A MEMORY DEVICE - Methods for data transfer and/or programming a memory device, memory devices and memory systems are provided. According to at least one such method, additional data is appended to original data and the resulting data is programmed in a selected memory cell. The appended data increases the program threshold voltage margin of the original data. The appended data can be a duplicate of the original data or logical zeros. When the selected memory cell is read, the memory control circuitry can read just the original data in the MSB field or the memory control circuitry can read the entire programmed data and ignore the LSB field, for example.05-06-2010
20090313422FLASH MEMORY CONTROL APPARATUS HAVING SEQUENTIAL WRITING PROCEDURE AND METHOD THEREOF - A flash memory control apparatus having a sequential writing procedure and method thereof are described. The flash memory control apparatus includes primary controller, a command module, an address module, a data buffer, a status unit, a counting device and a secondary controller. The primary controller generates a predetermined value which represents the amount of a plurality of pages in the flash memory. The command module stores a writing command during the writing procedure. The address module stores a current address for addressing a current page of the pages based on the current address and the writing command via a control bus. The data buffer stores the data for allowing the command module to write the data to the current page based on the current address via the control bus while the writing command is executed on the flash memory. The status unit determines that the flash memory is either ready or busy in writing the data to the current page of the flash memory. If the command module correctly writes the data to the current page according to the determination result, the address module generates at least one next address. The address module addresses at least one next page of the pages based on the at least one next address and the writing command. The command module sequentially writes the data to the at least one next page during the writing procedure until the pages are written successively.12-17-2009
20120233389MULTI-HOST CONCURRENT WRITING TO MAGNETIC TAPE - According to one embodiment, a method for storing data on a magnetic tape comprises receiving data from two different hosts and simultaneously writing the data from the hosts to the magnetic tape using multiple transducers. In another approach, a method for storing data on a magnetic tape comprises receiving requests to establish a concurrent reservation from multiple hosts and allocating a unique stripe in a wrap to each of the hosts that sent the requests, wherein the wrap is a collection of data tracks to be written simultaneously in one direction of tape movement by multiple transducers of a tape head, and the wrap is logically divided into the stripes. Also, the method includes receiving data from the hosts and simultaneously writing the data from the hosts to the magnetic tape using the multiple transducers. Other systems and methods concerning storing data on magnetic tapes are described as well.09-13-2012
20120084492STORAGE SYSTEM LOGICAL BLOCK ADDRESS DE-ALLOCATION MANAGEMENT AND DATA HARDENING - Storage system Logical Block Address (LBA) de-allocation management and data hardening provide improvements in performance, efficiency, and utility of use. Optionally, LBA de-allocation information in a first format (e.g. associated with a first protocol) is converted to a second format (e.g. associated with a second protocol). An example of the first protocol is a Small Computer System Interface (SCSI) protocol, and an example of the second protocol is an Advanced Technology Attachment (ATA) protocol. Optionally, LBA de-allocation status information is determined by a storage device, such as a Solid-State Disk (SSD), and communicated to another device such as an initiator, expander, or bridge. Optionally, data stored on an SSD is hardened, such as in response to determining that the SSD is to be powered off. The hardening is via power supplied by an energy storage element, such as a super capacitor or a battery.04-05-2012
20100268873FLASH MEMORY CONTROLLER UTILIZING MULTIPLE VOLTAGES AND A METHOD OF USE - A Flash memory controller is disclosed. The Flash memory controller comprises a host interface, a Flash memory interface, controller logic coupled between the host interface, the controller logic handling a plurality of voltages. The controller also includes a mechanism for allowing a multiple voltage host to interface with a high voltage or a multiple voltage Flash memory. A multiple voltage Flash memory controller in accordance with the present invention provides the following advantages over conventional Flash memory controllers: (1) a voltage host is allowed to interface with multiple Flash memory components that operate at different voltages in any combination; (2) power consumption efficiency is improved by integrating the programmable voltage regulator, and voltage comparator mechanism with the Flash memory controller; (3) External jumper selection is eliminated for power source configuration; and (4) Flash memory controller power source interface pin-outs are simplified.10-21-2010
20100268870DATA STORAGE DEVICE AND DATA STORAGE SYSTEM INCLUDING THE SAME - A data storage device includes a flash memory including a plurality of data blocks and a flash translation layer that divides the plurality of data blocks into a data block of a first group and a data block of a second group, and that records the data signal to a data block of the first group or a data block of the second group which is extended from a data block of the first group.10-21-2010
20100268868FLASH STORAGE DEVICE AND OPERATING METHOD THEREOF - The invention also provides a flash storage device. In one embodiment, the flash storage device is coupled to a host, and comprises a random access memory and a controller. The random access memory stores a plurality of link tables therein, wherein each of the link tables corresponds to one of a plurality of management units of at least one flash memory, and the link tables store corresponding relationships between logical addresses and physical addresses of the corresponding management units. The controller receives an access logical address from the host, determines an access physical address corresponding to the access logical address according to the link tables stored in the random access memory, and accesses data from the flash memory according to the access physical address.10-21-2010
20100268866SYSTEMS AND METHODS FOR OPERATING A DISK DRIVE - System and methods for storing data to a storage device are provided. In embodiments, the storage device may include a disk drive with a solid-state memory for storing certain frequently updated information. In some embodiments, the solid-state memory may be used to store journaling information.10-21-2010
20120239862MEMORY CONTROLLER CONTROLLING A NONVOLATILE MEMORY - Described is a memory controller interfacing with a host and a nonvolatile memory. The memory controller may include a buffer unit configured to store an input address table and a first hot address table; and a processing unit configured to judge whether an address from the host coincides with one of addresses stored in the input address table and to store the address from the host in the first hot address table according to the judgment.09-20-2012
20120239857SYSTEM AND METHOD TO EFFICIENTLY SCHEDULE AND/OR COMMIT WRITE DATA TO FLASH BASED SSDs ATTACHED TO AN ARRAY CONTROLLER - An apparatus comprising a controller and an array. The controller may be configured to generate control signals in response to one or more input requests. The array may comprise a plurality of solid state devices. The solid state devices may be configured to (i) read and/or write data in response to the control signals received from the controller and (ii) distribute writes across the plurality of solid state devices such that each of said solid state devices has a similar number of writes.09-20-2012
20120239856HYBRID SYSTEM ARCHITECTURE FOR RANDOM ACCESS MEMORY - Embodiments of the present invention provide a hybrid system architecture random access memory (RAM) such as Phase-Change RAM (PRAM), Magnetoresistive RAM (MRAM) and/or Ferroelectric RAM (FRAM). Specifically, embodiments of this invention provide a hybrid RAID controller coupled to a system control board. Coupled to the hybrid RAID controller are a DDR RAID controller, a RAM RAID controller, and a HDD/Flash RAID controller. A DDR RAID control block is coupled to the DDR RAID controller and includes (among other things) a set of DDR memory disks. Further, a RAM control block is coupled to the RAM RAID controller and includes a set of RAM SSDs. Still yet, a HDD RAID control block is coupled to the HDD/Flash RAID controller and includes a set of HDD/Flash SSD Units.09-20-2012
20100153624DATA MANAGING METHOD FOR NON-VOLATILE MEMORY AND NON-VOLATILE MEMORY DEVICE USING THE SAME - A data managing method for non-volatile memory which comprises a step for receiving a first logical block address and updated data, and a step for merging data in a plurality of physical blocks which have lowest usage rates according to usage parameters in a reference table when the first logical address doesn't exist in the reference table in a buffer memory and a number of pair blocks reaches a determined number.06-17-2010
20080215803SEMICONDUCTOR STORAGE DEVICE AND METHOD OF CONTROLLING THE SAME - A semiconductor storage device includes a first nonvolatile memory to store user data of a file, a second nonvolatile memory to store management data of the file, the second nonvolatile memory being different in type from the first nonvolatile memory, and a controller to control read/write of data with respect to the first and second nonvolatile memories.09-04-2008
20080215800Hybrid SSD Using A Combination of SLC and MLC Flash Memory Arrays - Hybrid solid state drives (SSD) using a combination of single-level cell (SLC) and multi-level cell (MLC) flash memory arrays are described. According to one aspect of the present invention, a hybrid SSD is built using a combination SLC and MLC flash memory arrays. The SSD also includes a micro-controller to control and coordinate data transfer from a host computing device to either the SLC flash memory array of the MLC flash memory array. A memory selection indicator is determined by triaging data file based on one or more criteria, which include, but is not limited to, storing system files and user directories in the SLC flash memory array and storing user files in the MLC flash memory array; or storing more frequent access files in the SLC flash memory array, while less frequent accessed files in the MLC flash memory array.09-04-2008
20100235570COMMAND CONTROLLER, PREFETCH BUFFER AND METHODS FOR ACCESSING A SERIAL FLASH IN AN EMBEDDED SYSTEM - The invention relates to a command controller and a prefetch buffer, and in particular, to a command controller and a prefetch buffer for accessing a serial flash in an embedded system. An embedded system comprises a serial flash, a processor, a plurality of access devices, and a prefetch buffer. The processor and the plurality of access devices send various commands to read data from or write data to the serial flash. The prefetch buffer temporarily stores a predetermined amount of data before data being read from or written to the serial flash.09-16-2010
20090089492FLASH MEMORY CONTROLLER - Methods, systems and computer program products for implementing a polling process among one or more flash memory devices are described. In some implementations, the polling process may include sending a read status command to a flash memory device to detect the ready or busy state of the flash memory device. A status register may be included in the flash memory device for storing a status signal indicating an execution state of a write (or erase) operation. A solid state drive system may perform the polling process by reading the status register of the flash memory device.04-02-2009
20100306452MULTI-MAPPED FLASH RAID - Disclosed is a storage system. The storage system includes a redundant array of inexpensive disks (RAID) controller. The RAID controller includes a flash memory controller coupled to a flash memory. The flash memory controller may perform background management tasks. These include logging and error reporting, address translation, cache table management, bad block management, defect management, wear leveling, and garbage collection. The array controller also allows the flash memory to be divided into multiple mappings.12-02-2010
20100262752STORAGE VIRTUAL CONTAINERS - A controller of a Solid State Device (SSD) defines a mapping from memory devices, such as flash packages, that make up the SSD to one or more storage virtual containers. The storage virtual containers are exposed to an operating system by the controller through an interface. The operating system may then make operation requests to the one or more storage virtual containers, and the controller may use the mapping to fulfill the operation requests from the corresponding flash packages. The storage virtual containers are mapped to the flash packages to take advantage of the parallelism of the flash packages in the SSD so that the controller may fulfill operation requests received from the operating system in parallel.10-14-2010
20110197017High Endurance Non-Volatile Memory Devices - High endurance non-volatile memory devices (NVMD) are described. A high endurance NVMD includes an I/O interface, a NVM controller, a CPU along with a volatile memory subsystem and at least one non-volatile memory (NVM) module. The volatile memory cache subsystem is configured as a data cache subsystem. The at least one NVM module is configured as a data storage when the NVMD is adapted to a host computer system. The I/O interface is configured to receive incoming data from the host to the data cache subsystem and to send request data from the data cache subsystem to the host. The at least one NVM module may comprise at least first and second types of NVM. The first type comprises SLC flash memory while the second type MLC flash. The first type of NVM is configured as a buffer between the data cache subsystem and the second type of NVM.08-11-2011
20110271036PHASED NAND POWER-ON RESET - A method and system for phasing power-intensive operations is disclosed. A non-volatile storage device controller detects a power reset. The controller is in communication with non-volatile memories in the non-volatile storage device. In response to detecting a power reset, the controller determines a current consumption necessary to reset the non-volatile memories in the non-volatile storage device. The controller simultaneously resets all of the non-volatile memories when the determined current consumption is less than a current consumption threshold. If the determined current consumption is greater than the current consumption threshold, the controller resets a first subset of the plurality of non-volatile memories, and after a predetermined delay, resets a second subset of the non-volatile memories. Therefore, a power-intensive operation may be performed without exceeding a current consumption threshold by dividing the operation into a sequence of steps that do not exceed the threshold.11-03-2011
20100115191System Including Hierarchical Memory Modules Having Different Types Of Integrated Circuit Memory Devices - A memory system is disclosed comprising a memory controller and a first set of volatile memory devices defining a first memory hierarchy. The first set of volatile memory devices are disposed on at least one first memory module, which is coupled to the memory controller in a daisy-chained configuration. A first integrated circuit buffer device is included on the module. The system has a second set of nonvolatile memory devices defining a second memory hierarchy. The second set of nonvolatile memory devices are disposed on at least one second memory module, which is coupled to the at least one first memory module in a daisy-chained configuration. The second module includes a second integrated circuit buffer device. The system is configured such that signals transmitted between the memory controller and the second memory hierarchy pass through the first memory hierarchy.05-06-2010
20100115188METHOD FOR MANAGING A MEMORY APPARATUS, AND ASSOCIATED MEMORY APPARATUS THEREOF - A method for managing a memory apparatus including at least one non-volatile (NV) memory element includes: recording usage information of at least one block during accessing pages of the block; and determining whether to erase a portion of the blocks according to the usage information. For example, the usage information includes a valid page count table for recording valid page counts of the blocks, respectively; and the ranking of a field of the valid page count table represents a physical block address, and the content of the field represents an associated valid page count. In another example, the usage information includes an invalid page count table for recording invalid page counts of the blocks, respectively; and the ranking of a field of the invalid page count table represents a physical block address, and the content of the field represents an associated invalid page count.05-06-2010
20110066793Implementing RAID In Solid State Memory - The present disclosure includes systems and techniques relating to implementing fault tolerant data storage in solid state memory. In some implementations, a method includes receiving data to be stored, dividing data into logical data blocks, assigning the blocks to a logical block grouping comprising at least one physical data storage block from two or more of multiple solid state physical memory devices, storing the blocks in physical data storage blocks, determining a code that corresponds to the persisted data, and storing the code that corresponds to the data stored in the logical block grouping. Blocks of damaged stored data may be recovered by identifying the logical data block and logical block grouping corresponding to the damaged physical data storage block, reading the data and the code stored in the identified grouping, and comparing the code to the read data other than the data stored in the damaged block.03-17-2011
20110072190MEMORY DEVICE AND METHOD - A device is disclosed having a memory module that comprises a first memory block, a second memory block, a programmable storage location, and a memory controller. The first memory block of non-volatile memory comprises a plurality of word locations and an address decoder coupled to a first access port of the memory controller. The address decoder to select one of the plurality of word locations for access in response to receiving address information via the first access port. The second memory block comprising a plurality of word locations and an address decoder coupled to a second access port of the memory controller. The address decoder to select one of the plurality of word locations for access in response to receiving address information via the second access port. The memory controller comprising an input coupled to the programmable storage location, and to access, in response to the programmable configuration information having a first value, a first portion of the first memory block and a first portion of the second memory block as interleaved memory, a second portion of the first memory block as non-interleaved memory, and a second portion of the second memory block as non-interleaved memory.03-24-2011
20100325354MECHANISM TO HANDLE EVENTS IN A MACHINE WITH ISOLATED EXECUTION - A platform and method for secure handling of events in an isolated environment. A processor executing in isolated execution “IsoX” mode may leak data when an event occurs as a result of the event being handled in a traditional manner based on the exception vector. By defining a class of events to be handled in IsoX mode, and switching between a normal memory map and an IsoX memory map dynamically in response to receipt of an event of the class, data security may be maintained in the face of such events.12-23-2010
20100325352HIERARCHICALLY STRUCTURED MASS STORAGE DEVICE AND METHOD - A hierarchically-structured computer mass storage system and method. The mass storage system includes a mass storage memory drive, control logic on the mass storage memory drive that includes a controller and one or more devices for executing a hierarchical storage management technique, a volatile memory cache configured to be accessed by the control logic, and first and second non-volatile storage arrays on the mass storage memory drive and comprising, respectively, first and second non-volatile memory devices. The first and second non-volatile memory devices have properties including access times and write endurance, and at least one of the access time and the write endurance of the first non-volatile memory devices is faster or higher, respectively, than the second non-volatile memory devices. Desired data storage localities on the storage arrays are determined through access patterns and selectively utilizing the properties of the memory devices to match the data storage requirements.12-23-2010
20100325351MEMORY SYSTEM HAVING PERSISTENT GARBAGE COLLECTION - Non-volatile memory systems such as those using NAND FLASH technology have a property that a memory location can be written to only once prior to being erased, and a contiguous group of memory locations need to be erased simultaneously. The process of recovering space that is no longer being used for storage of current data, called garbage collection, may interfere with the rapid access to data in other memory locations of the memory system during the erase period. The effects of garbage collection on system performance may be mitigated by performing portions of the process contemporaneously with the user initiated reading and writing operations. The memory circuits and the data may also be configured such that the data is stored in stripes of a RAID array and the scheduling of the erase operations may be arranged so that the erase operations for garbage collection are hidden from the user operations.12-23-2010
20100325347APPARATUS FOR CONTROLLING NAND FLASH MEMORY - Provided is an apparatus for controlling NAND flash memory. The apparatus for controlling NAND flash memory includes: a register unit in which a start address of a macro-command to be executed, selected from macro-commands included in a command script in which at least one macro-command in which a plurality of micro-commands for controlling a unit operation of NAND flash memory are arranged in an array shape, is described, is recorded; a command fetch unit, if a start address of the macro-command to be executed is recorded in the register unit, accessing first memory connected based on the start address of the macro-command to be executed and sequentially reading the plurality of micro-commands from the start address of the macro-command to be executed; a command interpretation unit interpreting the read micro-commands and outputting the result of interpretation including types of the micro-commands and command parameters; and a command execution unit generating interface signals for controlling an operation of NAND flash memory according to each of the micro-commands based on the result of interpretation. Time required for data transmission and NAND flash control can be reduced, and a high performance can be obtained.12-23-2010
20090150599METHOD AND SYSTEM FOR STORAGE OF DATA IN NON-VOLATILE MEDIA - A system and method for managing the storage of data in non-volatile memory is described. In an aspect, the data may be described by metadata and a transaction log file that are checkpointed from a volatile memory into the non-volatile memory. Actions that take place between the last checkpointing of a metadata segment and log file segment are discovered by scanning the non-volatile memory blocks, taking account of a record of the highest sector in each block that is known to have been recorded. Any later transactions are discovered and used to update the recovered metadata so that the metadata correctly represents the stored data.06-11-2009
20090150598APPARATUS AND METHOD OF MIRRORING FIRMWARE AND DATA OF EMBEDDED SYSTEM - Disclosed is an apparatus and method of mirroring firmware and data of an embedded system. The embedded system mirrors a boot loader image, a kernel image, a RAM disk image and data that are stored on a main flash memory to be operated onto a secondary flash memory. Therefore, when a main flash memory does not normally work, the firmware and data that are stored on the main flash memory to be operated is mirrored onto the secondary flash memory, which prevents the loss of data and maintains the operation of the embedded system. As a result, it is possible to secure the reliability and operability of the system.06-11-2009
20090150597DATA WRITING METHOD FOR FLASH MEMORY AND CONTROLLER USING THE SAME - A data writing method for a flash memory is provided. The data writing method includes: dividing a new data into at lease one sub-data by the length of a writing unit; selecting one of a plurality of spare blocks from the flash memory as a substitute block for substituting a data block, wherein the new data is to be written into the data block; sequentially writing the sub-data having the length of the writing unit into the substitute block in the writing unit; and storing the sub-data not having the length of the writing unit into a temporary area. The writing efficiency of the flash memory can be improved by temporarily storing the sub-data not having the length of the writing unit into the temporary area and then writing the sub-data not having the length of the writing unit with subsequent data into the substitute block.06-11-2009
20090150594METHOD TO MINIMIZE FLASH WRITES ACROSS A RESET - A method and apparatus described herein are for minimizing flash writes across reset. When a commonly accessed variable is to be updated, an erase conscious value is written to minimize erase operations. As an example, the location for the commonly accessed variable holds consecutive values to represent a usable value instead of a binary representation. Furthermore, when the commonly accessed variable is to be read, the stored value is translated into the associated usable value for use by a system.06-11-2009
20090150600MEMORY SYSTEM - A memory system includes a nonvolatile memory having a plurality of data blocks each of which is a unit of data erase and has a plurality of pages, each of the pages being a unit of data write, and a controller which checks whether or not the nonvolatile memory has been affected by power interruption at power-on time and, if the nonvolatile memory has been affected by power interruption, writes data to that first page in a first data block which has not been affected by power interruption.06-11-2009
20090150596DEVICE IDENTIFIERS FOR NONVOLATILE MEMORY MODULES - A memory card has a data scrambler that performs a data scrambling operation on data stored in the memory card according to a device ID associated with the memory card. The device ID is either set at the factory and permanently stored in the card, or configurable by a user or a host system.06-11-2009
20090150595BALANCED PROGRAMMING RATE FOR MEMORY CELLS - A balanced program rate on NVM cells is achieved by (i) scrambling data bits and user bits; and (ii) shifting ED bits (of data and user bits) according to an incremental shift number, which may be the PBE-counter (which provides an incremental number). ED bits for the LSS may also be shifted, according to an incremental shift number (which may be the PBE-counter). The ED bits of the shift-niumber inherently have an evenly balanced distribution The ED bits of the PBE-counter inherently have an evenly balanced distribution.06-11-2009
20090031076Method for Managing Flash Memory - A method for managing a flash memory, a method for leveling the wear of blocks in a flash memory, and a method for managing a file system for a flash memory are provided. The method for managing a flash memory includes: if changing of data of a data block recorded in a data area is requested, recording the data block having changed data in an alternative area and recording mapping information of the data block recorded in the alternative area in a mapping area; and if changing of data of the data block recorded in the alternative area is requested, recording a data block having changed data in the data area and deleting the mapping information recorded in the alternative area from the mapping area.01-29-2009
20120110250MEETHOD, SYSTEM AND COMPUTER READABLE MEDIUM FOR COPY BACK - Systems, computer readable media and methods for updating a flash memory device involve procedures for transferring, from a flash memory device to an external controller, only a portion of a data entity; and determining, by the external controller, based upon the portion of the data entity, whether to complete a copy back operation of the data entity or to correct errors of the data entity. If it is determined to correct errors of the data entity, then the procedure includes (a) completing a transfer of the data entity to the external controller; (b) error correcting the data entity to provide an amended data entity; and (c) writing the amended data entity to the flash memory device. If, however, it is determined to complete the copy back operation then the procedures includes completing the copy back operation of the data entity by transferring the data entity within the flash memory device.05-03-2012
20120110253COMBINED MEMORY AND STORAGE DEVICE IN AN APPARATUS FOR DATA PROCESSING - The invention concerns an apparatus for data processing comprising a central processing unit and a non volatile random access memory. The central processing unit and the non volatile random access memory are connected via a memory bus. The data related to an operating system for running said apparatus is at least partly stored in said non volatile random access memory and the memory used by the operating system for operating said apparatus is at least partly said non volatile memory.05-03-2012
20120110252 System and Method for Providing Performance-Enhanced Rebuild of a Solid-State Drive (SSD) in a Solid-State Drive Hard Disk Drive (SSD HDD) Redundant Array of Inexpensive Disks 1 (Raid 1) Pair - The present invention is a method for implementing a storage system. The storage system may include a disk array having a disk drive pair which includes a solid-state disk drive and a hard disk drive. The method may include the step of copying a data subset of a data set from the hard disk drive to a spare solid-state disk drive during a solid-state disk drive rebuild process. The data subset includes a first amount of data and the data set includes a second amount of data, where the first amount of data is less than the second amount of data. The method may further include the step of receiving a read request from a host server requesting the data subset. The method further includes the step of directing the read command to the spare solid-state disk drive.05-03-2012
20120110251PROCESSOR-BUS-CONNECTED FLASH STORAGE MODULE - A system includes multiple nodes coupled using a network of processor buses. The multiple nodes include a first processor node, including one or more processing cores and main memory, and a flash memory node coupled to the first processor node via a first processor bus of the network of processor buses. The flash memory node includes a flash memory including flash pages, a first memory including a cache partition for storing cached flash pages for the flash pages in the flash memory and a control partition for storing cache control data and contexts of requests to access the flash pages, and a logic module including a direct memory access (DMA) register and configured to receive a first request from the first processor node via the first processor bus to access the flash pages.05-03-2012
20120110249MEMORY SYSTEM, DATA STORAGE DEVICE, USER DEVICE AND DATA MANAGEMENT METHOD THEREOF - A data management method of a data storage device having a data management unit different from a data management unit of a user device receives information regarding a storage area of a file to be deleted, from the user device, selects a storage area which matches with the data management unit of the data storage device, from among the storage area of the deleted file, and performs an erasing operation on the selected storage area which matches with the data management unit.05-03-2012
20120110247MANAGEMENT OF CACHE MEMORY IN A FLASH CACHE ARCHITECTURE - A method for managing cache memory in a flash cache architecture. The method includes providing a storage cache controller, at least a flash memory comprising a flash controller, and at least a backend storage device, and maintaining read cache metadata for tracking on the flash memory cached data to be read, and write cache metadata for tracking on the flash memory data expected to be cached.05-03-2012
20120110246EXECUTE-IN-PLACE MODE CONFIGURATION FOR SERIAL NON-VOLATILE MEMORY - Example embodiments for configuring a serial non-volatile memory device for an execute-in-place mode may comprise a non-volatile configuration register to store an execute-in-place mode value that may be read at least in part in response to power being applied to the memory device.05-03-2012
20120110245Data writing method and writing device for an electronic erasable read only dynamic memory - A data writing method for an EEPROM in an electronic device is performed by a writing device. The electronic device includes a system unit generating a system voltage and a write-protection voltage. The writing device includes a processor stored with data to be written, and connected electrically to a connector with the same interface as that of an expansion connector of the electronic device. When the connector is connected electrically to the expansion connector, the processor generates a write-enable voltage greater than the system voltage upon receipt of the system voltage from the electronic device, and outputs the write-enable voltage to the system unit. The system unit raises the system voltage in response to the write-enable voltage such that the write-protection voltage is smaller than the raised system voltage to thereby enable the EEPROM to operate in a write state, where the processing unit writes the data into the EEPROM.05-03-2012
20120110244COPYBACK OPERATIONS - Methods and systems for copyback operations are described. One or more methods include reading data from a first memory unit of a memory device responsive to a copyback command, performing signal processing on the data using a signal processing component local to the memory device, and programming the data to a second memory unit of the memory device.05-03-2012
20120110243DATA WRITING METHOD, MEMORY CONTROLLER, AND MEMORY STORAGE APPARATUS - A data writing method for a rewritable non-volatile memory module is provided, the rewritable non-volatile memory module has a plurality of physical blocks, each of the physical blocks has a plurality of physical pages, a portion of the physical blocks are mapped to a plurality of logical blocks, and each of the logical blocks has a plurality of logical pages. The data writing method includes receiving data, and the data has a plurality of data bits and belongs to one of the logical pages. The data writing method also includes determining whether each of the data bits is a specific value. The data writing method further includes not writing the data into the physical pages when each of the data bits is the specific value. Thereby, the performance of a memory storage apparatus is improved.05-03-2012
20120110242PROGRAMMABLE MEMORY CONTROLLER - A memory controller, in one embodiment, includes a command translation data structure, a front end and a back end. The command translation data structure maps command operations to primitives, wherein the primitives are decomposed from command operations determined for one or more memory devices. The front end receives command operations from a processing unit and translates each command operation to a set of one or more corresponding primitives using the command translation data structure. The back end outputs the set of one or more corresponding primitives for each received command operation to a given memory device.05-03-2012
20120110241SYSTEM FOR NAND FLASH PARAMETER AUTO-DETECTION - A system comprising a NAND flash memory device having a multiplicity of parameters; a flash controller configured to perform a NAND flash memory parameter automatic detection process including reading a device identifier of the NAND flash memory device and proceeding if a valid device identifier value is returned, detecting an address cycle and a block type of the NAND flash memory device, detecting a page size of the NAND flash memory device, detecting a spare size of the NAND flash memory device, detecting a memory size of the NAND flash memory device, and detecting a block size of the NAND flash memory device.05-03-2012
20120110240Method and System for Memory Controller Calibration - A method for calibration of a memory controller may include determining if an unused memory location exists in memory. The method may include writing a first pattern to the unused memory location in response to a determination that the unused memory location exists. The method may include determining if a second pattern exists in the memory in response to a determination that the unused memory location does not exist. The method may include iteratively modifying a first delay of a first delay control module among a plurality of delay values. The method may include reading from a memory location including the first pattern or the second pattern for each iteration of modification of the first delay. The method may include modifying one or more second delays, each second delay associated with one of one or more second delay control modules, based on the results of reading from the memory location.05-03-2012
20120110239Causing Related Data to be Written Together to Non-Volatile, Solid State Memory - A first write request that is associated with a first logical address is received via a collection of write requests targeted to a non-volatile, solid state memory. It is determined whether the logical address is related to logical addresses of one or more other write requests of the collection that are not proximately ordered with the first write request in the collection. In response to this determination, the first write request and the one or more other write requests are written together to the memory.05-03-2012
20100115181MEMORY DEVICE AND METHOD - A memory device may include a volatile memory and a non-volatile memory which are arranged to be accessed via a common bus. The memory device may include a controller that is arranged as an interface between the common bus and the volatile and non-volatile computer memories, the controller to transmit read/write commands from the common bus to either the volatile memory or the non-volatile memory.05-06-2010
20100125697COMPUTING DEVICE HAVING STORAGE, APPARATUS AND METHOD OF MANAGING STORAGE, AND FILE SYSTEM RECORDED RECORDING MEDIUM - A storage management apparatus and a file system for a storage device are provided. The storage management apparatus allocates a portion of storage for writing a file to the storage, including a table storing unit storing an allocation unit table that includes information of a unit of allocation of the storage according to a file extension of a file to be written. A storage management unit manages the storage based on the allocation unit table.05-20-2010
20100125696Memory Controller For Controlling The Wear In A Non-volatile Memory Device And A Method Of Operation Therefor - A memory controller controls the operation of a non-volatile memory device. The memory device has a data storage section and an erased storage section. The data storage section has a first plurality of blocks and the erased storage section has a second plurality of blocks. Each of the first and second plurality of blocks has a plurality of non-volatile memory bits that are erased together. Further, each block has an associated counter for storing the number of times the block has been erased. The memory controller has program instructions which are to scan the counters associated with the blocks of the first plurality of blocks based upon the count contained in each of the counters associated therewith to select a third block, and to scan the counters associated with the blocks of the second plurality of blocks based upon the count contained in each of the counters associated therewith to select a fourth block. The program instructions are further configured to transfer data from the third block to the fourth block, and associating said fourth block with said first plurality of blocks. Finally the program instructions are configured to erase said third block and incrementing the counter associated with said third block, and associating said third block with said second plurality of blocks. The present invention is also a method of operating a non-volatile memory device in accordance with the above described steps.05-20-2010
20100191902STORAGE DEVICE EMPLOYING A FLASH MEMORY - A semiconductor disk wherein a flash memory into which data is rewritten in block unit is employed as a storage medium, the semiconductor disk including a data memory in which file data are stored, a substitutive memory which substitutes for blocks of errors in the data memory, an error memory in which error information of the data memory are stored, and a memory controller which reads data out of, writes data into and erases data from the data memory, the substitutive memory and the error memory. Since the write errors of the flash memory can be remedied, the service life of the semiconductor disk can be increased.07-29-2010
20100037007NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device includes a memory cell array in which memory cells having an electrically rewritable charge accumulation layer are arranged, a data writing/reading circuit that writes/reads data to/from the memory cell array in units of pages, a write state information storage circuit for nonvolatile storage of write state information indicating a data write state to the memory cell array by the data writing/reading circuit, and a control circuit that controls the data writing/reading circuit based on an access page address indicating a page from which data is about to be read by the data writing/reading circuit and write state information stored in the write state information storage circuit.02-11-2010
20110197016Aggregation of Write Traffic to a Data Store - A method and a processing device are provided for sequentially aggregating data to a write log included in a volume of a random-access medium. When data of a received write request is determined to be suitable for sequentially aggregating to a write log, the data may be written to the write log and a remapping tree, for mapping originally intended destinations on the random-access medium to one or more corresponding entries in the write log, may be maintained and updated. At time periods, a checkpoint may be written to the write log. The checkpoint may include information describing entries of the write log. One or more of the checkpoints may be used to recover the write log, at least partially, after a dirty shutdown. Entries of the write log may be drained to respective originally intended destinations upon an occurrence of one of a number of conditions.08-11-2011
20100125695NON-VOLATILE MEMORY STORAGE SYSTEM - The present invention discloses a flash memory storage system, comprising at least one RAID controller; a plurality of flash memory cards electrically connected with the RAID controller; and a cache memory electrically connected with the RAID controller and shared by the RAID controller and the flash memory cards. The cache memory efficiently enhances the system performance. The storage system may comprise more RAID controllers to construct a nested RAID architecture.05-20-2010
20110078365DATA ACCESS METHOD OF A MEMORY DEVICE - The invention provides a data access method of a memory device. In one embodiment, the memory device comprises a plurality of memories. First, a plurality of commands sequentially received from a host is stored in a command queue. A target command is then retrieved from the command queue. A target memory accessed by the target command is then determined. Whether the target memory is in a busy state is then determined. When the target memory is not in a busy state, access operations requested by the target command are then performed. When the target memory is in a busy state, a substitute command is selected from a plurality of subsequent commands stored in the command queue and access operations requested by the substitute command are performed, wherein the sequence of the subsequent commands in the command queue is subsequent to the target command.03-31-2011
20080209106Memory access - A memory access system including a memory in which data is organized in pages, each page holding a sequence of data elements; means for receiving a requested address including a requested page address and a requested data element address; logic for accessing a current page from the memory using a current page address; logic for reading out data elements of the current page in the sequence in which they are held in memory; logic for comparing the requested page address with the current page address and for issuing a memory access request with the requested page address when they are not the same; and logic operable when the requested page address is the same as the current page address for comparing a requested data element address with the current address of a data element being read out and returning the data element when the requested data element address matches the current data element address.08-28-2008
20130219113MEMORY SYSTEM CONTROLLER - The present disclosure includes methods and devices for a memory system controller. In one or more embodiments, a memory system controller includes a host interface communicatively coupled to a system controller. The system controller has a number of memory interfaces, and is configured for controlling a plurality of intelligent storage nodes communicatively coupled to the number of memory interfaces. The system controller includes logic configured to map between physical and logical memory addresses, and logic configured to manage wear level across the plurality of intelligent storage nodes.08-22-2013
20130219106TRIM TOKEN JOURNALING - Systems and methods are disclosed for trim token journaling. A device can monitor the order in which trim commands and write commands are applied to an indirection system stored in a volatile memory of the device. In some embodiments, the device can directly write to a page of an NVM with a trim token that indicates that a LBA range stored in the page has been trimmed. In other embodiments, a device can add pending trim commands to a trim buffer stored in the volatile memory. Then, when the trim buffer reaches a pre-determined threshold or a particular trigger is detected, trim tokens associated with all of the trim commands stored in the trim buffer can be written to the NVM. Using these approaches, the same sequence of events that was applied to the indirection system during run-time can be applied during device boot-up.08-22-2013
20120036310DATA PROCESSING DEVICE - A data processing device is provided enabling faster read access to data in an on-chip EEPROM with relative ease, without increasing the area occupied by the chip and its power consumption. The on-chip nonvolatile memory included in the data processing device is provided with a pre-read cache which latches all or part of data, once having been read to bit lines from an array of nonvolatile memory cells by selecting a row address, and a selecting circuit which selects a portion of the data latched by the pre-read cache by selecting a portion of columns. Control is performed to retain address information for data latched by the pre-read cache, inhibit latching new data into the pre-read cache for read access to data in the nonvolatile memory according to the same address as the retained address information, and cause the selecting circuit to select the data latched by the pre-read cache.02-09-2012
20120036309COORDINATED GARBAGE COLLECTION FOR RAID ARRAY OF SOLID STATE DISKS - An optimized redundant array of solid state devices may include an array of one or more optimized solid-state devices and a controller coupled to the solid-state devices for managing the solid-state devices. The controller may be configured to globally coordinate the garbage collection activities of each of said optimized solid-state devices, for instance, to minimize the degraded performance time and increase the optimal performance time of the entire array of devices.02-09-2012
20100088462METHODS FOR HANDLING DATA UPDATING OF FLASH MEMORY AND RELATED MEMORY CARDS - A method for handling data updating of a flash memory is disclosed, in which the flash memory comprises a mother block with a plurality of pages to be updated, and each page comprises a plurality of sectors. In such method, a first data for updating a target page in the mother block is obtained, and then whether the first data comprises data for updating an ending sector in the target page is determined. The first data is written into a replacing page in a first FAT block when the first data does not comprise data for updating the ending sector in the target page. The first data is written into a corresponding page in a second FAT block when the first data comprises the data for updating the ending sector, in which the corresponding page in the second FAT block and the target page in the mother block have the same page indexes.04-08-2010
20090094406SCALABLE MASS DATA STORAGE DEVICE - A scalable data storage device which includes non-volatile memory uses a networked bus system which can be employed on a single memory storage chip level or in a multi-chip package (MCP). The scalable data storage device uses data routing modules which are adapted to store incoming data and send outgoing data thereby providing decoupling of the networked buses. This arrangement enables significantly higher data transfer rates, surpassing DRAM SSDs at a fraction of the size and cost, provides increased volumetric density (1 TB in less than 1 cubic inch), and permits concurrency of operations. The scalable data storage device can be engineered to have a rewrite capability of over 500 times that of Flash RAM and can scale down to 8 bits and up to exabytes, yottabytes and beyond. The scalable data storage device may be used in a wide range of applications from large data centers to small consumer electronic products.04-09-2009
20120066442SYSTEM AND METHOD OF PAGE BUFFER OPERATION FOR MEMORY DEVICES - Systems and methods are provided for using page buffers of memory devices connected to a memory controller through a common bus. A page buffer of a memory device is used as a temporary cache for data which is written to the memory cells of the memory device. This can allow the memory controller to use memory devices as temporary caches so that the memory controller can free up space in its own memory.03-15-2012
20080270677Safe software revision for embedded systems - The present invention, in one embodiment includes identifying a first partition of an embedded program memory, reading a description associated with the first partition, identifying a second partition of an embedded program memory, reading a description associated with the second partition, comparing descriptions, selecting an embedded program memory partition using the comparison, and writing program code to the selected program memory partition.10-30-2008
20120066437DATA PROGRAMMING CIRCUIT AND METHOD FOR OTP MEMORY - A data programming circuit is provided. A one-time-programmable (OTP) stores a first version of encoding data corresponding to a first version of a read-only memory (ROM) code. A control unit stores a second version of the ROM code into the OTP memory, wherein the control unit obtains a matching table according to the first version of the encoding data and the second version of the ROM code. The control unit obtains a first data segment of the first version of the encoding data and a second data segment of the second version of the ROM code that have the same content, according to the matching table. The control unit encodes the second data segment as a specific address, and the specific address points to the first data segment of the first version of the encoding data in the OTP memory.03-15-2012
20080270679CONTROL CIRCUIT OF FLASH MEMORY DEVICE AND METHOD OF OPERATING THE FLASH MEMORY DEVICE - Provided is a method of operating a flash memory device having a first area and a second area, in which a programmed state and an erased state of the first area are opposite to that of the second area. The method includes receiving a program command, inverting the program data when the received program command is a command for programming the second area, and programming the inverted program data into the second area.10-30-2008
20080270682METHOD FOR USING A MULTI-BIT CELL FLASH DEVICE IN A SYSTEM NOT DESIGNED FOR THE DEVICE - A computerized system is booted from a flash memory device configured to always operate one or more of its blocks only in a M-bit-per-cell mode and the rest of its blocks in a N>M-bit-per-cell mode. When the system is powered up, an initialization program is retrieved from the M-bit-per-cell block(s), corrected for errors using a first error correction method, and executed. Data accessed subsequently from the N-bit-per-cell blocks are corrected using an error correction method that corrects more errors per block than the first error correction method.10-30-2008
20080270678COMMAND RESEQUENCING IN MEMORY OPERATIONS - Systems and processes may include a memory coupled to a memory controller. Command signals for performing memory access operations may be received. Attributes of the command signals, such as type, time lapsed since receipt, and relatedness to other command signals, may be determined. Command signals may be sequenced in a sequence of execution based on the attributes. Command signals may be executed in the sequence of execution.10-30-2008
20100125702Non-Volatile Memory System and Access Method Thereof - Disclosed is a method for accessing a non-volatile memory device using a flash translation layer. The method includes receiving a write request for data from a file system and recording the data in the non-volatile memory device in response to the write request. The flash translation layer is informed whether a confirm mark for the data is recorded or not from the file system.05-20-2010
20100125699Flash memory device and reading method thereof - Provided are a flash memory device and a reading method of the flash memory device. A multi-level cell flash memory device includes: a memory cell array comprising main memory cells storing main data, and indicator cells storing indicate data indicating one of a first mode and a second mode in which the main data of the main memory cell, to which the indicate cells correspond, is written; and an output unit outputting in response to a control signal corresponding to the indicate data, one of main data read from the memory cell array and forced data forcing some bit values of the main data to bit values of mode specific data, as reading data.05-20-2010
20100125700DISK DRIVE AND METHOD OF CHANGING A PROGRAM THEREFOR - A method of changing a program for controlling a disk drive that includes an EEPROM. The method includes storing a program block to a disk area such that the program block is associated with a second area for storing the program block that is not utilized for a read operation from the disk area. The method also includes storing a program block that is associated with a first area to an area that includes at least a portion of the second area in the EEPROM such that the first area contained a program block that is utilized for a read operation from the disk area. In addition, the method includes changing the program block in the first area after storing to the second area. Moreover, the method includes storing to the second area the program block that is not utilized for a read operation from the disk area after storing to the first area.05-20-2010
20110197018METHOD AND SYSTEM FOR PERPETUAL COMPUTING USING NON-VOLATILE RANDOM ACCESS MEMORY - Provided is a computing system and method that utilizes a non-volatile random access memory (NVRAM). A system including the NVRAM as a part of a memory or a whole memory may execute a program in the NVRAM, and, when the system is re-operated after being shut down, may restore a state and data of the program being executed in the NVRAM to an original state and thus, may provide a permanent computing environment.08-11-2011
20120159050MEMORY SYSTEM AND DATA TRANSFER METHOD - According to one embodiment, a memory system comprises a nonvolatile memory including a memory cell array and a read buffer and a controller configured to receive a read request and to issue a first read command and a second read command to the memory. When issuing the first read command, the memory transfers data of the first size from the memory cell array to the read buffer and outputs the data from the read buffer to the controller. When issuing the second read command, the memory transfers first data of the first size from the memory cell array to the read buffer, outputs the first data from the read buffer to the controller, and transfers second data of the first size from the memory cell array to the read buffer. The controller selects one command from the two commands according to the read request.06-21-2012
20090070518Adaptive Block List Management - In a nonvolatile memory array, selected blocks are maintained as open blocks that are available to store additional data without being erased first. Nonsequential open blocks are selected from two lists, one list based on recency of the last write operation, and the other list based on frequency of writes to the block. Sequential open blocks are divided into blocks expected to remain sequential and blocks that are not expected to remain sequential.03-12-2009
20120210047RAM Daemons - A method of managing a database system using a swarm database system that communicates a request to read data to at least a subset of nodes. Checking the identifier by each respective node in the subset of nodes to determine if the requested read data is stored in the node. Providing the read data to the first node if the respective node in the subset includes read data.08-16-2012
20120278539MEMORY APPARATUS, MEMORY CONTROL APPARATUS, AND MEMORY CONTROL METHOD - A memory apparatus includes: a plurality of flash memory sections connected to a common data line; and a control section configured to perform control for data read/write on the plurality of flash memory sections, wherein the control section performs control so as to give a read instruction to a first flash memory section among the plurality of flash memory sections to output read data from the first flash memory section onto the common data line, and to give a write instruction to a second flash memory section other than the first flash memory section to write the read data obtained on the common data line into the second flash memory section with timing in accordance with timing of outputting the read data from the first flash memory section.11-01-2012
20100287331ELECTRONIC DEVICE AND METHOD FOR RECORDING POWER-ON TIME THEREOF - An electronic device and a method for recording power-on time include a flash memory to store a plurality of bits used to record power-on time. The electronic device sets the plurality of bits stored in the flash memory to a first value, sets a changing interval, and copies the plurality of bits from the flash memory to a random access memory (RAM). The electronic device further searches for a first bit of the first value from the plurality of bits in the RAM, and records an index of the first bit of the first value in a variable. The electronic device further changes the bit corresponding to the variable to a second value and increases the variable by 1 when the changing interval arrives. The electronic device further writes the bit changed to the second value from the RAM to the flash memory.11-11-2010
20120331218FLASH MEMORY STORAGE SYSTEM, AND CONTROLLER AND ANTI-FALSIFYING METHOD THEREOF - A flash memory storage system having a flash memory controller, a flash memory chip and a smart card chip is provided. The flash memory chip is configured to store security data. The flash memory controller generates a signature corresponding to the security data according to a private key and the security data with a one-way hash function, and stores the signature into the smart card chip.12-27-2012
20100082887MEMORY CONTROLLER, FLASH MEMORY SYSTEM WITH MEMORY CONTROLLER, AND METHOD OF CONTROLLING FLASH MEMORY - The memory controller forms temporary virtual blocks each composed of a plurality of physical blocks, whose physical addresses are the same value, each of which is included in each of flash memories, extracts temporary virtual block to which at least one defective block belongs from the temporary virtual blocks, generates a second temporary virtual block to which a defective block does not belong by replacing a defective block belonging to one temporary virtual block with a normal block belonging to another temporary virtual block among temporary virtual blocks extracted, and allocates temporary virtual blocks not extracted and second temporary virtual blocks generated to available virtual blocks.04-01-2010
20100082878MEMORY CONTROLLER, NONVOLATILE STORAGE DEVICE, NONVOLATILE STORAGE SYSTEM, AND DATA WRITING METHOD - Used is a nonvolatile memory such as a multi-level NAND flash memory having memory cells for holding data of a plurality of pages. When the data is to be written in the nonvolatile memory 04-01-2010
20130031299DISK INPUT/OUTPUT (I/O) LAYER ARCHITECTURE HAVING BLOCK LEVEL DEVICE DRIVER - In general, embodiments of the present invention provide a disk an I/O layer architecture having a customized block-level device driver. In a typical embodiment, the architecture described herein comprises a file system layer being configured to handle user data; a buffer cache layer, adjacent the file system layer, the buffer cache layer being configured to handle page data; a block device driver layer adjacent the buffer cache layer, the block device driver layer being configured to handle block data, and the block device driver layer comprising an I/O scheduler layer and a device driver layer; and a storage unit layer adjacent the block device driver layer, the storage unit layer being configured to hand command data. Moreover, the storage unit layer can comprise a set (e.g., at least one) of semiconductor storage device (SSD) memory units, and the I/O scheduler layer can be configured to handle memory-based devices (e.g. a flash SSD memory device, a dynamic random access memory (DRAM) SSD memory device, etc.).01-31-2013
20100088463NONVOLATILE MEMORY SYSTEM AND DATA PROCESSING METHOD - A solid-state disk device exchanging data with a host includes a nonvolatile memory device, a buffer memory configured to temporarily store data exchanged between the host and the nonvolatile memory, and a buffer manager configured to control transfer of data to/from the buffer memory, wherein the transfer of data between the nonvolatile memory device and the host during a streaming mode of operation begins immediately when a defined unit data is input to the buffer memory.04-08-2010
20100088466STORAGE DEVICE, STORAGE CONTROL DEVICE, AND CONTROL METHOD - According to one embodiment, a storage device includes an actuator to move a head to a position on a disk medium; a module to record or reproduce data to or from the disk medium using the head; a memory controller to write or read to or from a non-volatile memory; a buffer controller to write or read to or from a buffer memory; an interface controller to transmit and receive to or from an upper device; a switching module to switch data transfer paths among the module, the memory controller, and the interface controller; and an access controller to control the switching module to transfer data read from the non-volatile memory to the upper device concurrently with transferring and storing the read data in a cache region of the buffer memory, upon receiving from the upper device a command to read the data from the non-volatile memory.04-08-2010
20100217924HYBRID MEMORY DEVICE WITH SINGLE INTERFACE - Described is a technology by which a memory controller is a component of a hybrid memory device having different types of memory therein (e.g., SDRAM and flash memory), in which the controller operates such that the memory device has only a single memory interface with respect to voltage and access protocols defined for one type of memory. For example, the controller allows a memory device with a standard SDRAM interface to provide access to both SDRAM and non-volatile memory with the non-volatile memory overlaid in one or more designated blocks of the volatile memory address space (or vice-versa). A command protocol maps memory pages to the volatile memory interface address space, for example, permitting a single pin compatible multi-chip package to replace an existing volatile memory device in any computing device that wants to provide non-volatile storage, while only requiring software changes to the device to access the flash.08-26-2010
20090287873SEMICONDUCTOR INTEGRATED CIRCUIT, SYSTEM DEVICE INCLUDING SEMICONDUCTOR INTEGRATED CIRCUIT, AND SEMICONDUCTOR INTEGRATED CIRCUIT CONTROL METHOD - A disclosed semiconductor integrated circuit interfaces an external circuit and a host for controlling the external circuit and obtains data used to interface the external circuit and the host from a rewritable external memory. The disclosed semiconductor integrated circuit includes external terminals to which an external signal line group is connected, the external signal line group including signal lines connecting the external circuit and the external memory in parallel; an external terminal interface circuit configured to interface the semiconductor integrated circuit and the external circuit or the external memory connected via the external signal line group; and a control circuit configured to activate or deactivate the external circuit and the external memory. The control circuit is configured to activate either the external circuit or the external memory that is to be accessed via the external terminal interface circuit.11-19-2009
20090210614Non-Volatile Memories With Versions of File Data Identified By Identical File ID and File Offset Stored in Identical Location Within a Memory Page - In the file storage system, each portion belonging to a data file is identified by its file ID and an offset along the data file, where the offset is a constant for the file and every file data portion is always kept at the same position within a memory page to be read or programmed in parallel. In this way, every time a page containing a file portion is read and copy to another page, the data in it is always page-aligned, and each bit within the file portion can always be manipulated by the same sense amplifier and same set data latches within the same memory column. In a preferred implementation, the page alignment is such that (offset within a page)=(data offset within a file) MOD (page size). Any gaps that may exist in page can be padded with any existing page-aligned valid data.08-20-2009
20090070523Flash memory device storing data with multi-bit and single-bit forms and programming method thereof - A flash memory device may include a memory cell array including a plurality of memory blocks and a partition information block, the partition information block storing partition information that indicates a boundary between multi-bit memory blocks and single-bit memory blocks among the memory blocks. The memory device may include a control logic configured to determining whether a memory block that a block address from the outside indicates has a multi-bit form or a single-bit form based on the partition information and to control program and read operations in a multi-bit form or a single-bit form based on a determination result. The control logic automatically programs data in the partition information block according to whether a fuse connected to the control logic fuse is cut or not, the data being used for preventing the partition information block from being programmed or erased.03-12-2009
20110191531MEMORY DEVICE AND CONTROL METHOD THEREOF - A control method of a memory device including a storage area formed of a nonvolatile semiconductor memory, includes updating a file stored in the storage area by using a file system which supports an incremental write method, recording, in the storage area, an allocation table representing a correlation between a logical address indicating a recording position of the file and a virtual address representing a virtual recording position of the file and management information of the allocation table, and recording position information representing a recording position of the management information in a position information area of the storage area.08-04-2011
20110185105MEMORY SYSTEM - A memory system in which speed of processing for searching through management tables is increased by providing a forward lookup table for searching for, respectively in track and cluster units, from a logical address, a storage device position where data corresponds to the logical address, and a reverse lookup table for searching for, from a position of the storage device, a logical address stored in the position. These forward and reverse lookup tables are linked.07-28-2011
20100100668CONTROL METHOD FOR LOGICAL STRIPS BASED ON MULTI-CHANNEL SOLID-STATE NON-VOLATILE STORAGE DEVICE - A control method for logical strips based on a multi-channel solid-state non-volatile storage device is provided. The method includes the following processing steps. In Step 1, a storage space of every channel is partitioned into a plurality of storage units of equal size. In Step 2, at least one logical strip is set by which the storage units with discrete physical addresses across a plurality of channels are organized into a continuous logical space. In Step 3, during data reading/writing operation, the data is divided according to a size of each local strip, the divided data is mapped to the storage units of every channel, and a parallel reading/writing operation is performed across the channels. This method may increase the efficiency of reading and writing operations of the storage device and prolong the operating life span of the device.04-22-2010
20090300274SSD WITH DISTRIBUTED PROCESSORS - In one embodiment, a system includes a serial data bus, a plurality of processors of a first type, and a processor of a second type. The serial data bus is configured to be coupled to a corresponding serial data bus of a host device. Each of the plurality of processors of the first type is coupled to a respective flash memory device. The processor of the second type is configured to manage the access that the plurality of the processors of the first type have to the serial data bus.12-03-2009
20100082885METHOD AND SYSTEM FOR ADAPTIVE CODING IN FLASH MEMORIES - Bits are stored by attempting to set parameter value(s) of (a) cell(s) to represent some of the bits. In accordance with the attempt, an adaptive mapping of the bits to value ranges is provided and the value(s) is/are adjusted accordingly as needed. Or, to store (a) bit(s) in (a) cell(s), a default mapping of the bit(s) to a predetermined set of value ranges is provided and an attempt is made to set the cell value(s) accordingly. If, for one of the cells, the attempt sets the value such that the desired range is inaccessible, an adaptive mapping is provided such that the desired range is accessible. Or, to store (a) bit(s) in (a) cell(s), several mappings of the bit(s) to a predetermined set of ranges is provided. Responsive to an attempt to set the cell value(s) according to one of the mappings, the mapping to actually use is selected.04-01-2010
20100082893Flash Memory Controller For Electronic Data Flash Card - An electronic data flash card is accessible by a host computer, and includes a processing unit connected to a flash memory device that stores a data file, and an input-output interface circuit activated so as to establish a communication with the host computer. In an embodiment, the electronic data flash card uses a USB input/output interface circuit for communication with the host computer. A flash memory controller includes an index for converting logical addresses sent by the host computer into physical addresses associated with sectors of the flash memory device. The index is controlled by arbitration logic referencing to values from various look up tables and valid data stored in the flash memory device. The flash memory controller further includes a first-in-first-out unit (FIFO) for recycling obsolete sectors of the flash memory device in the background process so that they are available for reprogramming.04-01-2010
20100082886VARIABLE SPACE PAGE MAPPING METHOD AND APPARATUS FOR FLASH MEMORY DEVICE - Disclosed is a method and apparatus embodying a flash translation layer (FTL) in a storage device including a flash memory. The FTL may classify a block into a sequential group and a fusion group based on a locality of a write request. The FTL may store data in blocks of the fusion group by using a page mapping scheme, and sequentially store data by using a block mapping scheme. The FTL may improve efficiency of garbage collection operation that is performed by using limited redundant blocks and also may increase efficiency of a non-sequential reference operation.04-01-2010
20100082881SOLID STATE STORAGE DEVICE CONTROLLER WITH EXPANSION MODE - Solid state storage device controllers, solid state storage devices, and methods for operation of solid state storage device controllers are disclosed. In one such solid state storage device, the controller can operate in either an expansion DRAM mode or a non-volatile memory mode. In the DRAM expansion mode, one or more of the memory communication channels normally used to communicate with non-volatile memory devices is used to communicate with an expansion DRAM device.04-01-2010
20100082883Hybrid density memory system and control method thereof - A control method of a memory system for accessing an updated data between a host and the memory system is provided. The host has storage space which is divided into a plurality of logical segments to access the data. The system includes a high density memory and a low density memory, and the high density memory includes a plurality of physical segments to access the data. The control method includes the following steps: first, providing a LDM table in the memory system to indicate the allocation information of the low density memory; finally, deciding where the data is written to is according to its properties and the LDM table.04-01-2010
20100082882SEMICONDUCTOR DISK DEVICES AND RELATED METHODS OF RANDOMLY ACCESSING DATA - A computing system includes a host, a data source device, and a controller. The controller is configured to respond to a random access command from the host by setting information in a register that selects what data is to be accessed in the data source device. The controller then successively accesses the data in the data source device using the information that was set in the register.04-01-2010
20100082879PRIORITY COMMAND QUEUES FOR LOW LATENCY SOLID STATE DRIVES - A method, apparatus, and system of a priority command queues for low latency solid state drives are disclosed. In one embodiment, a system of a storage system includes a command sorter to determine a target storage device for at least one of a solid state drive (SSD) command and a hard disk drive (HDD) command and to place the command in a SSD ready queue if the SSD command is targeted to a SSD storage device of the storage system and to place the HDD command to a HDD ready queue if the HDD command is targeted to an HDD storage device of the storage system, a SSD ready queue to queue the SSD command targeted to the SSD storage device, and a HDD ready queue to queue the HDD command targeted to the HDD storage device.04-01-2010
20090259797METHOD, APPARATUS AND COMPUTER READABLE MEDIUM FOR STORING DATA ON A FLASH DEVICE USING MULTIPLE WRITING MODES - Methods, apparatus and computer readable medium for writing data into a flash memory device are disclosed. In some embodiments, the data is written in a writing mode selected in accordance with an extent to which the flash memory storage device or a flash die thereof is full of previously-stored data. The presently disclosed techniques may be implemented on the “device-side” (for example, by a device controller of the flash device) and/or on the “host-side.” In some embodiments, the selected writing mode is a bits-per-cell density mode. In some embodiments, the selected writing mode is a “slower” or “faster” writing mode. The presently disclosed techniques relate to SBC as well as MBC devices.10-15-2009
20090172268METHOD FOR SECURING A MICROPROCESSOR, CORRESPONDING COMPUTER PROGRAM AND DEVICE - A method is provided for securing a microprocessor containing at least one main program, which operates with at least one memory. The method includes implementing counter-measures, during which additional operations, that are not required for the main program, are implemented so as to modify the consumption of current and/or the processing time of the microprocessor. The method also includes: identification of at least one address or one memory zone of the memory(ies), called critical addresses, and which contain, or which may contain, critical data for said main program; monitoring the addressing ports of the memory(ies), so as to detect the access to the critical address(es); and activation of the step of implementing counter-measures, when an access to the critical address(es) is detected.07-02-2009
20100100666SYSTEM AND METHOD FOR CONTROLLING FLASH MEMORY USING DESCRIPTOR ARRAY - Disclosed are a system and method for controlling a flash memory using a descriptor array, which may maximize a performance of a flash memory based-storage system. The system includes a descriptor array receipt unit for receiving, from a processor, a descriptor array including, at least one descriptor corresponding to at least one operation; and a flash memory control unit for verifying the descriptor included in the descriptor array and executing a flash memory control command included in the verified descriptor, wherein the flash memory control unit executes the flash memory control command independent from the operation of the processor.04-22-2010
20100100663Method of Performing Wear Leveling with Variable Threshold - A wear leveling limit and/or an overall erase count threshold used for activating wear leveling in a non-volatile memory may be adjusted by determining a stage according to a highest erase count, and determining the wear leveling limit and/or the overall erase count threshold corresponding to the stage. Wear leveling may then be performed according to the wear leveling limit and/or the overall erase count threshold.04-22-2010
20090089481Leveraging Portable System Power to Enhance Memory Management and Enable Application Level Features - A memory device and techniques for its operation are presented. After operating on power received from a host, the memory device determines that it is no longer receiving host power and, in response, activates a power source on the memory device itself. Using this reserve power, the memory device can then perform data management operations. The techniques can also be applied to a digital appliance having a non-volatile memory. The memory device or digital appliance can prioritize its memory management operation during the host/user operating window based on the ability to perform these operations outside of the host/user operating window. Additionally, in a data write operations, where the memory device receives data from a host, stores the data in volatile memory, and then writes the data into the non-volatile memory, the memory device sends the host an acknowledgment of the data having been written into the non-volatile memory after it has been store in the volatile memory, but before the write into the non-volatile memory is complete.04-02-2009
20090089491SEMICONDUCTOR MEMORY DEVICE AND DATA MANAGEMENT METHOD USING SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises: a memory part which has a plurality of memory blocks having a memory cell capable of storing a plurality of different kinds of data which require a memory area having different characteristics, and a memory controller which has a function of treating each of the memory blocks as a deletion unit in order to manage the memory part and converting a logic address of the memory part to a physical address identifying the memory block, and which replaces the memory block with a preregistered free block in rewriting the memory block. The memory controller manages the different kinds of data to be stored in the memory part so as to store the same kind of data as before, even after each of the memories and free blocks in the memory part are rewritten.04-02-2009
20090089487MULTIPORT SEMICONDUCTOR MEMORY DEVICE HAVING PROTOCOL-DEFINED AREA AND METHOD OF ACCESSING THE SAME - A multiprocessor system includes a first processor for performing a first task, a second processor for performing a second task, and a multiport semiconductor memory device having a protocol-defined area for defining a specification related to data communication between the first processor and the second processor. The protocol-defined area is located in at least one shared memory area accessible in common by the first processor and the second processor through a first port and a second port, respectively, and is assigned as a predetermined memory capacity to a portion of a memory cell array.04-02-2009
20090182933DURABLE DATA STORAGE SYSTEM AND METHOD - A method of operating a storage system, comprising: issuing a first command to write a first data to a first nonvolatile storage device; writing the first data to a second nonvolatile storage device if write condition is unstable; retrieving the first data from the second nonvolatile storage device; and writing the first data to the first nonvolatile storage device during a stable write condition, wherein whether write condition is stable is determined based on one of a sensor output or a memory access status signal, and wherein the memory access status signal is one of a predetermined value of retries, idling, access commands, or any combination thereof.07-16-2009
20100100669SELF-ADAPTIVE CONTROL METHOD FOR LOGICAL STRIPS BASED ON MULTI-CHANNEL SOLID-STATE NON-VOLATILE STORAGE DEVICE - A self-adaptive control method for logical strips based on a multi-channel solid-state non-volatile storage device is provided. The method includes the following steps. Storage space of every channel is divided into a plurality of storage units of equal size. At least one logical strip is set by which the storage units with discrete physical addresses across the channels are organized into a continuous logical space, and a logical strip variable is set for determining the storage units organized by the logical strip. Historical operation information of the storage device is obtained statistically, and the logical strip variable is dynamically adjusted according to the obtained operation information. During data interaction, the data is divided according to the logical strip variable, the divided data is mapped to the storage units of every channel, and parallel reading and writing operations are performed among the channels.04-22-2010
20090282184COMPENSATING NON-VOLATILE STORAGE USING DIFFERENT PASS VOLTAGES DURING PROGRAM-VERIFY AND READ - Optimized verify and read pass voltages are obtained to improve read accuracy in a non-volatile storage device. The optimized voltages account for changes in unselected storage element resistance when the storage elements become programmed. This change in resistance is referred to as a front pattern effect. In one approach, the verify pass voltage is higher than the read pass voltage, and a common verify voltage is applied on the source and drain sides of a selected word line. In other approaches, different verify pass voltages are applied on the source and drain sides of the selected word line. An optimization process can include determining a metric for different sets of verify and read pass voltages. The metric can indicate threshold voltage width, read errors or a decoding time or number of iterations of an ECC decoding engine.11-12-2009
20090287877MULTI NON-VOLATILE MEMORY CHIP PACKAGED STORAGE SYSTEM AND CONTROLLER AND ACCESS METHOD THEREOF - A multi non-volatile memory chip packaged storage system having a memory module, a controller, a first and a second control buses and a first and a second I/O buses is provided. The memory module at least includes a first and a second non-volatile memory chips which are both enabled by receiving a chip enabled signal via a chip enabled pin, wherein the memory module and the controller are stacked and packaged as a single chip. After the first and the second non-volatile memory chips are enabled by the chip enable signal via the chip enabled pin, the controller may active the first and second control buses and the first and second I/O buses to access the first and the second non-volatile memory chips, or only active the first control and I/O buses or the second control and I/O buses to access the corresponding first or second non-volatile memory chip.11-19-2009
20120144093INTERLEAVING CODEWORD PORTIONS BETWEEN MULTIPLE PLANES AND/OR DIES OF A FLASH MEMORY DEVICE - A system, a method and non-transitory computer readable medium storing instructions for interleaving at least two portions of a first codeword of the group between at least two flash memory planes while violating at least one ordering rule out of (a) an even odd ordering rule, (b) a programming type ordering rule, and (c) a codeword portions ordering rule and interleaving different portions of other codewords of the group between multiple flash memory planes while maintaining the even odd ordering rule, the programming type ordering rule and the codeword portions ordering rule.06-07-2012
20120144098MULTIPLE LOCALITY-BASED CACHING IN A DATA STORAGE SYSTEM - A data storage caching architecture supports using native local memory such as host-based RAM, and if available, Solid State Disk (SSD) memory for storing pre-cache delta-compression based delta, reference, and independent data by exploiting content locality, temporal locality, and spatial locality of data accesses to primary (e.g. disk-based) storage. The architecture makes excellent use of the physical properties of the different types of memory available (fast r/w RAM, low cost fast read SSD, etc) by applying algorithms to determine what types of data to store in each type of memory. Algorithms include similarity detection, delta compression, least popularly used cache management, conservative insertion and promotion cache replacement, and the like.06-07-2012
20080288716STORAGE DEVICE - A storage device includes: a binary flash memory that has a first storage area and a capacity of storing two values per each cell; a multivalued flash memory that has a second storage area and a capacity of storing at least three values per each cell; and a controller configured to arrange the first storage area ahead of the second storage area, logically combine the first storage area with the second storage area to form a single combined storage area, and perform data reading and data writing from and into the combined storage area. Data management information is stored in a head of the combined storage area according to a predetermined file system. The storage device of this arrangement has the advantages of both an SLC flash memory and an MLC flash memory.11-20-2008
20120297117DATA STORAGE DEVICE AND DATA MANAGEMENT METHOD THEREOF - Disclosed is a data managing method of a storage device including a nonvolatile memory device. The data managing method includes detecting an update count of update-requested page data and allocating the update-requested page data to a first memory block or a second memory block based upon the update count, an erase count of the second memory block being different from that of the first memory block.11-22-2012
20090089488MEMORY SYSTEM, MEMORY READ METHOD AND PROGRAM - According to one embodiment, there is disclosed a memory system comprising a flash memory unit which suspends a write operation to execute a read operation when receiving a suspend command during a write operation, a CPU, an OS which includes a device driver, a TLB which has a page table for conversion from a virtual address to a physical address, and an application program which makes a TLB setting request with respect to the device driver when receiving a read command under the control of the CPU and the OS, acquires address information read from the page table of the TLB by the device driver in response to the setting request, and executes read directly with respect to the flash memory unit using the acquired address information without using the device driver.04-02-2009
20090089490MEMORY SYSTEM - A memory system including a nonvolatile memory, a first controller connected to a host equipment, the first controller controlling the entire memory system, a second controller connected to the first controller and also connected to the nonvolatile memory, the second controller controlling an access process to said nonvolatile memory, the second controller receives a command via the first controller and carries out the access process to the nonvolatile memory according to the command, the command being input from the host equipment.04-02-2009
20090089486PORTABLE DATA STORAGE DEVICE INCORPORATING MULTIPLE FLASH MEMORY UNITS - A portable data storage device is disclosed which includes an Interface for enabling the portable data storage device to be used for data transfer with a host Computer, and an Interface controller for controlling the interface. There is also a master control unit for controlling the writing of data to and reading data from a non-volatile memory. The non-volatile memory includes at least one single layer cell flash memory and at least one multiple layer cell flash memory. Upon receiving a write instruction, the master control unit determines which of the memories data contained in the instruction should be written to, and writes the data as appropriate similarly, upon receiving a read instruction, the master control unit reads the data from the appropriate one of the memories and transmits the data out of the device.04-02-2009
20090089485WEAR LEVELING METHOD AND CONTROLLER USING THE SAME - A wear leveling method for a non-volatile memory is provided. The non-volatile memory is substantially divided into a plurality of blocks, and these blocks are grouped into at least a data area, a spare area, a substitute area, and a temporary area. The wear leveling method includes selecting blocks from the spare area according to different purposes and executing a wear leveling procedure.04-02-2009
20090089483Storage device and deduplication method - This storage device performs deduplication of eliminating duplicated data by storing a logical address of one or more corresponding logical unit memory areas in a prescribed management information storage area of a physical unit memory area defined in the storage area provided by the flash memory chip, and executes a reclamation process of managing a use degree as the total number of the logical addresses used stored in the management information storage area and a duplication degree as the number of valid logical addresses corresponding to the physical unit memory area for each of the physical unit memory areas, and returning the physical unit memory area to an unused status when the difference of the use degree and the duplication degree exceeds a default value in the physical unit memory area.04-02-2009
20090089482DYNAMIC METABLOCKS - A nonvolatile block erasable memory array links erase blocks together for programming with high parallelism as a metablock. Erase blocks are operated in banks, with each bank having a dedicated bus and controller. Sub-metablocks of different metablocks, in different banks, are accessed in parallel allowing different metablocks to be updated at the same time.04-02-2009
20080209115SEMICONDUCTOR MEMORY CARD ACCESS APPARATUS, A COMPUTER-READABLE RECORDING MEDIUM, AN INITIALIZATION METHOD, AND A SEMICONDUCTOR MEMORY CARD - A predetermined number of erasable blocks positioned at a start of a volume area in a semiconductor memory card are provided so as to include volume management information. A user area following the volume management information includes a plurality of clusters. A data length NOM of an area from a master boot record & partition table sector to a partition boot sector is determined so that the plurality of clusters in the user area are not arranged so as to straddle erasable block boundaries. Since cluster boundaries and erasable block boundaries in the user area are aligned, there is no need to perform wasteful processing in which two erasable blocks are erased to rewrite one cluster.08-28-2008
20080209113Method For Increasing Storage Capacity of a Memory Device - A method for increasing memory storage capacity in a memory device having at least two storage cells wherein at least one measurable physical property is associated with each of the storage cells a nominal value of which may be used to assign a data value to the respective storage cell. Differences between at least two storage cells with regard to the respective nominal values of one or more of the respective physical properties associated with a storage cell and its actual value at a given time are used to provide additional storage capacity.08-28-2008
20080209111OVER-SAMPLING READ OPERATION FOR A FLASH MEMORY DEVICE - A flash memory device and a reading method are provided where memory cells are divided into at least two groups. Memory cells are selected according to a threshold voltage distribution. Data stored in the selected memory cells are detected and the data is latched corresponding to one of the at least two groups according to a first read operation. A second read operation detects and latches data of the memory cells corresponding to another one of the at least two groups. The data is processed through a soft decision algorithm during the second read operation.08-28-2008
20080209116Multi-Processor Flash Memory Storage Device and Management System - A data storage device has a host controller interface, a plurality of microprocessor units each having a portion of random access memory (RAM) dedicated thereto, a plurality of Flash device configurations each having dedicated bus connections to individual ones or multiples of the microprocessor units, and a dataflow controller accessible to the host controller interface for managing access to the Flash device configurations.08-28-2008
20080209110APPARATUS AND METHOD OF PAGE PROGRAM OPERATION FOR MEMORY DEVICES WITH MIRROR BACK-UP OF DATA - An apparatus and method of page program operation is provided. When performing a page program operation with a selected memory device, a memory controller loads the data into the page buffer of one selected memory device and also into the page buffer of another selected memory device in order to store a back-up copy of the data. In the event that the data is not successfully programmed into the memory cells of the one selected memory device, then the memory controller recovers the data from the page buffer of the other memory device. Since a copy of the data is stored in the page buffer of the other memory device, the memory controller does not need to locally store the data in its data storage elements.08-28-2008
20080209108System and method of page buffer operation for memory devices - Systems and methods are provided for using page buffers of memory devices connected to a memory controller through a common bus. A page buffer of a memory device is used as a temporary cache for data which is written to the memory cells of the memory device. This can allow the memory controller to use memory devices as temporary caches so that the memory controller can free up space in its own memory.08-28-2008
20090113115NON-VOLATILE MEMORY ARRAY PARTITIONING ARCHITECTURE AND METHOD TO UTILIZE SINGLE LEVEL CELLS AND MULTI-LEVEL CELLS WITHIN THE SAME MEMORY - A memory device is disclosed, and includes an array of memory cells and a partitioning system configured to address a first portion of the array in a single level cell mode, and a second portion of the array in a multi-level cell mode.04-30-2009
20090106482MEMORY DEVICE PROGRAM WINDOW ADJUSTMENT - In one or more embodiments, a memory device is disclosed as having an adjustable programming window having a plurality of programmable levels. The programming window is moved to compensate for changes in reliable program and erase thresholds achievable as the memory device experiences factors such as erase/program cycles that change the program window. The initial programming window is determined prior to an initial erase/program cycle. The programming levels are then moved as the programming window changes, such that the plurality of programmable levels still remain within the program window and are tracked with the program window changes.04-23-2009
20110271045Controller for One Type of NAND Flash Memory for Emulating Another Type of NAND Flash Memory - A method of executing an erasing instruction to erase host data from a flash memory device is provided. The method initiates with receiving from a host device an erase instruction to erase host data from an array of NAND flash memory cells grouped into separately-erasable device blocks, each device block including multiple device pages, the host data being a portion of device data that is stored in a device block. The host data is marked as erased, and a message is sent to the host device indicating that the host data has been erased.11-03-2011
20110271043SYSTEM AND METHOD FOR ALLOCATING AND USING SPARE BLOCKS IN A FLASH MEMORY - A method for using a single spare block pool in flash memory comprising: allocating a plurality of flash memory arrays, wherein each flash memory array comprises a plurality of flash memory blocks; within a main flash memory array: allocating a used block pool comprising a plurality of used blocks and allocating a main spare block pool comprising a plurality of spare blocks; within each of the other flash memory arrays: allocating a used block pool comprising multiple used blocks; allocating a minimum spare block pool comprising a minimum number of spare blocks; allocating the main spare block pool and each of the minimum spare block pools to a single spare block pool; transferring a spare block from the main spare block pool to one of the minimum spare block pools; and transferring a spare block from a first minimum spare block pool to a second minimum spare block pool.11-03-2011
20110271042METHOD FOR WRITING INTO AND READING FROM AN ATOMICITY MEMORY - A method for writing data into a reprogrammable non-volatile memory, wherein a marking pattern including several bits is added at the beginning of the data and the set formed of the marking pattern and of the data is written from an address in the memory varying from one write operation to another, the marking pattern being identical for each write operation.11-03-2011
20110271041ELECTRONIC DEVICE COMPRISING FLASH MEMORY AND RELATED METHOD OF HANDLING PROGRAM FAILURES - A storage device performs a program operation to store program data in a selected memory block of a flash memory. The storage device allocates a reserved area of the flash memory as a free block upon detecting that a program failure has occurred in the program operation, reads the program data from a cache latch in a page buffer of the flash memory, copies valid data stored in the selected memory block to a first area of the free block, and reprograms the program data read from the cache latch to a second area of the free block.11-03-2011
20110271040MEMORY SYSTEM HAVING NONVOLATILE SEMICONDUCTOR STORAGE DEVICES - According to an embodiment, a memory system includes a memory unit, a memory controller, a timer and a timer control unit. The memory unit has nonvolatile first and second chips capable of holding data. The memory controller transfers data received from host equipment simultaneously to the first and second chips. The timer measures a lapse of preset shift time. The timer control unit starts writing of data into the second chip immediately after the lapse of the shift time.11-03-2011
20110173378COMPUTER SYSTEM WITH BACKUP FUNCTION AND METHOD THEREFOR - A solid-state mass storage device and method of anticipating a failure of the mass storage device resulting from a memory device of the mass storage device reaching a write endurance limit. A procedure is then initiated to back up data to a second mass storage device prior to failure. The method includes assigning at least a first memory block of the memory device as a wear indicator, using other memory blocks of the memory device as data blocks for data storage, performing program/erase (P/E) cycles and wear leveling on the data blocks, subjecting the wear indicator to more P/E cycles than the data blocks, performing integrity checks and monitoring the bit error rate of the wear indicator, and taking corrective action if the bit error rate increases, including the initiation of the backup procedure and generating a request to replace the device.07-14-2011
20090300272Method for increasing reliability of data accessing for a multi-level cell type non-volatile memory - A method for increasing reliability of data accessing for a multi-level cell type non-volatile memory, wherein a plurality of data storage blocks are taken for data accessing of a computer system in accordance with the structure of storage of the multi-level cell type non-volatile memory; and a page jumper is provided to select at least a set of data storage pages in corresponding to a physical page of same storage cell, by jump connecting of the page jumper which jumps over another data storage page in corresponding to the physical page of the same storage cell, then the data storage page selected is accessed for at least a data storage block. the frequency of erasing of flash memory blocks can thus be reduced to elongate the life of use of the multi-level cell type non-volatile memory, this can assure integrity of the data in accessing during abnormal system power breaking.12-03-2009
20090282188MEMORY DEVICE AND CONTROL METHOD - A memory device includes a first controller and a second controller. The first controller receives a first command from a host and stores the first command in a first command queue, and transmits the first command to the second controller relating to the first command stored in the first command queue. The second controller transmits the first command stored in the second command queue to a flash memory.11-12-2009
20090282187FLASH MEMORY DEVICE CAPABLE OF PREVENTING READ DISTURBANCE - A storage has a first cache area temporarily storing one page data read from a flash memory, and a second cache area to which data of the first cache area is transferred. A controller stores data of the first cache area in the second cache area, and reads and outputs the data stored in the second cache area when data having the same address as data read from the first cache area is read.11-12-2009
20090282185FLASH MEMORY DEVICE AND A METHOD FOR USING THE SAME - A flash memory device is presented. The device includes a flash memory, which has a temporary storage portion, a main storage portion and a controller. The temporary storage portion is provided for buffering data and addresses. The buffered addresses are indicative of the destination of the buffered data in the main storage portion. The controller is configured for selectively accessing the main storage portion or the temporary storage portion or a combination thereof for receiving and/or outputting the data from the memory. The controller is further configured for enabling communication of data between the two portions. Because non-volatile flash memory is used for the temporary storage, no other memory components are needed and, in case of an unexpected power failure, the data in the temporary area is not lost.11-12-2009
20110271035EMULATED ELECTRICALLY ERASABLE (EEE) MEMORY AND METHOD OF OPERATION - A system has an emulation memory having a plurality of sectors for storing information. A controller calculates a number of addresses used divided by a number of valid records in a predetermined address range of the emulation memory. An amount of remaining addresses in a currently used space of the emulation memory which have not been used to store information is calculated. A determination is made whether the calculation is greater than a first predetermined number and whether the amount of remaining addresses is greater than a second predetermined number. If both the fraction is greater than the first predetermined number and the amount of remaining addresses is greater than the second predetermined number, any subsequent update requests are responded to using the currently used space of the emulation memory. Otherwise a compression of the emulation memory is required by copying valid data to an available sector.11-03-2011
20090287878STORAGE APPARATUS USING FLASH MEMORY - For a storage apparatus in which flash memory disks and hard disks coexist, high-density mounting of flash memory modules is achieved. A storage apparatus in accordance with the present invention includes flash memories and a storage controller. A second storage apparatus including magnetic disks is connected to the storage apparatus. For creation of a logical volume, the storage controller can form a storage area using a flash memory or a magnetic disk. When an input/output request is issued from a host computer, if a storage area is formed with a flash memory, the storage controller directly accesses the flash memory to handle the input/output request. When the storage apparatus defines a storage area formed with a flash memory, the storage apparatus defines the storage area by adding up the capacity of a storage area to be provided for the host computer and a substitute area capacity determined in consideration of restrictions imposed on the number of times of deletion of the flash memory.11-19-2009
20090287876METHOD, APPARATUS AND CONTROLLER FOR MANAGING MEMORIES - A method, an apparatus and a controller for managing memories are provided. In the present invention, a data accessing format of each of the memories is adjusted such that the accessing units for each data accessing operation are unified. A mapping table is then established for recording the adjusted data accessing format. When a data accessing command is received from a host, the mapping table is inquired so as to execute the data accessing command. Accordingly, incompatibility of hardware structures can be resolved, and management of different types of flash memory can be achieved.11-19-2009
20090157950NAND flash module replacement for DRAM module - An electronic memory module according to the invention provides non-volatile memory that can be used in place of a DRAM module without battery backup. An embodiment of the invention includes an embedded microprocessor with microcode that translates the FB-DIMM address and control signals from the system into appropriate address and control signals for NAND flash memory. Wear-leveling, bad block management, garbage collection are preferably implemented by microcode executed by the microprocessor. The microprocessor, additional logic, and embedded memory provides the functions of a flash memory controller. The microprocessor memory preferably contains address mapping tables, free page queue, and garbage collection information.06-18-2009
20090287879NAND FLASH MEMORY DEVICE AND METHOD OF MAKING SAME - An integrated circuit includes a NAND string including a string selection transistor SST and a ground selection transistor GST disposed at either end of series-connected memory storage cells MC. Each of the memory storage cells is a memory transistor having a floating gate, and at least one of the string selection transistor SST and the ground selection transistor GST is a memory transistor having a floating gate. The threshold voltage Vth of programmable string selection transistors SST and the ground selection transistor GST is variable and user controllable and need not be established by implantation during manufacture. Each of the programmable string selection transistors SST and the ground selection transistors GST in a memory block may be used to store random data, thus increasing the memory storage capacity of the flash memory device.11-19-2009
20090287875MEMORY MODULE AND METHOD FOR PERFORMING WEAR-LEVELING OF MEMORY MODULE - The invention comprises a memory module capable of wear-leveling. In one embodiment, the memory module comprises a flash memory and a controller. The flash memory comprises a plurality of management units, wherein each of the management units comprises a plurality of blocks. The controller receives new data with a logical address managed by a first management unit selected from the management units, pops a first spare block from a spare area of the first management unit, determines whether an erase count of the first spare block is greater than a first threshold value, searches a second management unit selected from the management units for a replacing block with an erase count lower than a second threshold value when the erase count of the first spare block is greater than the first threshold value, and directs the first management unit and the second management unit to exchange the first spare block with the replacing block.11-19-2009
20090287874Flash Recovery Employing Transaction Log - A transaction log for flash recovery includes a chained sequence of blocks specifying the operations that have been performed, such as a write to a sector or an erase to a block. Checkpoints are performed writing the entire flash state to flash. Once a checkpoint is performed, all of the log entries prior to the checkpoint are deleted and the log processing on recovery begins with the latest checkpoint. If the system is able to safely shutdown, then a checkpoint may be performed before the driver unloads, and on initialization, the entire persisted flash state may be loaded into the flash memory with a minimal amount of flash scanning. If a power failure occurs during system operation, then on the next boot-up, only the sectors or blocks specified in the log entries after the latest checkpoint have to be scanned, rather than all the sectors on the part.11-19-2009
20110271046WEAR LEVELING FOR LOW-WEAR AREAS OF LOW-LATENCY RANDOM READ MEMORY - Described herein are method and apparatus for performing wear leveling of erase-units of an LLRRM device that considers all active erase-units. Wear counts of all active erase-units (containing client data) and free erase-units (not containing client data) are tracked. Wear counts are used to determine low-wear active erase-units having relatively low wear counts and high-wear free erase-units having relatively high wear counts. In some embodiments, data contents of low-wear active erase-units are transferred to high-wear free erase-units, whereby the low-wear active erase-units are converted to free erase-units and may later store different client data which may increase the current rate of wear for the erase-unit. The high-wear free erase-units are converted to active erase-units that store client data that is infrequently erased/written, which may reduce the current rate of wear for the erase-unit. As such, wear is spread more evenly among erase-units of the LLRRM device.11-03-2011
20110271038INDEXED REGISTER ACCESS FOR MEMORY DEVICE - Example embodiments of a non-volatile memory device may comprise receiving an index value at one or more input terminals of a memory device and storing the index value in a first register of the memory device. The first register may be implemented in a first clock domain, and the index value may identify a second register of the memory device implemented in a second clock domain.11-03-2011
20120297123WEAR LEVELING - A method for operating a computer memory. The memory is organized to store data in units of such memory. For each unit of a set of units a wear level of the unit is determined. A maximum wear level among the wear levels is determined. A suggestion of a subset of one or more units for being selected for data erasure is received and at least one unit in the subset is identified for subsequent data erasure, a wear level (c(i)) of which units (i) is less than the maximum wear level (c_max).11-22-2012
20120297112DATA STORAGE METHODS AND APPARATUSES FOR REDUCING THE NUMBER OF WRITES TO FLASH-BASED STORAGE - Methods and apparatuses are provided for reducing the number of write operations to a flash-based storage system that stores and replaces data. The storage system includes a first storage implemented using non-flash storage and a second storage implemented using flash memory. Missed data is first stored in the first storage, which can be less sensitive than flash to write operations. The missed data is stored in the flash-based second storage only after the missed data satisfies a storage management algorithm.11-22-2012
20120297116SPARSE PROGRAMMING OF ANALOG MEMORY CELLS - A method for data storage in a memory including an array of analog memory cells, includes selecting a group of the memory cells such that each memory cell in the group has one or more neighbor memory cells in the array that are excluded from the group. Data is stored in the group of the memory cells while excluding the neighbor memory cells from programming as long as the data is stored in the group of the memory cells.11-22-2012
20120297114STORAGE CONTROL APPARATUS AND MANAGMENT METHOD FOR SEMICONDUCTOR-TYPE STORAGE DEVICE - The present invention is provided for maintaining and replacing storage devices systematically in accordance with schedule. A storage control apparatus 11-22-2012
20100115185MEMORY CONTROLLER, NONVOLATILE MEMORY DEVICE, ACCESS DEVICE, AND NONVOLATILE MEMORY SYSTEM - Without corresponding to different address spaces between an access device (05-06-2010
20110208897METHOD AND MEMORY SYSTEM USING A PRIORI PROBABILITY INFORMATION TO READ STORED DATA - A memory system comprises a non-volatile memory device that stores user data and state information regarding the user data. In a read operation of the non-volatile memory device, a memory controller calculates a priori probabilities for the user data based on the state information, calculates a posteriori probabilities based on the a priori probabilities, and performs a soft-decision operation to determine values of the user data based on the a posteriori probabilities.08-25-2011
20110208896DYNAMICALLY ALLOCATING NUMBER OF BITS PER CELL FOR MEMORY LOCATIONS OF A NON-VOLATILE MEMORY - Systems and methods are provided for dynamically allocating a number of bits per cell to memory locations of a non-volatile memory (“NVM”) device. In some embodiments, a host may determine whether to store data in the NVM device using SLC programming or MLC programming operations. The host may allocate an erased block as an SLC block or MLC block based on this determination regardless of whether the erased block was previously used as an SLC block, MLC block, or both. In some embodiments, to dynamically allocate a memory location as SLC or MLC, the host may provide an address vector to the NVM package, where the address vector may specify the memory location and the number of bits per cell to use for that memory location.08-25-2011
20110208900METHODS AND SYSTEMS UTILIZING NONVOLATILE MEMORY IN A COMPUTER SYSTEM MAIN MEMORY - Methods and systems capable of capitalizing on fast access capabilities (low initial access latencies) of nonvolatile memory technologies for use in a host system, such as computers and other processing apparatuses. The host system has a central processing unit, processor cache, and a system main memory. The system main memory includes first and second memory slots, a volatile memory subsystem having at least one DRAM-based memory module received in the first memory slot and addressed by the central processing unit, and a nonvolatile memory subsystem having at least a first nonvolatile-based memory module in the second memory slot and addressed by the central processing unit. At least one memory controller is integrated onto the central processing unit for controlling the processor cache, the volatile memory subsystem, and the nonvolatile memory subsystem.08-25-2011
20110173383METHODS OF OPERATING A MEMORY SYSTEM - Methods of operating a memory system are useful in facilitating access to data. Where repetitive data patterns are detected among portions of received data, and an indication is provided, a portion of the data may be stored and/or subsequently retrieved without having to store and/or retrieve, respectively, all portions of the data.07-14-2011
20110173381SYSTEM AND APPARATUS FOR FLASH MEMORY DATA MANAGEMENT - The system and apparatus for managing flash memory data includes a host transmitting data, wherein when the data transmitted from the host have a first time transmission trait and the address for the data indicates a temporary address, temporary data are retrieved from the temporary address to an external buffer. A writing command is then executed and the temporary data having a destination address are written to a flash memory buffer. When the flash memory buffer is not full, the buffer data are written into a temporary block of the flash memory. The writing of buffer data into the temporary block includes using an address changing command, or executing a writing command to rewrite the external buffer data to the flash memory buffer so that the data are written into the temporary block.07-14-2011
20110173382NAND INTERFACE - A NAND interface having a reduced pin count configuration, in which all command and address functions and operations of the NAND are provided serially on a single serial command and address pin.07-14-2011
20090024787Data writing method and apparatus - Provided are a data writing method and apparatus. In the data writing method, data that is to be written to a first storage medium and the address of the first storage medium are received, data is read from the address of the first storage medium, the received data is compared with the read data, and then the received data is stored in either the first storage medium or a second storage medium, depending on the comparison result. Accordingly, it is possible to reduce the time required for data writing and to increase the lifetime of a storage medium.01-22-2009
20110173380MEMORY SYSTEM AND METHOD OF CONTROLLING MEMORY SYSTEM - A first log indicating that a system is running is recorded in a second storage unit before a first difference log is recorded in the second storage unit after system startup, and a second log indicating that the system halts is recorded in the second storage unit following the difference log, at the time of normal system halt, and it is judged whether normal system halt has been performed or an incorrect power-off sequence has been performed last time, based on a recorded state of the first and second logs in the second storage unit, at the time of system startup, thereby detecting an incorrect power-off easily and reliably.07-14-2011
20110173379SEMICONDUCTOR DEVICE WITH DOUBLE PROGRAM PROHIBITION CONTROL - The present invention provides a semiconductor device and a method for controlling the semiconductor device, the semiconductor device including memory regions; program prohibition information units storing program prohibition information to be used for determining whether to prohibit or allow programming in the memory regions corresponding to the program prohibition information units; a first prohibition information control circuit that prohibits a change of the program prohibition information from a program prohibiting state with respect to a memory region based on first prohibition information; and a second prohibition information control circuit that prohibits a change of the program prohibition information from a program allowing state to a program prohibiting state with respect to the corresponding memory region based on second prohibition information with respect to the corresponding memory region.07-14-2011
20110173375METHOD FOR ENHANCING FILE SYSTEM PERFORMANCE, AND ASSOCIATED MEMORY DEVICE AND CONTROLLER THEREOF - A method for enhancing file system performance includes: in a situation where operations of visiting a file system of a memory device according to a plurality of file names are performed, regarding each of the file names, extracting a characteristic value and full file name location information from file information that is first read, and temporarily storing the characteristic value and the full file name location information; and when visiting the file system according to a target file name, checking whether any of temporarily stored characteristic values matches the target file name, and determining accordingly whether to perform a file system operation corresponding to the target file name. An associated memory device and the controller thereof are further provided.07-14-2011
20110173376CACHE APPARATUS FOR INCREASING DATA ACCESSING SPEED OF STORAGE DEVICE - A cache apparatus for increasing data accessing speed of a storage device includes: a non-volatile memory, for storing data; a memory controller, coupled to the non-volatile memory, for controlling data accessing operations of the non-volatile memory; a first transmission interface, coupled to the memory controller, for electrically connecting the memory controller to the storage device; and a second transmission interface, coupled to the memory controller, for electrically connecting the memory controller to a user-end personal computer.07-14-2011
20110173377Secure portable data storage device - A portable memory device for use with a host device includes an array of non-volatile memory and a memory controller for performing memory access operations. A processor issues an authorization challenge to a host device prior to enabling external access to the memory. Upon receipt of a valid authorization from the host device, access is enabled. In one embodiment, the processor preconditions at least one signal in the interface between the host device and the memory controller. The preconditioning results in a desynchronization of synchronized signals applied at the memory device interface, thereby interfering with proper operation of the memory device. Attempts to access the memory device prior to authorization lead to intentional corruption of data stored in the memory. In alternative embodiment, a secure, machine-readable digital storage device is implemented as a boot device for a host machine. When booted off of the secure device operating system, the host machine's access to secure files on the secure digital storage device is restricted. When the secure digital storage device is accessed by a host device not booted off of the secure device's operating system, the secured files on the secure digital storage device are inaccessible.07-14-2011
20100325348DEVICE OF FLASH MODULES ARRAY - This invention provides a device of Flash Modules Array or Flash Array (FA) for short, with a higher capacity, higher speed and lower power consumption. A device of flash array comprises: a one or more physical I/O interfaces, for performing data transmission with the outside or upstream; one or more ports for flash modules consisting of multiple flash memory modules, a flash array controller, set between the physical I/O interface and the flash modules, further including: a block mapping unit, for performing the address mapping between the logical address which is transmitted between the physical I/O interface and the outside and the physical address which is transmitted between the physical I/O interface and the flash array. The invention is applied in the field of flexible solid state storage device.12-23-2010
20120297124FLASH MEMORY DEVICE - In a flash memory device, after an updated value is copied from a first block to a second block, a block management value of the first block is set to an unused state, and maintenance is performed to erase data from the first block. When performing maintenance, the block management value of the first block B1 is rewritten from “$FFF0” to “$FFFF.” When a reset occurs and the power supply is deactivated during the maintenance, the digit of “$0” in the block management value may become “1” to “E” of the hexadecimal system. In this manner, when the block management value includes a single digit of “1” to “E” and three digits of “F,” the reading of an updated value from the block corresponding to the block management value is restricted.11-22-2012
20100146196MEMORY SYSTEM HAVING A PLURALITY OF TYPES OF MEMORY CHIPS AND A MEMORY CONTROLLER FOR CONTROLLING THE MEMORY CHIPS - A memory controller converts controller output signals output from a controller into memory input signals according to the operation specifications of memory chips to operate, and outputs the resultant to the memory chips through a common bus. The memory controller also receives memory output signals output from the memory chips through the common bus, and converts the received signals into controller input signals receivable to the controller. This allows the single memory controller to access the plurality of types of memory chips. As a result, the memory controller can be reduced in chip size, lowering the cost of the memory system.06-10-2010
20100146192METHODS FOR ADAPTIVELY PROGRAMMING FLASH MEMORY DEVICES AND FLASH MEMORY SYSTEMS INCORPORATING SAME - A method for programming a plurality of data sequences into a corresponding plurality of flash memory functional units using a programming process having at least one selectable programming duration-controlling parameter controlling the duration of the programming process for a given data sequence, the method comprising providing at least one indication of at least one varying situational characteristic and determining a value for said at least one selectable programming duration-controlling parameter controlling the duration of the programming process for a given data sequence, for each flash memory functional unit, depending at least partly on said indication of said varying characteristic; and, for each individual flash memory functional unit from among said plurality of flash memory functional units, programming a sequence of bits into said individual flash memory functional unit using a programming process having at least one selectable parameter, said at least one selectable parameter being set at said value determined for said individual flash memory functional unit.06-10-2010
20100146197Non-Volatile Memory And Method With Memory Allocation For A Directly Mapped File Storage System - In a memory system with a file storage system, a scheme for allocating memory locations for a write operation is to write the files substantially contiguously in a memory block one after another rather than to start a new file in a new block. In this way, they are more efficiently packed into the blocks by being written contiguously one after another. In a preferred embodiment, an incrementing write pointer points to the write location in memory for the next data for a file, which is independent of the offset address of the data within the file. When a current write block becomes filled with file data, an erased block is allocated, and the write pointer is moved to this block. Similarly a relocation pointer is used for data relocation during garbage collection or data compaction operations.06-10-2010
20100138593MEMORY CONTROLLER, SEMICONDUCTOR RECORDING DEVICE, AND METHOD FOR NOTIFYING THE NUMBER OF TIMES OF REWRITING - User data transferred from a host apparatus and a first information table 06-03-2010
20100138590CONTROL APPARATUS FOR CONTROLLING PERIPHERAL DEVICE, NON-VOLATILE STORAGE ELEMENT, AND METHOD THEREOF - A control apparatus for controlling at least one peripheral device includes a non-volatile storage element and a controller. The non-volatile storage element is used for storing at least one control information set. The controller is externally coupled to the non-volatile storage element and includes a read-only storage element which stores a segment of program code. The controller loads the segment of program code to execute the segment of program code for reading at least one portion of the control information set from the non-volatile storage element to control the operation of the peripheral device.06-03-2010
20100138588MEMORY CONTROLLER AND A METHOD OF OPERATING AN ELECTRICALLY ALTERABLE NON-VOLATILE MEMORY DEVICE - A controller operates a NAND non-volatile memory device which has an array of non-volatile memory cells. The array of non-volatile memory cells is susceptible to suffering loss of data stored in one or more memory cells of the array. The controller interfaces with a host device and receives from the host device a time-stamp signal. The controller comprises a processor, and a memory having program code stored therein for execution by the processor. The program code is configured to receive by the controller the time stamp signal from the host device; to compare the received time stamp signal with a stored signal wherein the stored signal is a time stamp signal received earlier in time by the controller from the host device; and to determine when to perform a data retention and refresh operation for data stored in the memory array based upon the comparing step.06-03-2010
20110271034MULTIPLE PARTITIONED EMULATED ELECTRICALLY ERASABLE (EEE) MEMORY AND METHOD OF OPERATION - A method and system wherein a volatile memory is partitioned to have a first percentage of address space dedicated to a first classification of data which is data that is expected to have greater than a predetermined number of times of being modified and a second percentage of address space dedicated to a second classification of data which is data that is expected to have less than the predetermined probability of being modified. Address assignment of data to be stored in the volatile memory is made on a basis of predicted change of the data. Memory addresses of the first and second percentages of address space are respectively assigned to first and second sections of nonvolatile memory. The memory addresses of the first percentage initially consume a smaller percentage of an address map of the first section than the memory addresses of the second percentage of the second section.11-03-2011
20080244162METHOD FOR READING NON-VOLATILE STORAGE USING PRE-CONDITIONING WAVEFORMS AND MODIFIED RELIABILITY METRICS - Data stored in non-volatile storage is read using sense operations and associated pre-conditioning waveforms. The pre-conditioning waveform provides a short term history for a non-volatile element which is analogous to the conditions experienced during programming when a programming pulse is applied prior to a verify operation. The pre-conditioning waveform can cause electrons to enter and exit trap sites, for instance, so that the accuracy of a probabilistic decoding process is improved. In one approach, multiple read operations are performed, some with pre-conditioning waveforms and some without. Pre-conditioning waveforms with different characteristics, such as amplitude, shape, duration and time before the associated read pulse, can also be used. For probabilistic decoding, initial reliability metrics can be developed based on multiple reads. Tables which store the reliability metrics can then be prepared for use in subsequent decoding.10-02-2008
20080244166System and method for configuration and management of flash memory - A system and a method for configuration and management of flash memory is provided, including a flash memory, a virtual memory region, and a memory logical block region. The flash memory includes a plurality of physical erase units. Each physical erase unit is configured to include at least a consecutive segment, and each segment is configured to include at least a consecutive frame. Each frame is configured to include at least a consecutive page. Each virtual memory region is configured to include a plurality of areas, and each area is configured to include at least a virtual erase unit. The memory logical block region is configured to include a plurality of clusters, and each cluster includes at least a consecutive memory logical block. By forming correspondence among the physical erase unit, segment, frame, page, virtual erase unit, area, memory logical block and cluster to control the data access to the flash memory, the present invention achieves the reconfiguration and management of memory consumption and access efficiency for the flash memory.10-02-2008
20080250195Multi-Operation Write Aggregator Using a Page Buffer and a Scratch Flash Block in Each of Multiple Channels of a Large Array of Flash Memory to Reduce Block Wear - A flash system has multiple channels of flash memory chips that can be accessed in parallel. Host data is assigned to one of the channels by a multi-channel controller processor and accumulated in a multi-channel page buffer. When a page boundary in the page buffer is reached, the page buffer is written to a target physical block if full, or combined with old data fragments in an Aggregating Flash Block (AFB) when the logical-sector addresses (LSA's) match. Thus small fragments are aggregated using the AFB, reducing erases and wear of flash blocks. The page buffer is copied to the AFB when a STOP command occurs. Each channel has one or more AFB's, which are tracked by an AFB tracking table.10-09-2008
20080250191FLEXIBLE, LOW COST APPARATUS AND METHOD TO INTRODUCE AND CHECK ALGORITHM MODIFICATIONS IN A NON-VOLATILE MEMORY - A flash memory includes input/output buffers, a memory array having memory cells coupled to the input/output buffers, and row and column decoders, and a voltage-generator circuit coupled to the row and column decoders. A microcontroller is coupled to the command user interface. Switch-instruction circuitry selectively provides instructions to the microcontroller from the read-only memory and from off chip through on-board t-latches coupled to the input/output buffers under control of a command user interface.10-09-2008
20080276038Storage system using flash memory modules logically grouped for wear-leveling and raid - A storage system using flash memories includes a storage controller and plural flash memory modules as storage media. Each flash memory module includes at least one flash memory chip and a memory controller for leveling erase counts of blocks belonging to the flash memory chip. The storage controller combines the plural flash memory modules into a first logical group, translates a first address used for accessing the flash memory modules belonging to the first logical group to a second address used for handling the first address in the storage controller, and combines the plural first logical groups into a second logical group.11-06-2008
20080276037Method to Access Storage Device Through Universal Serial Bus - A method accessing a flash memory storage device through universal serial bus (USB) of the present invention includes a flash controller and a flash memory, wherein the method includes connecting the storage device to a USB interface of an electronic device; outputting a plurality of accessing instructions to the flash controller via the electronic device; deciding which data is needed to be temporarily saved in a cache memory and a priority of the accessing instructions according to the characteristic of the file system and the content of preceding instructions of the flash controller; and writing the data temporarily saved in the cache memory into the flash memory according to the priority of the flash controller. The objective of the method of the present invention is to enhance the operation efficiency of the storage device.11-06-2008
20110208905Non-Volatile Memory Device For Concurrent And Pipelined Memory Operations - This disclosure provides a non-volatile memory device that concurrently processes multiple page reads, erases or writes involving the same memory space. The device relies upon a crossbar and a set of page buffers that may each be dynamically assigned to each read or write request. The device also separates memory array control from IO control, such that multiple cycle state change operations can be performed while the buffers are used to transfer data into and out of the buffers along an external data bus; using this structure, the memory device can accept multiple transactions where pages can be immediately loaded into buffers and then “pipelined” either for transfer to a write data register or to an external bus as appropriate. By significantly mitigating the substantial “busy time” associated with program and erase of non-volatile memory devices, especially flash devices, this disclosure greatly expands potential application of such devices.08-25-2011
20110208899MEMORY WRITING SYSTEM AND METHOD - Memory writing system and method determining an optimum data amount per one-time data transmission to one memory writer to enable optimization of communication efficiency and write speed, include: setting the amount of data to be transmitted per one-time transmission from a writer controller to different values for respective memory writers; transmitting data of each of the data amounts from the writer controller to a corresponding one of the memory writers; measuring, for each of the data amounts, a processing time required for the writer controller to transmit data to the corresponding memory writer and a data write time of the corresponding memory writer; obtaining, for each of the data amounts, a correlation between the processing time and the data write time based on respective measured values; setting an optimum data amount based on the correlation to satisfy a desired data write time condition; and, after the optimum data amount is set, sequentially transmitting data of the optimum data amount from the writer controller to the memory writers.08-25-2011
20110208898STORAGE DEVICE, COMPUTING SYSTEM, AND DATA MANAGEMENT METHOD - A data storage device receives an invalidity command, and in response to the invalidity command, records information identifying a first region of a main storage unit. In a first interval, the data storage device copies valid data from the first region of the main storage unit to a second region of the main storage unit based on the recorded information. In a second interval after the first interval, the data storage device invalidates the first region.08-25-2011
20130219112MANAGING MEMORY SYSTEMS CONTAINING COMPONENTS WITH ASYMMETRIC CHARACTERISTICS - A memory controller (MC) is associated with a remapping table to enable access to content in a memory system that includes asymmetric memory. The MC receives a request for a memory read or an Input/Output (I/O) write from a central processing unit (CPU) for a physical address specified by the system's memory management unit (MMU). The CPU uses the MMU to manage memory operations for the CPU, by translating the virtual addresses associated with CPU instructions into physical addresses representing system memory or I/O locations. The MC for asymmetric memories is configured to process the MMU-specified physical addresses as an additional type of virtual addresses, creating a layer of abstraction between the physical address specified by the MMU and the physical memory address with which that address is associated by the MC. The MC shields the CPU from the computational complexities required to implement a memory system with asymmetric components.08-22-2013
20130219108Method, Memory Controller and System for Reading Data Stored in Flash Memory - An exemplary method for reading data stored in a flash memory. The method includes: controlling the flash memory to perform a read operation upon a first page of the flash memory; obtaining a first codeword of the first page; obtaining a first set of log-likelihood ratio (LLR) mapping values of the first codeword according to a first LLR mapping rule; performing an error correction operation according to the first set of LLR mapping values; obtaining a second set of LLR values of the first codeword according to a second LLR mapping rule, if the error correction operation performed according to the first set of LLR mapping values indicates an uncorrectable result; and performing the error correction operation according to the second set of LLR mapping values.08-22-2013
20090100218HARD DISK DRIVE WITH REDUCED POWER CONSUMPTION, RELATED DATA PROCESSING APPARATUS, AND I/O METHOD - A hard disk drive is disclosed and related methods of reading/writing data are disclosed. The hard disk drive includes a disk serving as a main data storage medium, and first and second buffers storing data to be stored on the disk, as well as a controller defining a data I/O path in relation to a detected operating state of the hard disk drive.04-16-2009
20090037648INPUT/OUTPUT CONTROL METHOD AND APPARATUS OPTIMIZED FOR FLASH MEMORY - An input/output control method and apparatus optimized for a flash memory, which can improve the performance of the flash memory. The input/output control method optimized for a flash memory includes determining whether a random write operation of data occurs in a flash memory, and successively writing randomly input data in a predetermined surplus region of the flash memory if it is judged that the random write operation occurs.02-05-2009
20090037644System and Method of Storing Reliability Data - Systems and methods of storing error correction data are provided. A method may include storing data at a first memory having a first non-volatile memory type. The method may also include determining error correction data related to the stored data. The method may further include storing the error correction data at a second memory having a second non-volatile memory type. The first non-volatile memory may have a slower random access capability than the second non-volatile memory.02-05-2009
20090265507SYSTEM TO REDUCE DRIVE OVERHEAD USING A MIRRORED CACHE VOLUME IN A STORAGE ARRAY - A system comprising a host, a solid state device, and an abstract layer. The host may be configured to generate a plurality of input/output (IO) requests. The solid state device may comprise a write cache region and a read cache region. The read cache region may be a mirror of the write cache region. The abstract layer may be configured to (i) receive the plurality of IO requests, (ii) process the IO requests, and (iii) map the plurality of IO requests to the write cache region and the read cache region.10-22-2009
20090265506STORAGE DEVICE - A computing system and a storage device are provided. A computing system includes a first storage media, a second storage media having an input/output speed slower than that of the first storage media, and a hybrid file system management unit to manage a first physical file system and second physical file system, and provide a virtual file system manager with a virtual file system converted from the first physical file system and second physical file system. The first physical file system controls the first storage media and the second physical file system controls the second storage media.10-22-2009
20080282024Management of erase operations in storage devices based on flash memories - A method of freeing physical memory space in an electrically alterable memory that includes a plurality of physical memory blocks includes a plurality of physical memory pages. Each physical memory block may be individually erased as a whole, and which memory is used to emulate a random access logical memory space including a plurality of logical memory sectors by storing updated versions of a logical memory sector data into different physical memory pages. The method includes causing a most recent version of multiple versions of logical memory sector data, stored in physical pages of at least one physical memory block, to be copied into an unused physical memory block, marking the at least one physical memory block, and when the electrically alterable memory is idle, erasing the marked physical memory block.11-13-2008
20080282023Restoring storage devices based on flash memories and related circuit, system, and method - A solution for restoring operation of a storage device based on a flash memory is proposed. The storage device emulates a logical memory space (including a plurality of logical blocks each one having a plurality of logical sectors), which is mapped on a physical memory space of the flash memory (including a plurality of physical blocks each one having a plurality of physical sectors for storing different versions of the logical sectors). A corresponding method starts by detecting a plurality of conflicting physical blocks for a corrupted logical block (resulting from a breakdown of the storage device). The method continues by determining a plurality of validity indexes (indicative of the number of last versions of the logical sectors of the corrupted logical block that are stored in the conflicting physical blocks). One ore more of the conflicting physical blocks are selected according to the validity indexes. The selected conflicting physical blocks are then associated with the corrupted logical block. At the end, each one of the non-selected conflicting physical blocks is discarded.11-13-2008
20080282025Wear leveling in storage devices based on flash memories and related circuit, system, and method - A wear leveling solution is proposed for use in a storage device based on a flash memory. The flash memory includes a plurality of physical blocks, which are adapted to be erased individually. A corresponding method starts with the step for erasing one of the physical blocks. One of the physical blocks being allocated for storing data is selected; this operation is performed in response to the reaching of a threshold by an indication of a difference between a number of erasures of the erased physical block and a number of erasures of the selected physical block. At least the data of the selected physical block being valid is copied into the erased physical block. The selected physical block is then erased.11-13-2008
20080288717SINGLE SECTOR WRITE OPERATION IN FLASH MEMORY - A flash storage device having improved write performance is provided. The device includes a storage block having a plurality of physical pages and a controller for mapping the plurality of physical pages to a plurality of logical addresses and for writing data to the plurality of physical pages. When updating data previously written to one of the plurality of logical addresses, the controller is configured to write the updated data to a second physical page which is mapped to the logical address. Each of the logical addresses may be associated with a pointer field, which is for storing a pointer value indicating the invalidity of a physical page and/or the location of another physical page.11-20-2008
20080288712ACCESSING METADATA WITH AN EXTERNAL HOST - Systems and processes may be used to retrieve metadata from a nonvolatile memory of a portable device and transmit the retrieved metadata to an external host. Metadata may be analyzed using the external host and/or at least a portion of the metadata may be modified based on the analysis. Modified metadata may be transmitted from the external host to a memory controller of the host.11-20-2008
20080288714FILE STORAGE IN A COMPUTER SYSTEM WITH DIVERSE STORAGE MEDIA - A method for storing data in a computer having a magnetic hard disk drive (HDD) and an electronic solid-state drive (SSD). The method includes configuring the computer so that the HDD and the SSD are each independently accessible by an operating system of the computer. A plurality of files is received for storage by the computer. A predicted use profile of the computer is defined. A respective one of the HDD and the SDD is selected for the storage of each of the files responsively to the predicted use profile.11-20-2008
20080288713FLASH-AWARE STORAGE OPTIMIZED FOR MOBILE AND EMBEDDED DBMS ON NAND FLASH MEMORY - Reliable storage for database management systems (DBMS) running on memory devices such as NAND type flash memory utilizes minimum I/O overhead and provides maximum data durability. A virtual page map is utilized between the flash memory and a page access component to record changes to the DBMS pages and prevent overwriting or data loss. There is no need for journaling and logging, and performance is increased by reducing the write and erase counts on the flash memory. The logical page numbers of the DBMS are mapped to physical page numbers in the page map, such that the virtual page map allocates an available page from the physical pages when changes to a page occur, and the updated information is stored in the allocated page. The allocated page number is mapped to the logical page number of the original page, thus maintaining a modified page representation while preventing physical in-place updates.11-20-2008
20120297113OPTIMIZED FLASH BASED CACHE MEMORY - Embodiments of the invention relate to throttling accesses to a flash memory device. The flash memory device is part of a storage system that includes the flash memory device and a second memory device. The throttling is performed by logic that is external to the flash memory device and includes calculating a throttling factor responsive to an estimated remaining lifespan of the flash memory device. It is determined whether the throttling factor exceeds a threshold. Data is written to the flash memory device in response to determining that the throttling factor does not exceed the threshold. Data is written to the second memory device in response to determining that the throttling factor exceeds the threshold.11-22-2012
20080313387SEMICONDUCTOR MEMORY DEVICE CAPABLE OF READING DATA RELIABLY - A control unit reads data from a plurality of memory cells connected to one of the word lines in a read operation at a first level CR generated by a voltage generator circuit and in a read operation at a second level CR−x and finds the number of cells included between the first level and the second level from the data and, if the number is equal to or smaller than a specified value, determines the result of the read operation at the first level to be read data.12-18-2008
20080313391SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR DEVICE - A semiconductor memory device, including: a cell array block including a plurality of memory cells arranged therein; and a controller, wherein the controller controls the semiconductor memory device so that: an operation of reading out data from a second region in the cell array block is initiated before completion of an operation of outputting data read out from a first region in the cell array block; and the data read out from the second region is output successively after the completion of the operation of outputting data read out from the first region.12-18-2008
20080313389ELECTRONIC DATA FLASH CARD WITH VARIOUS FLASH MEMORY CELLS - An electronic data flash card is accessible by a host computer, and includes a processing unit connected to a flash memory device that stores a data file, and an input-output interface circuit activated so as to establish a communication with the host computer. In an embodiment, the electronic data flash card uses a USB input/output interface circuit for communication with the host computer. A flash memory controller includes an index for converting logical addresses sent by the host computer into physical addresses associated with sectors of the flash memory device. The index is controlled by arbitration logic referencing to values from various look up tables and valid data stored in the flash memory device. The flash memory controller further includes a first-in-first-out unit (FIFO) for recycling obsolete sectors of the flash memory device in the background process so that they are available for reprogramming.12-18-2008
20080313388ELECTRONIC DATA FLASH CARD WITH VARIOUS FLASH MEMORY CELLS - An electronic data flash card is accessible by a host computer, and includes a processing unit connected to a flash memory device that stores a data file, and an input-output interface circuit activated so as to establish a communication with the host computer. In an embodiment, the electronic data flash card uses a USB input/output interface circuit for communication with the host computer. A flash memory controller includes an index for converting logical addresses sent by the host computer into physical addresses associated with sectors of the flash memory device. The index is controlled by arbitration logic referencing to values from various look up tables and valid data stored in the flash memory device. The flash memory controller further includes a first-in-first-out unit (FIFO) for recycling obsolete sectors of the flash memory device in the background process so that they are available for reprogramming.12-18-2008
20090193183NONVOLATILE MEMORY SYSTEM, AND DATA READ/WRITE METHOD FOR NONVOLATILE MEMORY SYSTEM - A nonvolatile memory system comprises a nonvolatile memory having a plurality of data areas; and a memory controller operative to control read and write operations to the nonvolatile memory. The memory controller successively executes read/write operations to plural sectors within a selected data area in the nonvolatile memory in accordance with a command and a sector count and sector address fed from a host device.07-30-2009
20080235443Intelligent Solid-State Non-Volatile Memory Device (NVMD) System With Multi-Level Caching of Multiple Channels - A flash memory system stores blocks of data in Non-Volatile Memory Devices (NVMD) that are addressed by a logical block address (LBA). The LBA is remapped for wear-leveling and bad-block relocation by the NVMD. The NVMD are interleaved in channels that are accessed by a NVMD controller. The NVMD controller has a controller cache that caches blocks stored in NVMD in that channel, while the NVMD also contain high-speed cache. The multiple levels of caching reduce access latency. Power is managed in multiple levels by a power controller in the NVMD controller that sets power policies for power managers inside the NVMD. Multiple NVMD controllers in the flash system may each controller many channels of NVMD. The flash system with NVMD may include a fingerprint reader for security.09-25-2008
20080235441Reducing power dissipation for solid state disks - A data processing device including a computer, the computer including a solid state disk (SSD), including a primary memory for single level cell storage, and a secondary memory for multi-level cell storage, a limited internal battery for supplying power to the computer, a socket for connecting the computer to an external power supply source, a detector for indicating that the computer is connected to an external power source, a processor for transferring data from the primary memory to the secondary memory, and an SSD controller for deciding whether or not the processor may transfer data from the primary memory to the secondary memory, based on a signal received from said detector. A method for SSD memory management is also described and claimed.09-25-2008
20080235442FLASH MEMORY DEVICE CAPABLE OF IMPROVING READ PERFORMANCE - A flash memory device, related system ad method are disclosed. The memory device includes a memory cell array a page buffer receiving read data, wherein the page buffer includes a main register transferring read data to a cache register during an read operation, and a control logic block controlling operation of the page buffer during the read operation, such that initialization of the main register continuously extends beyond a time period during which read data is transferred from the main register to the cache register.09-25-2008
20080235440Memory device - A memory device includes a housing, a memory within the housing, and a first electrical interface accessible on a top surface of the housing and a second electrical interface accessible on a bottom surface of the housing. As such, at least one of the first electrical interface and the second electrical interface is configured to establish electrical connection of the memory device with an electrical interface of another memory device when the memory device and the another memory device are in a stacked configuration.09-25-2008
20080235439Methods for conversion of update blocks based on association with host file management data structures - A method for operating a memory system is provided. In this method, a sequential update block is provided and a write command is received to write data. The write command comprises a logical address associated with the data. If the logical address is associated with a host file management data structure, then the sequential update block is converted to a chaotic update block. After the conversion, the data are written to the chaotic update block.09-25-2008
20080235438System and method for effectively implementing a multiple-channel memory architecture - A system and method for implementing a multiple-channel memory architecture includes a plurality of memory channels that are configured in a parallel manner to store electronic data. In certain embodiments, the memory channels are implemented to include non-volatile flash memory devices. A transfer controller communicates with the memory channels to control concurrent data transfer operations for transferring the electronic data in and out of the memory channels. The transfer controller generates individual channel clock signals to the respective memory channels for triggering corresponding data transfer operations which occur in an overlapping temporal sequence.09-25-2008
20080235437Methods for forcing an update block to remain sequential - A method for operating a memory system is provided. In this method, a sequential update block and preexisting data associated with the sequential update block are provided. Here, an option to convert the sequential update block to a chaotic update block also is provided. A write command is received to write data following a previous write command, where the write command and the previous write command have a discontinuity in logical addresses. If a logical address of the write command is different from logical addresses of the preexisting data, then the data are written to the sequential update block. If the logical address of the write command matches one of the logical addresses of the preexisting data, then the sequential update block is converted to a chaotic update block.09-25-2008
20080235436STORAGE ACCESS CONTROL - A system and device are disclosed. In one embodiment, the system includes a processor, system memory, chipset, flash memory, and flash memory controller. The flash memory controller includes a base address register for a flash memory hidden protected area (HPA) to store a flash memory HPA base address, a size register for a flash memory HPA to store a size of the flash memory HPA, and control logic to allocate a portion of the flash memory as a flash memory HPA using the flash memory HPA base address and the flash memory HPA size address.09-25-2008
20080235435USE OF A SHUTDOWN OBJECT TO IMPROVE INITIALIZATION PERFORMANCE - According to some embodiments, use of a shutdown object during system initialization is disclosed. The shutdown object may be read from a non-volatile memory device and loaded into a random access memory. A plurality of headers may then be scanned from the non-volatile memory device. The shutdown object may be referenced to determine whether each of the plurality of headers includes valid data. Each of the plurality of headers that includes valid data may be represented in the random access memory.09-25-2008
20120297121Non-Volatile Memory and Method with Small Logical Groups Distributed Among Active SLC and MLC Memory Partitions - A non-volatile memory organized into flash erasable blocks receives data from host writes by first staging into logical groups before writing into the blocks. Each logical group contains data from a predefined set of order logical addresses and has a fixed size smaller than a block. The totality of logical groups are obtained by partitioning a logical address space of the host into non-overlapping sub-ranges of ordered logical addresses, each logical group having a predetermined size within a range delimited by a minimum size of at least one page and a maximum size of fitting at least two logical groups in a block and up to an order of magnitude higher than a typical size of a host write. In this way, excessive garbage collection due to operating a large logical group is avoided while the address space is reduced to minimize the size of a caching RAM.11-22-2012
20120297120STACK PROCESSOR USING A FERROELECTRIC RANDOM ACCESS MEMORY (F-RAM) FOR CODE SPACE AND A PORTION OF THE STACK MEMORY SPACE HAVING AN INSTRUCTION SET OPTIMIZED TO MINIMIZE PROCESSOR STACK ACCESSES - A stack processor and method implemented using a ferroelectric random access memory (F-RAM) for code and a portion of the stack memory space having an instruction set optimized to minimize processor stack accesses and thus minimize program execution time. This is particularly advantageous in low power applications and those in which the power supply is only available for a finite period of time such as RFID implementations. Disclosed herein is a relatively small but complete set of instructions enabling a multitude of possible applications to be supported with a program execution time that is not too long.11-22-2012
20120297118FAST TRANSLATION INDICATOR TO REDUCE SECONDARY ADDRESS TABLE CHECKS IN A MEMORY DEVICE - A system and method for reducing the need to check both a secondary address table and a primary address table for logical to physical translation tasks is disclosed. The method may include generating a fast translation indicator, such as a logical group bitmap, indicating whether there is an entry in the secondary address table that contains desired information pertaining to a particular logical address. Upon a host request relating to the particular logical address, the storage device may check the bitmap to determine if retrieval and parsing of the secondary table is necessary. The system may include a storage device having RAM cache storage, flash storage and a controller configured to generate and maintain at least one fast translation indicator to reduce the need to check both secondary and primary address tables during logical to physical address translation operations of the storage device.11-22-2012
20120297115PROGRAM CODE LOADING AND ACCESSING METHOD, MEMORY CONTROLLER, AND MEMORY STORAGE APPARATUS - A method of loading a program code from a rewritable non-volatile memory module is provided, wherein the program code includes data segments and two program code copies corresponding to the program code are stored in the rewritable non-volatile memory module. The method includes loading a first data segment of a first program code copy and determining whether the first data segment contains any uncorrectable error bit. The method still includes, when the first data segment does not contain any uncorrectable error bit, loading a second data segment of the first program code copy. The method further includes, when the first data segment contains an uncorrectable error bit, loading a first data segment of a second program code copy, and then loading a second data segment of the first program code copy or the second program code copy. Thereby, the program code can be successfully loaded.11-22-2012
20080282026Bioprocess data management - A data management system for a biological process, comprising: 11-13-2008
20080201519MEMORY CARD - A memory card is structured to support a variety of applications by dividing a storage region into a plurality of sub storage regions, each sub storage region being assigned a particular data format associated with each of a plurality of application programs stored in a controller of the memory card. The data stored in each of the sub storage regions co-exists compatibly in the memory card. This allows for a multiplicity of applications, which can be made available through the use of a single memory card.08-21-2008
20090313425MEMORY CONTROL APPARATUS, CONTENT PLAYBACK APPARATUS, CONTROL METHOD AND RECORDING MEDIUM - A data storage apparatus is provided that realizes a measure against deterioration of a flash memory in which integrity check data is stored. A content playback apparatus (12-17-2009
20090313420Method for saving an address map in a memory device - A method for saving an address map in a memory device is provided. In one embodiment, a logical-to-physical address map is stored in a volatile memory of a memory device. The memory device receives a command from a host device to perform an operation that is associated with a power-down sequence of the host device, such as a flush cache command. In response to receiving the command, the memory device performs the operation and saves the logical-to-physical address map in a non-volatile memory of the memory device. In this way, the command triggers both the performance of the operation and the saving of the logical-to-physical address map in the non-volatile memory of the memory device.12-17-2009
20090313419METHOD OF STORING DATA ON A FLASH MEMORY DEVICE - Methods and apparatus are disclosed, such as those involving a flash memory device. One such method includes storing data on memory cells on a memory block including a plurality of word lines and a plurality of memory cells on the word lines. The word lines comprising one or more bottom edge word lines, one or more top edge word lines, and intermediate word lines between the bottom and top edge word lines. The data is stored first on memory cells on the intermediate word lines. Then, a remaining portion, if any, of the data is stored on memory cells on the bottom edge word lines and/or the top edge word lines. This method enhances the life of the flash memory by preventing a premature failure of memory cells on the bottom or top edge word lines, which can be more prone to failure.12-17-2009
20090313417Methods for Data Management in a Flash Memory Medium - A method for data management in a flash memory medium is provided in the present invention, The method comprises the following steps: dividing a plurality of blocks of the flash memory medium into two or more sections; generating a section-address-mapping table by scanning logic addresses in the blocks in each section; storing the section-address-mapping table into a backup block in each section; and performing an operation of writing/reading by reading the section-address-mapping table, storing the section-address-mapping table to a RAM, and performing a conversion between a physical address and a logic address based on the section-address-mapping table stored in the RAM. Since the section-address-mapping tables are stored in the backup block in respective sections, when an operation of writing/reading is performed and it is necessary to switch to a section-address-mapping table for a next section, data stored in the next section can be read out based on the section-address-mapping table stored in the backup block in the next section, without needing to scan each block in the next section for generating a new section-address-mapping table dynamically. Therefore, the method of the present invention can save the time for operation and thus achieve effective management on data in the flash memory medium.12-17-2009
20090313423MULTI-BIT FLASH MEMORY DEVICE AND METHOD OF ANALYZING FLAG CELLS OF THE SAME - Disclosed is a multi-bit flash memory device which includes a memory cell array and a control circuit. The memory cell array has multiple memory cells and multiple flag cells. The control circuit determines whether the flag cells are programmed, based on a reference corresponding to a read margin of the flag cells, and controls a program operation of the memory cells in response to the determination.12-17-2009
20080229000FLASH MEMORY DEVICE AND MEMORY SYSTEM - A memory system comprises a flash memory, a processing unit, and a flash controller including address and control registers, the address and control registers being configured to receive information from the processing unit, wherein the flash controller is configured to control a copy-back program operation of the flash memory in hardware based on information stored in the address and control registers.09-18-2008
20120297128REDUCING ACCESS CONTENTION IN FLASH-BASED MEMORY SYSTEMS - Exemplary embodiments include a method for reducing access contention in a flash-based memory system, the method including selecting a chip stripe in a free state, from a memory device having a plurality of channels and a plurality of memory blocks, wherein the chip stripe includes a plurality of pages, setting the ship stripe to a write state, setting a write queue head in each of the plurality of channels, for each of the plurality of channels in the flash stripe, setting a write queue head to a first free page in a chip belonging to the channel from the chip stripe, allocating write requests according to a write allocation scheduler among the channels, generating a page write and in response to the page write, incrementing the write queue head, and setting the chip stripe into an on-line state when it is full.11-22-2012
20120297126INFORMATION PROCESSING APPARTUS, NON-TRANSITORY COMPUTER-READABLE MEDIUM STORING CONTROL PROGRAM AND CONTROL METHOD - An information processing apparatus includes a calculator configured to perform a calculation, a plurality of system boards, each of the plurality of system boards including a first storage unit that stores a first program of a first type, the first program being to be used to operate the calculator, a preliminary board including a plurality of second storage units, at least one of the plurality of second storage units storing a second program of a second type, the second program corresponding to the first programs, and a controller configured to compare any one of the first types of the first programs with the second type of the second program and to write, when any one of the first types does not match the second type, the first program of the any one of the first types into the second storage unit.11-22-2012
20120297125SOLID-STATE DEVICE WITH LOAD ISOLATION - Systems and methods are provided for coupling multiple flash devices to a shared bus utilizing isolation switches within a SSD device. The SSD device is operable at a speed of about 400 MT/s or higher with high signal integrity. The SSD device includes a controller, a channel in electrical communication with the controller, a plurality of isolation devices in electrical communication with channel, and a plurality of flash memory devices, wherein each flash memory device is in electrical communication with the channel and controller through the one of the isolation devices.11-22-2012
20120297122Non-Volatile Memory and Method Having Block Management with Hot/Cold Data Sorting - A non-volatile memory organized into flash erasable blocks sorts units of data according to a temperature assigned to each unit of data, where a higher temperature indicates a higher probability that the unit of data will suffer subsequent rewrites due to garbage collection operations. The units of data either come from a host write or from a relocation operation. The data are sorted either for storing into different storage portions, such as SLC and MLC, or into different operating streams, depending on their temperatures. This allows data of similar temperature to be dealt with in a manner appropriate for its temperature in order to minimize rewrites. Examples of a unit of data include a logical group and a block.11-22-2012
20080209112High Endurance Non-Volatile Memory Devices - High endurance non-volatile memory devices (NVMD) are described. A high endurance NVMD includes an I/O interface, a NVM controller, a CPU along with a volatile memory subsystem and at least one non-volatile memory (NVM) module. The volatile memory cache subsystem is configured as a data cache subsystem. The at least one NVM module is configured as a data storage when the NVMD is adapted to a host computer system. The I/O interface is configured to receive incoming data from the host to the data cache subsystem and to send request data from the data cache subsystem to the host. The at least one NVM module may comprise at least first and second types of NVM. The first type comprises SLC flash memory while the second type MLC flash. The first type of NVM is configured as a buffer between the data cache subsystem and the second type of NVM.08-28-2008
20080209107Apparatus, method, and system of NAND defect management - Various embodiments comprise apparatus, methods, and systems that include an apparatus comprising a memory device configurable as a plurality of erase block groups including a base erase block group, wherein each of the plurality of erase block groups comprises a plurality of erase blocks each identified by a matching unique plurality of erase block numbers unique within the plurality of erase blocks and matching across the plurality of erase block groups; and a mapping table coupled to the plurality of erase block groups to store at least one group address number corresponding to one of the matching unique plurality of erase block numbers identifying a non-defective erase block in the base erase block group, and corresponding to several of the matching unique plurality of erase block numbers identifying a single non-defective erase block in each of the plurality of erase block groups other than the base erase block group.08-28-2008
20080276036Memory with Block-Erasable Location - A non-volatile main memory (11-06-2008
20100138589STORAGE OPTIMIZATIONS BY DIRECTORY COMPACTION IN A FAT FILE SYSTEM - Storage optimizations by directory compaction in a file allocation table (FAT) file system. The method comprises determining if a cluster comprises a deleted content, indicating that the deleted content is deleted, and updating an entry of a FAT associated with the cluster to indicate that the cluster is free. The method may also comprise indicating that the deleted content is deleted and modifying a metadata of at least one of a file of the cluster and a directory of the cluster according to a specified protocol.06-03-2010
20080288715Memory Page Size Auto Detection - Methods and apparatuses are presented for memory page size auto detection. A method for automatically determining a page size of a memory device includes receiving page size extents of the memory device, determining a bus width of the memory device, detecting a number of pages having an automatic detection marker, and determining the page size of the memory device based upon the detected number of pages and the received page size extents. An apparatus for automatically determining page size detection includes logic for performing the above presented method.11-20-2008
20120144100MEMORY SYSTEM AND METHOD OF WRITING INTO NONVOLATILE SEMICONDUCTOR MEMORY - A memory system includes a nonvolatile semiconductor memory which includes a first original block composed of n (n being natural number) write unit areas and a first subblock composed of a plurality of write unit areas. A controller writes data having one of first to p-th (p being natural number smaller than n) addresses into the first original block. The controller writes data which has a first write address of one of the first to p-th addresses into the first subblock when the controller receives request to write data having the first write address and data having the first write address exists in the first original block.06-07-2012
20120144096MASS STORAGE SYSTEMS AND METHODS USING SOLID-STATE STORAGE MEDIA - A mass storage system comprising multiple memory cards, each with non-volatile memory components, a system bus interface for communicating with a system bus of a host system, and at least one ancillary interface. The ancillary interface is configured for direct communication of commands, addresses and data between the memory cards via a cross-link connector without accessing the system bus interface.06-07-2012
20100146195Defragmentation Method For A Machine-Readable Storage Device - A defragmentation method includes the steps of: a) configuring a processor to determine a type of a target machine-readable storage device coupled electrically to the processor; b) configuring the processor to select, from among a plurality of pre-established defragmentation algorithms respectively for performing defragmentation on different types of machine-readable storage devices, a defragmentation algorithm that corresponds to the type of the target machine-readable storage device as determined in step a); and c) configuring the processor to perform defragmentation on the target machine-readable storage device according to the defragmentation algorithm as selected in step b).06-10-2010
20110208903FLASH MEMORY DEVICE CAPABLE OF IMPROVING READ PERFORMANCE - A flash memory device, related system ad method are disclosed. The memory device includes a memory cell array a page buffer receiving read data, wherein the page buffer includes a main register transferring read data to a cache register during an read operation, and a control logic block controlling operation of the page buffer during the read operation, such that initialization of the main register continuously extends beyond a time period during which read data is transferred from the main register to the cache register.08-25-2011
20100138594FLASH MEMORY DATA READ/WRITE PROCESSING METHOD - A flash memory data read/write processing method is provided. The method includes the following steps. An encoding process is performed on the data to be written so that a number of a specific value in the encoded data is reduced compared with that in the original data, and the encoded data is written into a flash memory chip. The encoded data in the flash memory chip is read out, then a decoding process corresponding to the encoding process in Step 1 is performed on the read data, and finally, the decoded data is output. This method may reduce the consumption of a flash memory chip due to writing and erasing operations, thereby prolonging the operating life span of the flash memory chip. This method may also increase the efficiency of writing and erasing operations, reduce the operating time, as well as reduce the power consumption of flash memory operations.06-03-2010
20100005228DATA CONTROL APPARATUS, STORAGE SYSTEM, AND COMPUTER PROGRAM PRODUCT - A data control apparatus includes a mapping-table managing unit that manages a mapping table that is associated with a corrupted-data recovery function of recording data and error correcting code data as redundant data that is given separately from the data, distributed and stored in units of stripe blocks in the plural nonvolatile semiconductor memory devices, the mapping table containing arrangement information of the data and the error correcting code data; a determining unit that determines whether to differentiate frequencies of writing the data into the semiconductor memory devices; and a changing unit that changes the arrangement information by switching the data stored in units of the stripe blocks managed using the mapping table to differentiate the frequencies of writing the data into the semiconductor memory devices, when the determining unit determines that the frequencies of writing the data into the semiconductor memory devices are to be differentiated.01-07-2010
20100005226NONVOLATILE MEMORY DEVICE, ACCESS DEVICE, AND NONVOLATILE MEMORY SYSTEM - An access device 01-07-2010
20100005225NONVOLATILE MEMORY DEVICE, NONVOLATILE MEMORY SYSTEM, AND HOST DEVICE - A nonvolatile memory device has a file system manager and manages the file system of a file to be recorded. The nonvolatile memory device measures time by obtaining time information from outside in each writing file data or based on time information preliminarily obtained. At the time of writing file data, management information of the file system is configured based on the time information at the time. Thus, the time information can be stored in a file entry table, and the time information can be used as file management information. The nonvolatile memory system with high user's convenience can be provided.01-07-2010
20090031073MULTI-INTERFACE AND MULTI-BUS STRUCTURED SOLID-STATE STORAGE SUBSYSTEM - A solid-state storage subsystem, such as a non-volatile memory card or drive, includes multiple interfaces and a memory area storing information used by a data arbiter to prioritize data commands received through the interfaces. As one example, the information may store a priority ranking of multiple host systems that are connected to the solid-state storage subsystem, such that the data arbiter may process concurrently received data transfer commands serially according to their priority ranking. A host software component may be configured to store and modify the priority control information in solid-state storage subsystem's memory area.01-29-2009
20090031075Non-volatile memory device and a method of programming the same - Provided are a non-volatile memory device and a method of programming the same. The method includes: performing a program operation; performing a program verify read operation; and performing a pass/fail determine operation simultaneously with one of a verify recovery operation and a bit line setup operation, after the performing of the program verify read operation.01-29-2009
20090031074Multi-level Cell Flash Memory and Method of Programming the Same - Provided is a flash memory having a multi-level cell (MLC) and a method of programming the same. The method includes identifying a set of first patterns from input data, determining whether there is a set of second patterns stored within the flash memory that is of a number substantially similar to the number of the first patterns, and programming the input data as a most significant bit (MSB) in a location of the flash memory where the identified set of second patterns is stored when it is determined that there is a set of second patterns stored within the flash memory that is of a number substantially similar to the number of first patterns.01-29-2009
20090089489MEMORY CONTROLLER, FLASH MEMORY SYSTEM WITH MEMORY CONTROLLER, AND CONTROL METHOD OF FLASH MEMORY - The memory controller updates a count number based on a new assignment of a logical block to a physical block, and writes count information in the physical block to which the logical block is newly assigned. The count information is defined by the count number. The memory controller decides, based on the count number and the count information stored in each physical block, whether or not to transfer stored data in a physical block to another physical block.04-02-2009
20120036312Wear Leveling Technique for Storage Devices - A method for managing wear levels in a storage device having a plurality of data blocks, the method comprising moving data to data blocks having higher erasure counts based on a constraint on static wear levelness that tightens over at least a portion of the lives of the plurality of data blocks.02-09-2012
20110125959E/P DURABILITY BY USING A SUB-RANGE OF A FULL PROGRAMMING RANGE - A NAND flash memory system is controlled by determining whether to change a value of a voltage threshold. The voltage threshold is associated with an erase operation to a portion of a NAND flash memory chip. In the event it is determined to change the value of the voltage threshold, the value of the voltage threshold is changed and the changed value of the voltage threshold and an identifier associated with the portion of the NAND flash memory chip is stored.05-26-2011
20090083476SOLID STATE DISK STORAGE SYSTEM WITH PARALLEL ACCESSSING ARCHITECTURE AND SOLID STATE DISCK CONTROLLER - A solid state disk (SSD) storage system with a parallel accessing architecture, including a SSD controller and a plurality of transmission interfaces of a predetermined bit number and bandwidth, and a solid state disk controller thereof are provided. The SD controller forms channels for transmitting control signals and data with one or more flash memories through each of the transmission interfaces. That is, independent transmission channels are constituted between the SSD controller, the transmission interfaces with multiple bits, and the flash memories. In one embodiment, the transmission interfaces are compatible with MMC 4.0 protocol or higher. Moreover, a host controls and accesses the flash memories through a SATA bus interface and the SSD controller, and uses a direct memory access (DMA) engine with a bidirectional connection port in the SSD controller to transmit data.03-26-2009
20110208901Memory Systems and Methods of Operating the Same - A memory system includes a nonvolatile memory device, a memory controller for controlling the nonvolatile memory device and a virtual data interface layer that manages reading and/or writing of patterned data from/to the nonvolatile memory device. In a read operation, the virtual data interface layer generates patterned data that is requested to be read. Accordingly, a read speed of the memory system may be improved.08-25-2011
20110208902FILTERED REGISTER ARCHITECTURE TO GENERATE ACTUATOR SIGNALS - In various embodiments, apparatus and systems, as well as methods, may include an enhanced register to provide actuator signals to a memory array, the enhanced register including a first memory device including an first enable input, a first data input coupled to a register data input, and first memory device output, the first memory device output to couple to the memory array, and the enhances register to include a second memory device including a second enable input, a second data input coupled to the register data input, and a second memory device output, wherein the second memory device output provides a first output signal indicating when one or more of the actuator signals from the first memory device output are to be coupled to the register data input.08-25-2011
20100146186Program Control of a non-volatile memory - A method of storing data onto a non-volatile memory includes receiving, from a host, first data that is originally assigned to a first storage area, programming the first data to a second storage area, receiving second data from the host, and while receiving the second data from the host, programming, to the first storage area, the first data that has been programmed to the second storage area, wherein the second data is received from the host simultaneously with the first data being programmed to the first storage area. The second storage area is capable of having data stored thereon faster than the first storage area.06-10-2010
20090043949BLOCK DECODER OF A FLASH MEMORY DEVICE - A block decoder increases the integration level of a flash memory device by reducing the number of control signals. Address signals are substituted with existing high voltage switch signals. The block decoder of a flash memory device includes a primary decoding unit and a secondary decoding unit. The primary decoding unit outputs a decoding signal in response to first and second address coding signals of a high voltage and first to third control signals. The secondary decoding unit outputs a control signal to control the potential of a block word line in response to the decoding signal and first and second pre-decoded signals.02-12-2009
20090164705System and Method for Implementing Extensions to Intelligently Manage Resources of a Mass Storage System - Systems and methods for implementing extensions to intelligently manage resources of a mass storage system are disclosed. Generally, a host sends an extension of an enabled set of extensions to a mass storage system that includes at least one of command sequence information, command information or file attribute information. The host additionally sends a host application command to the mass storage system that includes logical block address information associated with the at least one of command sequence information, command information or file attribute information of the extension. Based on the received extension, the mass storage system intelligently performs operations that efficiently manage the resources of the mass storage system to reduce the frequency of operations such as data consolidation operations, data collection operations, and data copy operations, thereby increasing the data programming and reading performance of the mass storage system.06-25-2009
20100268867METHOD AND APPARATUS FOR UPDATING FIRMWARE AS A BACKGROUND TASK - A method comprising storing data in a first memory that includes a first portion that has read-only access during a normal mode of operation; and during a update mode of operation: copying at least one data structure from the first memory to a second memory where it is available for use during the update mode; and updating data in the first portion of the first memory.10-21-2010
20120072649NONVOLATILE MEMORY SYSTEM, AND DATA READ/WRITE METHOD FOR NONVOLATILE MEMORY SYSTEM - A nonvolatile memory system comprises a nonvolatile memory having a plurality of data areas; and a memory controller operative to control read and write operations to the nonvolatile memory. The memory controller successively executes read/write operations to plural sectors within a selected data area in the nonvolatile memory in accordance with a command and a sector count and sector address fed from a host device.03-22-2012
20120084489SYNCHRONIZED MAINTENANCE OPERATIONS IN A MULTI-BANK STORAGE SYSTEM - A method and system for managing maintenance operations in a multi-bank non-volatile storage device is disclosed. The method includes receiving a data write command and associated data from a host system for storage in the non-volatile storage device and directing a head of the data write command to a first bank in the and a tail of the data write command to a second bank, where the head of the data write command only includes data having logical block addresses preceding logical block addresses of data in the tail of the data write command. When a status of the first bank delays execution of the data write command the controller executes a second bank maintenance procedure in the second bank while the data write command directed to the first and second banks is pending. The system includes a plurality of banks, where each bank may be associated with the same or different controllers, and the one or more controllers are adapted to execute the method noted above.04-05-2012
20110219173SEMICONDUCTOR MEMORY SYSTEM - According to one embodiment, there is provided a semiconductor memory system including a controller and a memory unit. The controller includes a generation unit, an association unit, a retaining unit, an encoding/decoding unit, and a determination unit. When the access request information is managed, the encoding/decoding unit performs, without generating an obfuscation information by the generation unit, an encoding processing or a decoding processing by using the obfuscation information retained in the retaining unit. And when the access request information is not managed, the encoding/decoding unit performs, after the generation unit generates obfuscation information based on the access request information, the encoding processing or the decoding processing.09-08-2011
20090083477METHOD AND APPARATUS FOR FORMATTING PORTABLE STORAGE DEVICE - A method and apparatus for formatting a portable storage device, which are capable of performing formatting optimized for a non-volatile memory of the portable storage device. The method includes: detecting whether file system information is initialized when formatting of the non-volatile memory is started; if the initialization of the non-volatile memory is detected, detecting a cluster size and cluster start position of a storage space of the portable storage device; and if the detected cluster size and the cluster start position information do not match a size and a staring position of a minimum recording unit of the storage space, performing a re-formatting operation of the portable storage device.03-26-2009
20090083475APPARATUS AND METHOD FOR UPDATING FIRMWARE STORED IN A MEMORY - The invention provides a method for updating firmware stored in a memory. In one embodiment, the memory is divided into a plurality of blocks, and the firmware to be updated with a new image version. First, a first data block is obtained from the new image version, and a second data block is obtained from a target block selected from the memory. Whether the first data block is different from the second data block is then checked. The first data block is then written into the target block when the first data block is different from the second data block. Finally, the aforementioned steps are repeated until all of the blocks are processed.03-26-2009
20090182936SEMICONDUCTOR MEMORY DEVICE AND WEAR LEVELING METHOD - Disclosed is a semiconductor memory device and wear leveling method thereof. The semiconductor memory device including: a nonvolatile memory having pluralities of memory blocks, at least one of the memory blocks storing erasing counts of the memory blocks; and a memory controller managing wear leveling of the nonvolatile memory. The memory controller adjusts a period of managing the wear leveling with reference to the erasing counts.07-16-2009
20090182934Memory device and method of multi-bit programming - Memory devices and multi-bit programming methods are provided. A memory device may include a plurality of memory units; a data separator that separates data into a plurality of groups; a selector that rotates each of the plurality of groups and transmits each of the groups to at least one of the plurality of memory units. The plurality of memory units may include page buffers that may program the transmitted group in a plurality of multi-bit cell arrays using a different order of a page programming operation. Through this, evenly reliable data pages may be generated.07-16-2009
20090182937SEMICONDUCTOR MEMORY CARD, AND PROGRAM FOR CONTROLLING THE SAME - A semiconductor memory card that has a sufficient storage capacity when an EC application writes data to a storage is provided. A usage area for the EC application in an EEPROM 07-16-2009
20090164712FLASH MEMORY - A flash memory includes a memory sector, a command interface, a first signal buffer, a control signal generation circuit, a data input buffer, an error correction circuit, an address buffer, an address signal generation circuit, a plurality of data memory circuits, and write circuit. The command interface receives a write data input instruction from an external device to generate a write data input instruction signal, and receives a write instruction from the external device to generate a write instruction signal. The error correction circuit is activated by the write data input instruction signal to receive the write data in synchronization with the write enable signal, and is activated by the write instruction signal to generate a check data for an error correction in synchronization with the control signal.06-25-2009
20090187703MEMORY CARD AND ITS INITIAL SETTING METHOD - In the initial setting of a memory card 07-23-2009
20090164706Emulation of a NAND memory system - A system and a method for emulating a NAND memory system are disclosed. In the method, a command associated with a NAND memory is received. After receipt of the command, a vertically configured non-volatile memory array is accessed based on the command. In the system, a vertically configured non-volatile memory array is connected with an input/output controller and a memory controller. The memory controller is also connected with the input/output controller. The memory controller is operative to interface with a command associated with a NAND memory and based on the command, to access the vertically configured non-volatile memory array for a data operation, such as a read operation or write operation. An erase operation on the vertically configured non-volatile memory array is not required prior to the write operation. The vertically configured non-volatile memory array can be partitioned into planes, blocks, and sub-planes, for example.06-25-2009
20090164707Method and system for accessing non-volatile memory - Accessing a non-volatile memory array is described, including receiving a first data and a memory address associated with the first data, writing the first data to the non-volatile memory array at the memory address of the first data without erasing a second data stored in the non-volatile memory array at the memory address of the first data before writing the first data.06-25-2009
20090164710SEMICONDUCTOR MEMORY SYSTEM AND ACCESS METHOD THEREOF - A semiconductor memory system and access method thereof. The semiconductor memory system includes a nonvolatile memory and a memory controller. The nonvolatile memory stores monitoring data in one or more of plural memory cells. The memory controller controls the nonvolatile memory. The memory controller detects the monitoring data and adjusts a bias voltage, which is provided to the plural memory cells, in accordance with a result of the detection.06-25-2009
20090164709SECURE STORAGE DEVICES AND METHODS OF MANAGING SECURE STORAGE DEVICES - Methods of managing a secure area in a secure storage device include conducting an authentication process between a host and the secure storage device while modifying a size of the secure area, backing up secure data to the host from the secure area after completing the authentication process, updating management information to modify a size of the secure area, and storing the secure data, which has been backed up to the host, into the secure area that is modified in size. Related storage devices are also disclosed.06-25-2009
20090164703FLEXIBLE FLASH INTERFACE - Systems and methods that can facilitate providing a flexible flash interface component that can accommodate communicating with almost any flash memory component (e.g., Open NAND Flash Interface (ONFI) compliant and ONFI noncompliant flash memory). A micro-operations component can contain one or more micro-operation that can be used to execute commands within the flash interface component. To facilitate a flexible flash interface, the micro-operations can include such commands as, but are not limited to, sending a command to the flash memory, sending a row address, sending a column address, transmit data (TXD), receive data (RXD), have the flash interface wait for a ready signal from the flash memory, read a status register from a flash memory, and/or provide an end of sequence (EOS) indication to the flash interface, for example.06-25-2009
20090164700 EFFICIENT MEMORY HIERARCHY IN SOLID STATE DRIVE DESIGN - Systems and methods for improving the performance and reliability of flash memory solid state drive devices are described herein. A flash memory array component stores data. A memory hierarchy component transfers data between the host and the flash memory array component. The memory hierarchy component includes a level one (“L1”) cache coupled to a merge buffer, the flash memory array component, and the host. The merge buffer is coupled to the flash memory array component. The L1 cache and merge buffer include volatile memory, and the host is coupled to the merge buffer and flash memory array component. The memory hierarchy component includes a write component and a read component. The write component writes data to at least one of the L1 cache, merge buffer, or flash memory array component. The read component reads data from at least one of the L1 cache, merge buffer, or flash memory array component.06-25-2009
20090187700RETARGETING OF A WRITE OPERATION RETRY IN THE EVENT OF A WRITE OPERATION FAILURE - Methods and systems are herein disclosed for write operation retry using the data stored and retained in an internal buffer within the non-volatile memory device. By using the data stored in the internal buffer, the systems and method of the present invention eliminate the need to include a dedicated retry buffer at the system level. Thereby, reducing the system cost, minimizing space consumption on a board within the system and, in some instance, limiting the latency attributed to a retry that relies on retrying the write based on re-transferring of the data contents to the internal non-volatile memory buffer.07-23-2009
20090150601Partial Block Data Programming And Reading Operations In A Non-Volatile Memory - Data in less than all of the pages of a non-volatile memory block are updated by programming the new data in unused pages of either the same or another block. In order to prevent having to copy unchanged pages of data into the new block, or to program flags into superceded pages of data, the pages of new data are identified by the same logical address as the pages of data which they superceded and a time stamp is added to note when each page was written. When reading the data, the most recent pages of data are used and the older superceded pages of data are ignored. This technique is also applied to metablocks that include one block from each of several different units of a memory array, by directing all page updates to a single unused block in one of the units.06-11-2009
20090094409WEAR LEVELING METHOD AND CONTROLLER USING THE SAME - A wear leveling method for non-volatile memory is provided, by which the non-volatile memory is substantially divided into a plurality of blocks and the blocks are grouped into a data area and a spare area. The method includes selecting a block based on an erased sequence when getting the block from the spare area. The method also includes performing a wear leveling procedure.04-09-2009
20090138652NON-VOLATILE MEMORY GENERATING DIFFERENT READ VOLTAGES - In one aspect, a non-volatile memory is provided which includes a plurality of m-bit non-volatile memory cells and a plurality of n-bit non-volatile memory cells, where 1≦m05-28-2009
20090138651ENCODING METHOD FOR FLASH MEMORIES - A encoding method for a flash memory is provided, which can be used for reducing the memory wear and extend the endurance of the memory. The encoding method includes the steps as follows: (A) receiving a set of information bits; (B) counting an amount of the information bits needed to be programmed in the set; (C) reversing the set of information bits if the amount of information bits needed to be programmed is less than half of the amount of whole information bits in the set, so that there are more than half of the information bits needed to be programmed in the reversed set; and (D) programming the information bits needed to be programmed in the reversing set, including the reverse flag bit for read out check.05-28-2009
20120198136FLASH BACKED DRAM MODULE INCLUDING LOGIC FOR ISOLATING THE DRAM - A memory device for use with a primary power source including: non-volatile memory; volatile memory; an interface for connecting to a backup power source; isolation logic for controlling access to the volatile memory by a host processor, said isolation logic having a first mode during which the isolation logic provides the host processor with access to the volatile memory for storing or reading data and a second mode during which the isolation logic isolates the volatile memory from access by the host processor; and a controller controlling the isolation logic, said controller programmed to place the isolation logic in the first mode when the volatile memory is being powered by the primary power source and, when power to the volatile memory from the primary power source is interrupted, to place the isolation logic in the second mode and transfer data from the volatile memory to the non-volatile memory.08-02-2012
20130219109MEMORY SYSTEM AND PROGRAM METHOD THEREOF - A memory system includes a nonvolatile memory device having a first data area storing M-bit data using a buffer program operation and a second data area storing N-bit data (N being an integer larger than M) using a main program operation and a memory controller configured to control the nonvolatile memory device. When a main program operation using data stored at the first and second data areas is required, the memory controller calculates values indicating a performance of the required main program operation to be executed according to a plurality of main program manners, selects one of the plurality of main program manners based on the calculated values, and controls the nonvolatile memory device to perform the required main program operation according to the selected main program manner.08-22-2013
20090177835Flash Drive With Spring-Loaded Retractable Connector - A pen-type computer peripheral device includes an elongated housing containing a PCBA having a plug connector. The PCBA is secured to a positioning member that is actuated by way of a press-push button that is exposed through a slot defined in a wall of the housing. A spring-loaded mechanism includes a spring and a locking mechanism that locks the connector in a retracted position and a deployed position, and the spring biases the connector from the retracted position to the deployed position, or vice versa.07-09-2009
20090177834METHOD FOR MANAGING DATA INTENDED TO BE WRITTEN TO AND READ FROM A MEMORY - The invention relates to a method for managing data intended to be written to and read from a memory of FLASHPROM type organized into pages. Several data are stored per page and the method consists: 07-09-2009
20090187701Nand flash memory access with relaxed timing constraints - Timing constraints on data transfers during access of a NAND flash memory can be relaxed by providing a plurality of data paths that couple the NAND flash memory to a buffer that provides external access to the memory. The buffer defines a bit width associated with the external access, and each of the data paths accommodates that bit width.07-23-2009
20090055579Semiconductor memory device for simultaneously programming plurality of banks - Provided is a semiconductor memory device for simultaneously programming a plurality of banks. The semiconductor memory device includes: a memory cell array comprising a plurality of banks; a plurality of data buffers storing a plurality of pieces of program data to be programmed in the corresponding banks; and a plurality of scan latches configured to scan the plurality of program data transmitted from the corresponding data buffers, and configured to generate 102-26-2009
20090055576MEMORY CONTROLLER, NONVOLATILE STORAGE DEVICE, NONVOLATILE STORAGE SYSTEM, AND DATA WRITING METHOD - A nonvolatile storage device is provided with a nonvolatile main storage memory (02-26-2009
20090144489ELECTRONIC DEVICE AND PROGRAM FOR OPERATING THE SAME - A navigation device realizes such processing as map display and route guidance based on map data stored in a memory card. The data in the memory card tends to be volatilized with an increase in the frequency of reading of data. Therefore, the data that are highly frequently read out are held in a RAM so as to be read from the memory card at a decreased frequency. Further, the passage of time is calculated from the date and hour the data are recorded in the memory card, and the whole data in the memory card are refreshed every time when the passage of time exceeds a threshold value T06-04-2009
20090144487STORAGE EMULATOR AND METHOD THEREOF - A storage emulator and method thereof are disclosed. The storage emulator allows a host system to access a storage unit connected to a storage system as if the storage unit is directly coupled to the host system. The storage emulator includes a virtual storage emulating module, a storage-managing unit, and a communicating module. The virtual storage emulating module emulates at least one virtual storage unit corresponding to the storage unit on the host system and receives a storage accessing command from the host system. The storage-managing unit identifies the storage accessing command as either a self-sustaining type command or a non-self-sustaining type command. The communicating module communicates with the storage unit of the storage system via the network. If the storage accessing generates a self-sustaining command response in accordance with the storage accessing command and returns the self-sustaining command response to the host system directly. If the storage accessing command is identified as the non-self-sustaining type command, the storage-managing unit forwards the storage accessing command to the storage system via the network, receives a command response in accordance with the storage accessing command from the storage system, and returns the command response to the host system.06-04-2009
20090024788PORTABLE ELECTRONIC DEVICE AND DATA CONTROL METHOD - A portable electronic device is provided with a storage section which stores various pieces of information and a transmitter/receiver section which transmits and receives data to and from external equipment. It is determined whether or not data paired with write data contained in a write command is stored by the storage section when the write command is received by the transmitter/receiver section, the write data is written to the storage section if it is concluded that the data paired with the write data contained in the write command is stored by the storage section, and the transmitter/receiver section is caused to transmit a result of determination on abnormality to the external equipment if it is concluded that the data paired with the write data contained in the write command is not stored by the storage section.01-22-2009
20090024786External storage device - An external storage device includes a hard-drive, a flash memory, and a memory arrangement unit. The memory arrangement determines if the tag of the data accessed by a computer stored in the tag list of the memory arrangement unit and controls the hard-drive and the flash memory according to the result of the determination.01-22-2009
20110225350Methods and Apparatus for Soft Data Generation for Memory Devices Based Using Reference Cells - Methods and apparatus are provided for soft data generation for memory devices using reference cells. At least one soft data value is generated in a memory device by writing a known data to one or more reference cells; reading one or more of the reference cells; obtaining a read statistic based on the read one or more reference cells; and obtaining the at least one soft data value based on the obtained read statistic. The read statistics can optionally be obtained for one or more desired locations of a memory array; or for a given pattern, PATT, in one or more aggressor cells. The read statistic can optionally comprise asymmetric statistics obtained for a plurality of possible values.09-15-2011
20110225353REDUNDANT ARRAY OF INDEPENDENT DISKS (RAID) WRITE CACHE SUB-ASSEMBLY - In at least some embodiments, a computing system includes a processor and a communication bus external to the processor. The computing system also includes a Redundant Array of Independent Disks (RAID) write cache sub-assembly coupled to the communication bus, the RAID write cache sub-assembly having non-volatile memory.09-15-2011
20110225352APPARATUS AND SYSTEM FOR OBJECT-BASED STORAGE SOLID-STATE DRIVE - An object-based storage system comprising a host system capable of executing applications for and with an object-based storage device (OSD). Exemplary configurations include a call interface, a physical layer interface, an object-based storage solid-state device (OSD-SSD), and are further characterized by the presence of a storage processor capable of processing object-based storage device algorithms interleaved with processing of physical storage device management. Embodiments include a storage controller capable of executing recognition, classification and tagging of application files, especially including image, music, and other media. Also disclosed are methods for initializing and configuring an OSD-SSD device.09-15-2011
20110225351MEMORY CARD AND MEMORY SYSTEM HAVING THE SAME - A memory card includes: a first memory chip responding to all commands input externally; and a second memory chip responding to commands, among the commands input externally, relevant to reading, programming, and erasing operations with data. Card identification information stored in the first memory chip includes capacity information corresponding to a sum of sizes of the first and second memory chips. The plurality of memory chips of the memory card are useful in designing the memory card with storage capacity in various forms.09-15-2011
20110225349Firmware Flashing of a Portable Device Using a Serial Bus Hub - System and method for configuring a portable device. The portable device includes a serial bus hub, one or more processors coupled to the serial bus hub via a serial bus, and a flash memory coupled to the serial bus hub via the serial bus. A degraded signal is received to a serial bus hub included in the portable device via a serial bus, where the degraded signal includes code to be written to the flash memory to initialize or update firmware for the portable device. The serial bus hub restores the degraded signal, thereby generating a restored signal, and sends the restored signal to at least one of the one or more processors to initialize or update the firmware in the flash memory for the portable device.09-15-2011
20110225348ELECTRONIC DEVICES USING REMOVABLE AND PROGRAMMABLE ACTIVE PROCESSING MODULES - System and methods for assembling electronic devices (09-15-2011
20110225347LOGICAL BLOCK STORAGE IN A STORAGE DEVICE - In general, this disclosure relates to storage of logical blocks in a storage device. Aspects of this disclosure describe techniques to monitor the frequency of access of one or more logical blocks referenced by one or more logical block addresses. Based on the frequency of access, in non-limiting aspects of this disclosure, a controller may select one or more physical blocks of a common memory storage block. The storage device may store the logical blocks in the selected physical blocks.09-15-2011
20110225345Storage System Having Volatile Memory and Non-Volatile Memory - The present invention allows a save target stored in a volatile memory, to be reliably saved to a non-volatile memory and reduces the time required for the save processing as much as possible. The charging state of a battery is regularly of irregularly checked. It is determined, according to the checked charging state, which information element stored in the volatile memory should be made a save target at the time of the occurrence of a power interruption. Among a plurality of information elements stored in the volatile memory, a predetermined information element is made a non-save target of save processing, according to a state related to the predetermined information element.09-15-2011
20090240868MANAGEMENT METHOD, MANAGEMENT APPARATUS, AND CONTROLLER FOR MEMORY DATA ACCESS - A management method, a management apparatus, and a controller for memory data access are provided. The management apparatus is disposed between a host and a device for managing the data transmitted between the host and the device, wherein the management apparatus includes a control unit and a storage unit. When the control unit receives a data writing command from the host, it searches for a set mapped to the data in the storage unit and updates the data in the set. Then, the control unit collects the other parts of the data in the storage unit and the device, integrates all parts of the data, and writes the integrated data into the device. Accordingly, the efficiency in data transmission can be improved, and the number of data writing operations can be reduced so that the lifespan of the device can be prolonged.09-24-2009
20090222613INFORMATION PROCESSING APPARATUS AND NONVOLATILE SEMICONDUCTOR MEMORY DRIVE - According to one embodiment, an information processing apparatus includes an information processing apparatus main body, and a nonvolatile semiconductor memory drive which is accommodated in the information processing apparatus main body. The nonvolatile semiconductor memory drive includes a nonvolatile semiconductor memory, an address management table which is indicative of a correspondency between logical block addresses and physical addresses of the nonvolatile semiconductor memory, and a control module. The control module refers to the address management table in response to reception of a read request from the information processing apparatus main body, and outputs data of a predetermined value to the information processing apparatus main body in a case where the physical address corresponding to the logical block address, which is included in the read request, is not stored in the address management table.09-03-2009
20090198879MEMORY SYSTEM AND METHOD OF CONTROLLING THE SAME - A memory system has a memory unit composed of a plurality of memory cells, a memory controller for controlling to read out and write data from and to the memory unit, and a host processor connected to the memory controller for reading out and writing data from and to the memory unit through the memory controller. The memory controller has a refresh controller for rewriting the data stored in the memory unit. The host processor has a determination unit for determining whether or not a refresh operation can be executed to the memory unit and a permission signal transmission unit for transmitting a refresh permission signal when it is determined that the refresh operation can be executed to the memory unit by the determination unit. The refresh controller controls the start of the refresh operation to the memory unit based on the refresh permission signal transmitted from the host processor.08-06-2009
20090198870Methods and Media for Writing Data to Flash Memory - A method for writing bytes to flash memory is disclosed herein whereby the method comprising includes counting bytes from a data source, the bytes associated with a first value and a second value and comparing a number of bytes associated with the first value with a number of bytes associated with the second value. The method may further include inverting the bytes in the case where the number of bytes associated with the first value is greater than the number of bytes associated with the second value and transferring the bytes not associated with the second value to the flash memory.08-06-2009
20090198878INFORMATION PROCESSING SYSTEM AND INFORMATION PROCESSING METHOD - The information processing system is comprised of: a first nonvolatile storage device in which a plurality of first programs for initiating the information processing system, and duplications of the plural first programs have been stored in blocks different from each other; a second volatile storage device to which the plurality of first programs are transferred; a third nonvolatile storage device into which a second program for executing the plural first programs is stored; and a CPU (Central Processing Unit) for executing the plural first programs. While an instruction has been contained in the second program, the instruction instructs that the plurality of first programs are transferred from the first storage device to the second storage device, contents of the plurality of first programs transferred to the second storage devices are compared with each other; and if the contents of the plurality of first programs are not made coincident with each other, then a normal program is judged from the plurality of first programs based upon a majority decision. The CPU executes the first program judged as the normal program so as to initially initiate the information processing system.08-06-2009
20090198877SYSTEM, CONTROLLER, AND METHOD FOR DATA STORAGE - A system, a controller, and a method for data storage are provided. The system includes a first storage unit, a second storage unit, and a controller. The first storage unit comprises a single-layer structure for storing data, and the second storage unit comprises a multi-layer structure for storing data. The controller is coupled to the first storage unit, the second storage unit, and a host and controls the host to set the first storage unit as a master storage device and set the second storage unit as a slave storage device. As a result, the host can recognize the first storage unit and the second storage unit as two independent storage devices for storing data. Thereby, the data storage process can be simplified.08-06-2009
20090198876Programmable Command Sequencer - An embedded subsystem IC which provides simple procedures for an external CPU IC to invoke one or more functions provided by modules of the subsystem is disclosed. The embedded subsystem comprises at least one module to perform at least one function, a first memory, and a sequence controller. Each module is controlled by values stored in local registers of the module. The first memory stores at least one predefined sequence of instructions. Each instruction sequence controls a module to perform a function. The sequence controller comprises a second memory to store a vector table and a state machine. In response to receiving a command the CPU, the sequence controller obtains a start address in the first memory of an instruction sequence corresponding with the command. The state machine programs one or more registers of a module that performs the function identified by the command according to the instruction sequence that begins with the start address.08-06-2009
20090198875DATA WRITING METHOD FOR FLASH MEMORY, AND CONTROLLER AND SYSTEM USING THE SAME - A data writing method for a flash memory is provided. The data writing method includes following steps. First, a block is selected as a substitute block from a spare area of the flash memory, wherein the substitute block is used for substituting a data block in a data area for writing a new data. Next, the new data is directly written into the substitute block starting from a start page, wherein there is valid data in the data block before the address for writing the new data. Thereby, meaningless data moving can be reduced, system performance can be improved, and overlong waiting time for writing the new data can be prevented.08-06-2009
20090198874MITIGATE FLASH WRITE LATENCY AND BANDWIDTH LIMITATION - A memory system is provided. The system includes a controller that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the controller to regulate read and write access to the one or more FLASH devices. Wear leveling components along with read and write processing components are provided to facilitate efficient operations of the FLASH memory devices.08-06-2009
20090198872HARDWARE BASED WEAR LEVELING MECHANISM - A memory system is provided. The system includes a controller that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the controller to regulate read and write access to the one or more FLASH devices. Wear leveling components along with read and write processing components are provided to facilitate efficient operations of the FLASH memory devices.08-06-2009
20090198871EXPANSION SLOTS FOR FLASH MEMORY BASED MEMORY SUBSYSTEM - A memory system is provided. The system includes a controller that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the controller to regulate read and write access to the one or more FLASH devices. Wear leveling components along with read and write processing components are provided to facilitate efficient operations of the FLASH memory devices.08-06-2009
20090198869ERASE COUNT RECOVERY - An erase count of a flash memory block which is lost, e.g., due to power failure is updated or replaced by using known erase counts of other blocks of the flash memory. A flash management algorithm assigns a new erase count value instead of the lost one based on either a maximum value, an average value or a value combining the maximum value of the known erase counts and some tolerance value. The known values may be obtained from wear leveling data or from a stored erase history.08-06-2009
20120290778INCREASED CAPACITY HETEROGENEOUS STORAGE ELEMENTS - Providing increased capacity in heterogeneous storage elements including a method for storing data in a heterogeneous memory that includes receiving a write message and a write address corresponding to a block of memory cells where at least two of the memory cells support different data levels, determining physical characteristics of the memory cells, and identifying virtual memories associated with the block of memory cells in response to the physical characteristics. The following is performed for each of the virtual memories: generating a constraint vector that describes the virtual cells in the virtual memory; and calculating a virtual write vector in response to the constraint vector and the write data, the calculating including writing the write data, bit by bit, in order, into the virtual memory, skipping locations known to be stuck to a particular value as indicated by the constraint vector. The virtual write vectors are combined into a write word and the write word is output to the block of memory cells.11-15-2012
20110145489HYBRID STORAGE DEVICE - A hybrid storage device comprises both solid-state disk (SDD) and at least one hard disk drive (HDD). The hybrid storage device has at least two operational modes: concatenation and safe. According to one aspect, the total capacity of hybrid storage device is the sum of SSD and at least one HDD in a concatenation or big mode, while the total capacity is the capacity of the HDD in a safe mode.06-16-2011
20110145486MEMORY MANAGEMENT DEVICE AND METHOD - According to one embodiment, a device includes a determination unit, compression unit, selecting unit, write updating unit, writing unit. The determination unit determines whether to compress write data based on specific information. The specific information including at least one of the type, number of accesses, access frequency and importance level of the write data. The compression unit compresses the write data when determining to compress the write data. The selecting unit selects a write region for the write data in nonvolatile memory based on the specific information. The write updating unit updates the specific information. The writing unit writes compressed write data into the write region when determining to compress the write data. The writing unit writes uncompressed write data into the write region when not determining to compress the write data.06-16-2011
20110145487Methods and Apparatus for Soft Demapping and Intercell Interference Mitigation in Flash Memories - Methods and apparatus are provided for soft demapping and intercell interference mitigation in flash memories. In one variation, a target cell in a flash memory device capable of storing at least two data levels, s, per cell is read by obtaining a measured read value, r, for at least one target cell in the flash memory; obtaining a value, h, representing data stored for at least one aggressor cell in the flash memory; selecting one or more probability density functions based on a pattern of values stored in at least a portion of the flash memory, wherein the probability density functions comprises pattern-dependent disturbance of one or more aggressor cells on the at least one target cell in the flash memory; evaluating at least one selected probability density function based on the measured read value, r; and computing one or more log likelihood ratios based on a result of the evaluating step.06-16-2011
20110145485METHOD FOR MANAGING ADDRESS MAPPING TABLE AND A MEMORY DEVICE USING THE METHOD - An address mapping table includes arrays each being allocated to a logical address and in which a physical address mapping the logical address is stored. In the case where the physical address mapped to the logical address is changed, a value of a difference between a pre-changed physical address and a physical address to be changed is stored in the address mapping table. When the logical address is mapped to the physical address, the mapped physical address is calculated by adding up the logical address and values stored in the arrays allocated to the logical address. The address mapping table is managed to decrease the number of erase counts of a memory device in which the address mapping table is stored.06-16-2011
20110145483SEMICONDUCTOR MEMORY DEVICE AND METHOD OF PROCESSING DATA FOR ERASE OPERATION OF SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises a plurality of memory blocks, and erase flag storage block storing erase flag information to indicate erase states of the plurality of memory blocks. The erase flag information can be used to monitor completion of erase operations of the memory blocks and to update erase count information of the memory blocks.06-16-2011
20110145480FLASH MEMORY STORAGE SYSTEM FOR SIMULATING REWRITABLE DISC DEVICE, FLASH MEMORY CONTROLLER, COMPUTER SYSTEM, AND METHOD THEREOF - A flash memory storage system including a flash memory chip, a connector, and a controller is provided. The flash memory chip has a plurality of physical blocks. The connector is configured to couple to a host system. The controller is coupled to the flash memory chip and the connector. The controller configures a plurality of logical blocks and maps the logical blocks to a portion of the physical blocks. In addition, the controller identifies rewritable disc commands from the host system and writes data from the host system into the physical blocks mapped to the logical blocks according to the rewritable disc commands. Thereby, a rewritable disc device is simulated by using the flash memory storage system.06-16-2011
20110145479EFFICIENT USE OF HYBRID MEDIA IN CACHE ARCHITECTURES - A multi-tiered cache manager and methods for managing multi-tiered cache are described. Multi-tiered cache manager causes cached data to be initially stored in the RAM elements and selects portions of the cached data stored in the RAM elements to be moved to the flash elements. Each flash element is organized as a plurality of write blocks having a block size and wherein a predefined maximum number of writes is permitted to each write block. The portions of the cached data may be selected based on a maximum write rate calculated from the maximum number of writes allowed for the flash device and a specified lifetime of the cache system.06-16-2011
20110145476Persistent Content in Nonvolatile Memory - Applications may request persistent storage in nonvolatile memory. The persistent storage is maintained across power events and application instantiations. Persistent storage may be maintained by systems with or without memory management units.06-16-2011
20110145475REDUCING ACCESS CONTENTION IN FLASH-BASED MEMORY SYSTEMS - Exemplary embodiments include a method for reducing access contention in a flash-based memory system, the method including selecting a chip stripe in a free state, from a memory device having a plurality of channels and a plurality of memory blocks, wherein the chip stripe includes a plurality of pages, setting the ship stripe to a write state, setting a write queue head in each of the plurality of channels, for each of the plurality of channels in the flash stripe, setting a write queue head to a first free page in a chip belonging to the channel from the chip stripe, allocating write requests according to a write allocation scheduler among the channels, generating a page write and in response to the page write, incrementing the write queue head, and setting the chip stripe into an on-line state when it is full.06-16-2011
20110145474Efficient Use Of Flash Memory In Flash Drives - A data storage device having non-volatile solid state memory permits efficient access by permitting multiple pending commands from a host device. A controller in the data storage device stores information about each command from the host device, and determines which stored command, if any, is presently able to be performed based on the portion of the non-volatile memory and the type of access of the command. The data storage device provides reduced access delays, improves read/write throughput, and avoids the cost of additional memory in the data storage device, by allowing accesses to idle portions of memory to proceed, and by signaling the host device when the data storage device is able to accept data to be written to portions of the non-volatile memory already active due to a previous command.06-16-2011
20110145473Flash Memory Cache for Data Storage Device - A storage device made up of multiple storage media is configured such that one such media serves as a cache for data stored on another of such media. The device includes a controller configured to manage the cache by consolidating information concerning obsolete data stored in the cache with information concerning data no longer desired to be stored in the cache, and erase segments of the cache containing one or more of the blocks of obsolete data and the blocks of data that are no longer desired to be stored in the cache to produce reclaimed segments of the cache.06-16-2011
20110145472METHOD FOR ADDRESS SPACE LAYOUT RANDOMIZATION IN EXECUTE-IN-PLACE CODE - A method for dynamically (i.e., upon boot) rewriting, in a failure resistant manner, of part of, or the entirety of, the flash memory for a device allows for a changing of location for logical blocks of execute-in-place code. Conveniently, the rewriting results in a randomization, of varying degree, of the address space layout upon each boot up cycle.06-16-2011
20090063758PROGRAM AND READ METHOD AND PROGRAM APPARATUS OF NAND FLASH MEMORY - A program method, a read method, and a program apparatus of a NAND flash memory are disclosed. The program method and apparatus of the NAND flash memory provided by the present invention can reduce the programming time of each page and increase the programming speed of the entire NAND flash memory when the data to be programmed in a single operation is less than the storage capacity of all the data storage areas in the page. In addition, the read method of the NAND flash memory provided by the present invention can reduce the number of reading each page and accordingly the number of reading the entire NAND flash memory when the data to be read in a single operation is less than the storage capacity of all the data storage areas in the page.03-05-2009
20090063757Memory emulation in an electronic organizer - An electronic organizer using a memory array that is directly addressed and non-volatile is disclosed. The memory array can be used to replace and emulate multiple memory types such as DRAM, SRAM, non-volatile RAM, FLASH memory, and a non-volatile memory card, for example. The memory array may be randomly accessed. Data stored in the memory array is retained in the absence of electrical power. One or more memory arrays may be used in the electronic organizer. At least one of the memory arrays may be in the form of a removable memory card.03-05-2009
20090063756USING FLASH STORAGE DEVICE TO PREVENT UNAUTHORIZED USE OF SOFTWARE - A flash storage device and a method for using the flash storage device to prevent unauthorized use of a software application are provided. An identifier may be encoded within specific sectors of the flash storage device. One bits of the identifier may be encoded as unusable ones of the specific sectors and zero bits of the identifier may be encoded as usable one of the specific sectors. Alternatively, the zero bits of the identifier may be encoded as the unusable ones of the specific sectors and the one bits of the identifier may be encoded as the usable ones of the specific sectors. The software application may be permitted to execute on a processing device connected to the flash storage device only when the identifier is encoded within the flash storage device.03-05-2009
20090055574NAND Flash Memory Device And Related Method Thereof - The NAND flash memory device contains a NAND flash memory, a mirror data area, and a controller. The mirror data area has a size at least to hold a page of data and is usually formed by random access memory. The controller saves a data to be written into the NAND flash memory that occupies a partial number of the sectors of a first page of the NAND flash memory into the sectors of a second page of the mirror data area. When a new data is to be written into the remaining sectors of the first page of the NAND flash memory, the new data is stored instead into the second page's remaining sectors of the mirror data area. When the second page of the mirror data area is full, the entire second page is written into the first page of the NAND flash memory.02-26-2009
20090055577PROGRAMMING METHODS FOR NONVOLATILE MEMORY - Example embodiments are directed to methods, memory devices, and systems for programming a nonvolatile memory device having a charge storage layer including performing at least one unit programming loop, each unit programming loop including, applying a programming pulse to at least two pages, applying a time delay to the at least two pages, and applying a verifying pulse to the at least two pages.02-26-2009
20090240872MEMORY DEVICE WITH MULTIPLE-ACCURACY READ COMMANDS - A method for data storage includes defining at least first and second read commands for reading storage values from analog memory cells. The first read command reads the storage values at a first accuracy, and the second read command reads the storage values at a second accuracy, which is finer than the first accuracy. A condition is evaluated with respect to a read operation that is to be performed over a given group of the memory cells. One of the first and second read commands is selected responsively to the evaluated condition. The storage values are read from the given group of the memory cells using the selected read command.09-24-2009
20090055578APPARATUS USING FLASH MEMORY AS STORAGE AND METHOD OF OPERATING THE SAME - An apparatus usable with a flash memory as storage and a method of operating the same are provided, which can provide an optimized architecture to a flash memory through combination of a flash transition layer (FTL) with a database. The apparatus includes a flash memory, a device driver to manage a mapping table between logical addresses and physical addresses in accordance with a data operation in the flash memory, and a control unit to perform data recovery of the flash memory by requesting the mapping table through an interface provided by the device driver.02-26-2009
20090055575Flash memory with small data programming capability - The present invention provides a method featuring receiving a request to access a memory array having one or more memory erase units with a data area of flash array and with a specific amount of memory which offers small data programming capability; and if the memory access request includes programming small data, then providing access to the specific amount of memory, or if the memory access request does not include programming small data, then providing access to the data area of flash array; as well as an apparatus in the form of a flash memory device featuring a memory array having one or more memory erase units with a data area of flash array and with a specific amount of memory which offers small data programming capability, and a memory controller, responsive to a request, for providing access to the specific amount of memory if the request includes programming small data, or for providing access to the data area of flash array if the request does not include programming small data.02-26-2009
20120079173NONVOLATILE SEMICONDUCTOR MEMORY DEVICE WITH ADVANCED MULTI-PAGE PROGRAM OPERATION - A nonvolatile semiconductor memory device includes a memory cell array having a plurality of banks and a cache block corresponding to each of the plurality of banks. The cache block has a predetermined data storage capacity. A page buffer is included which corresponds to each of the plurality of banks. A programming circuit programs all of the plurality of banks except a last of said banks with page data. The page data is loaded through each page buffer and programmed into each cache block such that when page data for the last bank is loaded into the page buffer, the loaded page data and the page data programmed into the respective cache blocks are programmed into respective corresponding banks.03-29-2012
20120079171Non-volatile memory systems and methods of managing power of the same - A non-volatile memory system and a method of managing the power of the same are provided. The non-volatile memory system includes a non-volatile memory configured to store a first mapping table comprising a list of a logical address and a physical address corresponding to the logical address with respect to a code region and a list of a logical address and a physical address corresponding to the logical address with respect to a general purpose (GP) region, and a controller configured to load the first mapping table from the non-volatile memory to a first memory and load the second mapping table from the non-volatile memory to a second memory. Power-up of the second memory is delayed with respect to power-up of the non-volatile memory system and the first or second memory is powered down if a condition is satisfied, so that power consumption of the non-volatile memory system is reduced.03-29-2012
20120079170METHOD FOR PERFORMING BLOCK MANAGEMENT, AND ASSOCIATED MEMORY DEVICE AND CONTROLLER THEREOF - A method for performing block management is provided. The method is applied to a controller of a Flash memory having multiple channels, where the Flash memory includes a plurality of blocks respectively corresponding to the channels. The method includes: obtaining at least one portion of a plurality of address-to-channel mapping relationships, for use of writing/programming operations; and according to at least one address-to-channel mapping relationship of the plurality of address-to-channel mapping relationships, programming at least one page of data into the Flash memory through at least one channel in a page mode. An associated memory device and a controller thereof are also provided.03-29-2012
20120079169METHOD FOR PERFORMING META BLOCK MANAGEMENT, AND ASSOCIATED MEMORY DEVICE AND CONTROLLER THEREOF - A method for performing meta block management is provided. The method is applied to a controller of a Flash memory having multiple channels, where the Flash memory includes a plurality of blocks respectively corresponding to the channels. The method includes: utilizing a meta block mapping table to store block grouping relationships respectively corresponding to a plurality of meta blocks, where blocks in each meta block respectively correspond to the channels; and when it is detected that a specific block corresponding to a specific channel within a meta block does not have remaining space for programming, according to the meta block mapping table, utilizing at least one blank block corresponding to the specific channel within at least one other meta block as extension of the specific block, for use of further programming. An associated memory device and a controller thereof are also provided.03-29-2012
20120079168METHOD FOR PERFORMING BLOCK MANAGEMENT, AND ASSOCIATED MEMORY DEVICE AND CONTROLLER THEREOF - A method for performing block management is provided. The method is applied to a controller of a Flash memory having multiple channels. The Flash memory includes a plurality of blocks respectively corresponding to the channels. The method includes: temporarily storing at least one index of at least one good block that is not grouped into any meta block into a spare good block table, where the good block is a block that is not determined as a bad block within the plurality of blocks; and when it is detected that a specific block corresponding to a specific channel within blocks currently grouped into meta blocks is a bad block, dynamically updating the spare good block table for use of block management. In particular, when needed, the good block is utilized for replacing a block grouped into a meta block. An associated memory device and a controller thereof are also provided.03-29-2012
20120079167MEMORY SYSTEM - According to one embodiment, a memory system includes a non-volatile semiconductor memory, a block management unit, and a transcription unit. The semiconductor memory includes a plurality of blocks to which data can be written in both the first mode and the second mode. The block management unit manages a block that stores therein no valid data as a free block. When the number of free blocks managed by the block management unit is smaller than or equal to a predetermined threshold value, the transcription unit selects one or more used blocks that stores therein valid data as transcription source blocks and transcribes valid data stored in the transcription source blocks to free blocks in the second mode.03-29-2012
20120079166ELECTRONIC DEVICE AND METHOD FOR INITIALIZING DATA STORAGE - An electronic device for initializing a data storage is provided. The data storage has been accessed. The data storage includes a plurality blocks, which comprise some bad blocks. Each block comprising a block marking area for writing a block identifier. The block identifier is for marking whether the block is a bad block or a good block. After the data storage is accessed, a bad-block table for recording the block identifier of each block is stored at a predetermined location of the data storage. When initializing the data storage, the electronic device accesses the bad-block table from the predetermined location of the data storage, erases data stored on the data storage, obtains the block identifier of each block from the bad-block table; and writes the block identifier to the block marking area of each block.03-29-2012
20100153628METHOD OF FABRICATING SYSTEMS INCLUDING HEAT-SENSITIVE MEMORY DEVICES - A system code is stored in a first nonvolatile memory. The first nonvolatile memory and a second nonvolatile memory are heated during assembly of an electronic device including the first nonvolatile memory and a second nonvolatile memory. The heating is to a temperature sufficient to change a state of at least some memory cells in the second nonvolatile memory device. After the heating, the system code stored in the first nonvolatile memory is copied into the second nonvolatile memory. The first nonvolatile memory may he less vulnerable to temperature-related data alteration than the second nonvolatile memory. For example, the first nonvolatile memory may include a NAND flash memory and the second nonvolatile memory may include a variable resistance memory.06-17-2010
20100153631Method and data storage device for processing commands - A data storage device for processing a command includes a host interface and a controller. The host interface stores program information sent within the command from a host. The controller decodes the program information that indicates a memory type to be accessed for the command. In addition, the controller determines whether the specified memory type can be accessed according to the command. The controller performs the command by accessing the memory type when the memory type specified by the program information is available for access.06-17-2010
20080263266ADAPTIVE DYNAMIC READING OF FLASH MEMORIES - Each of a plurality of flash memory cells is programmed to a respective one of L≧2 threshold voltage states within a threshold voltage window. A histogram is constructed by determining how many of some or all of the cells have threshold voltages in each of two or more of m≧2 threshold voltage intervals within the threshold voltage window. Reference voltages for reading the cells are selected based on estimated values of shape parameters of the histogram. Alternatively, the cells are read relative to reference voltages that define m≧2 threshold voltage intervals that span the threshold voltage window, to determine numbers of at least a portion of the cells whose threshold voltages are in each of two or more of the threshold voltage intervals. Respective threshold voltage states are assigned to the cells based on the numbers without re-reading the cells.10-23-2008
20080263265ADAPTIVE DYNAMIC READING OF FLASH MEMORIES - Each of a plurality of flash memory cells is programmed to a respective one of L≧2 threshold voltage states within a threshold voltage window. Values of parameters of threshold voltage functions are adjusted in accordance with comparisons of the threshold voltages of some or all of the cells to two or more of m≧2 threshold voltage intervals within the threshold voltage window. Reference voltages for reading the cells are selected based on the values. Alternatively, the m threshold voltage intervals span the threshold voltage window, and respective threshold voltage states are assigned to the cells based on numbers of cells whose threshold voltages are in the intervals, without re-reading the cells.10-23-2008
20080263264DATA ACCESS CONTROL SYSTEM AND METHOD OF MEMORY DEVICE - A data access control system of a memory includes a micro-processor, having a micro-controller, a command decoder, and a memory interface. The data access control system can be used to control display driving of a display system. The command decoder is used to decode the content of a data access command. A memory unit is configured into a first region for storing a first-type data being stored in a memory manner, and a second region for storing a second-type data being stored in a simulation manner of the memory. A bus is connected between the micro-processor and the memory unit, for performing data transmission. The micro-processor uses the memory interface to write data into the first region of the memory unit, and uses the command decoder to convert the nonvolatile data and write into the second region of the memory unit.10-23-2008
20110231598MEMORY SYSTEM AND CONTROLLER - According to one embodiment, a memory system includes a first memory that is nonvolatile, a second memory, and a controller that performs data transfer between a host device and the first memory by using the second memory. The controller caches data of each write command transmitted from the host device in the second memory, and performs a first transfer of transferring the data of each write command, which is cached in the second memory, to the first memory while leaving a beginning portion at a predetermined timing.09-22-2011
20110231597DATA ACCESS METHOD, MEMORY CONTROLLER AND MEMORY STORAGE SYSTEM - A data access method for accessing a non-volatile memory module is provided. The data access method includes configuring a plurality of logical addresses and grouping the logical addresses into logical blocks to map to the physical blocks of the non-volatile memory module, and a host system formats the logical addresses into one partition by using a file system and the partition stores at least one file and a file description block corresponding to the file. The data access method further includes searching an end mark corresponding to entry values of the file description block, setting logical addresses storing the end mark as default pattern addresses, and setting values stored in the logical addresses as default values corresponding to the default pattern addresses. Accordingly, the data access method can divide one partition into a write protect area and a writable area by updating data stored in the default pattern addresses.09-22-2011
20110231596Multi-Tiered Metadata Scheme for a Data Storage Array - Method and apparatus for managing metadata associated with a data storage array. In accordance with various embodiments, a group of user data blocks are stored to memory cells at a selected physical address of the array. A multi-tiered metadata scheme is used to generate metadata which describes the selected physical address of the user data blocks. The multi-tiered metadata scheme provides an upper tier metadata format adapted for groups of N user data blocks, and a lower tier metadata format adapted for groups of M user data blocks where M is less than N. The generated metadata is formatted in accordance with a selected one of the upper or lower tier metadata formats in relation to a total number of the user data blocks in the group.09-22-2011
20110231595SYSTEMS AND METHODS FOR HANDLING HIBERNATION DATA - Systems and methods are disclosed for storing hibernation data in a non-volatile memory (“NVM”). Hibernation data is data stored in volatile memory that is lost during a reduced power event, but is needed to restore the device to the operational state it was in prior to entering into the reduced power event. When a reduced power event occurs, the hibernation data is stored in the NVM. When the device “wakes up” the hibernation data is retrieved and used to restore the device to its prior operational state.09-22-2011
20110231594STORAGE SYSTEM HAVING PLURALITY OF FLASH PACKAGES - The storage system comprises a plurality of flash packages configuring one or more RAID groups, and a controller coupled to the plurality of flash packages. Each flash package comprises a plurality of flash chips configured from a plurality of physical blocks. The controller identifies a target area related to an unnecessary area, unmaps a physical block allocated to a logical block belonging to this target area from this logical block, and manages the unmapped physical block as a free block.09-22-2011
20090100214Management Platform For Extending Lifespan Of Memory In Storage Devices - A management platform for extending lifespan of memory, such as SD, MMC, micro SD, of storage devices is provided. The memory includes a plurality of virtual access units, and a virtual block is defined to include a fixed number of virtual access units. In the management platform, a memory control unit tallies the number of operations performed on a virtual access unit when the virtual access unit is selected to perform on. A processing unit determines whether the data stored in virtual access units should be move to another virtual access unit according to an operation threshold in order to prevent from data loss caused by the memory damage.04-16-2009
20090100216Power saving optimization for disk drives with external cache - A power conservation system implementable in a computer system. The system includes a non-volatile cache memory (NVCM) device for storing information. The NVCM device is operationally coupled to the computer system. The system also includes a data storage device coupled to the NVCM device. The data storage device is for storing said information. The system further includes a controller coupled to the NVCM device. The controller initiates an occurrence of writing the information in the NVCM device to the data storage device. The occurrence of writing causes powering up of the data storage device to which the data is to be written or from which data is to be retrieved.04-16-2009
20090204746FLASH MEMORY STORAGE DEVICE FOR ADJUSTING EFFICIENCY IN ACCESSING FLASH MEMORY - A flash memory storage device for boosting efficiency in accessing flash memory is disclosed. The flash memory storage device provides a Multi-level cell (MLC) flash memory for storing data, a single-level cell (SLC) flash memory for storing data, and a control unit for determining whether to store a file into the MLC NAND flash memory or a SLC NAND flash memory based on the file's data characteristics.08-13-2009
20090083478INTEGRATED MEMORY MANAGEMENT AND MEMORY MANAGEMENT METHOD - An integrated memory management device according to an example of the invention comprises an acquiring unit acquiring a read destination logical address from a processor, an address conversion unit converting the read destination logical address into a read destination physical address of a non-volatile main memory, an access unit reading, from the non-volatile main memory, data that corresponds to the read destination physical address and has a size that is equal to a block size or an integer multiple of the page size of the non-volatile main memory, and transmission unit transferring the read data to a cache memory of the processor having a cache size that depends on the block size or the integer multiple of the page size of the non-volatile main memory.03-26-2009
20090037646Method of using a flash memory for a circular buffer - A method of using a FLASH memory for a circular buffer, and the FLASH memory for same, the method including one or more of the following steps in various exemplary embodiments: providing a circular buffer having a plurality of sectors; designating a byte of each of the plurality of sectors of the circular buffer as a binary state indicator; saving data sequentially in the circular buffer; and cycling through a plurality of sectors of the binary state indicators, such as empty or erase, last, middle and first, as the data is sequentially saved in the circular buffer.02-05-2009
20110029725Switching Drivers Between Processors - Systems, methods, and computer software for operating a device can be used to operate the device in multiple modes. The device can be operated in a first operating mode adapted for processing data, in which a first processor executes a driver for a nonvolatile memory and a second processor performs processing of data stored in files on the nonvolatile memory. An instruction can be received to switch the device to a second operating mode adapted for reading and/or writing files from or to the nonvolatile memory. The driver for the nonvolatile memory can be switched from the first processor to the second processor in response to the instruction, and the driver for the nonvolatile memory can be executed on the second processor after performing the switch. A communications driver can be executed on the first processor in response to the instruction to switch the device to the second operating mode.02-03-2011
20110145488FLASH MEMORY MODULE, STORAGE APPARATUS USING FLASH MEMORY MODULE AS RECORDING MEDIUM AND ADDRESS TRANSLATION TABLE VERIFICATION METHOD FOR FLASH MEMORY MODULE - A purpose of the invention is to immediately return the operation in a flash memory module from low power consumption mode to regular mode. A flash memory controller having memory that stores an address translation table for translating between a logical page address and a physical page address in the flash memory chip controls regular mode and low power consumption mode of operating at lower power consumption than in regular mode by halting operation, or decreasing power supply voltage or lowering operating frequency. A flash memory module having the flash memory controller verifies data in the address translation table while low power consumption mode is set.06-16-2011
20090222614INFORMATION PROCESSING APPARATUS AND NONVOLATILE SEMICONDUCTOR MEMORY DRIVE - According to one embodiment, an information processing apparatus includes an information processing apparatus main body, and a nonvolatile semiconductor memory drive which is accommodated in the information processing apparatus main body. The nonvolatile semiconductor memory drive includes a nonvolatile semiconductor memory, and a control module configured to control, in accordance with a command from the information processing apparatus main body, a write operation, a read operation and an erase operation of the nonvolatile semiconductor memory, to generate, in every predetermined time period, statistical information relating to the write operation, the read operation and the erase operation of the nonvolatile semiconductor memory, and to store the statistical information, which corresponds to each of a plurality of time periods each having a time length corresponding to the predetermined time period, in a memory area of the nonvolatile semiconductor memory.09-03-2009
20090106485READING ANALOG MEMORY CELLS USING BUILT-IN MULTI-THRESHOLD COMMANDS - A method for data storage includes storing data in a memory that includes multi-bit analog memory cells, each of which stores at least first and second data bits by assuming one of a predefined plurality of programming levels associated with respective storage values. The memory has at least a first built-in command for reading the first data bits of the memory cells by comparing the storage values of the memory cells to a first number of first thresholds, and a second built-in command for reading the second data bits of the memory cells by comparing the storage values of the memory cells to a second number of second thresholds, such that the first number is less than the second number. After storing the data, the first data bits are read from the memory cells by executing at least the second built-in command.04-23-2009
20090106487 Electronic Device Having a Memory Element and Method of Operation Therefor - An electronic device comprises a processing unit operably coupled to a buffer random access memory, in turn operably coupled to a non-volatile memory configured to emulate an electrically erasable programmable read only memory. The processing unit is arranged to transfer data between the buffer RAM and the non-volatile memory at a first clock frequency. A second RAM is operably coupled between the processing unit and the non-volatile memory and the processing unit sets a Tag bit in the second RAM to identify an address in the buffer RAM that is being written to or read from by the processing unit.04-23-2009
20090106484DATA WRITING METHOD FOR NON-VOLATILE MEMORY AND CONTROLLER USING THE SAME - A data writing method for a non-volatile memory is provided, wherein the non-volatile memory includes a data area and a spare area. In the data writing method, a plurality of blocks in a substitution area of the non-volatile memory is respectively used for substituting a plurality of blocks in the data area, wherein data to be written into the blocks in the data area is written into the blocks in the substitution area, and the blocks in the substitution area are selected from the spare area of the non-volatile memory. A plurality of temporary blocks of the non-volatile memory is used as a temporary area of the blocks in the substitution area, wherein the temporary area is used for temporarily storing the data to be written into the blocks in the substitution area.04-23-2009
20090204750DIRECT LOGICAL BLOCK ADDRESSING FLASH MEMORY MASS STORAGE ARCHITECTURE - A nonvolatile semiconductor mass storage system and architecture can be substituted for a rotating hard disk. The system and architecture avoid an erase cycle each time information stored in the mass storage is changed. Erase cycles are avoided by programming an altered data file into an empty mass storage block rather than over itself as a hard disk would. Periodically, the mass storage will need to be cleaned up. These advantages are achieved through the use of several flags, and a map to correlate a logical block address of a block to a physical address of that block. In particular, flags are provided for defective blocks, used blocks, and old versions of a block. An array of volatile memory is addressable according to the logical address and stores the physical address.08-13-2009
20090204749Redimdamt purge for flash storage device - A flash storage device includes flash storage units that are purged in response to a condition or command. A flash controller interface receives a command for purging the flash storage device and provides a purge command to flash controllers in the flash storage device. Alternatively, the flash storage device detects a condition in response to which the flash controller interface provides a purge command to the flash controllers. Each flash controller independently erases a flash storage unit in response to receiving the purge command, by writing a pattern of data to the flash storage unit, such that the flash storage units are purged substantially in parallel with each other.08-13-2009
20090204748MULTI-CHANNEL FLASH MEMORY SYSTEM AND ACCESS METHOD - Disclosed is a multi-channel flash memory system formed by flash memories having pages divided into sectors and accessed by corresponding channels. An interface device is configured to access the flash memories via the channels by a unit of at least one sector, wherein the interface device divides an address into a plurality of addresses of sector unit and controls the divided addresses so as to be jumped by a given size.08-13-2009
20090204745Programming device for non-volatile memory and programming method thereof - The invention presents a programming method for a non-volatile memory with a bit signal to be programmed unidirectionally. The method includes the steps of a) providing first data each having a first number of sequential bits of first status in a data page in a non-volatile memory, b) decoding the first number of sequential bits of the first status in the first data into a second number of sequential bits of second status, and c) programming second data in a portion of the data page where the first status has been decoded to the second status.08-13-2009
20090204747Non binary flash array architecture and method of operation - A Flash memory array comprises a plurality of Erase Sectors (Esecs) arranged in a plurality of Erase Sector Groups (ESGs), Physical Pages (slices), and Physical Sectors (PSecs), and there is a non-binary number of at least one of the Erase Sector Groups (ESGs), Physical Pages (slices), and Physical Sectors (PSecs). A user address is translated into a physical address using modular arithmetic to determine pointers (ysel, esg, psec) for specifying a given Erase Sector (ESec) within a given Erase Sector Group (ESG); a given Erase Sector Group (ESG) within a given Physical Sector (Psec); and a given Physical Sector (PSec) within the array.08-13-2009
20090210613Method for Programming a Controller in a Motor Vehicle - A method and apparatus are provided for programming of a control device of a motor vehicle, in which the control device includes at least one program-controlled processor and at least two individually addressable memory areas, in particular at least two physically separated memory components. In order to accelerate the inputting of memory contents the invention suggests that the processor carries out or brings about the following two steps at least intermittently largely simultaneously. On the one hand, checking whether programs, program parts and/or data already written into the first memory area correspond to the data to be written into the first memory area, and on the other hand, writing a program, a program part and/or data into the second memory area.08-20-2009
20090248961MEMORY MANAGEMENT METHOD AND CONTROLLER FOR NON-VOLATILE MEMORY STORAGE DEVICE - A memory management method and a controller for a non-volatile memory storage device are provided. The memor management method and the controller are adapted for establishing a logical-to-physical mapping table of each block in a memory buffer of the controller by merely reading the data stored in a system management area within a start page of each block, so as to promote the management efficiency of the non-volatile memory storage device. In addition, the method and the controller of the present invention integrate all of or a part of the system management areas within the start page for efficiently managing and using the memory capacity of all the system management areas within the start page.10-01-2009
20090138653ELECTRONIC APPARATUS AND METHOD OF CONTROLLING A MEMORY UNIT CONNECTED TO THE SAME - An electronic apparatus in which a memory unit containing a memory and a controller to access the memory in response to an externally input command can be installed. The electronic apparatus comprises a first acquiring section which acquires identification information from the memory unit, a second acquiring section which, on the basis of the identification information acquired by the first acquiring section, acquires one from a plurality of control programs to control the controller of the memory unit, and a setting section which sets an operating environment so as to apply the control program acquired by the second acquiring section to the process of inputting and outputting data to and from the memory unit.05-28-2009
20090210611STORAGE SYSTEM AND DATA WRITE METHOD - The size of a memory management unit in a low-performance non-volatile memory device is maintained, and the size of write data is compared with the size of the memory management unit. If the size of the write data is smaller than that of the memory management unit, the write data is cached by the high-performance non-volatile memory device; or if the size of the write data is not smaller, the write data is written to the low-performance device. Subsequently, a plurality of address values for the write data cached by the high-performance device are referred to; an address segment that is equal to the size of the memory management unit and in which the cached address values are consecutive; and data contained in that address segment is copied from the high-performance device to the low-performance device.08-20-2009
20080276035Wear Leveling - A reference memory location can be designated in a memory device. A memory location can be designated in response to storing data in the memory device. If the identified memory location is associated with the reference memory location then an allocated memory location can be designated relative to the reference memory location, and the allocated memory location can be leveled.11-06-2008
20090240869Sharing Data Fabric for Coherent-Distributed Caching of Multi-Node Shared-Distributed Flash Memory - A Sharing Data Fabric (SDF) causes flash memory attached to multiple compute nodes to appear to be a single large memory space that is global yet shared by many applications running on the many compute nodes. Flash objects stored in flash memory of a home node are copied to an object cache in DRAM at an action node by SDF threads executing on the nodes. The home node has a flash object map locating flash objects in the home node's flash memory, and a global cache directory that locates copies of the object in other sharing nodes. Application programs use an applications-programming interface (API) into the SDF to transparently get and put objects without regard to the object's location on any of the many compute nodes. SDF threads and tables control coherency of objects in flash and DRAM.09-24-2009
20090222612Programmable Food Service Systems - A data key, for use with a programmable food service device, comprises: an insertion portion, for insertion into a key aperture in the programmable food service device; a data memory for storing data relating to the operation of the programmable food service device; and a data connection portion for connecting directly with a data port on a computer, to allow the computer to access the data memory.09-03-2009
20080270680Controller for Non-Volatile Memories and Methods of Operating the Memory Controller - A non-volatile memory system (10-30-2008
20090248963MEMORY CONTROLLER AND MEMORY SYSTEM INCLUDING THE SAME - A memory system includes a memory system includes a nonvolatile memory including a memory space which is formatted from outside by an additional-write type file system, and a memory controller controlling the nonvolatile memory, the memory controller transmitting a write protect error when the memory controller is instructed to write data in an address which is equal to or smaller than an address of previously written data in an address area of the memory space.10-01-2009
20090248967PORTABLE ALARM CONFIGURATION/UPDATE TOOL - A stand-alone portable alarm update tool includes a memory interface for receiving a computer readable memory; a serial port for interconnection to a security alarm panel, by way of a complementary port; a processor; and processor readable memory in communication with the processor, storing software adapting the processor to upload and download configuration files from a removable memory received by the memory port, to the alarm panel, by way of the serial port. Conveniently, the tool may be packaged in a hand-held casing, and which may also house a battery. In this way, the tool may be readily transported by an installer, without being unnecessary heavy or bulky.10-01-2009
20090248966FLASH DRIVE WITH USER UPGRADEABLE CAPACITY VIA REMOVABLE FLASH - An exemplary data storage device includes a fixed storage medium, an expansion socket configured to selectively receive at least one removable memory card, and a controller configured to interface the fixed storage medium and the at least one removable memory card with a host device. An exemplary method includes verifying credentials with verification data stored on the fixed storage medium of the data storage unit, and protecting data on the removable storage medium removably attached to the data storage unit.10-01-2009
20090248965HYBRID FLASH MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME - A hybrid flash memory device and a control method of the hybrid flash memory device are provided. The hybrid flash memory device includes a micro controller connected to a host bus for receiving data to be written in the hybrid flash memory device from a host via the host bus; and a memory module coupled to the micro controller. The flash module includes a first type of flash memory and a second type of flash memory. The data are determined to be written in a first log block of the first type of flash memory when the data size is not greater than a predetermined data size. On the contrary, the data are determined to be written in a second log block of the second type of flash memory when the data size is greater than the predetermined data size.10-01-2009
20090248962Memory system and wear leveling method thereof - A memory system includes a variable resistance memory configured to input and output data by a first unit and a translation layer for managing the degree of wear of the variable resistance memory by a second unit, different from the first unit.10-01-2009
20090248960METHODS AND SYSTEMS FOR CREATING AND USING VIRTUAL FLASH CARDS - Creating and using virtual flash cards is disclosed. A disclosed method includes receiving an input of sets of flash data into a portable handheld device, associating related sets of the flash data based on manual inputs that define the relationship between the related sets of flash data, presenting one of the related sets of flash data via the handheld device and prompting a selection of a set of flash data that is associated with the presented set of flash data. Feedback is provided that indicates whether or not a selected set of flash data is correct.10-01-2009
20090222618MEMORY SYSTEM AND BLOCK MERGE METHOD - In one embodiment, the invention provides a memory system including a flash memory device including a plurality of memory blocks implementing a plurality of data blocks, a plurality of log blocks, and a plurality of free blocks. The memory system further includes a flash translation layer maintaining the number of the free blocks to be at least equal to a reference number by converting selected memory blocks among the data and log blocks into free blocks via at least one merge operation during a background period. Additionally, the flash translation layer converts selected ones of the free blocks into data and log blocks, respectively.09-03-2009
20090222616MEMORY SYSTEM - A controller includes an identification information management table that manages identification information indicating, for each of addresses in second-management unit, whether one or more data in first management unit belonging to the addresses is stored in the second or the third storing area. When the controller executes a process of flushing data from the first storing area to the second storing area or the third storing area, the controller updates the identification information in the identification information management table. The controller executes a process of reading data from the second storing area or the third storing area by referring to the identification information. As a result, the speed of searches conducted in the management table is increased.09-03-2009
20120198142SYSTEM AND APPARATUS FOR FLASH MEMORY DATA MANAGEMENT - The system and apparatus for managing flash memory data includes a host transmitting data, wherein when the data transmitted from the host have a first time transmission trait and the address for the data indicates a temporary address, temporary data are retrieved from the temporary address to an external buffer. A writing command is then executed and the temporary data having a destination address are written to a flash memory buffer. When the flash memory buffer is not full, the buffer data are written into a temporary block of the flash memory. The writing of buffer data into the temporary block includes using an address changing command, or executing a writing command to rewrite the external buffer data to the flash memory buffer so that the data are written into the temporary block.08-02-2012
20120198140ASYMMETRIC MEMORY MIGRATION IN HYBRID MAIN MEMORY - Main memory is managed by receiving a command from an application to read data associated with a virtual address that is mapped to the main memory. A memory controller determines that the virtual address is mapped to one of the symmetric memory components of the main memory, and accesses memory use characteristics indicating how the data associated with the virtual address has been accessed, The memory controller determines that the data associated with the virtual address has access characteristics suited to an asymmetric memory component of the main memory and loads the data associated with the virtual address to the asymmetric memory component of the main memory. After the loading and using the memory management unit, a command is received from the application to read the data associated with the virtual address, and the data associated with the virtual address is retrieved from the asymmetric memory component.08-02-2012
20120198132NON-VOLATILE MEMORY SYSTEM AND APPARATUS, AND PROGRAM METHOD THEREOF - A non-volatile memory system includes a memory area including one or more non-volatile memory apparatuses, and a controller includes a buffer for storing program data, and is configured to transmit a program command and the program data to the memory area and delete the program data stored in the buffer as a program operation is started in the memory area.08-02-2012
20120198130STORAGE SYSTEM AND DATA CONTROL METHOD THEREFOR - A package controller of a flash package, upon receiving an update data write request with respect to a first logical storage area corresponding to a first LU that is treated as a backup target, manages a first physical storage area as a backup storage area in a state where pre-update data is maintained, newly allocates a second physical storage area to the first logical storage area, and writes the update data to the second physical storage area. The package controller, upon receiving an update data write request with respect to a second logical storage area corresponding to a second LU that is treated as a non-backup target, manages a third physical storage area allocated to the second logical storage area as an invalid storage area, and writes the update data to a fourth physical storage area newly allocated to the second logical storage area. The package controller performs control so as to use the first physical storage area to provide backup data for the first LU, and delete pre-update data stored in the third physical storage area.08-02-2012
20120198129AT LEAST SEMI-AUTONOMOUS MODULES IN A MEMORY SYSTEM AND METHODS - A memory system for digital data communication with a host device is described to provide data storage capacity. The system can include a controller and a plurality of modules, each module including a nonvolatile memory device wherein the module is configured to perform a management function with respect to the module at least partially based on a parameter. The parameter is provided by the controller and/or the module. The system and modules, in one feature, can support multiple forms of concurrency with respect to data accesses involving the modules.08-02-2012
20120198128CONTROL ARRANGEMENTS AND METHODS FOR ACCESSING BLOCK ORIENTED NONVOLATILE MEMORY - A read/write arrangement is described for use in accessing at least one nonvolatile memory device in read/write operations with the memory device being made up of a plurality of memory cells which memory cells are organized as a set of pages that are physically and sequentially addressable with each page having a page length such that a page boundary is defined between successive ones of the pages in the set. The read/write arrangement includes a control arrangement that is configured to store and access a group of data blocks that is associated with a given write operation in a successive series of pages of the memory such that at least an initial page in the series is filled and each block includes a block length that is different than the page length.08-02-2012
20120198127COMPOSITE SOLID STATE DRIVE CONTROL SYSTEM - A composite solid state drive control system, composed of a redundant array of independent disks (RAID) formed by SD Cards, and multi-channel Flash Memory. Wherein, at least a RAID control unit combines a plurality of relatively inexpensive SD Cards into a set of redundant arrays of independent disks (RAIDs), so that its storage capacity can reach or even surpass a costly and huge capacity SD Card. Through controlling data transmission and accessing between at least a flash memory control unit and at least a SD Card control unit, data read and write speeds can be increased, and back-up redundant data can be made, hereby achieving stable operations of an electronic computing device by means of highly stable Flash Memory.08-02-2012
20090265505DATA WRITING METHOD, AND FLASH STORAGE SYSTEM AND CONTROLLER USING THE SAME - A data writing method, and a flash storage system and a controller using the same are provided. The method includes grouping the physical blocks of a flash memory into the physical blocks of a data area, a spare area and a special area. The method also includes writing the update data into the corresponding physical block of the special area when the update data is the single accessing unit. The method may include moving a part of valid data in a physical block mapping a logical block where the update data is belonged into a physical block of the spare area during each data writing command. Accordingly, it is possible to reduce the response time for each data writing command, thereby preventing a time-out problem caused by a flash memory having a large erasing unit configured at the flash storage system.10-22-2009
20080244163PORTABLE DATA ACCESS DEVICE - A portable data access device is applicable to a data processing system. The portable data access device includes at least a first data access sector preset to be a read-only data access sector, for storing at least data and/or application programs executable by the data processing system; at least a second data access sector set to be a general data access sector; and a controller for interfacing with the data processing system and controlling data access to the first data access sector and the second data access sector. The data processing system may execute the application programs and/or access the data through the portable data access device, and the risk of modifying or damaging the data and/or application programs can be reduced by the read-only data access sector.10-02-2008
20090210612MEMORY CONTROLLER, NONVOLATILE MEMORY DEVICE, AND NONVOLATILE MEMORY SYSTEM - In rewriting processing of logical sectors, data of the transferred logical sectors are temporarily stored in a memory buffer. When the buffer memory has been full filled with data, the data is written into a flash memory. In rewriting processing for the flash memory including a writing unit (page) having a capacity larger than a minimum writing unit (sector) from outside, the number of executions of the evacuation processing can be reduced and the fast data rewriting can be performed. Thus, it is possible to rationalize the evacuation processing for old data caused in the rewriting in units of sectors and to improve the data rewriting speed.08-20-2009
20090198873PARTIAL ALLOCATE PAGING MECHANISM - A memory system is provided. The system includes a controller that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the controller to regulate read and write access to the one or more FLASH devices. Wear leveling components along with read and write processing components are provided to facilitate efficient operations of the FLASH memory devices.08-06-2009
20090259798Method And System For Accessing A Storage System With Multiple File Systems - In order to write data to a storage system accessible with a first and second file system, a manager receives a data write request associated with a file. The manager determines if a function supported by the second file system is needed to complete the write request. If so, the file is opened and extended with the first file system. The file is then opened and written to by the second file system. The file is truncated by the first file system, and closed by both file systems. If the second file system function is not needed, the file is opened, written, and closed by the first file system. In order to read data from a storage system using a function supported by the second file system, the second file system's cached storage system index is updated, then the file is opened, read, and closed by the second file system.10-15-2009
20090259799METHOD AND APPARATUS FOR A VOLUME MANAGEMENT SYSTEM IN A NON-VOLATILE MEMORY DEVICE - Embodiments for partitioning a non-volatile memory device is described. In one embodiment a memory system includes a first addressable range of memory blocks for storing different types of data. The memory system is partitioned to include a second addressable range of memory blocks capable of storing data indicating attributes of the first addressable range of memory blocks. The second addressable range of memory blocks may also be periodically updated such that the capacities of the first addressable range of memory blocks may be dynamically adjusted depending on application needs and changes to the non-volatile memory device over time. In some embodiments, one partition of a memory device may be configured for high reliability data storage while a second partition is configured for normal reliability storage.10-15-2009
20100036999NOVEL METHOD OF FLASH MEMORY CONNECTION TOPOLOGY IN A SOLID STATE DRIVE TO IMPROVE THE DRIVE PERFORMANCE AND CAPACITY - The present invention provides a novel flash memory connection method between a flash controller and flash devices such that the controller can manage two or more flash devices concurrently. It provides the ability to efficiently manage a large array of non-volatile flash devices in a solid state drive (SSD) and allocate flash memory usage in such a way that at least doubles the SSD bandwidth and the total storage capacity.02-11-2010
20100274957SYSTEM AND APPARATUS WITH A MEMORY CONTROLLER CONFIGURED TO CONTROL ACCESS TO RANDOMLY ACCESSIBLE NON-VOLATILE MEMORY - An apparatus includes a printed circuit board with a plurality of printed circuit board traces, a memory controller mounted on the printed circuit board coupled to one or more of the plurality of printed circuit board traces, a plurality of non-volatile type of memory integrated circuits coupled to the printed circuit board, and a plurality of support integrated circuits coupled between the memory controller and the plurality of non-volatile type of memory integrated circuits.10-28-2010
20100274951ELECTRONIC STORAGE DEVICE WITH IMPROVED STORAGE METHOD - An electronic storage device includes a first memory segment having at least one source block to store information, a second memory segment having at least one backup block corresponding to the source block to make a backup of the information in a LSB memory page of the source block and a control unit connecting with said first memory segment and second memory segment. The control unit reads/writes the first memory segment and second memory segment through two different signal channels respectively. The information can be simultaneously written into the first and second memory segment to get a backup of the information so that the information can be stored safely. The control unit recycles the backup block of the second memory segment not only after the source block of the first memory segment entirely finishes writing the information but also after the source block is erased up in order to release the storage space of the backup block.10-28-2010
20100274949DATA ACCESS METHOD FOR FLASH MEMORY AND STORAGE SYSTEM AND CONTROLLER USING THE SAME - A data access method for accessing a flash memory storage system, a storage system and a controller using the same are provided. A flash memory has a plurality of physical blocks, which are grouped into a system area, a data area, and a spare area. One or more variable tables are established to record transient information of each set of mother-child blocks of the data area and the spare area. The number of the variable table could be adjusted adaptively according to time required for writing the variable table into the system area, such that an overall data access efficiency of the flash memory storage system is enhanced.10-28-2010
20090240871MEMORY SYSTEM - A system includes: a first input buffer that functions as an input buffer for a third storing area; and a second input buffer that functions as an input buffer for the third storing area and that separately stores data with a high update frequency for the third storing area. In the system, a plurality of data written in a first storing area or a second storing area are flushed to the first input buffer in units of logical blocks. Also, a plurality of data written in the first input buffer are relocated to the third storing area in units of logical blocks.09-24-2009
20090164711SEMICONDUCTOR MEMORY CONTROLLER, SEMICONDUCTOR MEMORY, AND METHOD OF CONTROLLING SEMICONDUCTOR MEMORY CONTROLLER - A semiconductor memory controller, which outputs data to be stored in a memory unit to the memory unit via a bus of N-bit width (N is an even number), executes a duplexing process on the data to generate duplicated data, simultaneously outputs the respective duplicated data to two different sections of the memory unit using N/2 bit width for each duplicated data, and stores the duplicated data in the two sections of the memory unit, respectively.06-25-2009
20090144488MEMORY CARD AND METHOD FOR HANDLING DATA UPDATING OF A FLASH MEMORY - The invention provides a method for handling data updating of a flash memory. In one embodiment, the flash memory comprises a mother block comprising a plurality of updated pages to be updated. First, a spare block, recording no data, is popped as a file allocation table (FAT) block corresponding to the mother block. Data for updating the updated pages of the mother block is then written to a plurality of replacing pages of the FAT block. Finally, a plurality of mapping relationships between the replacing pages and the updated pages are recorded in a page mapping table stored in the FAT block.06-04-2009
20090248959FLASH MEMORY AND OPERATING SYSTEM KERNEL - A memory system is provided. The system includes an operating system kernel that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the kernel to regulate read and write access to the one or more FLASH devices.10-01-2009
20090248958FLASH MEMORY USABILITY ENHANCEMENTS IN MAIN MEMORY APPLICATION - A memory system is provided. The system includes an operating system kernel that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the kernel to regulate read and write access to the one or more FLASH devices.10-01-2009
20090248957MEMORY RESOURCE MANAGEMENT FOR A FLASH AWARE KERNEL - A memory system is provided. The system includes an operating system kernel that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the kernel to regulate read and write access to the one or more FLASH devices.10-01-2009
20090248956Apparatus for Storing Management Information in a Computer System - An apparatus for providing management storage via a USB port of a computer system is disclosed. The apparatus includes a flash memory, a first and second switches, a first and second inverters, a designated port, and a controller. Coupled to the flash memory, the first and second switches are controlled by a main power of a computer system in a complementary manner. The first and second inverters, which are powered by a standby power of the computer system, are coupled to a respective control input of the first and second switches. The designated port, which is coupled to the flash memory via the first switch, allows data to be read from and written to the flash memory without booting up the computer system. On the other hand, the controller, which is coupled to the flash memory via the second switch, allows data to be read from and written to the flash memory by the computer system only after the computer system has been booted up.10-01-2009
20100180073FLASH MEMORY DEVICE WITH PHYSICAL CELL VALUE DETERIORATION ACCOMMODATION AND METHODS USEFUL IN CONJUNCTION THEREWITH - A method for determining thresholds useful for converting cell physical levels into cell logical values in an array of digital memory cells storing physical levels which diminish over time, the method comprising determining extent of deterioration of the physical levels and determining thresholds accordingly for at least an individual cell in said array; and reading the individual cell including reading a physical level in the cell and converting the physical level into a logical value using the thresholds, wherein the determining comprises storing predefined physical levels rather than data-determined physical levels in each of a plurality of cells and computing extent of deterioration by determining deterioration of the predefined physical levels.07-15-2010
20100180069BLOCK MANAGEMENT METHOD FOR FLASH MEMORY, AND STORAGE SYSTEM AND CONTROLLER USING THE SAME - A block management method for a flash memory of a storage system is provided, wherein the flash memory includes a plurality of physical blocks. The block management method includes grouping the physical blocks into a plurality of physical units, and grouping the physical units into a data area, a spare area, and a replacement area. The block management method further includes performing a first physical unit switch which switches the physical units between the data area and the spare area, and performing a second physical unit switch which switches the physical units between the spare area and the replacement area. Therefore, the block management method can uniformly use the physical blocks and thereby effectively prolong a lifespan of the storage system.07-15-2010
20090271567METHODS FOR MANAGING BLOCKS IN FLASH MEMORIES - A method for managing blocks in a flash memory is provided, which includes dynamic and static block managing methods. In the dynamic block managing method, a blank block is selected as a swap block for write operation. During each write operation, new data and/or original data in an object block to be operated are written into the swap block, and the object block is erased. Then, a logical address of the object block is changed to be a logical address of the swap block, so that the object block served as the swap block for a next write operation. In the static block managing method, a variable seed parameter is set. Different values of the seed parameter are each associated with a logical address of a respective flash memory block. When the value of the seed parameter varies, data in the flash memory block and the swap block associated to the value of the seed parameter are exchanged, so that the flash memory block associated to the value of the seed parameter becomes the swap block for the next write operation.10-29-2009
20090259801CIRCULAR WEAR LEVELING - A method for flash memory management comprises providing a head pointer configured to define a first location in a flash memory, and a tail pointer configured to define a second location in a flash memory. The head pointer and tail pointer define a payload data area. Payload data is received from a host, and written to the flash memory in the order it was received. The head pointer and tail pointer are updated such that the payload data area moves in a circular manner within the flash memory.10-15-2009
20100161888Data storage system with non-volatile memory using both page write and block program and block erase - An optimized data storage system including non-volatile re-writeable memory having both block program and erase and full or partial page write is disclosed. A memory controller of the system can use block data operations for large data transfers, and page data operations for small data transfers. Page data operations in the non-volatile re-writeable memory do not require block rewrites. One or more layers of the non-volatile re-writeable memory can be fabricated BEOL as two-terminal cross-point memory arrays that are fabricated over a substrate including active circuitry fabricated FEOL. Some or all of the active circuitry can be electrically coupled with the one or more layers of two-terminal cross-point memory arrays to perform data operations on the arrays, such as the block program and block erase and/or full or partial page writes. The arrays can include a plurality of two-terminal memory cells.06-24-2010
20090259805FLASH MANAGEMENT USING LOGICAL PAGE SIZE - Disclosed are techniques for flash memory management, including tracking payload data via one or more data structures configured to define the size of logical pages in a flash memory. In various embodiments, the logical page size may be larger than, equal to, or smaller than a physical page size of a flash memory chip.10-15-2009
20090259808Methods of Sanitizing a Flash-Based Data Storage Device - A data storage device includes one or more non-volatile, blockwise erasable data storage media and a mechanism for sanitizing the media in response to a single external stimulus or in response to a predetermined physical or logical condition. Optionally, only part of the media is sanitized, at a granularity finer than the blocks of the medium. Setting a flag in an auxiliary nonvolatile memory enables an interrupted sanitize to be detected and restarted. Optionally, a “death certificate” verifying the sanitizing is issued. Preferably, the media are configured in a manner that allows atomic operations of the sanitizing to be effected in parallel.10-15-2009
20090259807FLASH MEMORY ARCHITECTURE WITH SEPARATE STORAGE OF OVERHEAD AND USER DATA - A memory device has a plurality of dedicated data blocks for storing only user data and a plurality of dedicated overhead blocks for storing only overhead data. Current overhead segments of a dedicated overhead block can be consolidated and moved to a new dedicated overhead block.10-15-2009
20090259806FLASH MANAGEMENT USING BAD PAGE TRACKING AND HIGH DEFECT FLASH MEMORY - Disclosed are techniques for flash memory management, including utilizing defect information corresponding to a granularity smaller than a physical erase block size of a flash memory chip.10-15-2009
20090259802SMART DEVICE RECORDATION - Valuable information can be retained upon a storage device, such as a flash memory unit. Due to the portable nature of the memory, there can be increased likelihood of theft, less back up of important files not a reliable medium, legal physical transfer of the device between parties, and the like. When an operation is requested to take place related to the device, a check can take place if the operation should be allowed based upon device metadata, such as physical location of the device, device history, and so forth. A determination can be made on if the operation should automatically occur based upon a result of the check. If it is determination that the operation should not automatically occur, then the operation can be denied or a request can be made to an owner of the device on if the operation should be allowed to occur.10-15-2009
20090259800FLASH MANAGEMENT USING SEQUENTIAL TECHNIQUES - Disclosed are techniques for flash memory management, including receiving data from a host, writing the data to a flash memory device in the order it was received from the host, and providing at least one data structure configured to locate the data written to the flash memory device.10-15-2009
20090259804CALIBRATED TRANSFER RATE - Methods, systems, and devices are described for the implementation of a novel architecture to support a calibrated rate for the transfer of circuit configuration data. Sets of configuration data from a memory may be transferred to volatile memory to support reconfigurable circuit elements, for example, for use in a clock generator. Upon system power-up, there may be a default speed for the transfer of the configuration data. Techniques are described to first transfer calibration data upon power-up; the transferred calibration data may then be used to set an accelerated speed for a remaining portion of the transfer.10-15-2009
20100153630Data storage system with complex memory and method of operating the same - A data storage system and a data storing method for the data storage system are provided. The data storage system includes a host unit, a storage unit, and a first input/output bus functioning as an interface between the host unit and the storage unit. The storage unit includes a non-volatile memory buffer unit and a flash memory unit. The non-volatile memory buffer unit includes a plurality of buffers arranged in parallel. The flash memory unit includes a plurality of data storage devices arranged in parallel to input and output data using a parallel method. In the method, a writing request is first classified into one of a plurality of grades according to a writing request frequency when there is a writing request and the writing requested data is stored in one of the non-volatile memory buffer unit and the flash memory unit according to the writing request frequency.06-17-2010
20100153620Storage system snapshot assisted by SSD technology - A method and apparatus for taking a snapshot of a storage system employing a solid state disk (SSD). A plurality of mapping tables in the SSD store data needed to create a one or more point in time snapshots and a current view of the SSD. In response to a write command, the SSD executes its normal write process and updates its mapping tables to indicate the current view of the SSD and additionally retains the original data in a table of pointers to the original data, as the snapshot of an earlier state of the SSD. In the preferred embodiment, the innate ability of SSDs to write data to a new location is used to perform a point-in-time copy with little or no loss in performance in performing the snapshot.06-17-2010
20090276561SPI NAND PROTECTED MODE ENTRY METHODOLOGY - One or more techniques are provided for restricting access to protected modes of operation in a memory device. In one embodiment, detection circuitry is provided and configured to receive and evaluate a protected mode entry sequence for accessing a protected mode of operation. The detection circuitry may be further configured to temporarily enable an output pin on a serial interface between the memory device and a master device to receive inputs, such that a entry sequence may be entered on both the input and output pins. In another embodiment, the detection circuitry may be enabled only if a security code is first provided, thus requiring both the correct security code and entry sequence before protected mode access is allowed. The memory device may also include a parallel NAND memory array, and detection logic may be further configured to enable a serial-to-parallel NAND translator once protected mode access is allowed.11-05-2009
20080307159Method and control device for operating a non-volatile memory, in particular for use in motor vehicles - A method for the consecutive writing of performance quantity data to a non-volatile memory, in particular in a control device in a motor vehicle. The method encompasses the operations of determining a write address, which defines an address space for the writing of a performance quantity datum to be written, the address space being directly contiguous with a memory area occupied by a previously written performance quantity datum, and of writing the performance quantity datum to be written, to the address space of the non-volatile memory defined by the write address. In the determination operation, the write address corresponds directly to an address datum assigned to the most recently written performance quantity data, which is stored in a referencing datum in the non-volatile memory, or it is determined therefrom with the aid of an address offset that is independent of the size of the previously written performance quantity data.12-11-2008
20080307156System For Interfacing A Host Operating Through A Logical Address Space With A Direct File Storage Medium - A method and system for interfacing a system operating through a logical address space with a direct file storage (DFS) medium is disclosed. The method includes receiving data associated with addresses in a logical block address (LBA) format from a host system and generating file objects manageable by the DFS medium based on a determination of the correlation of the LBA data to host file data. The memory system includes non-volatile memory using the DFS format, an interface for receiving LBA format data, and a controller configured to communicate with the host via an LBA interface and generate file objects from the LBA format data correlated to the host application files usable by the memory system.12-11-2008
20080307158METHOD AND APPARATUS FOR PROVIDING DATA TYPE AND HOST FILE INFORMATION TO A MASS STORAGE SYSTEM - A method and system for providing advance data type information to a mass storage system is disclosed. The method may include a host system providing host file information, such as a host file identifier and/or a data type, to a memory system in addition to LBA format data. The system may include a processor, a memory system interface and a host file system operative on the processor to identify and provide host file information and/or data type information to the memory system along with LBA format data.12-11-2008
20080307155Method of Interfacing A Host Operating Through A Logical Address Space With A Direct File STorage Medium - A method and system for interfacing a system operating through a logical address space with a direct file storage (DFS) medium is disclosed. The method includes receiving data associated with addresses in a logical block address (LBA) format from a host system and generating file objects manageable by the DFS medium based on a determination of the correlation of the LBA data to host file data. The memory system includes non-volatile memory using the DFS format, an interface for receiving LBA format data, and a controller configured to communicate with the host via an LBA interface and generate file objects from the LBA format data correlated to the host application files usable by the memory system.12-11-2008
20100185808METHODS AND SYSTEMS FOR STORING AND ACCESSING DATA IN UAS BASED FLASH-MEMORY DEVICE - Methods and systems for storing and accessing data in UAS based flash memory device are disclosed. UAS based flash memory device comprises a controller and a plurality of non-volatile memories (e.g., flash memory) it controls. Controller is configured for connecting to a UAS host via a physical layer (e.g., plug and wire based on USB 3.0) and for conducting data transfer operations via two sets of logical pipes. Controller further comprises a random-access-memory (RAM) buffer configured for enabling parallel and duplex data transfer operations through the sets of logical pipes. In addition, a Smart Storage Switch configured for connecting multiple non-volatile memory devices is included in the controller. Finally, a security module/engine/unit is provided for data security via user authentication data encryption/decryption of the device. Furthermore, the flash memory device includes an optical transceiver configured for optical connection to a host also configured with an optical transceiver.07-22-2010
20100185804INFORMATION PROCESSING DEVICE THAT ACCESSES MEMORY, PROCESSOR AND MEMORY MANAGEMENT METHOD - An information processing device of an example of the invention comprises an address generation section that generates a write address indicating a write position in a nonvolatile memory so that the write position is shifted in order to suppress each number of times of overlapped writing for each position of the nonvolatile memory when a write operation to the nonvolatile memory from a processor is performed, an order generation section that generates order information indicating a generation order of the writing operation, and a write control section that stores write information to the write address, and stores the order information to the nonvolatile memory so that the order information is related to at least one of the stored write information and the write address.07-22-2010
20120246398DISK ARRAY DEVICE AND ITS CONTROL METHOD - To shorten the time from power restoration to the resumption of business operation. During a power failure, a memory controller saves configuration information and directory information of a shared memory to a nonvolatile memory, and saves data of a cache memory to the nonvolatile memory. During power restoration from a power failure, the memory controller returns information of the nonvolatile memory to the shared memory so that it can be updated before the lapse of the initialization time, the micro processor executes online processing based on information of the shared memory, and the memory controller 70 controls the storage area of the cache memory so that it will become gradually writable according to the battery capacity of the battery if the battery capacity of the battery is still gradually increasing even after the lapse of the initialization time.09-27-2012
20120246395MEMORY SYSTEM WITH INTERLEAVED ADDRESSING METHOD - Disclosed is a memory system which includes a nonvolatile memory device including a memory cell array having a plurality of word lines including a first set of word lines storing first data having a high bit error rate, and a second set of word lines storing second data having low bit error rate less than the high bit error rate, and a memory controller that during a program operation maps logical addresses for a portion of the first data and a portion of the second data onto a selected word line selected from the plurality of word lines.09-27-2012
20090094410METHOD FOR BLOCK WRITING IN A MEMORY - A method is provided for block writing in an electrically programmable non-volatile memory, in which a block to be written in the memory includes at least one word. The method includes determining a word write time by dividing a fixed block write time by the number of words in the block to be written, and controlling the memory to successively write each word in the memory during the write time.04-09-2009
20130219110ELECTRONIC APPARATUSES - Electronic apparatus, comprising: non-volatile memory configured to be written to or read from in memory portions which are erased a sector at a time, each said sector comprising a plurality of said portions, and the memory having at least three said sectors each of which is adapted to be erased independently of the others; and control means operable to control erasing of the sectors, wherein: the control means is configured to store in a plurality of the sectors other than a target said sector erasure information concerning an erasure procedure, the erasure procedure involving erasing the target sector, so that such information in the sectors may be inspected to establish a suitable recovery procedure following an interruption event.08-22-2013
20130219105METHOD, DEVICE AND SYSTEM FOR CACHING FOR NON-VOLATILE MEMORY DEVICE - Example embodiments described herein may relate to memory devices, and may relate more particularly to caching for non-volatile memory devices.08-22-2013
20100180070METHOD OF HANDLING I/O REQUEST AND SOLID STATE DRIVE USING THE SAME - A solid state drive (SSD) including a storage that includes a plurality of flash memories configured to be independently drivable and a controller to receive an input/output (I/O) request from a host, to split the I/O request into a plurality of sub-requests each having a size configured to be capable of being processed independently by each flash memory, and to process the I/O request based on the sub-requests.07-15-2010
20100180065Systems And Methods For Non-Volatile Cache Control - In some embodiments, a method for controlling a cache having a volatile memory and a non-volatile memory during a power up sequence is provided. The method includes receiving, at a controller configured to control the cache and a storage device associated with the cache, a signal indicating whether the non-volatile memory includes dirty data copied from the volatile memory to the non-volatile memory during a power down sequence, the dirty data including data that has not been stored in the storage device. In response to the received signal, the dirty data is restored from the non-volatile memory to the volatile memory, and flushed from the volatile memory to the storage device.07-15-2010
20100180066ELECTRONICALLY ADDRESSED NON-VOLATILE MEMORY-BASED KERNEL DATA CACHE - An operating system on a computer system can comprise a user space, which can comprise a persistent data store, and a kernel space, which can be extended by loading kernel modules. As provided herein, the kernel space can utilize kernel designated electronically addressed non-volatile memory (e.g., flash memory) to cache data from the user space persistent store, for example, upon a boot event. The kernel space can further comprise a cache controller that can be used to populate the kernel electronically addressed non-volatile memory with kernel in-memory data caches that comprise user space persistently stored data. In one embodiment, the kernel space can further comprise kernel designated volatile main memory (e.g., RAM), which can be used in conjunction with the kernel electronically addressed non-volatile memory to cache user space persistently stored data. In this way, kernel modules may access user space persistent store data from the RAM and/or electronically addressed non-volatile kernel cache.07-15-2010
20100161891METHOD OF CONTROLLING CARD-SHAPED MEMORY DEVICE - Each of a plurality of memory areas includes a plurality of blocks. Each of the blocks includes a plurality of pages. Each of the memory areas also includes a data cache and a page buffer. A control unit controls a lower-limit value of the number of empty blocks in each of the plurality of memory areas.06-24-2010
20100161889Delivering secured media using a portable memory device - In some embodiments an interface of a portable memory device is used to store content information in a hidden memory region of the portable memory device. The interface is also used to store information in a visible memory region of the portable memory device. The information stored in the visible memory region allows the content information stored in the hidden memory region to be accessed. Other embodiments are described and claimed.06-24-2010
20100161880FLASH INITIATIVE WEAR LEVELING ALGORITHM - A method and apparatus for initiative wear leveling for non-volatile memory. An embodiment of a method includes counting erase cycles for each of a set of multiple memory blocks of a non-volatile memory, the counting of erase cycles for each memory block including incrementing a first count for a physical block address of the memory block, and if the memory block is not a spare memory block, incrementing a second count for a logical block address of the memory block. The method also includes determining whether the non-volatile memory has uneven wear of memory blocks based at least in part on the counting of the erase cycles of the plurality of memory blocks.06-24-2010
20100262753METHOD AND APPARATUS FOR CONNECTING MULTIPLE MEMORY DEVICES TO A CONTROLLER - A control system includes a controller having shared pins and unique pins for receiving and outputting signals from and to first and second memory devices. The first memory device includes signal lines which are electrically connected to shared pins, and the second memory device includes signal lines which are electrically connected to the shared pins together with the signal lines from the first memory device. The controller selectively inputs signals from and output signals to the first memory device and second memory device through the select shared pins.10-14-2010
20100262763DATA ACCESS METHOD EMPLOYED IN MULTI-CHANNEL FLASH MEMORY SYSTEM AND DATA ACCESS APPARATUS THEREOF - A data access method used in a multi-channel flash memory system includes: respectively writing a plurality of data into a plurality of buffer areas of a buffer unit through direct memory accessing; and sequentially reading the plurality of data from the plurality of buffer areas, and respectively and synchronously storing the plurality of read data into the plurality of flash memory units, wherein each of the plurality of data is a data block protected by an error correction code (ECC).10-14-2010
20090292863MEMORY SYSTEM WITH A SEMICONDUCTOR MEMORY DEVICE - A memory system with a semiconductor memory device, in which a physical block of n-bits serves as an erase unit, wherein the address management of the memory device is performed by a logical block with m-bits, “m” being larger than “n” and expressed by a power of two, and wherein a n-bit portion continued from the head address in the logical block is defined as a first management unit corresponding to one physical block of the memory device, and a number of the remaining fraction portions each defined as a second management unit are gathered so as to correspond to one physical block of the memory device.11-26-2009
20100191901NON-VOLATILE STORAGE DEVICE, HOST DEVICE, NON-VOLATILE STORAGE SYSTEM, DATA RECORDING METHOD, AND PROGRAM - A memory controller, a non-volatile storage device, a host device, and a non-volatile storage system capable of performing real-time recording even in the case where normal data and file management information/auxiliary information are written in alternating manner are provided. The host device (07-29-2010
20100191896Solid state drive controller with fast NVRAM buffer and non-volatile tables - Systems and methods for a SSD controller enabling data transfer between a host and flash memories have been achieved. A major component of the SSD controller is a non-volatile buffer memory, which interfaces fast disk drive protocols and slow write and read cycles of NAND flash. Preferably MRAM or Phase Change RAM can be used for the buffer memory. Non-volatile tables can also be implemented for storing dynamic logical to physical address translation, defective sector information and their spare sectors and/or SSD configuration parameters. data are kept in a buffer memory when the buffer memory is not powered07-29-2010
20100185803METHOD AND APPARATUS FOR ADAPTIVE DATA CHUNK TRANSFER - A block memory device and method of transferring data to a block memory device are described. Various embodiments provide methods for transferring data to a block memory device by adaptive chunking. The data transfer method comprises receiving data in a data chunk. The data transfer method then determines that the data chunk is ready to be transferred to a block memory and transfers the data chunk to the block memory. The transfer occurs over duration, repeating the above steps until the transfer is complete. The data transfer method determines that the data chunk is ready to be transferred to the block memory based on at least in part on a duration of a previous transfer.07-22-2010
20100185806CACHING SYSTEMS AND METHODS USING A SOLID STATE DISK - A system includes a control module, a location description module, and a page invalidation module. The control module is configured to write data received from a host to a storage medium, read data from the storage medium, and cache data from at least one of the host and the storage medium in a flash memory. The location description module is configured to map one of a valid and invalid state to a physical location of a subset of data in the flash memory. The page invalidation module is configured to receive a command from one of the host and the control module that includes an address corresponding to the subset and an instruction to set a state of the physical location to the invalid state. The page invalidation module is further configured to set the state of the physical location to the invalid state in response to the command.07-22-2010
20100185807DATA STORAGE PROCESSING METHOD, DATA SEARCHING METHOD AND DEVICES THEREOF - A data storage processing method, a data searching method, and devices thereof are provided. The data storage processing method includes: sequentially writing data to a data recording area in a flash; generating log information according to a physical address of the data in the data recording area and an identifier (ID) of the data, and sequentially writing the log information to a log area in the flash; and constructing a Bloom filter data for the log information in the log area, and sequentially writing the Bloom filter data to a log digest area in the flash. A flash storage structure including the data recording area, the log area, and the log digest area is adopted, thereby reducing the occupied storage space of the flash. In addition, since all the areas adopt a sequential storage mode, the data maintenance is quite simple.07-22-2010
20100185805Method And Apparatus For Performing Wear Leveling In Memory - The embodiment of the solution provides a method for performing wear leveling in a memory. The method includes: dividing the lifecycle of the memory which includes more than one physical blocks into at least one sampling interval; for each sampling interval, getting the first physical block by taking statistics of the degree of the wear leveling of each physical block in the memory in the current sampling interval; getting the second physical block by taking statistics of the updating times of each logical address in the current sampling interval; exchanging the logical addresses and data of the first physical block and the second physical block. The embodiment of the solution also provides an apparatus corresponding the method07-22-2010
20120198125METHODS AND SYSTEMS FOR PERFORMING EFFICIENT PAGE READS IN A NON-VOLATILE MEMORY - Systems and methods are disclosed for increasing efficiency of read operations by selectively adding pages from a pagelist to a batch, such that when the batch is executed as a read operation, each page in the batch can be concurrently accessed. The pagelist can include all the pages associated a read command received, for example, from a file system. Although the pages associated with the read command may have an original read order sequence, embodiments according to this invention re-order this original read order sequence by selectively adding pages to a batch. A page is added to the batch if it does not collide with any other page already added to the batch. A page collides with another page if neither page can be accessed simultaneously. One or more batches can be constructed in this manner until the pagelist is empty.08-02-2012
20100262758DATA STORAGE DEVICE - A data storage device may include a first memory board including multiple memory chips and a controller board that is arranged and configured to operably connect to the first memory board. The controller board may include an interface to a host and a controller that includes a power module and that is arranged and configured to control command processing for multiple memory chips having different voltages, automatically recognize a voltage of the memory chips on the first memory board, configure the power module to operate at the recognized voltage of the memory chips, receive commands from the host using the interface and execute the commands using the memory chips.10-14-2010
20100262766GARBAGE COLLECTION FOR FAILURE PREDICTION AND REPARTITIONING - A method of formatting a data storage device that includes a plurality of flash memory chips includes monitoring a failure rate of memory blocks of one or more flash memory chips of a storage device that has a first usable size for user space applications, estimating a future usable size of the data storage device based on the monitored failure rate, and defining, via a host coupled to the data storage device, a second usable size of the data storage device for user space applications based on the monitored failure rate.10-14-2010
20100262768CONFIGURABLE FLASH MEMORY CONTROLLER AND METHOD OF USE - A FLASH memory controller is disclosed. The controller comprises a microcontroller. The microcontroller including firmware for providing different mappings for different types of FLASH memory chips. The controller also includes FLASH control logic for communicating with the microcontroller and adapted to communicate via a FLASH data bus to at least one FLASH memory chip. The FLASH control logic including mapping logic for configuring the FLASH data bus based upon the type of FLASH memory chip coupled thereto. A method and system in accordance with the present invention provides the following advantages: Configurable data bus on the FLASH memory controller through software to simplify routing complexity. Configurable chip select and control bus for flexibility of FLASH memory placement. Elimination of external resistor network for layout simplicity. A scalable architecture for higher data bus bandwidth support. Auto-detection of FLASH memory type and capacity configuration.10-14-2010
20100262762RAID CONFIGURATION IN A FLASH MEMORY DATA STORAGE DEVICE - A method of storing data in a flash memory data storage device that includes a plurality of memory chips is disclosed. The method includes determining a number of memory chips in the data storage device, defining, via a host coupled to the data storage device, a first partition of the data storage device, where the first partition includes a first subset of the plurality of memory chips and defining a second partition of the data storage device via a host coupled to the data storage device, where the second partition includes a second subset of the plurality of memory chips. First data is written to the first partition while reading data from the second partition, and first data is written to the second partition while reading data from the first partition.10-14-2010
20100262764METHOD FOR ACCESSING STORAGE APPARATUS AND RELATED CONTROL CIRCUIT - A storage apparatus includes a first storage unit and at least a second storage unit. A method for accessing the storage apparatus generates a plurality of bad block lists regarding the plurality of the storage units, respectively, and according to at least one bad block indicated by a bad block list of the first storage unit, configures at least a good block in each second storage unit corresponding to the at least one bad block of the first storage unit as a replacement block of each second storage unit. Accordingly, the method generates a mapping result of each second storage unit according to a bad block list of the second storage unit and each replacement block, and accesses the storage apparatus according to the bad block list of the first storage unit and each mapping result.10-14-2010
20100262765STORAGE APPARATUS, COMPUTER SYSTEM HAVING THE SAME, AND METHODS THEREOF - A storage apparatus includes a memory unit and a controller to set up a memory space of the memory unit as a user data space and a spare space according to a signal representing at least one of the user data space and spare space. An electronic apparatus controls the storage apparatus, and a method controls at least one of the storage apparatus and the electronic apparatus to control a memory space of the storage apparatus.10-14-2010
20100262761PARTITIONING A FLASH MEMORY DATA STORAGE DEVICE - A method of partitioning a data storage device that has a plurality of memory chips includes determining a number memory chips in the data storage device, defining, via a host coupled to the data storage device, a first partition of the data storage device, where the first partition includes a first subset of the plurality of memory chips, defining a second partition of the data storage device via the host where the second partition includes a second subset of the plurality of memory chips, such that the first subset does not include any memory chips of the second subset and wherein the second subset does not include any memory chips of the first subset.10-14-2010
20100262757DATA STORAGE DEVICE - A data storage device may include a first memory board having multiple memory chips and a controller board that is arranged and configured to operably connect to the first memory board. The controller board may include an interface to a host and a controller that is arranged and configured to control command processing for multiple different types of memory chips, automatically recognize a type of the memory chips on the first memory board, receive commands from the host using the interface, and execute the commands using the memory chips.10-14-2010
20100262760COMMAND PROCESSOR FOR A DATA STORAGE DEVICE - An apparatus for queuing and ordering commands for a data storage device may include a slot tracker module that is arranged and configured to track available slots for commands from a host, a command transfer module that is operably coupled to the slot tracker module and that is arranged and configured to retrieve commands from the host based on a number of the available slots, a pending command module that is operably coupled to the command transfer module and that is arranged and configured to queue and order the commands from the host for processing using an ordered list that is based on an age of the commands and a task dispatch module that is operably coupled to the pending command module and that is arranged and configured to dispatch the commands for processing using the ordered list from the pending command module and an availability of storage locations.10-14-2010
20100262754CPU DATA BUS PLD/FPGA INTERFACE USING DUAL PORT RAM STRUCTURE BUILT IN PLD - A programmable logic device and a system and method using the programmable logic device are disclosed. The programmable logic device may include first and second ports in data communication with a memory block including a pair of address areas. The system may include the programmable logic device in data communication with a central processing unit and a controller. The method may include generating a command from the central processing unit based on data read from one of the address areas and written to the second address area wherein the address areas are associated with a common memory address.10-14-2010
20120271992STORAGE SYSTEM THAT EXECUTES PERFORMANCE OPTIMIZATION THAT MAINTAINS REDUNDANCY - One storage area is selected from two or more storage areas of a high load physical storage device, a physical storage device with a lower load than that of the physical storage device is selected, and it is judged whether the redundancy according to the RAID level corresponding to the logical volume decreases when the data elements stored in the selected storage area are transferred to the selected low load physical storage device. If the result of this judgment is that the redundancy does not decrease, the data elements stored in the selected storage area are transferred to a buffer area of the selected low load physical storage device and the logical address space of the logical volume that corresponds to the selected storage area is associated with the buffer area.10-25-2012
20100199023APPARATUS AND METHOD FOR MANAGING MEMORY - A memory management method and apparatus are disclosed. The memory management apparatus may compute a remaining storage capacity of a flash memory based on a number of bad blocks in a flash memory or a number of block-erases of each of a plurality of blocks, and may display the computed remaining storage capacity of the flash memory.08-05-2010
20100191900NONVOLATILE MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A nonvolatile memory device includes memory chips driven in response to respective chip enable signals, and each of the memory chips includes a controller configured to generate and output information about an operation state, and a state information processor configured to calculate an expected consumption current when a target operation is performed based on the information about the operation states for the memory chips, and to output a control signal regarding whether to suspend or perform the target operation.07-29-2010
20100191899Information Processing Apparatus and Data Storage Apparatus - According to one embodiment, an information processing apparatus includes an storage apparatus including a first storage and a second storage. The storage apparatus includes a first data management module which stores data which is required to be read in a the predetermined period in the second storage so that the data requested to be read in the predetermined period is distinguishable. The storage apparatus further includes a second data management module which performs replacement of the data in the second storage so that data should be stored in the second storage, in an order reverse to that in which the data is requested to be read, while retaining the data stored in the second storage by the first data management module.07-29-2010
20100191897SYSTEM AND METHOD FOR WEAR LEVELING IN A DATA STORAGE DEVICE - The present disclosure provides a system and method for wear leveling. In one example, the method includes receiving first data to be stored to a first data storage medium and storing the first data to a first storage location in a nonvolatile data store of a second data storage medium comprising a solid-state memory. The method also includes setting a pointer to enable writing second data that is received to a next storage location in the nonvolatile data store. The next storage location comprises an address of the nonvolatile data store that is sequentially after an address of the first storage location. When the address of the first storage location is a last addressed location of the nonvolatile data store the pointer is set to enable writing the second data to a first addressed location of the nonvolatile data store. The method also includes writing the first data stored in the nonvolatile data store to the first data storage medium when a trigger occurs and preserving the pointer during the writing from the nonvolatile data store to the first data storage device such that the pointer enables writing the second data to the next storage location.07-29-2010
20100161884Nonvolatile Semiconductor Memory Drive, Information Processing Apparatus and Management Method of Storage Area in Nonvolatile Semiconductor Memory Drive - According to one embodiment, a nonvolatile semiconductor memory drive includes a nonvolatile semiconductor memory, and a controller which controls a process of writing and reading data with respect to the nonvolatile semiconductor memory. The controller includes a compaction control module which acquires free groups set in an unused state by rearranging valid data scattered in n groups in groups of a number not larger than n−1 when the number of free groups remaining in a plurality of groups formed as a storage area management unit of the nonvolatile semiconductor memory becomes not larger than a predetermined number, and a compression control module which acquires free groups by compressing stored data in m groups in which access to stored valid data has not been made for a period longer than a predetermined period and rearranging the compressed data in groups of a number not larger than m−1.06-24-2010
20120246387SEMICONDUCTOR MEMORY DEVICE AND CONTROLLING METHOD - According to an embodiment, a semiconductor memory device includes a nonvolatile memory; an input/output control unit to control input/output of data to/from the nonvolatile memory; an address translation table that associates first address information specifying a logical recording position of user data stored in the nonvolatile memory with second address information indicating a physical recording position in the nonvolatile memory; a translating unit to translate the first address information to the second address information according to the table; and a generating unit to generate redundant data for checking whether there is error in the user data and the first address information used as one data piece. The input/output control unit records, as data set, the user data, the first address information, and the redundant data, which are used as one data set, in the physical recording position in the nonvolatile memory indicated by the second address information.09-27-2012
20120246386STORAGE SYSTEM AND STORAGE AREA ALLOCATION METHOD - If a monitor measurement cycle is set as a long cycle, promotion in a short cycle cannot be performed; and even if the number of I/Os is very large in response to fluctuations of the number of I/Os in several minutes to several hours of normal work, pages will be promoted after waiting for several weeks. As a result, I/Os which could have normally accepted by an upper tier will be accepted by a lower tier, which results in a problem of worsening the performance efficiency. A monitoring system capable of preventing demotion due to temporary reduction of the number of I/Os for specific pages from a viewpoint of a long cycle and enabling prompt promotion in response to an increase of the number of U/Os for 309-27-2012
20100199027SYSTEM AND METHOD OF MANAGING INDEXATION OF FLASH MEMORY - The invention is a system of managing indexation of memory. Said system has a microprocessor, and a flash memory. Said flash memory has an indexed area comprising indexed items, and an index that is structured in a plurality of index areas comprising a plurality of entries. Said flash memory comprises an index summary comprising a plurality of elements. Each index summary element is linked to an index area of said index. Each index summary element is built from all entries belonging to said linked index area and is built using k hash functions, with 1≦k.08-05-2010
20100185802SOLID STATE MEMORY FORMATTING - The present disclosure includes methods and devices for solid state drive formatting. One device embodiment includes control circuitry coupled to a number of memory arrays, wherein each memory array has multiple physical blocks of memory cells. The memory arrays are formatted by the control circuitry that is configured to write system data to the number of memory arrays, where the system data ends at a physical block boundary; and write user data to the number of memory arrays, where the user data starts at a physical block boundary.07-22-2010
20120198138Managing Memory Systems Containing Components with Asymmetric Characteristics - A memory controller (MC) is associated with a remapping table to enable access to content in a memory system that includes asymmetric memory. The MC receives a request for a memory read or an Input/Output (I/O) write from a central processing unit (CPU) for a physical address specified by the system's memory management unit (MMU). The CPU uses the MMU to manage memory operations for the CPU, by translating the virtual addresses associated with CPU instructions into physical addresses representing system memory or I/O locations. The MC for asymmetric memories is configured to process the MMU-specified physical addresses as an additional type of virtual addresses, creating a layer of abstraction between the physical address specified by the MMU and the physical memory address with which that address is associated by the MC. The MC shields the CPU from the computational complexities required to implement a memory system with asymmetric components.08-02-2012
20120198137Logical-to-Physical Address Translation for a Removable Data Storage Device - A method for making memory more reliable involves accessing data stored in a removable storage device by translating a logical memory address provided by a host digital device to a physical memory address in the device. A logical memory address is received from the host digital device. The logical memory address corresponds to a location of data stored on the removable storage device. A physical memory address corresponding to the local address is determined by accessing a lookup table corresponding to the logical zone.08-02-2012
20120198135Mapping Data to Non-Volatile Memory - The present disclosure includes systems and techniques relating to non-volatile memory. A described system, for example, includes a non-volatile memory structure having a plurality of multi-level memory cells, a processing device, and a controller. The controller is configured to map a first portion of a first set of consecutive bits of a data segment to a first page associated with the plurality of multi-level memory cells, and map a second portion of the first set of consecutive bits of the data segment to a second page associated with the plurality of multi-level memory cells. The first page is associated with bits of a first significance, and the second page is associated with bits of a second significance.08-02-2012
20120198133ELECTRONIC DEVICE WITH EXPANDABLE MEMORY CAPACITY AND AN EXPANSION METHOD THEREOF - An electronic device includes a processor, an internal memory for storing system information and installing programs, and a memory expansion interface for connecting an expansion memory. The expansion memory is partitioned into at least one region to expand the internal memory. The internal memory is partitioned into a system region and a user region; the system region is used to store system information while the user region can be controlled and used by a user. The processor further includes a detection unit and a memory management unit. The detection unit detects the connection of the expansion memory to the memory expansion interface, and the memory management unit determines whether the expansion memory has been previously configured to expand the internal memory, and if not, the memory management unit associates the expansion memory with the internal memory to expand the internal memory.08-02-2012
20120198131DATA WRITING METHOD FOR REWRITABLE NON-VOLATILE MEMORY, AND MEMORY CONTROLLER AND MEMORY STORAGE APPARATUS USING THE SAME - A data writing method for writing data into physical blocks of a memory storage apparatus, and a memory controller and a memory storage apparatus using the same are provided, the physical blocks are grouped into a plurality of physical units. The method includes switching the speed mode of the memory storage apparatus into a first speed mode or a second speed mode according to a command and a work frequency received from a host system. The method also includes selecting a first writing mode to write the data into the physical units when the speed mode is the first speed mode. The method further includes selecting a second writing mode to write the data into the physical units when the speed mode is the second speed mode. Accordingly, the method can effectively shorten the time of executing a write command from the host system.08-02-2012
20120198123SYSTEMS AND METHODS FOR REDUNDANTLY STORING METADATA FOR NON-VOLATILE MEMORY - Systems and methods are provided for storing data to or reading data from a non-volatile memory (“NVM”), such as flash memory, using a metadata redundancy scheme. In some embodiments, an electronic device, which includes an NVM, may also include a memory interface for controlling access to the NVM. The memory interface may receive requests to write user data to the NVM. The user data from each request may be associated with metadata, such as a logical address, a directional flag, or other data. In response to a write request, the NVM interface may store the user data and its associated metadata in a first memory location (e.g., page), and may store a redundant copy of the metadata in a second memory location. The directional flag indicates the geometric relationship between the first memory location and the second memory location. Thus, if the first memory location becomes inaccessible, the memory interface can still recover the metadata from the backup copy stored in the second memory location.08-02-2012
20100250835METHOD FOR PROTECTING SENSITIVE DATA ON A STORAGE DEVICE HAVING WEAR LEVELING - Disclosed is a method for protecting sensitive data in a storage device having wear leveling. In the method, a write command, with an associated sensitive write signal indicating that sensitive data is associated with the write command, is received. The sensitive data is further associated with at least one address pointing to a storage location within an initial physical storage block. The write command is executed by writing to at least one storage location within an available physical storage block, pointing the at least one address to the at least one storage location within the available physical storage block, and erasing the initial physical storage block to complete execution of the write command.09-30-2010
20100250829SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR SENDING LOGICAL BLOCK ADDRESS DE-ALLOCATION STATUS INFORMATION - A system, method, and computer program product are provided for sending de-allocation status information. In use, a de-allocation status of at least a portion of memory associated with a logical block address is determined. Additionally, de-allocation status information is generated, based on the determination. Furthermore, the de-allocation status information is sent to a device.09-30-2010
20100250830SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR HARDENING DATA STORED ON A SOLID STATE DISK - A system, method, and computer program product are provided for hardening data stored on a solid state disk. In operation, it is determined whether a solid state disk is to be powered off. Furthermore, data stored on the solid state disk is hardened if it is determined that the solid state disk is to be powered off.09-30-2010
20100250839METHOD FOR CONTROLLING MEMORY CARD AND METHOD FOR CONTROLLING NONVOLATILE SEMICONDUCTOR MEMORY - A method for controlling a memory card which includes a nonvolatile semiconductor memory whose memory area includes a plurality of write areas is disclosed. A first area which is a part of the plurality of write areas is set in accordance with management executed by a first file system. The first file system sequentially writes data along a direction in which addresses of the plurality of write areas increase. A second area which is a part of the plurality of write areas is set in accordance with management executed by a second file system. The second file system writes data in an order which does not depend on the addresses.09-30-2010
20100161885SEMICONDUCTOR STORAGE DEVICE AND STORAGE CONTROLLING METHOD - A semiconductor storage device includes a first storage unit having a plurality of first blocks as data write regions; an instructing unit that issues a write instruction of writing data into the first blocks; a converting unit that converts an external address of input data to a memory position in the first block with reference to a conversion table in which external addresses of the data are associated with the memory positions of the data in the first blocks; and a judging unit that judges whether any of the first blocks store valid data associated with the external address based on the memory positions of the input data, wherein the instructing unit issues the write instruction of writing the data into the first block in which the valid data is not stored, when any of the first blocks does not store the valid data.06-24-2010
20100161890CACHE MANAGEMENT METHOD AND CACHE DEVICE USING SECTOR SET - A cache management method and a cache device using a sector sets, are provided. The cache management method includes receiving at least one of a write request and a read request for predetermined data, from a host device. The cache determines whether a cache memory is allocated to a sector set including the predetermined sector, and selectively allocates the cache memory to the sector set based on the result of determination. The cache may store the data in the cache memory allocated to the sector set.06-24-2010
20100161886Architecture for Address Mapping of Managed Non-Volatile Memory - The disclosed architecture uses address mapping to map a block address on a host interface to an internal block address of a non-volatile memory (NVM) device. The block address is mapped to an internal chip select for selecting a Concurrently Addressable Unit (CAU) identified by the block address. The disclosed architecture supports generic NVM commands for read, write, erase and get status operations. The architecture also supports an extended command set for supporting read and write operations that leverage a multiple CAU architecture.06-24-2010
20090077306OPTIMIZING MEMORY OPERATIONS IN AN ELECTRONIC STORAGE DEVICE - To optimize memory operations, a mapping table may be used that includes: logical fields representing a plurality of LBA sets, including first and second logical fields for representing respectively first and second LBA sets, the first and second LBA sets each representing a consecutive LBA set; PBA fields representing PBAs, including a first PBA disposed for representing a first access parameter set and a second PBA disposed for representing a second access parameter set, each PBA associated with a physical memory location in a memory store, and these logical fields and PBA fields disposed to associate the first and second LBA sets with the first and second PBAs; and, upon receiving an I/O transaction request associated with the first and second LBA sets, the mapping table causes optimized memory operations to be performed on memory locations respectively associated with the first and second PBAs.03-19-2009
20090077305Flexible Sequencer Design Architecture for Solid State Memory Controller - A method and apparatus for controlling access to solid state memory devices which may allow maximum parallelism on accessing solid state memory devices with minimal interventions from firmware. To reduce the waste of host time, multiple flash memory devices may be connected to each channel. A job/descriptor architecture may be used to increase parallelism by allowing each memory device to operate separately. A job may be used to represent a read, write or erase operation. When firmware wants to assign a job to a device, it may issue a descriptor, which may contain information about the target channel, the target device, the type of operation, etc. The firmware may provide descriptors without waiting for a response from a memory device, and several jobs may be issued continuously to form a job queue. After the firmware finishes programming descriptors, a sequencer may handle the remaining work so that the firmware may concentrate on other tasks.03-19-2009
20090077303System for transferring information and method thereof - A system for transferring information and method thereof, the system includes a management processor, a storage processor and a peripheral. Moreover, the management processor connects to the storage processor by I2C bus and GPIO bus, wherein the I2C bus is used for transmitting information from the management processor to the storage processor, and the GPIO bus is used for transmitting acknowledged instruction from the storage processor to the management processor. Moreover, the management processor transmits the information to the storage processor continuously until the management processor receives an acknowledged instruction from the storage processor. Furthermore, the storage processor waits to receive the information from the management processor, and replies the acknowledged instruction to the management processor after the storage processor receives the information correctly.03-19-2009
20090077304MEMORY SYSTEM HAVING NONVOLATILE AND BUFFER MEMORIES, AND READING METHOD THEREOF - Disclosed is a method for reading data in a memory system including a buffer memory and a nonvolatile memory, the method being comprised of: determining whether an input address in a read request is allocated to the buffer memory; determining whether a size of requested data is larger than a reference unless the input address is allocated to the buffer memory; and conducting a prefetch reading operation from the nonvolatile memory if the requested data size is larger than the reference.03-19-2009
20090077302Storage apparatus and control method thereof - This storage apparatus has a disk-shaped storage device for storing data sent from a host system, and includes a nonvolatile memory device for storing the data, a controller for controlling the reading or writing of the data sent from the host system from or into the disk-shaped storage device, and a device controller for controlling the nonvolatile memory device and the disk-shaped storage device. The device controller replicates data stored in the disk-shaped storage device to the nonvolatile memory device according to the usage of the disk-shaped storage device. The controller reads data from the nonvolatile memory device when the controller receives a data read request from the host system and corresponding data is stored in the nonvolatile memory device.03-19-2009
20090077301PROGRAMMABLE SEQUENCE GENERATOR FOR A FLASH MEMORY CONTROLLER - A programmable sequence generator for controlling a flash memory device. The programmable sequence generator includes a plurality of programmable sequence registers including control phase sequence (CPS) registers and data phase sequence (DPS) registers programmed with phase sequence values corresponding to an operation command sequence of the flash memory device; and logic circuitry in a programmable command sequencer for controlling a set of states of the programmable command sequencer using the plurality of programmable sequence registers.03-19-2009
20100223424MEMORY SYSTEM AND CONTROL METHOD THEREOF - A memory system includes a nonvolatile memory including a plurality of blocks as data erase units, a measuring unit which measures an erase time at which data of each block is erased, and a block controller which writes data supplied from at least an exterior into a first block which is set in a free state and whose erase time is oldest.09-02-2010
20100217925BLOCK MANAGEMENT FOR MASS STORAGE - An embodiment of the present invention includes a nonvolatile memory system comprising nonvolatile memory for storing sector information, the nonvolatile memory being organized into blocks with each block including a plurality of sectors, each sector identified by a logical block address and for storing sector information. A controller is coupled to the nonvolatile memory for writing sector information to the latter and for updating the sector information, wherein upon updating sector information, the controller writes to the next free or available sector(s) of a block such that upon multiple re-writes or updating of sector information, a plurality of blocks are substantially filled with sector information and upon such time, the controller rearranges the updated sector information in sequential order based on their respective logical block addresses thereby increasing system performance and improving manufacturing costs of the controller.08-26-2010
20100146191SYSTEM AND METHODS EMPLOYING MOCK THRESHOLDS TO GENERATE ACTUAL READING THRESHOLDS IN FLASH MEMORY DEVICES - A method for reading at least one page within an erase sector of a flash memory device, the method comprising computing at least one mock reading threshold; using the at least one mock reading threshold to perform at least one mock read operation of at least a portion of at least one page within the erase sector, thereby to generate a plurality of logical values; defining a set of reading thresholds based at least partly on the plurality of logical values; and reading at least one page in the erase sector using the set of reading thresholds.06-10-2010
20100217919MEMORY CONTROLLER, SEMICONDUCTOR MEMORY DEVICE AND CONTROL METHOD THEREOF - A memory controller includes logical-physical address conversion table, an access number storing section configured to store the number of accesses to read out data from a memory cell in association with a logical address, a storage state checking section configured to check a storage state of data stored in the memory cell at every predetermined number of accesses, and a refresh processing section configured to perform refresh processing to restore the data stored in the memory cell if the storage state of the data is in a predetermined degraded state.08-26-2010
20100153627SYSTEM AND METHOD FOR MANAGING FILES IN FLASH MEMORY - A system and method for managing files in a flash memory. The flash memory has a first storage area and a second storage area for storing files. Each of the files has a file header and a data block. The method includes writing the file header of each of the files into the first storage area and setting the first storage area as a first mode, writing the data block of each of the files into the second storage area and setting the second area as a second mode. Responding to the data block of one of the files being completely written into the second storage area, a memory address of the data block stored in the second storage area is written to a corresponding file header.06-17-2010
20100153626MEMORY SYSTEM - To provide a memory system that can surely restore management information even when a program error occurs during data writing. After “log writing (06-17-2010
20100153629SEMICONDUCTOR MEMORY DEVICE - A command analyzer 06-17-2010
20100153625SEMICONDUCTOR MEMORY DEVICE - A semiconductor device including a plurality of flash memories, a connector for establishing connection with a host apparatus, a cache memory for data transmission between the flash memories and the host apparatus, a drive control circuit that controls the data transmission between the flash memories and the host apparatus, and a power supply circuit that converts an external power supply voltage into an internal power supply voltage, all mounted on a substrate. A fuse that protects at least the flash memories from an overcurrent is also provided on the substrate.06-17-2010
20100228909Caching Performance Optimization - A method for managing data storage is described. The method includes receiving data from an external host at a peripheral storage device, detecting a file system type of the external host, and adapting a caching policy for transmitting the data to a memory accessible by the storage device, wherein the caching policy is based on the detected file system type. The detection of the file system type can be based on the received data. The detection bases can include a size of the received data. In some implementations, the detection of the file system type can be based on accessing the memory for file system type indicators that are associated with a unique file system type. Adapting the caching policy can reduce a number of data transmissions to the memory. The detected file system type can be a file allocation table (FAT) system type.09-09-2010
20100228908MULTI-PORT MEMORY DEVICES AND METHODS - An integrated circuit device may include a first integrated circuit (IC) portion having a single memory port to access at least one memory array, the single port including a first set of address, control and data paths; and a second IC portion comprising at least a first memory port and a second memory port for providing access to the memory locations of the first IC portion through the single port of the first IC portion.09-09-2010
20100241788FLASH MEMORY WRITING MTHEOD AND STROAGE SYSTEM AND CONTROLLER USING THE SAME - A flash memory writing method for writing data into a flash memory storage system is provided. In the present method, a big data usage number and a small data usage number are counted for each logical unit in the flash memory storage system, so as to respectively represent the numbers of writing a big data and a small data into each the logical unit. When a host system writes new data into a logical unit in the flash memory storage system, the new data is written through different writing processes according to the big data usage number and the small data usage number of the logical unit. Thereby, the data writing efficiency is improved and the lifespan of the flash memory storage system is prolonged.09-23-2010
20100241792STORAGE DEVICE AND METHOD OF MANAGING A BUFFER MEMORY OF THE STORAGE DEVICE - A storage device including a processor to transmit N pages of data from one or more pages in a buffer memory where N is a natural number. The storage device also includes a flash memory to program in parallel the N pages of data to N flash chips. The N pages may be transmitted via one or more channels.09-23-2010
20100241790METHOD OF STORING DATA INTO FLASH MEMORY IN A DBMS-INDEPENDENT MANNER USING THE PAGE-DIFFERENTIAL - The present invention proposes an effective and efficient method of storing data called page-differential logging for flash-based storage systems. The primary characteristics of the invention are: (1) it writes only the page-differential that is defined as the difference between an original page in flash memory and an up-to-date page in memory; (2) it computes and writes the page-differential only when an updated page needs to be reflected into flash memory. When an updated page needs to be reflected into flash memory, the present invention stores the page into a base page and a differential page in flash memory. When a page is recreated from flash memory, it reads the base page and the differential page, and then, creates the page by merging the base page with its page-differential in the differential page. This invention significantly improves I/O performance of flash-based storage systems compared with existing page-based and log-based methods.09-23-2010
20100228905MEMORY CONTROLLER, MEMORY CARD, AND NONVOLATILE MEMORY SYSTEM - A nonvolatile memory system includes a memory card (09-09-2010
20100228906Managing Data in a Non-Volatile Memory System - Management of data in a non-volatile memory system is disclosed. A write command may be received that indicates a logical block address for writing data associated with the write command. The logical block address may be within a logical zone. The logical zone may be one of a plurality of logical zones within the non-volatile memory, wherein each of the plurality of logical zones comprises a different range of logical block addresses than the rest of the plurality of logical zones. The logical zone may further comprise a temporary storage block. The data associated with the write command may be written to the temporary storage block of the logical zone when a size of the data associated with the write command does not exceed a threshold. The data associated with the write command may be transferred from the temporary storage block to the logical block address in response to a trigger event.09-09-2010
20100217927STORAGE DEVICE AND USER DEVICE INCLUDING THE SAME - A storage device includes a host interface, a buffer memory, a storage medium, and a controller. The host interface is configured to receive storage data and an invalidation command, where the invalidation command is indicative of invalid data among the storage data received by the host interface. The buffer memory is configured to temporarily store the storage data received by the host interface. The controller is configured to execute a transcribe operation in which the storage data temporarily stored in the buffer memory is selectively stored in the storage medium. Further, the controller is responsive to receipt of the invalidation command to execute a logging process when a memory capacity of the invalid data indicated by the invalidation command is equal to or greater than a reference capacity, and to execute an invalidation process when the memory capacity of the invalid data is less than the reference capacity. The logging process includes logging a location of the invalid data, and the invalidation process includes invalidating the invalid data.08-26-2010
20100217918DATA STORAGE DEVICE AND METHOD FOR ACCESSING FLASH MEMORY - The invention provides a method for accessing a flash memory. In one embodiment, the flash memory comprises a plurality of memory units, each of the memory units has a physical address, and an address link table records a mapping relationship between a plurality of logical addresses and a plurality of physical addresses. First, first data to be written to a first logical address is received from a host. Whether the first data is predetermined data is the determined. Whether the first logical address is mapped to a null physical address is then determined according to the address link table. When the first data is the predetermined data and the first logical address is not mapped to the null physical address according to the address link table, the address link table is modified to map the first logical address to the null physical address.08-26-2010
20100217917SYSTEM AND METHOD OF FINALIZING SEMICONDUCTOR MEMORY - Systems and methods of finalizing a semiconductor memory are disclosed. A method includes receiving an instruction to finalize data at a data storage device that includes a controller coupled to a semiconductor memory. The data storage device also includes a status indicator to indicate a finalize status of the semiconductor memory. In response to receiving the instruction to finalize the data at the data storage device, the status indicator is set to a finalize value. Write to the semiconductor memory operations are prevented by the controller in response to the status indicator having the finalize value.08-26-2010
20120036311CACHE AND DISK MANAGEMENT METHOD, AND A CONTROLLER USING THE METHOD - A cache and disk management method is provided. In the cache and disk management method, a command to delete all valid data stored in a cache, or specific data corresponding to a (*portion? part of the valid data may be transmitted to a plurality of member disks. That is, all of the valid data or the specific data may exist in the cache only, and may be deleted from the plurality of member disks. Accordingly, the plurality of member disks may secure more space, an internal copy overhead may be reduced, and more particularly, solid state disks may achieve better performance.02-09-2012
20100235563METHOD FOR ENHANCING PERFORMANCE OF A FLASH MEMORY, AND ASSOCIATED PORTABLE MEMORY DEVICE AND CONTROLLER THEREOF - A method for enhancing performance of a Flash memory includes: providing a random access memory (RAM); utilizing the RAM to temporarily store at least one virtual Flash block; and selectively moving data of the virtual Flash block to the Flash memory in order to write at least one new page in the Flash memory. An associated portable memory device and a controller thereof are also provided, where the controller includes: a read only memory (ROM) arranged to store a program code; and a microprocessor arranged to execute the program code to control the access to the Flash memory. In addition, the controller that executes the program code by utilizing the microprocessor selectively moves the data of the virtual Flash block to the Flash memory in order to write at least one new page in the Flash memory.09-16-2010
20100250833TECHNIQUES TO PERFORM POWER FAIL-SAFE CACHING WITHOUT ATOMIC METADATA - A method and system to allow power fail-safe write-back or write-through caching of data in a persistent storage device into one or more cache lines of a caching device. No metadata associated with any of the cache lines is written atomically into the caching device when the data in the storage device is cached. As such, specialized cache hardware to allow atomic writing of metadata during the caching of data is not required.09-30-2010
20100250826MEMORY SYSTEMS WITH A PLURALITY OF STRUCTURES AND METHODS FOR OPERATING THE SAME - Memory systems, such as solid state drives, and methods of operating such memory systems are disclosed, such as those adapted to provide parallel processing of data using redundant array techniques. Individual flash devices or channels containing multiple flash devices are operated as individual drives in an array of redundant drives. Ranges of physical addresses corresponding to logical addresses are provided to a host for performing read and write operations on different channels, such as to improve read variability.09-30-2010
20100250831DATA STORAGE SYSTEM MANAGER AND METHOD FOR MANAGING A DATA STORAGE SYSTEM - A data storage system manager includes one or more servers, at least one data collector deployed on at least one of the servers, at least one policy engine deployed on at least one of the servers, and at least one configuration manager deployed on at least one the servers. The at least one data collector is configured to collect resource utilization information including data storage wear rate of data storage system data storage modules. The at least one policy engine is configured to evaluate the collected information and to initiate changes to a configuration of the data storage system based on data storage wear rate and work load distribution policies. The at least one configuration manager is configured to implement the changes initiated by the at least one policy engine to control the data storage wear rate and a skew of the work load distribution within the data storage system.09-30-2010
20100250840VERSION BASED NON-VOLATILE MEMORY TRANSLATION LAYER - A non-volatile memory and erase block/data block/sector/cluster update and address translation scheme utilizing a version number is detailed that enhances data updating and helps reduce program disturb of the memory cells of the non-volatile memory device. The various embodiments utilize a version number associated with each erase block, data block, sector, and/or cluster. This allows for determination of currently valid data block, sector and/or cluster associated with the logical ID of the data grouping by locating the most recent version associated with the logical ID. With this approach, old data need not be invalidated by programming a valid/invalid flag, avoiding the risk of program disturb in the surrounding data rows.09-30-2010
20100250838PORTABLE DATA CARRIER COMPRISING A WEB SERVER - In a method for providing data for a data processing device (09-30-2010
20100250836Use of Host System Resources by Memory Controller - A method for data storage includes, in a system that includes a host having a host memory and a memory controller that is separate from the host and stores data for the host in a non-volatile memory including multiple analog memory cells, storing in the host memory information items relating to respective groups of the analog memory cells of the non-volatile memory. A command that causes the memory controller to access a given group of the analog memory cells is received from the host. In response to the command, a respective information item relating to the given group of the analog memory cells is retrieved from the host memory by the memory controller, and the given group of the analog memory cells is accessed using the retrieved information item.09-30-2010
20100250834METHOD AND SYSTEM TO PERFORM CACHING BASED ON FILE-LEVEL HEURISTICS - A method and system to perform caching based at least on one or more file-level heuristics. The caching of a storage medium in a caching device is performed by a cache policy engine. The cache policy engine receives file-level information of input/output access of data of the storage medium and caches or evicts the data of the storage medium in the caching device based on the received file-level information. By utilizing information about the files and file operations associated with the disk sectors or logical block addresses of the storage medium, the cache policy engine can make a better decision on the data selection of the storage medium to be cached in or evicted from the caching device in one embodiment of the invention. Higher cache hit rates can be achieved and the performance of the system utilizing the cache policy engine is improved.09-30-2010
20100250832STORAGE SERVICE DEVICE WITH DUAL CONTROLLER AND BACKUP METHOD THEREOF - A storage service device with a dual controller and a backup method thereof are applicable to provide the same view service to an event-login log and a configuration file of a server. The storage service device includes a first control module, a second control module, a battery unit, a basic input/output system (BIOS), and a backup procedure. Once a power failure occurs to the server, the following backup procedure is performed a hardware interrupt signal is sent to the battery unit, so as to provide an operation power to a first memory module and a second memory module; an index page of the first memory module is synchronized with that of the second memory module; and the updated index pages are recorded into a first flash memory and a second flash memory respectively.09-30-2010
20100250828CONTROL SIGNAL OUTPUT PIN TO INDICATE MEMORY INTERFACE CONTROL FLOW - Embodiments include but are not limited to apparatuses and systems including a memory array including a plurality of non-volatile memory cells, and a control signal output pin operatively coupled to the memory array. The control signal output pin may be configured to provide a control signal indicative of the memory interface control flow including, for example, an availability of the memory array for reading or writing. Other embodiments may be described and claimed.09-30-2010
20100241794NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device according to one aspect of the present invention includes: a memory cell array provided to perform programming in page units; and a control circuit provided to control the programming. The control circuit includes: means that performs a first detection for memory cells in a part provided as a unit smaller than a page, concurrently with programming to memory cells to be written in a page; and means that subjects the memory cells in the page to a second detection that takes into consideration a failure relief due to a redundant region, when the number of memory cells of unwritten state in the part as detected by the first detection becomes equal to or less than a first constant, and that ends the program operation when the number of memory cells of unwritten state in the page becomes equal to or less than a second constant.09-23-2010
20100228907METHOD OF EVENLY USING A PLURALITY OF BLOCKS OF A FLASH MEMORY, AND ASSOCIATED MEMORY DEVICE AND CONTROLLER THEREOF - A method of evenly using a plurality of blocks of a Flash memory comprises: providing at least one threshold value, which is utilized for sieving out blocks suitable for use from the plurality of blocks according to erase counts of the plurality of blocks; and by comparing erase counts of at least a portion of the plurality of blocks with the threshold value, sieving out a specific block for use from the plurality of blocks according to a purpose of use. An associated memory device and a controller thereof are also provided, where the controller comprises: a ROM arranged to store a program code, wherein the controller is provided with the at least one threshold value through the program code; and a microprocessor arranged to execute the program code to control the access to the Flash memory. The controller sieves out the specific block according to the purpose of use.09-09-2010
20100241797STORAGE DEVICE AND STORING METHOD - To enable a capacity of an entire storage device to be kept by adding a flash drive or a flash module in the flash drive for a flash memory that has a failure, even if the storage device using the flash memory has a failure in its part such as a part of flash memory chip has a failure, for example, the flash memory chip has run out of its lifetime. In a storage device equipped with two or more memory device units with a plurality of semiconductor memory devices, each of which has a functional capacity unit smaller than a capacity of an entire semiconductor memory device and has a writing lifetime for each functional capacity unit, only a functional capacity unit whose writing lifetime is run out to be determined as unable to be written is substituted by a functional capacity unit in a memory device of the other memory device unit to keep a predetermined capacity of the entire device.09-23-2010
20100146194Storage Device And Data Management Method - A storage device includes two flash memories of different flash memory types, and respectively including multiple data blocks. Each data block corresponds to a physical and a logical block address. The storage device further includes a processing module including a controller, which is capable of accessing two mapping tables respectively corresponding to the two flash memories and respectively recording the physical block addresses and the logical block addresses that correspond to the data blocks of the two flash memories. The controller is configured to determine, upon receipt of a command that contains a target logical block address therein, a selected one of the flash memories according to the target logical block address, and to locate a selected one of the physical block addresses by searching one of the mapping tables that corresponds to the selected one of the flash memories with reference to the target logical block address.06-10-2010
20100146190FLASH MEMORY STORAGE SYSTEM, AND CONTROLLER AND METHOD FOR ANTI-FALSIFYING DATA THEREOF - A flash memory storage system is provided. The flash memory storage system includes a controller having a rewritable non-volatile memory and a flash memory chip. The rewritable non-volatile memory stores a data token and the flash memory chip stores a security data and a message digest. When the security data in the flash memory chip is updated, the controller updates the data token and generates an eigenvalue, and updates the message digest according to the updated data token and the updated eigenvalue by using a one-way hash function, respectively. When the security data in the flash memory chip is processed by the controller, the controller determinates whether the security data is falsified according to the data token, the eigenvalue and the message digest. In such a way, the security data stored in the flash memory storage system can be effectively protected.06-10-2010
20100146188REPLICATED FILE SYSTEM FOR ELECTRONIC DEVICES - Disclosed is a method, system, and computer readable medium for correcting corrupted data in an embedded file system (EFS) within a non-volatile memory (NVM) system. The NVM System further includes a replicated file system (RFS). A memory comparison is performed between EFS memory sectors and corresponding RFS memory sectors to identify any RFS memory sectors that are out of sync with their corresponding EFS memory sectors. Those memory sectors that are out of sync are then erased and rewritten.06-10-2010
20100241793STORAGE SYSTEM AND METHOD FOR CONTROLLING STORAGE SYSTEM - The present invention efficiently uses the storage capacity in a storage system that has flash memory as a storage medium.09-23-2010
20100241787SENSOR PROTECTION USING A NON-VOLATILE MEMORY CELL - A method and apparatus for protecting an electrical device using a non-volatile memory cell, such as an STRAM or RRAM memory cell. In some embodiments, a memory element is connected in parallel with a sensor element, where the memory element is configured to be repetitively reprogrammable between a high resistance state and a low resistance state. The memory element is programmed to the low resistance state when the sensor element is in a non-operational state and reprogrammed to the high resistance state when the sensor element is in an operational state.09-23-2010
20100211723Memory controller, memory system with memory controller, and method of controlling flash memory - Access to flash memories is controlled so that efficiency of data writing and effective utilization of storage area go together. In the access control, priority order, for physical blocks each storing effective data, is managed so that a position of a physical block in the assignment order becomes higher according as assignment of a logical block to the physical block is performed more recently. When assigning a logical block to a free physical block, a determination is made whether a position of a previous physical block is higher than a predetermined position in the priority order. The previous physical block is a physical block, then, corresponding to the same logical block as the free physical block. When the determination is negative, effective data stored in the previous physical block is transferred to the free physical block.08-19-2010
20100235565APPARATUS AND METHOD TO PROTECT METADATA AGAINST UNEXPECTED POWER DOWN - A system includes first memory configured to store first metadata to associate logical addresses with physical addresses. Second memory is configured to include the physical addresses, to store first data based on the physical addresses, and to store portions of the first metadata when a status of a predetermined group of the physical addresses is changed. A recovery module is configured to update the first metadata based on the portions of the first metadata stored in the second memory.09-16-2010
20100235569Storage Optimization System - A method and apparatus optimizes storage on solid-state memory devices. The system aggregates object storage write requests. The system determines whether objects associated with the object storage requests that have been aggregated fit in a block of the solid-state memory device within a defined tolerance. Upon the aggregation of object storage write requests that fit in a block of the solid-state memory device, the system writes the objects associated with the aggregated object storage write requests to the solid-state memory device09-16-2010
20100235567AIRCRAFT INCLUDING DATA DESTRUCTION MEANS - The aircraft includes: 09-16-2010
20100235566FLASH MEMORY APPARATUS AND METHOD OF CONTROLLING THE SAME - Described herein is a flash memory apparatus and method controlling the same. The flash memory apparatus includes a processor and one or more flash memory units. The processor controls one or more memory operations performed in the one or more flash memory units. The processor stops controlling a memory operation in a flash memory unit when the memory operation is performed, and continues performing the memory operation in the flash memory unit when the flash memory unit generates an interrupt signal.09-16-2010
20100217926Direct Data File Storage Implementation Techniques in Flash Memories - Host system data files are written directly to a large erase block flash memory system with a unique identification of each file and offsets of data within the file but without the use of any intermediate logical addresses or a virtual address space for the memory. Directory information of where the files are stored in the memory is maintained within the memory system by its controller, rather than by the host. The file based interface between the host and memory systems allows the memory system controller to utilize the data storage blocks within the memory with increased efficiency.08-26-2010
20100217921Memory system and data processing method thereof - A method of processing data of a nonvolatile memory includes performing a randomization operation on a data unit including page data to be programmed into the nonvolatile memory and page metadata corresponding to the page data and generating a random seed; and programming the randomized data unit, and the random seed into the nonvolatile memory, the randomized data unit including the randomized page data and the randomized page metadata. The random seed is programmed within the page metadata and a position at which the random seed is programmed is based on a characteristic of the page data.08-26-2010
20100211725INFORMATION PROCESSING SYSTEM - An information processing system comprises a main memory operative to store data, and a control circuit operative to access the main memory for data. The main memory includes a nonvolatile semiconductor memory device containing electrically erasable programmable nonvolatile memory cells each using a variable resistor, and a DRAM arranged as a cache memory between the control circuit and the nonvolatile semiconductor memory device. The nonvolatile semiconductor memory device has a refresh mode of rewriting stored data. The control circuit activates the nonvolatile semiconductor memory device in said refresh mode based on the number of accesses to the nonvolatile semiconductor memory device.08-19-2010
20100211722METHOD FOR TRANSMITTING SPECIAL COMMANDS TO FLASH STORAGE DEVICE - The invention provides a data storage system. In one embodiment, the data storage system comprises a host and a flash storage device. The host sends a series of first access commands for accessing a plurality of special files to the flash storage device. The flash storage device having the stored plurality of special files and a command-symbol mapping table, sequentially generates a plurality of first digits respectively corresponding to the special files accessed by the first access commands to obtain a first data stream, converts the first data stream to a plurality of first special commands according to the command-symbol mapping table, and performs operations according to the first special commands. Each of the special files corresponds to a digit, the command-symbol mapping table records a corresponding relationship between a plurality of symbols and a plurality of special commands, and each of the symbols comprises a plurality of digits.08-19-2010
20100138592Memory device, memory system and mapping information recovering method - Disclosed is a memory device which comprises a data storing part having plural physical storage spaces; and a control part for storing data in the data storing part, wherein each of the physical storage spaces comprises a main area for storing user data at a write operation and a spare area for storing additional data other than the user data, the additional data including a logical address corresponding to a physical storage space and a link value indicating a physical storage space to be accessed next.06-03-2010
20120173793MEMORY DEVICE USING EXTENDED INTERFACE COMMANDS - A memory device includes a serial interface buffer that receives a hardware-decodable command and an extended interface command. The memory device also includes a logic module that directs the hardware-decodable command to a register for execution by a microcontroller. The logic module additionally loads a command received following the extended interface command into a sub-op-code register, wherein the logic module remains passive after loading the command received following the extended interface command into the sub-op-code register. Also included is a microcontroller that interprets the command in the sub-op-code register.07-05-2012
20100138591MEMORY SYSTEM - A memory system includes a volatile first storing unit, a nonvolatile second storing unit, and a controller. The controller stores management information of data stored in the second storing unit during a startup operation into the first storing unit and performs data management while updating the management information. The management information in a latest state stored into the first storing unit is also stored in the second storing unit. The management information includes a pre-log before and after change generated before a change occurs in the management information and a post-log, which is generated after the change occurs in the management information, concerning the change in the management information. The pre-log and the post-log are stored in the same areas of different blocks.06-03-2010
20100082888Memory controller, flash memory system with memory controller, and method of controlling flash memory - In a case where at least one of physical blocks composing the virtual block becomes a defective block, use of the virtual block to which the defective block belongs is forbidden and the virtual block of which use is forbidden is managed as a defective virtual block. Replacing the defective block with a normal block is performed among the defective virtual blocks so as to generate the virtual block to which the defective block does not belong. Then use of the virtual block generated is allowed.04-01-2010
20130219114COMBINED MOBILE DEVICE AND SOLID STATE DISK WITH A SHARED MEMORY ARCHITECTURE - A mobile device includes a system-on-chip (SOC) that includes a mobile device control module, a solid state disk (SSD) control module, and a random access memory (RAM) control module. The mobile device control module executes application programs for the mobile device. The solid-state disk (SSD) control module controls SSD operations. The RAM control module communicates with the mobile device control module and the SSD control module and stores both SSD-related data and mobile device-related data in a single RAM.08-22-2013
20100115187NON-VOLATILE DATA STORAGE SYSTEM AND METHOD THEREOF - A non-volatile data storage system including a first non-volatile storage medium, a second non-volatile storage medium, and a microprocessor is provided. The first non-volatile storage medium includes a popular data address recording area for recording logic addresses of popular data in the first non-volatile storage medium. The microprocessor is coupled to the first non-volatile storage medium and the second non-volatile storage medium. When the non-volatile data storage system boots up, the microprocessor copies the popular data from the first non-volatile storage medium to the second non-volatile storage medium according to the popular data address recording area. The popular data is accessed in the second non-volatile storage medium instead of the first non-volatile storage medium.05-06-2010
20100115178System and Method for Hierarchical Wear Leveling in Storage Devices - Systems and methods for reducing problems and disadvantages associated with wear leveling in storage devices are disclosed. A method may include maintaining module usage data associated with each of a plurality of storage device modules communicatively coupled to a channel. The method may also include maintaining device usage data associated with each of the plurality of storage devices associated with the storage device module for each of the plurality of storage device modules. The method may additionally include determining a particular storage device module of the plurality of storage device modules to which to store data associated with a write request based at least on the module usage data. The method may further include determining a particular storage device of the particular storage device module to which to store data associated with a write request based at least on the device usage data associated with the particular storage device module.05-06-2010
20110238888PROVIDING VERSIONING IN A STORAGE DEVICE - Provided are a computer program product, system and method for managing Input/Output (I/O) requests to a storage device. A write request is received having write data for a logical address in the storage device. A determination is made as to whether preserve mode is enabled. A first entry is located in a volume control table for the logical address indicating a version number of the data in the storage device for the logical address and a first physical location in the storage device having the data for the logical address. The write data is written to a second physical location in the storage device. A second entry is added to the volume control table for the logical address to write in response to determining that the preserve mode is enabled. In response to determining that the preserve mode is enabled, the volume control table is updated to have one of the first and second entry for the logical address point to the second physical location and have the version number indicate a current version and to have the first or second entry not indicating the current version to indicate the first physical location and the version number indicate a previous version.09-29-2011
20120246384FLASH MEMORY AND FLASH MEMORY ACCESSING METHOD - A flash memory accessing method is provided. The method includes: firstly, dividing the flash memory into a primary storage area and a backup storage area, wherein the difference between a first start address of the primary storage area and a second start address of the backup storage area is an offset address not equal to zero; reading the flash memory according to a address pointer equal to the first start address so as to obtain the boot data; making the electronic apparatus perform a boot sequence according to the boot data; then, detecting whether the boot sequence is normal or not, and when the boot sequence is abnormal, providing the flash memory with changing the read pointer to the second start address according to an offset address to read the backup boot data.09-27-2012
20100199021Firehose Dump of SRAM Write Cache Data to Non-Volatile Memory Using a Supercap - A mechanism is provided for firehose dumping modified data in a static random access memory of a hard disk drive to non-volatile memory of the hard disk drive during a power event. Responsive an indication of a power event in the hard disk drive, hard disk drive command processing is suspended. A token is set in the non-volatile storage indicating that flash memory in the non-volatile memory contains modified data. A portion of a static random access memory cache table containing information on the modified data in the static random access memory is copied to the flash memory. The modified data from the static random access memory is then copied to the flash memory. Responsive to a determination that the power event that initiated the copy of the modified data in the static random access memory to the flash memory is still present, the hard disk drive is shut down.08-05-2010
20120144095MEMORY SYSTEM PERFORMING INCREMENTAL MERGE OPERATION AND DATA WRITE METHOD - Disclosed is a method of executing a write operation in a nonvolatile memory system. The method includes receiving a write command indicating the write operation and write data associated with the write operation, and determining a selected merge size for use by a merge operation responsive to the write command by determining a number of free blocks and then determining a selected free block level (FBL) from among a plurality of FBLs in accordance with the number of free blocks.06-07-2012
20120144099DEVICE DRIVER DEPLOYMENT OF SIMILARITY-BASED DELTA COMPRESSION FOR USE IN A DATA STORAGE SYSTEM - A data storage caching architecture supports using native local memory such as host-based RAM, and if available, Solid State Disk (SSD) memory for storing pre-cache delta-compression based delta, reference, and independent data by exploiting content locality, temporal locality, and spatial locality of data accesses to primary (e.g. disk-based) storage. The architecture makes excellent use of the physical properties of the different types of memory available (fast r/w RAM, low cost fast read SSD, etc) by applying algorithms to determine what types of data to store in each type of memory. Algorithms include similarity detection, delta compression, least popularly used cache management, conservative insertion and promotion cache replacement, and the like.06-07-2012
20120144102FLASH MEMORY BASED STORAGE DEVICES UTILIZING MAGNETORESISTIVE RANDOM ACCESS MEMORY (MRAM) - A flash memory based storage device may utilize magnetoresistive random access memory (MRAM) as at least one of a device memory, a buffer, or high write volume storage. In some embodiments, a processor of the storage device may compare a logical block address of a data file to a plurality of logical block addresses stored in a write frequency file buffer table and causes the data file to be written to the high write volume MRAM when the logical block address of the data file matches at least one of the plurality of logical block addresses stored in the write frequency file buffer table. In other embodiments, upon cessation of power to the storage device, the MRAM buffer stores the data until power is restored, after which the processor causes the buffered data to be written to the flash memory under control of the flash memory controller.06-07-2012
20100088460MEMORY APPARATUS, SYSTEMS, AND METHODS - Memory requests for information from a processor are received in an interface device, and the interface device is coupled to a stack including two or more memory devices. The interface device is operated to select a memory device from a number of memory devices including the stack, and to retrieve some or all of the information from the selected memory device for the processor. Additional apparatus, systems and methods are disclosed.04-08-2010
20100070691Multiprocessor system having multiport semiconductor memory device and nonvolatile memory with shared bus - A multiprocessor system employing a multiport semiconductor memory device and a nonvolatile memory having a shared bus is provided. The multiprocessor system includes a first processor; a second processor; a semiconductor memory device including a shared memory area accessed in common by the first and second processors through different ports and assigned within a memory cell array, and an internal register positioned outside the memory cell array, the internal register being configured to provide an access authority for a shared bus to the first and second processors; and a nonvolatile semiconductor memory device having first and second nonvolatile memory areas coupled corresponding to the first and second processors through the shared bus, the first and second nonvolatile memory areas being accessed by and corresponding to the first and second processors according to the access authority for the shared bus.03-18-2010
20100064098Device and Method for Controlling Solid-State Memory System - A memory system includes an array of solid state memory devices which are in communication with and under the control of a controller module via a device bus with very few lines. This forms an integrated-circuit mass storage system which is contemplated to replace a mass storage system such as a disk drive memory in a computer system. Command, address and data information are serialized into component strings and multiplexed before being transferred between the controller module and the array of memory devices. The serialized information are is accompanied by a control signal to help sort out the multiplexed components. Each memory device in the array is mounted on a multi-bit mount and assigned an array address by it an array mount. An A memory device is selected by an appropriate address broadcast over the device bus, without requiring the usual dedicated select signal. A reserved array particular mount multi-bit configuration is used to unconditionally select the device mounted thereon. A reserved predefined address broadcast over the device bus deselects all previously selected memory devices. Read performance is enhanced by a read streaming technique in which while a current chunk of data is being serialized and shifted out of the memory subsystem devices to the controller module, the controller module is also setting up the address for the next chunk of data to begin to address the memory system.03-11-2010
20120144097MEMORY SYSTEM AND DATA DELETING METHOD - According to one embodiment, a memory system includes: a memory area; a transfer processing unit that stores write data received from a host apparatus in the memory area; a delete notification buffer that accumulates a delete notification; and a delete notification processing unit. The delete notification processing unit collectively reads out a plurality of delete notifications from the delete notification buffer and classifies the read-out delete notifications for each unit area. The delete notification processing unit sequentially executes, for each unit area, processing for collectively invalidating write data related to one or more delete notifications classified in a same unit area and, in executing processing for one unit area in the processing sequentially executed for the each unit area, invalidates all write data stored in the one unit area after copying write data excluding write data to be invalidated stored in the one unit area to another unit area.06-07-2012
20120144094DATA STORAGE APPARATUS AND METHOD FOR CONTROLLING FLASH MEMORY - According to one embodiment, a data storage apparatus includes a write command module, a read command module, and a controller. The write command module is configured to process a write command for writing data to the nonvolatile memories for a plurality of channels, respectively. The read command module is configured to process a read command usually and to process a read command for read modify write (RMW) operation. The controller is configured to control the read command module, causing to execute the read command for the RMW operation, prior to the normal read command, thereby to execute a flush command, and to control the write command module, causing to execute a write flush process that includes the processing of a write command for the RMW operation after the read command for the RMW operation has been executed.06-07-2012
20120144092EFFICIENT CACHE MANAGEMENT - A method of managing memory of a computing device includes providing a first memory that can be allocated as cache memory or that can be used by a computing device component. A first memory segment can be allocated as cache memory in response to a cache miss. Cache size can be dynamically increased by allocating additional first memory segments as cache memory in response to subsequent cache misses. Cache memory size can be dynamically decreased by reallocating first memory cache segments for use by computing device components. The cache memory can be a cache for a second memory accessible to the computing device. The computing device can be a mobile device. The first memory can be an embedded memory and the second memory can comprise embedded, removable or external memory, or any combination thereof. The maximum size of the cache memory scales with the size of the first memory.06-07-2012
20090327593READ-ONLY MEMORY DEVICE WITH SECURING FUNCTION AND ACCESSING METHOD THEREOF - The present invention provides a memory device and a method for accessing the memory device thereof. The memory device comprises an address encoding selector for selecting one of plurality of encoding circuits which encodes a first address into a second address, and a data decoding selector for selecting one of plurality of decoding circuits which decodes a first data corresponding to the second address into a second data and a non-volatile memory, coupled to address encoding selector and the data decoding selector, for storing the first data. The method for accessing the memory device comprises encoding a first address into a second address by an address encoding selector, and decoding a first data corresponding to the second address into a second data by a data decoding selector, wherein the first data being stored in the non-volatile memory.12-31-2009
20090327585DATA MANAGEMENT METHOD FOR FLASH MEMORY AND STORAGE SYSTEM AND CONTROLLER USING THE SAME - A data management method a flash memory storage system and a controller using the same are provided. The data management method is used for accessing a flash memory of the flash memory storage system, wherein the flash memory includes a plurality of physical blocks and the physical blocks are grouped into a data area and a spare area. The data management method includes configuring a plurality of logical blocks for be accessed by a host. The data management method also includes dividing each physical block into a plurality of physical parts and mapping the logical blocks to the physical parts. The data management method further includes accessing the mapped physical parts according to the physical blocks to be accessed by the host. Accordingly, it is possible to increase the usage and the accessing speed of the physical blocks in the flash memory storage system.12-31-2009
20090327580OPTIMIZATION OF NON-VOLATILE SOLID-STATE MEMORY BY MOVING DATA BASED ON DATA GENERATION AND MEMORY WEAR - An exemplary method includes writing data to locations in non-volatile solid-state memory and deciding whether to move data written to one location in the memory to another location in the memory based on generation of the data and wear of the other location. Such a method may be used for non-volatile random access memory (NVRAM). Various other methods, devices, systems, etc., are also disclosed.12-31-2009
20110113187SEMICONDUCTOR DEVICE AND METHOD FOR CONTROLLING THE SAME - According to one embodiment, a semiconductor device includes a NAND flash memory, an SRAM, and a controller. The NAND flash memory includes a plurality of blocks with a plurality of memory cells and a decoder which selects the blocks. The NAND flash memory is capable of erasing data in a plurality of the blocks simultaneously during a multi-block erase operation. The decoder stores bad-block information at least during a read operation and a write operation and stores information on a plurality of erase target blocks during the multi-block erase operation. The SRAM stores the information on the erase target blocks. The controller reads information on the erase target blocks from the SRAM to set the information into the decoder in a multi-block erase operation.05-12-2011
20110113185MEMORY APPARATUS AND MEMORY CONTROLLER FOR ACCESSING NON-VOLATILE MEMORY - A memory apparatus includes a non-volatile memory and a memory controller, where the memory controller is coupled to the non-volatile memory and is utilized for accessing the non-volatile memory, and the memory controller and the non-volatile memory are positioned in two independent chips, respectively. When external data is intended to be written into the non-volatile memory, the memory controller compresses the external data and stores compressed external data into the non-volatile memory.05-12-2011
20100199032ENHANCED DATA COMMUNICATION BY A NON-VOLATILE MEMORY CARD - A method of transmitting a stream of data bits from a memory card to a host device includes determining, at the memory card, a first number of data lines between the memory card and the host device, from one to a plurality of data lines. If the first number of data lines is determined to be a plurality of data lines, the method includes switching, at the memory card, the data stream between one of the first number of data lines and another of the first number of data lines after each occurrence of a second number of one or more bits of the data stream having passed toward the host device. The method also includes, if the first number of data lines is determined to be one data line, transmitting, from the memory card, the stream of data bits over the one data line to the host device.08-05-2010
20100199030METHOD OF MANAGING FLASH MEMORY ALLOCATION IN AN ELECTRONI TOKEN - The invention is a method of managing flash memory-allocation in an electronic token. Said token has a memory comprising a list area and a managed area. Said managed area comprises allocated spaces and at least one free memory chunk. Said list area comprises at least one valid entry referencing a free memory chunk. Said valid entry comprises a state field. Said method comprises the step of selecting a free memory chunk further to an allocation request where said free memory chunk is referenced by an old entry, and the step of identifying a new allocated space in the selected free memory chunk. The state field of said valid entry is preset with a virgin state. Said method comprises the step of invalidating the old entry referencing the selected free memory chunk.08-05-2010
20100199025MEMORY SYSTEM AND INTERLEAVING CONTROL METHOD OF MEMORY SYSTEM - A memory system comprising: a plurality of nonvolatile memory areas capable of operating individually; and a memory controller connected to each of the memory areas individually via a ready/busy signal for interleaving an operation in the memory areas by changing a memory area as a target of an operation command, every time the operation command is transmitted, wherein the memory controller includes a priority-level managing unit that manages a level of selection priority for each memory area, so that after transmission of an operation command, the memory controller selects a memory area with a highest level of selection priority from memory areas in a ready state, to change the selected memory area to a target of a next operation command, and shifts the level of selection priority of the selected memory area at a time of next selection to a lowest level by the priority-level managing unit.08-05-2010
20100199029Storage device, computer system, and data writing method - A storage device that includes a flash memory device providing a storage medium, a cache memory for use with the flash memory device, and a control circuit. In the storage device, based on a write command and provided address information, the control circuit selects either the flash memory device or the cache memory as a writing destination of input data.08-05-2010
20100199028Non-volatile storage device with forgery-proof permanent storage option - The invention is related to non-volatile storage devices.08-05-2010
20100199026Flash File System and Driving Method Thereof - The present invention discloses a flash file system and drive method thereof, characterized in that, after reception of an access function, it verifies the parameters in the access function and analyzes the file name of the file to be accessed included therein, then queries the starting position of the file to be accessed, and finally controls a physical driver module to access data from the flash according to the starting position and such parameters. The flash file system according to the present invention does not require FAT (File Allocation Table) file system and block interface, thereby simplifying the complexity of file system and enhancing system performance.08-05-2010
20090248964MEMORY SYSTEM AND METHOD FOR CONTROLLING A NONVOLATILE SEMICONDUCTOR MEMORY - A memory system includes a nonvolatile semiconductor memory having blocks, the block being data erasing unit; and a controller configured to execute; an update processing for; writing superseding data in a block, the superseding data being treated as valid data; and invalidating superseded data having the same logical address as the superseding data, the superseded data being treated as invalid data; and a compaction processing for; retrieving blocks having invalid data using a management tablet the management table managing blocks in a linked list format for each number of valid data included in the block; selecting a compaction source block having at least one valid data from the retrieved blocks; copying a plurality of valid data included in the compaction source blocks into a compaction target block; invalidating the plurality of valid data in the compaction source blocks; and releasing the compaction source blocks in which all data are invalidated.10-01-2009
20090276562Flash cache flushing method and system - A flash memory system that uses repeated writing of the data to achieve stable storage, is adapted for efficient cache flushing operations by utilizing a part of the non-volatile flash memory array as a designated buffer for the data, in which data integrity is retained until all repeat writing thereof is complete. Repeated writing is carried out from the designated buffer directly to the final storage locations in the flash memory array, for example using simple internal copy back operations.11-05-2009
20090327582Banded Indirection for Nonvolatile Memory Devices - Methods, apparatuses, and computer program products that enable banded indirection for nonvolatile memory devices, such as flash memory devices, are disclosed. One or more embodiments comprise a method for performing banded indirection when accessing data of a nonvolatile device. The methods comprise tracking fragmentation of a band of physical addresses of the nonvolatile memory device, storing a physical address of the band, and accessing data of a logical address of the band via the stored physical address based on the fragmentation of the band. Some embodiments comprise apparatuses for accessing data of nonvolatile devices using banded indirection. The embodiments comprise a nonvolatile memory element to store data, wherein the nonvolatile memory element has bands of physical addresses, a fragmentation detector to detect fragmentation of a band of the nonvolatile memory, and a data access module to access data of the band via a physical address based on the fragmentation.12-31-2009
20090327595STORAGE CAPACITY STATUS - In one embodiment of the present invention, a memory device is disclosed to include memory organized into blocks, each block having a status associated therewith and all of the blocks of the nonvolatile memory having collectively a capacity status associated therewith and a display for showing the capacity status even when no power is being applied to the display.12-31-2009
20090327594APPARATUS AND METHODS FOR PROGRAMMING MULTILEVEL-CELL NAND MEMORY DEVICES - Methods and apparatus are provided. A first data value is read from a first memory cell and is stored. An attempt is made to add a second data value to the first memory cell. If the attempt to add the second data value to the first memory cell is unsuccessful, the first data value and the second data value are written to one or more other memory cells.12-31-2009
20090327590ENHANCED MLC SOLID STATE DEVICE - Flash memory drives and related methods are disclosed that operate to keep frequently written data, which results in frequently erased blocks, in SLC-mimicking MLC flash, and relatively static data in normal MLC flash. A flash drive according to the present disclosure keeps track of the number of times that data for each logical block address (LBA) has been written to the flash memory, and determines whether to store newly received data associated with a particular LBA in SLC-mimicking MLC flash or in normal MLC flash depending on the number of writes that have occurred for that particular LBA. Dynamic allocation can occur between the two types of MLC. Related methods and software are also described.12-31-2009
20090327589TABLE JOURNALING IN FLASH STORAGE DEVICES - A method of table journaling in a flash storage device comprising a volatile memory and a plurality of non-volatile data blocks is provided. The method comprises the steps of creating a first copy in a first one or more of the plurality of non-volatile data blocks of an addressing table stored in the volatile memory, writing transaction log data to a second one or more of the plurality of non-volatile data blocks, and updating the first copy of the addressing table based on changes to the addressing table stored in the volatile memory after the second one or more of the plurality of non-volatile data blocks have been filled with transaction log data.12-31-2009
20090327588SOLID-STATE DISK WITH WIRELESS FUNCTIONALITY - A solid-state disk (SSD) controller includes a first integrated circuit (IC) that includes an interface module, a memory control module, and a wireless network interface module. The interface module externally interfaces the SSD controller to a computing device. The memory control module controls solid-state memory, receives data from the computing device via the interface module, and caches the data in the solid-state memory. The wireless network interface module communicates with the computing device via the interface module and allows the computing device to connect to a wireless network.12-31-2009
20090327584Apparatus and method for multi-level cache utilization - In some embodiments, a non-volatile cache memory may include a multi-level non-volatile cache memory configured to be located between a system memory and a mass storage device of an electronic system and a controller coupled to the multi-level non-volatile cache memory, wherein the controller is configured to control utilization of the multi-level non-volatile cache memory. Other embodiments are disclosed and claimed.12-31-2009
20090327583Seek Time Emulation for Solid State Drives - Methods and apparatuses for delaying execution of input/output (I/O) requests for solid state drives are contemplated. Some embodiments comprise receiving I/O requests for a solid state drive and calculating amounts of time based on characteristics of the requests, such as differences of the logical block addresses (LBAs) of the requests. The embodiments may then delay responses by the solid state drive for the requests. Calculating the amounts of time and delaying the responses by the amounts of time may allow the solid state drives to emulate the responses of various types of hard disk drives. Some embodiments comprise an apparatus for delaying execution of the I/O requests for solid state drives. The apparatuses may have numerous modules, such as a request receiver to receive the I/O requests, a calculation module to calculate the amounts of delay times, and a delay module to delay the responses of the I/O requests.12-31-2009
20090327581NAND MEMORY - Disclosed herein is a method and apparatus to refresh/rewrite the data in a NAND solid state storage device (“SSD”) only when it needs to be re-written. Upon power-up, the SSD assumes that it may have been a long time since some of its data was last written, and a background task to scan through all the data is started in the SSD. During idle periods, the entire contents of the drive is read. If a location is read and it has more than “bit error threshold” bits (for example three (3) bits if there is capability to correct eight (8) bits) in error before error correction is applied, it is assumed that this memory location is retaining the data only marginally, and the corrected data should be re-written to a new location, or alternatively re-written in the same location. The corrected data is then re-written to a new location or the same location.12-31-2009
20090327579LIMITED MEMORY POWER - Storage devices can retain information through application of a charge upon the storage device. However, applying the charge upon the storage device can be change physical characteristics of the charge and ultimately increase a likelihood of device failure. Therefore, a determination can be made on how to apply the charge based upon analysis of the device, of data for retention, and the like. Raw data can be analyzed and/or estimations can be made to determine the charge.12-31-2009
20090327578Flash Sector Seeding to Reduce Program Times - A non-volatile flash memory comprises a plurality of non-volatile memories where a first non-volatile memory is pre-programmed (erased) with all ones, and at least a second non-volatile memory is pre-programmed with a seed value that takes advantage of the reduced programming time for less than six zeros. When writing (programming) a data byte, the memory system looks up the data byte in one or more seed tables to determine a portion of non-volatile memory to which the memory system may write the data byte with a reduced programming time. The memory system then records the location of the data byte in an address translation table so the data byte may be accessed.12-31-2009
20090182935MASS STORAGE DEVICE, IN PARTICULAR OF THE USB TYPE, AND RELATED METHOD FOR TRANSFERRING DATA - A mass storage device of the present invention includes one or more memory elements and a logic module adapted to interface the one or more memory elements for exchanging data according to a data exchange protocol, in particular of the USB type, through a first port. The mass storage device has a module for detecting the presence of a power voltage associated with a first connector of the first port, and the logic module can set the storage device to either a Host or a Function device configuration depending on the detection carried out by the module for detecting the presence of a power voltage. The device also includes a second port adapted to implement a direct data exchange with further storage devices. The device additionally offers the possibility of communicating with radio or optical wireless ports exchanging data through a data bus, e.g. of the USB type.07-16-2009
20090228633Data processor - A data processor (09-10-2009
20090319723METHOD AND DEVICE FOR BINDING A NON-VOLATILE STORAGE DEVICE WITH A CONSUMER PRODUCT - A method is disclosed for binding a non-volatile storage device (12-24-2009
20080313392Data controlled power supply apparatus - A power supply, and a method of controlling the power supply, in which more or less power capacity of the power supply is activated depending on the state of a digital data signal on a data bus. The power supply has a control circuit which detects the number of “zero” bits present on the data bus, and responsively activates one or more of a plurality of power supply circuits such as charge pump circuits. The outputs of the charge pump circuits are mutually connected to a driver adapted to program memory cells of a flash memory circuit.12-18-2008
20090187702NONVOLATILE MEMORY - For a nonvolatile memory permitting electrical writing and erasing of information to be stored, such as a flash memory, the load on the system developer is to be reduced, and it is to be made possible to avoid, even if such important data for the system as management and address translation information are damaged, an abnormal state in which the system becomes unable to operate. The nonvolatile memory is provided with a replacing function to replace a group of memory cells including defective memory cells which are incapable of normal writing or erasion with a group of memory cells including no defective memory cell, a numbers of rewrites averaging function to grasp the number of data rewrites in each group of memory cells and to so perform replacement of memory cell groups that there may arise no substantial difference in the number of rewrites among a plurality of memory cell groups, and an error correcting function to detect and correct any error in data stored in the memory array, wherein first address translation information deriving from the replacing function and second address translation information deriving from the numbers of rewrites averaging function are stored in respectively prescribed areas in the memory array, and the first address translation information and second address translation information concerning the same memory cell group are stored in a plurality of sets in a time series.07-23-2009
20090319722AD HOC FLASH MEMORY REFERENCE CELLS - In a nonvolatile memory, that includes cells organized in a plurality of bit lines and a plurality of word lines, user data are stored in respective portions of each of two of the word lines. Control information is stored in a cell that is common to one of the bit lines and one of the two word lines. A cell that is common to the bit line and the other word line is used as a reference cell. A flash memory, that includes a plurality of primary cells and a plurality of spare cells, is interrogated to determine which spare cells have been used to replace respective primary cells. At least some of the other spare cells are used as reference cells.12-24-2009
20090319721FLASH MEMORY APPARATUS AND METHOD FOR OPERATING THE SAME - The invention provides a method for operating a flash memory apparatus. In one embodiment, the flash memory apparatus comprises a single-level-cell memory and a multiple-level-cell memory. First, new data for updating a logical block address is received from a host. An update count corresponding to the logical block address is then compared with a threshold value. When the update count is greater than the threshold value, it is determined whether a first physical block address corresponding to the logical block address is pointing to a multiple-level-cell block of the multiple-level-cell memory. When the first physical block address is pointing to the multiple-level-cell block, a target single-level-cell block is then selected from the single-level-cell memory. A corresponding relationship between the logical block address and a second physical block address of the target single-level-cell block is then built. The new data is then written to the target single-level-cell block with the second physical block address.12-24-2009
20090006726MULTIPLE ADAPTER FOR FLASH DRIVE AND ACCESS METHOD FOR SAME - A multiple adapter is used for assembling a plurality of flash drives. The multiple adapter includes a multiple expansion port, a detector, a file manager, and a controller. The multiple expansion port coupled to the flash drives. The detector is coupled to the multiple expansion port for detecting store information of the flash drives. The file manager is coupled to the multiple expansion port and the detector for receiving the store information and calculating total memory capacity and total spare capacity of the flash drives. The controller is used for controlling the detector and the file manager. A writing procedure and a reading procedure of an access method are also provided.01-01-2009
20110131366MEMORY MANAGEMENT UNIT AND MEMORY MANAGEMENT METHOD - According to one embodiment, a memory management unit which controls a first memory as a nonvolatile memory and a second memory as a volatile memory, the memory management unit includes, judging whether data in the first memory desired to be accessed is stored in the second memory, setting an error flag to issue error data when the data is not stored in the second memory, and reading, into a free space of the second memory, the data to be accessed in the first memory.06-02-2011
20090113114Implementation of One Time Programmable Memory with Embedded Flash Memory in a System-on-Chip - System and method for implementing one time programmable (OTP) memory using embedded flash memory. A system-on-chip (SoC) includes a cleared flash memory array that includes an OTP block, including an OTP write inhibit field that is initially deasserted, a flash memory controller, and a controller. Data are written to the OTP block, including setting the OTP write inhibit field to signify prohibition of subsequent writes to the OTP block. The SoC is power cycled, and, in response, at least a portion of the OTP block is latched in a volatile memory, including asserting an OTP write inhibit bit based on the OTP write inhibit field, after which the OTP block is not writeable. In response to each subsequent power cycling, the controller is held in reset, the latching is performed, the controller is released from reset, and the flash array, now write protected, is configured to be controlled by the controller.04-30-2009
20090113121Swappable Sets of Partial-Mapping Tables in a Flash-Memory System With A Command Queue for Combining Flash Writes - A flash controller has a flash interface accessing physical blocks of multi-level-cell (MLC) flash memory. An Extended Universal-Serial-Bus (EUSB) interface loads host commands into a command queue where writes are re-ordered and combined to reduce flash writes. A partial logical-to-physical L2P mapping table in a RAM has entries for only 1 of N sets of L2P mapping tables. The other N−1 sets are stored in flash memory and fetched into the RAM when a L2P table miss occurs. The RAM required for mapping is greatly reduced. A data buffer stores one page of host write data. Sector writes are merged using the data buffer. The data buffer is flushed to flash when a different page is written, while the partial logical-to-physical mapping table is flushed to flash when a L2P table miss occurs, when the host address is to a different one of the N sets of L2P mapping tables.04-30-2009
20100223421User device including flash memory storing index and index accessing method thereof - A user device includes a flash memory configured to store an index including a plurality of index nodes and a controller configured to control the flash memory. The controller is configured to detect a pointer ID corresponding to a selected key of a first index node, translate the detected pointer ID to an index address by using a pointer table, and access a second index node corresponding to the selected key by using the index address.09-02-2010
20100223420Memory system and data management method of flash translation layer thereof - A data management method includes determining the size of input data, storing the input data in a log block if the size of the input data is determined to be a write unit, and storing the input data in a partial block if the size of the input data is determined to be smaller than the write unit. The log block is a temporary block storing data of same addresses and the partial block is a temporary block storing data regardless of their addresses. The memory system includes a nonvolatile memory and a memory controller configured to control the nonvolatile memory. The memory controller is configured to temporarily store input data smaller than a write unit in a selected memory block even when the input data have different addresses.09-02-2010
20090138650METHOD AND APPARATUS FOR MANAGING FIRMWARE OF AN OPTICAL STORAGE APPARATUS - A method of managing a firmware includes configuring the firmware to include at least a first firmware portion with a plurality of program codes, and a second firmware portion with a plurality of parameters separately; and storing the first firmware portion and the second firmware portion in a first storage area and a second storage area of a first storage module, respectively.05-28-2009
20110238897MEMORY SYSTEM, PERSONAL COMPUTER, AND METHOD OF CONTROLLING THE MEMORY SYSTEM - According to one embodiment, a memory system includes: a nonvolatile semiconductor memory including a plurality of normal blocks and at least one dummy block, each of the normal blocks being a unit of data erasing; a writing control unit that rewrites the dummy block the number of times equal to or larger than a maximum number of times among the numbers of times of rewriting of the normal blocks; a monitor unit that monitors a data erasing time or a data writing time of the dummy block; and a wear-leveling control unit that averages the numbers of times of rewriting of the normal blocks. The memory system determines, based on a monitor result of the monitor unit, possibility of continuation of the rewriting of the normal blocks.09-29-2011
20090113120States Encoding in Multi-Bit Cell Flash Memory for Optimizing Error Rate - To store N bits of M≧2 logical pages, the bits are interleaved and the interleaved bits are programmed to [N/M] memory cells, M bits per cell. Preferably, the interleaving puts the same number of bits from each logical page into each bit-page of the [N/M] cells. When the bits are read from the cells, the bits are de-interleaved. The interleaving may be deterministic or random, and may be effected by software or by dedicated hardware.04-30-2009
20090113117RE-FLASH PROTECTION FOR FLASH MEMORY - A method for storing data includes providing a memory package including an integrated circuit containing a non-volatile memory and counter circuitry. The data is written to the non-volatile memory. The counter circuitry is operated to maintain a count of write operations performed on the non-volatile memory. The data and the count from the memory package are received at a controller, separate from the memory package, and the data is authenticated in response to the count.04-30-2009
20090113113METHOD AND APPARATUS FOR SANITIZING OR MODIFYING FLASH MEMORY CHIP DATA - A method and apparatus is provided for individually checking, sanitizing and/or otherwise altering data bits of a plurality of memory chips via one or more processes where the memory chips being processed at any given time may be of different unformatted memory capacities, may be of different memory types, and may have the process started at different times. The method utilizes a computer based program capable of multithreaded operation whereby a new procedure thread is initiated upon a determination by the main program that a given reader port is in recent initial communication with a memory chip.04-30-2009
20090113119DATA WRITING METHOD - Data are write commanded from a host into a NAND flash memory. The data are saved once in a cache memory before being written into the NAND flash memory. The cache memory includes a physical segment whose size is the product of one page sector size of the NAND flash memory and the m-th power of 2 (m is 0 or a positive integer). A CPU records and manages the data writing status for each physical segment in a sector unit.04-30-2009
20120198139STORAGE DEVICE AND DEDUPLICATION METHOD - This storage device performs deduplication of eliminating duplicated data by storing a logical address of one or more corresponding logical unit memory areas in a prescribed management information storage area of a physical unit memory area defined in the storage area provided by the flash memory chip, and executes a reclamation process of managing a use degree as the total number of the logical addresses used stored in the management information storage area and a duplication degree as the number of valid logical addresses corresponding to the physical unit memory area for each of the physical unit memory areas, and returning the physical unit memory area to an unused status when the difference of the use degree and the duplication degree exceeds a default value in the physical unit memory area.08-02-2012
20120198126METHODS AND SYSTEMS FOR PERFORMING SELECTIVE BLOCK SWITCHING TO PERFORM READ OPERATIONS IN A NON-VOLATILE MEMORY - Systems and methods are disclosed for increasing efficiency of read operations by minimizing the number of block switching events necessary to read each page associated with a read command. According to embodiments of this invention, for any given block containing one or more pages that need to be read for a read command, each of those one or more pages is read before switching to another block, thereby eliminating potential time penalties in switching between blocks. A block switching module according to embodiments of the invention instructs a NVM controller to read all relevant pages out of a given block even if an original read order sequence of the pages to be read would otherwise normally cause NVM controller to switch to another block.08-02-2012
20100223423Direct File Data Programming and Deletion in Flash Memories - Host system data files are written directly to a large erase block flash memory system with a unique identification of each file and offsets of data within the file but without the use of any intermediate logical addresses or a virtual address space for the memory. Directory information of where the files are stored in the memory is maintained within the memory system by its controller, rather than by the host. The file based interface between the host and memory systems allows the memory system controller to utilize the data storage blocks within the memory with increased efficiency.09-02-2010
20100223422Advanced Dynamic Disk Memory Module - Memory modules address the growing gap between main memory performance and disk drive performance in computational apparatus such as personal computers. Memory modules disclosed herein fill the need for substantially higher storage capacity in end-user add-in memory modules. Such memory modules accelerate the availability of applications, and data for those applications. An exemplary application of such memory modules is as a high capacity consumer memory product that can be used in Hi-Definition video recorders. In various embodiments, memory modules include a volatile memory, a non-volatile memory, and a command interpreter that includes interfaces to the memories and to various busses. The first memory acts as an accelerating buffer for the second memory, and the second memory provides non-volatile backup for the first memory. In some embodiments data transfer from the first memory to the second memory may be interrupted to provide read access to the second memory.09-02-2010
20120144101PROGRAMMING MEMORY CELLS WITH ADDITIONAL DATA FOR INCREASED THRESHOLD VOLTAGE RESOLUTION - Methods for programming memory and memory devices are provided. According to at least one such method, additional data is appended to original data and the resulting data is programmed in a selected memory cell. The appended data increases the program threshold voltage margin of the original data. The appended data can be a duplicate of the original data or logical zeros. When the selected memory cell is read, the memory control circuitry can read just the original data in the MSB field or the memory control circuitry can read the entire programmed data and ignore the LSB field, for example.06-07-2012
20110238899MEMORY SYSTEM, METHOD OF CONTROLLING MEMORY SYSTEM, AND INFORMATION PROCESSING APPARATUS - A WC resource usage is compared with an auto flush (AU) threshold Caf that is smaller than an upper limit Clmt, and when the WC resource usage exceeds the AF threshold Caf, the organizing state of a NAND memory 09-29-2011
20090049232EXECUTE-IN-PLACE IMPLEMENTATION FOR A NAND DEVICE - An Execute-In-Place (XIP) implementation in a NAND controller of the kind that controls a NAND flash memory device. A page load command is provided to a predefined block and page address in a NAND device and identifies whether the boot read request received from the processor is a continuation of a previous boot read request. A read enable pin in the NAND device is toggled if the boot read request is a continuation of the previous boot read request. A random data output command sequence is sent to the NAND device and the read enable pin is toggled if the boot read request is not a continuation of the previous boot read address.02-19-2009
20090049233Flash Memory, and Method for Operating a Flash Memory - A method for operating a flash memory is provided. The flash memory comprises a controller, a cache, and a plurality of blocks. By using a cache to preload data from the host, the buffer of the controller can be smaller than the capacity of a single block or omitted entirely. Smooth data transmission is still maintained.02-19-2009
20090106486EFFICIENT PREFETCHING AND ASYNCHRONOUS WRITING FOR FLASH MEMORY - Disclosed herein are a flash file system and an address translation method. The flash file system includes a file system, a Flash Translation Layer (FTL), and flash memory. The FTL receives Local Block Addresses (LBAs) from the file system, and translates the LBAs into Physical Block Address (PBAs. The flash memory receives the resulting PBAs. The FTL includes a memory block in which a multi-stage clustered hash table for mapping the LBAs to the PBAs is stored, and performs the address translation using the clustered hash table.04-23-2009
20100306453METHOD FOR OPERATING A PORTION OF AN EXECUTABLE PROGRAM IN AN EXECUTABLE NON-VOLATILE MEMORY - A method for operating at least a portion of an executable program in an executable non-volatile memory is described. The method includes determining, by a user input, at least a portion of an executable program for pinning in the executable non-volatile memory. The portion of the executable program is pinned to the executable non-volatile memory. The portion of the executable program is then executed from the executable non-volatile memory.12-02-2010
20100306455METHOD FOR MANAGING A PLURALITY OF BLOCKS OF A FLASH MEMORY, AND ASSOCIATED MEMORY DEVICE AND CONTROLLER THEREOF - A method for managing a plurality of blocks of a Flash memory includes: sieving out at least one first block having invalid pages from the plurality of blocks; and moving data of a portion of valid pages of the first block to a second block, where data of all valid pages of the first block is not moved to the second block at a time. An associated memory device and a controller thereof are also provided, where the controller includes: a ROM arranged to store a program code; and a microprocessor arranged to execute the program code to control the access to the Flash memory and manage the plurality of blocks. The controller that executes the program code by utilizing the microprocessor sieves out the first block from the plurality of blocks, and moves the data of the portion of valid pages of the first block to the second block.12-02-2010
20110113184DATA BACKUP METHOD FOR A FLASH MEMORY AND CONTROLLER AND STORAGE SYSTEM USING THE SAME - A data backup method for backing up data temporarily stored in a cache memory of a flash memory storage device is provided, where the flash memory storage device has a plurality of physical units. The data backup method includes logically grouping a portion of the physical units into a data area and a cache area. The data backup method also includes determining whether a trigger signal is received; and when the trigger signal is received, copying the data temporarily stored in the cache memory into the cache area. Accordingly, the data backup method can quickly write the data temporarily stored in the cache memory into the physical units, thereby preventing a time out problem which may occur in the flash memory storage device.05-12-2011
20100306456METHOD FOR EVEN UTILIZATION OF A PLURALITY OF FLASH MEMORY CHIPS - A method for addressing a memory having a plurality of flash memory chips organized in erasable blocks, which in turn contain writable sectors, and where an erase counter is associated with each memory block. The overwriting of the sectors occurs by way of alternative memory blocks searched in the same chip for low erase counter values, as long as a threshold value of the erase counter is not exceeded. The copying operations are conducted efficiently using a copy command internal to the memory chip. As soon as the threshold value is exceeded, alternative memory blocks are searched in other memory chips as well.12-02-2010
20100306451ARCHITECTURE FOR NAND FLASH CONSTRAINT ENFORCEMENT - Described embodiments provide for constraint checking for constraints imposed on NAND flash devices. An exemplary implementation of a computing environment comprises at least one NAND data storage device. In the illustrative implementation, the data processing and storage management paradigm allows for the storage of data according using a selected constraint enforcement algorithm. A NAND data storage constraint checking module can be operable to enforce one or more selected device constraints with one or more co-operating components to the NAND data store.12-02-2010
20100306450SECURE DELIVERY OF DIGITAL MEDIA VIA FLASH DEVICE - A flash device for secure delivery of media content is provided. The flash device can include a controller module and a memory module. The controller module can include at least one local central processing unit, at least one register having factory initialized data written therein, and at least one memory module interface. The factory initialized data can include: a vendor identification (“VID”) string, a product identification (“PID”) string, and a manufacturer identification string. The memory module can include at least one read-only partition having digital data disposed therein, where at least a portion of the digital data comprises at least one machine executable instruction set.12-02-2010
20100306448CACHE AUTO-FLUSH IN A SOLID STATE MEMORY DEVICE - A device, system and method in which data in a write cache, that must at some point be written to non-volatile memory, is written to non-volatile memory after expiration of a threshold time period during which no new host commands are received. If either the last dirty entry is written back or a host command is received during the write-back process, the time threshold time period and auto-flush process is restarted.12-02-2010
20100306447DATA UPDATING AND RECOVERING METHODS FOR A NON-VOLATILE MEMORY ARRAY - Methods for updating and recovering user data of a non-volatile memory array such as a flash memory are disclosed. An indication for indicating a mapping relationship for a logical address is established when original user data of the logical addresses is updated into new user data. The indication records new pointers, which record the mapping relationships between logical addresses and physical addresses storing the new user data of the logical addresses. Alternatively, the indication records memory positions of the non-volatile memory array which are defined as designated memory positions and a sequence for using these designated memory positions.12-02-2010
20090070520SEMICONDUCTOR STORAGE DEVICE AND METHOD OF CONTROLLING SEMICONDUCTOR STORAGE DEVICE - In a semiconductor storage device, a memory controller divides each of blocks in each of chips into a first page set composed of pages and a second page set composed of pages, divides a logical address space into groups, and divides each group into lines. Block units are created each of which is obtained by assembling a predetermined number of blocks from the blocks in each chip. A predetermined number of block units from the block units are managed as standard block units, and the other block units are managed as spare block units. Each standard block unit is made to correspond to one group. The corresponding group data is stored in the pages in the first page set in each block constituting the standard block unit, and unwritten pages for recording update data for the group data are provided to be included in the second page set.03-12-2009
20090037645NON-VOLATILE MEMORY DEVICE AND DATA ACCESS CIRCUIT AND DATA ACCESS METHOD - A non-volatile memory device, a data access circuit and a data access method are provided. The non-volatile memory device includes a main controller, a plurality of sub-controllers and a plurality of memory blocks. The sub-controllers are coupled to the main controller and are used to execute the tasks assigned by the main controller. The memory blocks are respectively coupled to the corresponding sub-controllers. The main controller is used to divide a received main data into a plurality of sub-data, and the sub-data are respectively saved in the memory blocks through corresponding sub-controllers. Therefore, the data access speed of the non-volatile memory device is substantially speeded-up.02-05-2009
20090037651Non-Volatile Memory and Method with Phased Program Failure Handling - In a memory with block management system, program failure in a block during a time-critical memory operation is handled by continuing the programming operation in a breakout block. Later, at a less critical time, the data recorded in the failed block prior to the interruption is transferred to another block, which could also be the breakout block. The failed block can then be discarded. In this way, when a defective block is encountered during programming, it can be handled without loss of data and without exceeding a specified time limit by having to transfer the stored data in the defective block on the spot. This error handling is especially critical for a garbage collection operation so that the entire operation need not be repeated on a fresh block during a critical time. Subsequently, at an opportune time, the data from the defective block can be salvaged by relocation to another block.02-05-2009
20090037650Function updatable device and an options card therefor - A device such as for example a electronic medical device has a memory that has prestored therein a number of programs or routines for performing various functions. Some of those functions are optional functions that were not enabled when the equipment was put into service. If the user of the equipment desires thereafter to activate any one of those optional functions, an options card that has a number of memory blocks each specifically configured to enable one of the prestored optional functions is sent to the user. The user can then insert the options card into a receptacle integrated into the device and, upon power up of the device, elect a menu for enabling the desired optional function(s) prestored in the device. The options card may be configured to have a count number that indicates the number of devices the card may be used for enabling a particular optional function. The options card may further be configured to include data that may be used to enable or disable multiple optional functions prestored in the device. When returned to the manufacturer, given that the serial numbers of the machines to which the options card was inserted are recorded therein, the manufacturer can easily keep tab of the status of those machines in the field that had had optional functions enabled/disabled.02-05-2009
20090037647SEMICONDUCTOR MEMORY CARD, METHOD FOR CONTROLLING THE SAME, AND SEMICONDUCTOR MEMORY SYSTEM - A semiconductor memory card which can be attached to a host apparatus and can be removed from the host apparatus includes a plurality of data transfer terminals, and an internal circuit transmitting a first signal to at least one first data transfer terminal comprising at least one of the data transfer terminals and transmitting a second signal to at least one second data transfer terminal comprising at least one of the data transfer terminals different from the first data transfer terminals. The second signal is generated by executing a logical operation on the first signal.02-05-2009
20090037643Semiconductor memory device including control means and memory system - A semiconductor memory device includes a first nonvolatile memory which has a first external interface and is capable of recording 1-bit data in one memory cell, a second nonvolatile memory which has a test terminal interface and is capable of recording a plurality of data in one memory cell, and a control unit which has a second external interface and is configured to control a physical state of an inside of the second nonvolatile memory.02-05-2009
20120036313METHOD FOR CONTROLLING MEMORY CARD AND METHOD FOR CONTROLLING NONVOLATILE SEMICONDUCTOR MEMORY - A method for controlling a memory card which includes a nonvolatile semiconductor memory whose memory area includes a plurality of write areas is disclosed. A first area which is a part of the plurality of write areas is set in accordance with management executed by a first file system. The first file system sequentially writes data along a direction in which addresses of the plurality of write areas increase. A second area which is a part of the plurality of write areas is set in accordance with management executed by a second file system. The second file system writes data in an order which does not depend on the addresses.02-09-2012
20100312954Multi-Chip Semiconductor Devices Having Non-Volatile Memory Devices Therein - A flash memory device and a flash memory system are disclosed. The flash memory device includes a first non-volatile memory including a plurality of page data cells, storing page data, and reading and outputting the stored page data when a read command is applied from an external portion; and a second non-volatile memory including a plurality of spare data cells respectively adjacent to the plurality of page data cells, storing spare data, scanning the spare data and temporarily storing corresponding information when a file system is mounted, reading and outputting the stored spare data when the read command is applied.12-09-2010
20100312952Multiprocessor System Having an Input/Output (I/O) Bridge Circuit for Transferring Data Between Volatile and Non-Volatile Memory - A disclosed circuit includes circuitry for coupling to a volatile memory, circuitry for coupling to a nonvolatile NAND flash memory, and circuitry that: (i) receives a volatile memory request from a processor and satisfies the volatile memory request by accessing the volatile memory, and (ii) receives a nonvolatile NOR flash memory read request from the processor and satisfies the NOR read request by accessing both the NAND flash memory and the volatile memory. The circuit may also include circuitry that receives a volatile memory request from another processor and satisfies the volatile memory request from the other processor by accessing the volatile memory, and circuitry that receives a NAND flash memory read request from the other processor and satisfies the NAND read request by accessing the NAND flash memory. Multiprocessor systems including the circuit are described, as is a method for satisfying a NOR flash memory read request.12-09-2010
20100281209Press-Push Flash Drive Apparatus With Metal Tubular Casing And Snap-Coupled Plastic Sleeve - A press-push type computer peripheral “flash drive” device includes an elongated (e.g., metal) tubular casing containing a PCBA having a plug connector. A plastic housing assembly includes front and rear cap portions mounted over the open ends of the tubular casing, and a fixed plastic sleeve portion disposed in the tubular casing. The PCBA is secured to a plastic sliding rack structure that is disposed in the tubular casing and includes an actuating button protruding through a slot formed in a wall of the tubular casing. When the actuating button is manually pushed and slid along the slot, a portion of the sliding rack structure slides against the plastic sleeve portion in deploying and retracting the USB connector out of the device.11-04-2010
20100281206METHOD OF CUSTOMIZING A MEMORY LIFESPAN MANAGEMENT POLICY IN AN ELECTRONIC TOKEN - The invention is a method of customizing a memory lifespan management policy of an electronic token. The electronic token is intended to be connected to a device able to establish a wireless channel. The electronic token has a microprocessor, a communication interface, a first memory intended to comprise said memory lifespan management policy, first means for exchanging data with a distant machine by means of a wireless channel established by said connected device, second means for applying said memory lifespan management policy in said electronic token, and third means for updating said memory lifespan management policy. Said method comprises the steps of—sending data from the distant machine to the electronic token by means of a wireless channel,—updating said memory lifespan management policy as a function of data received from said distant machine.11-04-2010
20100281205Micro Control Module For Universal Connection And Universal Connection Method Thereof - A micro control module for universal connection and a universal connection method thereof are provided. The micro control module includes a supporting interface module, a micro control unit, and a memory unit. The micro control unit is configured to read interface-setting data saved in the supporting interface module and save the interface-setting data into the memory unit. When a wireless transmission module is electrically connected to the micro control module, the micro control unit generates an identification result, selects the appropriate interface-setting data from the memory unit, and reads the corresponding initialization data from the supporting interface module, so as to initialize the wireless transmission module.11-04-2010
20110113183Method for Managing a Non-Violate Memory and Computer Readable Medium Thereof - A method for managing a non-violate memory is provided. The non-violate memory has a number of blocks, and each block has a number of sub-blocks. The method includes a number of steps. First, a last physical address is obtained. The last physical address corresponds to a sub-block which is close to another sub-block where data is newly stored. Next, it is determined, for each sub-block of at least one block, the validity of data being stored. The at least one block is at least one neighboring block of a block containing the corresponding sub-block of the last physical address. Then, a mapping table is produced according to the step of determining the validity of data.05-12-2011
20100312951METHOD, DEVICE AND DATA STRUCTURE FOR DATA STORAGE ON MEMORY DEVICES - A method is provided for storing data on memory devices comprising a plurality of erasable units, wherein the size of said erasable units is an integer multiple of a first integer value, comprising providing a data structure comprising a plurality of data units each including a data unit header, wherein the size of said data units is equal to said first integer value, a plurality of data items and corresponding data item headers within each data unit, associating at least one data unit to each erasable unit, storing said data in said data items and storing data item status information in the corresponding data item headers, and storing data unit status information in said data unit headers.12-09-2010
20100312953METHOD AND APPARATUS FOR REDUCING WRITE CYCLES IN NAND-BASED FLASH MEMORY DEVICES - A NAND-based flash memory device and a method of its operation that extends the life of the device by reducing the number of unnecessary write cycles to the device. The memory device includes blocks, pages contained by each of the blocks, and a page abstraction layer containing a look-up table for translating logical page numbers into physical page numbers. A certain number of the pages in at least one of the blocks is preferably reserved so as not to be used in default data storage mode but instead used to shuffle data within the at least one block using a dynamic page address scheme, whereby data are dynamically moved from one page to an empty page in the same block using dynamic page mapping.12-09-2010
20100312947Apparatus and method to share host system ram with mass storage memory ram - A method includes, in one non-limiting embodiment, sending a request from a mass memory storage device to a host device, the request being one to allocate memory in the host device; writing data from the mass memory storage device to allocated memory of the host device; and subsequently reading the data from the allocated memory to the mass memory storage device. The memory may be embodied as flash memory, and the data may be related to a file system stored in the flash memory. The method enables the mass memory storage device to extend its internal volatile RAM to include RAM of the host device, enabling the internal RAM to be powered off while preserving data and context stored in the internal RAM.12-09-2010
20100281203Nonvolatile Memory Device and Method for Operating the Same - A nonvolatile memory device includes a selecting unit configured to select one of a read data or a program signal indicating a program period, an output unit configured to output an output signal of the selecting unit to the outside of a chip, and an output pin connected to the output unit.11-04-2010
20100281204MEMORY SYSTEM - A memory system includes a WC 11-04-2010
20100281202WEAR-LEVELING AND BAD BLOCK MANAGEMENT OF LIMITED LIFETIME MEMORY DEVICES - Performing wear-leveling and bad block management of limited lifetime memory devices. A method for performing wear-leveling in a memory includes receiving logical memory addresses and applying a randomizing function to the logical memory addresses to generate intermediate addresses within a range of intermediate addresses. The intermediate addresses are mapped into physical addresses of a memory using an algebraic mapping. The physical addresses are within a range of physical addresses that include at least one more location than the range of intermediate addresses. The physical addresses are output for use in accessing the memory. The mapping between the intermediate addresses and the physical addresses is periodically shifted. In addition, contents of bad blocks are replaced with redundantly encoded redirection addresses.11-04-2010
20130138867Storing Multi-Stream Non-Linear Access Patterns in a Flash Based File-System - Accesses to logical pages of memory are monitored. Each logical page corresponds to a logical memory address and the accesses defining an access pattern. The logical memory addresses are logged in ordered pairs of consecutive logical pages in the access pattern. Upon receipt of a request to write data to a given logical page, a given ordered pair of consecutive logical pages containing the logical memory address of the given logical page as a first logical memory address in the ordered pair of logical memory addresses associated with that consecutive pair is obtained. A first physical memory address mapping to the first logical memory address is identified, and a second logical memory address from that identified consecutive pair. A second physical memory address mapping to the second logical memory address is identified, and the data and the second physical memory address are written to the first physical memory address.05-30-2013
20130138868SYSTEMS AND METHODS FOR IMPROVED COMMUNICATIONS IN A NONVOLATILE MEMORY SYSTEM - Systems and methods are provided for improved communications in a nonvolatile memory (“NVM”) system. The system can toggle between multiple communications channels to provide point-to-point communications between a host device and NVM dies included in the system. The host device can toggle between multiple communications channels that extend to one or more memory controllers of the system, and the memory controllers can toggle between multiple communications channels that extend to the NVM dies. Power islands may be incorporated into the system to electrically isolate system components associated with inactive communications channels.05-30-2013
20130138869NONVOLATILE MEMORY AND MEMORY DEVICE INCLUDING THE SAME - A nonvolatile memory has a first memory block including a plurality of sub memory blocks stacked in a direction perpendicular to a substrate, and a second memory block including a plurality of sub memory blocks stacked in a direction perpendicular to the substrate, the second memory block being parallel to the first memory block. Management data unchanged after it is programmed once is stored in at least one sub memory block of the first memory block and main data is stored in sub memory blocks of the second memory block. Meta data may be stored in a sub memory block of the first memory block of in any memory block that does not contain the management data.05-30-2013
20130138871Flash Memory Device and Data Access Method for Same - The invention provides a flash memory device. In one embodiment, the flash memory device is coupled to a host, and comprises a flash memory, a controller, and a random access memory. The flash memory comprises a plurality of blocks for data storage. The random access memory stores a read count table for recording read counts of the blocks. When the read counts of a plurality of original blocks are greater than a threshold according to the read count table, the controller obtains a plurality of spare blocks from the flash memory as mirror blocks respectively corresponding to the original blocks, and copies a portion of a plurality of data pages of the original blocks to the mirror blocks whenever the original blocks are read until all of the data pages of the original blocks have been copied to the mirror blocks.05-30-2013
20130138873MEMORY SYSTEMS - Memory systems having a volatile memory, a non-volatile memory arranged in blocks, and a controller coupled to the volatile memory and to the non-volatile memory. The controller is configured to maintain, in the volatile memory, a list of addresses of erased blocks of the non-volatile memory. The list of addresses of erased blocks of the non-volatile memory is limited to a maximum number of list entries. The controller is further configured to transfer the list of addresses of erased blocks of the non-volatile memory from the volatile memory to the non-volatile memory in response to the list containing its maximum number of list entries and/or in response to an operation that would increase the number of list entries to a number equal to or greater than the maximum number of list entries.05-30-2013
20130138874SYSTEMS WITH PROGRAMMABLE HETEROGENEOUS MEMORY CONTROLLERS FOR MAIN MEMORY - A translating memory module is disclosed including a printed circuit board, at least one memory integrated circuit coupled to the printed board, and at least one support chip coupled to the printed circuit board and coupled between the edge connector and the at least one memory integrated circuit. The at least one support chip includes a bi-directional translator to translate between a first memory communication protocol for the at least one memory integrated circuit and a second memory communication protocol for a memory channel differing from the first memory communication protocol. The second memory communication protocol to communicate data, address, and control signals over the memory channel bus to read and write data into the memory of the translating memory module.05-30-2013
20130138875STORING/READING SEVERAL DATA STREAMS INTO/FROM AN ARRAY OF MEMORIES - High speed mass storage devices using NAND flash memories (MDY.X) are suitable for recording and playing back a video data stream under real-time conditions, wherein the data are handled page-wise in the flash memories and are written in parallel to multiple memory buses (MBy). However, for operating with multiple independent data streams a significant buffer size is required. According to the invention, data from different data streams are collected in corresponding different buffers (FIFO 05-30-2013
20130145082MEMORY ACCESS CONTROL APPARATUS AND MEMORY ACCESS CONTROL METHOD - A memory is readable by page and erasable by block including a plurality of pages. After a read request to the memory is issued, a memory controller specifies all blocks which can be accessed based on an address specified by a read command, as candidate blocks, and specifies an inspection target page out of pages included in the candidate blocks on the basis of a predetermined rule. The memory controller inspects whether or not there is an error in the inspection target page.06-06-2013
20130145087MEMORY SYSTEM AND BLOCK MERGE METHOD - In one embodiment, the invention provides a memory system including a flash memory device including a plurality of memory blocks implementing a plurality of data blocks, a plurality of log blocks, and a plurality of free blocks. The memory system further includes a flash translation layer maintaining the number of the free blocks to be at least equal to a reference number by converting selected memory blocks among the data and log blocks into free blocks via at least one merge operation during a background period. Additionally, the flash translation layer converts selected ones of the free blocks into data and log blocks, respectively.06-06-2013
20100325349SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device, includes a plurality of flash memories and a controller for the flash memories. The flash memory includes a data cache operable to hold data for at least one record page in writing, the flash memory includes a plurality of erasure blocks each having a plurality of record pages, the record page is classified into a first record page and a second record page of which write time is longer than a write time of the first record page, and the controller for the flash memories is configured to: divide the plurality of flash memories into at least two groups; perform write control by interleaving data in the groups for each record page; determine whether a page to be written data is of the first record page or the second record page; and when it is determined that the page to be written data is the first record page, after a lapse of a first predetermined time from start of writing data of one of the groups, the controller starts writing data of another one of the groups, and when it is determined that the page to be written data is the second record page, after a lapse of a second predetermined time being longer than the first predetermined time from start of writing data of one of the groups, the controller starts writing data of another one of the groups.12-23-2010
20100325344DATA WRITING METHOD FOR FLASH MEMORY AND CONTROL CIRCUIT AND STORAGE SYSTEM USING THE SAME - A data writing method for writing data into a flash memory chip is provided, wherein the flash memory chip includes a plurality of physical units. The data writing method includes providing a flash memory control circuit and configuring a plurality of logical units, wherein each logical unit is mapped to at least one physical unit. The data writing method also includes configuring a plurality of logical addresses and mapping the logical addresses to the logical units, wherein at least one logical unit is mapped to at least two non-continuous logical addresses. The data writing method further includes writing the data from a host system into the corresponding physical units according to the logical units mapped to the logical addresses through the flash memory control circuit. Thereby, the data to be moved while writing data into the physical units is reduced, and accordingly the data writing speed is effectively increased.12-23-2010
20100325353FLASH MEMORY SYSTEM CONTROL SCHEME - A Flash memory system architecture having serially connected Flash memory devices to achieve high speed programming of data. High speed programming of data is achieved by interleaving pages of the data to be programmed amongst the memory devices in the system, such that different pages of data are stored in different memory devices. A memory controller issues program commands for each memory device. As each memory device receives a program command, it either begins a programming operation or passes the command to the next memory device. Therefore, the memory devices in the Flash system sequentially program pages of data one after the other, thereby minimizing delay in programming each page of data into the Flash memory system. The memory controller can execute a wear leveling algorithm to maximize the endurance of each memory device, or to optimize programming performance and endurance for data of any size.12-23-2010
20100325350SEMICONDUCTOR DEVICE - In executing an EEPROM emulation by a flash memory incorporated in a semiconductor device, there is a problem that the data holding period of the flash memory is shorter than the EEPROM. The flash memory manages data by block unit. Therefore, it is required to securely perform a block change before the specification of the data holding period of the flash memory passes. For satisfying this problem, for an EEPROM substitution area in a flash memory, a data level check voltage is set between an internal verification voltage and a read-out voltage. When data level becomes below the data level check voltage, the block change is performed.12-23-2010
20100325345METHOD FOR MANAGING STORAGE SYSTEM USING FLASH MEMORY, AND COMPUTER - To facilitate the management of a storage system that uses a flash memory as a storage area. A controller of the storage system provided with a flash memory chip manages a surplus capacity value of the flash memory chip, and transmits a value based on the surplus capacity value to a management server, on the basis of at least one of a definition of a parity group, a definition of an internal LU, and a definition of a logical unit. The management server displays a state of the storage system by using the received value based on the surplus capacity value.12-23-2010
20100325341Memory Device and Memory Interface - Memory devices and memory interfaces are disclosed. In an implementation a memory controller of a memory device is configured to receive a first part of an address for memory access, and to perform a memory access based on said first part and a part of a previously received address.12-23-2010
20100325340Memory Wear Control - The disclosure is related to systems and methods of controlling wear of a memory. In a particular embodiment, a system is disclosed that comprises a memory and a performance governor circuit coupled to the memory. The performance governor circuit is adapted to control a wear of the memory as a function of time.12-23-2010
20100325346PARALLEL FLASH MEMORY CONTROLLER, CHIP AND CONTROL METHOD THEREOF - A parallel flash memory controller, a chip, and a control method thereof are disclosed. First, an on-chip control bus sends flash memory control instructions in parallel to instruction parsing units (12-23-2010
20100325339STORAGE SYSTEM AND METHOD FOR CONTROLLING THE SAME - Optimum load distribution processing is selected and executed based on settings made by a user in consideration of load changes caused by load distribution in a plurality of asymmetric cores.12-23-2010
20100332742DEVICE AND METHOD FOR MONITORING AND USING INTERNAL SIGNALS IN A PROGRAMMABLE SYSTEM - The invention relates to a device for monitoring and using internal signals in a programmable system (12-30-2010
20100332731FLASH MEMORY APPARATUS AND METHOD FOR OPERATING THE SAME AND DATA STORAGE SYSTEM - A flash memory apparatus is provided. In one embodiment, the flash memory apparatus with a plurality of operation states is coupled to a host and includes a controller having an engine and a register array. A state machine logic circuit of the engine is provided for transition of the operation states and the register array provides state transition information. When a command is received from the host, the engine obtains the state transition information from the register array according to a first operation state and determines whether the valid command is one of a plurality of valid commands corresponding to the first operation state. The state machine logic circuit determines transition to the operation states according to the state transition information. The transition of the first operation state to the second operation state is performed in response to the valid command.12-30-2010
20100332739Storage device, storage controlling device, and storage controlling method - A storage device includes a programmable device into which predetermined control data is written, a control data storing unit that stores therein write control data and read control data, the write control data being control data for realizing a function to save data stored in a cache memory into a nonvolatile memory when an abnormal shut-down occurs and the read control data being control data for realizing a function to restore the data saved in the nonvolatile memory into the cache memory when an electric power source is turned on after the abnormal shut-down, a writing unit that, when an electric power source is turned on after occurrence of the abnormal shut-down of the storage device, writes the read control data into the programmable device, and a restoring instructing unit that instructs the programmable device to restore the data saved in the nonvolatile memory into the cache memory.12-30-2010
20100332736METHOD OF OPERATING NONVOLATILE MEMORY DEVICE - A method of programming a nonvolatile memory device comprises storing first data of a first memory block in a page buffer unit, and then programming the first data into a redundant memory block coupled to the page buffer unit, storing second data of a second memory block in the page buffer unit, and then programming the second data into the first memory block, storing third data of a third memory block in the page buffer unit, and then programming the third data into the second memory block, storing the second data of the first memory block in the page buffer unit, and then programming the stored second data into the third memory block, and storing the first data stored in the redundant memory block in the page buffer unit, and then programming the stored first data into the first memory block.12-30-2010
20100332740ZONED INITIALIZATION OF A SOLID STATE DRIVE - Zoned initialization of a solid state drive is provided. A solid state memory device includes a controller for controlling storage and retrieval of data to and from the device. A set of solid state memory components electrically coupled to the controller. The set is electrically divided into a first zone and a second zone, wherein the first zone is at least partially initialized independent from the second zone. An interface is coupled between the controller and the set of solid state memory components to facilitate transfer of data between the set of solid state memory components and the controller.12-30-2010
20100332738STORAGE DEVICE AND DATA PROCESSING METHOD - A storage device for connecting to a host system includes a flash memory and a controller coupled to the flash memory. The flash memory includes a plurality of memory blocks. The controller writes test data to the flash memory, and compares the test data read from the flash memory with the original test data to generate a bit error message corresponding to the flash memory. Then, the controller chooses and labels a quick read block from the plurality of memory blocks according to the bit error message, and finally writes a specific file to the quick read block.12-30-2010
20100332737FLASH MEMORY PREPROCESSING SYSTEM AND METHOD - A flash memory preprocessing system comprises at least one flash memory device, a memory controller controlling program and read operations of the at least one flash memory device, and a flash preprocessor receiving program data from an external source, generating preprocessed data by converting the received program data, and outputting the preprocessed data to the memory controller. The memory controller controls the at least one flash memory device to perform a program operation on the at least one flash memory device according to the preprocessed data.12-30-2010
20100332735FLASH MEMORY DEVICE AND METHOD FOR PROGRAMMING FLASH MEMORY DEVICE - A flash memory device resilient to bit errors and a programming method suitable for the flash memory are provided. The flash memory device stores data in a parallel manner in a superpage which is generated by grouping a plurality of physical pages into a logical page. The flash memory device spreads input data using a predetermined spreading code to generate spread data. The spread data is stored on a superpage-by-superpage basis.12-30-2010
20100332733MATERIAL SERVER AND METHOD OF STORING MATERIAL - According to one embodiment, a material server that includes a NAND flash memory which stores material that includes one or all of moving image data, audio data, and ANC data. A material ID detector detects a material ID in inputted material when such material is inputted into the material server. A block allocation unit in the material server allocates a block for storing the material each material ID. A plurality of buffers in the material server buffer the material each inputted material ID. A buffering data monitor in the material server monitors buffering data size in the buffers. A memory accessing unit in the material server writes buffered material to the NAND memory when a buffering data monitor detects that the buffering data size amounts to one page size.12-30-2010
20100332732MEMORY SYSTEMS AND MAPPING METHODS THEREOF - Memory systems and mapping methods thereof are provided. In one embodiment of a memory system, an interface device is coupled between a flash memory and a host and stores a flash translation layer. The flash translation layer utilizes a data block mapping table and a page mapping table to manage data blocks and log blocks of the flash memory by a page mapping scheme and utilizes a random write page mapping table independent from the block mapping table and the page mapping table to manage the random write blocks by a random write mapping scheme. When a first predetermined condition is satisfied, the flash translation layer converts one of the data blocks (and one of the log block corresponding to the converted data block if any) into random write block(s) and utilizes the random write mapping schemes to manage the random write block(s). When a second predetermined condition is satisfied, the flash translation layer merges and converts random write block(s) into a data block and utilizes the page mapping scheme to manage the converted random write block(s).12-30-2010
20100332730METHOD AND SYSTEM FOR MANAGING A NAND FLASH MEMORY - A method and system to facilitate paging of one or more segments of a logical-to-physical (LTP) address mapping structure to a non-volatile memory. The LTP address mapping structure is part of an indirection system map associated with the non-volatile memory in one embodiment of the invention. By allowing one or more segments of the LTP address mapping structure to be paged to the non-volatile memory, the amount of volatile memory required to store the LTP address mapping structure is reduced while maintaining the benefits of the LTP address mapping structure in one embodiment of the invention.12-30-2010
20100332729MEMORY OPERATIONS USING LOCATION-BASED PARAMETERS - Systems and methods of performing memory operations using location-based parameters are disclosed. A method includes identifying a first set of parameter values associated with a first physical block of a memory array. The first set of parameter values is identified based on a first physical location of the first physical block. A memory access operation is initiated with respect to the first physical block in accordance with the first set of parameter values.12-30-2010
20100235564SEMICONDUCTOR MEMORY DEVICE - First conversion from a logical address to a physical address is performed, and data is written in to a region in a first storage region specified by the first conversion. Second conversion from a logical address to a physical address which is different from the first conversion is performed, and data is written into a region in a second storage region specified by the second conversion. When the controller detects sequential writing having a predetermined length or more, it shifts to a first write mode that data is written into the first storage region. When the controller detects that a difference between a logical address at the end of a previous write operation and a logical address at the start of a subsequent write operation is not present in a predetermined range, it shifts to a second write mode that data is written into the second storage region.09-16-2010
20110010493NONVOLATILE STORAGE GATE, OPERATION METHOD FOR THE SAME, AND NONVOLATILE STORAGE GATE EMBEDDED LOGIC CIRCUIT, AND OPERATION METHOD FOR THE SAME - Provided is a nonvolatile storage gate embedded logic circuit embedding a nonvolatile storage gate which can hold data after power supply cutoff and can cut off a power supply at the same time shifting into a standby state. The nonvolatile storage gate embedded logic circuit includes a logic calculation unit having a logic gate, and a nonvolatile storage gate having a nonvolatile storage element, a data interface control unit disposed so as to be adjoining to the nonvolatile storage element, and receiving a nonvolatile storage control signal for data read-out from the nonvolatile storage element and data write-in to the nonvolatile storage element, and a volatile storage element disposed so as to be adjoining to the nonvolatile storage element, receiving a data input signal and a clock signal, and outputting a data output signal.01-13-2011
20110010489LOGICAL BLOCK MANAGEMENT METHOD FOR A FLASH MEMORY AND CONTROL CIRCUIT STORAGE SYSTEM USING THE SAME - A logical block management method for managing a plurality of logical blocks of a flash memory device is provided. The logical block management method includes providing a flash memory controller, grouping the logical blocks into a plurality of logical zones, wherein each logical block maps to one of the logical zones. The logical block management method also includes counting a use count value for each logical block, and dynamically adjusting mapping relations between the logical blocks and the logical zones according to the use count values. Accordingly, the logical block management method can effectively utilizing the logical zones to determine usage patterns of the logical blocks and use different mechanisms to write data, so as to increase the performance of the flash memory storage device.01-13-2011
20110010487Health Reporting From Non-Volatile Block Storage Device to Processing Device - Methods and devices are provided for adapting an I/O pattern, with respect to a processing device using a non-volatile block storage device based on feedback from the non-volatile block storage device. The feedback may include information indicating a status of the non-volatile block storage device. In response to receiving the feedback, a storage subsystem, included in an operating system executing on processing device, may change a behavior with respect to the non-volatile block storage device in order to avoid, or reduce, a negative impact to the non-volatile block storage device or to enhance an aspect of the non-volatile block storage device. The feedback may include performance information and/or operating environmental information of the non-volatile block storage device. When the non-volatile block storage device is not capable of providing the feedback, the processing device may request information about the non-volatile block storage device from a database service.01-13-2011
20110010491DATA STORAGE DEVICE - A data storage device comprising: at least two flash devices for storing data; a circuit board, wherein each of the flash devices are integrated on the circuit board; a controller integrated on the circuit board for reading and writing to each flash devices, wherein the controller interfaces each flash devices; at least one NOR Flash device in communication with the controller through a host bus; at least one host bus memory device in communication with the controller and at least one NOR Flash device through the host bus; at least one interface in communication with the controller and adapted to physically and electrically couple to a system, receive and store data therefrom and retrieve and transmit data to the system.01-13-2011
20110010485Flash Memory Control Device - A flash memory control device includes a controller and an expansion device. The expansion device is electrically connected to the controller and one and more flash memory devices for temporarily storing data, integrating data and presenting processing status, wherein the controller orders the expansion device to transform data to the one and more flash memory devices or receive data from the one and more flash memory devices according to processing status.01-13-2011
20110010490SOLID STATE DRIVE AND RELATED METHOD OF OPERATION - A solid state drive (SSD) comprises an input/output interface and a memory controller. The input/output interface stores a plurality of input/output commands. The memory controller comprises first and second input/output contexts and an input/output scheduler. The first and second input/output contexts process input/output commands from the input/output interface in an alternating sequence. The input/output scheduler schedules operations of the first and second input/output contexts. In particular, the input/output scheduler suspends execution of a first input/output command by the first input/output context upon determining that an execution time of the first input/output command exceeds an interval before a deadline time. After suspending execution of the first input/output command, the input/output scheduler transmits a second input/output command to the second input/output context.01-13-2011
20110010486REALTIME LINE OF RESPONSE POSITION CONFIDENCE MEASUREMENT - A PET event position calculation method using a combination angular and radial event map wherein identification of the radial distance of the event from the centroid of the scintillation crystal with which the event is associated as well as angular information is performed. The radial distance can be converted to a statistical confidence interval, which information can be used in downstream processing. More sophisticated reconstruction algorithms can use the confidence interval information selectively, to generate higher fidelity images with higher confidence information, and to improve statistics in dynamic imaging with lower confidence information.01-13-2011
20110016262STORAGE AND METHOD FOR PERFORMING DATA BACKUP USING THE STORAGE - A method for performing data backup using a storage device starts a backup battery when an electronic device is powered off, reads data from a memory of the electronic device by a system on chip (SoC) of the storage device, and writes the data into a field programmable gate array (FPGA) of the storage device. The method further encodes the data by the FPGA, and stores the encoded data into a flash memory of the storage device.01-20-2011
20120246391BLOCK MANAGEMENT SCHEMES IN HYBRID SLC/MLC MEMORY - A method for data storage includes storing data in a memory including multiple analog memory cells arranged in blocks. A first subset of the blocks is defined for storing first data with a first storage density, and a second subset of the blocks is defined for storing second data with a second storage density, larger than the first storage density. In each of the first and second subsets, one or more blocks are allocated to serve as spare blocks and blocks that become faulty are replaced with the spare blocks. Upon detecting that a number of the spare blocks in the second subset has decreased below a predefined threshold, the data is copied from at least one block in the second subset to the first subset, and the at least one block is added to the spare blocks of the second subset.09-27-2012
20110029724Partial Block Data Programming And Reading Operations In A Non-Volatile Memory - Data in less than all of the pages of a non-volatile memory block are updated by programming the new data in unused pages of either the same or another block. In order to prevent having to copy unchanged pages of data into the new block, or to program flags into superceded pages of data, the pages of new data are identified by the same logical address as the pages of data which they superceded and a time stamp is added to note when each page was written. When reading the data, the most recent pages of data are used and the older superceded pages of data are ignored. This technique is also applied to metablocks that include one block from each of several different units of a memory array, by directing all page updates to a single unused block in one of the units.02-03-2011
20110029722ELECTRONIC CONTROL APPARATUS INCLUDING ELECTRICALLY REWRITABLE NON-VOLATILE MEMORY - The electronic control apparatus includes an electrically rewritable non-volatile memory, a writing voltage there of being larger in absolute value than a reading voltage thereof, and a control section configured to access the non-volatile memory to perform data writing or data reading. The non-volatile memory includes a first terminal to receive the writing voltage generated by a voltage generating means disposed outside the electronic control apparatus, the first terminal being electrically isolated from the external voltage generating means.02-03-2011
20110029718METHOD AND SYSTEM TO IMPROVE THE PERFORMANCE OF A MULTI-LEVEL CELL (MLC) NAND FLASH MEMORY - A method and system to improve the performance of a multi-level cell (MLC) NAND flash memory. In one embodiment of the invention, the metadata associated with the data stored in a MLC NAND flash memory is stored only in one or more lower pages of the MLC NAND flash memory. The MLC NAND flash memory has lower and upper pages, where the lower pages have a faster programming time or rate than the upper pages in one embodiment of the invention. By storing the metadata only in the pages of the MLC NAND flash memory that have low latencies of programming, the quality of service (QoS) of the MLC NAND flash memory can be improved.02-03-2011
20110029721Cascaded combination structure of flash disks to create security function - Disclosed is a cascaded combination structure of flash disks to create security function, comprising of a plurality of data disks and a key disk. Each of the data disks includes a public zone and a private zone matched with the key disk. When the key disk is series-connected with the data disks, the private zone can be displayed and load/save by a public program in the key disk. Accordingly, there can be secured and hid the data in the private zone so that the data in the private zone is unable to be embezzled by other illegal users.02-03-2011
20110029717FLASH STORAGE DEVICE WITH FLEXIBLE DATA FORMAT - A flash storage device includes a flash storage for storing data and a controller for receiving a command containing data and selecting a sector size for the data. The controller allocates the data among data sectors having the sector size and writes the data sectors to the flash storage. In some embodiments, the controller generates system data and stores the system data in the data sectors or a system sector, or both.02-03-2011
20110029726DATA UPDATING METHOD, MEMORY SYSTEM AND MEMORY DEVICE - A data updating method, a memory system and a memory device in which the memory device is connectable to a host device and has a memory section and a memory controller, the memory section consists of a first memory section which can be divided into partitions having multiple different attributes, and a work space which is managed by the memory controller, and the method of updating data which is stored in the memory device uses one of the writing methods which has been selected from among multiple different writing methods of writing data into the partition, depending on the attribute of the partition, to perform an updating process, and can securely update the data.02-03-2011
20110029716SYSTEM AND METHOD OF RECOVERING DATA IN A FLASH STORAGE SYSTEM - A flash storage system includes a system controller that generates redundant data based on data stored in flash storage devices of the flash storage system. The system controller stores the redundant data in one or more of the flash storage devices. Additionally, the system controller identifies data that has become unavailable in one or more of the flash storage device, recovers the unavailable data based on the redundant data, and stores the recovered data into one or more other flash storage devices of the flash storage system.02-03-2011
20110029715WRITE-ERASE ENDURANCE LIFETIME OF MEMORY STORAGE DEVICES - A memory management system and method for managing memory blocks of a memory device of a computer. The system includes a free block data structure including free memory blocks for writing, and sorting the free memory blocks in a predetermined order based on block write-erase endurance cycle count and receiving new user-write requests to update existing data and relocation write requests to relocate existing data separately, a user-write block pool for receiving youngest blocks holding user-write data (i.e., any page being updated frequently) from the free block data structure, a relocation block pool for receiving oldest blocks holding relocation data (i.e., any page being updated infrequently) from the free block data structure, and a garbage collection pool structure for selecting at least one of user-write blocks and relocation blocks for garbage collection, wherein the selected block is moved back to the free block data structure upon being relocated and erased.02-03-2011
20100180068STORAGE DEVICE - A storage device realizing an improvement in rewrite endurance of a nonvolatile memory and an improvement in data transfer rate of write and read is provided including a nonvolatile memory 07-15-2010
20100161887STORAGE DEVICE, CONTROL METHOD THEREOF, AND ELECTRONIC DEVICE USING STORAGE DEVICE - According to one embodiment, a storage device includes a physical address specifying module, a logical address group specifying module, a data writer, and a storage controller. The physical address specifying module specifies a physical address of write destination of data received together with a logical address among physical addresses each representing a block group including a block of each of flash memories connected in parallel the storage area of which is divided into a plurality of blocks for each sector. The logical address group specifying module specifies a logical address group including logical addresses based on the logical address. The data writer writes data of the logical addresses to blocks in the physical address. The storage controller stores the physical address where the data is written and the logical address group from which the data is written in an address conversion map in association with each other.06-24-2010
20110035540FLASH BLADE SYSTEM ARCHITECTURE AND METHOD - A flash blade and associated methods enable improved areal density of information storage, reduced power consumption, decreased cost, increased IOPS, and/or elimination of unnecessary legacy components. In various embodiments, a flash blade comprises a host blade controller, a switched fabric, and one or more storage elements configured as flash DIMMs. Storage space provided by the flash DIMMs may be presented to a user in a configurable manner. Flash DIMMs, rather than magnetic disk drives or solid state drives, are the field-replaceable unit, enabling improved customization and cost savings.02-10-2011
20110035538NONVOLATILE MEMORY SYSTEM USING DATA INTERLEAVING SCHEME - A memory system comprises a plurality of nonvolatile memory devices configured for interleaved access. Programming times are measured and recorded for various memory cell regions of the nonvolatile memory devices, and interleaving units are formed by memory cell regions having different programming times.02-10-2011
20110213917Methods and Systems for Improving Read Performance in Data De-Duplication Storage - The present invention is directed toward methods and systems for data de-duplication. More particularly, in various embodiments, the present invention provides systems and methods for data de-duplication that may utilize a data de-duplication system that retrieves data from a data storage device in an order based on the location of blocks on the data storage device. Some embodiments break a data stream into multiple blocks of data and store the blocks of data on a data storage device of a data de-duplication system, wherein a code representing a redundant block of data is stored in place of the block of data. A location for each block of data may be stored. Additionally, the blocks may be read in an order that is determined based on the location of the blocks.09-01-2011
20110119428Method of duplicating data to multiple random accessible storage devices - A method of duplicating data to multiple random accessible storage devices has steps of reading one segment of source data having multiple segments, continuously detecting newly-connected random accessible storage devices, duplicating same segments to all connected random accessible storage devices, stopping duplicating the source data to any random accessible storage device that has stored all segments of the source data and repeating the steps from the beginning. When duplicating the source data to all connected random accessible storage devices, same segments of the source data are written to all connected random accessible storage devices. Therefore, a single writing task is proceeded in each writing session. The source data can be written to all random accessible storage devices at high speed. Consequently, efficiency of asynchronously duplicating data to multiple random accessible storage devices is increased.05-19-2011
20110119434System And Method For Safely Updating Thin Client Operating System Over A Network - A method for updating a thin client image includes the steps of writing a service operating system (OS) from a network device to limited capacity memory of a thin client device, writing a large part of a new image from the network to the memory of the thin client in a series of portions, without writing over the service OS, and writing a final small part of the new image over the service OS.05-19-2011
20110040929METHOD AND APPARATUS FOR MODIFYING DATA SEQUENCES STORED IN MEMORY DEVICE - A method of modifying data sequences in a memory system comprises receiving program data having a first data sequence, and determining whether the received first data sequence matches one of “m” predefined sequences stored in the memory system. The method further comprises replacing the received first data sequence with a replacement sequence upon determining that the received first data sequence matches one of the “m” predefined sequences, and outputting the replacement sequence from the memory system. The replacement sequence typically comprises pattern bits indicating a pattern of the first data sequence and location bits indicating a start location of the first data sequence.02-17-2011
20110040931MEMORY CONTROL METHOD AND DEVICE, MEMORY ACCESS CONTROL METHOD, COMPUTER PROGRAM, AND RECORDING MEDIUM - To dramatically increase the number of times data can be written into a flash memory.02-17-2011
20110040930Method for Accessing Flash Memory Device and Memory System Including the Same - Provided are a method for accessing a flash memory device and a memory system including the same. In the method, first and second storage regions of a memory block of the flash memory device are set to free blocks, and each of the first and second storage regions are set to a data block independently.02-17-2011
20110040926FLASH-based Memory System With Variable Length Page Stripes Including Data Protection Information - Methods and apparatuses for enhanced protection of data stored in a FLASH memory system involve a controller capable of protecting data using different size page stripes. The controller is configured to store data in FLASH memory devices in the form of page stripes, each page stripe comprising a plurality of pages of information, each page of information being stored in a different FLASH memory chip. The controller stores the data in a manner such that the pages making up each page stripe includes a plurality of data pages and at least one data protection page. In one implementation, the page stripes stored by the controller include a first page stripe having N data pages and one data protection page, and a second page stripe having M data pages and one data protection page, where N is an integer greater than three and M is an integer less than N.02-17-2011
20110040927Method and Apparatus for Performing Enhanced Read and Write Operations in a FLASH Memory System - Methods and apparatus for enhanced READ and WRITE operations in a FLASH-based solid state storage system that includes a logical to physical translation table where the logical to physical translation table can include entries associating a logical block address with one or more data identifiers, where each data identifier is associated with a data string.02-17-2011
20110040925Method and Apparatus for Addressing Actual or Predicted Failures in a FLASH-Based Storage System - Methods and apparatuses for enhanced protection of data stored in a FLASH memory system involve a controller capable of adapting to the failure of one or more FLASH memory devices in the memory system. The controller stores data in the form of page stripes, each page stripe composed of data pages, and each data page stored in a different FLASH memory device. The controller also detects failure of a FLASH memory device in which a data page of a particular page stripe is stored, reconstructs the data page, and stores the reconstructed data page in a new page stripe, where the number of data pages in the new page stripe is less than the number of data pages in the particular page stripe, and where no page of the new page stripe is stored in a memory location within the failed FLASH memory device.02-17-2011
20090193178SYSTEMS AND METHODS FOR POWER MANAGEMENT IN RELATION TO A WIRELESS STORAGE DEVICE - Various embodiments of the present invention provide systems and methods for reducing power consumption in a device including a memory system. As one example, a system may include a memory system with a hard disk drive and a flash memory. The flash memory maintains a menu file that includes a list of content objects available on the hard disk drive. In addition, the system includes a processor that executes software maintained on the memory system to update the menu file when a previously unavailable content object becomes available on the hard disk drive. Further, in some cases, the processor executes software that is operable to update the menu file when a previously available content object becomes unavailable on the hard disk drive. Additionally, the systems may include instructions executable by the processor to receive a play list, and to copy a first content object identified on the play list from the hard disk drive to the flash memory, and to copy a second content object identified on the play list from the hard disk drive to the flash memory. With the content objects thus moved to the flash memory, they can be uploaded to either the application device that supplied the play list, or to another application device designated as the recipient of the content objects.07-30-2009
20100153622Data Access Controller and Data Accessing Method - A data access controller and data accessing method is provided. The data access controller includes: a flash memory configuration register unit for storing information used for data access in a flash memory; a flash memory control unit for generating a control signal for data access to a block and a page in the flash memory according to the information used for data access stored in the flash memory configuration register unit; and a temporary memory control unit under the control of the flash memory control unit, adapted to generate a control signal for temporary storage of data. In the inventive solution, data access in the flash memory is under the control of the data access controller, thereby reducing CPU workload, improving operation speed and generality of the control on the data access in flash memory by storing the information for data access for at least one type of flash memory.06-17-2010
20110119431MEMORY SYSTEM WITH READ-DISTURB SUPPRESSED AND CONTROL METHOD FOR THE SAME - According to one embodiment, a memory system includes a memory and a controller. The memory includes NAND strings. Each of the NAND strings includes memory cells. The memory cells capable of holding data. The memory writing and reading data in units of a page corresponding to a set of the memory cells and erasing data in units of a block corresponding to a set of the NAND strings. The controller controls the memory. The controller includes a holding unit and a control unit. The holding unit holds a table in which information on a check page is recorded, for each zone corresponding to a set of the blocks. The control unit references the table to calculate a read error and instructs the memory to write the data in the block including the check page to another block in the memory, if the occurrence rate exceeds a preset threshold.05-19-2011
20110055453INTERRUPTIBLE NAND FLASH MEMORY - A NAND flash memory logical unit. The NAND flash memory logical unit includes a control circuit that responds to commands and permits program and/or erase commands to be interruptible by read commands. The control circuit includes a set of internal registers for performing the current command, and a set of external registers for receiving commands. The control circuit also includes a set of supplemental registers that allow the NAND flash memory logical unit to have redundancy to properly hold state of an interrupted program or erase command. When the interrupted program or erase command is to resume, the NAND flash memory logical unit thus can quickly resume the paused program or erase operation. This provides significant improvement to read response times in the context of a NAND flash memory logical unit.03-03-2011
20110055457METHOD FOR GIVING PROGRAM COMMANDS TO FLASH MEMORY, AND CONTROLLER AND STORAGE SYSTEM USING THE SAME - A method for giving program commands to a flash memory chip is provided, the method is suitable for writing data from a host system into the flash memory chip. In the present method, a plurality of host write commands and data corresponding to the host write commands are received from the host system by using a native command queuing (NCQ) protocol, and cache program commands are gived to the flash memory chip to write the data into the flash memory chip. Accordingly, the time for executing the host write commands is effectively shortened by writing the data through the cache program commands and the NCQ protocol.03-03-2011
20100146189Programming Non Volatile Memories - Non volatile memories and methods of programming thereof are disclosed. In one embodiment, the method of programming a memory array includes receiving a series of data blocks, each data block having a number of bits that are to be programmed, determining the number of bits that are to be programmed in a first data block, determining the number of bits that are to be programmed in a second data block, and writing the first and the second data blocks into a memory array in parallel if the sum of the number of bits that are to be programmed in the first data block and the second data block is not greater than a maximum value.06-10-2010
20100146193SYSTEM AND METHOD FOR CACHE SYNCHRONIZATION - A system for cache synchronization includes a data managing unit and a storage medium. The data managing unit is configured to control storing of data of a buffer cache of the storage medium, in response to an event signal received from a host, by classifying the data of the buffer cache into random data and sequential data. The storage medium includes a first area and a second area, and is configured to store the random data and an address information map in the first area, and to store the sequential data in the second area.06-10-2010
20100146187ENDURANCE MANAGEMENT TECHNIQUE - According to embodiments of the present invention, endurance management techniques are disclosures. Adherence to endurance and data retention ratings are ensured by managing write accesses to a memory device.06-10-2010
20110246710Encoding and Decoding to Reduce Switching of Flash Memory Transistors - Methods of encoding data to and decoding data from flash memory devices are provided. User data having an unknown ratio of 1's to 0's is received. The user data is utilized in generating transformed data that has a predictable ratio of 1's to 0's. The transformed data is stored to flash memory. The transformed data is illustratively generate by either applying an “exclusive or” function to the user data or by converting the user data into a number having a greater number of bits.10-06-2011
20110246711STORAGE CONTROLLER AND METHOD FOR CONTROLLING THE SAME - A storage controller that can maintain its performance and reduce power consumption and thereby realize large capacity and low power consumption, and a method for controlling such a storage controller are provided.10-06-2011
20110246705METHOD AND SYSTEM FOR WEAR LEVELING IN A SOLID STATE DRIVE - A method and system for wear leveling in a solid state drive by mapping the logical regions of the solid state drive that hold static content or information into the physical regions of the solid state drive that have erase counts more than an average erase count of all of the physical regions. By doing so, it allows the solid state drive to wear level itself naturally through continued usage. In one embodiment of the invention, the erase count of each physical region is incremented with every erasing operation of each physical region. The physical regions that have a high count of erase count operations are mapped with content of the logical regions with static content so that the possibility of future erase operations of these physical regions is reduced.10-06-2011
20110246702Management Of Configuration Data Using Persistent Memories Requiring Block-Wise Erase Before Rewriting - According to an aspect, the values corresponding to each group of parameters are stored in successive memory locations of a set of blocks, and pointer locations are maintained to point to the area where the groups of values are stored. When a new value is received for a parameter of a group, the values of parameters (with the new value substituted for the corresponding old value) of the group are replicated to a new set of locations in the same set of blocks if sufficient number of successive unwritten memory locations are available. A pointer data from the prior set of locations to the new set of locations is also maintained. According to another aspect, when there is insufficient space for the replication, all the present valid values of all groups are first written to a new set of blocks, and then only the earlier set of blocks are erased.10-06-2011
20110213913MEMORY SYSTEM - According to one embodiment, a memory system includes a nonvolatile memory, a managing unit, an order rule holding unit, a position information storing unit, a list selecting unit, a block selecting unit, a writing unit, and an updating unit. The managing unit holds for each of storage areas of the nonvolatile memory a free block list indicating free blocks. The order rule holding unit holds an order rule used to determine an order of the free block lists. The position information storing unit stores position information indicating the position of the free block list in the order rule. The list selecting unit selects the free block list corresponding to the position indicated by the position information and the block selecting unit selects the free block therefrom. The updating unit updates after the list selection the position information in the position information storing unit with position information indicating the position of the subsequently selected free block list.09-01-2011
20110082968NONVOLATILE MEMORY SYSTEM, AND DATA READ/WRITE METHOD FOR NONVOLATILE MEMORY SYSTEM - A nonvolatile memory system comprises a nonvolatile memory having a plurality of data areas; and a memory controller operative to control read and write operations to the nonvolatile memory. The memory controller successively executes read/write operations to plural sectors within a selected data area in the nonvolatile memory in accordance with a command and a sector count and sector address fed from a host device.04-07-2011
20110087832WEAR LEVELING IN STORAGE DEVICES BASED ON FLASH MEMORIES AND RELATED CIRCUIT, SYSTEM, AND METHOD - A wear leveling solution is proposed for use in a storage device based on a flash memory. The flash memory includes a plurality of physical blocks, which are adapted to be erased individually. A corresponding method starts with the step for erasing one of the physical blocks. One of the physical blocks being allocated for storing data is selected; this operation is performed in response to the reaching of a threshold by an indication of a difference between a number of erasures of the erased physical block and a number of erasures of the selected physical block. At least the data of the selected physical block being valid is copied into the erased physical block. The selected physical block is then erased.04-14-2011
20110087827DATA WRITING METHOD FOR A FLASH MEMORY, AND CONTROLLER AND STORAGE SYSTEM USING THE SAME - A data writing method for writing data from a host system into a flash memory chip is provided. The method includes configuring a plurality of logical page addresses, grouping the logical page addresses into a plurality of logical blocks, and recording the data dispersion degree of each of the logical blocks. The method also includes receiving write-in data from the host system, identifying a logical block that a logical page address to be written by the host system belongs to, and writing the write-in data into the flash memory chip according to the data dispersion degree of the logical block, wherein the data dispersion degree of each of the logical blocks is not larger than a logical block data dispersion degree threshold value. Accordingly, the method can effectively reduce the time for executing a host write command.04-14-2011
20110087825Electronic Device with Removable USB Flash Drive and USB Flash Drive with Added Functionality - A USB flash drive for removable connection to another device such as a cell phone, camera, computer, gaming system and photo printer, for example. In one embodiment, a cell phone having a USB port is provided wherein the USB flash drive configured to connect into a slot in the cell phone housing. A user may then quickly transfer data downloaded to the USB flash drive when connected to the cell phone, and another device such as a photo printer, for example. One or more optional additional functionality is incorporated into the USB flash drive such as, for example, a camera, internet card and MP3 player.04-14-2011
20090070519SYSTEM AND METHOD FOR SECURE DOCUMENT PROCESSING USING REMOVABLE DATA STORAGE - The subject application is directed to a system and method for secure document processing. A removable storage, such as a flash drive, magnetic storage, IC card, is installed in document processing device. A selected document processing operation, such as copying, scanning, and the like, is then performed. Data files resultant from the selected document processing operations are directed to the removable storage for being stored temporary, instead of being sent to the storage inherent to the document processing device. Data files temporary stored in the removable storage are then deleted.03-12-2009
20100138595SEMICONDUCTOR DEVICE COMPRISING FLASH MEMORY AND ADDRESS MAPPING METHOD - A semiconductor device with flash memory includes; a log type determining unit configured to select log type from among a plurality of log types with respect to a log block storing program data requested to be programmed in the flash memory and generate a control signal indicating information indicating the selected log type, and a plurality of log units configured to store program data in the log block having a corresponding log type in response to the control signal, wherein the log type determining unit converts a first type log block formed by a first log type and included in a first type log unit from among the plurality of log units into second type log block formed by a second log type and converts the log block included in a second type log unit from among the plurality of log units into the first type log blocks, the first loge type being different from the second log type.06-03-2010
20110213915NONVOLATILE STORAGE DEVICE, ACCESS DEVICE AND NONVOLATILE STORAGE SYSTEM - A nonvolatile storage device includes a nonvolatile memory that stores data and a memory controller that controls the nonvolatile memory. The memory controller accepts a pause instruction to pause writing from the access device within a period in which data from the access device are written, and writes the data received from the access device to the nonvolatile memory within a predetermined time interval, then pauses the writing and accepts read and/or write of new data from the access device.09-01-2011
20110213912MEMORY MANAGEMENT AND WRITING METHOD, AND MEMORY CONTROLLER AND MEMORY STORAGE SYSTEM USING THE SAME - A memory management and writing method for managing a memory module is provided. The memory module has a plurality of memory units and a plurality of data input/output buses corresponding to the memory units. The method includes configuring a plurality of logical units, dividing each of the logical units as a plurality of logical parts, and mapping the logical parts of each of the logical units to physical blocks of the memory units. The method also includes respectively establishing mapping tables corresponding to the data input/output buses, and only using one of the data input/output buses to write data from a host system into the corresponding memory unit according to the mapping table corresponding to the data input/output bus. Accordingly, the method can effectively increase the speed of writing data into the memory module.09-01-2011
20100153623Data Managing Method for Flash Memory and Flash Memory Device Using the Same - A data management method for a flash memory apparatus, entailing a step for handling a plurality of flash chips, a step for enabling the flash chips in sequence, and a step for updating the first data in the first block on the first flash chip among the flash chips. Additionally there is a step for updating f writing of the first new data corresponding to the first data into a second block in a second flash chip among the flash chips, and a step merging the first block and the second block, wherein both of the first new data and the first data are corresponding to a first logical block address.06-17-2010
20090307413DATA WRITING METHOD FOR FLASH MEMORY AND STORAGE SYSTEM AND CONTROLLER USING THE SAME - A data writing method for a multi-level cell (MLC) NAND flash memory and a storage system and a controller using the same are provided. The flash memory includes a plurality of blocks. Each of the blocks includes a plurality of page addresses. The page addresses are categorized into a plurality of upper page addresses and a plurality of lower page addresses. The writing speed of the lower page addresses is faster than that of the upper page addresses. The data writing method includes receiving a writing command and data and writing the data into a page address. The page address is skipped when it is an upper page address and a corresponding lower page address stores a valid data written by a previous writing command. Thereby, the accuracy of the data written by the previous writing command is ensured when a programming error occurs to the flash memory.12-10-2009
20100241786Apparatus and method for optimized NAND flash memory management for devices with limited resources - An apparatus and method for managing memory in low-end electronic devices is provided. The apparatus includes a memory management unit. The memory management unit configured to allocate a portion of random access memory and a portion of flash memory as swap areas. The memory management unit performs swapping operations by swapping pages of content between the random access memory swap area and one or more blocks of the flash memory swap area. Thereafter, a page of content can be loaded from the flash memory swap area. The memory management unit also allocates a portion of flash memory as a garbage collection area. The memory management unit transfers dirty pages from the flash swap area to the garbage collection unit to free up flash memory swap area blocks.09-23-2010
20100235568STORAGE DEVICE USING NON-VOLATILE MEMORY - According to one embodiment, a storage device includes a plurality of writable non-volatile memory devices, a buffer memory, a memory controller, and a spare non-volatile memory device. The buffer memory temporarily stores write data from a host. The memory controller writes the write data in the buffer memory to the non-volatile memory devices in a distributed manner. The memory controller writes write data in the buffer memory not having been written to the non-volatile memory devices to the spare non-volatile memory device when detecting a power down, and writes the write data having been written to the spare non-volatile memory device to the buffer memory when the power is restored.09-16-2010
20100217923STORAGE DEVICE WITH FLASH MEMORY - According to one embodiment, a write detector detects a predetermined state where a flash memory contains an area to which write data subject to a write request from a host is to be written and from which data has been erased. A data reception controller allows a data buffer to receive the requested write data in accordance with the detection of the predetermined state.08-26-2010
20100217922ACCESS MODULE, STORAGE MODULE, MUSICAL SOUND GENERATING SYSTEM AND DATA WRITING MODULE - An access module is connected to a storage module which stores multiplexed musical sound data in a non-compressed form. Based on a read request status of each sounding channel and access status of the nonvolatile storage module as a read target, a read instructing part transfers a read instruction to the storage module and reads musical sound data in parallel from the storage modules. In this musical sound generating system, since a plurality of pieces of musical sound data can be read from a plurality of nonvolatile storage modules in parallel, a sounding delay time can be made smaller than an acceptable time. For this reason, a prevailing mass NAND flash memory can be used as a memory for the musical sound data, thereby realizing a high sound quality and compact musical sound generating system.08-26-2010
20100217920Memory system and address allocating method of flash translation layer thereof - The memory system includes a flash memory and a memory controller. The flash memory has at least two addresses with different program times. The memory controller is configured to control the flash memory. The memory controller is configured to assign an address corresponding to a shorter program time from among the at least two addresses for a write operation executed at interruption of a power supply to the flash memory. The assigned address is used to store data of the memory controller in the flash memory.08-26-2010
20110082969Associative data storage devices for authentication of collectable objects - In one embodiment of the present invention, an associative data storage device for authentication of collectable objects is described. A non-volatile electronic data storage device is used in combination with at least one collectable object. The non-volatile electronic data storage device is detached from the collectable object and electronically configured to store at least one immutable digital image of at least one unique appearance characteristic of the collectable object. The data storage device is provided with tamper resistant visual markings that are associative with visual markings of the collectable object so as to provide association of the data storage device with the collectable object. The non-volatile electronic data storage device is compatible with a standard computer system for a user to view one or more digital images of the unique appearance characteristics of the collectable object for authentication and identification of the collectable object. In preferred embodiments, the non-volatile data storage device is a solid-state Flash Memory type data storage device.04-07-2011
20110179216Data Storage Device and Data Access Method - The invention provides a data access method for a flash memory. First, a write command, a write address, and target data are received from a host. A target block corresponding to the write address is then determined. Whether a storage space with the write address in the target block stores data is then determined. When the storage space does not store data, the target data is written to the storage space of the target block. When the storage space stores data, whether a file allocation table (FAT) block mapped to the target block exists in the flash memory is then determined. When the FAT block exists, the target data is written to the FAT block. When the FAT block does not exist, whether a child block mapped to the target block exists in the flash memory is determined. When the child block exists, the target data is written to the child block.07-21-2011
20110078362OPERATING AN EMULATED ELECTRICALLY ERASABLE (EEE) MEMORY - An emulated electrically erasable memory system includes a random access memory (RAM) and a non-volatile memory (NVM). A write access to the RAM is received which provides first write data and a first address, where the first write data is stored in the RAM at the first address, and a currently filling sector of the NVM is updated to store both the first write data and the first address as a first record. In response to the write access, based on whether there are any remaining active records in an oldest filled sector of the NVM, a portion of an erase process or a transfer of up to a predetermined number of active records from the oldest filled sector to the currently filling sector is performed. The predetermined number of active records is less than a maximum number of total records that may be stored within the oldest filled sector.03-31-2011
20100082889Memory controller, flash memory system with memory controller, and method of controlling flash memory - First operations and second operations are performed in parallel. The first operations are operations to write first data to a first unit area which is any one of unit areas. The second operations are operations to read second data corresponding to the same logical page as first data from one or more flash memories and write the second data to a second unit area which is any one of the unit areas and different from the first unit area. Data transfer is performed between the first unit area and the second unit area so as to form data composed of the first data and a portion of the second data which is not replaced with the first data.04-01-2010
20110087830SYSTEM, METHOD AND APPARATUS FOR EMBEDDED FIRMWARE CODE UPDATE - A wireless module is provided for wirelessly updating code to any appropriate peripheral device and may allow for wireless communication with the desired peripheral device to update an operating software code. The wireless module has the similar size, shape, and form factor as the current Memory Stick™. In one embodiment, the method of updating code to the wireless module and/or the desired peripheral devices includes providing a fail-safe code to the peripheral device, updating the peripheral device with a new code utilizing the wireless module, and executing a primary code for operation of the peripheral device. Further, the wireless module may be provided to any number of peripheral devices compatible with the Memory Stick™ removable data storage media. The wireless module is removably connected to the desired peripheral device and provides the peripheral device with a fail-safe system, method and apparatus for updating the embedded operational software code without recalling and servicing the peripheral device.04-14-2011
20110087831MEMORY SYSTEM AND METHOD OF WRITING INTO NONVOLATILE SEMICONDUCTOR MEMORY - A memory system includes a nonvolatile semiconductor memory which includes a first original block composed of n (n being natural number) write unit areas and a first subblock composed of a plurality of write unit areas. A controller writes data having one of first to p-th (p being natural number smaller than n) addresses into the first original block. The controller writes data which has a first write address of one of the first to p-th addresses into the first subblock when the controller receives request to write data having the first write address and data having the first write address exists in the first original block.04-14-2011
20110087829DATA STORAGE DEVICE AND DATA ACCESS METHOD - The invention provides a data storage device. In one embodiment, the data storage device comprises a storage medium, a random access memory, and a controller. The storage medium stores a plurality of link tables. The random access memory comprises a plurality of storage units respectively corresponding to a plurality of logical address ranges. The controller receives a target logical address from the host, determines a target link table corresponding to a logical address set comprising the target logical address, determines a target storage unit corresponding to a logical address range comprising the target logical address, determines whether the target storage unit has stored the target link table, and when the target storage unit has stored the target link table, determines a target physical address mapped to the target logical address according to a mapping relationship stored in the target link table, and accesses data stored in the storage medium according to the target physical address.04-14-2011
20110087826FLASH MEMORY ACCESSING APPARATUS AND ACCESSING METHOD THEREOF - A flash memory accessing apparatus is disclosed. The flash memory accessing apparatus includes a memory controller, a first open NAND flash interface (ONFI) and an expanding flash memory module. The first ONFI is used for connecting a main flash memory module. The memory controller obtains a detecting result by, detecting whether the main flash memory module and the expanding flash memory module are single side or double side. The memory controller further configures an accessing method of the main flash memory module and the expanding flash memory module according to the detecting result.04-14-2011
20100131702SINGLE SEGMENT DATA OBJECT MANAGEMENT - A single segment data structure and method for storing data objects employing a single segment data object having a header and a data record. The header includes a segment length field describing the length of memory reserved for the data record and the data record contains at least one data instance object. Each of the data instance objects has a data instance header and data field. The header includes a data instance state field and a data instance length field. The data instance length field contains data representing the length of the data instance data field allowing for variable length “in place” updating. The data instance state field contains data representing an object state of the instance data. Only one of the data instance objects of the data record of the single segment data object has a valid object state. The state field facilitates a power loss recovery process.05-27-2010
20100131701NONVOLATILE MEMORY DEVICE WITH PREPARATION/STRESS SEQUENCE CONTROL - Provided is a nonvolatile memory device which includes a command buffer configured to receive and store a sequence of first and second commands, a memory including an array of nonvolatile memory cells, and an operation controller configured to control the execution of first and second operations in the memory as respectively defined by the first and second commands, wherein each one of the first and second operations comprises a preparation sequence followed by a stress sequence, and execution of the preparation sequence for the second operation is parallel with the stress sequence of the first operation.05-27-2010
20100131700MEMORY INDEXING SYSTEM AND PROCESS - The invention relates to a memory index management system. The said system comprises an indexed storage memory, a memory zone containing the index and a microprocessor. The index is built in the form of a hierarchical tree structure and comprises at least two nodes. A node contains an identifier associated with a pointer that references either a node of the index or a memory zone in the storage memory. The content of a node is distributed over a first and a second memory zone that are separate in the memory zone. The first space has a first specific pointer that points to the second space and the second space has a second specific pointer whose value has a blank state.05-27-2010
20100131699METHODS, APPARATUSES, AND COMPUTER PROGRAM PRODUCTS FOR ENHANCING MEMORY ERASE FUNCTIONALITY - A method, apparatus, and computer program product are provided for enhancing memory erase functionality. An apparatus may include a block-based mass memory and a controller configured to receive an erase command from a host device comprising an indication of a location of a block in the mass memory storing memory allocation data. The controller may be further configured to access the memory allocation data based at least in part upon the indicated location. The controller may additionally be configured to determine, based at least in part upon the memory allocation data, blocks within the mass memory that have been freed by the host device. The controller may also be configured to erase the freed blocks. Corresponding methods and computer program products are also provided.05-27-2010
20100131698MEMORY SHARING METHOD FOR FLASH DRIVER - A memory sharing method for flash driver includes determining a target memory size corresponding to a target flash driver, and loading a target flash program included in the target flash driver into a stack memory allocated in a specific memory device when an unused size of the stack memory available for data storage is greater than the target memory size. Additionally, the step of determining the target memory size includes determining a specific flash program having a maximum size among a plurality of flash programs included in the target flash driver, and setting the target memory size equal to the maximum size of the specific flash program.05-27-2010
20100131697METHODS FOR TAG-GROUPING OF BLOCKS IN STORAGE DEVICES - Embodiments described herein disclose methods, devices, and media for storing data. Methods including the steps of: receiving data to be stored in a memory that includes at least three blocks, wherein each block, for storing the data, has at least one metadata value, associated with each block, that is dependent upon a writing time of each block; grouping at least three blocks into at least two block groups, wherein at least one block group contains at least two blocks; associating a respective metadata value with each block group; and associating the respective metadata value of a respective block group with each block storing the data contained in the respective block group, without storing a dedicated copy of at least one metadata value for each block. In some embodiments, at least one metadata value is stored in a block-group table.05-27-2010
20100131695Method for Utilizing a Memory Interface to Control Partitioning of a Memory Module - Apparatuses and methods for implementing partitioning in memory cards and modules where conventional memory cards or modules have only a single partition. A representative memory card/module in accordance with the invention includes a memory devices), and a memory interface which includes a data bus, a command line and a clock line. The memory card/module further includes a memory controller coupled to the memory device(s) and to the memory interface. The memory card/module includes means for controlling the partitioning of the memory device(s), and the memory controller is configured to operate the memory device(s) in accordance with the partition information.05-27-2010
20100131696System and Method for Information Handling System Data Redundancy - Flash memory integrated in a hard disk drive chassis maintains a back-up copy of data stored on the hard disk drive between back-ups of the hard disk drive data to separate storage devices. If the hard disk drive fails, the data on the flash memory provides a back-up of changes made since the previous hard disk drive back-up. When a back-up is made of data stored on the hard disk drive to an external storage device, the back-up on the flash memory device is erased to make room for subsequent back-up data. If back-up data stored on the flash memory approaches the capacity of the flash memory, a notice is provided to an end user that a back-up is needed.05-27-2010
20100262756METHOD FOR WRITING TO AND ERASING A NON-VOLATILE MEMORY - A method for writing to and erasing a non-volatile memory is described. The method includes determining the size of a command window for use in n write operations for the non-volatile memory, each write operation having the same time period. A long latency erase command is sliced by a factor of n to provide a plurality of erase slices, each erase slice having the same time period. The method further includes executing n commands to the non-volatile memory, each command composed of the combination of one of the n write operations and one of the erase slices. The total of the time period of one erase slice added to the time period of one write operation is less than or equal to the size of the command window.10-14-2010
20100037010SEMICONDUCTOR STORAGE DEVICE, METHOD OF CONTROLLING THE SAME, CONTROLLER AND INFORMATION PROCESSING APPARATUS - A semiconductor storage device includes first, second, third, fourth and fifth memory areas and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data by a first management unit in the fourth memory area, a third processing for storing data by a second management unit in the fifth memory area, a fourth processing for moving an area of the third unit to the second memory area, a fifth processing for selecting and copying data to an empty area of the third unit in the second memory area, a sixth processing for moving an area of the third unit to the third memory area, and a seventh processing for selecting and copying data to an empty area of the third unit in the third memory area.02-11-2010
20100037008APPARATUS WITH A FLASH MEMORY AND METHOD FOR WRITING DATA TO THE FLASH MEMORY THEREOF - An apparatus 02-11-2010
20100037001Flash memory based storage devices utilizing magnetoresistive random access memory (MRAM) - A flash memory based storage device may utilize magnetoresistive random access memory (MRAM) as at least one of a device memory, a buffer, or high write volume storage. In some embodiments, a processor of the storage device may compare a logical block address of a data file to a plurality of logical block addresses stored in a write frequency file buffer table and causes the data file to be written to the high write volume MRAM when the logical block address of the data file matches at least one of the plurality of logical block addresses stored in the write frequency file buffer table. In other embodiments, upon cessation of power to the storage device, the MRAM buffer stores the data until power is restored, after which the processor causes the buffered data to be written to the flash memory under control of the flash memory controller.02-11-2010
20100030947HIGH-SPEED SOLID STATE STORAGE SYSTEM - A solid state storage device includes a main memory cell array and a sub-memory area. The main memory cell array stores data in a flash memory, whereas the sub-memory includes a non-volatile random access memory for storing data. The data storage speed of the non-volatile random access memory of the sub-memory area is faster than the data storage speed of the flash memory of the main memory cell area. The sub-memory area of the solid state storage device also stores address mapping information therein, so that the address mapping information does not have to be transferred to the main memory cell area and a portion of the main memory cell area does not have to be designated for a non-volatile memory for storing the address mapping information.02-04-2010
20100057978Storage system and data guarantee method - A system according to the invention reads/writes data by using a memory device performing a wear leveling. A host 03-04-2010
20090313421Data Update Method and Electronic Device Using Such Data Update Method - A data update method is provided for updating the data stored in a memory unit of an electronic device. The data update method includes the following steps. In response to a data update request, a data content indexing table is read from the memory unit. According to the data content indexing table, position information associated with the portion of the data to be updated is computed. According to the position information, the portion of the data to be updated is updated.12-17-2009
20090313418Using asymmetric memory - In one illustrative embodiment, a computer implemented method using asymmetric memory management is provided. The computer implemented method receives a request, containing a search key, to access an array of records in the asymmetric memory, wherein the array has a sorted prefix portion and an unsorted append portion, the append portion alternatively comprising a linked-list, and responsive to a determination that the request is an insert request, inserts the record in the request in arrival order in the unsorted append portion to form a newly inserted record. Responsive to a determination that the newly inserted record completes the group of records, stores an index, in sorted order, for the group of records.12-17-2009
20100005230DATA STORING METHODS AND APPARATUS THEREOF - A data storing method for non-volatile memory is provided, wherein the non-volatile memory includes at least one memory block having a plurality of strong pages and weak pages. A logic block writing command is received for storing the corresponding writing data into the memory block. It is then determined whether the writing data is larger than one page. The writing data is divided into a plurality of page data according to the memory size of the page when the writing data is larger than one page. Next, a first storing page for each page data is determined according to a starting writing page according to the logic block writing command. And, the page data are sequentially written into the first storing pages. Note that each first storing page is a strong page within the memory block.01-07-2010
20100070690 LOAD REDUCTION DUAL IN-LINE MEMORY MODULE (LRDIMM) AND METHOD FOR PROGRAMMING THE SAME - A load reduction dual in-line memory module (LRDIMM) is similar to a registered dual in-line memory module (RDIMM) in which control signals are synchronously buffered but the LRDIMM includes a load reduction buffer (LRB) in the data path as well. To make an LRDIMM which appears compatible with RDIMMs on a system memory bus, the serial presence detector (SPD) of the LRDIMM is programmed with modified latency support and minimum delay values. When the dynamic read only memory (DRAMs) devices of the LRDIMM are subsequently set up by the host at boot time based on the parameters provided by the SPD, selected latency values are modified on the fly in an enhanced register phase look loop (RPLL) device. This has the effect of compensating for the delay introduced by the LRB without violating DRAM constraints, and provides memory bus timing for a LRDIMM that is indistinguishable from that of a RDIMM.03-18-2010
20090037652Command Queuing Smart Storage Transfer Manager for Striping Data to Raw-NAND Flash Modules - A flash module has raw-NAND flash memory chips accessed over a physical-block address (PBA) bus by a NVM controller. The NVM controller is on the flash module or on a system board for a solid-state disk (SSD). The NVM controller converts logical block addresses (LBA) to physical block addresses (PBA). Data striping and interleaving among multiple channels of the flash modules is controlled at a high level by a smart storage transaction manager, while further interleaving and remapping within a channel may be performed by the NVM controllers. A SDRAM buffer is used by a smart storage switch to cache host data before writing to flash memory. A Q-R pointer table stores quotients and remainders of division of the host address. The remainder points to a location of the host data in the SDRAM. A command queue stores Q, R for host commands.02-05-2009
20100037006NON-VOLATILE MEMORY AND CONTROLLING METHOD THEREOF - A non-volatile memory of present invention includes a number of memory blocks and a static wear leveling device. The static wear leveling device includes a memory unit for storing the erase counts of the memory blocks and a controlling unit for getting the erase counts from the memory unit, and calculating the standard deviation based on the EC, and deciding the way of the static wear leveling cycle according to the standard deviation. The controlling unit deciding the way of the static wear leveling cycle include the steps of setting at least one predetermined threshold point and judging whether the standard deviation of the erase counts is smaller than the predetermined threshold point. If the standard deviation of the erase counts is smaller than the predetermined threshold point, the static wear leveling cycle starts for a first amount of cycles and moves the static data stored a first number of memory blocks. If the standard deviation of the erase counts is bigger than the predetermined threshold point, starts for a second amount of cycles and moves the static data stored a second number of memory blocks.02-11-2010
20100037004STORAGE SYSTEM FOR BACKUP DATA OF FLASH MEMORY AND METHOD FOR THE SAME - A storage system for backup data of a flash memory includes a flash memory for storing a first file, a detector for detecting a number of accesses to the first file, and a driving unit coupled to the detector. The driving unit is used for duplicating the first file as one or more second files when the number of accesses to the first file exceeds a predetermined value, and storing the one or more first files into the flash memory. If the access number is higher than the predetermined value, which indicates this file is more likely to be accessed, the invention automatically backups this file and accesses the backup file at the next access request for fear that the file is damaged by multiple access to the same file.02-11-2010
20100037003FLASH MEMORY CONTROL APPARATUS HAVING SIGNAL-CONVERTING MODULE - A flash memory control apparatus having a signal-converting module is described. The signal-converting module includes a primary controller, a signal-converting module, a data buffer, and a secondary controller. The primary controller generates a plurality of control signals based on a first control interface. The signal-converting module receiving a reading enable signal and a writing enable signal of the control signals and converts the reading enable signal and the writing enable signal into a writing/reading signal based on a second control interface. The data buffer stores the data from the primary controller according to the first control interface and stores the data from the flash memory according to the second control interface. The secondary controller transmits the writing/reading signal, a clock signal and a data strobe signal to the flash memory based on the second control interface.02-11-2010
20100037000ONE-TIME-PROGRAMMABLE MEMORY EMULATION - This document discloses one-time-programmable (“OTP”) memory emulation and methods of performing the same. OTP memory can be emulated by managing reads and writes to a memory array in response to an instruction to write data to a OTP memory location and selectively setting a security flag that corresponds to the memory locations. The memory array can be a NAND Flash memory array that includes multiple pages of memory. The memory array can be defined by memory blocks that can include multiple pages of memory. When an OTP write instruction is received, previously stored data can be read from a first page of memory, combined with the new data and stored to a target page of memory. A security flag can be set to prevent the target page from being reprogrammed prior to an erase.02-11-2010
20100064094Memory managing method for non-volatile memory and controller using the same - A memory managing method for a non-volatile memory and a controller using the same are disclosed. The controller includes a system wear leveling member for performing a first wear leveling process in a non-volatile memory for choosing a memory unit; and a subsystem wear leveling member for performing a second wear leveling process in the chosen memory unit for selecting a block from the chosen memory unit for data programming; whereby uneven use of the blocks of the chosen memory unit is avoided.03-11-2010
20100070686METHOD AND DEVICE FOR RECONFIGURATION OF RELIABILITY DATA IN FLASH EEPROM STORAGE PAGES - A data processing system comprises a Flash memory (03-18-2010
20090216938Management Of Non-Volatile Memory Systems Having Large Erase Blocks - A non-volatile memory system of a type having blocks of memory cells erased together and which are programmable from an erased state in units of a large number of pages per block. If the data of only a few pages of a block are to be updated, the updated pages are written into another block provided for this purpose. The valid original and updated data are then combined at a later time, when doing so does not impact on the performance of the memory. If the data of a large number of pages of a block are to be updated, however, the updated pages are written into an unused erased block and the unchanged pages are also written to the same unused block. By handling the updating of a few pages differently, memory performance is improved when small updates are being made.08-27-2009
20090216937MEMORY CONTROLLER, MEMORY SYSTEM, AND ACCESS CONTROL METHOD OF FLASH MEMORY - A memory controller adds dummy data to write data by referring to instruction information about a descriptor transfer of the write data if a size of the write data to be written according to a data-write request information does not match a page size unit, thereby adjusting the size of the write data to the page size unit and then outputs the write data.08-27-2009
20090216936DATA READING METHOD FOR FLASH MEMORY AND CONTROLLER AND STORAGE SYSTEM USING THE SAME - A data reading method suitable for a flash memory storage system having a flash memory is provided, wherein the flash memory is substantially divided into a plurality of blocks and these blocks are grouped into at least a data area and a spare area. The data reading method includes: respectively determining whether the blocks in the data area are frequently read blocks; allocating a buffer storage area corresponding to the frequently read block and copying data stored in the frequently read block to the buffer storage area; and reading the data from the buffer storage area corresponding to the frequently read block when the data stored in the frequently read block is to be read. As described above, data loss caused by read disturb can be effectively prevented.08-27-2009
20100070693INITIALIZATION OF FLASH STORAGE VIA AN EMBEDDED CONTROLLER - A digital system including flash memory, coupled to a system-on-a-chip within which a flash memory subsystem controller is embedded, is disclosed. The system-on-a-chip includes support for a standard external interface, such as a Universal Serial Bus (USB) or IEEE 1394 interface, to which a host system such as flash memory test equipment can connect. Initialization of the flash memory is effected by opening a communications channel between the host system and the embedded flash memory subsystem controller. The host system can then effect initialization of the flash memory subsystem, including formatting of the flash memory arrays, loading application programs, and the like, over the communications channel.03-18-2010
20100070685METHOD FOR OPERATING MEMORY CARD - A method is used for operating a memory card, which comprises following steps: (1) a file is preloaded in the first sector of the file allocation table and the second sectors of the description block, wherein the file at least including first data, second data and third data, wherein the first sector is filled up with the first data, only one of the second sectors is not filled up with the second data and the other second sectors are filled up with the third data. (2) A command is received, where the command is capable of updating the file. (3) The command for the first sector is ignored. (4) The only one of the second sectors is updated according to the command. (5) The command for the other second sectors is ignored. (6) The second data of the only one of the second sectors are recovered.03-18-2010
20100070683METHOD TO MONITOR READ/WRITE STATUS OF FLASH MEMORY DEVICES - A method and flash memory device employing the method includes a flash memory device having a logic routine saved on the flash memory being a computer readable medium. The flash memory device generates a plurality of memory inputs and outputs. The logic routine determines a memory input and/or memory output operation, and incrementally counts memory inputs and memory outputs using a counter function of the logic routine. The logic routine determines the total number of the plurality of memory inputs and outputs using the counter function. Additionally, the logic routine generates an alert signal when the total number of the memory inputs and outputs exceeds a predetermined value programmed in the logic routine.03-18-2010
20100070682BUILT IN ON-CHIP DATA SCRAMBLER FOR NON-VOLATILE MEMORY - A non-volatile memory in which data is randomized before being stored in the non-volatile memory to minimize data pattern-related read failures. Randomizing is performed using circuitry on the memory die so that the memory die is portable relative to an external, off-chip controller. Circuitry on the memory die scrambles user data based on a key which is generated using a seed which is shifted according to a write address. Corresponding on-chip descrambling is also provided.03-18-2010
20110179217Flash Storage Device and Data Access Method of Flash Memory - The invention provides a data access method of a flash memory. First, a write command, a write address, and target data are received from a host. A target block corresponding to the write address is then determined from the flash memory. Whether a storage space corresponding to the write address in the target block has stored data therein is then determined When the storage space of the target block does not have stored data therein, the target data is written into the storage space of the target block. When the storage space of the target block does have stored data therein, whether a child block mapped to the target block exists in the flash memory is determined. When the child block exists in the flash memory, the target data is written into the child block.07-21-2011
20110179215PROGRAMMABLE READ PREAMBLE - The subject systems and/or methods relate to a high speed memory device that enables a preamble pattern to be updated after manufacture. A high speed memory device can include a FLASH module and a RAM module. The FLASH module can include an initial preamble pattern, wherein the initial preamble pattern is loaded during a power-up of the high speed memory. The RAM module can include a default preamble pattern, wherein the default preamble pattern is loaded after the power-up of the high speed memory. The initial preamble pattern or the default preamble pattern can be defined by a manufacture of the high speed memory or an OEM of the high speed memory. Additionally, the initial preamble pattern or the default preamble pattern can be updated with a customized preamble pattern based upon a target environment.07-21-2011
20100064096SYSTEMS AND METHODS FOR TEMPORARILY RETIRING MEMORY PORTIONS - Flash memory apparatus including a plurality of memory portions, and a controller operative to reserve for data retention purposes, for at least a first duration of time, only certain portions from among said plurality of memory portions including allocating data, during the first duration of time, only to the certain portions, thereby to define at least one of the plurality of memory portions other than the certain portions as a retired memory portion for the first duration of time.03-11-2010
20100064095Flash memory system and operation method - The present invention discloses a flash memory system comprising: a cache memory, a cache memory interface, a host interface, a flash memory interface, and a microprocessor The cache memory interface contains an arbitrator for performing data bus bandwidth time sharing process to access the cache memory The host interface is used for receiving data from a host system, and storing the data into the cache memory to form ready data The flash memory interface reads the ready data from the cache memory and stores it into at least one flash memory The microprocessor is used for controlling the host interface and the flash memory interface to access the cache memory Hence, the present invention can achieve the purpose of enhancing the access efficiency and increasing the life of the flash memory03-11-2010
20100064092INTERFACE FOR WRITING TO MEMORIES HAVING DIFFERENT WRITE TIMES - An interface between memories having different write times is described. The interface includes a latch for capturing address and data information during a memory access by a processor of a first memory device. The interface also includes an index counter for providing frame management. The interface also includes a variable identity array logic for determining what data is to be written into a second memory device and address generation logic to determine where the data is to be stored in the second memory device. Additionally, the interface includes data validity logic to ensure that the data being written into the second memory device is valid. As a result, the processor can operate in substantially real time and can restore itself after detecting an event upset using the data stored in the second memory device.03-11-2010
20100064097FLASH MEMORY STORAGE SYSTEM - A flash memory storage system has a plurality of flash memory devices comprising a plurality of flash memories, and a controller having an I/O processing control unit for accessing a flash memory device specified by a designated access destination in an I/O request received from an external device from among the plurality of flash memory devices. A parity group can be configured of flash memory devices having identical internal configuration.03-11-2010
20100070684MEMORY DEVICE AND OPERATING METHOD THEREOF - A memory device preloads a command file and a plurality of response files. Whenever a host sends a command to the memory apparatus, the command assigns one of the response files; thereby the host can receive response of the memory apparatus by reading the assigned response file.03-18-2010
20100057977REDUCED-POWER PROGRAMMING OF MULTI-LEVEL CELL (MLC) MEMORY - In one embodiment, a mobile electronic device has a host controller, an energy-saving encoder, an energy-saving decoder, and a multi-level cell (MLC) NAND flash memory. The host controller provides raw user data to the energy-saving encoder in k-bit segments. The energy-saving encoder encodes each k-bit segment into an n-bit segment of encoded user data for programming the MLC NAND flash memory as a p-symbol codeword, where (i) k is smaller than n (ii) p(=n/log03-04-2010
20100070688FLASH MEMORY DEVICE AND METHOD FOR WRITING DATA THERETO - The invention provides a flash memory device. In one embodiment, the flash memory device is coupled to a host, and comprises a multiple-level-cell (MLC) flash memory and a controller. The MLC flash memory comprises a turbo area and a normal area, wherein the turbo area comprises a plurality of first blocks, the normal area comprises a plurality of second blocks, and each of the first blocks and the second blocks comprises a plurality of pages, wherein the pages of the first blocks and the second blocks are divided into strong pages with high data endurance and weak pages with low data endurance. The controller receives data to be written to the MLC flash memory from the host, determines whether the data is important data, and writes the data to the strong pages of the first blocks of the turbo area when the data is important data.03-18-2010
20100070687PROCEDURE FOR ACCESSING A NON-VOLATILE WATCH MEMORY - The invention relates to a procedure for accessing a non-volatile watch memory, the watch comprising two supply terminals accessible from the outside that define a potential difference corresponding to a standard supply voltage, and a control circuit of the non-volatile memory produced using a technology supporting a predefined maximum supply voltage, the access procedure consisting of transmitting the following to the control circuit of the non-volatile memory by means of a supply terminal of the watch: a) an opening key to authorise access to the non-volatile memory; b) an instruction for access to the non-volatile memory; the procedure being characterised in that the opening key is a predefined instruction transmitted by modulation of the standard supply voltage such that this does not exceed the predefined maximum supply voltage.03-18-2010
20100057976MULTIPLE PERFORMANCE MODE MEMORY SYSTEM - A method and system for controlling a write performance level of a memory is disclosed. The method includes receiving an input at the memory, and configuring the memory to an operation mode providing a write performance level and a storage capacity. The input may specify a storage capacity, a working area capacity, a write performance level, and/or a ratio of the storage capacity to the working area capacity. A desired write performance level may be set by receiving a software command or hardware setting. The storage capacity may be varied depending on whether the memory device has been formatted. As the storage capacity decreases, working area capacity of the memory device increases and write performance increases. Conversely, as the storage capacity increases, working area capacity decreases and write performance decreases.03-04-2010
20110093651DATA STORAGE APPARATUS AND CONTROLLING METHOD OF THE DATA STORAGE APPARATUS - According to one embodiment, a data storage apparatus includes a first nonvolatile storage, a second nonvolatile storage and a controller. The controller is configured to control data writing and data reading for the first and second nonvolatile storage. The controller includes an allocation control module. The allocation control module is configured to allocate part of a storage area of the first nonvolatile storage to a logical address space and to allocate part or all of a storage area of the second nonvolatile storage to the logical address space in order to use the part of the storage area of the first nonvolatile storage allocated to the logical address space as storage area of substantial data, and to use part or whole of a remaining part of the storage area of the first nonvolatile storage not allocated to the logical address space as nonvolatile cache for the second nonvolatile storage.04-21-2011
20110107016SOLID STATE STORAGE SYSTEMS AND METHODS FOR FLEXIBLY CONTROLLING WEAR LEVELING - Solid-state storage systems and methods are provided for controlling a wear leveling process for uniform use of the memory cells that replaces worn memory blocks with less frequently used memory blocks. The wear leveling process is performed by changing the physical locations of the storage cells within each memory zone or plane. Reference values of target memory block erase counts and worn memory block erase counts are used for searching target memory blocks to be used as replacements.05-05-2011
20100057980DATA MEMORY DEVICE WITH AUXILIARY FUNCTION - The invention relates to a method, a data storage device, and a system with a data storage device having an additional module (03-04-2010
20110087823APPARATUS AND METHOD FOR PRODUCING IDS FOR INTERCONNECTED DEVICES OF MIXED TYPE - A plurality of memory devices of mixed type (e.g., DRAMs, SRAMs, MRAMs, and NAND-, NOR-, AND-type Flash memories) are serially interconnected. Each device has device type information on its device type. A specific device type (DT) and a device identifier (ID) contained in a serial input are fed to one device of the serial interconnection configuration. The device determines whether the fed DT matches the DT of the device. In a case of match, a calculator included in the device performs calculation to generate an ID for another device and the fed ID is latched in a register of the device. The generated ID is transferred to another device of the serial interconnection. In a case of no match, the ID generation is skipped and no ID is generated for another device. Such a device type match determination and ID generation or skip are performed in all devices of the serial interconnection.04-14-2011
20100241791CONTROLLER WHICH CONTROLS OPERATION OF NONVOLATILE SEMICONDUCTOR MEMORY AND SEMICONDUCTOR MEMORY DEVICE INCLUDING NONVOLATILE SEMICONDUCTOR MEMORY AND CONTROLLER THEREFORE - A controller includes an instruction table memory, a program counter, a first decoder, and a first executing unit. The instruction table memory stores an instruction code obtained by coding a sequence to access a nonvolatile semiconductor memory. A read address in the instruction table memory is set to the program counter. The first decoder decodes the instruction code read from the instruction table memory to output a first decode signal. The first executing unit executes access to the nonvolatile semiconductor memory on the basis of the first decode signal output from the first decoder.09-23-2010
20110252190Apparatus, System, and Method for Managing Data From a Requesting Device with an Empty Data Token Directive - An apparatus, system, and method are disclosed for managing data with an empty data segment directive at the requesting device. The apparatus, system, and method include a token directive generation module and a token directive transmission module. The token directive generation module generates a storage request with a token directive. The token directive includes a request to store on the storage device a data segment token. The token directive substitutes for a series of repeated, identical characters or a series of repeated, identical character strings to be stored as a data segment. The token directive includes at least a data segment identifier and a data segment length. The data segment token and the token directive are substantially free from data of the data segment. The token directive transmission module transmits the token directive to the storage device.10-13-2011
20110252189METHOD FOR GENERATING PHYSICAL IDENTIFIER IN STORAGE DEVICE AND MACHINE-READABLE STORAGE MEDIUM - A method and system for generating a physical identifier in a storage device that includes a plurality of storage regions is provided. The method includes determining a number of reference storage regions for uniquely identifying the storage device; comparing the number of reference storage regions to a threshold; generating auxiliary storage regions for uniquely identifying the storage device, such that a number of the auxiliary storage regions corresponds to a result of the comparison; generating location distribution information of the reference storage regions and auxiliary storage regions; and storing the location distribution information in the storage device.10-13-2011
20110252188SYSTEM AND METHOD FOR STORING INFORMATION IN A MULTI-LEVEL CELL MEMORY - A multi-level memory is used to store analog data by mapping a difference data using a mapping scheme that reduces the effect of errors caused by voltage level drift in the memory.10-13-2011
20110252187SYSTEM AND METHOD FOR OPERATING A NON-VOLATILE MEMORY INCLUDING A PORTION OPERATING AS A SINGLE-LEVEL CELL MEMORY AND A PORTION OPERATING AS A MULTI-LEVEL CELL MEMORY - System and method for storing data in a non-volatile memory including a multi-level cell and single-level cell memory portions. To write a dataset to the non-volatile memory, if the size of the dataset is equal to the size of pages in the multi-level cell memory portion, the dataset may be written directly to the multi-level cell memory portion to fill an integer number of pages in a single write operation. However, if the size of the dataset is different than the size of the multi-level cell memory pages, at least a portion of the dataset may be temporarily written to the single-level cell memory portion until data is accumulated in a plurality of write operations having a size equal the size of the multi-level cell memory pages. The accumulated data may fill an integer number of the pages in the multi-level cell memory portion in a single write operation.10-13-2011
20110252186MINIMIZING WRITE OPERATIONS TO A FLASH MEMORY-BASED OBJECT STORE - Approaches for minimizing the amount of write transactions issued to an object store maintained on a solid state device (SSD). Transactions requested against an object store maintained on a SSD may be committed once transaction information for the transaction is durably stored in a non-volatile dynamic random access memory (DRAM), which may be maintained in a HDD controller. Further, data blocks stored in a volatile cache of a database server that issues write requests to an object store maintained on one or more SSDs may be considered persistent stored once confirmation is received that the data blocks are written to a double-write buffer stored on a non-volatile medium, such as NV RAM in a HDD controller. Additionally, any data blocks that are to be written over in a non-volatile DRAM are first ensured to be no longer present within the volatile write cache maintained a the solid state device.10-13-2011
20110252185Method Of Operating A NAND Memory Controller To Minimize Read Latency Time - A NAND memory chip has a plurality of blocks with each block having a certain amount of storage and wherein the amount of storage in each block is the minimum amount that is erasable as a group. A controller controls the NAND memory chip. The method of operating the controller comprises writing data into a block of the NAND memory chip to partially fill the block. Then the controller tracks the extent to which the block has been written. After the block is partially written, the step is stopped. The controller determines if a request to the NAND memory chip needs to be serviced. The controller resumes the writing into the block after servicing the request. The present invention also relates to a method for controlling, the operation of a memory device having a controller for interfacing with and controlling a NAND memory. The memory device is responsive to either serial or parallel ATA protocol commands supplied from a host.10-13-2011
20110078364SOLID STATE STORAGE SYSTEM FOR CONTROLLING RESERVED AREA FLEXIBLY AND METHOD FOR CONTROLLING THE SAME - A solid state storage system includes a flash memory area and a memory controller. The flash memory area includes memory blocks and replacement blocks configured to replace bad blocks occurring within the memory blocks. The memory controller is configured to perform a logical-to-physical address mapping on logical blocks including the replacement blocks, and select the replacement blocks using logical addresses of the logical blocks corresponding to the bad blocks.03-31-2011
20110078363BLOCK MANAGEMENT METHOD FOR A FLASH MEMORY AND FLASH MEMORY CONTROLLER AND STORAGE SYSTEM USING THE SAME - A block management method for managing a plurality of physical blocks of a flash memory chip is provided. The block management method includes configuring a plurality of logical addresses; mapping the logical addresses to a plurality of logical blocks; and mapping the logical blocks to the physical blocks. Additionally, the block management method also includes obtaining deleting records related to a plurality of deleted logical addresses from a host system, wherein data stored in the deleted logical addresses is recognized as invalid by the host system. And, the block management method further includes obtaining a deleted logical block, marking each of the logical addresses mapped to the deleted logical block as a bad logical address, and linking the physical block mapped to the deleted logical block to a spare area. Accordingly, the block management method can effectively prolong the lifespan of a flash memory chip.03-31-2011
20110153920ELECTRONIC APPARATUS OF RECORDING DATA USING NON-VOLATILE MEMORY - An electronic apparatus for recording data using a non-volatile memory is provided. The electronic apparatus includes a non-volatile memory and a controller. The non-volatile memory stores a plurality of sets of playing information of the electronic apparatus. The controller is coupled to the non-volatile memory for receiving an input data and transforming a data structure of the input data into a bitmapping data structure. The controller includes a bitmapping module that is capable of transforming the input data into data having at least one bit but less than one byte in a bitmapping manner.06-23-2011
20100125701Multi-Level Non-Volatile Memory Device, Memory System Including the Same, and Method of Operating the Same - Methods of programming nonvolatile memory devices include programming a plurality of nonvolatile multi-state memory cells in the non-volatile memory device with state-converted data derived from non-state-converted data. This state-converted data may be associated with a greater number of erased states relative to the non-state-converted data, when programmed into the plurality of nonvolatile memory cells. The methods also include generating a flag having a value that indicates which ones of the plurality of nonvolatile memory cells have been programmed with data that is swapped with data in other ones of the plurality of nonvolatile memory cells. This flag may also be programmed into the nonvolatile memory device. Operations may also be performed to read the state-converted data (and flag) from the plurality of nonvolatile memory cells and then decode the state-converted data into the non-state-converted data, based on the value of the flag.05-20-2010
20110082966Authentication and Securing of Write-Once, Read-Many (WORM) Memory Devices - These embodiments relate to authentication and securing of write-once, read-many (WORM) memory devices. In one embodiment, a memory device comprises a controller operable in first and second modes of operation after stored security information is validated, wherein in the first mode of operation, the memory device operates in a read-only mode, and wherein in the second mode of operation, the memory device operates in a write-once, read-many (WORM) mode. In another embodiment, the controller is operative to perform security methods.04-07-2011
20110082965PROCESSOR-BUS-CONNECTED FLASH STORAGE MODULE - A system includes multiple nodes coupled using a network of processor buses. The multiple nodes include a first processor node, including one or more processing cores and main memory, and a flash memory node coupled to the first processor node via a first processor bus of the network of processor buses. The flash memory node includes a flash memory including flash pages, a first memory including a cache partition for storing cached flash pages for the flash pages in the flash memory and a control partition for storing cache control data and contexts of requests to access the flash pages, and a logic module including a direct memory access (DMA) register and configured to receive a first request from the first processor node via the first processor bus to access the flash pages.04-07-2011
20110082964PARTITIONING PROCESS TO IMPROVE MEMORY CELL RETENTION - Subject matter disclosed herein relates to improving memory cell retention for non-volatile flash memory.04-07-2011
20110072201Novel NAND-based hybrid NVM design that integrates NAND and NOR in 1-die with serial interface - A nonvolatile memory device includes multiple independent nonvolatile memory arrays that concurrently for parallel reading and writing the nonvolatile memory arrays. A serial interface communicates commands, address, device status, and data between a master device and nonvolatile memory arrays for concurrently reading and writing of the nonvolatile memory arrays and sub-arrays. Data is transferred on the serial interface at the rising edge and the falling edge of the synchronizing clock. The serial interface transmits a command code and an address code from a master device and transfers a data code between the master device and the nonvolatile memory device, wherein the data code has a length that is determined by the command code and a location determined by the address code. Reading one nonvolatile memory array may be interrupted for reading another. One reading operation has two sub-addresses with one transferred prior to a command.03-24-2011
20110072200Novel NAND-based hybrid NVM design that integrates NAND and NOR in 1-die with parallel interface - A nonvolatile memory device includes multiple independent nonvolatile memory arrays that concurrently for parallel reading and writing the nonvolatile memory arrays. A parallel interface communicates commands, address, device status, and data between a master device and nonvolatile memory arrays for concurrently reading and writing of the nonvolatile memory arrays and sub-arrays. Data is transferred on the parallel interface at the rising edge and the falling edge of the synchronizing clock. The parallel interface transmits a command code and an address code from a master device and transfers a data code between the master device and the nonvolatile memory device, wherein the data code has a length that is determined by the command code and a location determined by the address code. Reading one nonvolatile memory array may be interrupted for reading another. One reading operation has two sub-addresses with one transferred prior to a command.03-24-2011
20110072199STARTUP RECONSTRUCTION OF LOGICAL-TO-PHYSICAL ADDRESS TRANSLATION DATA FOR SOLID STATE DISKS - Described embodiments provide reconstruction of logical-to-physical address mapping data for one or more sectors of a storage device at startup of a media controller. The sectors of the storage device are organized into blocks and superblocks and the address mapping data is stored in a volatile memory. At a startup condition of the media controller, a buffer layer module of the media controller allocates space in the volatile memory for one or more logical-to-physical address mapping data structures. A media layer module of the media controller determines a block type of each block of the storage device and places each block of the storage device into corresponding groups based on the determined block type of each block. The one or more blocks of each group are processed, and one or more address mapping data structures for the storage device are constructed in the allocated space in the volatile memory.03-24-2011
20110072198ACCESSING LOGICAL-TO-PHYSICAL ADDRESS TRANSLATION DATA FOR SOLID STATE DISKS - Described embodiments provide a media controller for a storage device having sectors, the sectors organized into blocks and superblocks. The media controller stores, on the storage device, logical-to-physical address translation data in N summary pages, where N corresponds to the number of superblocks of the storage device. A buffer layer module of the media controller initializes a summary page cache in a buffer. The summary page cache has space for M summary page entries, where M is less than or equal to N. For operations that access a summary page, the media controller searches the summary page cache for the summary page. If the summary page is stored in the summary page cache, the buffer layer module retrieves the summary page from the summary page cache. Otherwise, the buffer layer module retrieves the summary page from the storage device and stores the retrieved summary page to the summary page cache.03-24-2011
20110072193DATA READ METHOD, AND FLASH MEMORY CONTROLLER AND STORAGE SYSTEM USING THE SAME - A data read method for reading data to be accessed by a host system from a plurality of flash memory modules is provided. The data read method includes receiving command queuing information related to a plurality of host read commands from the host system, each of the host read commands is corresponding to one of a plurality of data input/output buses coupled to the flash memory modules. The data read method also includes re-arranging the host read commands and generating a command giving sequence according to the data input/output buses corresponding to the host read commands. The data read method further includes sequentially receiving and processing the host read commands from the host system according to the command giving sequence and pre-reading data corresponding to a second host read command. Thereby, the time for executing the host read commands can be effectively shortened.03-24-2011
20110072203METHOD AND DEVICES FOR INSTALLING AND RETRIEVING LINKED MIFARE APPLICATIONS - A method for installing linked MIFARE applications (TK03-24-2011
20120303882USB MEMORY DEVICE - A flash memory drive comprising: a male USB connector; a female USB connector; a flash memory chip to store file data; a computing processor, operatively connected to the flash memory chip, to manage tranfers of data to and from the flash memory chip; and a changeover switch, operatively connected to the computing processor, to connect the computing processor to one of the male USB connector and the female USB connector; wherein there is no data communication link between the male USB connector and the female USB connector when the changeover switch is connected to one of the male USB connector and the female USB connector.11-29-2012
20120303881Method and Memory Device that Powers-Up in a Read-Only Mode and Is Switchable to a Read/Write Mode - One-time programmable (OTP) and write-once read-many (WORM) memory devices and methods for use therewith are provided. These embodiments can be used to provide compatibility between a memory device that uses an OTP (or few-time programmable (FTP)) memory array and host devices that use a file system, such as the DOS FAT file system, that expects to be able to rewrite to a memory address in the memory device. These embodiments can also be used to prevent accidental or deliberate overwrites, changes, or deletions to existing data in a WORM memory device.11-29-2012
20120303878Method and Controller for Identifying a Unit in a Solid State Memory Device for Writing Data to - In a method for identifying a unit in a solid state memory device for writing data to a tier structure is maintained the tier structure comprising at least two tiers for assigning units available for writing data to. In response to receiving a request for writing data it is determined if a unit for writing data to is available in a first tier of the at least two tiers. In response to determining that a unit is available for writing data to in the first tier this unit is identified for writing data to, and in response to determining that no unit is available for writing the data to in the first tier it is determined if a unit is available for writing data to in a second tier of the at least two tiers subject to a priority of the write request.11-29-2012
20120303880METHOD AND APPARATUS FOR ENCRYPTING AND PROCESSING DATA IN FLASH TRANSLATION LAYER - A method and apparatus for preventing a user from interpreting optional stored data information even when the user extracts the optional stored data, by managing data associated with a flash memory in a flash translation layer, the method comprising searching at least one page of the flash memory when writing data to the flash memory, determining whether authority information corresponding to respective searched pages includes an encryption storage function, generating, corresponding to respective searched pages, a page key according to an encrypting function when the authority information includes the encryption storage function encrypting the data using the generated page key and storing the encrypted data in the respective searched pages, and storing the data in the respective searched pages without encryption when the authority information does not include the encryption storage function.11-29-2012
20120303879Memory Device and Method for Programming Flash Memory Utilizing Spare Blocks - An access method for use in a memory device. The memory device comprises a data area having a plurality of data blocks and a spare area having a plurality of spare blocks. First, data from a host is received. A spare block is popped from the spare area and the received data is programmed into the popped spare block accordingly. A data block corresponding to the data is pushed to the spare area. The pushed data block is erased when the memory device is waiting for a specific instruction to be issued from the host.11-29-2012
20120303876CACHING DATA IN A STORAGE SYSTEM HAVING MULTIPLE CACHES INCLUDING NON-VOLATILE STORAGE CACHE IN A SEQUENTIAL ACCESS STORAGE DEVICE - Provided are a computer program product, system, and method for caching data in a storage system having multiple caches. A sequential access storage device includes a sequential access storage medium and a non-volatile storage device integrated in the sequential access storage device, received modified tracks are cached in the non-volatile storage device, wherein the non-volatile storage device is a faster access device than the sequential access storage medium. A spatial index indicates the modified tracks in the non-volatile storage device in an ordering based on their physical location in the sequential access storage medium. The modified tracks are destaged from the non-volatile storage device by comparing a current position of a write head to physical locations of the modified tracks on the sequential access storage medium indicated in the spatial index to select a modified track to destage from the non-volatile storage device to the storage device.11-29-2012
20120303875POPULATING STRIDES OF TRACKS TO DEMOTE FROM A FIRST CACHE TO A SECOND CACHE - Provided are a computer program product, system, and method for populating strides of tracks to demote from a first cache to a second cache. A first cache maintains modified and unmodified tracks from a storage system subject to Input/Output (I/O) requests. A determination is made to demote tracks from the first cache. A determination is made as to whether there are enough tracks ready to demote to form a stride, wherein tracks are written to a second cache in strides defined for a Redundant Array of Independent Disk (RAID) configuration. A stride is populated with tracks ready to demote in response to determining that there are enough tracks ready to demote to form the stride. The stride of tracks, to demote from the first cache, are promoted to the second cache. The tracks in the second cache that are modified are destaged to the storage system.11-29-2012
20120303874INFORMATION PROCESSING UNIT AND INFORMATION PROCESSING METHOD - There are provided an information processing unit and an information processing method which are capable of reducing a startup time. The information processing unit includes: a volatile memory temporarily holding, as memory data, information which indicates a plurality of programs; a nonvolatile memory; and a page information generation section generating page information which identifies memory data for a plurality of predetermined pages from memory data stored in the volatile memory. The page information includes a memory address for each page in the volatile memory, and a program number of a program including memory data for each page.11-29-2012
20120303873METHOD FOR STORAGE DEVICES TO ACHIEVE LOW WRITE AMPLIFICATION WITH LOW OVER PROVISION - A solid state drive (SSD) includes an SSD control module configured to determine frequencies corresponding to how often data stored in respective logical addresses associated with the SSD is updated and form groups of the logical addresses according to the frequencies, and a memory control module configured to rewrite the data to physical addresses in blocks of an SSD storage region based on the groups.11-29-2012
20120303872CACHE MANAGEMENT OF TRACKS IN A FIRST CACHE AND A SECOND CACHE FOR A STORAGE - Provided a computer program product, system, and method for cache management of tracks in a first cache and a second cache for a storage. The first cache maintains modified and unmodified tracks in the storage subject to Input/Output (I/O) requests. Modified and unmodified tracks are demoted from the first cache. The modified and the unmodified tracks demoted from the first cache are promoted to the second cache. The unmodified tracks demoted from the second cache are discarded. The modified tracks in the second cache that are at proximate physical locations on the storage device are grouped and the grouped modified tracks are destaged from the second cache to the storage device.11-29-2012
20120303871SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME - According to one embodiment, a semiconductor memory device includes a memory cell array including a plurality of memory cells, a first register configured to store data of the memory cells, and a sequence control circuit configured to control the memory cell array and the first register. In at least a data read operation of the memory cells, the sequence control circuit reads out, from the memory cell array, data including flag information representing whether the number of failed bits is in an allowable range.11-29-2012
20120303870MEMORY CHIP, MEMORY SYSTEM, AND METHOD OF ACCESSING THE MEMORY CHIP - A memory chip, a memory system, and a method of accessing the memory chip. The memory chip includes a substrate, a first storage unit, and a second storage unit. The first storage unit includes a plurality of first memory cells may have a first storage capacity of 211-29-2012
20120303869HANDLING HIGH PRIROITY REQUESTS IN A SEQUENTIAL ACCESS STORAGE DEVICE HAVING A NON-VOLATILE STORAGE CACHE - Modified tracks for write requests to a sequential access storage medium in a sequential access storage device are cached in a non-volatile storage, which is a faster access device than the sequential access storage medium. A request queue includes destage requests to destage the modified tracks in the non-volatile storage device to the sequential access storage medium and read requests to access read requested tracks from the sequential access storage medium. A comparison is made of a current position of a read/write mechanism with respect to physical locations on the sequential access storage medium of the tracks subject to the destage requests indicated in the request queue. A determination is made of one of the destage requests to process based on the comparison. The modified track for the determined destage request is written from the non-volatile storage device to the sequential access storage medium.11-29-2012
20120303868IDENTIFYING A LOCATION CONTAINING INVALID DATA IN A STORAGE MEDIA - A system includes storage media and control logic coupled to the storage media, where the control logic is configured to receive a write request and determine whether the write request specifies writing a predetermined pattern to a particular location of the storage media. In response to determining that the write request specifies writing the predetermined pattern to the particular location, the control logic is configured to identify with an indicator that the particular location contains invalid data.11-29-2012
20120303867IMPLEMENTING ENHANCED EPO PROTECTION FOR INDIRECTION DATA - A method and a storage system are provided for implementing indirection tables for persistent media or disk drives with enhanced emergency power outage (EPO) protection for the indirection data, such as shingled perpendicular magnetic recording (SMR) indirection tables. Chaining of indirection data is provided with one block pointing to another block of the indirection data stored to disk or flash memory. An EPO-safe buffer is used to store a metadata entry responsive to completing each host write command. Each metadata entry is added to a metadata block, a pointer is stored in the EPO-safe buffer to a current metadata block and a previous metadata block. For a next EPO-safe buffer update entries are removed for the previous metadata block, keeping the last two metadata pointers and last metadata block.11-29-2012
20120303866Storage device with inline address indirection metadata storage - Methods are described that allow disk drives, such as shingle-written magnetic recording (SMR) drives, to recover an Indirection Address Table mapping of LBAs to PBAs after an emergency power off (EPO). Indirection Address Table (IAT) snapshots are periodically written inline with user data stores, and in one embodiment Cumulative Delta Lists (CDLs) with incremental address update information are stored between snapshots. In an embodiment of the invention, when an imminent loss of power is detected, the current CDL, covering IAT updates not yet written to disk, is saved to a nonvolatile memory. The IAT snapshots combined with the set of CDLs provide the information needed to recreate the current Indirection Address Table when power is restored after an emergency power loss. In an alternative embodiment the CDL is obviated by including metadata in the sector that encodes the address indirection mapping and the last snapshot ID.11-29-2012
20120303865Write Operation with Immediate Local Destruction of Old Content in Non-Volatile Memory - Method and apparatus for writing data to a non-volatile memory device, such as a solid state drive (SSD). In accordance with various embodiments, a host write command is serviced by writing a newer copy of user data to a first selected empty physical location in a non-volatile memory, and by concurrently overwriting an older copy of said user data previously stored to a different, second selected occupied physical location of the non-volatile memory.11-29-2012
20120303864CACHE MANAGEMENT OF TRACKS IN A FIRST CACHE AND A SECOND CACHE FOR A STORAGE - Provided a computer program product, system, and method for cache management of tracks in a first cache and a second cache for a storage. The first cache maintains modified and unmodified tracks in the storage subject to Input/Output (I/O) requests. Modified and unmodified tracks are demoted from the first cache. The modified and the unmodified tracks demoted from the first cache are promoted to the second cache. The unmodified tracks demoted from the second cache are discarded. The modified tracks in the second cache that are at proximate physical locations on the storage device are grouped and the grouped modified tracks are destaged from the second cache to the storage device.11-29-2012
20120303862CACHING DATA IN A STORAGE SYSTEM HAVING MULTIPLE CACHES INCLUDING NON-VOLATILE STORAGE CACHE IN A SEQUENTIAL ACCESS STORAGE DEVICE - Provided are a computer program product, system, and method for caching data in a storage system having multiple caches. A sequential access storage device includes a sequential access storage medium and a non-volatile storage device integrated in the sequential access storage device, received modified tracks are cached in the non-volatile storage device, wherein the non-volatile storage device is a faster access device than the sequential access storage medium. A spatial index indicates the modified tracks in the non-volatile storage device in an ordering based on their physical location in the sequential access storage medium. The modified tracks are destaged from the non-volatile storage device by comparing a current position of a write head to physical locations of the modified tracks on the sequential access storage medium indicated in the spatial index to select a modified track to destage from the non-volatile storage device to the storage device.11-29-2012
20120303861POPULATING STRIDES OF TRACKS TO DEMOTE FROM A FIRST CACHE TO A SECOND CACHE - Provided are a computer program product, system, and method for populating strides of tracks to demote from a first cache to a second cache. A first cache maintains modified and unmodified tracks from a storage system subject to Input/Output (I/O) requests. A determination is made to demote tracks from the first cache. A determination is made as to whether there are enough tracks ready to demote to form a stride, wherein tracks are written to a second cache in strides defined for a Redundant Array of Independent Disk (RAID) configuration. A stride is populated with tracks ready to demote in response to determining that there are enough tracks ready to demote to form the stride. The stride of tracks, to demote from the first cache, are promoted to the second cache. The tracks in the second cache that are modified are destaged to the storage system.11-29-2012
20110078366Semiconductor device with non-volatile memory and random access memory - A semiconductor device including a large capacity non-volatile memory and at least one random access memory, said the access time of said device being matched to the access time of each random access memory. The semiconductor memory device is comprised of: a non-volatile memory FLASH having a first reading time; a random access memory DRAM having a second reading time which is more than 100 times shorter than the first reading time; a circuit that includes a control circuit connected to both the FLASH and the DRAM and enabled to control accesses to those FLASH and DRAM; and a plurality of I/O terminals connected to the circuit. As a result, FLASH data is transferred to the DRAM before the DRAM is accessed, thereby matching the access time between the FLASH and the DRAM. Data is written back from the DRAM to the FLASH as needed, thereby keeping data matched between the FLASH and the DRAM and storing the data.03-31-2011
20090019216Disk drive device and method for saving a table for managing data in non-volatile semiconductor memory in disk drive device - Embodiments of the present invention help to suppress adverse effects on