Entries |
Document | Title | Date |
20080201518 | LOG-BASED FTL AND OPERATING METHOD THEREOF - A log-based FTL and an operating method thereof for improving performances of reading and writing operations to increase the lifetime of a flash memory. In the method, when a reading operation for an LBN and an LPN is requested, a PBN and a PPN corresponding to the LBN and the LPN are calculated with reference to a pagemap corresponding to the LBN. A physical page of a physical block corresponding to the PBN and the PPN is accessed so that a reading operation is performed. On the other hand, when a writing operation for the LBN and the LPN is requested, a PBN and a PPN for a free-page of a physical block last assigned for the LBN are calculated with reference to a blockmap. The physical page of the physical block corresponding to the PBN and the PPN is accessed, so that a writing operation is performed. The pagemap stores a PBN and a PPN, and the blockmap stores a PBN list and a PPN. | 08-21-2008 |
20080201519 | MEMORY CARD - A memory card is structured to support a variety of applications by dividing a storage region into a plurality of sub storage regions, each sub storage region being assigned a particular data format associated with each of a plurality of application programs stored in a controller of the memory card. The data stored in each of the sub storage regions co-exists compatibly in the memory card. This allows for a multiplicity of applications, which can be made available through the use of a single memory card. | 08-21-2008 |
20080201520 | Flash firmware management - A computing host executes a web browser to access a utility application for managing one or more storage devices connected to the computing host. Management of each storage device may include making queries about the storage spaces and contents of the storage device, updating firmware of the storage device, updating programmable hardware of the storage device, erasing the storage device, sanitizing the storage device, logging events occurring in the storage device, and maintaining statistics on operation of the storage device. | 08-21-2008 |
20080201521 | Memory controller for controlling memory and method of controlling memory - A memory controller for controlling a memory that operates in synchronization with a clock signal, wherein the memory sequentially outputs data of addresses starting from a target address in synchronization with the clock signal after receiving a read command and the target address, the memory controller includes a supply control module that performs a supply process for supplying data inside the memory corresponding to a request address to an external device, in response to a read request designating the request address which is transmitted from the external device, wherein the supply process includes a supply process using a sequential mode, and wherein the supply process using the sequential mode includes a process for acquiring data to be supplied to the external device from the memory in response to read requests by repeatedly stopping and restarting supply of the clock signal without supplying the read command and the target address to the memory, in a case where a plurality of consecutive request addresses are sequentially designated one after another by a plurality of the consecutive read requests and a process for supplying requested data from among data acquired in response to the plurality of the read requests to the external device. | 08-21-2008 |
20080209106 | Memory access - A memory access system including a memory in which data is organized in pages, each page holding a sequence of data elements; means for receiving a requested address including a requested page address and a requested data element address; logic for accessing a current page from the memory using a current page address; logic for reading out data elements of the current page in the sequence in which they are held in memory; logic for comparing the requested page address with the current page address and for issuing a memory access request with the requested page address when they are not the same; and logic operable when the requested page address is the same as the current page address for comparing a requested data element address with the current address of a data element being read out and returning the data element when the requested data element address matches the current data element address. | 08-28-2008 |
20080209107 | Apparatus, method, and system of NAND defect management - Various embodiments comprise apparatus, methods, and systems that include an apparatus comprising a memory device configurable as a plurality of erase block groups including a base erase block group, wherein each of the plurality of erase block groups comprises a plurality of erase blocks each identified by a matching unique plurality of erase block numbers unique within the plurality of erase blocks and matching across the plurality of erase block groups; and a mapping table coupled to the plurality of erase block groups to store at least one group address number corresponding to one of the matching unique plurality of erase block numbers identifying a non-defective erase block in the base erase block group, and corresponding to several of the matching unique plurality of erase block numbers identifying a single non-defective erase block in each of the plurality of erase block groups other than the base erase block group. | 08-28-2008 |
20080209108 | System and method of page buffer operation for memory devices - Systems and methods are provided for using page buffers of memory devices connected to a memory controller through a common bus. A page buffer of a memory device is used as a temporary cache for data which is written to the memory cells of the memory device. This can allow the memory controller to use memory devices as temporary caches so that the memory controller can free up space in its own memory. | 08-28-2008 |
20080209109 | INTERRUPTIBLE CACHE FLUSHING IN FLASH MEMORY SYSTEMS - Cache flushing is effected for a flash memory by copying, to a block of the memory, first and second portions of cached data, and servicing a host access in-between copying the first portion and the second portion. Either both portions are selected before the copying, or erasing the block is forbidden until after the copying, or a portion of the block left unwritten by the first copying remains unwritten until after the host access is serviced. | 08-28-2008 |
20080209110 | APPARATUS AND METHOD OF PAGE PROGRAM OPERATION FOR MEMORY DEVICES WITH MIRROR BACK-UP OF DATA - An apparatus and method of page program operation is provided. When performing a page program operation with a selected memory device, a memory controller loads the data into the page buffer of one selected memory device and also into the page buffer of another selected memory device in order to store a back-up copy of the data. In the event that the data is not successfully programmed into the memory cells of the one selected memory device, then the memory controller recovers the data from the page buffer of the other memory device. Since a copy of the data is stored in the page buffer of the other memory device, the memory controller does not need to locally store the data in its data storage elements. | 08-28-2008 |
20080209111 | OVER-SAMPLING READ OPERATION FOR A FLASH MEMORY DEVICE - A flash memory device and a reading method are provided where memory cells are divided into at least two groups. Memory cells are selected according to a threshold voltage distribution. Data stored in the selected memory cells are detected and the data is latched corresponding to one of the at least two groups according to a first read operation. A second read operation detects and latches data of the memory cells corresponding to another one of the at least two groups. The data is processed through a soft decision algorithm during the second read operation. | 08-28-2008 |
20080209112 | High Endurance Non-Volatile Memory Devices - High endurance non-volatile memory devices (NVMD) are described. A high endurance NVMD includes an I/O interface, a NVM controller, a CPU along with a volatile memory subsystem and at least one non-volatile memory (NVM) module. The volatile memory cache subsystem is configured as a data cache subsystem. The at least one NVM module is configured as a data storage when the NVMD is adapted to a host computer system. The I/O interface is configured to receive incoming data from the host to the data cache subsystem and to send request data from the data cache subsystem to the host. The at least one NVM module may comprise at least first and second types of NVM. The first type comprises SLC flash memory while the second type MLC flash. The first type of NVM is configured as a buffer between the data cache subsystem and the second type of NVM. | 08-28-2008 |
20080209113 | Method For Increasing Storage Capacity of a Memory Device - A method for increasing memory storage capacity in a memory device having at least two storage cells wherein at least one measurable physical property is associated with each of the storage cells a nominal value of which may be used to assign a data value to the respective storage cell. Differences between at least two storage cells with regard to the respective nominal values of one or more of the respective physical properties associated with a storage cell and its actual value at a given time are used to provide additional storage capacity. | 08-28-2008 |
20080209114 | Reliability High Endurance Non-Volatile Memory Device with Zone-Based Non-Volatile Memory File System - Improved reliability high endurance non-volatile memory device with zone-based non-volatile memory file system is described. According to one aspect of the present invention, a zone-based non-volatile memory file system comprises a two-level address mapping scheme: a first level address mapping scheme maps linear or logic address received from a host computer system to a virtual zone address; and a second level address mapping scheme maps the virtual zone address to a physical zone address of a non-volatile memory module. The virtual zone address represents a number of zones each including a plurality of data sectors. Zone is configured as a unit smaller than data blocks and larger than data pages. Each of the data sector consists of 512-byte of data. The ratio between zone and the sectors is predefined by physical characteristics of the non-volatile memory module. A tracking table is used for correlating the virtual zone address with the physical zone address. Data programming and erasing are performed in a zone basis. | 08-28-2008 |
20080209115 | SEMICONDUCTOR MEMORY CARD ACCESS APPARATUS, A COMPUTER-READABLE RECORDING MEDIUM, AN INITIALIZATION METHOD, AND A SEMICONDUCTOR MEMORY CARD - A predetermined number of erasable blocks positioned at a start of a volume area in a semiconductor memory card are provided so as to include volume management information. A user area following the volume management information includes a plurality of clusters. A data length NOM of an area from a master boot record & partition table sector to a partition boot sector is determined so that the plurality of clusters in the user area are not arranged so as to straddle erasable block boundaries. Since cluster boundaries and erasable block boundaries in the user area are aligned, there is no need to perform wasteful processing in which two erasable blocks are erased to rewrite one cluster. | 08-28-2008 |
20080209116 | Multi-Processor Flash Memory Storage Device and Management System - A data storage device has a host controller interface, a plurality of microprocessor units each having a portion of random access memory (RAM) dedicated thereto, a plurality of Flash device configurations each having dedicated bus connections to individual ones or multiples of the microprocessor units, and a dataflow controller accessible to the host controller interface for managing access to the Flash device configurations. | 08-28-2008 |
20080215798 | Randomizing for suppressing errors in a flash memory - Original data to be stored in a nonvolatile memory are first randomized while preserving the size of the original data, In response for a request for the original data, the randomized data are retrieved, derandomized and exported without authenticating the requesting entity. ECC encoding is applied either before or after randomizing; correspondingly, ECC decoding is applied either after or before derandomizing. | 09-04-2008 |
20080215799 | Control Chip of Adapter Interconnecting Pc and Flash Memory Medium and Method of Enabling the Control Chip to Program the Flash Memory Medium to be Accessible by the Pc - In one embodiment an apparatus interconnecting a PC and a flash memory device is provided and includes a control chip including a RAM, a ROM, and a processor. The control chip is adapted to program the flash memory device as a main firmware stored with compatible configuration codes, an auxiliary firmware stored with programs of data encryption, flash memory device activation, and data compression, and a data storage segment so as to enable the PC to access the flash memory device via the control chip. Also, method of enabling the control chip to program the flash memory medium to be accessible by the PC is provided. | 09-04-2008 |
20080215800 | Hybrid SSD Using A Combination of SLC and MLC Flash Memory Arrays - Hybrid solid state drives (SSD) using a combination of single-level cell (SLC) and multi-level cell (MLC) flash memory arrays are described. According to one aspect of the present invention, a hybrid SSD is built using a combination SLC and MLC flash memory arrays. The SSD also includes a micro-controller to control and coordinate data transfer from a host computing device to either the SLC flash memory array of the MLC flash memory array. A memory selection indicator is determined by triaging data file based on one or more criteria, which include, but is not limited to, storing system files and user directories in the SLC flash memory array and storing user files in the MLC flash memory array; or storing more frequent access files in the SLC flash memory array, while less frequent accessed files in the MLC flash memory array. | 09-04-2008 |
20080215801 | Portable Data Storage Using Slc and Mlc Flash Memory - A portable data storage device is disclosed that includes an interface ( | 09-04-2008 |
20080215802 | High Integration of Intelligent Non-volatile Memory Device - High integration of a non-volatile memory device (NVMD) is disclosed. According to one aspect of the present invention, a non-volatile memory device comprises an intelligent non-volatile memory (NVM) controller and an intelligent non-volatile memory module. The NVM controller includes a central processing unit (CPU) configured to handle data transfer operations to the NVM module to ensure source synchronous interface, interleaved data operations and block abstracted addressing. The intelligent NVM module includes an interface logic, a block address manager and at least one non-volatile memory array. The interface logic is configured to handle physical block management. The block address manager is configured to ensure a physical address is converted to a transformed address that is accessible to the CPU of the intelligent NVM controller. The transformed address may be an address in blocks, pages, sectors or bytes either logically or physically. | 09-04-2008 |
20080215803 | SEMICONDUCTOR STORAGE DEVICE AND METHOD OF CONTROLLING THE SAME - A semiconductor storage device includes a first nonvolatile memory to store user data of a file, a second nonvolatile memory to store management data of the file, the second nonvolatile memory being different in type from the first nonvolatile memory, and a controller to control read/write of data with respect to the first and second nonvolatile memories. | 09-04-2008 |
20080222347 | Method and apparatus for protecting flash memory - A method is provided for protecting flash memory residing on a computing device. The method includes: receiving a data file having a digital signature at a main processor; forwarding the data file from the main processor to a secondary processor for signature validation; validating the digital signature associated with the data file at the secondary processor; enabling a write capability of a flash memory upon successful validation of the digital signature; and writing the data file to the flash memory. | 09-11-2008 |
20080222348 | File system for managing files according to application - The present invention discloses systems for managing files according to application. A digital storage system including: a storage memory having program code configured: to identify an application identity of an application issuing a storage command to access a file; and to adjust a storage mode of the file according to the application identity; and a processor for executing the program code. Preferably, the identifying is performed using a PID that is an indicator of the application identity. Preferably, the adjusting includes adjusting the storage mode according to the storage command. Preferably, the adjusting is performed using an SAT and/or an AST. A digital storage system including: a storage memory having program code configured: to identify an application scenario associated with a storage command to access a file; and to adjust a storage mode of the file according to the application scenario; and a processor for executing the program code. | 09-11-2008 |
20080222349 | IEEE 1394 INTERFACE-BASED FLASH DRIVE USING MULTILEVEL CELL FLASH MEMORY DEVICES - A flash drive and method of transferring data from a system to a flash drive. The flash drive includes a casing, a plurality of flash memory devices within the casing, each of the flash memory devices having multilevel cells, an IEEE 1394 interface controller within the casing, coupled to the flash memory devices, and interfacing with the flash memory devices for interleaved multichannel access to and from at least two of the flash memory devices, and at least one IEEE 1394 interface connector projecting from the casing for interfacing the flash memory devices with a system through the controller. The method entails coupling a plurality of multilevel cell flash memory devices to a system through an IEEE 1394 interface controller and at least one IEEE 1394 interface connector, and performing interleaved multichannel access to and from at least two of the flash memory devices. | 09-11-2008 |
20080222350 | Flash memory device for storing data and method thereof - A flash memory device which comprises a controller and one or plurality of flash memories for storing data and method thereof are disclosed. The controller comprises a control interface to accept data access which is from a main board and is managed by a control element of flash memory and a buffer management element. Through a micro-processing element in the controller, the data access from main board is checked for a random access or a serial page access. The random access and serial page access are written to different blocks by different processes in one or plurality of flash memories. The lifetime and processing speed of flash memories are improved for reduced erasure times during writing data. | 09-11-2008 |
20080228995 | Portable Data Storage Device Using a Memory Address Mapping Table - A portable data storage device includes a USB controller, a master control unit and a NAND flash memory device. The master control unit receives data to be written to logical addresses, and instructions to read data from logical addresses. It uses a memory address mapping table to associate the logical addresses with the physical addresses in the memory device, and writes data to or reads data from the physical address corresponding to the logical address. The mapping is changed at intervals, so that different ones of the physical address regions are associated at different times with the logical addresses. This increases the speed of the device, and also means that no physical addresses are rapidly worn out by being permanently associated with logical addresses to which data is written relatively often. | 09-18-2008 |
20080228996 | Portable Data Storage Device Using Multiple Memory Devices - A portable data storage device includes a USB interface ( | 09-18-2008 |
20080228997 | ZONED INITIALIZATION OF A SOLID STATE DRIVE - Zoned initialization of a solid state drive is provided. A solid state memory device includes a controller for controlling storage and retrieval of data to and from the device. A set of solid state memory components electrically coupled to the controller. The set is electrically divided into a first zone and a second zone, wherein the first zone is at least partially initialized independent from the second zone. An interface is coupled between the controller and the set of solid state memory components to facilitate transfer of data between the set of solid state memory components and the controller. | 09-18-2008 |
20080228998 | MEMORY STORAGE VIA AN INTERNAL COMPRESSION ALGORITHM - The subject specification discloses flash memory device with the capability of performing both internal compression as well as internal de-compression. Each of these actions takes place through appropriate algorithms. In normal operation, the compression occurs prior to a writing of data in a flash memory device. The compressed data travels to a storage location. The de-compression occurs after the reading of stored data and de-compressed data travels to an external system. | 09-18-2008 |
20080228999 | Dual use for data valid signal in non-volatile memory - In some types of non-volatile memory devices, the same signal from a memory device may be used for two purposes: During a read operation, the signal may be used by a memory controller to latch the data that is being received from the memory device. During a block erase operation and/or a block write operation, the signal may be used to notify the memory controller that the operation has been completed by the memory device. | 09-18-2008 |
20080229000 | FLASH MEMORY DEVICE AND MEMORY SYSTEM - A memory system comprises a flash memory, a processing unit, and a flash controller including address and control registers, the address and control registers being configured to receive information from the processing unit, wherein the flash controller is configured to control a copy-back program operation of the flash memory in hardware based on information stored in the address and control registers. | 09-18-2008 |
20080229001 | Solid memory module with extensible capacity - A solid memory module with extensible capacity includes at least a non-volatile memory module, each of which has at least a memory chip and a first connector, and at least a second connector, which electrically connects the first connector of the volatile memory module, at least a control unit and as a system interface. This control unit obtains external signals by this system interface and then transmits to this non-volatile memory module by the control unit to store or use the memory content. | 09-18-2008 |
20080229002 | SEMICONDUCTOR MEMORY AND INFORMATION PROCESSING SYSTEM - A semiconductor memory ( | 09-18-2008 |
20080229003 | STORAGE SYSTEM AND METHOD OF PREVENTING DETERIORATION OF WRITE PERFORMANCE IN STORAGE SYSTEM - Provided is a storage system capable of inhibiting the deterioration of its write performance. This storage system includes a flash memory, a cache memory, and a controller for controlling the reading, writing and deletion of data of the flash memory and the reading and writing of data of the cache memory, and detecting the generation of a defective block in the flash memory. When the controller detects the generation of a defective block in the flash memory, it migrates prescribed data stored in the flash memory to the cache memory and, even upon receiving from the host computer a command for updating the migrated data, disables the writing of data in the flash memory based on the command. | 09-18-2008 |
20080229004 | PROCESSOR SYSTEM USING SYNCHRONOUS DYNAMIC MEMORY - A processor system including: a processor and controller core connected via an internal bus; and a plurality of synchronous memory chips connected to the processor via an external bus; the controller core including a mode register selected by an address signal from the processor core and written with an information by a data signal from the processor core to select the operation mode of the plurality of synchronous memory chips, and a control unit to prescribe the operate mode to the plurality of synchronous memory chips based on the information written in the mode register, wherein the controller core outputs a mode setting signal based on the information written in the mode register or an access address signal from the processor core to the plurality of synchronous memory chips via the external bus selectively; and wherein the clock signal is commonly supplied to the plurality of synchronous memory chips. | 09-18-2008 |
20080229005 | Multi Partitioned Storage Device Emulating Dissimilar Storage Media - A digital media. In one embodiment, the digital media devices includes a storage unit/partition that emulates a Compact Disc-Read Only Memory (CD-ROM), and optionally, a second storage unit/partition that acts as a Read/Write storage device. | 09-18-2008 |
20080235435 | USE OF A SHUTDOWN OBJECT TO IMPROVE INITIALIZATION PERFORMANCE - According to some embodiments, use of a shutdown object during system initialization is disclosed. The shutdown object may be read from a non-volatile memory device and loaded into a random access memory. A plurality of headers may then be scanned from the non-volatile memory device. The shutdown object may be referenced to determine whether each of the plurality of headers includes valid data. Each of the plurality of headers that includes valid data may be represented in the random access memory. | 09-25-2008 |
20080235436 | STORAGE ACCESS CONTROL - A system and device are disclosed. In one embodiment, the system includes a processor, system memory, chipset, flash memory, and flash memory controller. The flash memory controller includes a base address register for a flash memory hidden protected area (HPA) to store a flash memory HPA base address, a size register for a flash memory HPA to store a size of the flash memory HPA, and control logic to allocate a portion of the flash memory as a flash memory HPA using the flash memory HPA base address and the flash memory HPA size address. | 09-25-2008 |
20080235437 | Methods for forcing an update block to remain sequential - A method for operating a memory system is provided. In this method, a sequential update block and preexisting data associated with the sequential update block are provided. Here, an option to convert the sequential update block to a chaotic update block also is provided. A write command is received to write data following a previous write command, where the write command and the previous write command have a discontinuity in logical addresses. If a logical address of the write command is different from logical addresses of the preexisting data, then the data are written to the sequential update block. If the logical address of the write command matches one of the logical addresses of the preexisting data, then the sequential update block is converted to a chaotic update block. | 09-25-2008 |
20080235438 | System and method for effectively implementing a multiple-channel memory architecture - A system and method for implementing a multiple-channel memory architecture includes a plurality of memory channels that are configured in a parallel manner to store electronic data. In certain embodiments, the memory channels are implemented to include non-volatile flash memory devices. A transfer controller communicates with the memory channels to control concurrent data transfer operations for transferring the electronic data in and out of the memory channels. The transfer controller generates individual channel clock signals to the respective memory channels for triggering corresponding data transfer operations which occur in an overlapping temporal sequence. | 09-25-2008 |
20080235439 | Methods for conversion of update blocks based on association with host file management data structures - A method for operating a memory system is provided. In this method, a sequential update block is provided and a write command is received to write data. The write command comprises a logical address associated with the data. If the logical address is associated with a host file management data structure, then the sequential update block is converted to a chaotic update block. After the conversion, the data are written to the chaotic update block. | 09-25-2008 |
20080235440 | Memory device - A memory device includes a housing, a memory within the housing, and a first electrical interface accessible on a top surface of the housing and a second electrical interface accessible on a bottom surface of the housing. As such, at least one of the first electrical interface and the second electrical interface is configured to establish electrical connection of the memory device with an electrical interface of another memory device when the memory device and the another memory device are in a stacked configuration. | 09-25-2008 |
20080235441 | Reducing power dissipation for solid state disks - A data processing device including a computer, the computer including a solid state disk (SSD), including a primary memory for single level cell storage, and a secondary memory for multi-level cell storage, a limited internal battery for supplying power to the computer, a socket for connecting the computer to an external power supply source, a detector for indicating that the computer is connected to an external power source, a processor for transferring data from the primary memory to the secondary memory, and an SSD controller for deciding whether or not the processor may transfer data from the primary memory to the secondary memory, based on a signal received from said detector. A method for SSD memory management is also described and claimed. | 09-25-2008 |
20080235442 | FLASH MEMORY DEVICE CAPABLE OF IMPROVING READ PERFORMANCE - A flash memory device, related system ad method are disclosed. The memory device includes a memory cell array a page buffer receiving read data, wherein the page buffer includes a main register transferring read data to a cache register during an read operation, and a control logic block controlling operation of the page buffer during the read operation, such that initialization of the main register continuously extends beyond a time period during which read data is transferred from the main register to the cache register. | 09-25-2008 |
20080235443 | Intelligent Solid-State Non-Volatile Memory Device (NVMD) System With Multi-Level Caching of Multiple Channels - A flash memory system stores blocks of data in Non-Volatile Memory Devices (NVMD) that are addressed by a logical block address (LBA). The LBA is remapped for wear-leveling and bad-block relocation by the NVMD. The NVMD are interleaved in channels that are accessed by a NVMD controller. The NVMD controller has a controller cache that caches blocks stored in NVMD in that channel, while the NVMD also contain high-speed cache. The multiple levels of caching reduce access latency. Power is managed in multiple levels by a power controller in the NVMD controller that sets power policies for power managers inside the NVMD. Multiple NVMD controllers in the flash system may each controller many channels of NVMD. The flash system with NVMD may include a fingerprint reader for security. | 09-25-2008 |
20080244162 | METHOD FOR READING NON-VOLATILE STORAGE USING PRE-CONDITIONING WAVEFORMS AND MODIFIED RELIABILITY METRICS - Data stored in non-volatile storage is read using sense operations and associated pre-conditioning waveforms. The pre-conditioning waveform provides a short term history for a non-volatile element which is analogous to the conditions experienced during programming when a programming pulse is applied prior to a verify operation. The pre-conditioning waveform can cause electrons to enter and exit trap sites, for instance, so that the accuracy of a probabilistic decoding process is improved. In one approach, multiple read operations are performed, some with pre-conditioning waveforms and some without. Pre-conditioning waveforms with different characteristics, such as amplitude, shape, duration and time before the associated read pulse, can also be used. For probabilistic decoding, initial reliability metrics can be developed based on multiple reads. Tables which store the reliability metrics can then be prepared for use in subsequent decoding. | 10-02-2008 |
20080244163 | PORTABLE DATA ACCESS DEVICE - A portable data access device is applicable to a data processing system. The portable data access device includes at least a first data access sector preset to be a read-only data access sector, for storing at least data and/or application programs executable by the data processing system; at least a second data access sector set to be a general data access sector; and a controller for interfacing with the data processing system and controlling data access to the first data access sector and the second data access sector. The data processing system may execute the application programs and/or access the data through the portable data access device, and the risk of modifying or damaging the data and/or application programs can be reduced by the read-only data access sector. | 10-02-2008 |
20080244164 | STORAGE DEVICE EQUIPPED WITH NAND FLASH MEMORY AND METHOD FOR STORING INFORMATION THEREOF - A storage device equipped with NAND flash memory and method for storing information thereof includes a SLC processing structure to provide fast information access and improve processing performance and a MLC processing structure to increase data density of each storage unit and reduce the cost and size of each unit of information. The data storing method includes storing important information such as operating system programs, application programs and information that have been accessed frequently in the SLC processing structure, and storing ordinary information in the MLC processing structure to reduce the cost and size of each unit of information. | 10-02-2008 |
20080244165 | Integrated Memory Management Device and Memory Device - An example of a device comprises a first MMU converting a logical address into a physical address for a cache, a controller accessing the cache based on the physical address for the cache, a first storage storing history data showing an access state to a main memory outside a processor, a second storage storing relation data showing a relationship between a logical address and a physical address in the main memory, and a second MMU converting a logical address into a physical address for the main memory based on the history and relation data and accessing the main memory based on the physical address for the main memory. The first and second MMU, controller, first storage, second storage are included in the processor. | 10-02-2008 |
20080244166 | System and method for configuration and management of flash memory - A system and a method for configuration and management of flash memory is provided, including a flash memory, a virtual memory region, and a memory logical block region. The flash memory includes a plurality of physical erase units. Each physical erase unit is configured to include at least a consecutive segment, and each segment is configured to include at least a consecutive frame. Each frame is configured to include at least a consecutive page. Each virtual memory region is configured to include a plurality of areas, and each area is configured to include at least a virtual erase unit. The memory logical block region is configured to include a plurality of clusters, and each cluster includes at least a consecutive memory logical block. By forming correspondence among the physical erase unit, segment, frame, page, virtual erase unit, area, memory logical block and cluster to control the data access to the flash memory, the present invention achieves the reconfiguration and management of memory consumption and access efficiency for the flash memory. | 10-02-2008 |
20080250190 | PORTABLE MEMORY DEVICE OPERATING SYSTEM AND METHOD OF USING SAME - A portable operating system for use by a user on a portable memory device, the system being accessible by the user on a primary host computer having a host graphical user interface. The system includes a portable graphical user interface accessible by the user when the portable memory device is placed into communication with the primary host computer, at least one portable application executable by the user via the portable graphical user interface, and a file system accessible by the user. Dragging at least one file from a host graphical user interface of the primary host computer to the portable graphical user interface activates a file system to transfer files into respective portable file folders corresponding to the respective filetype. | 10-09-2008 |
20080250191 | FLEXIBLE, LOW COST APPARATUS AND METHOD TO INTRODUCE AND CHECK ALGORITHM MODIFICATIONS IN A NON-VOLATILE MEMORY - A flash memory includes input/output buffers, a memory array having memory cells coupled to the input/output buffers, and row and column decoders, and a voltage-generator circuit coupled to the row and column decoders. A microcontroller is coupled to the command user interface. Switch-instruction circuitry selectively provides instructions to the microcontroller from the read-only memory and from off chip through on-board t-latches coupled to the input/output buffers under control of a command user interface. | 10-09-2008 |
20080250192 | Integrating flash memory system - The present invention discloses an integrating data processing system. The system includes a master device with a host interface for processing data, at least one NAND flash memory unit having a unit interface, and a flash memory controller. For controlling access to the NAND flash memory unit, the flash memory controller is provided with a first interface connected with the host interface of the master device, and a second interface connected with the unit interface of the NAND flash memory unit. The first interface is identical to the unit interface of the flash memory and the second interface is identical to the host interface of the master device. The master device can access the NAND flash memory unit via the flash memory controller thereby facilitating to fit in with the development of new flash memory device without upgrading the original master device. | 10-09-2008 |
20080250193 | Method to transmit important emergency personal and medical information via portable storage media - This invention presents a way to carry concise, important personal and medical information in a very portable format using information storage media, in a convenient carrying form for universal use by emergency medical or police personnel to assist the person carrying the device. | 10-09-2008 |
20080250194 | TWO-DIMENSIONAL WRITING DATA METHOD FOR FLASH MEMORY AND CORRESPONDING STORAGE DEVICE - In a two-dimensional writing data method for a flash memory and a corresponding storage device the storage device includes a plurality of flash modules and a control module. The flash modules are electrically connected to the control module. The control module includes a plurality of buffers and a process unit. The buffers are electrically connected to the respective flash modules and electrically connected to the process unit. The process unit is configured for managing a plurality of memory pages of the flash modules and defining addresses of the memory pages of the flash modules to form a two-dimensional access sequence. The process unit divides data into a plurality of data packets, and transmits the data packets into the buffers in series. The data is written into the corresponding memory pages from the respective buffers, thus the access time of the storage device is decreased. | 10-09-2008 |
20080250195 | Multi-Operation Write Aggregator Using a Page Buffer and a Scratch Flash Block in Each of Multiple Channels of a Large Array of Flash Memory to Reduce Block Wear - A flash system has multiple channels of flash memory chips that can be accessed in parallel. Host data is assigned to one of the channels by a multi-channel controller processor and accumulated in a multi-channel page buffer. When a page boundary in the page buffer is reached, the page buffer is written to a target physical block if full, or combined with old data fragments in an Aggregating Flash Block (AFB) when the logical-sector addresses (LSA's) match. Thus small fragments are aggregated using the AFB, reducing erases and wear of flash blocks. The page buffer is copied to the AFB when a STOP command occurs. Each channel has one or more AFB's, which are tracked by an AFB tracking table. | 10-09-2008 |
20080256287 | Methods and systems of managing memory addresses in a large capacity multi-level cell (MLC) based flash memory device - Methods and systems of managing memory addresses in a large capacity multi-level cell based flash memory device are described. According to one aspect, a flash memory device comprises a processing unit to manage logical-to-physical address correlation using an indexing scheme. The flash memory is partitioned into N sets. Each set includes a plurality of entries (i.e., blocks). N sets of partial logical entry number to physical block number and associated page usage information (hereinafter ‘PLTPPUI’) are stored in the reserved area of the MLC based flash memory. Only one the N sets is loaded to address correlation and page usage memory (ACPUM), which is a limited size random access memory (RAM). In one embodiment, static RAM (SRAM) is implemented for fast access time for the address correlation. LSA received together with the data transfer request dictates which one of the N sets of PLTPPUI is loaded into ACPUM. | 10-16-2008 |
20080256288 | MICROCOMPUTER, ELECTRONIC INSTRUMENT, AND FLASH MEMORY PROTECTION METHOD - A microcomputer includes a flash memory and a flash controller that controls access to the flash memory, the flash memory including a protection information storage section that stores protection information, the protection information indicating whether or not access to a given area of the flash memory is available; the flash controller including a flash protection section that performs a protection process relating to access to a given area of the flash memory based on the protection information; and the flash protection section performing the protection process relating to access to the flash memory when an access target is data. | 10-16-2008 |
20080256289 | MEMORY APPARATUS TO WRITE AND READ DATA, AND METHOD THEREOF - An apparatus and method of reading and writing data from and on a storage medium include receiving at least one of file information and file data from a host, generating a logical block address corresponding to the one of the file information and the file data, and writing the one of the file information and the file data at the generated logical block address | 10-16-2008 |
20080263264 | DATA ACCESS CONTROL SYSTEM AND METHOD OF MEMORY DEVICE - A data access control system of a memory includes a micro-processor, having a micro-controller, a command decoder, and a memory interface. The data access control system can be used to control display driving of a display system. The command decoder is used to decode the content of a data access command. A memory unit is configured into a first region for storing a first-type data being stored in a memory manner, and a second region for storing a second-type data being stored in a simulation manner of the memory. A bus is connected between the micro-processor and the memory unit, for performing data transmission. The micro-processor uses the memory interface to write data into the first region of the memory unit, and uses the command decoder to convert the nonvolatile data and write into the second region of the memory unit. | 10-23-2008 |
20080263265 | ADAPTIVE DYNAMIC READING OF FLASH MEMORIES - Each of a plurality of flash memory cells is programmed to a respective one of L≧2 threshold voltage states within a threshold voltage window. Values of parameters of threshold voltage functions are adjusted in accordance with comparisons of the threshold voltages of some or all of the cells to two or more of m≧2 threshold voltage intervals within the threshold voltage window. Reference voltages for reading the cells are selected based on the values. Alternatively, the m threshold voltage intervals span the threshold voltage window, and respective threshold voltage states are assigned to the cells based on numbers of cells whose threshold voltages are in the intervals, without re-reading the cells. | 10-23-2008 |
20080263266 | ADAPTIVE DYNAMIC READING OF FLASH MEMORIES - Each of a plurality of flash memory cells is programmed to a respective one of L≧2 threshold voltage states within a threshold voltage window. A histogram is constructed by determining how many of some or all of the cells have threshold voltages in each of two or more of m≧2 threshold voltage intervals within the threshold voltage window. Reference voltages for reading the cells are selected based on estimated values of shape parameters of the histogram. Alternatively, the cells are read relative to reference voltages that define m≧2 threshold voltage intervals that span the threshold voltage window, to determine numbers of at least a portion of the cells whose threshold voltages are in each of two or more of the threshold voltage intervals. Respective threshold voltage states are assigned to the cells based on the numbers without re-reading the cells. | 10-23-2008 |
20080270677 | Safe software revision for embedded systems - The present invention, in one embodiment includes identifying a first partition of an embedded program memory, reading a description associated with the first partition, identifying a second partition of an embedded program memory, reading a description associated with the second partition, comparing descriptions, selecting an embedded program memory partition using the comparison, and writing program code to the selected program memory partition. | 10-30-2008 |
20080270678 | COMMAND RESEQUENCING IN MEMORY OPERATIONS - Systems and processes may include a memory coupled to a memory controller. Command signals for performing memory access operations may be received. Attributes of the command signals, such as type, time lapsed since receipt, and relatedness to other command signals, may be determined. Command signals may be sequenced in a sequence of execution based on the attributes. Command signals may be executed in the sequence of execution. | 10-30-2008 |
20080270679 | CONTROL CIRCUIT OF FLASH MEMORY DEVICE AND METHOD OF OPERATING THE FLASH MEMORY DEVICE - Provided is a method of operating a flash memory device having a first area and a second area, in which a programmed state and an erased state of the first area are opposite to that of the second area. The method includes receiving a program command, inverting the program data when the received program command is a command for programming the second area, and programming the inverted program data into the second area. | 10-30-2008 |
20080270680 | Controller for Non-Volatile Memories and Methods of Operating the Memory Controller - A non-volatile memory system ( | 10-30-2008 |
20080270681 | Non-Volatile Memory with Block Erasable Locations - A main memory ( | 10-30-2008 |
20080270682 | METHOD FOR USING A MULTI-BIT CELL FLASH DEVICE IN A SYSTEM NOT DESIGNED FOR THE DEVICE - A computerized system is booted from a flash memory device configured to always operate one or more of its blocks only in a M-bit-per-cell mode and the rest of its blocks in a N>M-bit-per-cell mode. When the system is powered up, an initialization program is retrieved from the M-bit-per-cell block(s), corrected for errors using a first error correction method, and executed. Data accessed subsequently from the N-bit-per-cell blocks are corrected using an error correction method that corrects more errors per block than the first error correction method. | 10-30-2008 |
20080276035 | Wear Leveling - A reference memory location can be designated in a memory device. A memory location can be designated in response to storing data in the memory device. If the identified memory location is associated with the reference memory location then an allocated memory location can be designated relative to the reference memory location, and the allocated memory location can be leveled. | 11-06-2008 |
20080276036 | Memory with Block-Erasable Location - A non-volatile main memory ( | 11-06-2008 |
20080276037 | Method to Access Storage Device Through Universal Serial Bus - A method accessing a flash memory storage device through universal serial bus (USB) of the present invention includes a flash controller and a flash memory, wherein the method includes connecting the storage device to a USB interface of an electronic device; outputting a plurality of accessing instructions to the flash controller via the electronic device; deciding which data is needed to be temporarily saved in a cache memory and a priority of the accessing instructions according to the characteristic of the file system and the content of preceding instructions of the flash controller; and writing the data temporarily saved in the cache memory into the flash memory according to the priority of the flash controller. The objective of the method of the present invention is to enhance the operation efficiency of the storage device. | 11-06-2008 |
20080276038 | Storage system using flash memory modules logically grouped for wear-leveling and raid - A storage system using flash memories includes a storage controller and plural flash memory modules as storage media. Each flash memory module includes at least one flash memory chip and a memory controller for leveling erase counts of blocks belonging to the flash memory chip. The storage controller combines the plural flash memory modules into a first logical group, translates a first address used for accessing the flash memory modules belonging to the first logical group to a second address used for handling the first address in the storage controller, and combines the plural first logical groups into a second logical group. | 11-06-2008 |
20080282023 | Restoring storage devices based on flash memories and related circuit, system, and method - A solution for restoring operation of a storage device based on a flash memory is proposed. The storage device emulates a logical memory space (including a plurality of logical blocks each one having a plurality of logical sectors), which is mapped on a physical memory space of the flash memory (including a plurality of physical blocks each one having a plurality of physical sectors for storing different versions of the logical sectors). A corresponding method starts by detecting a plurality of conflicting physical blocks for a corrupted logical block (resulting from a breakdown of the storage device). The method continues by determining a plurality of validity indexes (indicative of the number of last versions of the logical sectors of the corrupted logical block that are stored in the conflicting physical blocks). One ore more of the conflicting physical blocks are selected according to the validity indexes. The selected conflicting physical blocks are then associated with the corrupted logical block. At the end, each one of the non-selected conflicting physical blocks is discarded. | 11-13-2008 |
20080282024 | Management of erase operations in storage devices based on flash memories - A method of freeing physical memory space in an electrically alterable memory that includes a plurality of physical memory blocks includes a plurality of physical memory pages. Each physical memory block may be individually erased as a whole, and which memory is used to emulate a random access logical memory space including a plurality of logical memory sectors by storing updated versions of a logical memory sector data into different physical memory pages. The method includes causing a most recent version of multiple versions of logical memory sector data, stored in physical pages of at least one physical memory block, to be copied into an unused physical memory block, marking the at least one physical memory block, and when the electrically alterable memory is idle, erasing the marked physical memory block. | 11-13-2008 |
20080282025 | Wear leveling in storage devices based on flash memories and related circuit, system, and method - A wear leveling solution is proposed for use in a storage device based on a flash memory. The flash memory includes a plurality of physical blocks, which are adapted to be erased individually. A corresponding method starts with the step for erasing one of the physical blocks. One of the physical blocks being allocated for storing data is selected; this operation is performed in response to the reaching of a threshold by an indication of a difference between a number of erasures of the erased physical block and a number of erasures of the selected physical block. At least the data of the selected physical block being valid is copied into the erased physical block. The selected physical block is then erased. | 11-13-2008 |
20080282026 | Bioprocess data management - A data management system for a biological process, comprising:
| 11-13-2008 |
20080288712 | ACCESSING METADATA WITH AN EXTERNAL HOST - Systems and processes may be used to retrieve metadata from a nonvolatile memory of a portable device and transmit the retrieved metadata to an external host. Metadata may be analyzed using the external host and/or at least a portion of the metadata may be modified based on the analysis. Modified metadata may be transmitted from the external host to a memory controller of the host. | 11-20-2008 |
20080288713 | FLASH-AWARE STORAGE OPTIMIZED FOR MOBILE AND EMBEDDED DBMS ON NAND FLASH MEMORY - Reliable storage for database management systems (DBMS) running on memory devices such as NAND type flash memory utilizes minimum I/O overhead and provides maximum data durability. A virtual page map is utilized between the flash memory and a page access component to record changes to the DBMS pages and prevent overwriting or data loss. There is no need for journaling and logging, and performance is increased by reducing the write and erase counts on the flash memory. The logical page numbers of the DBMS are mapped to physical page numbers in the page map, such that the virtual page map allocates an available page from the physical pages when changes to a page occur, and the updated information is stored in the allocated page. The allocated page number is mapped to the logical page number of the original page, thus maintaining a modified page representation while preventing physical in-place updates. | 11-20-2008 |
20080288714 | FILE STORAGE IN A COMPUTER SYSTEM WITH DIVERSE STORAGE MEDIA - A method for storing data in a computer having a magnetic hard disk drive (HDD) and an electronic solid-state drive (SSD). The method includes configuring the computer so that the HDD and the SSD are each independently accessible by an operating system of the computer. A plurality of files is received for storage by the computer. A predicted use profile of the computer is defined. A respective one of the HDD and the SDD is selected for the storage of each of the files responsively to the predicted use profile. | 11-20-2008 |
20080288715 | Memory Page Size Auto Detection - Methods and apparatuses are presented for memory page size auto detection. A method for automatically determining a page size of a memory device includes receiving page size extents of the memory device, determining a bus width of the memory device, detecting a number of pages having an automatic detection marker, and determining the page size of the memory device based upon the detected number of pages and the received page size extents. An apparatus for automatically determining page size detection includes logic for performing the above presented method. | 11-20-2008 |
20080288716 | STORAGE DEVICE - A storage device includes: a binary flash memory that has a first storage area and a capacity of storing two values per each cell; a multivalued flash memory that has a second storage area and a capacity of storing at least three values per each cell; and a controller configured to arrange the first storage area ahead of the second storage area, logically combine the first storage area with the second storage area to form a single combined storage area, and perform data reading and data writing from and into the combined storage area. Data management information is stored in a head of the combined storage area according to a predetermined file system. The storage device of this arrangement has the advantages of both an SLC flash memory and an MLC flash memory. | 11-20-2008 |
20080288717 | SINGLE SECTOR WRITE OPERATION IN FLASH MEMORY - A flash storage device having improved write performance is provided. The device includes a storage block having a plurality of physical pages and a controller for mapping the plurality of physical pages to a plurality of logical addresses and for writing data to the plurality of physical pages. When updating data previously written to one of the plurality of logical addresses, the controller is configured to write the updated data to a second physical page which is mapped to the logical address. Each of the logical addresses may be associated with a pointer field, which is for storing a pointer value indicating the invalidity of a physical page and/or the location of another physical page. | 11-20-2008 |
20080294834 | SOLID STATE STORAGE SUBSYSTEM FOR EMBEDDED APPLICATIONS - A non-volatile storage subsystem solution is provided for embedded applications. The storage subsystem is preferably designed to communicate with the host system using a signal interface, such as a USB or SATA interface, that uses substantially fewer signal lines than the IDE interface traditionally used for embedded applications. Thus, the amount of board real estate used to carry interface signals in the host system is reduced. To further reduce board real estate, the host system may include a processor that includes an integrated controller (e.g., a USB or SATA controller) corresponding to the host-subsystem signal interface. The storage subsystem may plug into, and lock to, an internal connector on a circuit board of the host system. | 11-27-2008 |
20080294835 | SOLID STATE STORAGE SUBSYSTEM FOR EMBEDDED APPLICATIONS - A non-volatile storage subsystem solution is provided for embedded applications. The storage subsystem is preferably designed to communicate with the host system using a signal interface, such as a USB or SATA interface, that uses substantially fewer signal lines than the IDE interface traditionally used for embedded applications. Thus, the amount of board real estate used to carry interface signals in the host system is reduced. To further reduce board real estate, the host system may include a processor that includes an integrated controller (e.g., a USB or SATA controller) corresponding to the host-subsystem signal interface. The storage subsystem may plug into, and lock to, an internal connector on a circuit board of the host system. | 11-27-2008 |
20080294836 | NAND flash memory system with programmable connections between a NAND flash memory controller and a plurality of NAND flash memory modules and method thereof - A method and related system for programming connections between a NAND flash memory controller and a plurality of NAND flash memory modules includes the NAND flash memory controller generating a switch signal and a swap signal according to a condition of one of the plurality of NAND flash memory modules, a remap module selectively coupling the plurality of NAND flash memory modules to the NAND flash memory controller according to the switch signal, and a swap module selectively coupling the plurality of NAND flash memory modules to the NAND flash memory controller according to the swap signal. | 11-27-2008 |
20080294837 | MEMORY CONTROLLER FOR CONTROLLING A NON-VOLATILE SEMICONDUCTOR MEMORY AND MEMORY SYSTEM - A memory controller includes a host interface, a holding circuit and a control circuit. The memory controller controls a semiconductor memory. The semiconductor memory includes memory blocks. The host interface is connectable to a host apparatus and receivable of write data and an address. The holding circuit is capable of holding the address. The control circuit searches information indicating an existence of a parent directory from the write data, and holds the address in the holding circuit when the information is detected. The control circuit successively writes the write data to the same memory block when a new write access is made with respect to the same address as the address held in the holding circuit. | 11-27-2008 |
20080294838 | UNIVERSAL BOOT LOADER USING PROGRAMMABLE ON-CHIP NON-VOLATILE MEMORY - In one embodiment, an IC system includes a system on a chip (SoC) adapted to load boot-up code from an external NAND flash memory, which stores the boot-up code. The SoC has a processor, an internal ROM including boot-loading code, an operating RAM, a NAND flash controller (NFC), and an OTP memory. At some point after SoC manufacture, the OTP memory is programmed with parameters needed for communication between the NFC and the external NAND flash memory. This provides a system designer flexibility in choosing a type of external NAND flash memory for the IC system. During SoC power-up, the NFC is initialized with the communication parameters, thereby allowing the NFC to control the NAND flash memory. The boot-loading code directs the processor to load the boot-up code from the external NAND memory onto the operating RAM. The processor then executes the boot-up code from the operating RAM. | 11-27-2008 |
20080301355 | FLASH MEMORY INFORMATION READING/WRITING METHOD AND STORAGE DEVICE USING THE SAME - A flash memory information read/write method in which an external resource such as host, external memory, EEPROM, or external controller is used to read and update new flash memory information after fabrication of a flash memory device, enabling the new flash memory information to be written in a predetermined address in a flash memory module of the flash device by a controller of the flash memory device, so that every flash memory device that has an erroneous or damaged factory data or information is still usable, and the flash memory controller provider needs not to continuously develop new firmware controllers for different flash memories. | 12-04-2008 |
20080301356 | FAST WRITING NON-VOLATILE MEMORY - A method writes data in a non-volatile memory comprising memory cells that are erased before being written. The method comprises the steps of providing a main non-volatile memory area comprising target pages, providing an auxiliary non-volatile memory area comprising auxiliary pages, providing a look-up table to associate to an address of invalid target page an address of valid auxiliary page, and, in response to a command for writing a piece of data in a target page writing the piece of data as well as the address of the target page in a first erased auxiliary page, invalidating the target page, and updating the look-up table. | 12-04-2008 |
20080301357 | NON-VOLATILE MEMORY WITH AUXILIARY ROTATING SECTORS - A method writes data in a non-volatile memory. The method provides, in the memory, a non-volatile main memory area comprising target pages, a non-volatile auxiliary memory area comprising auxiliary pages, and, in the auxiliary memory area: a current sector comprising erased auxiliary pages usable to write data, a save sector comprising auxiliary pages comprising data linked to target pages to be erased or being erased, a transfer sector comprising auxiliary pages including data to be transferred to erased target pages, and an unavailable sector comprising auxiliary pages to be erased or being erased. The method can be applied in particular to FLASH memories. | 12-04-2008 |
20080301358 | Electronic device that Downloads Operational Firmware from an External Host - An electronic device comprises an interface unit, a control circuit and a microprocessor. The interface unit receives a first operational firmware from a host. The control circuit transfers the first operational firmware to a memory. The microprocessor executes the first operational firmware which stored in the memory. The microprocessor controls operations of the electronic device according to the first operational firmware. And the control circuit is electrically coupled to a non-volatile memory which stores a second operational firmware for performing a specific function also performed by the first operational firmware. | 12-04-2008 |
20080301359 | Non-Volatile Memory and Method With Multi-Stream Updating - In a memory that is programmable page by page and each page having multiple sectors that are once-programmable, even if successive writes are sequential, the data recorded to an update block may be fragmented and non-sequential. Instead of recording update data to an update block, the data is being recorded in at least two interleaving streams. When a full page of data is available, it is recorded to the update block. Otherwise, it is temporarily recorded to the scratch pad block until a full page of data becomes available to be transferred to the update block. Preferably, a pipeline operation allows the recording to the update block to be set up as soon as the host write command indicates a full page could be written. If the actual write data is incomplete due to interruptions, the setup will be canceled and recording is made to the scratch pad block instead. | 12-04-2008 |
20080307154 | System and Method for Dual-Ported I2C Flash Memory - A method for emulating a dual-port I2C device includes monitoring a bus for I2C traffic. A system receives an I2C interrupt on the bus. The system determines whether the received I2C interrupt is one of either a hardware interrupt or a software interrupt. In the event the received I2C interrupt is a hardware interrupt, the system responds to the hardware interrupt, and accesses a flash memory for read/write operation based on the hardware interrupt. In the event the received I2C interrupt is a software interrupt, the system responds to the software interrupt, and accesses a flash memory for read/write operation based on the software interrupt. | 12-11-2008 |
20080307155 | Method of Interfacing A Host Operating Through A Logical Address Space With A Direct File STorage Medium - A method and system for interfacing a system operating through a logical address space with a direct file storage (DFS) medium is disclosed. The method includes receiving data associated with addresses in a logical block address (LBA) format from a host system and generating file objects manageable by the DFS medium based on a determination of the correlation of the LBA data to host file data. The memory system includes non-volatile memory using the DFS format, an interface for receiving LBA format data, and a controller configured to communicate with the host via an LBA interface and generate file objects from the LBA format data correlated to the host application files usable by the memory system. | 12-11-2008 |
20080307156 | System For Interfacing A Host Operating Through A Logical Address Space With A Direct File Storage Medium - A method and system for interfacing a system operating through a logical address space with a direct file storage (DFS) medium is disclosed. The method includes receiving data associated with addresses in a logical block address (LBA) format from a host system and generating file objects manageable by the DFS medium based on a determination of the correlation of the LBA data to host file data. The memory system includes non-volatile memory using the DFS format, an interface for receiving LBA format data, and a controller configured to communicate with the host via an LBA interface and generate file objects from the LBA format data correlated to the host application files usable by the memory system. | 12-11-2008 |
20080307157 | Method and system for updating firmware of microcontroller - A system for updating firmware of a microcontroller includes a serial peripheral interface (SPI), an inter integrated Circuit (I | 12-11-2008 |
20080307158 | METHOD AND APPARATUS FOR PROVIDING DATA TYPE AND HOST FILE INFORMATION TO A MASS STORAGE SYSTEM - A method and system for providing advance data type information to a mass storage system is disclosed. The method may include a host system providing host file information, such as a host file identifier and/or a data type, to a memory system in addition to LBA format data. The system may include a processor, a memory system interface and a host file system operative on the processor to identify and provide host file information and/or data type information to the memory system along with LBA format data. | 12-11-2008 |
20080307159 | Method and control device for operating a non-volatile memory, in particular for use in motor vehicles - A method for the consecutive writing of performance quantity data to a non-volatile memory, in particular in a control device in a motor vehicle. The method encompasses the operations of determining a write address, which defines an address space for the writing of a performance quantity datum to be written, the address space being directly contiguous with a memory area occupied by a previously written performance quantity datum, and of writing the performance quantity datum to be written, to the address space of the non-volatile memory defined by the write address. In the determination operation, the write address corresponds directly to an address datum assigned to the most recently written performance quantity data, which is stored in a referencing datum in the non-volatile memory, or it is determined therefrom with the aid of an address offset that is independent of the size of the previously written performance quantity data. | 12-11-2008 |
20080313387 | SEMICONDUCTOR MEMORY DEVICE CAPABLE OF READING DATA RELIABLY - A control unit reads data from a plurality of memory cells connected to one of the word lines in a read operation at a first level CR generated by a voltage generator circuit and in a read operation at a second level CR−x and finds the number of cells included between the first level and the second level from the data and, if the number is equal to or smaller than a specified value, determines the result of the read operation at the first level to be read data. | 12-18-2008 |
20080313388 | ELECTRONIC DATA FLASH CARD WITH VARIOUS FLASH MEMORY CELLS - An electronic data flash card is accessible by a host computer, and includes a processing unit connected to a flash memory device that stores a data file, and an input-output interface circuit activated so as to establish a communication with the host computer. In an embodiment, the electronic data flash card uses a USB input/output interface circuit for communication with the host computer. A flash memory controller includes an index for converting logical addresses sent by the host computer into physical addresses associated with sectors of the flash memory device. The index is controlled by arbitration logic referencing to values from various look up tables and valid data stored in the flash memory device. The flash memory controller further includes a first-in-first-out unit (FIFO) for recycling obsolete sectors of the flash memory device in the background process so that they are available for reprogramming. | 12-18-2008 |
20080313389 | ELECTRONIC DATA FLASH CARD WITH VARIOUS FLASH MEMORY CELLS - An electronic data flash card is accessible by a host computer, and includes a processing unit connected to a flash memory device that stores a data file, and an input-output interface circuit activated so as to establish a communication with the host computer. In an embodiment, the electronic data flash card uses a USB input/output interface circuit for communication with the host computer. A flash memory controller includes an index for converting logical addresses sent by the host computer into physical addresses associated with sectors of the flash memory device. The index is controlled by arbitration logic referencing to values from various look up tables and valid data stored in the flash memory device. The flash memory controller further includes a first-in-first-out unit (FIFO) for recycling obsolete sectors of the flash memory device in the background process so that they are available for reprogramming. | 12-18-2008 |
20080313390 | Method and System for Presenting an Executing Status of a Memory Card - A system and a method for presenting an executing status of a memory card are provided. The system comprises a processing apparatus and an access device. The processing apparatus stores an application program having a plurality of icons. The access device connects the memory card and the processing apparatus. The processing apparatus sends a reading command to the memory card via the access device. The memory card sends executing information in reply after receiving the reading command. Finally, the processing apparatus analyzes the executing information of the memory card and presents a corresponding icon through the application program in association with the analytic result. | 12-18-2008 |
20080313391 | SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR DEVICE - A semiconductor memory device, including: a cell array block including a plurality of memory cells arranged therein; and a controller, wherein the controller controls the semiconductor memory device so that: an operation of reading out data from a second region in the cell array block is initiated before completion of an operation of outputting data read out from a first region in the cell array block; and the data read out from the second region is output successively after the completion of the operation of outputting data read out from the first region. | 12-18-2008 |
20080313392 | Data controlled power supply apparatus - A power supply, and a method of controlling the power supply, in which more or less power capacity of the power supply is activated depending on the state of a digital data signal on a data bus. The power supply has a control circuit which detects the number of “zero” bits present on the data bus, and responsively activates one or more of a plurality of power supply circuits such as charge pump circuits. The outputs of the charge pump circuits are mutually connected to a driver adapted to program memory cells of a flash memory circuit. | 12-18-2008 |
20080320206 | Nonvolatile Memory Card and Configuration Conversion Adapter - A nonvolatile memory card, including interface parts for plural kinds of memory cards; interface controllers corresponding to the interface parts for corresponding memory cards; and a switch configured to select a single one of the interface controllers. | 12-25-2008 |
20080320207 | MULTI-LEVEL CELL (MLC) DUAL PERSONALITY EXTENDED FIBER OPTIC FLASH MEMORY DEVICE - A multi-level cell (MLC) dual-personality extended fiber optic flash drive includes a MLC dual-personality extended fiber optic Universal Serial Bus (USB) plug connector connected to a dual-personality extended fiber optic flash drive and being removably connectable to a host. The connector is adaptable to receive electrical data and optical data. A transceiver, located on the flash drive, is operative to convert received electrical data to optical data or to convert received optical data to electrical data. | 12-25-2008 |
20080320208 | SEMICONDUCTOR DEVICE AND METHOD FOR CONTROLLING THEREOF - A semiconductor device includes a first nonvolatile storage area including a plurality of sectors, a second nonvolatile storage area, a third nonvolatile storage area located in the first nonvolatile storage area, a fourth nonvolatile storage area located in the second nonvolatile storage area, and a control portion selecting one of a first mode and a second mode. In first mode, sectors where the third nonvolatile storage area is not located in the first nonvolatile storage area are used as a main storage area, and the second nonvolatile storage area is used to store a program or data that is read before the first nonvolatile storage area is accessed, the third nonvolatile storage area being used to store control information that controls writing, reading, and erasing of data involved in the first nonvolatile storage area or the second nonvolatile storage area. In the second mode, the first nonvolatile storage area is used as the main storage area, and the fourth nonvolatile storage area is used to store the control information. | 12-25-2008 |
20080320209 | High Performance and Endurance Non-volatile Memory Based Storage Systems - High performance and endurance non-volatile memory (NVM) based storage systems are disclosed. According to one aspect of the present invention, a NVM based storage system comprises at least one intelligent NVM device. Each intelligent NVM device includes a control interface logic and NVM. Logical-to-physical address conversion is performed within the control interface logic, thereby eliminating the need of address conversion in a storage system level controller. In another aspect, a volatile memory buffer together with corresponding volatile memory controller and phase-locked loop circuit is included in a NVM based storage system. The volatile memory buffer is partitioned to two parts: a command queue; and one or more page buffers. The command queue is configured to hold received data transfer commands by the storage protocol interface bridge, while the page buffers are configured to hold data to be transmitted between the host computer and the at least one NVM device. | 12-25-2008 |
20080320210 | Data management systems, methods and computer program products using a phase-change random access memory for selective data maintenance - A data management system includes a data processor configured to provide a file system module configured to store first data in a flash memory in block units and a filter layer module configured to receive second data from the file system module and to store the second data in a phase-change random access memory (PRAM) in sub-block units. The filter layer module may be configured to identify difference data in the second data received from the file system module by comparing the received second data and third data stored in the PRAM, and to write the identified difference data to the PRAM. The second data may include file metadata and the first data may include data other than file metadata. The sub-block units may be byte units. | 12-25-2008 |
20080320211 | NONVOLATILE MEMORY CONTROL DEVICE, NONVOLATILE MEMORY CONTROL METHOD, AND STORAGE DEVICE - According to an embodiment of the present invention is to increase the number of arbitrarily available physical blocks in a nonvolatile memory device. The device comprises a file system control section which analyzes a file allocation table (FAT) to identify an unused logical block, a logical/physical block address conversion table management section which uses a table of a logical/physical block address conversion table information section to obtain a first physical block corresponding to the unused logical block and releases the association between the first physical block and the unused logical block, and a physical block address information management section which registers the first physical block in a physical block address information section as an arbitrarily available second physical block. | 12-25-2008 |
20080320212 | CONTROL DEVICE AND CONTROL METHOD OF NONVOLATILE MEMORY AND STORAGE DEVICE - According to one embodiment, the control device according to an embodiment of the present invention, facilitates and speeds up averaging processing of the number of erases of a physical block (exchange processing of a physical block) of a nonvolatile memory. The device includes a file system control section that analyzes a file system of a nonvolatile memory and identifies a logical block of a read-only file, a logical/physical block address conversion table management section that obtains a first physical block corresponded to the logical block, and a physical block information management section that selects a second physical block that can be optionally used. Further, the device includes a physical block information modification section that moves data of the first physical block to the second physical block. | 12-25-2008 |
20080320213 | CONTROL DEVICE OF NONVOLATILE MEMORY AND CONTROL METHOD THEREOF, AND STORAGE DEVICE - According to one embodiment, the overall information processing time can be shortened. There are provided (1) a logical/physical block address conversion table information section that associates a logical block address of a logical address space with a physical block address of a nonvolatile memory device, (2) a physical block use state management section and a physical block erase count management section to read out erase count information from a physical block of which the logical block address and the physical block address are not associated, and a physical block that satisfies a predetermined condition set related to the erase count information is selected as a selected physical block, and (3) a logical/physical block address conversion table management section that registers a physical block address of the selected physical block in the logical/physical block address conversion table. | 12-25-2008 |
20080320214 | Multi-Level Controller with Smart Storage Transfer Manager for Interleaving Multiple Single-Chip Flash Memory Devices - A solid-state disk (SSD) has a smart storage switch with a smart storage transaction manager that re-orders host commands for accessing downstream single-chip flash-memory devices. Each single-chip flash-memory device has a lower-level controller that converts logical block addresses (LBA) to physical block addresses (PBA) that access flash memory blocks in the single-chip flash-memory device. Wear-leveling and bad block remapping are preformed by each single-chip flash-memory device, and at a higher level by a virtual storage processor in the smart storage switch. Virtual storage bridges between the smart storage transaction manager and the single-chip flash-memory devices bridge LBA transactions over LBA buses to the single-chip flash-memory devices. Data striping and interleaving among multiple channels of the single-chip flash-memory device is controlled at a high level by the smart storage transaction manager, while further interleaving and remapping may be performed within each single-chip flash-memory device. | 12-25-2008 |
20090006718 | SYSTEM AND METHOD FOR PROGRAMMABLE BANK SELECTION FOR BANKED MEMORY SUBSYSTEMS - A programmable memory system and method for enabling one or more processor devices access to shared memory in a computing environment, the shared memory including one or more memory storage structures having addressable locations for storing data. The system comprises: one or more first logic devices associated with a respective one or more processor devices, each first logic device for receiving physical memory address signals and programmable for generating a respective memory storage structure select signal upon receipt of pre-determined address bit values at selected physical memory address bit locations; and, a second logic device responsive to each the respective select signal for generating an address signal used for selecting a memory storage structure for processor access. The system thus enables each processor device of a computing environment memory storage access distributed across the one or more memory storage structures. | 01-01-2009 |
20090006719 | SCHEDULING METHODS OF PHASED GARBAGE COLLECTION AND HOUSE KEEPING OPERATIONS IN A FLASH MEMORY SYSTEM - An embodiment of a non-volatile memory storage system comprises a memory controller, and a flash memory module. The memory controller manages the storage operations of the flash memory module. The memory controller is configured to assign a priority level to one or more types of house keeping operations that may be higher than a priority level of one or more types of commands received by a host coupled to the storage system, and to service all operations required of the flash memory module according to priority. | 01-01-2009 |
20090006720 | SCHEDULING PHASED GARBAGE COLLECTION AND HOUSE KEEPING OPERATIONS IN A FLASH MEMORY SYSTEM - An embodiment of a non-volatile memory storage system comprises a memory controller, and a flash memory module. The memory controller manages the storage operations of the flash memory module. The memory controller is configured to assign a priority level to one or more types of house keeping operations that may be higher than a priority level of one or more types of commands received by a host coupled to the storage system, and to service all operations required of the flash memory module according to priority. | 01-01-2009 |
20090006721 | METHODS OF AUTO STARTING WITH PORTABLE MASS STORAGE DEVICE - A portable flash memory storage device such as a memory card can configure a host device upon insertion. The configuration may specify applications or other sequences of operations to be executed by the host upon insertion of the card. Files on the card may be associated with an appropriate application and then automatically opened with the appropriate application. A secure configuration may override a more freely modifiable configuration in certain embodiments. | 01-01-2009 |
20090006722 | AUTO START CONFIGURATION WITH PORTABLE MASS STORAGE DEVICE - A portable flash memory storage device such as a memory card can configure a host device upon insertion. The configuration may specify applications or other sequences of operations to be executed by the host upon insertion of the card. Files on the card may be associated with an appropriate application and then automatically opened with the appropriate application. A secure configuration may override a more freely modifiable configuration in certain embodiments. | 01-01-2009 |
20090006723 | METHOD FOR COMMUNICATING WITH A NON-VOLATILE MEMORY STORAGE DEVICE - Method for a storage device is provided. The method includes interpreting a command from a host system, wherein a command parser module for a storage device interprets the command; and extracting information regarding an operation from the command, wherein the command parser module extracts the information and interfaces with the host system. | 01-01-2009 |
20090006724 | Method of Storing and Accessing Header Data From Memory - Methods of storing and accessing data using a header portion of a file are disclosed. In an embodiment, a method of storing content in a non-volatile memory is disclosed. The method includes reading a content file including media content and including a trailer, storing information related to the trailer together with secure data in a header portion of a file, and storing the file to a storage element of the non-volatile memory or a memory area of a host device coupled to the non-volatile memory device. | 01-01-2009 |
20090006725 | MEMORY DEVICE - A memory device includes a nonvolatile memory and a controller. The nonvolatile memory includes a storage area having a plurality of memory blocks each including a plurality of nonvolatile memory cells, and a buffer including a plurality of nonvolatile memory cells and configured to temporarily store data, and in which data is erased for each block. If a size of write data related to one write command is not more than a predetermined size, the controller writes the write data to the buffer. | 01-01-2009 |
20090006726 | MULTIPLE ADAPTER FOR FLASH DRIVE AND ACCESS METHOD FOR SAME - A multiple adapter is used for assembling a plurality of flash drives. The multiple adapter includes a multiple expansion port, a detector, a file manager, and a controller. The multiple expansion port coupled to the flash drives. The detector is coupled to the multiple expansion port for detecting store information of the flash drives. The file manager is coupled to the multiple expansion port and the detector for receiving the store information and calculating total memory capacity and total spare capacity of the flash drives. The controller is used for controlling the detector and the file manager. A writing procedure and a reading procedure of an access method are also provided. | 01-01-2009 |
20090006727 | SYSTEM PROGRAMMING PROCESS FOR AT LEAST ONE NON-VOLATILE MEANS OF STORAGE OF A WIRELESS COMMUNICATION DEVICE, CORRESPONDING PROGRAMMING EQUIPMENT AND PACKET TO BE DOWNLOADED - It is proposed an in-system programming process, by programming equipment of at least one non-volatile storage memory of a communication device. The process includes the following steps: transmission, by the programming equipment to the communication device, of at least one extension file; transmission, by at least one of the extension files, called an enlightening extension file, of at least one first item of configuration information for the communication device; selection, by the programming equipment depending on the first item(s) of configuration information for the communication device of at least one data file associated to an internal application of the communication device; and transmission, by the programming equipment to the storage memory, of the selected data file(s). | 01-01-2009 |
20090013122 | Transaction Method for Managing the Storing of Persistent Data in a Transaction Stack - A transaction method manages the storing of persistent data to be stored in at least one memory region of a non-volatile memory device before the execution of update operations that involve portions of the persistent data. Values of the persistent data are stored in a transaction stack that includes a plurality of transaction entries before the beginning of the update operations so that the memory regions involved in such an update are restored in a consistent state if an unexpected event occurs. A push extreme instruction reads from the memory cells a remaining portion of the persistent data that is not involved in the update operation, and stores the remaining portion in a subset of the transaction entries. The push extreme instruction is executed instead of a push instruction when the restoring of the portion of persistent data is not required after the unexpected event. The restoring corresponds to the values that the persistent data had before the beginning of the update operations. | 01-08-2009 |
20090013123 | Storage Bridge and Storage Device and Method Applying the Storage Bridge - A storage bridge includes a flash memory register unit for temporarily storing data and for storing data of a storage unit when a host unit stores data to the storage unit, and a transmission interface control unit coupled to the flash memory register unit for controlling operations of the flash memory register unit. | 01-08-2009 |
20090013124 | ROM CODE PATCH METHOD - The present invention relates to a method of replacing a sequence of one or more commands from a routine in a ROM of a device using a RAM. The method allows replacing part of a routine, for example a single command, while continuing to use the rest of the commands of the routine from the ROM. In an exemplary embodiment of the invention, a single command is replaced by adding only two additional commands or four additional commands as overhead in the replacement process. | 01-08-2009 |
20090013125 | MEMORY CARD - A memory device is provided which is connected to operate with power and clocks supplied from a host apparatus. The memory device includes external terminals, a flash memory chip to store data, an IC chip to process data; and a controller chip connected with the external terminals, the flash memory chip and the IC chip. The flash memory chip, the IC chip and the controller chip are discrete chips. The controller chip writes data inputted from the host apparatus into the flash memory chip or the IC chip and transfers data read from the flash memory chip or the IC chip to the host apparatus, based upon commands from the host apparatus. | 01-08-2009 |
20090013126 | METHOD AND DEVICES FOR COMPRESSING DELTA LOG USING FLASH TRANSACTIONS - Each received piece of configuration data is added at a next currently free location in a volatile buffer. The contents of the volatile buffer are compressed after adding each received piece of configuration data. The compression result is stored in a non-volatile flash memory. If the compression result was shorter than a limit, it is allowed to be overwritten in the flash memory by a next compression result. If the compression result was longer than the limit, it is stored in the flash memory and the next compression result is directed to a different location in the flash memory. | 01-08-2009 |
20090019211 | Establishing A Redundant Array Of Inexpensive Drives - Establishing, with a USB RAID controller connected to a USB hub and with USB mass storage devices connected to the USB hub and the USB RAID controller through USB connectors, the USB hub controlled by a USB host controller, a RAID array including enumerating, by the USB host controller, the USB mass storage devices, including discovering the USB RAID controller; receiving, by the USB RAID controller from a RAID console application program, an instruction to designate USB connectors as RAIDable USB connectors, the instruction including selected USB connectors; designating, by the USB RAID controller, the selected USB connectors as RAIDable USB connectors; enumerating by the USB RAID controller the USB mass storage devices connected to the RAIDable USB connectors; configuring by the USB RAID controller a RAID array, the RAID array including the USB mass storage devices; and storing, through the USB RAID controller, computer data on the RAID array. | 01-15-2009 |
20090019212 | Flash disk of phone book - The present invention provides a flash disk of phone book, it comprises an autorun part, a phone book part and a free use part. | 01-15-2009 |
20090019213 | Method and control unit for operating a non-volatile memory, in particular for use in motor vehicles - A method for operating a nonvolatile memory, wherein the nonvolatile memory is configured to read out an erased data pattern when reading out a memory area that has not been written in, and performing the operations or tasks of setting a memory area for storing operating variable data that are to be written, providing operating variable data to be written in the nonvolatile memory, checking whether the operating variable data to be written correspond to the erased data pattern of the memory area set, writing the operating variable data in the determined memory area if the operating variable data that are to be written are different from the erased data pattern, and if the operating variable data that are to be written correspond to the erased data pattern, preventing writing the operating variable data in the determined memory area. | 01-15-2009 |
20090019214 | REGISTER HAVING SECURITY FUNCTION AND COMPUTER SYSTEM INCLUDING THE SAME - A register having a security function is provided. The register includes: a write security unit and a storage unit. The write security unit outputs a first control signal to control whether a write operation is permissible, in response to a write signal, an address signal, and a write permission signal. The storage unit writes and stores input data, in response to the first control signal. The write permission signal is received from an external source and indicates whether to protect the written data. | 01-15-2009 |
20090019215 | Method and device for performing cache reading - Method and device for reading data from a semiconductor device, where tR is a read operation time, tT is a buffer transfer time, and tH is a host transfer time, where at least two of tR, tT, and tH may be overlapped to reduce a total transfer time. | 01-15-2009 |
20090019216 | Disk drive device and method for saving a table for managing data in non-volatile semiconductor memory in disk drive device - Embodiments of the present invention help to suppress adverse effects on the host computer operation caused by saving a segment table. According to one embodiment, a hard disk drive (HDD) creates a segment table to associate addresses of user data in a flash memory with LBAs in a magnetic disk. The HDD updates the segment table in a DRAM and saves it to the flash memory at a specific timing. The HDD creates a journal indicating an update of the segment table and saves it to the flash memory. The segment table and the journal in the flash memory enable the latest segment table to be restored. If the HDD receives a predetermined command from a host computer, it saves the segment table in the DRAM into the flash memory. | 01-15-2009 |
20090019217 | Non-Volatile Memory And Method With Memory Planes Alignment - A non-volatile memory is constituted from a set of memory planes, each having its own set of read/write circuits so that the memory planes can operate in parallel. The memory is further organized into erasable blocks, each for storing a logical group of logical units of data. In updating a logical unit, all versions of a logical unit are maintained in the same plane as the original. Preferably, all versions of a logical unit are aligned within a plane so that they are all serviced by the same set of sensing circuits. In a subsequent garbage collection operation, the latest version of the logical unit need not be retrieved from a different plane or a different set of sensing circuits, otherwise resulting in reduced performance. In one embodiment, any gaps left after alignment are padded by copying latest versions of logical units in sequential order thereto. | 01-15-2009 |
20090019218 | Non-Volatile Memory And Method With Non-Sequential Update Block Management - In a nonvolatile memory with block management system that supports update blocks with non-sequential logical units, an index of the logical units in a non-sequential update block is buffered in RAM and stored periodically into the nonvolatile memory. In one embodiment, the index is stored in a block dedicated for storing indices. In another embodiment, the index is stored in the update block itself. In yet another embodiment, the index is stored in the header of each logical unit. In another aspect, the logical units written after the last index update but before the next have their indexing information stored in the header of each logical unit. In this way, after a power outage, the location of recently written logical units can be determined without having to perform a scanning during initialization. In yet another aspect, a block is managed as partially sequential and partially non-sequential, directed to more than one logical subgroup. | 01-15-2009 |
20090024786 | External storage device - An external storage device includes a hard-drive, a flash memory, and a memory arrangement unit. The memory arrangement determines if the tag of the data accessed by a computer stored in the tag list of the memory arrangement unit and controls the hard-drive and the flash memory according to the result of the determination. | 01-22-2009 |
20090024787 | Data writing method and apparatus - Provided are a data writing method and apparatus. In the data writing method, data that is to be written to a first storage medium and the address of the first storage medium are received, data is read from the address of the first storage medium, the received data is compared with the read data, and then the received data is stored in either the first storage medium or a second storage medium, depending on the comparison result. Accordingly, it is possible to reduce the time required for data writing and to increase the lifetime of a storage medium. | 01-22-2009 |
20090024788 | PORTABLE ELECTRONIC DEVICE AND DATA CONTROL METHOD - A portable electronic device is provided with a storage section which stores various pieces of information and a transmitter/receiver section which transmits and receives data to and from external equipment. It is determined whether or not data paired with write data contained in a write command is stored by the storage section when the write command is received by the transmitter/receiver section, the write data is written to the storage section if it is concluded that the data paired with the write data contained in the write command is stored by the storage section, and the transmitter/receiver section is caused to transmit a result of determination on abnormality to the external equipment if it is concluded that the data paired with the write data contained in the write command is not stored by the storage section. | 01-22-2009 |
20090031073 | MULTI-INTERFACE AND MULTI-BUS STRUCTURED SOLID-STATE STORAGE SUBSYSTEM - A solid-state storage subsystem, such as a non-volatile memory card or drive, includes multiple interfaces and a memory area storing information used by a data arbiter to prioritize data commands received through the interfaces. As one example, the information may store a priority ranking of multiple host systems that are connected to the solid-state storage subsystem, such that the data arbiter may process concurrently received data transfer commands serially according to their priority ranking. A host software component may be configured to store and modify the priority control information in solid-state storage subsystem's memory area. | 01-29-2009 |
20090031074 | Multi-level Cell Flash Memory and Method of Programming the Same - Provided is a flash memory having a multi-level cell (MLC) and a method of programming the same. The method includes identifying a set of first patterns from input data, determining whether there is a set of second patterns stored within the flash memory that is of a number substantially similar to the number of the first patterns, and programming the input data as a most significant bit (MSB) in a location of the flash memory where the identified set of second patterns is stored when it is determined that there is a set of second patterns stored within the flash memory that is of a number substantially similar to the number of first patterns. | 01-29-2009 |
20090031075 | Non-volatile memory device and a method of programming the same - Provided are a non-volatile memory device and a method of programming the same. The method includes: performing a program operation; performing a program verify read operation; and performing a pass/fail determine operation simultaneously with one of a verify recovery operation and a bit line setup operation, after the performing of the program verify read operation. | 01-29-2009 |
20090031076 | Method for Managing Flash Memory - A method for managing a flash memory, a method for leveling the wear of blocks in a flash memory, and a method for managing a file system for a flash memory are provided. The method for managing a flash memory includes: if changing of data of a data block recorded in a data area is requested, recording the data block having changed data in an alternative area and recording mapping information of the data block recorded in the alternative area in a mapping area; and if changing of data of the data block recorded in the alternative area is requested, recording a data block having changed data in the data area and deleting the mapping information recorded in the alternative area from the mapping area. | 01-29-2009 |
20090037643 | Semiconductor memory device including control means and memory system - A semiconductor memory device includes a first nonvolatile memory which has a first external interface and is capable of recording 1-bit data in one memory cell, a second nonvolatile memory which has a test terminal interface and is capable of recording a plurality of data in one memory cell, and a control unit which has a second external interface and is configured to control a physical state of an inside of the second nonvolatile memory. | 02-05-2009 |
20090037644 | System and Method of Storing Reliability Data - Systems and methods of storing error correction data are provided. A method may include storing data at a first memory having a first non-volatile memory type. The method may also include determining error correction data related to the stored data. The method may further include storing the error correction data at a second memory having a second non-volatile memory type. The first non-volatile memory may have a slower random access capability than the second non-volatile memory. | 02-05-2009 |
20090037645 | NON-VOLATILE MEMORY DEVICE AND DATA ACCESS CIRCUIT AND DATA ACCESS METHOD - A non-volatile memory device, a data access circuit and a data access method are provided. The non-volatile memory device includes a main controller, a plurality of sub-controllers and a plurality of memory blocks. The sub-controllers are coupled to the main controller and are used to execute the tasks assigned by the main controller. The memory blocks are respectively coupled to the corresponding sub-controllers. The main controller is used to divide a received main data into a plurality of sub-data, and the sub-data are respectively saved in the memory blocks through corresponding sub-controllers. Therefore, the data access speed of the non-volatile memory device is substantially speeded-up. | 02-05-2009 |
20090037646 | Method of using a flash memory for a circular buffer - A method of using a FLASH memory for a circular buffer, and the FLASH memory for same, the method including one or more of the following steps in various exemplary embodiments: providing a circular buffer having a plurality of sectors; designating a byte of each of the plurality of sectors of the circular buffer as a binary state indicator; saving data sequentially in the circular buffer; and cycling through a plurality of sectors of the binary state indicators, such as empty or erase, last, middle and first, as the data is sequentially saved in the circular buffer. | 02-05-2009 |
20090037647 | SEMICONDUCTOR MEMORY CARD, METHOD FOR CONTROLLING THE SAME, AND SEMICONDUCTOR MEMORY SYSTEM - A semiconductor memory card which can be attached to a host apparatus and can be removed from the host apparatus includes a plurality of data transfer terminals, and an internal circuit transmitting a first signal to at least one first data transfer terminal comprising at least one of the data transfer terminals and transmitting a second signal to at least one second data transfer terminal comprising at least one of the data transfer terminals different from the first data transfer terminals. The second signal is generated by executing a logical operation on the first signal. | 02-05-2009 |
20090037648 | INPUT/OUTPUT CONTROL METHOD AND APPARATUS OPTIMIZED FOR FLASH MEMORY - An input/output control method and apparatus optimized for a flash memory, which can improve the performance of the flash memory. The input/output control method optimized for a flash memory includes determining whether a random write operation of data occurs in a flash memory, and successively writing randomly input data in a predetermined surplus region of the flash memory if it is judged that the random write operation occurs. | 02-05-2009 |
20090037649 | Methods and Systems for Running Multiple Operating Systems in a Single Mobile Device - Methods and systems for running multiple operating systems in a single embedded or mobile device (include PDA, cellular phone and other devices) are disclosed. The invention allows a mobile device that normally can only run a single operating system to run another operating system while preserving the state and data of the original operating system. Guest OS is packaged into special format recognizable by the host OS that still can be executed in place by the system. The Methods include: Change the memory protection bits for the original OS; Fake a reduced physical memory space for guest OS; Use special memory device driver to claim memories of host OS; Backup whole image of the current OS and data to external memory card. | 02-05-2009 |
20090037650 | Function updatable device and an options card therefor - A device such as for example a electronic medical device has a memory that has prestored therein a number of programs or routines for performing various functions. Some of those functions are optional functions that were not enabled when the equipment was put into service. If the user of the equipment desires thereafter to activate any one of those optional functions, an options card that has a number of memory blocks each specifically configured to enable one of the prestored optional functions is sent to the user. The user can then insert the options card into a receptacle integrated into the device and, upon power up of the device, elect a menu for enabling the desired optional function(s) prestored in the device. The options card may be configured to have a count number that indicates the number of devices the card may be used for enabling a particular optional function. The options card may further be configured to include data that may be used to enable or disable multiple optional functions prestored in the device. When returned to the manufacturer, given that the serial numbers of the machines to which the options card was inserted are recorded therein, the manufacturer can easily keep tab of the status of those machines in the field that had had optional functions enabled/disabled. | 02-05-2009 |
20090037651 | Non-Volatile Memory and Method with Phased Program Failure Handling - In a memory with block management system, program failure in a block during a time-critical memory operation is handled by continuing the programming operation in a breakout block. Later, at a less critical time, the data recorded in the failed block prior to the interruption is transferred to another block, which could also be the breakout block. The failed block can then be discarded. In this way, when a defective block is encountered during programming, it can be handled without loss of data and without exceeding a specified time limit by having to transfer the stored data in the defective block on the spot. This error handling is especially critical for a garbage collection operation so that the entire operation need not be repeated on a fresh block during a critical time. Subsequently, at an opportune time, the data from the defective block can be salvaged by relocation to another block. | 02-05-2009 |
20090037652 | Command Queuing Smart Storage Transfer Manager for Striping Data to Raw-NAND Flash Modules - A flash module has raw-NAND flash memory chips accessed over a physical-block address (PBA) bus by a NVM controller. The NVM controller is on the flash module or on a system board for a solid-state disk (SSD). The NVM controller converts logical block addresses (LBA) to physical block addresses (PBA). Data striping and interleaving among multiple channels of the flash modules is controlled at a high level by a smart storage transaction manager, while further interleaving and remapping within a channel may be performed by the NVM controllers. A SDRAM buffer is used by a smart storage switch to cache host data before writing to flash memory. A Q-R pointer table stores quotients and remainders of division of the host address. The remainder points to a location of the host data in the SDRAM. A command queue stores Q, R for host commands. | 02-05-2009 |
20090043947 | MANAGING PROCESSING DELAYS IN AN ISOCHRONOUS SYSTEM - Command cycles incorporate mechanisms to inform a host processor in advance of a need to service the memory so that the host can respond when it suits the host, but in time for the service to be performed before a catastrophic failure. The regular host cycle need not be interrupted for such notification. | 02-12-2009 |
20090043948 | Method and System for Storing Logical Data Blocks Into Flash-Blocks in Multiple Non-Volatile Memories Which Are Connected to At Least One Common Data I/0 Bus - For recording or replaying in real-time digital HDTV signals very fast memories are required. For storage of streaming HD video data NAND flash memory based systems can be used. However, NAND flash memories have a slow write access, and they have unmasked production defects. Write or read operations can be carried out on complete physical data blocks only, and defect data blocks must not be used by the file system. Logical file system blocks are used which are larger than the physical data blocks. According to the invention the error reporting mechanism of the NAND flash memories is exploited. The video data is not only written to the non-volatile flash memories, but is also written to corresponding buffer slots (LFSB) of a volatile SRAM or DRAM memory operating in parallel. The video data are kept in the vola- tile memory until the flash memory holding the respective data has reported that its program or write operation succeeded. Once this has taken place, the data within the volatile memory can be overwritten in order to save memory capacity. If the flash memory has reported an error, the respective block (FSBD) of data is marked bad and will not be overwritten until the end of the entire recorded take has been reached. At this time, the marked video data from the volatile memory are copied to spare flash-blocks within the flash memories. | 02-12-2009 |
20090043949 | BLOCK DECODER OF A FLASH MEMORY DEVICE - A block decoder increases the integration level of a flash memory device by reducing the number of control signals. Address signals are substituted with existing high voltage switch signals. The block decoder of a flash memory device includes a primary decoding unit and a secondary decoding unit. The primary decoding unit outputs a decoding signal in response to first and second address coding signals of a high voltage and first to third control signals. The secondary decoding unit outputs a control signal to control the potential of a block word line in response to the decoding signal and first and second pre-decoded signals. | 02-12-2009 |
20090043950 | SEMICONDUCTOR MEMORY STORAGE APPARATUS AND CONTENT DATA MANAGEMENT METHOD - A semiconductor memory storage apparatus includes a packetization unit receiving content data includes a plurality of variable-length frames, and adding management data showing frame data inherent information to frame data of each variable-length frame, and further, packetizing the content data storing the frame data and the management data in each fixed-length packet for every variable-length frame, a buffer temporarily storing the content data at a fixed-length packet unit in write/read operation of the content data packetized at the fixed-length packet unit, a storage unit using a non-volatile memory as an information storage medium, and storing the content data supplied from the buffer, and a controller writing/reading content data packetized at the fixed-length packet unit with respect to the storage unit at a fixed-length packet unit. | 02-12-2009 |
20090043951 | PROGRAMMING SCHEMES FOR MULTI-LEVEL ANALOG MEMORY CELLS - A method for data storage includes storing first data bits in a set of multi-bit analog memory cells at a first time by programming the memory cells to assume respective first programming levels. Second data bits are stored in the set of memory cells at a second time that is later than the first time by programming the memory cells to assume respective second programming levels that depend on the first programming levels and on the second data bits. A storage strategy is selected responsively to a difference between the first and second times. The storage strategy is applied to at least one group of the data bits, selected from among the first data bits and the second data bits. | 02-12-2009 |
20090043952 | MOVING SECTORS WITHIN A BLOCK OF INFORMATION IN A FLASH MEMORY MASS STORAGE ARCHITECTURE - A device is disclosed for storing mapping information for mapping a logical block address identifying a block being accessed by a host to a physical block address, identifying a free area of nonvolatile memory, the block being selectively erasable and having one or more sectors that may be individually moved. The mapping information including a virtual physical block address for identifying an “original” location, within the nonvolatile memory, wherein a block is stored and a moved virtual physical block address for identifying a “moved” location, within the nonvolatile memory, wherein one or more sectors of the stored block are moved. The mapping information further including status information for use of the “original” physical block address and the “moved” physical block address and for providing information regarding “moved” sectors within the block being accessed. | 02-12-2009 |
20090049231 | EFFICIENT AND SYSTEMATIC MEASUREMENT FLOW ON DRAIN VOLTAGE FOR DIFFERENT TRIMMING IN FLASH SILICON CHARACTERIZATION - Systems and methods that facilitate characterization of a flash memory device are presented. A characterization component can be associated with a regulator component included in a memory device to facilitate setting and measuring respective drain voltage levels for programming, erase, and soft programming operations at address bit combinations available for the respective operations. The characterization component can utilize external address bits that can be fixed when performing the operations to minimize disruption to the drain voltage measurement flow. The characterization component can detect when a particular operation has already been performed based in part on an applicable portion of the address bit combination associated with such operation, and can bypass such operation at that address bit combination to proceed to the next operation that has yet to be performed thereby efficiently setting and measuring drain voltage levels for various operations and trim settings to characterize the memory device. | 02-19-2009 |
20090049232 | EXECUTE-IN-PLACE IMPLEMENTATION FOR A NAND DEVICE - An Execute-In-Place (XIP) implementation in a NAND controller of the kind that controls a NAND flash memory device. A page load command is provided to a predefined block and page address in a NAND device and identifies whether the boot read request received from the processor is a continuation of a previous boot read request. A read enable pin in the NAND device is toggled if the boot read request is a continuation of the previous boot read request. A random data output command sequence is sent to the NAND device and the read enable pin is toggled if the boot read request is not a continuation of the previous boot read address. | 02-19-2009 |
20090049233 | Flash Memory, and Method for Operating a Flash Memory - A method for operating a flash memory is provided. The flash memory comprises a controller, a cache, and a plurality of blocks. By using a cache to preload data from the host, the buffer of the controller can be smaller than the capacity of a single block or omitted entirely. Smooth data transmission is still maintained. | 02-19-2009 |
20090049234 | SOLID STATE MEMORY (SSM), COMPUTER SYSTEM INCLUDING AN SSM, AND METHOD OF OPERATING AN SSM - In one aspect, data is stored in a solid state memory which includes first and second memory layers. A first assessment is executed to determine whether received data is hot data or cold data. Received data which is assessed as hot data during the first assessment is stored in the first memory layer, and received data which is first assessed as cold data during the first assessment is stored in the second memory layer. Further, a second assessment is executed to determine whether the data stored in the first memory layer is hot data or cold data. Data which is then assessed as cold data during the second assessment is migrated from the first memory layer to the second memory layer. | 02-19-2009 |
20090055574 | NAND Flash Memory Device And Related Method Thereof - The NAND flash memory device contains a NAND flash memory, a mirror data area, and a controller. The mirror data area has a size at least to hold a page of data and is usually formed by random access memory. The controller saves a data to be written into the NAND flash memory that occupies a partial number of the sectors of a first page of the NAND flash memory into the sectors of a second page of the mirror data area. When a new data is to be written into the remaining sectors of the first page of the NAND flash memory, the new data is stored instead into the second page's remaining sectors of the mirror data area. When the second page of the mirror data area is full, the entire second page is written into the first page of the NAND flash memory. | 02-26-2009 |
20090055575 | Flash memory with small data programming capability - The present invention provides a method featuring receiving a request to access a memory array having one or more memory erase units with a data area of flash array and with a specific amount of memory which offers small data programming capability; and if the memory access request includes programming small data, then providing access to the specific amount of memory, or if the memory access request does not include programming small data, then providing access to the data area of flash array; as well as an apparatus in the form of a flash memory device featuring a memory array having one or more memory erase units with a data area of flash array and with a specific amount of memory which offers small data programming capability, and a memory controller, responsive to a request, for providing access to the specific amount of memory if the request includes programming small data, or for providing access to the data area of flash array if the request does not include programming small data. | 02-26-2009 |
20090055576 | MEMORY CONTROLLER, NONVOLATILE STORAGE DEVICE, NONVOLATILE STORAGE SYSTEM, AND DATA WRITING METHOD - A nonvolatile storage device is provided with a nonvolatile main storage memory ( | 02-26-2009 |
20090055577 | PROGRAMMING METHODS FOR NONVOLATILE MEMORY - Example embodiments are directed to methods, memory devices, and systems for programming a nonvolatile memory device having a charge storage layer including performing at least one unit programming loop, each unit programming loop including, applying a programming pulse to at least two pages, applying a time delay to the at least two pages, and applying a verifying pulse to the at least two pages. | 02-26-2009 |
20090055578 | APPARATUS USING FLASH MEMORY AS STORAGE AND METHOD OF OPERATING THE SAME - An apparatus usable with a flash memory as storage and a method of operating the same are provided, which can provide an optimized architecture to a flash memory through combination of a flash transition layer (FTL) with a database. The apparatus includes a flash memory, a device driver to manage a mapping table between logical addresses and physical addresses in accordance with a data operation in the flash memory, and a control unit to perform data recovery of the flash memory by requesting the mapping table through an interface provided by the device driver. | 02-26-2009 |
20090055579 | Semiconductor memory device for simultaneously programming plurality of banks - Provided is a semiconductor memory device for simultaneously programming a plurality of banks. The semiconductor memory device includes: a memory cell array comprising a plurality of banks; a plurality of data buffers storing a plurality of pieces of program data to be programmed in the corresponding banks; and a plurality of scan latches configured to scan the plurality of program data transmitted from the corresponding data buffers, and configured to generate 1 | 02-26-2009 |
20090063756 | USING FLASH STORAGE DEVICE TO PREVENT UNAUTHORIZED USE OF SOFTWARE - A flash storage device and a method for using the flash storage device to prevent unauthorized use of a software application are provided. An identifier may be encoded within specific sectors of the flash storage device. One bits of the identifier may be encoded as unusable ones of the specific sectors and zero bits of the identifier may be encoded as usable one of the specific sectors. Alternatively, the zero bits of the identifier may be encoded as the unusable ones of the specific sectors and the one bits of the identifier may be encoded as the usable ones of the specific sectors. The software application may be permitted to execute on a processing device connected to the flash storage device only when the identifier is encoded within the flash storage device. | 03-05-2009 |
20090063757 | Memory emulation in an electronic organizer - An electronic organizer using a memory array that is directly addressed and non-volatile is disclosed. The memory array can be used to replace and emulate multiple memory types such as DRAM, SRAM, non-volatile RAM, FLASH memory, and a non-volatile memory card, for example. The memory array may be randomly accessed. Data stored in the memory array is retained in the absence of electrical power. One or more memory arrays may be used in the electronic organizer. At least one of the memory arrays may be in the form of a removable memory card. | 03-05-2009 |
20090063758 | PROGRAM AND READ METHOD AND PROGRAM APPARATUS OF NAND FLASH MEMORY - A program method, a read method, and a program apparatus of a NAND flash memory are disclosed. The program method and apparatus of the NAND flash memory provided by the present invention can reduce the programming time of each page and increase the programming speed of the entire NAND flash memory when the data to be programmed in a single operation is less than the storage capacity of all the data storage areas in the page. In addition, the read method of the NAND flash memory provided by the present invention can reduce the number of reading each page and accordingly the number of reading the entire NAND flash memory when the data to be read in a single operation is less than the storage capacity of all the data storage areas in the page. | 03-05-2009 |
20090070518 | Adaptive Block List Management - In a nonvolatile memory array, selected blocks are maintained as open blocks that are available to store additional data without being erased first. Nonsequential open blocks are selected from two lists, one list based on recency of the last write operation, and the other list based on frequency of writes to the block. Sequential open blocks are divided into blocks expected to remain sequential and blocks that are not expected to remain sequential. | 03-12-2009 |
20090070519 | SYSTEM AND METHOD FOR SECURE DOCUMENT PROCESSING USING REMOVABLE DATA STORAGE - The subject application is directed to a system and method for secure document processing. A removable storage, such as a flash drive, magnetic storage, IC card, is installed in document processing device. A selected document processing operation, such as copying, scanning, and the like, is then performed. Data files resultant from the selected document processing operations are directed to the removable storage for being stored temporary, instead of being sent to the storage inherent to the document processing device. Data files temporary stored in the removable storage are then deleted. | 03-12-2009 |
20090070520 | SEMICONDUCTOR STORAGE DEVICE AND METHOD OF CONTROLLING SEMICONDUCTOR STORAGE DEVICE - In a semiconductor storage device, a memory controller divides each of blocks in each of chips into a first page set composed of pages and a second page set composed of pages, divides a logical address space into groups, and divides each group into lines. Block units are created each of which is obtained by assembling a predetermined number of blocks from the blocks in each chip. A predetermined number of block units from the block units are managed as standard block units, and the other block units are managed as spare block units. Each standard block unit is made to correspond to one group. The corresponding group data is stored in the pages in the first page set in each block constituting the standard block unit, and unwritten pages for recording update data for the group data are provided to be included in the second page set. | 03-12-2009 |
20090070521 | WRITE ABORT AND ERASE ABORT HANDLING - A portion of a nonvolatile memory array that is likely to contain, partially programmed data may be identified from a high sensitivity read, by applying stricter than usual ECC requirements, or using pointers to programmed sectors. The last programmed data may be treated as likely to be partially programmed data. Data in the identified portion may be copied to another location, or left where it is with an indicator to prohibit further programming to the same cells. To avoid compromising previously stored data during subsequent programming, previously stored data may be backed up. Backing up may be done selectively, for example, only for nonsequential data, or only when the previously stored data contains an earlier version of data being programmed. If a backup copy already exists, another backup copy is not created. Sequential commands are treated as a single command if received within a predetermined time period. | 03-12-2009 |
20090070522 | METHOD AND APPARATUS FOR CASCADE MEMORY - A system and method of operating a cascade of a plurality of memory devices connected in series is disclosed. In one aspect, there is a memory controller operatively connected to the memory cell and a cascade circuit configured to enable a subsequent memory device in a cascade of memory devices. | 03-12-2009 |
20090070523 | Flash memory device storing data with multi-bit and single-bit forms and programming method thereof - A flash memory device may include a memory cell array including a plurality of memory blocks and a partition information block, the partition information block storing partition information that indicates a boundary between multi-bit memory blocks and single-bit memory blocks among the memory blocks. The memory device may include a control logic configured to determining whether a memory block that a block address from the outside indicates has a multi-bit form or a single-bit form based on the partition information and to control program and read operations in a multi-bit form or a single-bit form based on a determination result. The control logic automatically programs data in the partition information block according to whether a fuse connected to the control logic fuse is cut or not, the data being used for preventing the partition information block from being programmed or erased. | 03-12-2009 |
20090077301 | PROGRAMMABLE SEQUENCE GENERATOR FOR A FLASH MEMORY CONTROLLER - A programmable sequence generator for controlling a flash memory device. The programmable sequence generator includes a plurality of programmable sequence registers including control phase sequence (CPS) registers and data phase sequence (DPS) registers programmed with phase sequence values corresponding to an operation command sequence of the flash memory device; and logic circuitry in a programmable command sequencer for controlling a set of states of the programmable command sequencer using the plurality of programmable sequence registers. | 03-19-2009 |
20090077302 | Storage apparatus and control method thereof - This storage apparatus has a disk-shaped storage device for storing data sent from a host system, and includes a nonvolatile memory device for storing the data, a controller for controlling the reading or writing of the data sent from the host system from or into the disk-shaped storage device, and a device controller for controlling the nonvolatile memory device and the disk-shaped storage device. The device controller replicates data stored in the disk-shaped storage device to the nonvolatile memory device according to the usage of the disk-shaped storage device. The controller reads data from the nonvolatile memory device when the controller receives a data read request from the host system and corresponding data is stored in the nonvolatile memory device. | 03-19-2009 |
20090077303 | System for transferring information and method thereof - A system for transferring information and method thereof, the system includes a management processor, a storage processor and a peripheral. Moreover, the management processor connects to the storage processor by I2C bus and GPIO bus, wherein the I2C bus is used for transmitting information from the management processor to the storage processor, and the GPIO bus is used for transmitting acknowledged instruction from the storage processor to the management processor. Moreover, the management processor transmits the information to the storage processor continuously until the management processor receives an acknowledged instruction from the storage processor. Furthermore, the storage processor waits to receive the information from the management processor, and replies the acknowledged instruction to the management processor after the storage processor receives the information correctly. | 03-19-2009 |
20090077304 | MEMORY SYSTEM HAVING NONVOLATILE AND BUFFER MEMORIES, AND READING METHOD THEREOF - Disclosed is a method for reading data in a memory system including a buffer memory and a nonvolatile memory, the method being comprised of: determining whether an input address in a read request is allocated to the buffer memory; determining whether a size of requested data is larger than a reference unless the input address is allocated to the buffer memory; and conducting a prefetch reading operation from the nonvolatile memory if the requested data size is larger than the reference. | 03-19-2009 |
20090077305 | Flexible Sequencer Design Architecture for Solid State Memory Controller - A method and apparatus for controlling access to solid state memory devices which may allow maximum parallelism on accessing solid state memory devices with minimal interventions from firmware. To reduce the waste of host time, multiple flash memory devices may be connected to each channel. A job/descriptor architecture may be used to increase parallelism by allowing each memory device to operate separately. A job may be used to represent a read, write or erase operation. When firmware wants to assign a job to a device, it may issue a descriptor, which may contain information about the target channel, the target device, the type of operation, etc. The firmware may provide descriptors without waiting for a response from a memory device, and several jobs may be issued continuously to form a job queue. After the firmware finishes programming descriptors, a sequencer may handle the remaining work so that the firmware may concentrate on other tasks. | 03-19-2009 |
20090077306 | OPTIMIZING MEMORY OPERATIONS IN AN ELECTRONIC STORAGE DEVICE - To optimize memory operations, a mapping table may be used that includes: logical fields representing a plurality of LBA sets, including first and second logical fields for representing respectively first and second LBA sets, the first and second LBA sets each representing a consecutive LBA set; PBA fields representing PBAs, including a first PBA disposed for representing a first access parameter set and a second PBA disposed for representing a second access parameter set, each PBA associated with a physical memory location in a memory store, and these logical fields and PBA fields disposed to associate the first and second LBA sets with the first and second PBAs; and, upon receiving an I/O transaction request associated with the first and second LBA sets, the mapping table causes optimized memory operations to be performed on memory locations respectively associated with the first and second PBAs. | 03-19-2009 |
20090083474 | FILE ALLOCATION TABLE MANAGEMENT - In one embodiment, a storage controller comprises a first port that provides an interface to a host computer, a second port that provides an interface a storage device, a processor, and a flash memory module communicatively connected to the processor and comprising logic instructions which, when executed by the processor, configure the processor to receive, in a file allocation table manager, a signal indicative of a request to perform a first update of a file allocation table stored in a memory module, locate, in the memory module, a first memory sector corresponding to a first entry in the file allocation table having an active status, write, in the memory module, a second file allocation table entry, set a status flag associated with the second entry to an active state, and set a status flag associated with the first entry to a standby state. | 03-26-2009 |
20090083475 | APPARATUS AND METHOD FOR UPDATING FIRMWARE STORED IN A MEMORY - The invention provides a method for updating firmware stored in a memory. In one embodiment, the memory is divided into a plurality of blocks, and the firmware to be updated with a new image version. First, a first data block is obtained from the new image version, and a second data block is obtained from a target block selected from the memory. Whether the first data block is different from the second data block is then checked. The first data block is then written into the target block when the first data block is different from the second data block. Finally, the aforementioned steps are repeated until all of the blocks are processed. | 03-26-2009 |
20090083476 | SOLID STATE DISK STORAGE SYSTEM WITH PARALLEL ACCESSSING ARCHITECTURE AND SOLID STATE DISCK CONTROLLER - A solid state disk (SSD) storage system with a parallel accessing architecture, including a SSD controller and a plurality of transmission interfaces of a predetermined bit number and bandwidth, and a solid state disk controller thereof are provided. The SD controller forms channels for transmitting control signals and data with one or more flash memories through each of the transmission interfaces. That is, independent transmission channels are constituted between the SSD controller, the transmission interfaces with multiple bits, and the flash memories. In one embodiment, the transmission interfaces are compatible with MMC 4.0 protocol or higher. Moreover, a host controls and accesses the flash memories through a SATA bus interface and the SSD controller, and uses a direct memory access (DMA) engine with a bidirectional connection port in the SSD controller to transmit data. | 03-26-2009 |
20090083477 | METHOD AND APPARATUS FOR FORMATTING PORTABLE STORAGE DEVICE - A method and apparatus for formatting a portable storage device, which are capable of performing formatting optimized for a non-volatile memory of the portable storage device. The method includes: detecting whether file system information is initialized when formatting of the non-volatile memory is started; if the initialization of the non-volatile memory is detected, detecting a cluster size and cluster start position of a storage space of the portable storage device; and if the detected cluster size and the cluster start position information do not match a size and a staring position of a minimum recording unit of the storage space, performing a re-formatting operation of the portable storage device. | 03-26-2009 |
20090083478 | INTEGRATED MEMORY MANAGEMENT AND MEMORY MANAGEMENT METHOD - An integrated memory management device according to an example of the invention comprises an acquiring unit acquiring a read destination logical address from a processor, an address conversion unit converting the read destination logical address into a read destination physical address of a non-volatile main memory, an access unit reading, from the non-volatile main memory, data that corresponds to the read destination physical address and has a size that is equal to a block size or an integer multiple of the page size of the non-volatile main memory, and transmission unit transferring the read data to a cache memory of the processor having a cache size that depends on the block size or the integer multiple of the page size of the non-volatile main memory. | 03-26-2009 |
20090089481 | Leveraging Portable System Power to Enhance Memory Management and Enable Application Level Features - A memory device and techniques for its operation are presented. After operating on power received from a host, the memory device determines that it is no longer receiving host power and, in response, activates a power source on the memory device itself. Using this reserve power, the memory device can then perform data management operations. The techniques can also be applied to a digital appliance having a non-volatile memory. The memory device or digital appliance can prioritize its memory management operation during the host/user operating window based on the ability to perform these operations outside of the host/user operating window. Additionally, in a data write operations, where the memory device receives data from a host, stores the data in volatile memory, and then writes the data into the non-volatile memory, the memory device sends the host an acknowledgment of the data having been written into the non-volatile memory after it has been store in the volatile memory, but before the write into the non-volatile memory is complete. | 04-02-2009 |
20090089482 | DYNAMIC METABLOCKS - A nonvolatile block erasable memory array links erase blocks together for programming with high parallelism as a metablock. Erase blocks are operated in banks, with each bank having a dedicated bus and controller. Sub-metablocks of different metablocks, in different banks, are accessed in parallel allowing different metablocks to be updated at the same time. | 04-02-2009 |
20090089483 | Storage device and deduplication method - This storage device performs deduplication of eliminating duplicated data by storing a logical address of one or more corresponding logical unit memory areas in a prescribed management information storage area of a physical unit memory area defined in the storage area provided by the flash memory chip, and executes a reclamation process of managing a use degree as the total number of the logical addresses used stored in the management information storage area and a duplication degree as the number of valid logical addresses corresponding to the physical unit memory area for each of the physical unit memory areas, and returning the physical unit memory area to an unused status when the difference of the use degree and the duplication degree exceeds a default value in the physical unit memory area. | 04-02-2009 |
20090089484 | DATA PROTECTION METHOD FOR POWER FAILURE AND CONTROLLER USING THE SAME - A data protection method suitable for a plurality of physical blocks mapped to a logical block in a non-volatile memory is provided. The data protection method includes recording data update information in each of the physical blocks for identifying an update relationship of the physical blocks and re-establishing the update relationship of the physical blocks according to the data update information. The data update information is composed of a plurality of words having a circular relationship, and the number of these words is greater than the number of the physical blocks. The data update information is sequentially recorded in each of the physical blocks according to the update relationship and the circular relationship. | 04-02-2009 |
20090089485 | WEAR LEVELING METHOD AND CONTROLLER USING THE SAME - A wear leveling method for a non-volatile memory is provided. The non-volatile memory is substantially divided into a plurality of blocks, and these blocks are grouped into at least a data area, a spare area, a substitute area, and a temporary area. The wear leveling method includes selecting blocks from the spare area according to different purposes and executing a wear leveling procedure. | 04-02-2009 |
20090089486 | PORTABLE DATA STORAGE DEVICE INCORPORATING MULTIPLE FLASH MEMORY UNITS - A portable data storage device is disclosed which includes an Interface for enabling the portable data storage device to be used for data transfer with a host Computer, and an Interface controller for controlling the interface. There is also a master control unit for controlling the writing of data to and reading data from a non-volatile memory. The non-volatile memory includes at least one single layer cell flash memory and at least one multiple layer cell flash memory. Upon receiving a write instruction, the master control unit determines which of the memories data contained in the instruction should be written to, and writes the data as appropriate similarly, upon receiving a read instruction, the master control unit reads the data from the appropriate one of the memories and transmits the data out of the device. | 04-02-2009 |
20090089487 | MULTIPORT SEMICONDUCTOR MEMORY DEVICE HAVING PROTOCOL-DEFINED AREA AND METHOD OF ACCESSING THE SAME - A multiprocessor system includes a first processor for performing a first task, a second processor for performing a second task, and a multiport semiconductor memory device having a protocol-defined area for defining a specification related to data communication between the first processor and the second processor. The protocol-defined area is located in at least one shared memory area accessible in common by the first processor and the second processor through a first port and a second port, respectively, and is assigned as a predetermined memory capacity to a portion of a memory cell array. | 04-02-2009 |
20090089488 | MEMORY SYSTEM, MEMORY READ METHOD AND PROGRAM - According to one embodiment, there is disclosed a memory system comprising a flash memory unit which suspends a write operation to execute a read operation when receiving a suspend command during a write operation, a CPU, an OS which includes a device driver, a TLB which has a page table for conversion from a virtual address to a physical address, and an application program which makes a TLB setting request with respect to the device driver when receiving a read command under the control of the CPU and the OS, acquires address information read from the page table of the TLB by the device driver in response to the setting request, and executes read directly with respect to the flash memory unit using the acquired address information without using the device driver. | 04-02-2009 |
20090089489 | MEMORY CONTROLLER, FLASH MEMORY SYSTEM WITH MEMORY CONTROLLER, AND CONTROL METHOD OF FLASH MEMORY - The memory controller updates a count number based on a new assignment of a logical block to a physical block, and writes count information in the physical block to which the logical block is newly assigned. The count information is defined by the count number. The memory controller decides, based on the count number and the count information stored in each physical block, whether or not to transfer stored data in a physical block to another physical block. | 04-02-2009 |
20090089490 | MEMORY SYSTEM - A memory system including a nonvolatile memory, a first controller connected to a host equipment, the first controller controlling the entire memory system, a second controller connected to the first controller and also connected to the nonvolatile memory, the second controller controlling an access process to said nonvolatile memory, the second controller receives a command via the first controller and carries out the access process to the nonvolatile memory according to the command, the command being input from the host equipment. | 04-02-2009 |
20090089491 | SEMICONDUCTOR MEMORY DEVICE AND DATA MANAGEMENT METHOD USING SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises: a memory part which has a plurality of memory blocks having a memory cell capable of storing a plurality of different kinds of data which require a memory area having different characteristics, and a memory controller which has a function of treating each of the memory blocks as a deletion unit in order to manage the memory part and converting a logic address of the memory part to a physical address identifying the memory block, and which replaces the memory block with a preregistered free block in rewriting the memory block. The memory controller manages the different kinds of data to be stored in the memory part so as to store the same kind of data as before, even after each of the memories and free blocks in the memory part are rewritten. | 04-02-2009 |
20090089492 | FLASH MEMORY CONTROLLER - Methods, systems and computer program products for implementing a polling process among one or more flash memory devices are described. In some implementations, the polling process may include sending a read status command to a flash memory device to detect the ready or busy state of the flash memory device. A status register may be included in the flash memory device for storing a status signal indicating an execution state of a write (or erase) operation. A solid state drive system may perform the polling process by reading the status register of the flash memory device. | 04-02-2009 |
20090094406 | SCALABLE MASS DATA STORAGE DEVICE - A scalable data storage device which includes non-volatile memory uses a networked bus system which can be employed on a single memory storage chip level or in a multi-chip package (MCP). The scalable data storage device uses data routing modules which are adapted to store incoming data and send outgoing data thereby providing decoupling of the networked buses. This arrangement enables significantly higher data transfer rates, surpassing DRAM SSDs at a fraction of the size and cost, provides increased volumetric density (1 TB in less than 1 cubic inch), and permits concurrency of operations. The scalable data storage device can be engineered to have a rewrite capability of over 500 times that of Flash RAM and can scale down to 8 bits and up to exabytes, yottabytes and beyond. The scalable data storage device may be used in a wide range of applications from large data centers to small consumer electronic products. | 04-09-2009 |
20090094407 | Non-volatile memory device having assignable network identification - Memory devices and methods disclosed such as memory devices that include a network identification that uniquely identifies the memory device on a network. The memory device can then receive memory commands that include the network identification. The memory device can also generate memory commands, including the network identification, for broadcast over the network. | 04-09-2009 |
20090094408 | MEMORY WRITING DEVICE - After power-on, the start-up of a CPU | 04-09-2009 |
20090094409 | WEAR LEVELING METHOD AND CONTROLLER USING THE SAME - A wear leveling method for non-volatile memory is provided, by which the non-volatile memory is substantially divided into a plurality of blocks and the blocks are grouped into a data area and a spare area. The method includes selecting a block based on an erased sequence when getting the block from the spare area. The method also includes performing a wear leveling procedure. | 04-09-2009 |
20090094410 | METHOD FOR BLOCK WRITING IN A MEMORY - A method is provided for block writing in an electrically programmable non-volatile memory, in which a block to be written in the memory includes at least one word. The method includes determining a word write time by dividing a fixed block write time by the number of words in the block to be written, and controlling the memory to successively write each word in the memory during the write time. | 04-09-2009 |
20090094411 | NAND FLASH CONTROLLER AND DATA EXCHANGE METHOD BETWEEN NAND FLASH MEMORY AND NAND FLASH CONTROLLER - The invention discloses a NAND flash controller, including a command and address data transmission channel adapted to connect the bus timing interface with the channel selector and transmit command and address data, a data buffer region adapted to receive message data from the bus timing interface through system bus, a control register adapted to receive an operation parameter configured through system bus via the bus timing interface, a logic controller adapted to write the data information into or read the data information from the data buffer region according to the operation parameter, a channel selector adapted to connect the DMA data transmission channel or the command and address data transmission channel according to the operation parameter for transmitting data. The invention also discloses a date exchange method between NAND flash controller and NAND flash memory. The invention improves the data transmission efficiency and is compatible with various NAND flash memories. | 04-09-2009 |
20090100214 | Management Platform For Extending Lifespan Of Memory In Storage Devices - A management platform for extending lifespan of memory, such as SD, MMC, micro SD, of storage devices is provided. The memory includes a plurality of virtual access units, and a virtual block is defined to include a fixed number of virtual access units. In the management platform, a memory control unit tallies the number of operations performed on a virtual access unit when the virtual access unit is selected to perform on. A processing unit determines whether the data stored in virtual access units should be move to another virtual access unit according to an operation threshold in order to prevent from data loss caused by the memory damage. | 04-16-2009 |
20090100215 | IDENTITY-BASED FLASH MANAGEMENT - Methods, apparatus, and computer code for effecting flash policy configuration operations in accordance with an end-user identifier and/or a host-instance identifier are disclosed herein. Exemplary flash policy configuration operations include (i) configuring a flash error-correction policy, (ii) configuring a flash-management table storage policy; (iii) configuring a wear-leveling policy; (iv) configuring a bad-block management policy and (v) configuring a flash-programming voltage parameter. Exemplary end-user identifiers include but are not limited to email account identifiers, logon user names, and International Mobile Subscriber Identities (IMSI). Exemplary host-instance identifiers may include but are not limited to International Mobile EQUIPMENT Identifiers (IMEI). Optionally, the flash policy configuration is contingent on authentication context data—for example, strength of the authentication (e.g. login/password vs. smartcard authentication or biometric authentication), date of the authentication, and identity provider information. | 04-16-2009 |
20090100216 | Power saving optimization for disk drives with external cache - A power conservation system implementable in a computer system. The system includes a non-volatile cache memory (NVCM) device for storing information. The NVCM device is operationally coupled to the computer system. The system also includes a data storage device coupled to the NVCM device. The data storage device is for storing said information. The system further includes a controller coupled to the NVCM device. The controller initiates an occurrence of writing the information in the NVCM device to the data storage device. The occurrence of writing causes powering up of the data storage device to which the data is to be written or from which data is to be retrieved. | 04-16-2009 |
20090100217 | Portable Data Transfer and Mass Storage Device for Removable Memory Modules - A hand-held battery powered device for transferring data between one or more flash memory modules and a mass storage device. The device includes one or more slots to accept a flash memory module into a housing which includes fixed or removable mass storage device and logic circuitry disposed within the housing for transferring data between the flash memory module and mass storage device. Ports are disclosed for transferring data from the resident mass storage device to the user's computer. | 04-16-2009 |
20090100218 | HARD DISK DRIVE WITH REDUCED POWER CONSUMPTION, RELATED DATA PROCESSING APPARATUS, AND I/O METHOD - A hard disk drive is disclosed and related methods of reading/writing data are disclosed. The hard disk drive includes a disk serving as a main data storage medium, and first and second buffers storing data to be stored on the disk, as well as a controller defining a data I/O path in relation to a detected operating state of the hard disk drive. | 04-16-2009 |
20090106481 | HYBRID FLASH MEMORY DEVICE - A hybrid memory system is provided that combines the advantages of NAND flash memory devices with the advantages of NOR flashes memory devices. The system includes a NAND flash memory portion to provide mass storage and fast programming/erasure capabilities of conventional NAND flash memory devices. The system further comprises a NOR flash memory portion to provide code storage and fast random reading capabilities of conventional NOR flash memory devices. Accordingly, the hybrid memory system provides both mass storage and code storage. along with fast programming/erasure speeds and fast random access speeds. | 04-23-2009 |
20090106482 | MEMORY DEVICE PROGRAM WINDOW ADJUSTMENT - In one or more embodiments, a memory device is disclosed as having an adjustable programming window having a plurality of programmable levels. The programming window is moved to compensate for changes in reliable program and erase thresholds achievable as the memory device experiences factors such as erase/program cycles that change the program window. The initial programming window is determined prior to an initial erase/program cycle. The programming levels are then moved as the programming window changes, such that the plurality of programmable levels still remain within the program window and are tracked with the program window changes. | 04-23-2009 |
20090106483 | SECURE PERSONALIZATION OF MEMORY-BASED ELECTRONIC DEVICES - Systems and/or methods that facilitate programming content to a plurality of nonvolatile memory devices are presented. A wafer program component facilitates programming content to a plurality of memory devices contained on a wafer. The wafer program component can interface with the wafer and can employ parallel processes to program the memory devices on the wafer at substantially the same time. The content programmed to the memory devices can be the same content or different content. A portion of the content can be access-restricted where authentication information is to be provided in order to be granted access to such content, where access-restricted content can include content associated with subscriptions or personal information of a user(s). | 04-23-2009 |
20090106484 | DATA WRITING METHOD FOR NON-VOLATILE MEMORY AND CONTROLLER USING THE SAME - A data writing method for a non-volatile memory is provided, wherein the non-volatile memory includes a data area and a spare area. In the data writing method, a plurality of blocks in a substitution area of the non-volatile memory is respectively used for substituting a plurality of blocks in the data area, wherein data to be written into the blocks in the data area is written into the blocks in the substitution area, and the blocks in the substitution area are selected from the spare area of the non-volatile memory. A plurality of temporary blocks of the non-volatile memory is used as a temporary area of the blocks in the substitution area, wherein the temporary area is used for temporarily storing the data to be written into the blocks in the substitution area. | 04-23-2009 |
20090106485 | READING ANALOG MEMORY CELLS USING BUILT-IN MULTI-THRESHOLD COMMANDS - A method for data storage includes storing data in a memory that includes multi-bit analog memory cells, each of which stores at least first and second data bits by assuming one of a predefined plurality of programming levels associated with respective storage values. The memory has at least a first built-in command for reading the first data bits of the memory cells by comparing the storage values of the memory cells to a first number of first thresholds, and a second built-in command for reading the second data bits of the memory cells by comparing the storage values of the memory cells to a second number of second thresholds, such that the first number is less than the second number. After storing the data, the first data bits are read from the memory cells by executing at least the second built-in command. | 04-23-2009 |
20090106486 | EFFICIENT PREFETCHING AND ASYNCHRONOUS WRITING FOR FLASH MEMORY - Disclosed herein are a flash file system and an address translation method. The flash file system includes a file system, a Flash Translation Layer (FTL), and flash memory. The FTL receives Local Block Addresses (LBAs) from the file system, and translates the LBAs into Physical Block Address (PBAs. The flash memory receives the resulting PBAs. The FTL includes a memory block in which a multi-stage clustered hash table for mapping the LBAs to the PBAs is stored, and performs the address translation using the clustered hash table. | 04-23-2009 |
20090106487 | Electronic Device Having a Memory Element and Method of Operation Therefor - An electronic device comprises a processing unit operably coupled to a buffer random access memory, in turn operably coupled to a non-volatile memory configured to emulate an electrically erasable programmable read only memory. The processing unit is arranged to transfer data between the buffer RAM and the non-volatile memory at a first clock frequency. A second RAM is operably coupled between the processing unit and the non-volatile memory and the processing unit sets a Tag bit in the second RAM to identify an address in the buffer RAM that is being written to or read from by the processing unit. | 04-23-2009 |
20090113113 | METHOD AND APPARATUS FOR SANITIZING OR MODIFYING FLASH MEMORY CHIP DATA - A method and apparatus is provided for individually checking, sanitizing and/or otherwise altering data bits of a plurality of memory chips via one or more processes where the memory chips being processed at any given time may be of different unformatted memory capacities, may be of different memory types, and may have the process started at different times. The method utilizes a computer based program capable of multithreaded operation whereby a new procedure thread is initiated upon a determination by the main program that a given reader port is in recent initial communication with a memory chip. | 04-30-2009 |
20090113114 | Implementation of One Time Programmable Memory with Embedded Flash Memory in a System-on-Chip - System and method for implementing one time programmable (OTP) memory using embedded flash memory. A system-on-chip (SoC) includes a cleared flash memory array that includes an OTP block, including an OTP write inhibit field that is initially deasserted, a flash memory controller, and a controller. Data are written to the OTP block, including setting the OTP write inhibit field to signify prohibition of subsequent writes to the OTP block. The SoC is power cycled, and, in response, at least a portion of the OTP block is latched in a volatile memory, including asserting an OTP write inhibit bit based on the OTP write inhibit field, after which the OTP block is not writeable. In response to each subsequent power cycling, the controller is held in reset, the latching is performed, the controller is released from reset, and the flash array, now write protected, is configured to be controlled by the controller. | 04-30-2009 |
20090113115 | NON-VOLATILE MEMORY ARRAY PARTITIONING ARCHITECTURE AND METHOD TO UTILIZE SINGLE LEVEL CELLS AND MULTI-LEVEL CELLS WITHIN THE SAME MEMORY - A memory device is disclosed, and includes an array of memory cells and a partitioning system configured to address a first portion of the array in a single level cell mode, and a second portion of the array in a multi-level cell mode. | 04-30-2009 |
20090113116 | Digital content kiosk and methods for use therewith - A digital content kiosk and methods for use therewith are disclosed. Various embodiments are disclosed relating to exemplary memory devices, memory architectures, and programming techniques that can be used with a digital content kiosk, exemplary mechanical and electrical components of a digital content kiosk, exemplary security aspects of a digital content kiosk, and exemplary uses of a digital content kiosk. Other embodiments are disclosed, and each of these embodiments can be used alone or in combination with one another. | 04-30-2009 |
20090113117 | RE-FLASH PROTECTION FOR FLASH MEMORY - A method for storing data includes providing a memory package including an integrated circuit containing a non-volatile memory and counter circuitry. The data is written to the non-volatile memory. The counter circuitry is operated to maintain a count of write operations performed on the non-volatile memory. The data and the count from the memory package are received at a controller, separate from the memory package, and the data is authenticated in response to the count. | 04-30-2009 |
20090113118 | MEMORY MODULE AND CONTROL METHOD OF SERIAL PERIPHERAL INTERFACE USING ADDRESS CACHE - A serial peripheral interface memory module using address cache comprises a flash memory array for storing data, a serial/parallel convertor for receiving serial signals and generating a control command, an address and data, an address register, an address accumulator for accumulating the address in the address register and storing the accumulated address back to the address register, and a flash memory controller for controlling the access to the flash memory array. When the control command is a standard command, the serial/parallel controller first stores the address following the control command into the address register and then the flash memory controller accesses data according to the address in the address register. When the control command is a specific command, the flash memory controller directly accesses data according to the address in the address register without waiting for an address update. | 04-30-2009 |
20090113119 | DATA WRITING METHOD - Data are write commanded from a host into a NAND flash memory. The data are saved once in a cache memory before being written into the NAND flash memory. The cache memory includes a physical segment whose size is the product of one page sector size of the NAND flash memory and the m-th power of 2 (m is 0 or a positive integer). A CPU records and manages the data writing status for each physical segment in a sector unit. | 04-30-2009 |
20090113120 | States Encoding in Multi-Bit Cell Flash Memory for Optimizing Error Rate - To store N bits of M≧2 logical pages, the bits are interleaved and the interleaved bits are programmed to [N/M] memory cells, M bits per cell. Preferably, the interleaving puts the same number of bits from each logical page into each bit-page of the [N/M] cells. When the bits are read from the cells, the bits are de-interleaved. The interleaving may be deterministic or random, and may be effected by software or by dedicated hardware. | 04-30-2009 |
20090113121 | Swappable Sets of Partial-Mapping Tables in a Flash-Memory System With A Command Queue for Combining Flash Writes - A flash controller has a flash interface accessing physical blocks of multi-level-cell (MLC) flash memory. An Extended Universal-Serial-Bus (EUSB) interface loads host commands into a command queue where writes are re-ordered and combined to reduce flash writes. A partial logical-to-physical L2P mapping table in a RAM has entries for only 1 of N sets of L2P mapping tables. The other N−1 sets are stored in flash memory and fetched into the RAM when a L2P table miss occurs. The RAM required for mapping is greatly reduced. A data buffer stores one page of host write data. Sector writes are merged using the data buffer. The data buffer is flushed to flash when a different page is written, while the partial logical-to-physical mapping table is flushed to flash when a L2P table miss occurs, when the host address is to a different one of the N sets of L2P mapping tables. | 04-30-2009 |
20090119444 | MULTIPLE WRITE CYCLE MEMORY USING REDUNDANT ADDRESSING - The present invention produces a low-cost reliable non-volatile memory with multiple write cycles. The memory circuit trades full configurability for increased reliability and decreased cost by providing a limited number of write or rewrite cycles utilizing an indirectly accessible register set that writes data into fully configurable memory. The circuit is useful for both providing upgrade capability to electronic computational systems and data robustness to logic storage systems. Less configurable non-volatile memory (NVM) block | 05-07-2009 |
20090119445 | COMPUTER MEMORY ACCESSIBLE IN EITHER POWER STATE OF THE COMPUTER - A system on a computer for providing access to data stored on the computer in either power state is provided. The system can include a memory module and an external data interface connector. The system can further include a data interface controller for managing a data interface to the memory module and a data interface to the external data interface connector. The system can further include a multiplexer conductively connecting the data interface controller with the memory module when the computer is powered on, the multiplexer conductively disconnecting the data interface controller from the memory module when the computer is powered off and the multiplexer conductively connecting the external data interface connector with the memory module when the computer is powered on. | 05-07-2009 |
20090119446 | DIVIDED BITLINE FLASH MEMORY ARRAY WITH LOCAL SENSE AND SIGNAL TRANSMISSION - A flash memory array and a method for performing read operation therein are disclosed. The flash memory array comprises a plurality of memory segment, a data cache and a plurality of data handlers coupled between a pair of memory segment and between a memory segment and the data cache. A read operation of selected bitlines of a selected memory segment is performed by a segment data handler coupled to the selected memory segment locally and the read data is transmitted to the data cache. A segment data handler is configured to get read data from the selected bitlines by first pre-charging the bitlines and sensing the bitlines. Further, the read data is transmitted to the data cache through all of the segment data handlers in a sequential manner, if present between the selected memory segment and the data cache. | 05-07-2009 |
20090119447 | CONTROLLED BIT LINE DISCHARGE FOR CHANNEL ERASES IN NONVOLATILE MEMORY - Systems and/or methods that facilitate discharging bit lines (BL) associated with memory arrays in nonvolatile memory at a controlled rate are presented. A discharge component facilitates discharging the BL at a desired rate thus preventing the “hot switching” phenomenon from occurring within a y-decoder component(s) associated with the nonvolatile memory. The discharge component can be comprised of, in part, a discharge transistor component that controls the rate of BL discharge wherein the gate voltage of the discharge transistor component can be controlled by a discharge controller component. The rate of BL discharge can be determined by the size of discharge transistor component used in the design, the strength and/or size of the y-decoder component, the number of erase errors that occur for a particular memory device, and/or other factors in order to facilitate preventing hot switching from occurring. | 05-07-2009 |
20090119448 | Memory Apparatus, and Method of Averagely Using Blocks of a Flash Memory - A flash memory controller for averagely using blocks of a flash memory and the method thereof are provided. The flash memory controller is configured to process wear-leveling by allocating frequently updated data in less-erased blocks, and, allocating less-updated data in frequently erased blocks to achieve dynamic uniformity of times of erasion of blocks. | 05-07-2009 |
20090119449 | Apparatus and method for use of redundant array of independent disks on a muticore central processing unit - The invention is based on running the entire RAID stack on a dedicated core of one of the cores of the multi-core CPU. This makes it possible to eliminate the use of a conventional separate RAID controller and replace its function with a special flash memory chip that contains a program, which isolates the dedicated cores from the rest of the operating system and converts it into a powerful RAID engine. A part of the memory of the flash memory chip can also be used for storing data at power failure. This makes it possible to avoid having the battery backup module. The invention of the method of RAID on multi-core CPU may have many useful applications on an enterprise level, e.g., for increased accessibility and preserving critical data. | 05-07-2009 |
20090119450 | MEMORY DEVICE, MEMORY MANAGEMENT METHOD, AND PROGRAM - A memory device includes a non-volatile memory which allows data to be written, read, and erased electrically and in which writing and reading are done in units of a page and erasing is done in units of a block including a plurality of pages, and a control section that manages access to the non-volatile memory. The control section performs management of access to the non-volatile memory by performing logical address-physical address translation (logical-physical translation) in translation units (TUs) each being an integer fraction of a size of the block and an integer multiple of a page size. | 05-07-2009 |
20090125668 | Management of erased blocks in flash memories - The invention relates to a method for managing the erasure process in a memory system comprising individually erasable memory blocks (SB) that can be addressed with the aid of real memory block addresses (SBA). Said memory blocks are sub-divided into a plurality of writable sectors and can be addressed by means of an address conversion that uses an allocator table (ZT) to convert logical block addresses (LBA) into one of the respective memory block addresses (SBA). According to the invention, the allocator table (ZT) is sub-divided into at least one useful data area (NB) and a buffer block area (BB). The invention is characterised in that a first identifier erased (ER), indicating the physical erasure status and a second identifier content erased (CER), indicating the logical erasure status, is set for each memory block (SB) in the allocator table (ZT). | 05-14-2009 |
20090125669 | PREVENTING DATA LOSS IN A STORAGE SYSTEM - Storage servers use a fast, non-volatile or persistent memory to store data until it can be written to slower mass storage devices such as disk drives. If the server crashes before a write can complete, the data remains safely stored in non-volatile memory. If the data cannot be committed to disk when the server reboots (e.g. because the destination mass storage device is unavailable), it is stored in a file. When the disk reappears, the data in the file may be used to restore a file or file system on the disk to a consistent state. | 05-14-2009 |
20090125670 | ERASE BLOCK MANAGEMENT - An improved Flash memory device with a distributed erase block management (EBM) scheme is detailed that enhances operation and helps minimize write fatigue of the floating gate memory cells of the Flash memory device. The Flash memory device of the invention combines the EBM data in a user data erase block by placing it in an EBM data field of the control data section of the erase block sectors. Therefore distributing the EBM data within the Flash memory erase block structure. This allows the Flash memory to update and/or erase the user data and the EBM data in a single operation, to reduce overhead and speed operation. The Flash memory also reduces the process of EBM data structure write fatigue by allowing the EBM data fields to be load leveled by rotating them with the erase blocks they describe. | 05-14-2009 |
20090125671 | APPARATUS, SYSTEM, AND METHOD FOR STORAGE SPACE RECOVERY AFTER REACHING A READ COUNT LIMIT - An apparatus, system, and method are disclosed for storage space recovery after reaching a read count limit. A read module reads data in a storage division of solid-state storage. A read counter module then increments a read counter corresponding to the storage division. A read counter limit module determines if the read count exceeds a maximum read threshold, and if so, a storage division selection module selects the corresponding storage division for recovery. A data recovery module reads valid data packets from the selected storage division, stores the valid data packets in another storage division of the solid-state storage, and updates a logical index with a new physical address of the valid data. | 05-14-2009 |
20090125672 | MEMORY CARD AND HOST DEVICE THEREOF - A memory card is attached to a host device, and includes a data control circuit which transfers data with respect to the host device in synchronism with a rise edge and a fall edge of a clock signal. | 05-14-2009 |
20090125673 | MEMORY CARD AND HOST DEVICE THEREOF - A memory card is attached to a host device, and includes a data control circuit which transfers data with respect to the host device in synchronism with a rise edge and a fall edge of a clock signal. | 05-14-2009 |
20090132752 | Interface for Non-Volatile Memories - A portable storage device for storage of data. The portable storage device comprises a first non-volatile memory of a first character; a second non-volatile memory of a second character, the second character being different to the first character; and a controller for determining to which of the first and second non-volatile memory the data is to be sent. The determining is based on a defined relationship between the first and second non-volatile memories, the defined relationship being buffer or backup. | 05-21-2009 |
20090132753 | REPLICATION MANAGEMENT SYSTEM AND METHOD WITH UNDO AND REDO CAPABILITIES - A method for replicating a volume of data including UNDO and REDO data replication commands includes identifying a current state of the database through a point in time (PIT) copy of all volumes to be affected, ensuring that enough storage volume is identified to carry out the point in time copies and if not, the appropriate user warning issued notifying the user that the UNDO or REDO functions will not be available for a particular session. | 05-21-2009 |
20090132754 | DATA STORAGE DEVICE WITH HISTOGRAM OF IDLE TIME AND SCHEDULING OF BACKGROUND AND FOREGROUND JOBS - A data storage device includes a cumulative data histogram of lengths of idle times between foreground user service requests. The cumulative data histogram is updated with measured lengths of current idle times between successive user service requests. Background service request are scheduled following a user service request after a time delay that is controlled as a function of the cumulative data histogram and a calculated length of a busy time of the background service request. | 05-21-2009 |
20090132755 | FAULT-TOLERANT NON-VOLATILE INTEGRATED CIRCUIT MEMORY - Apparatus and methods are disclosed, such as those that store data in a plurality of non-volatile integrated circuit memory devices, such as NAND flash, with convolutional encoding. A relatively high code rate for the convolutional code consumes relatively little extra memory space. In one embodiment, the convolutional code is spread over portions of a plurality of memory devices, rather than being concentrated within a page of a particular memory device. In one embodiment, a code rate of m/n is used, and the convolutional code is stored across n memory devices. | 05-21-2009 |
20090132756 | Portable flash memory storage device that may show its remaining lifetime - A portable flash memory storage device that may show its remaining lifetime according to this invention is provided, in which an average erase count that is stored may be read and, after being processed and converted, is formed into a piece of information on its remaining lifetime that is further shown on a display screen of a display module in the portable flash memory storage device, and an erase is implemented on the portable flash memory storage device for an automatic update of average erase count, allowing a user to decide to replace the device or not depending on a latest remaining lifetime information. | 05-21-2009 |
20090132757 | STORAGE SYSTEM FOR IMPROVING EFFICIENCY IN ACCESSING FLASH MEMORY AND METHOD FOR THE SAME - A storage system for improving efficiency in accessing flash memory and method for the same are disclosed. The present invention provides a cache unit for temporarily storing data prior to writing in the flash memory or reading from the flash memory. In reading process, after data stored in a flash memory is accessed by a host, the cache unit holds the data. Upon subsequent read requests to read the same data, the data is cached accordingly, thereby shortening a preparation time for reading the data from the flash memory. In writing process, a host requests write a series of requests to write data into the flash memory, the data is gathered and is stored in the cache unit until the cache unit is full. A cluster of data in the cache unit is accordingly written into the flash memory, so that a preparation time for writing the data into the flash memory is also shortened. | 05-21-2009 |
20090132758 | RANK MODULATION FOR FLASH MEMORIES - We investigate a novel storage technology, Rank Modulation, for flash memories. In this scheme, a set of n cells stores information in the permutation induced by the different charge levels of the individual cells. The resulting scheme eliminates the need for discrete cell levels, and overshoot errors when programming cells (a serious problem that reduces the writing speed), as well as mitigate the problem of asymmetric errors. We present schemes for Gray codes, rewriting and joint coding in the rank modulation paradigm. | 05-21-2009 |
20090138650 | METHOD AND APPARATUS FOR MANAGING FIRMWARE OF AN OPTICAL STORAGE APPARATUS - A method of managing a firmware includes configuring the firmware to include at least a first firmware portion with a plurality of program codes, and a second firmware portion with a plurality of parameters separately; and storing the first firmware portion and the second firmware portion in a first storage area and a second storage area of a first storage module, respectively. | 05-28-2009 |
20090138651 | ENCODING METHOD FOR FLASH MEMORIES - A encoding method for a flash memory is provided, which can be used for reducing the memory wear and extend the endurance of the memory. The encoding method includes the steps as follows: (A) receiving a set of information bits; (B) counting an amount of the information bits needed to be programmed in the set; (C) reversing the set of information bits if the amount of information bits needed to be programmed is less than half of the amount of whole information bits in the set, so that there are more than half of the information bits needed to be programmed in the reversed set; and (D) programming the information bits needed to be programmed in the reversing set, including the reverse flag bit for read out check. | 05-28-2009 |
20090138652 | NON-VOLATILE MEMORY GENERATING DIFFERENT READ VOLTAGES - In one aspect, a non-volatile memory is provided which includes a plurality of m-bit non-volatile memory cells and a plurality of n-bit non-volatile memory cells, where 1≦m05-28-2009 | |
20090138653 | ELECTRONIC APPARATUS AND METHOD OF CONTROLLING A MEMORY UNIT CONNECTED TO THE SAME - An electronic apparatus in which a memory unit containing a memory and a controller to access the memory in response to an externally input command can be installed. The electronic apparatus comprises a first acquiring section which acquires identification information from the memory unit, a second acquiring section which, on the basis of the identification information acquired by the first acquiring section, acquires one from a plurality of control programs to control the controller of the memory unit, and a setting section which sets an operating environment so as to apply the control program acquired by the second acquiring section to the process of inputting and outputting data to and from the memory unit. | 05-28-2009 |
20090138654 | FATIGUE MANAGEMENT SYSTEM AND METHOD FOR HYBRID NONVOLATILE SOLID STATE MEMORY SYSTEM - A solid state memory system comprises a first nonvolatile semiconductor memory having a first write cycle lifetime and a first set of physical addresses, and a second nonvolatile semiconductor memory having a second write cycle lifetime and a second set of physical addresses. The first write cycle lifetime is greater than the second write cycle lifetime. The system further comprises a fatigue management module to generate a write frequency ranking for a plurality of logical addresses. The fatigue management module maps each of the plurality of logical addresses to a physical address of the first set of physical addresses or the second set of physical addresses based on the write frequency rankings. | 05-28-2009 |
20090144487 | STORAGE EMULATOR AND METHOD THEREOF - A storage emulator and method thereof are disclosed. The storage emulator allows a host system to access a storage unit connected to a storage system as if the storage unit is directly coupled to the host system. The storage emulator includes a virtual storage emulating module, a storage-managing unit, and a communicating module. The virtual storage emulating module emulates at least one virtual storage unit corresponding to the storage unit on the host system and receives a storage accessing command from the host system. The storage-managing unit identifies the storage accessing command as either a self-sustaining type command or a non-self-sustaining type command. The communicating module communicates with the storage unit of the storage system via the network. If the storage accessing generates a self-sustaining command response in accordance with the storage accessing command and returns the self-sustaining command response to the host system directly. If the storage accessing command is identified as the non-self-sustaining type command, the storage-managing unit forwards the storage accessing command to the storage system via the network, receives a command response in accordance with the storage accessing command from the storage system, and returns the command response to the host system. | 06-04-2009 |
20090144488 | MEMORY CARD AND METHOD FOR HANDLING DATA UPDATING OF A FLASH MEMORY - The invention provides a method for handling data updating of a flash memory. In one embodiment, the flash memory comprises a mother block comprising a plurality of updated pages to be updated. First, a spare block, recording no data, is popped as a file allocation table (FAT) block corresponding to the mother block. Data for updating the updated pages of the mother block is then written to a plurality of replacing pages of the FAT block. Finally, a plurality of mapping relationships between the replacing pages and the updated pages are recorded in a page mapping table stored in the FAT block. | 06-04-2009 |
20090144489 | ELECTRONIC DEVICE AND PROGRAM FOR OPERATING THE SAME - A navigation device realizes such processing as map display and route guidance based on map data stored in a memory card. The data in the memory card tends to be volatilized with an increase in the frequency of reading of data. Therefore, the data that are highly frequently read out are held in a RAM so as to be read from the memory card at a decreased frequency. Further, the passage of time is calculated from the date and hour the data are recorded in the memory card, and the whole data in the memory card are refreshed every time when the passage of time exceeds a threshold value T | 06-04-2009 |
20090150594 | METHOD TO MINIMIZE FLASH WRITES ACROSS A RESET - A method and apparatus described herein are for minimizing flash writes across reset. When a commonly accessed variable is to be updated, an erase conscious value is written to minimize erase operations. As an example, the location for the commonly accessed variable holds consecutive values to represent a usable value instead of a binary representation. Furthermore, when the commonly accessed variable is to be read, the stored value is translated into the associated usable value for use by a system. | 06-11-2009 |
20090150595 | BALANCED PROGRAMMING RATE FOR MEMORY CELLS - A balanced program rate on NVM cells is achieved by (i) scrambling data bits and user bits; and (ii) shifting ED bits (of data and user bits) according to an incremental shift number, which may be the PBE-counter (which provides an incremental number). ED bits for the LSS may also be shifted, according to an incremental shift number (which may be the PBE-counter). The ED bits of the shift-niumber inherently have an evenly balanced distribution The ED bits of the PBE-counter inherently have an evenly balanced distribution. | 06-11-2009 |
20090150596 | DEVICE IDENTIFIERS FOR NONVOLATILE MEMORY MODULES - A memory card has a data scrambler that performs a data scrambling operation on data stored in the memory card according to a device ID associated with the memory card. The device ID is either set at the factory and permanently stored in the card, or configurable by a user or a host system. | 06-11-2009 |
20090150597 | DATA WRITING METHOD FOR FLASH MEMORY AND CONTROLLER USING THE SAME - A data writing method for a flash memory is provided. The data writing method includes: dividing a new data into at lease one sub-data by the length of a writing unit; selecting one of a plurality of spare blocks from the flash memory as a substitute block for substituting a data block, wherein the new data is to be written into the data block; sequentially writing the sub-data having the length of the writing unit into the substitute block in the writing unit; and storing the sub-data not having the length of the writing unit into a temporary area. The writing efficiency of the flash memory can be improved by temporarily storing the sub-data not having the length of the writing unit into the temporary area and then writing the sub-data not having the length of the writing unit with subsequent data into the substitute block. | 06-11-2009 |
20090150598 | APPARATUS AND METHOD OF MIRRORING FIRMWARE AND DATA OF EMBEDDED SYSTEM - Disclosed is an apparatus and method of mirroring firmware and data of an embedded system. The embedded system mirrors a boot loader image, a kernel image, a RAM disk image and data that are stored on a main flash memory to be operated onto a secondary flash memory. Therefore, when a main flash memory does not normally work, the firmware and data that are stored on the main flash memory to be operated is mirrored onto the secondary flash memory, which prevents the loss of data and maintains the operation of the embedded system. As a result, it is possible to secure the reliability and operability of the system. | 06-11-2009 |
20090150599 | METHOD AND SYSTEM FOR STORAGE OF DATA IN NON-VOLATILE MEDIA - A system and method for managing the storage of data in non-volatile memory is described. In an aspect, the data may be described by metadata and a transaction log file that are checkpointed from a volatile memory into the non-volatile memory. Actions that take place between the last checkpointing of a metadata segment and log file segment are discovered by scanning the non-volatile memory blocks, taking account of a record of the highest sector in each block that is known to have been recorded. Any later transactions are discovered and used to update the recovered metadata so that the metadata correctly represents the stored data. | 06-11-2009 |
20090150600 | MEMORY SYSTEM - A memory system includes a nonvolatile memory having a plurality of data blocks each of which is a unit of data erase and has a plurality of pages, each of the pages being a unit of data write, and a controller which checks whether or not the nonvolatile memory has been affected by power interruption at power-on time and, if the nonvolatile memory has been affected by power interruption, writes data to that first page in a first data block which has not been affected by power interruption. | 06-11-2009 |
20090150601 | Partial Block Data Programming And Reading Operations In A Non-Volatile Memory - Data in less than all of the pages of a non-volatile memory block are updated by programming the new data in unused pages of either the same or another block. In order to prevent having to copy unchanged pages of data into the new block, or to program flags into superceded pages of data, the pages of new data are identified by the same logical address as the pages of data which they superceded and a time stamp is added to note when each page was written. When reading the data, the most recent pages of data are used and the older superceded pages of data are ignored. This technique is also applied to metablocks that include one block from each of several different units of a memory array, by directing all page updates to a single unused block in one of the units. | 06-11-2009 |
20090157946 | MEMORY HAVING IMPROVED READ CAPABILITY - In the present invention, a memory, and in particular, a NOR emulating memory comprises a memory controller having a non-volatile memory for storing program code to initiate the operation of the memory controller. The controller has a first bus for receiving address signals from a host device and a second bus for interfacing with a RAM memory, and a third bus for interfacing with a NAND memory. A volatile RAM memory is connected to the second bus. A NAND memory is connected to the third bus. The controller receives commands and a first address from the first bus, and maps the first address to a second address in the NAND memory, and operates the NAND memory in response thereto. The RAM memory serves as cache for data to or from the NAND memory. The controller also maintains data coherence between the data stored in the RAM memory as cache and the data in the NAND memory. The invention further has a first buffer for storing data from the NAND memory in response to a read command to be written to the RAM memory, and a second buffer for storing data from the RAM memory to be written to the NAND memory. In the event of a read operation, if the data from the specified address is in the RAM memory, then the data is read from the RAM memory completing the read operation. In the event of a read operation, and if the data from the specified address is not in the RAM memory, and if there is sufficient space in the RAM memory to store an entire page of data from the NAND memory, then the entire page is read from the NAND memory, stored in the first buffer and then stored in the RAM memory, and from the specified address is read out, completing the read operation. Finally, in the event of a read operation, and if the data from the specified address is not in the RAM memory, and if there is insufficient space in the RAM memory to store an entire page of data from the NAND memory, then an entire page from the RAM memory is first stored in the second buffer, then an entire page is read from the NAND memory, stored in the first buffer, and from the first buffer, stored in the now freed RAM memory and data from the specified address is read out, completing the read operation. The page of data from the second buffer is subsequently stored back into the NAND memory after the completion of the read operation thereby reducing read latency. | 06-18-2009 |
20090157947 | Memory Apparatus and Method of Evenly Using the Blocks of a Flash Memory - A memory apparatus and a method of evenly using the blocks of a flash memory are provided. The memory apparatus comprises a flash memory and a controller. The flash memory comprises a data region with a plurality of data blocks and a spare region with a plurality of spare blocks. The controller is configured to receive data corresponding to the first data block, select a spare block, program data into the spare block when the erase count corresponding to the spare block is less than the predetermined value or to select a second data block and program data stored in the second data block into the spare block when the erased count corresponding to the spare block reaches the predetermined value. As a result, the blocks of the flash memory are used evenly. | 06-18-2009 |
20090157948 | INTELLIGENT MEMORY DATA MANAGEMENT - Systems and/or methods that facilitate data management on a memory device are presented. A data management component can log and tag data creating data tags. The data tags can comprise static metadata, dynamic metadata or a combination thereof. The data management component can perform file management to allocate placement of data and data tags to the memory or to erase data from the memory. Allocation and erasure are based in part on the characteristics of the data tags, and can follow embedded rules, an intelligent component or a combination thereof. The data management component can provide a search activity that can utilize the characteristics of the data tags and an intelligent component. The data management component can thereby optimize the useful life, increase operating speed, improve accuracy and precision, improve efficiency of non-volatile (e.g., flash) memory and provide improved functionality to memory devices. | 06-18-2009 |
20090157949 | ADDRESS TRANSLATION BETWEEN A MEMORY CONTROLLER AND AN EXTERNAL MEMORY DEVICE - In one or more embodiments, address translation is performed over a dedicated serial bus between a non-volatile memory controller and a memory device that is external from the non-volatile memory device. The memory controller accesses memory address translation data in the external memory device to determine a physical address that corresponds to a logical memory address. The controller can then use the physical memory address to generate memory signals for the non-volatile memory array. | 06-18-2009 |
20090157950 | NAND flash module replacement for DRAM module - An electronic memory module according to the invention provides non-volatile memory that can be used in place of a DRAM module without battery backup. An embodiment of the invention includes an embedded microprocessor with microcode that translates the FB-DIMM address and control signals from the system into appropriate address and control signals for NAND flash memory. Wear-leveling, bad block management, garbage collection are preferably implemented by microcode executed by the microprocessor. The microprocessor, additional logic, and embedded memory provides the functions of a flash memory controller. The microprocessor memory preferably contains address mapping tables, free page queue, and garbage collection information. | 06-18-2009 |
20090157951 | INFORMATION RECORDING DEVICE AND INFORMATION RECORDING METHOD - An information recording device includes a table showing a physical address in first and second areas and a number of rewriting at the physical address in a correspondence manner, the first area being a writing destination in a recording medium configured to be consumed by rewriting, the second area being not a writing destination in the recording medium, an instructor configured to instruct to change the first and second tables based on the first table and the physical address of the writing destination, a changer configured to change the table based on the instruction, and a writer configured to write data to the recording medium based on the physical address in the first area. | 06-18-2009 |
20090157952 | Semiconductor memory system and wear-leveling method thereof - Disclosed is a semiconductor memory system and wear-leveling method thereof. The semiconductor memory system is comprised of a nonvolatile memory including a plurality of logic blocks each of which is divided into a plurality of entries, a file system detecting a type of data to be stored and allocating the logic block or the entry for storing the data in accordance with the data type, and a translation layer leveling wearing degrees over the logic blocks or the entries in accordance with the data type. The semiconductor memory system is improved in performance and lifetime by managing wearing degrees over the logic block or the entries in accordance with the data type. | 06-18-2009 |
20090157953 | Data line disturbance free memory block divided flash memory and microcomputer having flash memory therein - A semiconductor device having an electrically erasable and programmable nonvolatile memory, for example, a rewritable nonvolatile memory including memory cells arranged in rows and columns and disposed to facilitate both flash erasure as well as selective erasure of individual units of plural memory cells. The semiconductor device which functions as a microcomputer chip also has a processing unit and includes an input terminal for receiving an operation mode signal for switching the microcomputer between a first operation mode in which the flash memory is rewritten under control of a processing unit and a second operation mode in which the flash memory is rewritten under control of separate writing circuit externally connectable to the microcomputer. | 06-18-2009 |
20090164700 | EFFICIENT MEMORY HIERARCHY IN SOLID STATE DRIVE DESIGN - Systems and methods for improving the performance and reliability of flash memory solid state drive devices are described herein. A flash memory array component stores data. A memory hierarchy component transfers data between the host and the flash memory array component. The memory hierarchy component includes a level one (“L1”) cache coupled to a merge buffer, the flash memory array component, and the host. The merge buffer is coupled to the flash memory array component. The L1 cache and merge buffer include volatile memory, and the host is coupled to the merge buffer and flash memory array component. The memory hierarchy component includes a write component and a read component. The write component writes data to at least one of the L1 cache, merge buffer, or flash memory array component. The read component reads data from at least one of the L1 cache, merge buffer, or flash memory array component. | 06-25-2009 |
20090164701 | PORTABLE IMAGE INDEXING DEVICE - A portable image-indexing device that includes a port adapter for connecting to a personal computer and a port adapter for receiving a camera card. The device includes memory for storing a plurality of image and video files and for storing image indexing application programs. A processor performs image indexing on images and/or videos and includes a power source. | 06-25-2009 |
20090164702 | FREQUENCY DISTRIBUTED FLASH MEMORY ALLOCATION BASED ON FREE PAGE TABLES - Systems and/or methods that provide for frequency distributed flash memory allocation are disclosed. The systems and methods determine the rate at which a system address is being written and the current erase cycle state of each data block in the non-volatile memory device and assigns a physical address to the write operation based on the determined system address rate and the current erase state of each data block in the non-volatile system. In this regard, system addresses that are assigned more frequently are assigned physical page addresses from data blocks which have a low erase cycle state (i.e., greater cycle endurance remaining) and system addresses that assigned less frequently are assigned physical page addresses from data blocks which have a high erase cycle state (i.e., lesser cycle endurance remaining). The result is a more robust non-volatile device having increased erase/initialization cycle endurance, which adds to the overall reliability of the device over time. | 06-25-2009 |
20090164703 | FLEXIBLE FLASH INTERFACE - Systems and methods that can facilitate providing a flexible flash interface component that can accommodate communicating with almost any flash memory component (e.g., Open NAND Flash Interface (ONFI) compliant and ONFI noncompliant flash memory). A micro-operations component can contain one or more micro-operation that can be used to execute commands within the flash interface component. To facilitate a flexible flash interface, the micro-operations can include such commands as, but are not limited to, sending a command to the flash memory, sending a row address, sending a column address, transmit data (TXD), receive data (RXD), have the flash interface wait for a ready signal from the flash memory, read a status register from a flash memory, and/or provide an end of sequence (EOS) indication to the flash interface, for example. | 06-25-2009 |
20090164704 | HIGH PERFORMANCE FLASH CHANNEL INTERFACE - Systems and/or methods that facilitate high performance flash channel interface techniques are presented. Integrated error correction code (ECC) engine and buffer sets facilitate bypassing error correction of data being written to or read from memory, such as flash memory, in addition to single ECC mode or multiple ECC mode. The integrated ECC engines and buffers can quickly analyze data, and provide error correction information or correct error, significantly increasing throughput. In addition, the programmable flash channel interface can provide more rapid development of flash products by accommodating both Open NAND Flash Interface (ONFI) standard flash and legacy flash devices, by using a configurable micro-code engine in the flash interface. | 06-25-2009 |
20090164705 | System and Method for Implementing Extensions to Intelligently Manage Resources of a Mass Storage System - Systems and methods for implementing extensions to intelligently manage resources of a mass storage system are disclosed. Generally, a host sends an extension of an enabled set of extensions to a mass storage system that includes at least one of command sequence information, command information or file attribute information. The host additionally sends a host application command to the mass storage system that includes logical block address information associated with the at least one of command sequence information, command information or file attribute information of the extension. Based on the received extension, the mass storage system intelligently performs operations that efficiently manage the resources of the mass storage system to reduce the frequency of operations such as data consolidation operations, data collection operations, and data copy operations, thereby increasing the data programming and reading performance of the mass storage system. | 06-25-2009 |
20090164706 | Emulation of a NAND memory system - A system and a method for emulating a NAND memory system are disclosed. In the method, a command associated with a NAND memory is received. After receipt of the command, a vertically configured non-volatile memory array is accessed based on the command. In the system, a vertically configured non-volatile memory array is connected with an input/output controller and a memory controller. The memory controller is also connected with the input/output controller. The memory controller is operative to interface with a command associated with a NAND memory and based on the command, to access the vertically configured non-volatile memory array for a data operation, such as a read operation or write operation. An erase operation on the vertically configured non-volatile memory array is not required prior to the write operation. The vertically configured non-volatile memory array can be partitioned into planes, blocks, and sub-planes, for example. | 06-25-2009 |
20090164707 | Method and system for accessing non-volatile memory - Accessing a non-volatile memory array is described, including receiving a first data and a memory address associated with the first data, writing the first data to the non-volatile memory array at the memory address of the first data without erasing a second data stored in the non-volatile memory array at the memory address of the first data before writing the first data. | 06-25-2009 |
20090164708 | MEMORY CHIP WITH EXTENDED INPUT/OUTPUT INTERFACE - A memory chip ( | 06-25-2009 |
20090164709 | SECURE STORAGE DEVICES AND METHODS OF MANAGING SECURE STORAGE DEVICES - Methods of managing a secure area in a secure storage device include conducting an authentication process between a host and the secure storage device while modifying a size of the secure area, backing up secure data to the host from the secure area after completing the authentication process, updating management information to modify a size of the secure area, and storing the secure data, which has been backed up to the host, into the secure area that is modified in size. Related storage devices are also disclosed. | 06-25-2009 |
20090164710 | SEMICONDUCTOR MEMORY SYSTEM AND ACCESS METHOD THEREOF - A semiconductor memory system and access method thereof. The semiconductor memory system includes a nonvolatile memory and a memory controller. The nonvolatile memory stores monitoring data in one or more of plural memory cells. The memory controller controls the nonvolatile memory. The memory controller detects the monitoring data and adjusts a bias voltage, which is provided to the plural memory cells, in accordance with a result of the detection. | 06-25-2009 |
20090164711 | SEMICONDUCTOR MEMORY CONTROLLER, SEMICONDUCTOR MEMORY, AND METHOD OF CONTROLLING SEMICONDUCTOR MEMORY CONTROLLER - A semiconductor memory controller, which outputs data to be stored in a memory unit to the memory unit via a bus of N-bit width (N is an even number), executes a duplexing process on the data to generate duplicated data, simultaneously outputs the respective duplicated data to two different sections of the memory unit using N/2 bit width for each duplicated data, and stores the duplicated data in the two sections of the memory unit, respectively. | 06-25-2009 |
20090164712 | FLASH MEMORY - A flash memory includes a memory sector, a command interface, a first signal buffer, a control signal generation circuit, a data input buffer, an error correction circuit, an address buffer, an address signal generation circuit, a plurality of data memory circuits, and write circuit. The command interface receives a write data input instruction from an external device to generate a write data input instruction signal, and receives a write instruction from the external device to generate a write instruction signal. The error correction circuit is activated by the write data input instruction signal to receive the write data in synchronization with the write enable signal, and is activated by the write instruction signal to generate a check data for an error correction in synchronization with the control signal. | 06-25-2009 |
20090172246 | DEVICE AND METHOD FOR MANAGING INITIALIZATION THEREOF - A host may initialize itself faster by enabling an associated storage device to respond to host access commands under specified conditions before the storage device has completed its own initialization. Embodiments of the invention include a storage device, a controller, a method of servicing commands, and a method of using a host that sends access commands to a storage device. Access commands to a flash memory use logical addresses to reference the memory contents. A controller translates the logical addresses to physical addresses using a mapping table that the controller constructs in volatile memory during initialization based on data retrieved from the flash memory. An access command satisfying a predefined condition is serviced before the controller completes the construction of the mapping table. | 07-02-2009 |
20090172247 | CONTROLLER FOR ONE TYPE OF NAND FLASH MEMORY FOR EMULATING ANOTHER TYPE OF NAND FLASH MEMORY - A controller for one type of NAND flash memory device that emulates another type of NAND flash memory device. The controller may include a host NAND interface to receive host data from a NAND host device, and a data aggregator for aggregating the host data with complementary data, to thereby create device data that is storable in a device page of an array of NAND flash memory cells of the NAND flash memory device. After creating the device data the controller writes the device data into a device page of the NAND flash memory cells. The controller also includes a data parser to parse host data from device data when data read operations are executed by the controller. If required, the controller uses the data parser to parse complementary data from device data to create device data when data writing operations are executed by the controller. | 07-02-2009 |
20090172248 | MANAGEMENT OF A FLASH MEMORY DEVICE - Methods, computing devices and machine readable medium to manage sector based file system accesses to block erasable flash memory devices are disclosed. One disclosed method includes allocating erasable blocks of a flash memory device to a volume and formatting the volume of a flash memory device with a file system designed to access the flash memory device via sectors that are each smaller than an erasable block. The method also includes writing a data unit to a special block of the erasable blocks and writing a sector mapping table unit to the special block to associate the data unit with a sector of the file system. The method further includes allocating a spare block of erasable blocks to support a reclaim process. | 07-02-2009 |
20090172249 | DYNAMICALLY ADJUSTING CACHE POLICY BASED ON DEVICE LOAD IN A MASS STORAGE SYSTEM - A dynamic cache policy manager for a mass memory may be used to decide whether a data request is to be routed to the cache or directly to the mass memory, based on estimated delays in processing the request. The choice may be based, at least partially, on the size of the respectively queues for the cache and mass memory. For write requests, the choice may be based on how many erase blocks are available in the cache. | 07-02-2009 |
20090172250 | RELOCATING DATA IN A MEMORY DEVICE - Systems and methods that can facilitate more optimized relocation of data associated with a memory are presented. In addition to a memory controller component, a memory manager component can be employed to increase available processing resources to facilitate more optimal execution of higher level functions. Higher level functions can be delegated to the memory manager component to allow execution of these higher level operations with reduced or no load on the memory controller component resources. A uni-bus or multi-bus architecture can be employed to further optimize data relocation operations. A first bus can be utilized for data access operations including read, write, erase, refresh, or combinations thereof, among others, while a second bus can be designated for higher level operations including data compaction, error code correction, wear leveling, or combinations thereof, among others. | 07-02-2009 |
20090172251 | Memory Sanitization - Apparatus and method for memory sanitization is disclosed, including a memory, the memory including—in whole or in part—multiple layers of memory, and control logic configured to perform a sanitize operation on a portion of the memory. In one example, a third dimensional memory array can constitute at least a portion of the multiple layers of memory. The multiple layers of memory may include non-volatile two-terminal cross-point memory arrays. Each non-volatile two-terminal cross-point memory array can include a plurality of two-terminal memory elements that store data as a plurality of conductivity profiles that can be non-destructively determined by applying a read voltage across the terminals of the two-terminal memory element. The two-terminal memory elements retain stored data in the absence of power. The non-volatile two-terminal cross-point memory arrays can be vertically stacked upon one another and may be positioned on top of a logic plane that includes active circuitry. | 07-02-2009 |
20090172252 | Memory device and method for performing a write-abort-safe firmware update - A memory device and method for performing a write-abort-safe firmware update are disclosed. In one embodiment, a location in a memory of a memory device for a firmware update is allocated. The firmware update is written into the allocated location in the memory. A pointer is written to the firmware update in a directory, and a pointer is written to the directory in a location in the memory that is read during boot-up. In another embodiment, a block in a memory of a memory device is allocated for updated file system data comprising a firmware update and a directory. The updated file system data is written into the allocated location in the memory. A pointer is written to the firmware update in the directory, and a pointer is written to the updated file system data in a boot block in the memory, wherein the boot block is read during boot-up. | 07-02-2009 |
20090172253 | Methods and apparatuses for nonvolatile memory wear leveling - Apparatuses, systems, and computer program products that enable wear leveling of nonvolatile memory devices, such as flash memory devices, are disclosed. One or more embodiments an apparatus that has a receiver and a wear leveling module. The receiver may receive low-level write requests to update direct-mapped values of nonvolatile memory. The wear leveling module may determine physical locations of the nonvolatile memory that correspond to logical locations of the write requests. Alternative embodiments may comprise systems or apparatuses that include one or more various types of additional modules, such as low-level driver modules, error correction code modules, queue modules, bad block management modules, and flash translation layer modules. Other embodiments comprise computer program products that receive a direct-mapped low-level write request, determine a physical write location of nonvolatile memory that corresponds to a logical write location of the low-level write request. | 07-02-2009 |
20090172254 | METHOD FOR PREVENTING READ-DISTURB HAPPENED IN NON-VOLATILE MEMORY AND CONTROLLER THEREOF - A method for preventing read-disturb happened in non-volatile memory and a controller thereof are disclosed. The non-volatile memory includes a plurality of blocks, and the blocks are grouped into at least a data group and a spare group, each block includes a plurality of pages. The method includes recording read times of at least a first block of the blocks within the data group and then renewing the original data stored in the first block when the read times of the first block is greater than a predetermined value. | 07-02-2009 |
20090172255 | WEAR LEVELING METHOD AND CONTROLLER USING THE SAME - A wear leveling method for a multi level cell (MLC) NAND flash memory is provided. The flash memory includes a first zone and a second zone respectively having a plurality of blocks, wherein each of the blocks includes an upper page and a lower page. The wear leveling method includes: respectively determining whether to start a block swapping operation of a wear leveling process in the first zone and the second zone of the flash memory according to different start-up conditions; and respectively performing the block swapping operation in the first zone and the second zone, wherein the blocks in the first zone are accessed by using only the lower pages, and the blocks in the second zone are accessed by using both the upper pages and the lower pages. Thereby, the lifespan of the flash memory is effectively prolonged and meaningless consumption of system resources is avoided. | 07-02-2009 |
20090172256 | DATA WRITING METHOD FOR FLASH MEMORY, AND FLASH MEMORY CONTROLLER AND STORAGE DEVICE THEREOF - A data writing method for a block of a multi level cell NAND flash memory including upper page addresses and lower page addresses is provided, wherein a writing speed at the lower page addresses is higher than that at the upper page addresses. The data writing method includes receiving a writing command and determining whether an address to be written with new data in the writing command is the upper page address of the block. The method also includes copying old data previously recorded on the lower page addresses of the block as an old data backup when the address to be written in the writing command is the upper page address of the block and then writing the new data to the address to be written. Thus, old data may be protected while writing data to the upper page address of the multi level cell NAND flash memory. | 07-02-2009 |
20090172257 | System and method for performing host initiated mass storage commands using a hierarchy of data structures - Disclosed is a mass storage system and method for breaking a host command into a hierarchy of data structures. Different types of data structures are designed to handle different phases of tasks required by the host command, and multiple data structures may be used to handle portions of the host command in parallel, thereby allowing increased performance. The disclosed embodiments include a flash memory controller designed to allow a high degree of pipelining and parallelism. | 07-02-2009 |
20090172258 | Flash memory controller garbage collection operations performed independently in multiple flash memory groups - A flash memory controller connected to multiple flash memory groups performs independent garbage collection operations in each group. For each group, the controller independently determines the amount of free space and performs garbage collection operations if the amount falls below a threshold. | 07-02-2009 |
20090172259 | Mass storage controller volatile memory containing metadata related to flash memory storage - A volatile memory associated with a mass storage controller and a flash memory module. The volatile memory includes a number of tables containing information related to the flash memory storage, including a table storing physical flash memory addresses and a plurality of tables containing metadata. | 07-02-2009 |
20090172260 | Flash memory controller and system including data pipelines incorporating multiple buffers - A storage controller connected to a flash memory storage module, the controller and module including multiple sets of buffers. The buffers are part of one or more pipelines through which data is moved between the storage module and one or more hosts. | 07-02-2009 |
20090172261 | Multiprocessor storage controller - A storage controller containing multiple processors. The processors are divided into groups, each of which handles a different stage of a pipelined process of performing host reads and writes. In one embodiment, the storage controller operates with a flash memory module, and includes multiple parallel pipelines that allow plural host commands to be handled simultaneously. | 07-02-2009 |
20090172262 | Metadata rebuild in a flash memory controller following a loss of power - A method of rebuilding metadata in a flash memory controller following a loss of power. The method includes reading logical address information associated with an area of flash memory, and using time stamp information to determine if data stored in the flash memory area is valid. | 07-02-2009 |
20090172263 | Flash storage controller execute loop - In a storage controller connected to a flash memory module, an execute loop used to carry out tasks related to reading or writing data from the module. The loop includes reading a data structure from a queue and carrying out a task specified by the data structure, unless resources required by the task are not available, in which event the loop moves on to another data structure stored in another queue. Data structures bypassed by the loop are periodically revisited, until all tasks required are completed. Data structures store state information that is updated when tasks are completed. | 07-02-2009 |
20090172264 | SYSTEM AND METHOD OF INTEGRATING DATA ACCESSING COMMANDS - A data accessing command integration method includes the following steps. Firstly, M data accessing commands are sequentially received through a bus, wherein N data accessing commands contained in the M data accessing commands have the same command type and comply with a sequential address relationship. Next, the N data accessing commands are re-ordered according to the addressing sequence, so that a first data corresponding to the re-ordered N data accessing commands are sequentially accessed in the data memory. | 07-02-2009 |
20090172265 | FLASH MEMORY DEVICE HAVING SECURE FILE DELETION FUNCTION AND METHOD FOR SECURELY DELETING FLASH FILE - Disclosed is a flash memory device having a secure flash file deletion function and a method for securely deleting a flash file. Data and object headers as actual contents of the flash file are separately stored in data blocks and header blocks. At this time, the data is encrypted and stored, and a decryption key is included in an object header and stored in a header block. When the flash file is deleted, the object header is deleted by searching the header block where the object header including the decryption key is stored. In order to search the header block, a binary tree structure is used in which a terminal node indicates an LSB of a file ID. Disclosed may be applied to an embedded system where a flash memory is used as a storage medium. In particular, disclosed is suitable for a NAND flash memory device. | 07-02-2009 |
20090172266 | MEMORY SYSTEM - A memory system includes a NAND flash memory including a memory block containing a plurality of pages, and a controller which controls write of data to the flash memory, and includes a scrambling circuit which converts the data into a pseudo random number, wherein the scrambling circuit includes an initial value generator which generates an initial value for every segment, an initial value shifter which shifts the initial value by N bits for every page address, a pseudo random number generator which generates a pseudo random number sequence by an M-sequence by using the initial value shifted N bits, and a random number adder which adds the pseudo random number sequence to the data. | 07-02-2009 |
20090172267 | REFRESH METHOD OF A FLASH MEMORY - A flash memory device includes a flash memory that stores many physical data blocks, a refresh management table that stores indications of the number of times each individual physical data block has been read, and a controller responsive to read and erase control signals from a source external to the flash memory device, and to the stored indications of the refresh management table for controlling reading, erasing and refreshing of the individual physical data blocks. In response to the number of times each individual physical data block has been read being equal to or exceeding a limit value, the controller refreshes the individual physical data block associated with the indication equaling or exceeding the limit value. | 07-02-2009 |
20090172268 | METHOD FOR SECURING A MICROPROCESSOR, CORRESPONDING COMPUTER PROGRAM AND DEVICE - A method is provided for securing a microprocessor containing at least one main program, which operates with at least one memory. The method includes implementing counter-measures, during which additional operations, that are not required for the main program, are implemented so as to modify the consumption of current and/or the processing time of the microprocessor. The method also includes: identification of at least one address or one memory zone of the memory(ies), called critical addresses, and which contain, or which may contain, critical data for said main program; monitoring the addressing ports of the memory(ies), so as to detect the access to the critical address(es); and activation of the step of implementing counter-measures, when an access to the critical address(es) is detected. | 07-02-2009 |
20090172269 | NONVOLATILE MEMORY DEVICE AND ASSOCIATED DATA MERGE METHOD - A memory system is disclosed with a nonvolatile memory adapted to store a file system containing file system information, and a controller adapted to read the file system information and perform a merge operation. | 07-02-2009 |
20090177833 | Buffering systems methods for accessing multiple layers of memory in integrated circuits - Embodiments of the invention relate generally to data storage and computer memory, and more particularly, to systems, integrated circuits and methods for accessing memory in multiple layers of memory implementing, for example, third dimension memory technology. In a specific embodiment, an integrated circuit is configured to implement write buffers to access multiple layers of memory. For example, the integrated circuit can include memory cells disposed in multiple layers of memory. In one embodiment, the memory cells can be third dimension memory cells. The integrated circuit can also include read buffers that can be sized differently than the write buffers. In at least one embodiment, write buffers can be sized as a function of a write cycle. Each layer of memory can include a plurality of two-terminal memory elements that retain stored data in the absence of power and store data as a plurality of conductivity profiles. | 07-09-2009 |
20090177834 | METHOD FOR MANAGING DATA INTENDED TO BE WRITTEN TO AND READ FROM A MEMORY - The invention relates to a method for managing data intended to be written to and read from a memory of FLASHPROM type organized into pages. Several data are stored per page and the method consists:
| 07-09-2009 |
20090177835 | Flash Drive With Spring-Loaded Retractable Connector - A pen-type computer peripheral device includes an elongated housing containing a PCBA having a plug connector. The PCBA is secured to a positioning member that is actuated by way of a press-push button that is exposed through a slot defined in a wall of the housing. A spring-loaded mechanism includes a spring and a locking mechanism that locks the connector in a retracted position and a deployed position, and the spring biases the connector from the retracted position to the deployed position, or vice versa. | 07-09-2009 |
20090182933 | DURABLE DATA STORAGE SYSTEM AND METHOD - A method of operating a storage system, comprising: issuing a first command to write a first data to a first nonvolatile storage device; writing the first data to a second nonvolatile storage device if write condition is unstable; retrieving the first data from the second nonvolatile storage device; and writing the first data to the first nonvolatile storage device during a stable write condition, wherein whether write condition is stable is determined based on one of a sensor output or a memory access status signal, and wherein the memory access status signal is one of a predetermined value of retries, idling, access commands, or any combination thereof. | 07-16-2009 |
20090182934 | Memory device and method of multi-bit programming - Memory devices and multi-bit programming methods are provided. A memory device may include a plurality of memory units; a data separator that separates data into a plurality of groups; a selector that rotates each of the plurality of groups and transmits each of the groups to at least one of the plurality of memory units. The plurality of memory units may include page buffers that may program the transmitted group in a plurality of multi-bit cell arrays using a different order of a page programming operation. Through this, evenly reliable data pages may be generated. | 07-16-2009 |
20090182935 | MASS STORAGE DEVICE, IN PARTICULAR OF THE USB TYPE, AND RELATED METHOD FOR TRANSFERRING DATA - A mass storage device of the present invention includes one or more memory elements and a logic module adapted to interface the one or more memory elements for exchanging data according to a data exchange protocol, in particular of the USB type, through a first port. The mass storage device has a module for detecting the presence of a power voltage associated with a first connector of the first port, and the logic module can set the storage device to either a Host or a Function device configuration depending on the detection carried out by the module for detecting the presence of a power voltage. The device also includes a second port adapted to implement a direct data exchange with further storage devices. The device additionally offers the possibility of communicating with radio or optical wireless ports exchanging data through a data bus, e.g. of the USB type. | 07-16-2009 |
20090182936 | SEMICONDUCTOR MEMORY DEVICE AND WEAR LEVELING METHOD - Disclosed is a semiconductor memory device and wear leveling method thereof. The semiconductor memory device including: a nonvolatile memory having pluralities of memory blocks, at least one of the memory blocks storing erasing counts of the memory blocks; and a memory controller managing wear leveling of the nonvolatile memory. The memory controller adjusts a period of managing the wear leveling with reference to the erasing counts. | 07-16-2009 |
20090182937 | SEMICONDUCTOR MEMORY CARD, AND PROGRAM FOR CONTROLLING THE SAME - A semiconductor memory card that has a sufficient storage capacity when an EC application writes data to a storage is provided. A usage area for the EC application in an EEPROM | 07-16-2009 |
20090187700 | RETARGETING OF A WRITE OPERATION RETRY IN THE EVENT OF A WRITE OPERATION FAILURE - Methods and systems are herein disclosed for write operation retry using the data stored and retained in an internal buffer within the non-volatile memory device. By using the data stored in the internal buffer, the systems and method of the present invention eliminate the need to include a dedicated retry buffer at the system level. Thereby, reducing the system cost, minimizing space consumption on a board within the system and, in some instance, limiting the latency attributed to a retry that relies on retrying the write based on re-transferring of the data contents to the internal non-volatile memory buffer. | 07-23-2009 |
20090187701 | Nand flash memory access with relaxed timing constraints - Timing constraints on data transfers during access of a NAND flash memory can be relaxed by providing a plurality of data paths that couple the NAND flash memory to a buffer that provides external access to the memory. The buffer defines a bit width associated with the external access, and each of the data paths accommodates that bit width. | 07-23-2009 |
20090187702 | NONVOLATILE MEMORY - For a nonvolatile memory permitting electrical writing and erasing of information to be stored, such as a flash memory, the load on the system developer is to be reduced, and it is to be made possible to avoid, even if such important data for the system as management and address translation information are damaged, an abnormal state in which the system becomes unable to operate. The nonvolatile memory is provided with a replacing function to replace a group of memory cells including defective memory cells which are incapable of normal writing or erasion with a group of memory cells including no defective memory cell, a numbers of rewrites averaging function to grasp the number of data rewrites in each group of memory cells and to so perform replacement of memory cell groups that there may arise no substantial difference in the number of rewrites among a plurality of memory cell groups, and an error correcting function to detect and correct any error in data stored in the memory array, wherein first address translation information deriving from the replacing function and second address translation information deriving from the numbers of rewrites averaging function are stored in respectively prescribed areas in the memory array, and the first address translation information and second address translation information concerning the same memory cell group are stored in a plurality of sets in a time series. | 07-23-2009 |
20090187703 | MEMORY CARD AND ITS INITIAL SETTING METHOD - In the initial setting of a memory card | 07-23-2009 |
20090193176 | Data storage device having a built-in display - A data storage device for an electronic device includes a hard disk for storing a plurality of pieces of data, a nonvolatile memory for storing a plurality of file names corresponding to the pieces of data, a display, and a controller connected electrically to the hard disk, the nonvolatile memory and the display unit, and operable so as to permit viewing of the file names stored in the nonvolatile memory by displaying a viewing result including a viewed one of the file names on the display. | 07-30-2009 |
20090193177 | Virtual Processor Based Security For On-Chip Memory, and Applications Thereof - A processor-based method, system and apparatus to comprise a method, system and apparatus to access a memory location in an on-chip memory based on a virtual processing element identification associated with an instruction. The system comprises multiple virtual processing elements, an access list and a comparator coupled to the memory and the access list. In response to an instruction from a virtual processing element to access a memory location in the memory, the comparator compares a first virtual processing identification associated with the instruction to a second virtual processing identification stored in the access list and grants access to the virtual processing element to read from or write to the memory location if the first virtual processing element identification is equal to the second virtual processing element identification. The data in the memory is allocated and de-allocated by software. In one embodiment, the access list is instantiated in hardware and cannot be read from or written to by software. A virtual processing element comprises multiple hardware thread contexts with each thread context being associated with a distinct register file. | 07-30-2009 |
20090193178 | SYSTEMS AND METHODS FOR POWER MANAGEMENT IN RELATION TO A WIRELESS STORAGE DEVICE - Various embodiments of the present invention provide systems and methods for reducing power consumption in a device including a memory system. As one example, a system may include a memory system with a hard disk drive and a flash memory. The flash memory maintains a menu file that includes a list of content objects available on the hard disk drive. In addition, the system includes a processor that executes software maintained on the memory system to update the menu file when a previously unavailable content object becomes available on the hard disk drive. Further, in some cases, the processor executes software that is operable to update the menu file when a previously available content object becomes unavailable on the hard disk drive. Additionally, the systems may include instructions executable by the processor to receive a play list, and to copy a first content object identified on the play list from the hard disk drive to the flash memory, and to copy a second content object identified on the play list from the hard disk drive to the flash memory. With the content objects thus moved to the flash memory, they can be uploaded to either the application device that supplied the play list, or to another application device designated as the recipient of the content objects. | 07-30-2009 |
20090193179 | Information processing apparatus - A main memory and a hard disk include predetermined serial numbers. A flash memory registers the main memory and hard disk together with their serial numbers. A BIOS reads the serial numbers from the main memory and hard disk. When a read-out serial number is not registered in the flash memory, the BIOS places the information processing apparatus in an unusable state. | 07-30-2009 |
20090193180 | SEMICONDUCTOR MEMORY DEVICE AND CONTROL METHOD FOR SEMICONDUCTOR MEMORY DEVICE - A memory card capable of connecting to a host device includes a flash memory, a host interface unit which transfers data between a host device and the memory card, and a transfer mode control unit which changes a data transfer mode based on a command from the host device. The transfer mode control unit outputs status data containing an error code to the host device if a transfer mode change command is inputted from the host device, instructing the memory card to change to a transfer mode not supported by the host interface unit of the memory card. | 07-30-2009 |
20090193181 | Control Unit, Image Processing Apparatus and Computer-Readable Storage Medium - A memory information storage control method is executed by a control unit which carries out a memory information storage process to generate memory information related to a program being executed by the control unit and to store the memory information. The memory information storage control method includes an interface process to register a storage location of the memory information generated by the memory information storage process, a registering process to register a portable storage device as the storage location of the memory information using the interface process, and an executing process to confirm coupling of the portable storage device to the control unit and to register the storage location of the memory information in the detachably coupled portable storage device by the registering process. | 07-30-2009 |
20090193182 | INFORMATION STORAGE DEVICE AND CONTROL METHOD THEREOF - According to one embodiment, an information storage device includes a non-volatile storage medium, a non-volatile memory configured to store specific data blocks to be read for a host device and write data to be written to the non-volatile storage medium, a buffer configured to temporarily store write data transmitted from the host device, and a controller. The controller is configured to delete synchronized data the same data block as which exists on the non-volatile storage medium among the specific data blocks stored in the non-volatile memory if the free space of the non-volatile memory is smaller than a given data size, and to write the write data stored in the buffer to the non-volatile memory. | 07-30-2009 |
20090193183 | NONVOLATILE MEMORY SYSTEM, AND DATA READ/WRITE METHOD FOR NONVOLATILE MEMORY SYSTEM - A nonvolatile memory system comprises a nonvolatile memory having a plurality of data areas; and a memory controller operative to control read and write operations to the nonvolatile memory. The memory controller successively executes read/write operations to plural sectors within a selected data area in the nonvolatile memory in accordance with a command and a sector count and sector address fed from a host device. | 07-30-2009 |
20090193184 | Hybrid 2-Level Mapping Tables for Hybrid Block- and Page-Mode Flash-Memory System - A hybrid solid-state disk (SSD) has multi-level-cell (MLC) or single-level-cell (SLC) flash memory, or both. SLC flash may be emulated by MLC that uses fewer cell states. A NVM controller converts logical block addresses (LBA) to physical block addresses (PBA). Most data is block-mapped and stored in MLC flash, but some critical or high-frequency data is page-mapped to reduce block-relocation copying. A hybrid mapping table has a first-level and a second level. Only the first level is used for block-mapped data, but both levels are used for page-mapped data. The first level contains a block-page bit that indicates if the data is block-mapped or page-mapped. A PBA field in the first-level table maps block-mapped data, while a virtual field points to the second-level table where the PBA and page number is stored for page-mapped data. Page-mapped data is identified by a frequency counter or sector count. SRAM space is reduced. | 07-30-2009 |
20090198869 | ERASE COUNT RECOVERY - An erase count of a flash memory block which is lost, e.g., due to power failure is updated or replaced by using known erase counts of other blocks of the flash memory. A flash management algorithm assigns a new erase count value instead of the lost one based on either a maximum value, an average value or a value combining the maximum value of the known erase counts and some tolerance value. The known values may be obtained from wear leveling data or from a stored erase history. | 08-06-2009 |
20090198870 | Methods and Media for Writing Data to Flash Memory - A method for writing bytes to flash memory is disclosed herein whereby the method comprising includes counting bytes from a data source, the bytes associated with a first value and a second value and comparing a number of bytes associated with the first value with a number of bytes associated with the second value. The method may further include inverting the bytes in the case where the number of bytes associated with the first value is greater than the number of bytes associated with the second value and transferring the bytes not associated with the second value to the flash memory. | 08-06-2009 |
20090198871 | EXPANSION SLOTS FOR FLASH MEMORY BASED MEMORY SUBSYSTEM - A memory system is provided. The system includes a controller that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the controller to regulate read and write access to the one or more FLASH devices. Wear leveling components along with read and write processing components are provided to facilitate efficient operations of the FLASH memory devices. | 08-06-2009 |
20090198872 | HARDWARE BASED WEAR LEVELING MECHANISM - A memory system is provided. The system includes a controller that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the controller to regulate read and write access to the one or more FLASH devices. Wear leveling components along with read and write processing components are provided to facilitate efficient operations of the FLASH memory devices. | 08-06-2009 |
20090198873 | PARTIAL ALLOCATE PAGING MECHANISM - A memory system is provided. The system includes a controller that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the controller to regulate read and write access to the one or more FLASH devices. Wear leveling components along with read and write processing components are provided to facilitate efficient operations of the FLASH memory devices. | 08-06-2009 |
20090198874 | MITIGATE FLASH WRITE LATENCY AND BANDWIDTH LIMITATION - A memory system is provided. The system includes a controller that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the controller to regulate read and write access to the one or more FLASH devices. Wear leveling components along with read and write processing components are provided to facilitate efficient operations of the FLASH memory devices. | 08-06-2009 |
20090198875 | DATA WRITING METHOD FOR FLASH MEMORY, AND CONTROLLER AND SYSTEM USING THE SAME - A data writing method for a flash memory is provided. The data writing method includes following steps. First, a block is selected as a substitute block from a spare area of the flash memory, wherein the substitute block is used for substituting a data block in a data area for writing a new data. Next, the new data is directly written into the substitute block starting from a start page, wherein there is valid data in the data block before the address for writing the new data. Thereby, meaningless data moving can be reduced, system performance can be improved, and overlong waiting time for writing the new data can be prevented. | 08-06-2009 |
20090198876 | Programmable Command Sequencer - An embedded subsystem IC which provides simple procedures for an external CPU IC to invoke one or more functions provided by modules of the subsystem is disclosed. The embedded subsystem comprises at least one module to perform at least one function, a first memory, and a sequence controller. Each module is controlled by values stored in local registers of the module. The first memory stores at least one predefined sequence of instructions. Each instruction sequence controls a module to perform a function. The sequence controller comprises a second memory to store a vector table and a state machine. In response to receiving a command the CPU, the sequence controller obtains a start address in the first memory of an instruction sequence corresponding with the command. The state machine programs one or more registers of a module that performs the function identified by the command according to the instruction sequence that begins with the start address. | 08-06-2009 |
20090198877 | SYSTEM, CONTROLLER, AND METHOD FOR DATA STORAGE - A system, a controller, and a method for data storage are provided. The system includes a first storage unit, a second storage unit, and a controller. The first storage unit comprises a single-layer structure for storing data, and the second storage unit comprises a multi-layer structure for storing data. The controller is coupled to the first storage unit, the second storage unit, and a host and controls the host to set the first storage unit as a master storage device and set the second storage unit as a slave storage device. As a result, the host can recognize the first storage unit and the second storage unit as two independent storage devices for storing data. Thereby, the data storage process can be simplified. | 08-06-2009 |
20090198878 | INFORMATION PROCESSING SYSTEM AND INFORMATION PROCESSING METHOD - The information processing system is comprised of: a first nonvolatile storage device in which a plurality of first programs for initiating the information processing system, and duplications of the plural first programs have been stored in blocks different from each other; a second volatile storage device to which the plurality of first programs are transferred; a third nonvolatile storage device into which a second program for executing the plural first programs is stored; and a CPU (Central Processing Unit) for executing the plural first programs. While an instruction has been contained in the second program, the instruction instructs that the plurality of first programs are transferred from the first storage device to the second storage device, contents of the plurality of first programs transferred to the second storage devices are compared with each other; and if the contents of the plurality of first programs are not made coincident with each other, then a normal program is judged from the plurality of first programs based upon a majority decision. The CPU executes the first program judged as the normal program so as to initially initiate the information processing system. | 08-06-2009 |
20090198879 | MEMORY SYSTEM AND METHOD OF CONTROLLING THE SAME - A memory system has a memory unit composed of a plurality of memory cells, a memory controller for controlling to read out and write data from and to the memory unit, and a host processor connected to the memory controller for reading out and writing data from and to the memory unit through the memory controller. The memory controller has a refresh controller for rewriting the data stored in the memory unit. The host processor has a determination unit for determining whether or not a refresh operation can be executed to the memory unit and a permission signal transmission unit for transmitting a refresh permission signal when it is determined that the refresh operation can be executed to the memory unit by the determination unit. The refresh controller controls the start of the refresh operation to the memory unit based on the refresh permission signal transmitted from the host processor. | 08-06-2009 |
20090198880 | READ STROBE FEEDBACK IN A MEMORY SYSTEM - A controller circuit is coupled to a memory device over a data/IO bus and a control bus. The controller circuit generates a read enable signal that is transmitted to the memory device to instruct the memory device to drive data onto the data/IO bus. The read enable signal is fed back to the controller circuit that then uses the fed back signal to read the data from the data/IO bus. | 08-06-2009 |
20090204744 | METHODS AND SYSTEMS FOR RECONFIGURING DATA MEMORY OF EMBEDDED CONTROLLER MANAGED FLASH MEMORY DEVICES - Methods and systems for reconfiguring data memory of an embedded controller managed flash memory device are disclosed. According to one method, using a controller managed flash memory device reconfiguration module configured to execute on a general purpose computing platform separate from a computing platform in which an embedded controller managed flash memory device is located, reconfiguration data to be written to a data memory of the embedded controller managed flash memory device is received from a user and I/O commands for writing the reconfiguration data to an external device are generated. Flash device commands corresponding to the I/O commands are generated. The reconfiguration data is communicated to the data memory of the embedded controller managed flash memory device by sending the flash device commands and the reconfiguration data over a flash device interface of the embedded controller managed flash memory device. | 08-13-2009 |
20090204745 | Programming device for non-volatile memory and programming method thereof - The invention presents a programming method for a non-volatile memory with a bit signal to be programmed unidirectionally. The method includes the steps of a) providing first data each having a first number of sequential bits of first status in a data page in a non-volatile memory, b) decoding the first number of sequential bits of the first status in the first data into a second number of sequential bits of second status, and c) programming second data in a portion of the data page where the first status has been decoded to the second status. | 08-13-2009 |
20090204746 | FLASH MEMORY STORAGE DEVICE FOR ADJUSTING EFFICIENCY IN ACCESSING FLASH MEMORY - A flash memory storage device for boosting efficiency in accessing flash memory is disclosed. The flash memory storage device provides a Multi-level cell (MLC) flash memory for storing data, a single-level cell (SLC) flash memory for storing data, and a control unit for determining whether to store a file into the MLC NAND flash memory or a SLC NAND flash memory based on the file's data characteristics. | 08-13-2009 |
20090204747 | Non binary flash array architecture and method of operation - A Flash memory array comprises a plurality of Erase Sectors (Esecs) arranged in a plurality of Erase Sector Groups (ESGs), Physical Pages (slices), and Physical Sectors (PSecs), and there is a non-binary number of at least one of the Erase Sector Groups (ESGs), Physical Pages (slices), and Physical Sectors (PSecs). A user address is translated into a physical address using modular arithmetic to determine pointers (ysel, esg, psec) for specifying a given Erase Sector (ESec) within a given Erase Sector Group (ESG); a given Erase Sector Group (ESG) within a given Physical Sector (Psec); and a given Physical Sector (PSec) within the array. | 08-13-2009 |
20090204748 | MULTI-CHANNEL FLASH MEMORY SYSTEM AND ACCESS METHOD - Disclosed is a multi-channel flash memory system formed by flash memories having pages divided into sectors and accessed by corresponding channels. An interface device is configured to access the flash memories via the channels by a unit of at least one sector, wherein the interface device divides an address into a plurality of addresses of sector unit and controls the divided addresses so as to be jumped by a given size. | 08-13-2009 |
20090204749 | Redimdamt purge for flash storage device - A flash storage device includes flash storage units that are purged in response to a condition or command. A flash controller interface receives a command for purging the flash storage device and provides a purge command to flash controllers in the flash storage device. Alternatively, the flash storage device detects a condition in response to which the flash controller interface provides a purge command to the flash controllers. Each flash controller independently erases a flash storage unit in response to receiving the purge command, by writing a pattern of data to the flash storage unit, such that the flash storage units are purged substantially in parallel with each other. | 08-13-2009 |
20090204750 | DIRECT LOGICAL BLOCK ADDRESSING FLASH MEMORY MASS STORAGE ARCHITECTURE - A nonvolatile semiconductor mass storage system and architecture can be substituted for a rotating hard disk. The system and architecture avoid an erase cycle each time information stored in the mass storage is changed. Erase cycles are avoided by programming an altered data file into an empty mass storage block rather than over itself as a hard disk would. Periodically, the mass storage will need to be cleaned up. These advantages are achieved through the use of several flags, and a map to correlate a logical block address of a block to a physical address of that block. In particular, flags are provided for defective blocks, used blocks, and old versions of a block. An array of volatile memory is addressable according to the logical address and stores the physical address. | 08-13-2009 |
20090210611 | STORAGE SYSTEM AND DATA WRITE METHOD - The size of a memory management unit in a low-performance non-volatile memory device is maintained, and the size of write data is compared with the size of the memory management unit. If the size of the write data is smaller than that of the memory management unit, the write data is cached by the high-performance non-volatile memory device; or if the size of the write data is not smaller, the write data is written to the low-performance device. Subsequently, a plurality of address values for the write data cached by the high-performance device are referred to; an address segment that is equal to the size of the memory management unit and in which the cached address values are consecutive; and data contained in that address segment is copied from the high-performance device to the low-performance device. | 08-20-2009 |
20090210612 | MEMORY CONTROLLER, NONVOLATILE MEMORY DEVICE, AND NONVOLATILE MEMORY SYSTEM - In rewriting processing of logical sectors, data of the transferred logical sectors are temporarily stored in a memory buffer. When the buffer memory has been full filled with data, the data is written into a flash memory. In rewriting processing for the flash memory including a writing unit (page) having a capacity larger than a minimum writing unit (sector) from outside, the number of executions of the evacuation processing can be reduced and the fast data rewriting can be performed. Thus, it is possible to rationalize the evacuation processing for old data caused in the rewriting in units of sectors and to improve the data rewriting speed. | 08-20-2009 |
20090210613 | Method for Programming a Controller in a Motor Vehicle - A method and apparatus are provided for programming of a control device of a motor vehicle, in which the control device includes at least one program-controlled processor and at least two individually addressable memory areas, in particular at least two physically separated memory components. In order to accelerate the inputting of memory contents the invention suggests that the processor carries out or brings about the following two steps at least intermittently largely simultaneously. On the one hand, checking whether programs, program parts and/or data already written into the first memory area correspond to the data to be written into the first memory area, and on the other hand, writing a program, a program part and/or data into the second memory area. | 08-20-2009 |
20090210614 | Non-Volatile Memories With Versions of File Data Identified By Identical File ID and File Offset Stored in Identical Location Within a Memory Page - In the file storage system, each portion belonging to a data file is identified by its file ID and an offset along the data file, where the offset is a constant for the file and every file data portion is always kept at the same position within a memory page to be read or programmed in parallel. In this way, every time a page containing a file portion is read and copy to another page, the data in it is always page-aligned, and each bit within the file portion can always be manipulated by the same sense amplifier and same set data latches within the same memory column. In a preferred implementation, the page alignment is such that (offset within a page)=(data offset within a file) MOD (page size). Any gaps that may exist in page can be padded with any existing page-aligned valid data. | 08-20-2009 |
20090216935 | Memory device for a user profile - A memory device for a user profile of a plurality of electronic devices or functional units in a motor vehicle is used for providing data corresponding to the user profile in the vehicle without a user having to make corresponding settings. As a result of being stored in the memory device, the user profile can be used in different vehicles. | 08-27-2009 |
20090216936 | DATA READING METHOD FOR FLASH MEMORY AND CONTROLLER AND STORAGE SYSTEM USING THE SAME - A data reading method suitable for a flash memory storage system having a flash memory is provided, wherein the flash memory is substantially divided into a plurality of blocks and these blocks are grouped into at least a data area and a spare area. The data reading method includes: respectively determining whether the blocks in the data area are frequently read blocks; allocating a buffer storage area corresponding to the frequently read block and copying data stored in the frequently read block to the buffer storage area; and reading the data from the buffer storage area corresponding to the frequently read block when the data stored in the frequently read block is to be read. As described above, data loss caused by read disturb can be effectively prevented. | 08-27-2009 |
20090216937 | MEMORY CONTROLLER, MEMORY SYSTEM, AND ACCESS CONTROL METHOD OF FLASH MEMORY - A memory controller adds dummy data to write data by referring to instruction information about a descriptor transfer of the write data if a size of the write data to be written according to a data-write request information does not match a page size unit, thereby adjusting the size of the write data to the page size unit and then outputs the write data. | 08-27-2009 |
20090216938 | Management Of Non-Volatile Memory Systems Having Large Erase Blocks - A non-volatile memory system of a type having blocks of memory cells erased together and which are programmable from an erased state in units of a large number of pages per block. If the data of only a few pages of a block are to be updated, the updated pages are written into another block provided for this purpose. The valid original and updated data are then combined at a later time, when doing so does not impact on the performance of the memory. If the data of a large number of pages of a block are to be updated, however, the updated pages are written into an unused erased block and the unchanged pages are also written to the same unused block. By handling the updating of a few pages differently, memory performance is improved when small updates are being made. | 08-27-2009 |
20090222612 | Programmable Food Service Systems - A data key, for use with a programmable food service device, comprises: an insertion portion, for insertion into a key aperture in the programmable food service device; a data memory for storing data relating to the operation of the programmable food service device; and a data connection portion for connecting directly with a data port on a computer, to allow the computer to access the data memory. | 09-03-2009 |
20090222613 | INFORMATION PROCESSING APPARATUS AND NONVOLATILE SEMICONDUCTOR MEMORY DRIVE - According to one embodiment, an information processing apparatus includes an information processing apparatus main body, and a nonvolatile semiconductor memory drive which is accommodated in the information processing apparatus main body. The nonvolatile semiconductor memory drive includes a nonvolatile semiconductor memory, an address management table which is indicative of a correspondency between logical block addresses and physical addresses of the nonvolatile semiconductor memory, and a control module. The control module refers to the address management table in response to reception of a read request from the information processing apparatus main body, and outputs data of a predetermined value to the information processing apparatus main body in a case where the physical address corresponding to the logical block address, which is included in the read request, is not stored in the address management table. | 09-03-2009 |
20090222614 | INFORMATION PROCESSING APPARATUS AND NONVOLATILE SEMICONDUCTOR MEMORY DRIVE - According to one embodiment, an information processing apparatus includes an information processing apparatus main body, and a nonvolatile semiconductor memory drive which is accommodated in the information processing apparatus main body. The nonvolatile semiconductor memory drive includes a nonvolatile semiconductor memory, and a control module configured to control, in accordance with a command from the information processing apparatus main body, a write operation, a read operation and an erase operation of the nonvolatile semiconductor memory, to generate, in every predetermined time period, statistical information relating to the write operation, the read operation and the erase operation of the nonvolatile semiconductor memory, and to store the statistical information, which corresponds to each of a plurality of time periods each having a time length corresponding to the predetermined time period, in a memory area of the nonvolatile semiconductor memory. | 09-03-2009 |
20090222615 | Information Processing Apparatus and Nonvolatile Semiconductor Memory Drive - According to one embodiment, a nonvolatile semiconductor memory includes a first memory area which is formed of a fixed area to which a predetermined physical address range is allocated, and which stores management information including an address management table indicative of a correspondency between logical block address and physical addresses of the nonvolatile semiconductor memory, and a second memory area to which a first logical address range is allocated and which stores log data indicative of an operation condition of the nonvolatile semiconductor memory drive. A control module accesses the first memory area by using the physical address belonging to the predetermined physical address range in a case of reading or writing the management information, and accesses the second memory area by using the physical address corresponding to the logical block address belonging to the first logical address range, which is obtained by referring to the address management table. | 09-03-2009 |
20090222616 | MEMORY SYSTEM - A controller includes an identification information management table that manages identification information indicating, for each of addresses in second-management unit, whether one or more data in first management unit belonging to the addresses is stored in the second or the third storing area. When the controller executes a process of flushing data from the first storing area to the second storing area or the third storing area, the controller updates the identification information in the identification information management table. The controller executes a process of reading data from the second storing area or the third storing area by referring to the identification information. As a result, the speed of searches conducted in the management table is increased. | 09-03-2009 |
20090222617 | MEMORY SYSTEM - A memory system includes a volatile first storing unit, a nonvolatile second storing unit in which data is managed in a predetermined unit, and a controller that writes data requested by a host apparatus in the second storing unit via the first storing unit and reads out data requested by the host apparatus from the second storing unit to the first storing unit and transfers the data to the host apparatus. The controller includes a management table for managing the number of failure areas in a predetermined unit that occur in the second storing unit and switches, according to the number of failure areas, an operation mode in writing data in the second storing unit from the host apparatus. | 09-03-2009 |
20090222618 | MEMORY SYSTEM AND BLOCK MERGE METHOD - In one embodiment, the invention provides a memory system including a flash memory device including a plurality of memory blocks implementing a plurality of data blocks, a plurality of log blocks, and a plurality of free blocks. The memory system further includes a flash translation layer maintaining the number of the free blocks to be at least equal to a reference number by converting selected memory blocks among the data and log blocks into free blocks via at least one merge operation during a background period. Additionally, the flash translation layer converts selected ones of the free blocks into data and log blocks, respectively. | 09-03-2009 |
20090222619 | Electronic Flash Memory External Storage Method and Device - An electronic flash memory external storage method and device for data processing system includes firmware which directly controls the access of electronic storage media and implements standard interface functions, adopts particular reading and writing formats of the external storage media, receives power via USB, externally stores data by flash memory and access control circuit with the cooperation of the firmware and the driver with the operating system, and has write-protection so that the data can be safely transferred. The method according to present invention is highly efficient and all parts involved are assembled as a monolithic piece so that it has large-capacity with small size and high speed. The device operates in static state and is driven by software. It is plug-and-play and adapted to data processing system. | 09-03-2009 |
20090228633 | Data processor - A data processor ( | 09-10-2009 |
20090240868 | MANAGEMENT METHOD, MANAGEMENT APPARATUS, AND CONTROLLER FOR MEMORY DATA ACCESS - A management method, a management apparatus, and a controller for memory data access are provided. The management apparatus is disposed between a host and a device for managing the data transmitted between the host and the device, wherein the management apparatus includes a control unit and a storage unit. When the control unit receives a data writing command from the host, it searches for a set mapped to the data in the storage unit and updates the data in the set. Then, the control unit collects the other parts of the data in the storage unit and the device, integrates all parts of the data, and writes the integrated data into the device. Accordingly, the efficiency in data transmission can be improved, and the number of data writing operations can be reduced so that the lifespan of the device can be prolonged. | 09-24-2009 |
20090240869 | Sharing Data Fabric for Coherent-Distributed Caching of Multi-Node Shared-Distributed Flash Memory - A Sharing Data Fabric (SDF) causes flash memory attached to multiple compute nodes to appear to be a single large memory space that is global yet shared by many applications running on the many compute nodes. Flash objects stored in flash memory of a home node are copied to an object cache in DRAM at an action node by SDF threads executing on the nodes. The home node has a flash object map locating flash objects in the home node's flash memory, and a global cache directory that locates copies of the object in other sharing nodes. Application programs use an applications-programming interface (API) into the SDF to transparently get and put objects without regard to the object's location on any of the many compute nodes. SDF threads and tables control coherency of objects in flash and DRAM. | 09-24-2009 |
20090240870 | STORAGE APPARATUS WITH A PLURALITY OF NONVOLATILE MEMORY DEVICES - According to one embodiment, a counter counts bits having a predetermined logical value contained in accessed data to be written or read in an access process of accessing any of the physical blocks provided in a selected one of the nonvolatile memory devices. A timer measures an access busy period in the access process. A control module updates an access busy period data item stored in a busy period storage module and concerning the selected one, in accordance with a count value of the counter, whereby the access busy period data item represents the access busy period measured. | 09-24-2009 |
20090240871 | MEMORY SYSTEM - A system includes: a first input buffer that functions as an input buffer for a third storing area; and a second input buffer that functions as an input buffer for the third storing area and that separately stores data with a high update frequency for the third storing area. In the system, a plurality of data written in a first storing area or a second storing area are flushed to the first input buffer in units of logical blocks. Also, a plurality of data written in the first input buffer are relocated to the third storing area in units of logical blocks. | 09-24-2009 |
20090240872 | MEMORY DEVICE WITH MULTIPLE-ACCURACY READ COMMANDS - A method for data storage includes defining at least first and second read commands for reading storage values from analog memory cells. The first read command reads the storage values at a first accuracy, and the second read command reads the storage values at a second accuracy, which is finer than the first accuracy. A condition is evaluated with respect to a read operation that is to be performed over a given group of the memory cells. One of the first and second read commands is selected responsively to the evaluated condition. The storage values are read from the given group of the memory cells using the selected read command. | 09-24-2009 |
20090240873 | Multi-Level Striping and Truncation Channel-Equalization for Flash-Memory System - Truncation reduces the available striped data capacity of all flash channels to the capacity of the smallest flash channel. A solid-state disk (SSD) has a smart storage switch salvages flash storage removed from the striped data capacity by truncation. Extra storage beyond the striped data capacity is accessed as scattered data that is not striped. The size of the striped data capacity is reduced over time as more bad blocks appear. A first-level striping map stores striped and scattered capacities of all flash channels and maps scattered and striped data. Each flash channel has a Non-Volatile Memory Device (NVMD) with a lower-level controller that converts logical block addresses (LBA) to physical block addresses (PBA) that access flash memory in the NVMD. Wear-leveling and bad block remapping are preformed by each NVMD. Source and shadow flash blocks are recycled by the NVMD. Two levels of smart storage switches enable three-level controllers. | 09-24-2009 |
20090248956 | Apparatus for Storing Management Information in a Computer System - An apparatus for providing management storage via a USB port of a computer system is disclosed. The apparatus includes a flash memory, a first and second switches, a first and second inverters, a designated port, and a controller. Coupled to the flash memory, the first and second switches are controlled by a main power of a computer system in a complementary manner. The first and second inverters, which are powered by a standby power of the computer system, are coupled to a respective control input of the first and second switches. The designated port, which is coupled to the flash memory via the first switch, allows data to be read from and written to the flash memory without booting up the computer system. On the other hand, the controller, which is coupled to the flash memory via the second switch, allows data to be read from and written to the flash memory by the computer system only after the computer system has been booted up. | 10-01-2009 |
20090248957 | MEMORY RESOURCE MANAGEMENT FOR A FLASH AWARE KERNEL - A memory system is provided. The system includes an operating system kernel that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the kernel to regulate read and write access to the one or more FLASH devices. | 10-01-2009 |
20090248958 | FLASH MEMORY USABILITY ENHANCEMENTS IN MAIN MEMORY APPLICATION - A memory system is provided. The system includes an operating system kernel that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the kernel to regulate read and write access to the one or more FLASH devices. | 10-01-2009 |
20090248959 | FLASH MEMORY AND OPERATING SYSTEM KERNEL - A memory system is provided. The system includes an operating system kernel that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the kernel to regulate read and write access to the one or more FLASH devices. | 10-01-2009 |
20090248960 | METHODS AND SYSTEMS FOR CREATING AND USING VIRTUAL FLASH CARDS - Creating and using virtual flash cards is disclosed. A disclosed method includes receiving an input of sets of flash data into a portable handheld device, associating related sets of the flash data based on manual inputs that define the relationship between the related sets of flash data, presenting one of the related sets of flash data via the handheld device and prompting a selection of a set of flash data that is associated with the presented set of flash data. Feedback is provided that indicates whether or not a selected set of flash data is correct. | 10-01-2009 |
20090248961 | MEMORY MANAGEMENT METHOD AND CONTROLLER FOR NON-VOLATILE MEMORY STORAGE DEVICE - A memory management method and a controller for a non-volatile memory storage device are provided. The memor management method and the controller are adapted for establishing a logical-to-physical mapping table of each block in a memory buffer of the controller by merely reading the data stored in a system management area within a start page of each block, so as to promote the management efficiency of the non-volatile memory storage device. In addition, the method and the controller of the present invention integrate all of or a part of the system management areas within the start page for efficiently managing and using the memory capacity of all the system management areas within the start page. | 10-01-2009 |
20090248962 | Memory system and wear leveling method thereof - A memory system includes a variable resistance memory configured to input and output data by a first unit and a translation layer for managing the degree of wear of the variable resistance memory by a second unit, different from the first unit. | 10-01-2009 |
20090248963 | MEMORY CONTROLLER AND MEMORY SYSTEM INCLUDING THE SAME - A memory system includes a memory system includes a nonvolatile memory including a memory space which is formatted from outside by an additional-write type file system, and a memory controller controlling the nonvolatile memory, the memory controller transmitting a write protect error when the memory controller is instructed to write data in an address which is equal to or smaller than an address of previously written data in an address area of the memory space. | 10-01-2009 |
20090248964 | MEMORY SYSTEM AND METHOD FOR CONTROLLING A NONVOLATILE SEMICONDUCTOR MEMORY - A memory system includes a nonvolatile semiconductor memory having blocks, the block being data erasing unit; and a controller configured to execute; an update processing for; writing superseding data in a block, the superseding data being treated as valid data; and invalidating superseded data having the same logical address as the superseding data, the superseded data being treated as invalid data; and a compaction processing for; retrieving blocks having invalid data using a management tablet the management table managing blocks in a linked list format for each number of valid data included in the block; selecting a compaction source block having at least one valid data from the retrieved blocks; copying a plurality of valid data included in the compaction source blocks into a compaction target block; invalidating the plurality of valid data in the compaction source blocks; and releasing the compaction source blocks in which all data are invalidated. | 10-01-2009 |
20090248965 | HYBRID FLASH MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME - A hybrid flash memory device and a control method of the hybrid flash memory device are provided. The hybrid flash memory device includes a micro controller connected to a host bus for receiving data to be written in the hybrid flash memory device from a host via the host bus; and a memory module coupled to the micro controller. The flash module includes a first type of flash memory and a second type of flash memory. The data are determined to be written in a first log block of the first type of flash memory when the data size is not greater than a predetermined data size. On the contrary, the data are determined to be written in a second log block of the second type of flash memory when the data size is greater than the predetermined data size. | 10-01-2009 |
20090248966 | FLASH DRIVE WITH USER UPGRADEABLE CAPACITY VIA REMOVABLE FLASH - An exemplary data storage device includes a fixed storage medium, an expansion socket configured to selectively receive at least one removable memory card, and a controller configured to interface the fixed storage medium and the at least one removable memory card with a host device. An exemplary method includes verifying credentials with verification data stored on the fixed storage medium of the data storage unit, and protecting data on the removable storage medium removably attached to the data storage unit. | 10-01-2009 |
20090248967 | PORTABLE ALARM CONFIGURATION/UPDATE TOOL - A stand-alone portable alarm update tool includes a memory interface for receiving a computer readable memory; a serial port for interconnection to a security alarm panel, by way of a complementary port; a processor; and processor readable memory in communication with the processor, storing software adapting the processor to upload and download configuration files from a removable memory received by the memory port, to the alarm panel, by way of the serial port. Conveniently, the tool may be packaged in a hand-held casing, and which may also house a battery. In this way, the tool may be readily transported by an installer, without being unnecessary heavy or bulky. | 10-01-2009 |
20090254696 | SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF OPERATION FOR SEMICONDUCTOR INTEGRATED CIRCUIT - The semiconductor IC has a nonvolatile memory including twin cells, a selector, and a sense circuit. When complementary data are written into a pair of nonvolatile memory cells of each twin cell, the pair of nonvolatile memory cells is set to be in a written state where one cell of the pair is set to one of low and high threshold voltages, and the other is set to the other threshold voltage. When non-complementary data are written into a pair of nonvolatile memory cells, for example, the memory cells both take the low threshold voltage and are made blank. The selector includes switching elements. During the blank-check action, switching elements of the selector are controlled to ON state. Then, the first total current of the twin cells forced to flow into the first input terminal of the sense circuit commonly is compared with the reference signal on the second input terminal, whereby whether the twin cells have been written or blank can be detected at a high speed. As to a semiconductor nonvolatile memory such that complementary data are written into memory cells in memory cell pairs, the blank-check time can be shortened. | 10-08-2009 |
20090259797 | METHOD, APPARATUS AND COMPUTER READABLE MEDIUM FOR STORING DATA ON A FLASH DEVICE USING MULTIPLE WRITING MODES - Methods, apparatus and computer readable medium for writing data into a flash memory device are disclosed. In some embodiments, the data is written in a writing mode selected in accordance with an extent to which the flash memory storage device or a flash die thereof is full of previously-stored data. The presently disclosed techniques may be implemented on the “device-side” (for example, by a device controller of the flash device) and/or on the “host-side.” In some embodiments, the selected writing mode is a bits-per-cell density mode. In some embodiments, the selected writing mode is a “slower” or “faster” writing mode. The presently disclosed techniques relate to SBC as well as MBC devices. | 10-15-2009 |
20090259798 | Method And System For Accessing A Storage System With Multiple File Systems - In order to write data to a storage system accessible with a first and second file system, a manager receives a data write request associated with a file. The manager determines if a function supported by the second file system is needed to complete the write request. If so, the file is opened and extended with the first file system. The file is then opened and written to by the second file system. The file is truncated by the first file system, and closed by both file systems. If the second file system function is not needed, the file is opened, written, and closed by the first file system. In order to read data from a storage system using a function supported by the second file system, the second file system's cached storage system index is updated, then the file is opened, read, and closed by the second file system. | 10-15-2009 |
20090259799 | METHOD AND APPARATUS FOR A VOLUME MANAGEMENT SYSTEM IN A NON-VOLATILE MEMORY DEVICE - Embodiments for partitioning a non-volatile memory device is described. In one embodiment a memory system includes a first addressable range of memory blocks for storing different types of data. The memory system is partitioned to include a second addressable range of memory blocks capable of storing data indicating attributes of the first addressable range of memory blocks. The second addressable range of memory blocks may also be periodically updated such that the capacities of the first addressable range of memory blocks may be dynamically adjusted depending on application needs and changes to the non-volatile memory device over time. In some embodiments, one partition of a memory device may be configured for high reliability data storage while a second partition is configured for normal reliability storage. | 10-15-2009 |
20090259800 | FLASH MANAGEMENT USING SEQUENTIAL TECHNIQUES - Disclosed are techniques for flash memory management, including receiving data from a host, writing the data to a flash memory device in the order it was received from the host, and providing at least one data structure configured to locate the data written to the flash memory device. | 10-15-2009 |
20090259801 | CIRCULAR WEAR LEVELING - A method for flash memory management comprises providing a head pointer configured to define a first location in a flash memory, and a tail pointer configured to define a second location in a flash memory. The head pointer and tail pointer define a payload data area. Payload data is received from a host, and written to the flash memory in the order it was received. The head pointer and tail pointer are updated such that the payload data area moves in a circular manner within the flash memory. | 10-15-2009 |
20090259802 | SMART DEVICE RECORDATION - Valuable information can be retained upon a storage device, such as a flash memory unit. Due to the portable nature of the memory, there can be increased likelihood of theft, less back up of important files not a reliable medium, legal physical transfer of the device between parties, and the like. When an operation is requested to take place related to the device, a check can take place if the operation should be allowed based upon device metadata, such as physical location of the device, device history, and so forth. A determination can be made on if the operation should automatically occur based upon a result of the check. If it is determination that the operation should not automatically occur, then the operation can be denied or a request can be made to an owner of the device on if the operation should be allowed to occur. | 10-15-2009 |
20090259803 | SYSTEMS, METHODS AND COMPUTER PROGRAM PRODUCTS FOR ENCODING DATA TO BE WRITTEN TO A NONVOLATILE MEMORY BASED ON WEAR-LEVELING INFORMATION - A nonvolatile memory system is operated by providing data to be written to a nonvolatile memory, logically combining the data to be written to the nonvolatile memory with a random pattern to generate encoded data; and programming the encoded data in the nonvolatile memory. | 10-15-2009 |
20090259804 | CALIBRATED TRANSFER RATE - Methods, systems, and devices are described for the implementation of a novel architecture to support a calibrated rate for the transfer of circuit configuration data. Sets of configuration data from a memory may be transferred to volatile memory to support reconfigurable circuit elements, for example, for use in a clock generator. Upon system power-up, there may be a default speed for the transfer of the configuration data. Techniques are described to first transfer calibration data upon power-up; the transferred calibration data may then be used to set an accelerated speed for a remaining portion of the transfer. | 10-15-2009 |
20090259805 | FLASH MANAGEMENT USING LOGICAL PAGE SIZE - Disclosed are techniques for flash memory management, including tracking payload data via one or more data structures configured to define the size of logical pages in a flash memory. In various embodiments, the logical page size may be larger than, equal to, or smaller than a physical page size of a flash memory chip. | 10-15-2009 |
20090259806 | FLASH MANAGEMENT USING BAD PAGE TRACKING AND HIGH DEFECT FLASH MEMORY - Disclosed are techniques for flash memory management, including utilizing defect information corresponding to a granularity smaller than a physical erase block size of a flash memory chip. | 10-15-2009 |
20090259807 | FLASH MEMORY ARCHITECTURE WITH SEPARATE STORAGE OF OVERHEAD AND USER DATA - A memory device has a plurality of dedicated data blocks for storing only user data and a plurality of dedicated overhead blocks for storing only overhead data. Current overhead segments of a dedicated overhead block can be consolidated and moved to a new dedicated overhead block. | 10-15-2009 |
20090259808 | Methods of Sanitizing a Flash-Based Data Storage Device - A data storage device includes one or more non-volatile, blockwise erasable data storage media and a mechanism for sanitizing the media in response to a single external stimulus or in response to a predetermined physical or logical condition. Optionally, only part of the media is sanitized, at a granularity finer than the blocks of the medium. Setting a flag in an auxiliary nonvolatile memory enables an interrupted sanitize to be detected and restarted. Optionally, a “death certificate” verifying the sanitizing is issued. Preferably, the media are configured in a manner that allows atomic operations of the sanitizing to be effected in parallel. | 10-15-2009 |
20090265505 | DATA WRITING METHOD, AND FLASH STORAGE SYSTEM AND CONTROLLER USING THE SAME - A data writing method, and a flash storage system and a controller using the same are provided. The method includes grouping the physical blocks of a flash memory into the physical blocks of a data area, a spare area and a special area. The method also includes writing the update data into the corresponding physical block of the special area when the update data is the single accessing unit. The method may include moving a part of valid data in a physical block mapping a logical block where the update data is belonged into a physical block of the spare area during each data writing command. Accordingly, it is possible to reduce the response time for each data writing command, thereby preventing a time-out problem caused by a flash memory having a large erasing unit configured at the flash storage system. | 10-22-2009 |
20090265506 | STORAGE DEVICE - A computing system and a storage device are provided. A computing system includes a first storage media, a second storage media having an input/output speed slower than that of the first storage media, and a hybrid file system management unit to manage a first physical file system and second physical file system, and provide a virtual file system manager with a virtual file system converted from the first physical file system and second physical file system. The first physical file system controls the first storage media and the second physical file system controls the second storage media. | 10-22-2009 |
20090265507 | SYSTEM TO REDUCE DRIVE OVERHEAD USING A MIRRORED CACHE VOLUME IN A STORAGE ARRAY - A system comprising a host, a solid state device, and an abstract layer. The host may be configured to generate a plurality of input/output (IO) requests. The solid state device may comprise a write cache region and a read cache region. The read cache region may be a mirror of the write cache region. The abstract layer may be configured to (i) receive the plurality of IO requests, (ii) process the IO requests, and (iii) map the plurality of IO requests to the write cache region and the read cache region. | 10-22-2009 |
20090265508 | Scheduling of Housekeeping Operations in Flash Memory Systems - A re-programmable non-volatile memory system, such as a flash EEPROM system, having its memory cells grouped into blocks of cells that are simultaneously erasable is operated to perform memory system housekeeping operations in the foreground during execution of a host command, wherein the housekeeping operations are unrelated to execution of the host command. Both one or more such housekeeping operations and execution of the host command are performed within a time budget established for executing that particular command. One such command is to write data being received to the memory. One such housekeeping operation is to level out the wear of the individual blocks that accumulates through repetitive erasing and re-programming. | 10-22-2009 |
20090271559 | Method for Storing Individual Data Items of a Low-Voltage Switch - A method is disclosed for storing individual data items of a low-voltage switch provided with a microcontroller triggering unit. According to an embodiment, the ROM cells of a dead microcontroller ROM which are not occupied by a program code memory cells are occupied by the individual data items of the low-voltage switch. | 10-29-2009 |
20090271560 | Dynamic Fix-Up of Global Variables During System BIOS Execution - A method is described for preserving the flexibility associated with relative memory addressing in programs designed to be stored in read-only memory. | 10-29-2009 |
20090271561 | MEDIUM FOR INTEGRATING STORING CAPACITIES OF MULTIPLE STORAGE DEVICES - A medium for integrating storing capacities of multiple storage devices has multiple memory card connectors, a memory card interface management module, a control module and a communication interface. Each memory card connector is used to connect to a memory card. The memory card interface management module is connected to the memory card connectors. The control module is connected to the memory card interface management module and stores a mount and unmount management process. The control module executes the mount and unmount management process to integrate storing capacities of all connected memory cards into a single storing capacity and unintegrate the storing capacity of the impendingly removed memory cards from the storing capacity of all connected memory cards. The communication interface is used to connect to a computer. Therefore, it is convenient for users to change the storing capacity of the medium based on different requirements. | 10-29-2009 |
20090271562 | Method and system for storage address re-mapping for a multi-bank memory device - A method and system for storage address re-mapping in a multi-bank memory is disclosed. The method includes allocating logical addresses in blocks of clusters and re-mapping logical addresses into storage address space, where short runs of host data dispersed in logical address space are mapped in a contiguous manner into megablocks in storage address space. Independently in each bank, valid data is flushed within each respective bank from blocks having both valid and obsolete data to make new blocks available for receiving data in each bank of the multi-bank memory when an available number of new blocks falls below a desired threshold within a particular bank. | 10-29-2009 |
20090271563 | FLASH MEMORY TRANSACTIONING - Providing for improved transactioning for Flash memory is described herein. By way of example, transactioning operations associated with abstract data structures can be bundled into a common layer of a Flash management protocol stack, to reduce transaction redundancy at abstracted layers. In some aspects, the common layer can be a block level layer providing relatively direct access to low level Flash. Thus, a file system or database application, operating at a higher, abstracted layer of the Flash management protocol stack, can offload transactioning operations to a block level process that has access to underlying Flash memory. As a result, increased efficiency, throughput, and added flexibility can be achieved for storage system transactioning. | 10-29-2009 |
20090271564 | STORAGE SYSTEM - A storage system has a storage controller and a flash memory module that is coupled to the storage controller. The storage controller manages the status of a storage area in a flash memory chip of the flash memory module. When a portion of the storage area in the flash memory chip becomes unwritable, the storage controller carries out control so as to use a free storage area as an alternate area for the unwritable storage area, and to store data that has been stored in the unwritable storage area, in the alternate area. | 10-29-2009 |
20090271565 | METHOD OF PROCESSING HARD DISK DRIVE - A method of processing a hard disk drive. The method can include downloading at least two process codes and a main code to a first storage area of the hard disk drive, sequentially performing processes based on the at least two process codes, and installing the main code in a second storage area. | 10-29-2009 |
20090271566 | METHOD FOR CONFIGURING OR RE-CONFIGURING PROGRAMMABLE DEVICE AND APPARATUS ASSOCIATED THEREWITH - A method of configuring a programmable device may include connecting an electronic storage medium to a configuration system with user-friendly input/output capabilities to establish configuration information for the programmable device, which may have limited input/output capabilities. The configuration information may be applied to the programmable device when the electronic storage medium is connected to the programmable device. Additional programmable devices may be configured when connected to the electronic storage medium. Further embodiments of the method and apparatus to provide the programmable device configuration service are also provided. | 10-29-2009 |
20090271567 | METHODS FOR MANAGING BLOCKS IN FLASH MEMORIES - A method for managing blocks in a flash memory is provided, which includes dynamic and static block managing methods. In the dynamic block managing method, a blank block is selected as a swap block for write operation. During each write operation, new data and/or original data in an object block to be operated are written into the swap block, and the object block is erased. Then, a logical address of the object block is changed to be a logical address of the swap block, so that the object block served as the swap block for a next write operation. In the static block managing method, a variable seed parameter is set. Different values of the seed parameter are each associated with a logical address of a respective flash memory block. When the value of the seed parameter varies, data in the flash memory block and the swap block associated to the value of the seed parameter are exchanged, so that the flash memory block associated to the value of the seed parameter becomes the swap block for the next write operation. | 10-29-2009 |
20090271568 | FLASH MEMORY SYSTEM AND DATA WRITING METHOD THEREOF - Provided are a flash memory system and a data reading method thereof, the method including serially reading groups of data and parity codes corresponding to each of the respective groups from a page buffer; calculating the parity for each serially read group; checking for errors in each serially read group by comparing each calculated parity with a corresponding serially read parity code, respectively; and providing an output signal indicative of any comparative parity errors detected, wherein the reading of each group of data is followed by the reading of the parity code for the group, and the checking for errors in each group of data is done during the serial reading operation. | 10-29-2009 |
20090276561 | SPI NAND PROTECTED MODE ENTRY METHODOLOGY - One or more techniques are provided for restricting access to protected modes of operation in a memory device. In one embodiment, detection circuitry is provided and configured to receive and evaluate a protected mode entry sequence for accessing a protected mode of operation. The detection circuitry may be further configured to temporarily enable an output pin on a serial interface between the memory device and a master device to receive inputs, such that a entry sequence may be entered on both the input and output pins. In another embodiment, the detection circuitry may be enabled only if a security code is first provided, thus requiring both the correct security code and entry sequence before protected mode access is allowed. The memory device may also include a parallel NAND memory array, and detection logic may be further configured to enable a serial-to-parallel NAND translator once protected mode access is allowed. | 11-05-2009 |
20090276562 | Flash cache flushing method and system - A flash memory system that uses repeated writing of the data to achieve stable storage, is adapted for efficient cache flushing operations by utilizing a part of the non-volatile flash memory array as a designated buffer for the data, in which data integrity is retained until all repeat writing thereof is complete. Repeated writing is carried out from the designated buffer directly to the final storage locations in the flash memory array, for example using simple internal copy back operations. | 11-05-2009 |
20090282184 | COMPENSATING NON-VOLATILE STORAGE USING DIFFERENT PASS VOLTAGES DURING PROGRAM-VERIFY AND READ - Optimized verify and read pass voltages are obtained to improve read accuracy in a non-volatile storage device. The optimized voltages account for changes in unselected storage element resistance when the storage elements become programmed. This change in resistance is referred to as a front pattern effect. In one approach, the verify pass voltage is higher than the read pass voltage, and a common verify voltage is applied on the source and drain sides of a selected word line. In other approaches, different verify pass voltages are applied on the source and drain sides of the selected word line. An optimization process can include determining a metric for different sets of verify and read pass voltages. The metric can indicate threshold voltage width, read errors or a decoding time or number of iterations of an ECC decoding engine. | 11-12-2009 |
20090282185 | FLASH MEMORY DEVICE AND A METHOD FOR USING THE SAME - A flash memory device is presented. The device includes a flash memory, which has a temporary storage portion, a main storage portion and a controller. The temporary storage portion is provided for buffering data and addresses. The buffered addresses are indicative of the destination of the buffered data in the main storage portion. The controller is configured for selectively accessing the main storage portion or the temporary storage portion or a combination thereof for receiving and/or outputting the data from the memory. The controller is further configured for enabling communication of data between the two portions. Because non-volatile flash memory is used for the temporary storage, no other memory components are needed and, in case of an unexpected power failure, the data in the temporary area is not lost. | 11-12-2009 |
20090282186 | DYNAMIC AND ADAPTIVE OPTIMIZATION OF READ COMPARE LEVELS BASED ON MEMORY CELL THRESHOLD VOLTAGE DISTRIBUTION - A process is performed periodically or in response to an error in order to dynamically and adaptively optimize read compare levels based on memory cell threshold voltage distribution. One embodiment of the process includes determining threshold voltage distribution data for a population of non-volatile storage elements, smoothing the threshold voltage distribution data using a weighting function to create an interim set of data, determining a derivative of the interim set of data, and identifying and storing negative to positive zero crossings of the derivative as read compare points. | 11-12-2009 |
20090282187 | FLASH MEMORY DEVICE CAPABLE OF PREVENTING READ DISTURBANCE - A storage has a first cache area temporarily storing one page data read from a flash memory, and a second cache area to which data of the first cache area is transferred. A controller stores data of the first cache area in the second cache area, and reads and outputs the data stored in the second cache area when data having the same address as data read from the first cache area is read. | 11-12-2009 |
20090282188 | MEMORY DEVICE AND CONTROL METHOD - A memory device includes a first controller and a second controller. The first controller receives a first command from a host and stores the first command in a first command queue, and transmits the first command to the second controller relating to the first command stored in the first command queue. The second controller transmits the first command stored in the second command queue to a flash memory. | 11-12-2009 |
20090287873 | SEMICONDUCTOR INTEGRATED CIRCUIT, SYSTEM DEVICE INCLUDING SEMICONDUCTOR INTEGRATED CIRCUIT, AND SEMICONDUCTOR INTEGRATED CIRCUIT CONTROL METHOD - A disclosed semiconductor integrated circuit interfaces an external circuit and a host for controlling the external circuit and obtains data used to interface the external circuit and the host from a rewritable external memory. The disclosed semiconductor integrated circuit includes external terminals to which an external signal line group is connected, the external signal line group including signal lines connecting the external circuit and the external memory in parallel; an external terminal interface circuit configured to interface the semiconductor integrated circuit and the external circuit or the external memory connected via the external signal line group; and a control circuit configured to activate or deactivate the external circuit and the external memory. The control circuit is configured to activate either the external circuit or the external memory that is to be accessed via the external terminal interface circuit. | 11-19-2009 |
20090287874 | Flash Recovery Employing Transaction Log - A transaction log for flash recovery includes a chained sequence of blocks specifying the operations that have been performed, such as a write to a sector or an erase to a block. Checkpoints are performed writing the entire flash state to flash. Once a checkpoint is performed, all of the log entries prior to the checkpoint are deleted and the log processing on recovery begins with the latest checkpoint. If the system is able to safely shutdown, then a checkpoint may be performed before the driver unloads, and on initialization, the entire persisted flash state may be loaded into the flash memory with a minimal amount of flash scanning. If a power failure occurs during system operation, then on the next boot-up, only the sectors or blocks specified in the log entries after the latest checkpoint have to be scanned, rather than all the sectors on the part. | 11-19-2009 |
20090287875 | MEMORY MODULE AND METHOD FOR PERFORMING WEAR-LEVELING OF MEMORY MODULE - The invention comprises a memory module capable of wear-leveling. In one embodiment, the memory module comprises a flash memory and a controller. The flash memory comprises a plurality of management units, wherein each of the management units comprises a plurality of blocks. The controller receives new data with a logical address managed by a first management unit selected from the management units, pops a first spare block from a spare area of the first management unit, determines whether an erase count of the first spare block is greater than a first threshold value, searches a second management unit selected from the management units for a replacing block with an erase count lower than a second threshold value when the erase count of the first spare block is greater than the first threshold value, and directs the first management unit and the second management unit to exchange the first spare block with the replacing block. | 11-19-2009 |
20090287876 | METHOD, APPARATUS AND CONTROLLER FOR MANAGING MEMORIES - A method, an apparatus and a controller for managing memories are provided. In the present invention, a data accessing format of each of the memories is adjusted such that the accessing units for each data accessing operation are unified. A mapping table is then established for recording the adjusted data accessing format. When a data accessing command is received from a host, the mapping table is inquired so as to execute the data accessing command. Accordingly, incompatibility of hardware structures can be resolved, and management of different types of flash memory can be achieved. | 11-19-2009 |
20090287877 | MULTI NON-VOLATILE MEMORY CHIP PACKAGED STORAGE SYSTEM AND CONTROLLER AND ACCESS METHOD THEREOF - A multi non-volatile memory chip packaged storage system having a memory module, a controller, a first and a second control buses and a first and a second I/O buses is provided. The memory module at least includes a first and a second non-volatile memory chips which are both enabled by receiving a chip enabled signal via a chip enabled pin, wherein the memory module and the controller are stacked and packaged as a single chip. After the first and the second non-volatile memory chips are enabled by the chip enable signal via the chip enabled pin, the controller may active the first and second control buses and the first and second I/O buses to access the first and the second non-volatile memory chips, or only active the first control and I/O buses or the second control and I/O buses to access the corresponding first or second non-volatile memory chip. | 11-19-2009 |
20090287878 | STORAGE APPARATUS USING FLASH MEMORY - For a storage apparatus in which flash memory disks and hard disks coexist, high-density mounting of flash memory modules is achieved. A storage apparatus in accordance with the present invention includes flash memories and a storage controller. A second storage apparatus including magnetic disks is connected to the storage apparatus. For creation of a logical volume, the storage controller can form a storage area using a flash memory or a magnetic disk. When an input/output request is issued from a host computer, if a storage area is formed with a flash memory, the storage controller directly accesses the flash memory to handle the input/output request. When the storage apparatus defines a storage area formed with a flash memory, the storage apparatus defines the storage area by adding up the capacity of a storage area to be provided for the host computer and a substitute area capacity determined in consideration of restrictions imposed on the number of times of deletion of the flash memory. | 11-19-2009 |
20090287879 | NAND FLASH MEMORY DEVICE AND METHOD OF MAKING SAME - An integrated circuit includes a NAND string including a string selection transistor SST and a ground selection transistor GST disposed at either end of series-connected memory storage cells MC. Each of the memory storage cells is a memory transistor having a floating gate, and at least one of the string selection transistor SST and the ground selection transistor GST is a memory transistor having a floating gate. The threshold voltage Vth of programmable string selection transistors SST and the ground selection transistor GST is variable and user controllable and need not be established by implantation during manufacture. Each of the programmable string selection transistors SST and the ground selection transistors GST in a memory block may be used to store random data, thus increasing the memory storage capacity of the flash memory device. | 11-19-2009 |
20090292860 | METHOD OF PROGRAMMING NON-VOLATILE MEMORY DEVICE - The present invention relates to a method of programming a non-volatile memory device. A method of programming an non-volatile memory device in accordance with an aspect of the present invention includes inputting n page of data, storing a single page of data in each of page buffer units of a plurality of memory cell units, programming a first page of data stored in a page buffer unit of a first memory cell unit, transferring a second page of data, stored in a page buffer unit of a second memory cell unit, to the page buffer unit of the first memory cell unit, and programming the transferred second page of data into the first memory cell unit. | 11-26-2009 |
20090292861 | USE OF RDMA TO ACCESS NON-VOLATILE SOLID-STATE MEMORY IN A NETWORK STORAGE SYSTEM - A network storage controller uses a non-volatile solid-state memory (NVSSM) subsystem which includes raw flash memory as stable storage for data, and uses remote direct memory access (RDMA) to access the NVSSM subsystem, including to access the flash memory. Storage of data in the NVSSM subsystem is controlled by an external storage operating system in the storage controller. The storage operating system uses scatter-gather lists to specify the RDMA read and write operations. Multiple client-initiated reads or writes can be combined in the storage controller into a single RDMA read or write, respectively, which can then be decomposed and executed as multiple reads or writes, respectively, in the NVSSM subsystem. Memory accesses generated by a single RDMA read or write may be directed to different memory devices in the NVSSM subsystem, which may include different forms of non-volatile solid-state memory. | 11-26-2009 |
20090292862 | FLASH MEMORY MODULE AND STORAGE SYSTEM - A storage controller manages address conversion information denoting the correspondence relationship between a logical address and a physical address of storage area (for example, a physical block) inside a flash memory. The storage controller uses the above-mentioned address conversion information to specify a physical address corresponding to a logical address specified by an I/O request from a higher-level device, and sends an I/O command including I/O-destination information based on the specified physical address to a memory controller inside a flash memory module. The memory controller carries out the I/O with respect to a storage area inside a flash memory specified from the I/O-destination information of the I/O command from the storage controller. | 11-26-2009 |
20090292863 | MEMORY SYSTEM WITH A SEMICONDUCTOR MEMORY DEVICE - A memory system with a semiconductor memory device, in which a physical block of n-bits serves as an erase unit, wherein the address management of the memory device is performed by a logical block with m-bits, “m” being larger than “n” and expressed by a power of two, and wherein a n-bit portion continued from the head address in the logical block is defined as a first management unit corresponding to one physical block of the memory device, and a number of the remaining fraction portions each defined as a second management unit are gathered so as to correspond to one physical block of the memory device. | 11-26-2009 |
20090292864 | IDENTIFICATION INFORMATION MANAGEMENT SYSTEM AND METHOD FOR MICROCOMPUTER - An exemplary object of the present invention is to facilitate the management of identification information in a microcomputer having a flash memory. A system | 11-26-2009 |
20090292865 | SYSTEMS AND METHODS FOR SCHEDULING A MEMORY COMMAND FOR EXECUTION BASED ON A HISTORY OF PREVIOUSLY EXECUTED MEMORY COMMANDS - A memory system is operated by maintaining a queue of memory commands to be executed, maintaining a list of previously executed memory commands, comparing local information associated with the commands to be executed with local information associated with the list of previously executed commands, and selecting one of the commands for execution from the queue of memory commands to be executed based on a result of the comparison. | 11-26-2009 |
20090300269 | HYBRID MEMORY MANAGEMENT - Methods and apparatus for managing data storage in hybrid memory devices utilizing single level and multi level memory cells. Logical addresses can be distributed between single level and multilevel memory cells based on a frequency of write operations performed. Initial storage of data corresponding to a logical address in memory can be determined by various methods including initially writing all data to single level memory or initially writing all data to multilevel memory. Other methods permit a host to direct logical address writes to single level or multilevel memory cells based on anticipated usage. | 12-03-2009 |
20090300270 | Dynamoelectric machine assemblies having memory for use by external devices - A method is provided for storing data from an external device in a dynamoelectric machine assembly (i.e., an electric motor or generator). The dynamoelectric machine assembly includes a memory device and a processor for controlling operation of the dynamoelectric machine assembly in response to commands from an external device. The method includes receiving a command from the external device to store data in the memory device of the dynamoelectric machine assembly, and storing the data in the memory device in response to the command. Dynamoelectric machine assemblies, external devices and systems suitable for use in the provided method are also disclosed. | 12-03-2009 |
20090300271 | STORAGE SYSTEM HAVING MULTIPLE NON-VOLATILE MEMORIES, AND CONTROLLER AND ACCESS METHOD THEREOF - A non-volatile memory storage system including a transmission interface, a memory module, and a controller is provided. The memory module includes first and second non-volatile memory chips. The first and the second non-volatile memory chips can be simultaneously enabled by receiving a chip enable signal from the controller via a chip enable pin. When the controller performs a multichannel access, the controller provides an access instruction to the first and second non-volatile memory chip, after enabling the first non-volatile memory chip and the second non-volatile memory chip with the chip enable signal. When the controller performs a single channel access, the controller provides the access signal to one of the first and second non-volatile memory chips, and provides a non-access instruction to the other one, after enabling the first non-volatile memory chip and the second non-volatile memory chip with the chip enable signal. | 12-03-2009 |
20090300272 | Method for increasing reliability of data accessing for a multi-level cell type non-volatile memory - A method for increasing reliability of data accessing for a multi-level cell type non-volatile memory, wherein a plurality of data storage blocks are taken for data accessing of a computer system in accordance with the structure of storage of the multi-level cell type non-volatile memory; and a page jumper is provided to select at least a set of data storage pages in corresponding to a physical page of same storage cell, by jump connecting of the page jumper which jumps over another data storage page in corresponding to the physical page of the same storage cell, then the data storage page selected is accessed for at least a data storage block. the frequency of erasing of flash memory blocks can thus be reduced to elongate the life of use of the multi-level cell type non-volatile memory, this can assure integrity of the data in accessing during abnormal system power breaking. | 12-03-2009 |
20090300273 | Flash memory apparatus with automatic interface mode switching - A flash memory controller with automatic interface mode switching is applied to a flash memory apparatus with a plurality of flash memories and the controller contains: a memory interface, a microprocessor, and an interface mode controller. The microprocessor recognizes the supported interface mode of every flash memory connected with the memory interface in an initial setting process, and individually sets the corresponding interface mode setting value into the interface mode controller. Thus, when the flash memory apparatus is operating in a normal operation state, the interface mode controller can output the corresponding interface mode setting value according to the present enabled flash memory, and the memory interface can adjust and switch the interface mode according to the interface mode setting value outputted by the interface mode controller. Thereby, the present invention can achieve the purpose whereby the flash memory apparatus can speed up accessing and increase efficiency. | 12-03-2009 |
20090300274 | SSD WITH DISTRIBUTED PROCESSORS - In one embodiment, a system includes a serial data bus, a plurality of processors of a first type, and a processor of a second type. The serial data bus is configured to be coupled to a corresponding serial data bus of a host device. Each of the plurality of processors of the first type is coupled to a respective flash memory device. The processor of the second type is configured to manage the access that the plurality of the processors of the first type have to the serial data bus. | 12-03-2009 |
20090300275 | SEMICONDUCTOR DEVICE AND CONTROL METHOD OF THE SAME - A semiconductor device includes: a first sector ( | 12-03-2009 |
20090300276 | ENHANCED DATA ACCESS IN A STORAGE DEVICE - A flash storage device having improved write performance is provided. The device includes a storage block having a plurality of physical pages and a controller configured to allocate subsets of the plurality of physical pages to a plurality of logical addresses, respectively, and to write data to the plurality of physical pages. Each of the subsets of physical pages includes more than one physical page. Upon receiving a first write request for one of the logical addresses, data from the first write request is written to a first physical page of the physical pages allocated to the logical address. Upon receiving a second write request for one of the logical address, the data from the second write request is written to a second physical page allocated to the logical address and the first physical page allocated to the logical address is invalidated. | 12-03-2009 |
20090307411 | METHOD AND APPARATUS FOR SECURING DIGITAL INFORMATION ON AN INTEGRATED CIRCUIT DURING TEST OPERATING MODES - The embodiments protect an IC against Design-For-Test (DFT) or other test mode attack. Transitory secrets are secured whether stored in registers or latches, RAM, and/or permanent secrets stored in ROM and/or PROM. One embodiment for securing information on an IC includes entering a test mode and resetting each register in response to entering the test mode of operation and prior to receiving a test mode command. An integrated circuit embodiment includes a test control logic operative to configure the integrated circuit into a test mode and to control the integrated circuit while in the test mode, a set of registers, and a functional reset controller coupled to the test control logic and to the set of registers, operative to receive a reset command from the test control logic and provide the reset command to the set of registers in response to a command to enter the test mode. | 12-10-2009 |
20090307412 | MEMORY MANAGEMENT METHOD FOR NON-VOLATILE MEMORY AND CONTROLLER USING THE SAME - A memory management method for a non-volatile memory and a controller using the same are provided. The non-volatile memory is substantially divided into a plurality of blocks. First, non-erasing information of a plurality of memory units comprising at least one block is recoded and used as a reference to establish an evaluation value. Then, whether to move data of at least one block on the memory units to another memory unit according to the evaluation value is determined. Accordingly, problems of read disturb and data retention due to excessive reading times can be resolved. | 12-10-2009 |
20090307413 | DATA WRITING METHOD FOR FLASH MEMORY AND STORAGE SYSTEM AND CONTROLLER USING THE SAME - A data writing method for a multi-level cell (MLC) NAND flash memory and a storage system and a controller using the same are provided. The flash memory includes a plurality of blocks. Each of the blocks includes a plurality of page addresses. The page addresses are categorized into a plurality of upper page addresses and a plurality of lower page addresses. The writing speed of the lower page addresses is faster than that of the upper page addresses. The data writing method includes receiving a writing command and data and writing the data into a page address. The page address is skipped when it is an upper page address and a corresponding lower page address stores a valid data written by a previous writing command. Thereby, the accuracy of the data written by the previous writing command is ensured when a programming error occurs to the flash memory. | 12-10-2009 |
20090307414 | MEMORY SYSTEM, MEMORY SYSTEM CONTROL METHOD, AND DRIVE RECORDER APPARATUS - A memory system includes a NAND-type flash memory which includes a plurality of memory cells and can store one-bit, two-bit or more data in one memory cell, and a duplicating-converting circuit configured to duplicate input data by assigning the input data to a predetermined threshold level and another threshold level different from the predetermined threshold level. Moreover, the memory system includes a controller configured to control to store the data duplicated by the duplicating-converting circuit, in the NAND-type flash memory. | 12-10-2009 |
20090307415 | Memory device having multi-layer structure and driving method thereof - A memory device having a multi-layer structure, the memory device includes a first semiconductor layer including at least one memory cell array. The memory cell array includes a plurality of memory cells. A second semiconductor layer is on the first semiconductor layer. The second semiconductor layer includes a bit line and a page buffer connected to the bit line corresponding to the memory cell array. The memory device also includes a contact between the first semiconductor substrate and the second semiconductor substrate to connect the page buffer with the memory cell array. | 12-10-2009 |
20090307416 | SSD WITH A CONTROLLER ACCELERATOR - In one embodiment, a data storage system includes a solid state data storage device and a memory controller in signal communication with the solid state data storage device. The memory controller includes a processor, a local memory, and an accelerator coupled between the processor and the local memory. The accelerator includes logic circuitry configured to perform data management for the local memory. | 12-10-2009 |
20090313417 | Methods for Data Management in a Flash Memory Medium - A method for data management in a flash memory medium is provided in the present invention, The method comprises the following steps: dividing a plurality of blocks of the flash memory medium into two or more sections; generating a section-address-mapping table by scanning logic addresses in the blocks in each section; storing the section-address-mapping table into a backup block in each section; and performing an operation of writing/reading by reading the section-address-mapping table, storing the section-address-mapping table to a RAM, and performing a conversion between a physical address and a logic address based on the section-address-mapping table stored in the RAM. Since the section-address-mapping tables are stored in the backup block in respective sections, when an operation of writing/reading is performed and it is necessary to switch to a section-address-mapping table for a next section, data stored in the next section can be read out based on the section-address-mapping table stored in the backup block in the next section, without needing to scan each block in the next section for generating a new section-address-mapping table dynamically. Therefore, the method of the present invention can save the time for operation and thus achieve effective management on data in the flash memory medium. | 12-17-2009 |
20090313418 | Using asymmetric memory - In one illustrative embodiment, a computer implemented method using asymmetric memory management is provided. The computer implemented method receives a request, containing a search key, to access an array of records in the asymmetric memory, wherein the array has a sorted prefix portion and an unsorted append portion, the append portion alternatively comprising a linked-list, and responsive to a determination that the request is an insert request, inserts the record in the request in arrival order in the unsorted append portion to form a newly inserted record. Responsive to a determination that the newly inserted record completes the group of records, stores an index, in sorted order, for the group of records. | 12-17-2009 |
20090313419 | METHOD OF STORING DATA ON A FLASH MEMORY DEVICE - Methods and apparatus are disclosed, such as those involving a flash memory device. One such method includes storing data on memory cells on a memory block including a plurality of word lines and a plurality of memory cells on the word lines. The word lines comprising one or more bottom edge word lines, one or more top edge word lines, and intermediate word lines between the bottom and top edge word lines. The data is stored first on memory cells on the intermediate word lines. Then, a remaining portion, if any, of the data is stored on memory cells on the bottom edge word lines and/or the top edge word lines. This method enhances the life of the flash memory by preventing a premature failure of memory cells on the bottom or top edge word lines, which can be more prone to failure. | 12-17-2009 |
20090313420 | Method for saving an address map in a memory device - A method for saving an address map in a memory device is provided. In one embodiment, a logical-to-physical address map is stored in a volatile memory of a memory device. The memory device receives a command from a host device to perform an operation that is associated with a power-down sequence of the host device, such as a flush cache command. In response to receiving the command, the memory device performs the operation and saves the logical-to-physical address map in a non-volatile memory of the memory device. In this way, the command triggers both the performance of the operation and the saving of the logical-to-physical address map in the non-volatile memory of the memory device. | 12-17-2009 |
20090313421 | Data Update Method and Electronic Device Using Such Data Update Method - A data update method is provided for updating the data stored in a memory unit of an electronic device. The data update method includes the following steps. In response to a data update request, a data content indexing table is read from the memory unit. According to the data content indexing table, position information associated with the portion of the data to be updated is computed. According to the position information, the portion of the data to be updated is updated. | 12-17-2009 |
20090313422 | FLASH MEMORY CONTROL APPARATUS HAVING SEQUENTIAL WRITING PROCEDURE AND METHOD THEREOF - A flash memory control apparatus having a sequential writing procedure and method thereof are described. The flash memory control apparatus includes primary controller, a command module, an address module, a data buffer, a status unit, a counting device and a secondary controller. The primary controller generates a predetermined value which represents the amount of a plurality of pages in the flash memory. The command module stores a writing command during the writing procedure. The address module stores a current address for addressing a current page of the pages based on the current address and the writing command via a control bus. The data buffer stores the data for allowing the command module to write the data to the current page based on the current address via the control bus while the writing command is executed on the flash memory. The status unit determines that the flash memory is either ready or busy in writing the data to the current page of the flash memory. If the command module correctly writes the data to the current page according to the determination result, the address module generates at least one next address. The address module addresses at least one next page of the pages based on the at least one next address and the writing command. The command module sequentially writes the data to the at least one next page during the writing procedure until the pages are written successively. | 12-17-2009 |
20090313423 | MULTI-BIT FLASH MEMORY DEVICE AND METHOD OF ANALYZING FLAG CELLS OF THE SAME - Disclosed is a multi-bit flash memory device which includes a memory cell array and a control circuit. The memory cell array has multiple memory cells and multiple flag cells. The control circuit determines whether the flag cells are programmed, based on a reference corresponding to a read margin of the flag cells, and controls a program operation of the memory cells in response to the determination. | 12-17-2009 |
20090313424 | MEMORY DEVICE AND METHOD FOR SECURE READOUT OF PROTECTED DATA - The invention relates to a memory device, preferably a non-volatile memory device, comprising a memory array ( | 12-17-2009 |
20090313425 | MEMORY CONTROL APPARATUS, CONTENT PLAYBACK APPARATUS, CONTROL METHOD AND RECORDING MEDIUM - A data storage apparatus is provided that realizes a measure against deterioration of a flash memory in which integrity check data is stored. A content playback apparatus ( | 12-17-2009 |
20090319720 | SYSTEM AND METHOD OF GARBAGE COLLECTION IN A MEMORY DEVICE - In a particular embodiment, a controller is adapted to perform a garbage collection operation to remove redundant data, to predict a performance parameter associated with performance of the garbage collection operation, and to abort the garbage collection operation when the predicted performance parameter exceeds a threshold. | 12-24-2009 |
20090319721 | FLASH MEMORY APPARATUS AND METHOD FOR OPERATING THE SAME - The invention provides a method for operating a flash memory apparatus. In one embodiment, the flash memory apparatus comprises a single-level-cell memory and a multiple-level-cell memory. First, new data for updating a logical block address is received from a host. An update count corresponding to the logical block address is then compared with a threshold value. When the update count is greater than the threshold value, it is determined whether a first physical block address corresponding to the logical block address is pointing to a multiple-level-cell block of the multiple-level-cell memory. When the first physical block address is pointing to the multiple-level-cell block, a target single-level-cell block is then selected from the single-level-cell memory. A corresponding relationship between the logical block address and a second physical block address of the target single-level-cell block is then built. The new data is then written to the target single-level-cell block with the second physical block address. | 12-24-2009 |
20090319722 | AD HOC FLASH MEMORY REFERENCE CELLS - In a nonvolatile memory, that includes cells organized in a plurality of bit lines and a plurality of word lines, user data are stored in respective portions of each of two of the word lines. Control information is stored in a cell that is common to one of the bit lines and one of the two word lines. A cell that is common to the bit line and the other word line is used as a reference cell. A flash memory, that includes a plurality of primary cells and a plurality of spare cells, is interrogated to determine which spare cells have been used to replace respective primary cells. At least some of the other spare cells are used as reference cells. | 12-24-2009 |
20090319723 | METHOD AND DEVICE FOR BINDING A NON-VOLATILE STORAGE DEVICE WITH A CONSUMER PRODUCT - A method is disclosed for binding a non-volatile storage device ( | 12-24-2009 |
20090327578 | Flash Sector Seeding to Reduce Program Times - A non-volatile flash memory comprises a plurality of non-volatile memories where a first non-volatile memory is pre-programmed (erased) with all ones, and at least a second non-volatile memory is pre-programmed with a seed value that takes advantage of the reduced programming time for less than six zeros. When writing (programming) a data byte, the memory system looks up the data byte in one or more seed tables to determine a portion of non-volatile memory to which the memory system may write the data byte with a reduced programming time. The memory system then records the location of the data byte in an address translation table so the data byte may be accessed. | 12-31-2009 |
20090327579 | LIMITED MEMORY POWER - Storage devices can retain information through application of a charge upon the storage device. However, applying the charge upon the storage device can be change physical characteristics of the charge and ultimately increase a likelihood of device failure. Therefore, a determination can be made on how to apply the charge based upon analysis of the device, of data for retention, and the like. Raw data can be analyzed and/or estimations can be made to determine the charge. | 12-31-2009 |
20090327580 | OPTIMIZATION OF NON-VOLATILE SOLID-STATE MEMORY BY MOVING DATA BASED ON DATA GENERATION AND MEMORY WEAR - An exemplary method includes writing data to locations in non-volatile solid-state memory and deciding whether to move data written to one location in the memory to another location in the memory based on generation of the data and wear of the other location. Such a method may be used for non-volatile random access memory (NVRAM). Various other methods, devices, systems, etc., are also disclosed. | 12-31-2009 |
20090327581 | NAND MEMORY - Disclosed herein is a method and apparatus to refresh/rewrite the data in a NAND solid state storage device (“SSD”) only when it needs to be re-written. Upon power-up, the SSD assumes that it may have been a long time since some of its data was last written, and a background task to scan through all the data is started in the SSD. During idle periods, the entire contents of the drive is read. If a location is read and it has more than “bit error threshold” bits (for example three (3) bits if there is capability to correct eight (8) bits) in error before error correction is applied, it is assumed that this memory location is retaining the data only marginally, and the corrected data should be re-written to a new location, or alternatively re-written in the same location. The corrected data is then re-written to a new location or the same location. | 12-31-2009 |
20090327582 | Banded Indirection for Nonvolatile Memory Devices - Methods, apparatuses, and computer program products that enable banded indirection for nonvolatile memory devices, such as flash memory devices, are disclosed. One or more embodiments comprise a method for performing banded indirection when accessing data of a nonvolatile device. The methods comprise tracking fragmentation of a band of physical addresses of the nonvolatile memory device, storing a physical address of the band, and accessing data of a logical address of the band via the stored physical address based on the fragmentation of the band. Some embodiments comprise apparatuses for accessing data of nonvolatile devices using banded indirection. The embodiments comprise a nonvolatile memory element to store data, wherein the nonvolatile memory element has bands of physical addresses, a fragmentation detector to detect fragmentation of a band of the nonvolatile memory, and a data access module to access data of the band via a physical address based on the fragmentation. | 12-31-2009 |
20090327583 | Seek Time Emulation for Solid State Drives - Methods and apparatuses for delaying execution of input/output (I/O) requests for solid state drives are contemplated. Some embodiments comprise receiving I/O requests for a solid state drive and calculating amounts of time based on characteristics of the requests, such as differences of the logical block addresses (LBAs) of the requests. The embodiments may then delay responses by the solid state drive for the requests. Calculating the amounts of time and delaying the responses by the amounts of time may allow the solid state drives to emulate the responses of various types of hard disk drives. Some embodiments comprise an apparatus for delaying execution of the I/O requests for solid state drives. The apparatuses may have numerous modules, such as a request receiver to receive the I/O requests, a calculation module to calculate the amounts of delay times, and a delay module to delay the responses of the I/O requests. | 12-31-2009 |
20090327584 | Apparatus and method for multi-level cache utilization - In some embodiments, a non-volatile cache memory may include a multi-level non-volatile cache memory configured to be located between a system memory and a mass storage device of an electronic system and a controller coupled to the multi-level non-volatile cache memory, wherein the controller is configured to control utilization of the multi-level non-volatile cache memory. Other embodiments are disclosed and claimed. | 12-31-2009 |
20090327585 | DATA MANAGEMENT METHOD FOR FLASH MEMORY AND STORAGE SYSTEM AND CONTROLLER USING THE SAME - A data management method a flash memory storage system and a controller using the same are provided. The data management method is used for accessing a flash memory of the flash memory storage system, wherein the flash memory includes a plurality of physical blocks and the physical blocks are grouped into a data area and a spare area. The data management method includes configuring a plurality of logical blocks for be accessed by a host. The data management method also includes dividing each physical block into a plurality of physical parts and mapping the logical blocks to the physical parts. The data management method further includes accessing the mapped physical parts according to the physical blocks to be accessed by the host. Accordingly, it is possible to increase the usage and the accessing speed of the physical blocks in the flash memory storage system. | 12-31-2009 |
20090327586 | MEMORY DEVICE AND DATA STORING METHOD - A memory device is provided, comprising a single-level memory unit, a multi-level memory unit and a control unit. The single-level memory unit comprises a first link table and stores data according to the first link table. The multi-level memory unit comprises a second link table and stores data according to the second link table. The control unit directs data which normally belongs to the single-level memory unit to the multi-level memory unit or directs data which normally belongs to the multi-level memory unit to the single-level memory unit according to a control signal. | 12-31-2009 |
20090327587 | PERSONALIZATION OF PORTABLE DATA STORAGE MEDIA - In a method for the personalization of portable data carriers ( | 12-31-2009 |
20090327588 | SOLID-STATE DISK WITH WIRELESS FUNCTIONALITY - A solid-state disk (SSD) controller includes a first integrated circuit (IC) that includes an interface module, a memory control module, and a wireless network interface module. The interface module externally interfaces the SSD controller to a computing device. The memory control module controls solid-state memory, receives data from the computing device via the interface module, and caches the data in the solid-state memory. The wireless network interface module communicates with the computing device via the interface module and allows the computing device to connect to a wireless network. | 12-31-2009 |
20090327589 | TABLE JOURNALING IN FLASH STORAGE DEVICES - A method of table journaling in a flash storage device comprising a volatile memory and a plurality of non-volatile data blocks is provided. The method comprises the steps of creating a first copy in a first one or more of the plurality of non-volatile data blocks of an addressing table stored in the volatile memory, writing transaction log data to a second one or more of the plurality of non-volatile data blocks, and updating the first copy of the addressing table based on changes to the addressing table stored in the volatile memory after the second one or more of the plurality of non-volatile data blocks have been filled with transaction log data. | 12-31-2009 |
20090327590 | ENHANCED MLC SOLID STATE DEVICE - Flash memory drives and related methods are disclosed that operate to keep frequently written data, which results in frequently erased blocks, in SLC-mimicking MLC flash, and relatively static data in normal MLC flash. A flash drive according to the present disclosure keeps track of the number of times that data for each logical block address (LBA) has been written to the flash memory, and determines whether to store newly received data associated with a particular LBA in SLC-mimicking MLC flash or in normal MLC flash depending on the number of writes that have occurred for that particular LBA. Dynamic allocation can occur between the two types of MLC. Related methods and software are also described. | 12-31-2009 |
20090327591 | SLC-MLC COMBINATION FLASH STORAGE DEVICE - Flash memory drives and related methods are disclosed that operate to keep frequently written data, which results in frequently erased blocks, in SLC flash, and relatively static data in MLC flash. A flash drive according to the present disclosure keeps track of the number of times that data for each logical block address (LBA) has been written to the flash memory, and determines whether to store newly received data associated with a particular LBA in SLC flash or in MLC flash depending on the number of writes that have occurred for that particular LBA. For each logical block sent to the flash drive, a comparison is made of the write count of the associated LBA to a threshold. If the write count is above the threshold, the logical block is written to SLC flash. If the write count is below the threshold, the logical block is written to MLC flash. | 12-31-2009 |
20090327592 | CLUSTERING DEVICE FOR FLASH MEMORY AND METHOD THEREOF - Disclosed are a clustering device for a flash memory and a method thereof. The clustering device for a flash memory in accordance with an embodiment of the present invention can gather pages having similar update times and perform a write operation of the pages in a same block. Accordingly, the writing performance of the flash memory can be improved and the lifetime of the flash memory can be increased. | 12-31-2009 |
20090327593 | READ-ONLY MEMORY DEVICE WITH SECURING FUNCTION AND ACCESSING METHOD THEREOF - The present invention provides a memory device and a method for accessing the memory device thereof. The memory device comprises an address encoding selector for selecting one of plurality of encoding circuits which encodes a first address into a second address, and a data decoding selector for selecting one of plurality of decoding circuits which decodes a first data corresponding to the second address into a second data and a non-volatile memory, coupled to address encoding selector and the data decoding selector, for storing the first data. The method for accessing the memory device comprises encoding a first address into a second address by an address encoding selector, and decoding a first data corresponding to the second address into a second data by a data decoding selector, wherein the first data being stored in the non-volatile memory. | 12-31-2009 |
20090327594 | APPARATUS AND METHODS FOR PROGRAMMING MULTILEVEL-CELL NAND MEMORY DEVICES - Methods and apparatus are provided. A first data value is read from a first memory cell and is stored. An attempt is made to add a second data value to the first memory cell. If the attempt to add the second data value to the first memory cell is unsuccessful, the first data value and the second data value are written to one or more other memory cells. | 12-31-2009 |
20090327595 | STORAGE CAPACITY STATUS - In one embodiment of the present invention, a memory device is disclosed to include memory organized into blocks, each block having a status associated therewith and all of the blocks of the nonvolatile memory having collectively a capacity status associated therewith and a display for showing the capacity status even when no power is being applied to the display. | 12-31-2009 |
20100005224 | Foldable USB flash memory device that can be manufactured in any desired shape and size suitable for different types of host devices - An enhanced design for the USB flash memory devices implemented with the USB specifications. The main idea in this design is to create two-section USB flash memory devices and both the sections be joined together with the help of rotating hinges and pivots so that both the sections can rotate with respect to each other. In this design, one section contains the USB connector that is used to connect the USB device with the host device and the other section contains the USB controller, memory controller, and flash memory components of a standard USB device. This arrangement provides the ability to both the sections in the device to rotate against each other and adjust at any desired angle and be folded together. While the rotating hinges are required at both the end sides of two sections where both the sections join together to be able to rotate around each other, rotating hinges or ribbon cables are used between the two sections to provide path for the data flow and the required power between the USB flash memory device and the USB host. | 01-07-2010 |
20100005225 | NONVOLATILE MEMORY DEVICE, NONVOLATILE MEMORY SYSTEM, AND HOST DEVICE - A nonvolatile memory device has a file system manager and manages the file system of a file to be recorded. The nonvolatile memory device measures time by obtaining time information from outside in each writing file data or based on time information preliminarily obtained. At the time of writing file data, management information of the file system is configured based on the time information at the time. Thus, the time information can be stored in a file entry table, and the time information can be used as file management information. The nonvolatile memory system with high user's convenience can be provided. | 01-07-2010 |
20100005226 | NONVOLATILE MEMORY DEVICE, ACCESS DEVICE, AND NONVOLATILE MEMORY SYSTEM - An access device | 01-07-2010 |
20100005227 | MEMORY CONTROLLER, NONVOLATILE MEMORY DEVICE, ACCESS DEVICE, AND NONVOLATILE MEMORY SYSTEM - A file to be read or written is designated and accessed from an access device side to a nonvolatile memory device. In an initialization after start-up of the power source, an empty capacity detector detects empty capacity parameters of a nonvolatile memory with dividing the memory into a plurality of regions. An empty capacity parameter notification part notifies the access device of the empty capacity parameters in a stepwise fashion whenever the empty capacity detector detects an empty capacity. With this, at the time when the empty capacity becomes not less than a capacity required to write file data, the data can be written to the nonvolatile memory without waiting for completion of the initialization, resulting in improvement of a response in the recording. | 01-07-2010 |
20100005228 | DATA CONTROL APPARATUS, STORAGE SYSTEM, AND COMPUTER PROGRAM PRODUCT - A data control apparatus includes a mapping-table managing unit that manages a mapping table that is associated with a corrupted-data recovery function of recording data and error correcting code data as redundant data that is given separately from the data, distributed and stored in units of stripe blocks in the plural nonvolatile semiconductor memory devices, the mapping table containing arrangement information of the data and the error correcting code data; a determining unit that determines whether to differentiate frequencies of writing the data into the semiconductor memory devices; and a changing unit that changes the arrangement information by switching the data stored in units of the stripe blocks managed using the mapping table to differentiate the frequencies of writing the data into the semiconductor memory devices, when the determining unit determines that the frequencies of writing the data into the semiconductor memory devices are to be differentiated. | 01-07-2010 |
20100005229 | FLASH MEMORY APPARATUS AND METHOD FOR SECURING A FLASH MEMORY FROM DATA DAMAGE - A method for securing a flash memory from data damage is provided. After writing of data to a plurality of written pages of a first block of a flash memory is completed, a last weak page of the written pages is determined. A first strong page corresponding to the last weak page is then determined. A plurality of strong pages between the first strong page and the last weak page are then determined. Data of the plurality of strong pages is the coped to a backup area of the flash memory for data recovery. | 01-07-2010 |
20100005230 | DATA STORING METHODS AND APPARATUS THEREOF - A data storing method for non-volatile memory is provided, wherein the non-volatile memory includes at least one memory block having a plurality of strong pages and weak pages. A logic block writing command is received for storing the corresponding writing data into the memory block. It is then determined whether the writing data is larger than one page. The writing data is divided into a plurality of page data according to the memory size of the page when the writing data is larger than one page. Next, a first storing page for each page data is determined according to a starting writing page according to the logic block writing command. And, the page data are sequentially written into the first storing pages. Note that each first storing page is a strong page within the memory block. | 01-07-2010 |
20100005231 | METHOD AND SYSTEM FOR HARDWARE IMPLEMENTATION OF RESETTING AN EXTERNAL TWO-WIRED EEPROM - Methods and systems for hardware controlling of an electrically erasable programmable read only memory (EEPROM) are described herein. Aspects of the invention may include generating a clock signal at a frequency suitable for EEPROM operation and resetting an EEPROM utilizing the generated clock signal and a hardware generated data signal without initiation by a central processing unit (CPU). The resetting may occur via a virtual CPU. The CPU and the virtual CPU may be integrated on a single chip. The signal generation and EEPROM resetting may occur via a virtual CPU integrated within a finite state machine. A frequency counter may be utilized to generate a clock signal from a clock source having a higher frequency than that required by the EEPROM. | 01-07-2010 |
20100005232 | MEMORY CONTROLLER INTERFACE - A memory interface controller and method to allow a processor designed and configured to operate with NOR flash and SRAM memory devices to instead operate using NAND flash and SDRAM. The system accomplishes this by caching sectors out of NAND flash into SDRAM, where the data can be randomly accessed by the processor as though it were accessing data from NOR flash/SRAM. Sectors containing data required by the processor are read out of NAND flash and written into SDRAM, where the data can be randomly accessed by the processor. | 01-07-2010 |
20100011149 | Data Storage Devices Accepting Queued Commands Having Deadlines - A data storage device accepts queued read and write commands that have deadlines. The queued read and write commands are requests to access the data storage device. The deadlines of the queued read and write commands can be advisory deadlines or mandatory deadlines. | 01-14-2010 |
20100011150 | DATA COLLECTION AND COMPRESSION IN A SOLID STATE STORAGE DEVICE - Methods for programming compressed data to a memory array, memory devices, and memory systems are disclosed. In one such method, memory pages or blocks that are partially programmed with valid data are found. The data is collected from these partially programmed pages or blocks and the data is compressed. The compressed data is then programmed back to different locations in the memory array of the memory device. | 01-14-2010 |
20100011151 | DATA ACCESSING METHOD, AND STORAGE SYSTEM AND CONTROLLER USING THE SAME - A data accessing method, and a storage system and a controller using the same are provided. The data accessing method is suitable for a flash memory storage system having a data perturbation module. The data accessing method includes receiving a read command from a host and obtaining a logical block to be read and a page to be read from the read command. The data accessing method also includes determining whether a physical block in a data area corresponding to the logical block to be read is a new block and transmitting a predetermined data to the host when the physical block corresponding to the logical block to be read is a new block. Thereby, the host is prevented from reading garbled code from the flash memory storage system having the data perturbation module. | 01-14-2010 |
20100011152 | DATA PROGRAMMING METHODS AND DEVICES - A data programming device is provided and comprises a non-volatile memory, a volatile memory, and a memory control unit. The non-volatile memory is arranged for programming data. The volatile memory is arranged for temporarily storing data. The memory control unit is arranged for receiving data and determining whether the data is programmed into the non-volatile memory or stored into the volatile memory. If the data exceeds one page, the memory control unit programs a first portion of the data into the non-volatile memory and stores a second portion of the data, which is insufficient for one page, into the volatile memory. | 01-14-2010 |
20100011153 | BLOCK MANAGEMENT METHOD, AND STORAGE SYSTEM AND CONTROLLER USING THE SAME - A block management method for managing a multi level cell (MLC) NAND flash memory is provided, wherein the MLC NAND flash memory has a plurality of physical blocks grouped into at least a data area and a spare area, each of the physical blocks has a plurality of pages divided into a plurality of upper pages, and a plurality of lower pages with a writing speed thereof being greater than that of the upper pages. The block management method includes configuring a plurality of logical blocks for being accessed by a host, recording the logical block belonged to a frequently accessed block and executing a special mode to use the lower pages of at least two physical blocks of the MLC NAND flash memory for storing data of one logical block belonged to the frequently accessed block. Accordingly, it is possible to increase the access speed of a storage system. | 01-14-2010 |
20100011154 | DATA ACCESSING METHOD FOR FLASH MEMORY AND STORAGE SYSTEM AND CONTROLLER USING THE SAME - A data accessing method for a flash memory and a storage system and a controller using the same are provided. The data accessing method includes grouping a plurality of physical blocks of the flash memory into a data area, a spare area, and a random area and when a write command and a new data to be written are received from a host, determining whether the new data is a continuous data, wherein the new data is written temporarily into the physical blocks in the random area if the new data is not a continuous data. Thereby, the number of data moving and physical block erasing is reduced and accordingly the data accessing speed in a random writing mode is increased. | 01-14-2010 |
20100011155 | Data processor with flash memory, and method for accessing flash memory - A data processor includes a flash memory that stores a plurality of types of data therein, a random access memory that stores record data information therein, and a controller that can access the flash memory and the RAM. The record data information indicates a head address in the flash memory and a data length corresponding to latest data of each of the plurality of types of data. The controller reads, from the flash memory, the latest data of a type of a reading target among the plurality of types of data, with reference to the record data information. | 01-14-2010 |
20100011156 | MEMORY DEVICE AND MANAGEMENT METHOD OF MEMORY DEVICE - A memory device includes a plurality of blocks, and the plurality of blocks may include a plurality of pages. The memory device may translate an external physical address into internal physical address using a non-volatile address translation memory. The memory device may access one page of a plurality of pages using the internal physical address. | 01-14-2010 |
20100011157 | DEVICE AND METHOD FOR BACKING UP DATA ON NON- VOLATILE MEMORY MEDIA, OF THE NAND FLASH TYPE, DESIGNED FOR ONBOARD COMPUTERS - The present invention relates to a device making it possible to manage a flash memory component designed for onboard computers notably in the aviation field. In particular, the invention makes it possible to use NAND flash memory media in fields such as aviation, by virtue of its judicious organisation and management of the flash memory components. On the one hand it makes it possible to optimise and on the other hand to control the lifetime of the flash memories. | 01-14-2010 |
20100011158 | MEMORY CONTROLLER, MEMORY SYSTEM, AND CONTROL METHOD FOR MEMORY SYSTEM - A memory controller for performing processing for writing data in an interleaved manner and in units of pages in a semiconductor memory section made up of chip | 01-14-2010 |
20100011159 | COMBINED MOBILE DEVICE AND SOLID STATE DISK WITH A SHARED MEMORY ARCHITECTURE - A mobile device includes a system-on-chip (SOC) that includes a mobile device control module, a solid state disk (SSD) control module, and a random access memory (RAM) control module. The mobile device control module executes application programs for the mobile device. The solid-state disk (SSD) control module controls SSD operations. The RAM control module communicates with the mobile device control module and the SSD control module and stores both SSD-related data and mobile device-related data in a single RAM. | 01-14-2010 |
20100011160 | Method and system for providing security to processors - There are various methods of securing programs and data on a processor. The external address enable pin of the processor is sampled upon a power-on or reset to the processor, to determine whether or not accesses to external memory are allowed. Other changes to the external address enable pin are thereafter ignored. In addition, if it is determined that an internal memory access is occurring, the contents of such an access can be masked to prevent unauthorized viewing of the memory contents via an external memory bus. In addition, a programmable security bit may be set to disable the dumping of flash memory contents, allowing only the erasing of the flash memory. | 01-14-2010 |
20100011161 | Memory emulation using resistivity sensitive memory - Interface circuitry in communication with at least one non-volatile resistivity-sensitive memory is disclosed. The memory includes a plurality of non-volatile memory elements that may have two-terminals, are operative to store data as a plurality of conductivity profiles that can be determined by applying a read voltage across the memory element, and retain stored data in the absence of power. A plurality of the memory elements can be arranged in a cross-point array configuration. The interface circuitry electrically communicates with a system configured for memory types, such as HDD, DRAM, SRAM, and FLASH, for example, and is operative to communicate with the non-volatile resistivity-sensitive memory to emulate one or more of those memory types. The interface circuitry can be fabricated in a logic plane on a substrate with at least one non-volatile resistivity-sensitive memory vertically positioned over the logic plane. The non-volatile resistivity-sensitive memories may be vertically stacked upon one another. | 01-14-2010 |
20100017554 | SYSTEM AND METHOD FOR MANAGING A PLUGGED DEVICE - An electronic device is provided including a non-volatile memory, a connection interface, a processor and at least one resource. The at least one resource has at least one configuration. The non-volatile memory stores the configuration for the resource. The processor generates the configuration for the resource. When plugged into the host device through the connection interface, the electronic device receives a request from the host device and performs an operation in the resource using the configuration. | 01-21-2010 |
20100017555 | Memory storage device and control method thereof - A control method of a memory storage device for writing an updated data from a host to the memory storage device is provided. The memory storage device provides storage space which is divided into a plurality of physical blocks to access the updated data. The control method includes the following steps: first, determining whether the updated data is a hot data or not; finally, storing the less updated data which is not the hot data into the physical block which has the higher erase counts according to the result of above determination. | 01-21-2010 |
20100017556 | NON-VOLATILE MEMORY STORAGE SYSTEM WITH TWO-STAGE CONTROLLER ARCHITECTURE - The present invention discloses a non-volatile memory storage system with two-stage controller, comprising: a plurality of flash memory devices; a plurality of first stage controllers coupled to the plurality of flash memory devices, respectively, wherein each of the first stage controllers performs data integrity management as well as writes and reads data to and from a corresponding flash memory device; and a storage adapter communicating with the plurality of first stage controllers through one or more internal interfaces. | 01-21-2010 |
20100017557 | MEMORY CONTROLLER, NONVOLATILE MEMORY DEVICE,ACCESS DEVICE, AND NONVOLATILE MEMORY SYSTEM - A nonvolatile memory device reads and writes file data according to a file ID designated by an access device. The nonvolatile memory device includes a capacity parameter decision part | 01-21-2010 |
20100017558 | Memory device operable in read-only and re-writable modes of operation - A one-time programmable (OTP) memory device and methods for use therewith are provided. These embodiments can be used to provide compatibility between a memory device that uses an OTP (or few-time programmable (FTP)) memory array and host devices that use a file system, such as the DOS FAT file system, that expects to be able to rewrite to a memory address in the memory device. | 01-21-2010 |
20100017559 | Memory device operable in read-only and write-once, read-many (WORM) modes of operation - One-time programmable (OTP) and write-once read-many (WORM) memory devices and methods for use therewith are provided. These embodiments can be used to provide compatibility between a memory device that uses an OTP (or few-time programmable (FTP)) memory array and host devices that use a file system, such as the DOS FAT file system, that expects to be able to rewrite to a memory address in the memory device. These embodiments can also be used to prevent accidental or deliberate overwrites, changes, or deletions to existing data in a WORM memory device. | 01-21-2010 |
20100017560 | MEMORY CONTROLLER, NONVOLATILE MEMORY DEVICE, ACCESS DEVICE, AND NONVOLATILE MEMORY SYSTEM - It has been difficult for an access device to obtain a remaining capacity of a memory from a nonvolatile memory device having a plurality of interfaces. A capacity parameter generation part | 01-21-2010 |
20100017561 | SELECTIVELY ACCESSING MEMORY - Devices, systems, methods, and other embodiments associated with selectively accessing memory are described. In one embodiment, a method detects an indication indicative of whether to program fast access pages or slow access pages of a flash memory. In response to the detected indication, data is programmed from a volatile memory: (1) to the fast access pages of the flash memory while skipping the slow access pages, or (2) to the slow access pages while skipping the fast access pages. | 01-21-2010 |
20100017562 | MEMORY SYSTEM - To provide a memory system that can store data smaller than a block size and data larger than the block size without deteriorating writing efficiency, and can dynamically change a parallelism according to the data. The memory system according to an embodiment of the present invention comprises a DRAM | 01-21-2010 |
20100017563 | MICROCONTROLLER BASED FLASH MEMORY DIGITAL CONTROLLER SYSTEM - Some embodiments includes a digital control system having a microcontroller for handling timed events, a command decoder for interpreting user commands, a separate burst controller for handling burst reads of the Flash memory, a program buffer for handling page writes to the Flash memory, a page transfer controller for handling data transfers from the Flash core to the program buffer as well as address control for page writes from the program buffer to the Flash memory, a memory control register block for storing and adjusting memory control, and memory test mode signals, a memory plane interface for multiplexing addresses into the Flash memory and accelerating program, erase, and recovery verification, and an I/O Mux module for multiplexing data out of the system, and a general purpose I/O port (GPIO) that can be read and written by the microcontroller for use in test and debug. Other embodiments are described. | 01-21-2010 |
20100023672 | Method And System For Virtual Fast Access Non-Volatile RAM - A method of writing data to a non-volatile memory with minimum units of erase of a block, a page being a unit of programming of a block, may read a page of stored data addressable in a first increment of address from the memory into a page buffer, the page of stored data comprising an allocated data space addressable in a second increment of address, pointed to by an address pointer, and comprising obsolete data. The first increment of address is greater than the second increment of address. A portion of stored data in the page buffer may be updated with the data to form an updated page of data. Storage space for the updated page of data may be allocated. The updated page of data may be written to the allocated storage space. The address pointer may be updated with a location of the allocated storage space. | 01-28-2010 |
20100023673 | AVOIDANCE OF SELF EVICTION CAUSED BY DYNAMIC MEMORY ALLOCATION IN A FLASH MEMORY STORAGE DEVICE - The operating firmware of a portable flash memory storage device is stored in the relatively large file storage memory, which is non executable. It is logically parsed into overlays to fit into an executable memory. The overlays can be of differing sizes to organize function calls efficiently while minimizing dead space or unnecessarily separating functions that should be within one or a group of frequently accessed overlays. For an overlay having functions that require data allocation, the data allocation can cause eviction. This self eviction is avoided altogether or after initial runtime. | 01-28-2010 |
20100023674 | Flash DIMM in a Standalone Cache Appliance System and Methodology - A method, system and program are disclosed for accelerating data storage in a cache appliance cluster that transparently monitors NFS and CIFS traffic between clients and NAS subsystems and caches files in a multi-rank flash DIMM cache memory by pipelining multiple page write and page program operations to different flash memory ranks, thereby improving write speeds to the flash DIMM cache memory. | 01-28-2010 |
20100023675 | WEAR LEVELING METHOD, AND STORAGE SYSTEM AND CONTROLLER USING THE SAME - A wear leveling method for a flash is provided, wherein the flash memory includes a plurality of physical blocks grouped into at least a data area and a spare area. The method includes setting a first predetermined threshold value as a wear-leveling start value and randomly generating a random number as a memory erased count, wherein the random number is smaller than the wear-leveling start value. The method also includes counting the memory erased count each time when the physical blocks are erased and determining whether the memory erased count is smaller than the wear-leveling start value, wherein a physical blocks switching is performed between the data area and the spare area when the memory erased count is not smaller then the wear-leveling start value. Accordingly, it is possible to uniformly use the physical blocks, so as to effectively prolong a lifetime of the store system. | 01-28-2010 |
20100023676 | SOLID STATE STORAGE SYSTEM FOR DATA MERGING AND METHOD OF CONTROLLING THE SAME ACCORDING TO BOTH IN-PLACE METHOD AND OUT-OF-PLACE METHOD - A solid state storage system includes a controller configured to divide memory blocks of a flash memory area into first blocks and second blocks corresponding to the first blocks, newly allocates pages of the second blocks when an external write command is requested. The controller is also configured to allocate selected sectors in the allocated pages according to sector addresses and execute a write command. | 01-28-2010 |
20100023677 | SOLID STATE STORAGE SYSTEM THAT EVENLY ALLOCATES DATA WRITING/ERASING OPERATIONS AMONG BLOCKS AND METHOD OF CONTROLLING THE SAME - A solid state storage system that evenly allocates data writing/erasing operations among blocks is presented. The solid state storage system includes a controller. The controller is configured to set a representative value that becomes a block allocation reference in accordance with predetermined information of blocks in a flash memory area. The controller is also configured to calculate a data value that becomes life time information according to the predetermined information in a current state for each block. The controller is also configured to determine a block where a deviation is generated between the representative value and the data value. The controller is also configured to allocate block where the deviation is generated as a new block where data is written. | 01-28-2010 |
20100023678 | NONVOLATILE MEMORY DEVICE, NONVOLATILE MEMORY SYSTEM, AND ACCESS DEVICE - When an access device accesses a nonvolatile memory device, the nonvolatile memory device or the access device detects or calculates a temperature T of the nonvolatile memory device. A temperature-adaptive control part of the nonvolatile memory device controls an access rate to a nonvolatile memory on the basis of the temperature T. Accordingly, the control part controls the rate so that the temperature T of the nonvolatile memory devices cannot exceed a limit temperature Trisk. In this manner, a nonvolatile memory system can eliminate a risk of a burn when ejecting the semiconductor memory device and can read and write data at a high speed. | 01-28-2010 |
20100023679 | SYSTEMS AND TECHNIQUES FOR NON-VOLATILE MEMORY BUFFERING - An apparatus, system, method, and article for non-volatile memory buffering are described. The apparatus may include a data storage manager to store a data item in a rewritable non-volatile memory buffer. The data item may have a file size less than or equal to a threshold value. The rewritable non-volatile memory buffer may include one or more rewritable memory regions configured to store the data item. Other embodiments are described and claimed. | 01-28-2010 |
20100023680 | Method for Controlling Non-Volatile Semiconductor Memory System - In a memory system using a storage medium, which is inserted into an electronic apparatus via a connector to add a memory function thereto, the storage medium has a GROUND terminal, a power supply terminal, a control terminal and a data input/output terminal, and the connector has a function of being sequentially connected to each of the terminals. When the storage medium is inserted into the connector, the GROUND terminal and control terminal of the storage medium are connected to corresponding terminals of the connector before the power supply terminal and data input/output terminal of the storage medium are connected to corresponding terminals of the connector. Thus, it is possible to improve the stability when a memory card is inserted into or ejected from the memory system. | 01-28-2010 |
20100023681 | Hybrid Non-Volatile Memory System - The present invention presents a hybrid non-volatile system that uses non-volatile memories based on two or more different non-volatile memory technologies in order to exploit the relative advantages of each these technology with respect to the others. In an exemplary embodiment, the memory system includes a controller and a flash memory, where the controller has a non-volatile RAM based on an alternate technology such as FeRAM. The flash memory is used for the storage of user data and the non-volatile RAM in the controller is used for system control data used by the control to manage the storage of host data in the flash memory. The use of an alternate non-volatile memory technology in the controller allows for a non-volatile copy of the most recent control data to be accessed more quickly as it can be updated on a bit by bit basis. In another exemplary embodiment, the alternate non-volatile memory is used as a cache where data can safely be staged prior to its being written to the to the memory or read back to the host. | 01-28-2010 |
20100023682 | Flash-Memory System with Enhanced Smart-Storage Switch and Packed Meta-Data Cache for Mitigating Write Amplification by Delaying and Merging Writes until a Host Read - A flash memory solid-state-drive (SSD) has a smart storage switch that reduces write acceleration that occurs when more data is written to flash memory than is received from the host. Page mapping rather than block mapping reduces write acceleration. Host commands are loaded into a Logical-Block-Address (LBA) range FIFO. Entries are sub-divided and portions invalidated when a new command overlaps an older command in the FIFO. Host data is aligned to page boundaries with pre- and post-fetched data filling in to the boundaries. Repeated data patterns are detected and encoded by compressed meta-data codes that are stored in meta-pattern entries in a meta-pattern cache of a meta-pattern flash block. The sector data is not written to flash. The meta-pattern entries are located using a meta-data mapping table. Storing host CRC's for comparison to incoming host data can detect identical data writes that can be skipped, avoiding a write to flash. | 01-28-2010 |
20100030943 | Semiconductor Memory - A semiconductor memory having a burst mode reading function in synchronization with a clock signal comprises a memory array composed of a plurality of memory cells, a sync read control circuit for releasing an upper group of the received address as a memory access address and a lower group of the received address as a burst address in synchronization with the clock signal, a sense amplifier for releasing an output data from each of the memory cells selected by the memory address, a decoder for decoding the burst address, a address latch for latching the decoded burst address in synchronization with the clock signal, a page selector for holding the output data and selecting corresponding one of the output data determined by the burst address of the address latch, and an output latch for latching the output data in synchronization with the clock signal. | 02-04-2010 |
20100030944 | Method and Apparatus for Storing Data in Solid State Memory - A method and a storage device for storing data in a flash memory drive are disclosed. In order to increase data throughput, the drive includes a cache memory including a tag memory and a plurality of flash devices coupled via a plurality of channels to the cache memory. | 02-04-2010 |
20100030945 | FLASH MEMORY ALLOCATING METHOD - An allocating method for a flash memory is disclosed. The allocating method includes the following steps: adjusting a preliminary data storage capacity corresponding to the flash memory for determining a real data storage capacity of the flash memory; adjusting a preliminary spare area capacity corresponding to the flash memory for determining a real spare area capacity of the flash memory, wherein a total capacity of the preliminary data storage capacity and the preliminary spare area capacity is equal to the total capacity of the real data storage capacity and the real spare area capacity; and allocating the real data storage capacity and the real spare area capacity to the flash memory, wherein the real data storage capacity stores data, and the real spare area capacity stores parity codes generated by an error codes correction algorithm performed upon the stored data in the real data storage capacity. | 02-04-2010 |
20100030946 | STORAGE APPARATUS, MEMORY AREA MANAGING METHOD THEREOF, AND FLASH MEMORY PACKAGE - A storage device is provided, which allows a write area associated with a data area of interest to be allocated according to write performance of a host computer. The storage apparatus includes one or more flash memory packages having a plurality of flash memories and stores data transmitted from one or more host computers. A storage area provided by the one or more flash memory packages includes a first area that is an area for storing actual data formed by one or more logical devices and a second area that is an area for storing a write instruction from the host computer to the logical device. The first and second areas are provided in each of the one or more flash memory packages. The apparatus further includes a monitoring section monitoring the frequency of write instructions from the host computer and a changing section for changing the size of the second area according to the frequency of write instructions. | 02-04-2010 |
20100030947 | HIGH-SPEED SOLID STATE STORAGE SYSTEM - A solid state storage device includes a main memory cell array and a sub-memory area. The main memory cell array stores data in a flash memory, whereas the sub-memory includes a non-volatile random access memory for storing data. The data storage speed of the non-volatile random access memory of the sub-memory area is faster than the data storage speed of the flash memory of the main memory cell area. The sub-memory area of the solid state storage device also stores address mapping information therein, so that the address mapping information does not have to be transferred to the main memory cell area and a portion of the main memory cell area does not have to be designated for a non-volatile memory for storing the address mapping information. | 02-04-2010 |
20100030948 | SOLID STATE STORAGE SYSTEM WITH DATA ATTRIBUTE WEAR LEVELING AND METHOD OF CONTROLLING THE SOLID STATE STORAGE SYSTEM - A solid state storage system is disclosed capable of performing wear leveling utilizing attributes of different types of data. The solid state storage system performs a control operation such that logical addresses are configured to be mapped to physical addresses of pages in multiple planes of a memory area. In addition, the continuous logical addresses are mapped to the physical addresses of the pages of the different planes. The logical addresses are subsequently grouped so as to define multiple data areas for programming data having different attributes. Accordingly, the data is allocated so as to reduce a life time deviation between planes. | 02-04-2010 |
20100030949 | Non-volatile memory devices and control and operation thereof - An improved non-volatile erase block memory device apparatus and method is described that incorporates an improved addressing scheme to provide for extended addressing allowing redundant erase blocks that are not utilized to repair general use erase blocks of the main memory array to be accessed and utilized as additional storage space by an end user. The additional storage space formed by the unused redundant erase blocks and the specified storage space of the main memory array is presented to the end user as a single contiguous address space. Additionally, the redundant erase blocks can be utilized to repair any damaged erase block in the memory array of the non-volatile erase block memory or Flash memory device regardless of bank placement. | 02-04-2010 |
20100030950 | CYCLIC BUFFER MECHANISM FOR RECEIVING WIRELESS DATA UNDER VARYING DATA TRAFFIC CONDITIONS - A method of ensuring that data sent to a handheld wireless communications device is written to non-volatile memory is disclosed. In a device, where data is initially written to a first volatile memory and then written to a second volatile memory before being written from the second volatile memory to a non-volatile memory, software code is implemented that causes the writing of the data to non-volatile memory concurrently with the writing of the data to the second volatile memory. The software code may incorporate operating system commands (such as Windows OS). | 02-04-2010 |
20100030951 | NONVOLATILE MEMORY SYSTEM - A Flash memory system is implemented in a system-in-package (SIP) enclosure, the system comprising a Flash memory controller and a plurality Flash memory devices. An SIP relates to a single package or module comprising a number of integrated circuits (chips). The Flash memory controller is configured to interface with an external system and a plurality of memory devices within the SIP. The memory devices are configured in a daisy chain cascade arrangement, controlled by the Flash memory controller through commands transmitted through the daisy chain cascade. | 02-04-2010 |
20100030952 | Memory Module, Memory System, and Information Device - A memory system including large-capacity ROM and RAM in which high-speed reading and writing are enabled is provided. | 02-04-2010 |
20100036999 | NOVEL METHOD OF FLASH MEMORY CONNECTION TOPOLOGY IN A SOLID STATE DRIVE TO IMPROVE THE DRIVE PERFORMANCE AND CAPACITY - The present invention provides a novel flash memory connection method between a flash controller and flash devices such that the controller can manage two or more flash devices concurrently. It provides the ability to efficiently manage a large array of non-volatile flash devices in a solid state drive (SSD) and allocate flash memory usage in such a way that at least doubles the SSD bandwidth and the total storage capacity. | 02-11-2010 |
20100037000 | ONE-TIME-PROGRAMMABLE MEMORY EMULATION - This document discloses one-time-programmable (“OTP”) memory emulation and methods of performing the same. OTP memory can be emulated by managing reads and writes to a memory array in response to an instruction to write data to a OTP memory location and selectively setting a security flag that corresponds to the memory locations. The memory array can be a NAND Flash memory array that includes multiple pages of memory. The memory array can be defined by memory blocks that can include multiple pages of memory. When an OTP write instruction is received, previously stored data can be read from a first page of memory, combined with the new data and stored to a target page of memory. A security flag can be set to prevent the target page from being reprogrammed prior to an erase. | 02-11-2010 |
20100037001 | Flash memory based storage devices utilizing magnetoresistive random access memory (MRAM) - A flash memory based storage device may utilize magnetoresistive random access memory (MRAM) as at least one of a device memory, a buffer, or high write volume storage. In some embodiments, a processor of the storage device may compare a logical block address of a data file to a plurality of logical block addresses stored in a write frequency file buffer table and causes the data file to be written to the high write volume MRAM when the logical block address of the data file matches at least one of the plurality of logical block addresses stored in the write frequency file buffer table. In other embodiments, upon cessation of power to the storage device, the MRAM buffer stores the data until power is restored, after which the processor causes the buffered data to be written to the flash memory under control of the flash memory controller. | 02-11-2010 |
20100037002 | MIXED TECHNOLOGY STORAGE DEVICE - A mixed storage device includes a set of storage units, each potentially based on a different storage technology, such as NAND flash drive, NOR flash drive, magnetic hard drive, magneto-optical drives, optical drives, etc. The mixed storage device comprises a host bus connector that is used to connect to a peripheral bus that facilitates communication to a processor of a device (such as a PC) and a controller. The controller manages a NAND flash storage device, a NOR flash storage device, an optical storage device, a hard drive and other storage components plugged into or integrated with the mixed storage device. | 02-11-2010 |
20100037003 | FLASH MEMORY CONTROL APPARATUS HAVING SIGNAL-CONVERTING MODULE - A flash memory control apparatus having a signal-converting module is described. The signal-converting module includes a primary controller, a signal-converting module, a data buffer, and a secondary controller. The primary controller generates a plurality of control signals based on a first control interface. The signal-converting module receiving a reading enable signal and a writing enable signal of the control signals and converts the reading enable signal and the writing enable signal into a writing/reading signal based on a second control interface. The data buffer stores the data from the primary controller according to the first control interface and stores the data from the flash memory according to the second control interface. The secondary controller transmits the writing/reading signal, a clock signal and a data strobe signal to the flash memory based on the second control interface. | 02-11-2010 |
20100037004 | STORAGE SYSTEM FOR BACKUP DATA OF FLASH MEMORY AND METHOD FOR THE SAME - A storage system for backup data of a flash memory includes a flash memory for storing a first file, a detector for detecting a number of accesses to the first file, and a driving unit coupled to the detector. The driving unit is used for duplicating the first file as one or more second files when the number of accesses to the first file exceeds a predetermined value, and storing the one or more first files into the flash memory. If the access number is higher than the predetermined value, which indicates this file is more likely to be accessed, the invention automatically backups this file and accesses the backup file at the next access request for fear that the file is damaged by multiple access to the same file. | 02-11-2010 |
20100037005 | COMPUTING SYSTEM INCLUDING PHASE-CHANGE MEMORY - A computing system, more particularly, a computing system including a phase-change memory is provided. The computing system includes a flash memory configured to store data and a phase-change memory configured to store address mapping information for converting a logical address into a physical address. The phase-change memory is configured to store the address mapping information while the computing system is in a power-off state. The computing system may store an address mapping table to manage the flash memory in the phase-change memory. | 02-11-2010 |
20100037006 | NON-VOLATILE MEMORY AND CONTROLLING METHOD THEREOF - A non-volatile memory of present invention includes a number of memory blocks and a static wear leveling device. The static wear leveling device includes a memory unit for storing the erase counts of the memory blocks and a controlling unit for getting the erase counts from the memory unit, and calculating the standard deviation based on the EC, and deciding the way of the static wear leveling cycle according to the standard deviation. The controlling unit deciding the way of the static wear leveling cycle include the steps of setting at least one predetermined threshold point and judging whether the standard deviation of the erase counts is smaller than the predetermined threshold point. If the standard deviation of the erase counts is smaller than the predetermined threshold point, the static wear leveling cycle starts for a first amount of cycles and moves the static data stored a first number of memory blocks. If the standard deviation of the erase counts is bigger than the predetermined threshold point, starts for a second amount of cycles and moves the static data stored a second number of memory blocks. | 02-11-2010 |
20100037007 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device includes a memory cell array in which memory cells having an electrically rewritable charge accumulation layer are arranged, a data writing/reading circuit that writes/reads data to/from the memory cell array in units of pages, a write state information storage circuit for nonvolatile storage of write state information indicating a data write state to the memory cell array by the data writing/reading circuit, and a control circuit that controls the data writing/reading circuit based on an access page address indicating a page from which data is about to be read by the data writing/reading circuit and write state information stored in the write state information storage circuit. | 02-11-2010 |
20100037008 | APPARATUS WITH A FLASH MEMORY AND METHOD FOR WRITING DATA TO THE FLASH MEMORY THEREOF - An apparatus | 02-11-2010 |
20100037009 | SEMICONDUCTOR STORAGE DEVICE, METHOD OF CONTROLLING THE SAME, CONTROLLER AND INFORMATION PROCESSING APPARATUS - A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second and third memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data outputted from the first memory area by a first management unit in the second memory area, and a third processing for storing data outputted from the first memory area by a second management unit in the third memory area. | 02-11-2010 |
20100037010 | SEMICONDUCTOR STORAGE DEVICE, METHOD OF CONTROLLING THE SAME, CONTROLLER AND INFORMATION PROCESSING APPARATUS - A semiconductor storage device includes first, second, third, fourth and fifth memory areas and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data by a first management unit in the fourth memory area, a third processing for storing data by a second management unit in the fifth memory area, a fourth processing for moving an area of the third unit to the second memory area, a fifth processing for selecting and copying data to an empty area of the third unit in the second memory area, a sixth processing for moving an area of the third unit to the third memory area, and a seventh processing for selecting and copying data to an empty area of the third unit in the third memory area. | 02-11-2010 |
20100037011 | Semiconductor Storage Device, Method of Controlling The Same, Controller and Information Processing Apparatus - A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second, third, and fourth memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data by a first management unit in the fourth memory area, a third processing for storing data by a second management unit in the third memory area, a fourth processing for moving an area of the third unit having the oldest allocation order in the fourth memory area to the second memory area, and a fifth processing for selecting data in the second memory area and copying the selected data to an empty area of the third unit in the second memory area. | 02-11-2010 |
20100037012 | Semiconductor Storage Device, Method of Controlling the Same, Controller and Information Processing Apparatus - A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second, third and fourth memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data by a first management unit in the fourth memory area, a third processing for storing data by a second management unit in the third memory area, a fourth processing for moving an area of the third unit from the fourth memory area to the second memory area, a fifth processing for copying data to an area of the third unit and allocating the area to the second memory area, and a sixth processing for copying data to an empty area of the third unit in the second memory area. | 02-11-2010 |
20100042772 | Method and apparatus for high reliability data storage and retrieval operations in multi-level flash cells - One or more multi-level NAND flash cells are operated so as to store only single-level data, and these operations achieve an increased level of charge separation between the data states of the single-level operation by requiring a write to both the upper and lower pages, even though only one bit of data is being stored. That is, the second write operation increases the difference in floating gate charge between the erased state and the programmed state of the first write operation without changing the data in the flash memory cell. In one embodiment, a controller instructs the flash memory to perform two write operations for storing a single bit of data in an MLC flash cell. In another embodiment, the flash memory recognizes that a single write operation is directed a high reliability memory area and internally generates the required plurality of programming steps to place at least a predetermined amount of charge on the specified floating gate. | 02-18-2010 |
20100042773 | FLASH MEMORY STORAGE SYSTEM AND DATA WRITING METHOD THEREOF - A flash memory storage system and a data writing method thereof are provided. The flash memory storage system includes a controller, a connector, a cache memory, a SLC NAND flash memory and a MLC NAND flash memory. When the controller receives data to be written into the MLC NAND flash memory from a host system, the data is temporarily stored in the cache memory first and then is written into the MLC NAND flash memory from the cache memory. And, the controller may backup the data stored in the cache memory to the SLC NAND flash memory. Accordingly, it is possible to reduce a response time for a flush command, thereby improving a performance of the flash memory storage system. | 02-18-2010 |
20100042774 | BLOCK MANAGEMENT METHOD FOR FLASH MEMORY, AND STORAGE SYSTEM AND CONTROLLER USING THE SAME - A block management method for a flash memory chip having multiple planes is provided, wherein each plane has a plurality of physical blocks. The method includes disposing a plurality of physical units, wherein each physical unit includes a physical block of each plane, and the physical blocks in the physical unit have a simultaneously-operable relationship. The method also includes writing data in a single plane access mode when a host system does not update all the physical blocks in an updated the physical unit. The method further includes writing the data in a multi-planes access mode when the host system updates all the physical blocks in the updated physical unit, wherein the physical blocks for writing the data have the simultaneously-operable relationship. | 02-18-2010 |
20100042775 | BLOCK MANAGEMENT METHOD FOR FLASH MEMORY, AND STORAGE SYSTEM AND CONTROLLER USING THE SAME - A block management method for managing a flash memory is provided. The method includes dividing the flash memory into a cache area and a storage area and dividing the cache area into a plurality of cache sub-areas, wherein the storage area has a plurality of physical blocks and each cache sub-area contains at least one physical block. The method also includes configuring a plurality of logical blocks for mapping the physical blocks of the storage area, and allocating one of the cache sub-areas for each logical block, wherein when the host writes the data into the logical blocks, the data may be temporarily stored in the cache sub-areas allocated for the logical blocks. Accordingly, it is possible to increase efficiency of the flash storage system and avoid wearing of the physical blocks, so as to prolong a lifetime of the flash storage system. | 02-18-2010 |
20100042776 | Method and apparatus for providing enhanced write performance using a buffer cache management scheme based on a buffer replacement rule - An approach is provided for improving write performance using a buffer cache based on a buffer replacement policy. A buffer cache manager is configured to improve address mapping scheme associated with write performance between an application system and a storage device system. The manager selects a victim page to be evicted from a victim block of a buffer cache according to a recently-evicted-first rule. And the victim block is selected associated with a log block of a memory. | 02-18-2010 |
20100042777 | SEMICONDUCTOR DEVICE INCLUDING MEMORY CELL HAVING CHARGE ACCUMULATION LAYER AND CONTROL GATE AND DATA WRITE METHOD FOR THE SAME - A semiconductor device includes a nonvolatile semiconductor memory and a controller. The nonvolatile semiconductor memory includes a first memory block configured to hold at least 2 bits data, and a second memory block configured to hold 1-bit data. The data is programmed into the first and second memory blocks in units of page. Each of the pages in the first memory block is assigned to a corresponding bit of the held data. Time required for write varies depending on the bit. The controller instructs the nonvolatile semiconductor memory to program the write data into the first memory block or the second memory block. The controller instructs the nonvolatile semiconductor memory to program the data on any of the pages in the second memory block if a final page of the write data corresponds to the bit requiring the longest time for the write. | 02-18-2010 |
20100049900 | MEMORY CARD AND NON-VOLATILE MEMORY CONTROLLER THEREOF - A memory card and a non-volatile memory controller thereof are provided. The non-volatile memory controller provides a process interface to allow a host to access a non-volatile memory. The non-volatile memory controller includes a mode setting port group, a firmware download port group, a host access port group, a memory port group, a control unit, a processing unit, an interface unit, and a switch unit. When a firmware in the non-volatile memory is to be updated, the switch unit switches to the firmware download port group and then connects it to a fixture to obtain a new firmware. The control unit writes the new firmware into the non-volatile memory directly on a printed circuit board according to an instruction of the process unit. Thereby, in the present invention, firmware updating can be carried out directly on a printed circuit board therefore is made more convenient. | 02-25-2010 |
20100049901 | MEMORY CARD AND NON-VOLATILE MEMORY CONTROLLER THEREOF - A memory card and a non-volatile memory controller thereof are provided. The non-volatile memory controller includes a firmware download port group, a memory interface unit, a processing unit, and a host interface unit. The firmware download port group is used for coupled to a firmware update fixture. The memory interface unit includes at least one tri-state buffer component, and the memory interface unit is coupled to a non-volatile memory and the firmware download port group through the tri-state buffer component, wherein the tri-state buffer component determines whether to operate in a high-impedance mode or a normal mode according to a mode single. The processing unit accesses the non-volatile memory through the memory interface unit. When the tri-state buffer component operates in the high-impedance mode according to the mode single, the firmware update fixture writes a new firmware into the non-volatile memory through the firmware download port group. | 02-25-2010 |
20100049902 | STORAGE SUBSYSTEM AND STORAGE SYSTEM INCLUDING STORAGE SUBSYSTEM - To provide a storage subsystem in which, even when plural types of storage devices are provided, write processing from a cache memory to the plural types of storage devices is not delayed. Even when there are relative merits in writing performance of write data from the cache memory to the HDD and the SSD, the cache memories | 02-25-2010 |
20100049903 | RECORDING SYSTEM AND DATA RECORDING METHOD - A recording method for writing data into an electrically erasable programmable read-only memory is disclosed, in which the memory has already been electrically connected to a controller through a logic device. The method sets the logic devices for the first time to disconnect the memory from the controller, and set the logic devices for the second time to write setting data required by the controller into the memory. After that, the method reads out the setting data stored in the memory to confirm the writing of the setting data, and connects the memory to the controller again. | 02-25-2010 |
20100049904 | STORAGE DEVICE USING A MULTI-LEVEL FLASH MEMORY AS A SINGLE FLASH MEMORY AND METHOD FOR THE SAME - A storage device includes a multi-level cell flash memory having a plurality of physical memory cells, a read controller, and a write controller. The physical memory cells form a first page and a second page. The write controller in response to a first request is used for writing first data into the first page, duplicating the first data as a second data and writing the second data into the second page. The read controller is used for adjusting the stored data value complying with a desired storing value. Each physical memory cell comprises four threshold voltage ranges indicative of two-bit logical values. The two-bit data is assigned as a first logical value accordingly in response to a two-bit data corresponding to a first and second threshold voltage ranges in a first physical memory cell. The two-bit data is assigned as a second logical value accordingly in response to a two-bit data corresponding to a third and fourth threshold voltage ranges in a second physical memory cell. | 02-25-2010 |
20100049905 | Flash memory-mounted storage apparatus - In a data center, there is a limit in power capacity supplied to a storage apparatus, and the rated power consumption of the storage apparatus may exceed the power supply capacity by addition of storage capacity. A storage apparatus according to the invention includes one or plural packages mounting plural flash memories and a circuit controlling the flash memories as well as information of power supply capacity. The number of flash memories performing writing, erasing or reading at the same time is designated with respect to each package based on the information of power supply capacity. | 02-25-2010 |
20100049906 | SECURE NON-VOLATILE MEMORY DEVICE AND METHOD OF PROTECTING DATA THEREIN - The invention relates to a non-volatile memory device comprising: an input for providing external data (D) to be stored on the non-volatile memory device; a first non-volatile memory block ( | 02-25-2010 |
20100049907 | Memory System and Control Method Thereof - A memory system includes a nonvolatile memory including a plurality of blocks as data erase units, a measuring unit which measures an erase time at which data of each block is erased, and a block controller which writes data supplied from at least an exterior into a first block which is set in a free state and whose erase time is oldest. | 02-25-2010 |
20100049908 | Adaptive Mode Switching of Flash Memory Address Mapping Based on Host Usage Characteristics - In a non-volatile memory storage system such as a flash EEPROM system, a controller switches the manner in which data sectors are mapped into blocks and metablocks of the memory in response to host programming and controller data consolidation patterns, in order to improve performance and reduce wear. Data are programmed into the memory with different degrees of parallelism. | 02-25-2010 |
20100049909 | NAND Flash Memory Controller Exporting a NAND Interface - A NAND controller for interfacing between a host device and a flash memory device (e.g. a NAND flash memory device) fabricated on a flash die is disclosed. In some embodiments, the presently disclosed NAND controller includes electronic circuitry fabricated on a controller die, the controller die being distinct from the flash die, a first interface (e.g. a host-type interface, for example, a NAND interface) for interfacing between the electronic circuitry and the flash memory device, and a second interface (e.g. a flash-type interface) for interfacing between the controller and the host device, wherein the second interface is a NAND interface. According to some embodiments, the first interface is an inter-die interface. According to some embodiments, the first interface is a NAND interface. Systems including the presently disclosed NAND controller are also disclosed. Methods for assembling the aforementioned systems, and for reading and writing data using NAND controllers are also disclosed. | 02-25-2010 |
20100049910 | Flash EEprom System With Simultaneous Multiple Data Sector Programming and Storage of Physical Block Characteristics in Other Designated Blocks - A non-volatile memory system is formed of floating gate memory cells arranged in blocks as the smallest unit of memory cells that are erasable together. The system includes a number of features that may be implemented individually or in various cooperative combinations. One feature is the storage in separate blocks of the characteristics of a large number of blocks of cells in which user data is stored. These characteristics for user data blocks being accessed may, during operation of the memory system by its controller, be stored in a random access memory for ease of access and updating. According to another feature, multiple sectors of user data are stored at one time by alternately streaming chunks of data from the sectors to multiple memory blocks. Bytes of data in the stream may be shifted to avoid defective locations in the memory such as bad columns. Error correction codes may also be generated from the streaming data with a single generation circuit for the multiple sectors of data. The stream of data may further be transformed in order to tend to even out the wear among the blocks of memory. Yet another feature, for memory systems having multiple memory integrated circuit chips, provides a single system record that includes the capacity of each of the chips and assigned contiguous logical address ranges of user data blocks within the chips which the memory controller accesses when addressing a block, making it easier to manufacture a memory system with memory chips having different capacities. A typical form of the memory system is as a card that is removably connectable with a host system but may alternatively be implemented in a memory embedded in a host system. The memory cells may be operated with multiple states in order to store more than one bit of data per cell. | 02-25-2010 |
20100057976 | MULTIPLE PERFORMANCE MODE MEMORY SYSTEM - A method and system for controlling a write performance level of a memory is disclosed. The method includes receiving an input at the memory, and configuring the memory to an operation mode providing a write performance level and a storage capacity. The input may specify a storage capacity, a working area capacity, a write performance level, and/or a ratio of the storage capacity to the working area capacity. A desired write performance level may be set by receiving a software command or hardware setting. The storage capacity may be varied depending on whether the memory device has been formatted. As the storage capacity decreases, working area capacity of the memory device increases and write performance increases. Conversely, as the storage capacity increases, working area capacity decreases and write performance decreases. | 03-04-2010 |
20100057977 | REDUCED-POWER PROGRAMMING OF MULTI-LEVEL CELL (MLC) MEMORY - In one embodiment, a mobile electronic device has a host controller, an energy-saving encoder, an energy-saving decoder, and a multi-level cell (MLC) NAND flash memory. The host controller provides raw user data to the energy-saving encoder in k-bit segments. The energy-saving encoder encodes each k-bit segment into an n-bit segment of encoded user data for programming the MLC NAND flash memory as a p-symbol codeword, where (i) k is smaller than n (ii) p(=n/log | 03-04-2010 |
20100057978 | Storage system and data guarantee method - A system according to the invention reads/writes data by using a memory device performing a wear leveling. A host | 03-04-2010 |
20100057979 | DATA TRANSMISSION METHOD FOR FLASH MEMORY AND FLASH MEMORY STORAGE SYSTEM AND CONTROLLER USING THE SAME - A data transmission method suitable for transmitting data from a cache to a plurality of flash memory groups through a single data bus in a flash memory storage system is provided. The data transmission method includes sequentially sorting and grouping data to be written at continuous logical addresses in the cache in unit of logical blocks. The data transmission method further includes respectively transmitting the grouped sector data into the flash memory groups through the data bus in an interleaving manner, wherein data in the same logical block is transmitted and written into physical blocks of the same flash memory group. Thereby, the data is prevented from being written into different physical blocks, and accordingly the lifespan of the flash memory storage system is prolonged. | 03-04-2010 |
20100057980 | DATA MEMORY DEVICE WITH AUXILIARY FUNCTION - The invention relates to a method, a data storage device, and a system with a data storage device having an additional module ( | 03-04-2010 |
20100064092 | INTERFACE FOR WRITING TO MEMORIES HAVING DIFFERENT WRITE TIMES - An interface between memories having different write times is described. The interface includes a latch for capturing address and data information during a memory access by a processor of a first memory device. The interface also includes an index counter for providing frame management. The interface also includes a variable identity array logic for determining what data is to be written into a second memory device and address generation logic to determine where the data is to be stored in the second memory device. Additionally, the interface includes data validity logic to ensure that the data being written into the second memory device is valid. As a result, the processor can operate in substantially real time and can restore itself after detecting an event upset using the data stored in the second memory device. | 03-11-2010 |
20100064093 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR CONVERTING DATA IN A BINARY REPRESENTATION TO A NON-POWER OF TWO REPRESENTATION - A system, method, and computer program product are provided for converting data in a binary representation to a non-power of two representation. In operation, data in a binary representation is identified. Additionally, the data in the binary representation is converted to a non-power of two representation having a non-power of two number of voltage levels. | 03-11-2010 |
20100064094 | Memory managing method for non-volatile memory and controller using the same - A memory managing method for a non-volatile memory and a controller using the same are disclosed. The controller includes a system wear leveling member for performing a first wear leveling process in a non-volatile memory for choosing a memory unit; and a subsystem wear leveling member for performing a second wear leveling process in the chosen memory unit for selecting a block from the chosen memory unit for data programming; whereby uneven use of the blocks of the chosen memory unit is avoided. | 03-11-2010 |
20100064095 | Flash memory system and operation method - The present invention discloses a flash memory system comprising: a cache memory, a cache memory interface, a host interface, a flash memory interface, and a microprocessor The cache memory interface contains an arbitrator for performing data bus bandwidth time sharing process to access the cache memory The host interface is used for receiving data from a host system, and storing the data into the cache memory to form ready data The flash memory interface reads the ready data from the cache memory and stores it into at least one flash memory The microprocessor is used for controlling the host interface and the flash memory interface to access the cache memory Hence, the present invention can achieve the purpose of enhancing the access efficiency and increasing the life of the flash memory | 03-11-2010 |
20100064096 | SYSTEMS AND METHODS FOR TEMPORARILY RETIRING MEMORY PORTIONS - Flash memory apparatus including a plurality of memory portions, and a controller operative to reserve for data retention purposes, for at least a first duration of time, only certain portions from among said plurality of memory portions including allocating data, during the first duration of time, only to the certain portions, thereby to define at least one of the plurality of memory portions other than the certain portions as a retired memory portion for the first duration of time. | 03-11-2010 |
20100064097 | FLASH MEMORY STORAGE SYSTEM - A flash memory storage system has a plurality of flash memory devices comprising a plurality of flash memories, and a controller having an I/O processing control unit for accessing a flash memory device specified by a designated access destination in an I/O request received from an external device from among the plurality of flash memory devices. A parity group can be configured of flash memory devices having identical internal configuration. | 03-11-2010 |
20100064098 | Device and Method for Controlling Solid-State Memory System - A memory system includes an array of solid state memory devices which are in communication with and under the control of a controller module via a device bus with very few lines. This forms an integrated-circuit mass storage system which is contemplated to replace a mass storage system such as a disk drive memory in a computer system. Command, address and data information are serialized into component strings and multiplexed before being transferred between the controller module and the array of memory devices. The serialized information are is accompanied by a control signal to help sort out the multiplexed components. Each memory device in the array is mounted on a multi-bit mount and assigned an array address by it an array mount. An A memory device is selected by an appropriate address broadcast over the device bus, without requiring the usual dedicated select signal. A reserved array particular mount multi-bit configuration is used to unconditionally select the device mounted thereon. A reserved predefined address broadcast over the device bus deselects all previously selected memory devices. Read performance is enhanced by a read streaming technique in which while a current chunk of data is being serialized and shifted out of the memory subsystem devices to the controller module, the controller module is also setting up the address for the next chunk of data to begin to address the memory system. | 03-11-2010 |
20100070681 | METHOD FOR SCRAMBLING DATA IN WHICH SCRAMBLING DATA AND SCRAMBLED DATA ARE STORED IN CORRESPONDING NON-VOLATILE MEMORY LOCATIONS - A method in which data is randomized before being stored in a non-volatile memory to minimize data pattern-related read failures. Predetermined randomized non-user data is stored in a block or other location of a memory array, and accessed as needed by a memory device controller to randomize user data before it is stored in other blocks of the array. Each portion of the user data which is stored in a block is randomized using a portion of the non-user data which is stored in the same relative location in another block. | 03-18-2010 |
20100070682 | BUILT IN ON-CHIP DATA SCRAMBLER FOR NON-VOLATILE MEMORY - A non-volatile memory in which data is randomized before being stored in the non-volatile memory to minimize data pattern-related read failures. Randomizing is performed using circuitry on the memory die so that the memory die is portable relative to an external, off-chip controller. Circuitry on the memory die scrambles user data based on a key which is generated using a seed which is shifted according to a write address. Corresponding on-chip descrambling is also provided. | 03-18-2010 |
20100070683 | METHOD TO MONITOR READ/WRITE STATUS OF FLASH MEMORY DEVICES - A method and flash memory device employing the method includes a flash memory device having a logic routine saved on the flash memory being a computer readable medium. The flash memory device generates a plurality of memory inputs and outputs. The logic routine determines a memory input and/or memory output operation, and incrementally counts memory inputs and memory outputs using a counter function of the logic routine. The logic routine determines the total number of the plurality of memory inputs and outputs using the counter function. Additionally, the logic routine generates an alert signal when the total number of the memory inputs and outputs exceeds a predetermined value programmed in the logic routine. | 03-18-2010 |
20100070684 | MEMORY DEVICE AND OPERATING METHOD THEREOF - A memory device preloads a command file and a plurality of response files. Whenever a host sends a command to the memory apparatus, the command assigns one of the response files; thereby the host can receive response of the memory apparatus by reading the assigned response file. | 03-18-2010 |
20100070685 | METHOD FOR OPERATING MEMORY CARD - A method is used for operating a memory card, which comprises following steps: (1) a file is preloaded in the first sector of the file allocation table and the second sectors of the description block, wherein the file at least including first data, second data and third data, wherein the first sector is filled up with the first data, only one of the second sectors is not filled up with the second data and the other second sectors are filled up with the third data. (2) A command is received, where the command is capable of updating the file. (3) The command for the first sector is ignored. (4) The only one of the second sectors is updated according to the command. (5) The command for the other second sectors is ignored. (6) The second data of the only one of the second sectors are recovered. | 03-18-2010 |
20100070686 | METHOD AND DEVICE FOR RECONFIGURATION OF RELIABILITY DATA IN FLASH EEPROM STORAGE PAGES - A data processing system comprises a Flash memory ( | 03-18-2010 |
20100070687 | PROCEDURE FOR ACCESSING A NON-VOLATILE WATCH MEMORY - The invention relates to a procedure for accessing a non-volatile watch memory, the watch comprising two supply terminals accessible from the outside that define a potential difference corresponding to a standard supply voltage, and a control circuit of the non-volatile memory produced using a technology supporting a predefined maximum supply voltage, the access procedure consisting of transmitting the following to the control circuit of the non-volatile memory by means of a supply terminal of the watch: a) an opening key to authorise access to the non-volatile memory; b) an instruction for access to the non-volatile memory; the procedure being characterised in that the opening key is a predefined instruction transmitted by modulation of the standard supply voltage such that this does not exceed the predefined maximum supply voltage. | 03-18-2010 |
20100070688 | FLASH MEMORY DEVICE AND METHOD FOR WRITING DATA THERETO - The invention provides a flash memory device. In one embodiment, the flash memory device is coupled to a host, and comprises a multiple-level-cell (MLC) flash memory and a controller. The MLC flash memory comprises a turbo area and a normal area, wherein the turbo area comprises a plurality of first blocks, the normal area comprises a plurality of second blocks, and each of the first blocks and the second blocks comprises a plurality of pages, wherein the pages of the first blocks and the second blocks are divided into strong pages with high data endurance and weak pages with low data endurance. The controller receives data to be written to the MLC flash memory from the host, determines whether the data is important data, and writes the data to the strong pages of the first blocks of the turbo area when the data is important data. | 03-18-2010 |
20100070689 | HYBRID HARD DISK DRIVE TO RAPIDLY READ FILES HAVING SPECIFIED CONDITIONS, METHOD OF CONTROLLING THE HYBRID HARD DISK DRIVE, AND RECORDING MEDIUM FOR THE HYBRID HARD DISK DRIVE - A method of controlling a hybrid hard disk drive. The method includes receiving a read command from a host; searching metadata of a file to be read; determining whether the metadata satisfies a predetermined setup condition; and if the metadata satisfies the setup conditions, copying the file to be read, from a first storage device and storing the file in a second storage device. | 03-18-2010 |
20100070690 | LOAD REDUCTION DUAL IN-LINE MEMORY MODULE (LRDIMM) AND METHOD FOR PROGRAMMING THE SAME - A load reduction dual in-line memory module (LRDIMM) is similar to a registered dual in-line memory module (RDIMM) in which control signals are synchronously buffered but the LRDIMM includes a load reduction buffer (LRB) in the data path as well. To make an LRDIMM which appears compatible with RDIMMs on a system memory bus, the serial presence detector (SPD) of the LRDIMM is programmed with modified latency support and minimum delay values. When the dynamic read only memory (DRAMs) devices of the LRDIMM are subsequently set up by the host at boot time based on the parameters provided by the SPD, selected latency values are modified on the fly in an enhanced register phase look loop (RPLL) device. This has the effect of compensating for the delay introduced by the LRB without violating DRAM constraints, and provides memory bus timing for a LRDIMM that is indistinguishable from that of a RDIMM. | 03-18-2010 |
20100070691 | Multiprocessor system having multiport semiconductor memory device and nonvolatile memory with shared bus - A multiprocessor system employing a multiport semiconductor memory device and a nonvolatile memory having a shared bus is provided. The multiprocessor system includes a first processor; a second processor; a semiconductor memory device including a shared memory area accessed in common by the first and second processors through different ports and assigned within a memory cell array, and an internal register positioned outside the memory cell array, the internal register being configured to provide an access authority for a shared bus to the first and second processors; and a nonvolatile semiconductor memory device having first and second nonvolatile memory areas coupled corresponding to the first and second processors through the shared bus, the first and second nonvolatile memory areas being accessed by and corresponding to the first and second processors according to the access authority for the shared bus. | 03-18-2010 |
20100070692 | MULTI-BIT-PER-CELL FLASH MEMORY DEVICE WITH NON-BIJECTIVE MAPPING - To store a plurality of input bits, the bits are mapped to a corresponding programmed state of one or more memory cells and the cell(s) is/are programmed to that corresponding programmed state. The mapping may be many-to-one or may be an “into” generalized Gray mapping. The cell(s) is/are read to provide a read state value that is transformed into a plurality of output bits, for example by maximum likelihood decoding or by mapping the read state value into a plurality of soft bits and then decoding the soft bits. | 03-18-2010 |
20100070693 | INITIALIZATION OF FLASH STORAGE VIA AN EMBEDDED CONTROLLER - A digital system including flash memory, coupled to a system-on-a-chip within which a flash memory subsystem controller is embedded, is disclosed. The system-on-a-chip includes support for a standard external interface, such as a Universal Serial Bus (USB) or IEEE 1394 interface, to which a host system such as flash memory test equipment can connect. Initialization of the flash memory is effected by opening a communications channel between the host system and the embedded flash memory subsystem controller. The host system can then effect initialization of the flash memory subsystem, including formatting of the flash memory arrays, loading application programs, and the like, over the communications channel. | 03-18-2010 |
20100077131 | UPDATING CONTROL INFORMATION IN NON-VOLATILE MEMORY TO CONTROL SELECTION OF CONTENT - To control selection of content in a non-volatile memory, control information is stored in the non-volatile memory, where the control information is to control selection of content in the non-volatile memory. An algorithm is used to update the control information in the non-volatile memory to cause different content in the non-volatile memory to be selected, wherein the algorithm sets the control information to an initial value that enhances use of programming of the non-volatile memory to update the control information, and reduces use of erasing of the non-volatile memory to update control information. | 03-25-2010 |
20100077132 | MEMORY DEVICES AND ACCESS METHODS THEREOF - Methods and devices capable of erasing a flash memory evenly are provided, in which a flash memory comprises a data region with a plurality of data blocks and a spare region with a plurality of spare blocks, and a controller retrieves a corresponding data with a check code from a first data block of the flash memory according to a read command from a host, performs a predetermined check to the corresponding data by the check code, determines whether an error is correctable when a check result of the predetermined check represents that the error has occurred, and increases an erase count of the first data block by a predetermined value when the error is correctable. | 03-25-2010 |
20100077133 | Flash Memory Integrated Circuit with Compression/Decompression CODEC - Provided is a flash memory integrated circuit with a compression codec. The flash memory integrated circuit may simultaneously include a memory block and a compression codec circuit. The compression codec circuit may compress input data. A controller circuit may store the compressed input data in at least one page that is included in the memory block. Through this, it is possible to enhance a usage efficiency of a flash memory. | 03-25-2010 |
20100077134 | FLASH DEVICE AND METHOD FOR IMPROVING PERFORMANCE OF FLASH DEVICE - The invention provides a flash device. In one embodiment, the flash device comprises a first NAND flash integrated circuit, a second NAND flash integrated circuit, and a control integrated circuit. The control integrated circuit generates a plurality of first access signals with first timings to access the first NAND flash IC, and generates a plurality of second access signals with second timings to access the second NAND flash IC, wherein the first timings are different from the second timings. The first NAND flash integrated circuit then accesses data stored therein according to the first access signals. The second NAND flash integrated circuit then accesses data stored therein according to the second access signals. | 03-25-2010 |
20100077135 | MEMORY WEAR LEVELING METHOD, SYSTEM AND DEVICE - A wear leveling method for a non-volatile memory is provided. The non-volatile memory includes a plurality of data blocks, each corresponding to a time value. The data blocks are arranged according to a sequence of the time values corresponding thereto. The arranged blocks form a key table. An erase operation is determined whether to be executed for the data blocks. When the erase operation is executed for the data blocks, the corresponding data block is erased according to a sequence of the time values of the data blocks in the key table. | 03-25-2010 |
20100077136 | Memory System Supporting Nonvolatile Physical Memory - A memory system includes nonvolatile physical memory, such as flash memory, that exhibits a wear mechanism asymmetrically associated with write operations. A relatively small cache of volatile memory reduces the number of writes, and wear-leveling memory access methods distribute writes evenly over the nonvolatile memory. | 03-25-2010 |
20100077137 | METHOD FOR CATALOGING AND STORING DATA IN A CONTROL SYSTEM - A method includes receiving a data input file, the data input file defining a first set of data fields to be included in a database and including a set of data elements to be included in the database. The method also includes identifying a second set of data fields in the data input file that are designated to contain a Boolean element, said second set of data fields being a subset of the first set of data fields. The method further includes defining at least one new data field, each new data field collectively storing a plurality of the Boolean elements. The first set of data fields are modified to eliminate the second set of data fields. The method also includes storing in a catalog data that defines an arrangement of the first set of data fields, wherein the arrangement includes the at least one new data field for collectively storing the Boolean elements. | 03-25-2010 |
20100082878 | MEMORY CONTROLLER, NONVOLATILE STORAGE DEVICE, NONVOLATILE STORAGE SYSTEM, AND DATA WRITING METHOD - Used is a nonvolatile memory such as a multi-level NAND flash memory having memory cells for holding data of a plurality of pages. When the data is to be written in the nonvolatile memory | 04-01-2010 |
20100082879 | PRIORITY COMMAND QUEUES FOR LOW LATENCY SOLID STATE DRIVES - A method, apparatus, and system of a priority command queues for low latency solid state drives are disclosed. In one embodiment, a system of a storage system includes a command sorter to determine a target storage device for at least one of a solid state drive (SSD) command and a hard disk drive (HDD) command and to place the command in a SSD ready queue if the SSD command is targeted to a SSD storage device of the storage system and to place the HDD command to a HDD ready queue if the HDD command is targeted to an HDD storage device of the storage system, a SSD ready queue to queue the SSD command targeted to the SSD storage device, and a HDD ready queue to queue the HDD command targeted to the HDD storage device. | 04-01-2010 |
20100082880 | PRE-CODE DEVICE, AND PRE-CODE SYSTEM AND PRE-CODING METHOD THEREROF - A pre-code device includes firstly memory circuit, an address decoder, and an alternative logic circuit. The first memory circuit includes a number of memory blocks and at east a replacing block. The memory blocks are pointed by a number of respective physical addresses. The replacing block is pointed by a replacing address. The address decoder decodes an input address to provide a pre-code address. The alternative logic circuit looks up an address mapping table, which maps defect physical address among the physical addresses to the replacing address, to map the pre-code address to the replacing address when the pre-code address corresponds to the defect physical address. The alternative logic circuit correspondingly pre-codes the pre-code data to the replacing block. | 04-01-2010 |
20100082881 | SOLID STATE STORAGE DEVICE CONTROLLER WITH EXPANSION MODE - Solid state storage device controllers, solid state storage devices, and methods for operation of solid state storage device controllers are disclosed. In one such solid state storage device, the controller can operate in either an expansion DRAM mode or a non-volatile memory mode. In the DRAM expansion mode, one or more of the memory communication channels normally used to communicate with non-volatile memory devices is used to communicate with an expansion DRAM device. | 04-01-2010 |
20100082882 | SEMICONDUCTOR DISK DEVICES AND RELATED METHODS OF RANDOMLY ACCESSING DATA - A computing system includes a host, a data source device, and a controller. The controller is configured to respond to a random access command from the host by setting information in a register that selects what data is to be accessed in the data source device. The controller then successively accesses the data in the data source device using the information that was set in the register. | 04-01-2010 |
20100082883 | Hybrid density memory system and control method thereof - A control method of a memory system for accessing an updated data between a host and the memory system is provided. The host has storage space which is divided into a plurality of logical segments to access the data. The system includes a high density memory and a low density memory, and the high density memory includes a plurality of physical segments to access the data. The control method includes the following steps: first, providing a LDM table in the memory system to indicate the allocation information of the low density memory; finally, deciding where the data is written to is according to its properties and the LDM table. | 04-01-2010 |
20100082884 | MEMORY CELL OPERATION - The present disclosure includes memory devices and systems having memory cells, as well as methods for operating the memory cells. One or more methods for operating memory cells includes determining age information for a portion of the memory cells and communicating a command set for the portion of the memory cells, the command set including the age information. | 04-01-2010 |
20100082885 | METHOD AND SYSTEM FOR ADAPTIVE CODING IN FLASH MEMORIES - Bits are stored by attempting to set parameter value(s) of (a) cell(s) to represent some of the bits. In accordance with the attempt, an adaptive mapping of the bits to value ranges is provided and the value(s) is/are adjusted accordingly as needed. Or, to store (a) bit(s) in (a) cell(s), a default mapping of the bit(s) to a predetermined set of value ranges is provided and an attempt is made to set the cell value(s) accordingly. If, for one of the cells, the attempt sets the value such that the desired range is inaccessible, an adaptive mapping is provided such that the desired range is accessible. Or, to store (a) bit(s) in (a) cell(s), several mappings of the bit(s) to a predetermined set of ranges is provided. Responsive to an attempt to set the cell value(s) according to one of the mappings, the mapping to actually use is selected. | 04-01-2010 |
20100082886 | VARIABLE SPACE PAGE MAPPING METHOD AND APPARATUS FOR FLASH MEMORY DEVICE - Disclosed is a method and apparatus embodying a flash translation layer (FTL) in a storage device including a flash memory. The FTL may classify a block into a sequential group and a fusion group based on a locality of a write request. The FTL may store data in blocks of the fusion group by using a page mapping scheme, and sequentially store data by using a block mapping scheme. The FTL may improve efficiency of garbage collection operation that is performed by using limited redundant blocks and also may increase efficiency of a non-sequential reference operation. | 04-01-2010 |
20100082887 | MEMORY CONTROLLER, FLASH MEMORY SYSTEM WITH MEMORY CONTROLLER, AND METHOD OF CONTROLLING FLASH MEMORY - The memory controller forms temporary virtual blocks each composed of a plurality of physical blocks, whose physical addresses are the same value, each of which is included in each of flash memories, extracts temporary virtual block to which at least one defective block belongs from the temporary virtual blocks, generates a second temporary virtual block to which a defective block does not belong by replacing a defective block belonging to one temporary virtual block with a normal block belonging to another temporary virtual block among temporary virtual blocks extracted, and allocates temporary virtual blocks not extracted and second temporary virtual blocks generated to available virtual blocks. | 04-01-2010 |
20100082888 | Memory controller, flash memory system with memory controller, and method of controlling flash memory - In a case where at least one of physical blocks composing the virtual block becomes a defective block, use of the virtual block to which the defective block belongs is forbidden and the virtual block of which use is forbidden is managed as a defective virtual block. Replacing the defective block with a normal block is performed among the defective virtual blocks so as to generate the virtual block to which the defective block does not belong. Then use of the virtual block generated is allowed. | 04-01-2010 |
20100082889 | Memory controller, flash memory system with memory controller, and method of controlling flash memory - First operations and second operations are performed in parallel. The first operations are operations to write first data to a first unit area which is any one of unit areas. The second operations are operations to read second data corresponding to the same logical page as first data from one or more flash memories and write the second data to a second unit area which is any one of the unit areas and different from the first unit area. Data transfer is performed between the first unit area and the second unit area so as to form data composed of the first data and a portion of the second data which is not replaced with the first data. | 04-01-2010 |
20100082890 | Method of managing a solid state drive, associated systems and implementations - A solid state drive may include one or more memory cell arrays divided into a plurality of blocks. A first portion of the blocks may be designated for storing user data and a second portion of the blocks may be designated as reserved blocks for replacing defective blocks in the first portion. In one embodiment, the method includes reformatting, by a memory controller, the solid state drive to convert one or more blocks in the first portion into reserved blocks. | 04-01-2010 |
20100082891 | APPARATUS AND METHODS FOR COMMUNICATING WITH PROGRAMMABLE DEVICES - A circuit arrangement includes a programmable logic device. The programmable logic device includes configuration logic circuitry. The programmable logic device also includes configurable interconnects. The circuit arrangement further includes a storage device configured to provide data to the programmable logic device. The storage device communicates with the programmable logic device via a bi-directional interface. | 04-01-2010 |
20100082892 | Flash Memory Controller For Electronic Data Flash Card - An electronic data flash card is accessible by a host computer, and includes a processing unit connected to a flash memory device that stores a data file, and an input— output interface circuit activated so as to establish a communication with the host computer. In an embodiment, the electronic data flash card uses a USB input/output interface circuit for communication with the host computer. A flash memory controller includes an index for converting logical addresses sent by the host computer into physical addresses associated with sectors of the flash memory device. The index is controlled by arbitration logic referencing to values from various look up tables and valid data stored in the flash memory device. The flash memory controller further includes a first-in-first-out unit (FIFO) for recycling obsolete sectors of the flash memory device in the background process so that they are available for reprogramming. | 04-01-2010 |
20100082893 | Flash Memory Controller For Electronic Data Flash Card - An electronic data flash card is accessible by a host computer, and includes a processing unit connected to a flash memory device that stores a data file, and an input-output interface circuit activated so as to establish a communication with the host computer. In an embodiment, the electronic data flash card uses a USB input/output interface circuit for communication with the host computer. A flash memory controller includes an index for converting logical addresses sent by the host computer into physical addresses associated with sectors of the flash memory device. The index is controlled by arbitration logic referencing to values from various look up tables and valid data stored in the flash memory device. The flash memory controller further includes a first-in-first-out unit (FIFO) for recycling obsolete sectors of the flash memory device in the background process so that they are available for reprogramming. | 04-01-2010 |
20100088458 | OPERATION METHOD OF MEMORY - An operation method of a memory includes the steps of calculating an offset of sequential write commands and the beginning of pages of a block of a non-volatile memory; shifting the block by the offset; and directly writing data from a host to the pages except the first and last pages of the block by the sequential write commands. In an embodiment, the pages are logical pages providing optimal writing efficiency and are determined before calculating the offset. The step of shifting the block by the offset is to increase corresponding logical block addresses (LBA) in the pages by the offset. | 04-08-2010 |
20100088459 | Improved Hybrid Drive - A non-volatile storage system comprises a hard disk drive (HDD) having a first capacity for storing information therein in a plurality of blocks. The storage system also comprises a non-volatile solid state memory (SSD) having a second capacity, less than the first capacity, for storing information therein. Finally, the storage system comprises a controller having a volatile memory and for controlling the read operation of the HDD and the read/write operation of the SSD. The controller stores in the volatile memory the address of read blocks from the HDD in a first period of time and determines a plurality of the most frequently read blocks in the first period of time, The controller then causes the SSD to store information from the most frequently read blocks from the HDD, and thereafter causes information to be read from the SSD when the storage system is requested to access information from the most frequently read blocks. The controller resets the identity of the most frequently read blocks in the volatile memory after a second period of time, where the second period of time is longer than said first period of time. | 04-08-2010 |
20100088460 | MEMORY APPARATUS, SYSTEMS, AND METHODS - Memory requests for information from a processor are received in an interface device, and the interface device is coupled to a stack including two or more memory devices. The interface device is operated to select a memory device from a number of memory devices including the stack, and to retrieve some or all of the information from the selected memory device for the processor. Additional apparatus, systems and methods are disclosed. | 04-08-2010 |
20100088461 | SOLID STATE STORAGE SYSTEM USING GLOBAL WEAR LEVELING AND METHOD OF CONTROLLING THE SOLID STATE STORAGE SYSTEM - A solid state storage system is disclosed including a memory area having a plurality of chips. The solid state storage system includes a micro controller unit (MCU) configured to utilize the number of deletions for logical blocks corresponding to logical block addresses when performing wear leveling on the memory area. The allocation of the logical block addresses can be performed using an interleaving process and a multi-plane method. The solid state storage system performs global wear leveling by which the lifespan of the cells of the chips can be uniformly managed. | 04-08-2010 |
20100088462 | METHODS FOR HANDLING DATA UPDATING OF FLASH MEMORY AND RELATED MEMORY CARDS - A method for handling data updating of a flash memory is disclosed, in which the flash memory comprises a mother block with a plurality of pages to be updated, and each page comprises a plurality of sectors. In such method, a first data for updating a target page in the mother block is obtained, and then whether the first data comprises data for updating an ending sector in the target page is determined. The first data is written into a replacing page in a first FAT block when the first data does not comprise data for updating the ending sector in the target page. The first data is written into a corresponding page in a second FAT block when the first data comprises the data for updating the ending sector, in which the corresponding page in the second FAT block and the target page in the mother block have the same page indexes. | 04-08-2010 |
20100088463 | NONVOLATILE MEMORY SYSTEM AND DATA PROCESSING METHOD - A solid-state disk device exchanging data with a host includes a nonvolatile memory device, a buffer memory configured to temporarily store data exchanged between the host and the nonvolatile memory, and a buffer manager configured to control transfer of data to/from the buffer memory, wherein the transfer of data between the nonvolatile memory device and the host during a streaming mode of operation begins immediately when a defined unit data is input to the buffer memory. | 04-08-2010 |
20100088464 | Compression Based Wear Leveling for Non-Volatile Memory - The present disclosure includes systems and techniques relating to non-volatile memory. Systems and techniques can include obtaining information to store in a non-volatile memory, the information including a data segment, compressing data within the data segment, including pad data in one or more portions of the data segment based on a compression result attained by the compression, and writing data of the data segment. | 04-08-2010 |
20100088465 | CONTROL DEVICE OF A STORAGE SYSTEM COMPRISING STORAGE DEVICES OF A PLURALITY OF TYPES - A control device of a storage system including a CPU which receives input information including at least a size and an archive deadline of data which is stored in storage devices; wherein data management information includes a write threshold value regarding one type of storage devices, the write threshold value indicating a write limit number to the one type of storage devices, wherein the CPU: selects a storage device which stores data corresponding to the information which is input to an input device, based on the information which is input to the input device and the data management information which is stored in the memory; CPU stores to the selected storage device, the data corresponding to the information which is input to the input device; and, registers to the data management information in the memory, at least one of the information which is input to the input device. | 04-08-2010 |
20100088466 | STORAGE DEVICE, STORAGE CONTROL DEVICE, AND CONTROL METHOD - According to one embodiment, a storage device includes an actuator to move a head to a position on a disk medium; a module to record or reproduce data to or from the disk medium using the head; a memory controller to write or read to or from a non-volatile memory; a buffer controller to write or read to or from a buffer memory; an interface controller to transmit and receive to or from an upper device; a switching module to switch data transfer paths among the module, the memory controller, and the interface controller; and an access controller to control the switching module to transfer data read from the non-volatile memory to the upper device concurrently with transferring and storing the read data in a cache region of the buffer memory, upon receiving from the upper device a command to read the data from the non-volatile memory. | 04-08-2010 |
20100095048 | SELF-CONTAINED DENSELY PACKED SOLID-STATE STORAGE SUBSYSTEM - A rack mountable solid-state storage subsystem includes a plurality of interface units and a plurality of data storage modules to implement a mass storage device. Each of the interface units may be coupled to a plurality of communication ports for connection to a host server and to other interface units. Each data storage module may be detachably mated to a corresponding connector mounted to a motherboard. Each data storage module may also include a non-volatile flash memory storage and a volatile storage. The data storage modules may be partitioned into a plurality of portions, each coupled to a respective interface unit via the motherboard. Each portion of the data storage modules and the respective interface unit to which each portion is coupled may form a separate storage domain that is isolated from each other domain. The storage subsystem may also include redundant power supplies and backup power supplies. | 04-15-2010 |
20100095049 | HOT MEMORY BLOCK TABLE IN A SOLID STATE STORAGE DEVICE - Solid state storage devices and methods for populating a hot memory block look-up table (HBLT) are disclosed. In one such method, an indication to an accessed page table or memory map of a non-volatile memory block is stored in the HBLT. If the page table or memory map is already present in the HBLT, the priority location of the page table or memory map is increased to the next priority location. If the page table or memory map is not already stored in the HBLT, the page table or memory map is stored in the HBLT at some priority location, such as the mid-point, and the priority location is incremented with each subsequent access to that page table or memory map. | 04-15-2010 |
20100095050 | COMPUTER MEMORY DEVICE WITH STATUS REGISTER - Method and apparatus for operating a memory device with a status register. In some embodiments, the memory device has a plurality of individually programmable non-volatile memory cells comprised of at least a resistive sense memory. The memory device engages an interface and maintains a status register in some embodiments by logging at least an error or busy signal during data transfer operations. | 04-15-2010 |
20100095051 | Memory system and a control method thereof - A control method for the memory system is suitable for a memory system to process the user data from a host. The control unit divides the address of the storage space of the host into a plurality of logical segments for accessing data. The memory system provides a storage space with a plurality of physical segments to access data. The control method comprises the following steps. Firstly, a master table is provided in the physical memory for recording the mapping relation between the addresses of the logical units and the addresses of the physical units. When the data is written, the mapping relation between the addresses of the logical units and the addresses of the physical units is adjusted according to the wear of the physical units. Finally, the data is written into the physical segment according to the master table. | 04-15-2010 |
20100095052 | DATA UPDATING IN NON-VOLATILE MEMORY - Various embodiments of the present invention are generally directed to an apparatus and associated method for updating data in a non-volatile memory array. In accordance with some embodiments, a memory block is formed with a plurality of types of memory cell sectors arranged in data pages of a first type and log pages of a second type that can be updated in-place. A first updated sector is written to a first log page while maintaining an outdated sector in an original data page, and overwritten with a second updated sector. | 04-15-2010 |
20100095053 | HYBRID MULTI-TIERED CACHING STORAGE SYSTEM - A hybrid storage system comprising mechanical disk drive means, flash memory means, SDRAM memory means, and SRAM memory means is described. IO processor means and DMA controller means are devised to eliminate host intervention. Multi-tiered caching system and novel data structure for mapping logical address to physical address results in a configurable and scalable high performance computer data storage solution. | 04-15-2010 |
20100095054 | Memory controller, flash memory system with memory controller, and method of controlling flash memory - The memory controller comprises a data holding unit which is composed of plural unit areas each for holding data corresponding to one logical page among logical pages each composed of plural logical sectors each assigned a logical address provided from a host system. The memory controller writes data held in a unit area which holds large amounts of write data, to the flash memories, in preference to data held in a unit area which holds small amounts of write data. | 04-15-2010 |
20100095055 | MEMORY SYSTEM FOR DATA STORAGE AND RETRIEVAL - According to a first aspect of an embodiment of the invention, there is provided a method of data storage and retrieval for use in a solid state memory system, having a non-volatile memory, wherein data is written to the non-volatile memory in the form of at least one logical sector the method comprising: monitoring the logical sector data which is to be written to the non-volatile memory, detecting the presence of a pattern in the logical sector data, upon detecting a repetitive pattern recording the repetitive pattern of the logical sector in a sector address table in the non-volatile memory without making a record of the logical sector data in the nonvolatile memory. | 04-15-2010 |
20100100663 | Method of Performing Wear Leveling with Variable Threshold - A wear leveling limit and/or an overall erase count threshold used for activating wear leveling in a non-volatile memory may be adjusted by determining a stage according to a highest erase count, and determining the wear leveling limit and/or the overall erase count threshold corresponding to the stage. Wear leveling may then be performed according to the wear leveling limit and/or the overall erase count threshold. | 04-22-2010 |
20100100664 | STORAGE SYSTEM - Increase in read-access response time is avoided in a RAID storage system loaded with SSD. A process or is configured such that the processor sets SSD to a write-enable state, and sets different SSD, from which the same data can be acquired, to a write-disable state; allows predetermined data in CM to be written into the SSD in the write-enable state; receives a read request of data from a host computer; acquires object data of the read request from the different SSD in the case that a storage location of the data is the SSD being set to the write-enable state and transmits the acquired data to the host computer. | 04-22-2010 |
20100100665 | DATA UPDATE METHOD AND FLASH MEMORY APPARATUS UTILIZING THE SAME - The invention discloses a flash memory apparatus, including a plurality of blocks and a memory controller. The blocks include a first block, wherein the first block includes a first page. The memory controller receives a first data to be written into the first page of the first block. When the first page has already been written to, the memory controller further selects one of the blocks as a first cache block, writes the first data into a first cache page of the first cache block and records the number of the first block and the number of the first page into the first cache page. The memory controller further updates the first block according to the number of the first block and the number of the first page recorded in the first cache page when receiving an update command. | 04-22-2010 |
20100100666 | SYSTEM AND METHOD FOR CONTROLLING FLASH MEMORY USING DESCRIPTOR ARRAY - Disclosed are a system and method for controlling a flash memory using a descriptor array, which may maximize a performance of a flash memory based-storage system. The system includes a descriptor array receipt unit for receiving, from a processor, a descriptor array including, at least one descriptor corresponding to at least one operation; and a flash memory control unit for verifying the descriptor included in the descriptor array and executing a flash memory control command included in the verified descriptor, wherein the flash memory control unit executes the flash memory control command independent from the operation of the processor. | 04-22-2010 |
20100100667 | Flash memory system and designing method of flash translation layer thereof - The method of designing a flash translation layer includes receiving a logical address according to an external request and mapping a physical address that corresponds to the logical address. The mapping manages continuous logical addresses and physical addresses corresponding to the logical addresses as one mapping unit. | 04-22-2010 |
20100100668 | CONTROL METHOD FOR LOGICAL STRIPS BASED ON MULTI-CHANNEL SOLID-STATE NON-VOLATILE STORAGE DEVICE - A control method for logical strips based on a multi-channel solid-state non-volatile storage device is provided. The method includes the following processing steps. In Step 1, a storage space of every channel is partitioned into a plurality of storage units of equal size. In Step 2, at least one logical strip is set by which the storage units with discrete physical addresses across a plurality of channels are organized into a continuous logical space. In Step 3, during data reading/writing operation, the data is divided according to a size of each local strip, the divided data is mapped to the storage units of every channel, and a parallel reading/writing operation is performed across the channels. This method may increase the efficiency of reading and writing operations of the storage device and prolong the operating life span of the device. | 04-22-2010 |
20100100669 | SELF-ADAPTIVE CONTROL METHOD FOR LOGICAL STRIPS BASED ON MULTI-CHANNEL SOLID-STATE NON-VOLATILE STORAGE DEVICE - A self-adaptive control method for logical strips based on a multi-channel solid-state non-volatile storage device is provided. The method includes the following steps. Storage space of every channel is divided into a plurality of storage units of equal size. At least one logical strip is set by which the storage units with discrete physical addresses across the channels are organized into a continuous logical space, and a logical strip variable is set for determining the storage units organized by the logical strip. Historical operation information of the storage device is obtained statistically, and the logical strip variable is dynamically adjusted according to the obtained operation information. During data interaction, the data is divided according to the logical strip variable, the divided data is mapped to the storage units of every channel, and parallel reading and writing operations are performed among the channels. | 04-22-2010 |
20100106887 | FLASH PRESENTATION (FLAPRE) AUTHORING TOOL THAT CREATES FLASH PRESENTATIONS INDEPENDENT OF A FLASH SPECIFICATION - A system for authoring a FLASH presentation can include a FLASH-based FLASH presentation (FLAPRE) authoring tool and a launching application. The FLAPRE authoring tool can be configured to create a specialized FLAPRE code file containing a user-created FLASH presentation. The specialized FLAPRE code file can be created without the use of a FLASH specification. The launching application can be configured to present the FLASH-based FLAPRE authoring tool. The launching application can also support the use of FLASH animation. | 04-29-2010 |
20100106888 | Method and System For Device Independence In Storage Device Wear Algorithms - A device, methods and systems that provide device independence in storage device wear algorithms are disclosed. A storage device that provides such device independence includes a device-specific wear algorithm, and may also include an integrated wear algorithm. The device-specific wear algorithm is configured to be loaded into a wear algorithm space and is at least a portion of a wear algorithm. The device-specific wear algorithm is stored in the storage device. The integrated wear algorithm, if employed, is resident in the storage device. A method that provides such device independence is also disclosed. The method includes loading a device-specific wear algorithm from a storage device into a wear algorithm space. The device-specific wear algorithm is configured to be stored in the storage device and loaded into the wear algorithm space. The device-specific wear algorithm is at least a portion of a wear algorithm. | 04-29-2010 |
20100106889 | SOLID STATE DRIVE OPERATION - The present disclosure includes methods and devices for operating a solid state drive. One method embodiment includes mirroring programming operations such that data associated with a programming operation is programmed to two or more locations in memory of the solid state drive. The method also includes ceasing to mirror programming operations upon an occurrence of a particular event. | 04-29-2010 |
20100106890 | METHOD AND APPARATUS FOR ENFORCING A FLASH MEMORY CACHING POLICY - Methods, apparatus and computer medium for enforcing one or more cache management policies are disclosed herein. In some embodiments, a flash memory of a storage device includes a plurality of flash memory dies each flash memory die including a respective cache storage area and a respective main storage area. A determination is made, for data that is received from an external host device to which main storage area the received data is addressed thereby specifying one of the plurality of flash memory dies as a target die for the received data. Whenever the received data is written into a cache storage area before being written into a main storage area, the received data is written into the cache storage area of the specified target die. | 04-29-2010 |
20100106891 | Preventing Unintended Permanent Write-Protection - An input voltage range may be established between different voltage levels used for different programming functions of an integrated circuit device, thus implementing a protection zone (“safe zone”) of non-operation to facilitate prevention of an unintended irreversible programming operation, e.g., permanent write protection. | 04-29-2010 |
20100106892 | Access Methods For Memory Devices And Memory Devices Thereof - An access method for use in a memory device is provided. The memory device comprises a data area having a plurality of data blocks and a spare area having a plurality of spare blocks. First, data from a host is received. A spare block is popped from the spare area and the received data is programmed into the popped spare block accordingly. A data block corresponding to the data is pushed to the spare area. The pushed data block is erased when the memory device is waiting for a specific instruction to be issued from the host. | 04-29-2010 |
20100106893 | PAGE BUFFER PROGRAM COMMAND AND METHODS TO REPROGRAM PAGES WITHOUT RE-INPUTTING DATA TO A MEMORY DEVICE - A technique for efficiently handling write operation failures in a memory device which communicates with an external host device allows a page of data to be re-written to a memory array from a page buffer. The host provides user data, a first write address and a write command to the memory device. If the write attempt fails, the host provides a re-write command with a new address, without re-sending the user data to the memory device. Additional data can be received at a data cache of the memory device while a re-write from the page buffer is in progress. The re-written data may be obtained in a copy operation in which the data is read out to the host, modified and written back to the memory device. Additional data can be input to the memory device during the copy operation. Page buffer data can also be modified in place. | 04-29-2010 |
20100106894 | Method of storing and accessing error correcting code in NAND Flash - A method of storing and accessing an error correcting code in NAND Flash, includes utilizing n pages of a block of the NAND Flash as an extended space of a spare area, n≦1, wherein when writing data, the data is stored in a data area of a sector, and when the error correcting code needs a space which has correcting capability larger than 16 bytes, first 16 bytes of the error correcting code is stored in the 16 bytes spare area, and the remaining of the error correcting code is stored in the extended space of the spare area corresponding to the sector. Therefore, the method develops new storing space for the error correcting code, arranges the error correcting code in sequence of data blocks in sub-space, and loads the error correcting code into system memory for the decoder before reading original data. | 04-29-2010 |
20100106895 | Hardware and Operating System Support For Persistent Memory On A Memory Bus - Implementations of a file system that is supported by a non-volatile memory that is directly connected to a memory bus, and placed side by side with a dynamic random access memory (DRAM), are described. | 04-29-2010 |
20100106896 | METHOD FOR WRITING AND READING DATA IN AN ELECTRICALLY ERASABLE AND PROGRAMMABLE NONVOLATILE MEMORY - A method for writing and reading data in a main nonvolatile memory having target pages in which data are to be written and read, the method including providing a nonvolatile buffer having an erased area, providing a volatile cache memory, and receiving a write command to update a target page with updating data the length of which can be lower than the length of a page. The method also includes, in response to the write command, writing the updating data into the erased area of the nonvolatile buffer, together with management data of a first type, and recording an updated version of the target page in the cache memory or updating in the cache memory a previously updated version of the target page. | 04-29-2010 |
20100106897 | STORAGE DEVICE, DISK DEVICE, WRITE DETERMINING METHOD, AND CONTROL DEVICE - According to one embodiment, a storage device divides and writes into pages a management information table for managing addresses at which data are written. The storage device includes: a writing module configured to write a duplicate of a last page of the management information table after writing the management information table divided into the pages; an acquiring module configured to acquire the last page and the duplicate of the last page written by the writing module; and a determining module configured to determine whether the writing of the management information table has been successful, by comparing the last page and the duplicate of the last page acquired by the acquiring module with each other, or by checking whether the duplicate of the last page has been written by the writing module. | 04-29-2010 |
20100106898 | STORAGE AND REPRODUCTION APPARATUS - The storage and reproducing apparatus includes a signal processing block, a memory, a reproduction block, an operation block, and a control block. The signal processing block converts a sound signal entered, into a digital signal. The memory stores a digital signal outputted form the signal processing block and a management data of the digital data. The reproduction block at least converts a digital signal read out from the memory, into a hearable sound for reproduction output. The operation block is provided on an apparatus main body and includes a rotary operation block provided on the apparatus main body in such a manner that the rotary operation block can be rotated around a rotation center and shifted along plane which almost orthogonally intersects the rotation center. The control block, according to an input from the operation block, writes a digital signal and a management data into the memory and reads out a digital signal and a management data stored in the memory. The control block, according to a rotation direction of the rotary operation block, reads out a management data from the memory. When the rotary operation block is shifted along the plane, the control block reads out a digital signal from the memory according to a management information which is being read out from the memory. | 04-29-2010 |
20100115175 | Method of managing a large array of non-volatile memories - The present invention provides a non-volatile flash memory management system and method that provides the ability to efficiently manage a large array of flash devices and allocate flash memory use in a way that improves reliability and longevity, while maintaining excellent performance. The invention mainly comprises of a processor, an array of flash memories that are modularly organized, an array of module flash controllers and DRAM caching. The processor manages the above mention large array of flash devices with caching memory through mainly two tables: Virtual Zone Table and Physical Zone Table, a number of queues: Cache Line Queue, Evict Queue, Erase Queue, Free Block Queue, and a number of lists: Spare Block List and Bad Block List. | 05-06-2010 |
20100115176 | DATA TRANSFER AND PROGRAMMING IN A MEMORY DEVICE - Methods for data transfer and/or programming a memory device, memory devices and memory systems are provided. According to at least one such method, additional data is appended to original data and the resulting data is programmed in a selected memory cell. The appended data increases the program threshold voltage margin of the original data. The appended data can be a duplicate of the original data or logical zeros. When the selected memory cell is read, the memory control circuitry can read just the original data in the MSB field or the memory control circuitry can read the entire programmed data and ignore the LSB field, for example. | 05-06-2010 |
20100115177 | DATA STORAGE DEVICES - A data storage device includes a non-volatile memory array, a user input device, and a host interface adapted to connect the data storage device to a host device and convey data to the host device. In response to a first operation of the user input device, application configuration data is communicated from the data storage device to the host device. The application configuration data is configured to trigger execution by the host device of a configuration application that includes a listing of a plurality of applications for display by the host device allowing a user to identify a selected application. In response to selection of an application, application designation data is generated and stored in the non-volatile memory array. In response to a second operation of the user input device, the application designation data is communicated to the host device to trigger automatic execution by the host device of the selected application. | 05-06-2010 |
20100115178 | System and Method for Hierarchical Wear Leveling in Storage Devices - Systems and methods for reducing problems and disadvantages associated with wear leveling in storage devices are disclosed. A method may include maintaining module usage data associated with each of a plurality of storage device modules communicatively coupled to a channel. The method may also include maintaining device usage data associated with each of the plurality of storage devices associated with the storage device module for each of the plurality of storage device modules. The method may additionally include determining a particular storage device module of the plurality of storage device modules to which to store data associated with a write request based at least on the module usage data. The method may further include determining a particular storage device of the particular storage device module to which to store data associated with a write request based at least on the device usage data associated with the particular storage device module. | 05-06-2010 |
20100115179 | MEMORY MODULE INCLUDING VOLTAGE SENSE MONITORING INTERFACE - Memory devices and systems include a voltage sense line for addressing voltage tolerances across variable loadings. The memory devices and systems comprise a memory module connector with a first plurality of pins coupled to circuitry on a memory module, and a second plurality of pins coupled to power rails on the memory module that enable monitoring of the power rails from external to the memory module. | 05-06-2010 |
20100115180 | MEMORY MODULE INCLUDING ENVIRONMENTAL OPTIMIZATION - A memory apparatus enable operation which is adapted to environmental conditions. The memory apparatus includes a memory module that can store and incorporate environment-dependent optimal operating parameters. The memory module comprises a plurality of volatile memory devices and one or more non-volatile memory devices that store a plurality of environment-dependent device parameters for a device selected from the plurality of volatile memory devices. The stored parameters enable the selected device to function optimally in multiple environmental conditions. | 05-06-2010 |
20100115181 | MEMORY DEVICE AND METHOD - A memory device may include a volatile memory and a non-volatile memory which are arranged to be accessed via a common bus. The memory device may include a controller that is arranged as an interface between the common bus and the volatile and non-volatile computer memories, the controller to transmit read/write commands from the common bus to either the volatile memory or the non-volatile memory. | 05-06-2010 |
20100115182 | FLASH MEMORY OPERATION - An embodiment is a technique to improve operations of flash memory devices. A plurality of logical block numbers is mapped to a plurality of physical block numbers using a mapper. The physical block numbers are associated with blocks in a flash memory device. A plurality of block statuses of the plurality of free physical block numbers is stored in a replacement table. Each of the block statuses is one of a ready, dirty, and broken status. A destination block in the blocks is written to. The destination block has the ready status. The mapper and the replacement table are updated. | 05-06-2010 |
20100115183 | Storage Apparatus and Method of Managing Data Storage Area - Disclosed is a storage apparatus that extends endurance and reduces bit cost. A storage apparatus includes a controller and a semiconductor storage media that has a plurality of storage devices. The plurality of storage devices include a first storage device and a second storage device having an upper limit of an erase count of data smaller than that of the first storage device. Area conversion information includes correspondence of a first address to be specified as a data storage destination and a second address of an area in which data is to be stored. A rewrite frequency of stored data is recorded for each area. The controller selects an area corresponding to the first address, determines whether or not the rewrite frequency of the selected area is equal to or larger than a first threshold value, when the rewrite frequency is equal to or larger than the threshold value, selects an area to be provided by the first storage device, and when the rewrite frequency is smaller than the threshold value, selects an area to be provided by the second storage device and maps the address of the selected area to the first address. | 05-06-2010 |
20100115184 | FLASH MEMORY STORAGE SYSTEM AND CONTROLLER AND DATA PROTECTION METHOD THEREOF - A flash memory storage system including a controller and a flash memory chip is provided, wherein the controller is disposed with a rewritable non-volatile memory. When the controller writes a security data into the flash memory chip, the controller randomly generates a data token and generates a message digest according to the security data and the data token by using a one-way hash function, wherein the data token and the message digest are respectively stored in the rewritable non-volatile memory and the flash memory chip. Subsequently, when the controller reads the security data from the flash memory chip, the controller determinates whether the security data is falsified according to the data token and the message digest respectively stored in the rewritable non-volatile memory and the flash memory chip. Thereby, the security data in the flash memory chip can be effectively protected. | 05-06-2010 |
20100115185 | MEMORY CONTROLLER, NONVOLATILE MEMORY DEVICE, ACCESS DEVICE, AND NONVOLATILE MEMORY SYSTEM - Without corresponding to different address spaces between an access device ( | 05-06-2010 |
20100115186 | FLASH MEMORY DEVICE WITH WEAR-LEVELING MECHANISM AND CONTROLLING METHOD THEREOF - A flash memory device with a wear-levelining mechanism includes at least one flash memory, a hot list, a bitmap, a source pointer, and a controller. The controller obtains a physical memory block with high erase count through the hot list, an erase count of the physical memory block, and an overall average erase count of the flash memory device. The controller further finds out a physical memory block which stores static data through managing the bitmap and the source pointer. The controller moves the static data to the physical memory block with high erase count, and releases the physical memory block which stores the static data to avoid the physical memory block with high erase count being worn down increasingly more seriously. | 05-06-2010 |
20100115187 | NON-VOLATILE DATA STORAGE SYSTEM AND METHOD THEREOF - A non-volatile data storage system including a first non-volatile storage medium, a second non-volatile storage medium, and a microprocessor is provided. The first non-volatile storage medium includes a popular data address recording area for recording logic addresses of popular data in the first non-volatile storage medium. The microprocessor is coupled to the first non-volatile storage medium and the second non-volatile storage medium. When the non-volatile data storage system boots up, the microprocessor copies the popular data from the first non-volatile storage medium to the second non-volatile storage medium according to the popular data address recording area. The popular data is accessed in the second non-volatile storage medium instead of the first non-volatile storage medium. | 05-06-2010 |
20100115188 | METHOD FOR MANAGING A MEMORY APPARATUS, AND ASSOCIATED MEMORY APPARATUS THEREOF - A method for managing a memory apparatus including at least one non-volatile (NV) memory element includes: recording usage information of at least one block during accessing pages of the block; and determining whether to erase a portion of the blocks according to the usage information. For example, the usage information includes a valid page count table for recording valid page counts of the blocks, respectively; and the ranking of a field of the valid page count table represents a physical block address, and the content of the field represents an associated valid page count. In another example, the usage information includes an invalid page count table for recording invalid page counts of the blocks, respectively; and the ranking of a field of the invalid page count table represents a physical block address, and the content of the field represents an associated invalid page count. | 05-06-2010 |
20100115189 | METHOD FOR MANAGING A MEMORY APPARATUS, AND ASSOCIATED MEMORY APPARATUS THEREOF - A method for managing a memory apparatus including at least one non-volatile (NV) memory element includes: providing at least one block of the memory apparatus with at least one local page address linking table within the memory apparatus, wherein the local page address linking table comprises linking relationships between physical page addresses and logical page addresses of a plurality of pages; and building a global page address linking table of the memory apparatus according to the local page address linking table. | 05-06-2010 |
20100115190 | SYSTEM AND METHOD FOR PROCESSING READ REQUEST - A system for processing a read request for maximizing host read performance in a flash memory-based storage device is provided. The system for processing the read request solves a bottleneck phenomenon caused by a processor by adding an independent automatic read request processor, different from a conventional system in which a processor of a storage device processes the read request. Also, when processing the read request, a storage device using a write buffer may control a process of merging data of the write buffer and a flash memory and transmitting the data to a host based on a descriptor array, thereby minimizing processor overhead. | 05-06-2010 |
20100115191 | System Including Hierarchical Memory Modules Having Different Types Of Integrated Circuit Memory Devices - A memory system is disclosed comprising a memory controller and a first set of volatile memory devices defining a first memory hierarchy. The first set of volatile memory devices are disposed on at least one first memory module, which is coupled to the memory controller in a daisy-chained configuration. A first integrated circuit buffer device is included on the module. The system has a second set of nonvolatile memory devices defining a second memory hierarchy. The second set of nonvolatile memory devices are disposed on at least one second memory module, which is coupled to the at least one first memory module in a daisy-chained configuration. The second module includes a second integrated circuit buffer device. The system is configured such that signals transmitted between the memory controller and the second memory hierarchy pass through the first memory hierarchy. | 05-06-2010 |
20100115192 | WEAR LEVELING METHOD FOR NON-VOLATILE MEMORY DEVICE HAVING SINGLE AND MULTI LEVEL MEMORY CELL BLOCKS - A method of executing a wear leveling operation within a non-volatile memory including a single-level memory cell block (SLC) and a multi-level memory cell block (MLC) is disclosed. The method includes calculating an average erase point in relation to a number of programming/erase (P/E) operations applied to a logical block address (LBA), a SLC mode usage point in relation to a number of the P/E operations applied to the SLC, a MLC mode usage point in relation to a number of the P/E operations applied to the MLC, and a wear value in relation to the average erase point, the SLC mode usage point, and the MLC mode usage point; and then if the wear value exceeds a defined threshold value, performing the wear leveling operation. | 05-06-2010 |
20100115193 | SYSTEM AND METHOD FOR IMPROVING DATA INTEGRITY AND MEMORY PERFORMANCE USING NON-VOLATILE MEDIA - A system and computer system for improving data integrity and memory performance using non-volatile media. A system includes a non-volatile mass storage unit, e.g., a flash memory device and/or a hard drive unit for instance. A memory device is used as a high speed data buffer and/or cache for the non-volatile storage unit. The memory device may be non-volatile, e.g., magnetic random access memory (MRAM) or volatile memory, e.g., static dynamic random access memory (SDRAM). By buffering and/or caching the write data, fewer accesses are required to the mass storage device thereby increasing system performance. Additionally, mechanical and electrical degradation of the mass storage device is reduced. Certain trigger events can be programmed to cause data from the memory device to be written to the mass storage device. In one embodiment, the write buffer contents are preserved across reset or power loss events. In one embodiment, the mass storage unit may be a data transport layer, e.g., Ethernet, USB, Bluetooth, etc. | 05-06-2010 |
20100115194 | SEMICONDUCTOR MEMORY INFORMATION STORAGE APPARATUS AND METHOD OF CONTROLLING WRITING - A semiconductor memory information storage apparatus includes a storage unit using a nonvolatile memory, a write number manager counting each of numbers of times of writing of all blocks, a list manager classifying the blocks in the nonvolatile memory by in-use/unused, managing in an in-use list a block of the in-use, managing in a first unused list a block with the number of times of writing equal to a maximum value, and managing in a second unused list a block with the number of times of writing less than the maximum value, and a controller writing and erasing information data to and from the storage unit. | 05-06-2010 |
20100122014 | Method For Protecting Memory Proprietary Commands - A method for protecting memory proprietary command is provided. By using the logic block area (LBA) address in the header of the LBA mode, the device end can determine whether the data sector in the LBA mode includes a proprietary command. Also, by using the pre-defined computation function to establish a relation among the values stored in a plurality of characteristic point addresses and a specific point address so that he device end can determine whether a proprietary command is received. As the operating system will not filter out the proprietary command wrapped in this manner, the proprietary command can pass the operating system and be executed by the device end. | 05-13-2010 |
20100122015 | SOFTWARE ADAPTED WEAR LEVELING - A subset of software objects stored in a first segment of non-volatile memory are identified as requiring frequent write operations or otherwise associated with a high endurance requirement. The subset of software objects are move to a second segment of non-volatile memory with a high endurance capacity, due to the application of wear leveling techniques to the second segment of non-volatile memory. The first and second segments of memory can be located in the same memory device or different memory devices. | 05-13-2010 |
20100122016 | DYNAMIC SLC/MLC BLOCKS ALLOCATIONS FOR NON-VOLATILE MEMORY - Apparatus and methods are disclosed, such as those that provide dynamic block allocations in NAND flash memory between single-level cells (SLC) and multi-level cells (MLC) based on characteristics. In one embodiment, a memory controller dynamically switches between programming and/or reprogramming blocks between SLC mode and MLC mode based on the amount of memory available for use. When memory usage is low, SLC mode is used. When memory usage is high, MLC mode is used. Dynamic block allocation allows a memory controller to obtain the performance and reliability benefits of SLC mode while retaining the space saving benefits of MLC mode. | 05-13-2010 |
20100122017 | MEMORY CONTROLLER, NON-VOLATILE MEMORY SYSTEM, AND HOST DEVICE - Provided is a nonvolatile memory system which can be used for a boot program storage and easily controlled by a host device. At the time of reading a boot code | 05-13-2010 |
20100122018 | BACKUP METHOD, BACKUP DEVICE, AND VEHICLE CONTROLLER - A backup method includes the following processes. Backup data is temporarily stored in a volatile memory. An erased area is saved in a flash memory for the backup data. The erased area is free of data. The backup data is written in the erased area. | 05-13-2010 |
20100122019 | APPARATUS, SYSTEM, AND METHOD FOR MANAGING PHYSICAL REGIONS IN A SOLID-STATE STORAGE DEVICE - An apparatus, system, and method are disclosed for managing physical regions in a solid-state storage device. The definition module defines a physical storage region on solid-state storage media of a solid-state storage device. The physical storage region includes a subset of total physical storage capacity on the solid-state storage media. The storage controller performs memory operations within the physical storage region such that the memory operations are bounded to the physical storage region. The implementation module implements the physical storage region definition with respect to the storage controller for the solid-state storage media. | 05-13-2010 |
20100122020 | DYNAMIC PERFORMANCE VIRTUALIZATION FOR DISK ACCESS - A storage control system includes performance monitor logic configured to track performance parameters for different volumes in a storage array. Service level enforcement logic is configured to assign target performance parameters to the different volumes and generate metrics for each of the different volumes identifying how much the performance parameters change for the different volumes responsive to changes in the amounts of tiering media allocated to the different volumes. Resource allocation logic is configured to allocate the tiering media to the different volumes according to the performance parameters, target performance parameters, and metrics for the different volumes. | 05-13-2010 |
20100122021 | USB-Attached-SCSI Flash-Memory System with Additional Command, Status, and Control Pipes to a Smart-Storage Switch - An electronic flash-memory card has additional pipes for commands and status messages so that data pipes are not clogged with commands and status messages, allowing for a higher data throughput. The command and status pipes are activated when a UAS/BOT detector detects that a host is using a USB-Attached-SCSI (UAS) mode rather than a Bulk-Only-Transfer (BOT) mode. The host can send additional commands and data without waiting for completion of a prior command when operating in UAS mode but not while operating in BOT mode. A command queue (CQ) in the device re-orders commands for accessing flash memory and merges data in a RAM buffer. Smaller 1 KB USB packets in the data pipes are merged into larger 8 KB payloads in the RAM buffer, allowing for more efficient flash access. | 05-13-2010 |
20100122022 | SSD WITH IMPROVED BAD BLOCK MANAGMENT - In some embodiments, a memory controller includes a plurality of processors of a first type and a processor of a second type coupled to the processors of the first type. Each of the plurality of processors of the first type is configured to determine a bad block rate of a memory channel of a solid state memory device to which it is configured to be coupled. The processor of the second type is configured to receive the bad block data rates from each of the plurality of processors of the first type and to report one of a total capacity or a bad block rate of the solid state memory device to a host device. The total capacity and the bad block rate of the solid state memory device are based on the bad block rates received from each of the plurality of processors of the first type. | 05-13-2010 |
20100125695 | NON-VOLATILE MEMORY STORAGE SYSTEM - The present invention discloses a flash memory storage system, comprising at least one RAID controller; a plurality of flash memory cards electrically connected with the RAID controller; and a cache memory electrically connected with the RAID controller and shared by the RAID controller and the flash memory cards. The cache memory efficiently enhances the system performance. The storage system may comprise more RAID controllers to construct a nested RAID architecture. | 05-20-2010 |
20100125696 | Memory Controller For Controlling The Wear In A Non-volatile Memory Device And A Method Of Operation Therefor - A memory controller controls the operation of a non-volatile memory device. The memory device has a data storage section and an erased storage section. The data storage section has a first plurality of blocks and the erased storage section has a second plurality of blocks. Each of the first and second plurality of blocks has a plurality of non-volatile memory bits that are erased together. Further, each block has an associated counter for storing the number of times the block has been erased. The memory controller has program instructions which are to scan the counters associated with the blocks of the first plurality of blocks based upon the count contained in each of the counters associated therewith to select a third block, and to scan the counters associated with the blocks of the second plurality of blocks based upon the count contained in each of the counters associated therewith to select a fourth block. The program instructions are further configured to transfer data from the third block to the fourth block, and associating said fourth block with said first plurality of blocks. Finally the program instructions are configured to erase said third block and incrementing the counter associated with said third block, and associating said third block with said second plurality of blocks. The present invention is also a method of operating a non-volatile memory device in accordance with the above described steps. | 05-20-2010 |
20100125697 | COMPUTING DEVICE HAVING STORAGE, APPARATUS AND METHOD OF MANAGING STORAGE, AND FILE SYSTEM RECORDED RECORDING MEDIUM - A storage management apparatus and a file system for a storage device are provided. The storage management apparatus allocates a portion of storage for writing a file to the storage, including a table storing unit storing an allocation unit table that includes information of a unit of allocation of the storage according to a file extension of a file to be written. A storage management unit manages the storage based on the allocation unit table. | 05-20-2010 |
20100125698 | RECORDABLE MEMORY DEVICE - A recordable memory device includes a nonvolatile semiconductor memory, and a controller controlling the nonvolatile semiconductor memory based on a recordable system. The nonvolatile semiconductor memory has a user area capable of directly making an access from a host, and a system area managed by the controller. A data writing to the reformatted user area of the nonvolatile semiconductor memory executes from a start point which is an unused area after the final physical address of old recordable data recorded in the user area before the reformat. The data writing executes from a start point which is a top physical address in the user area, when the start point exceeds the final physical address in the user area. | 05-20-2010 |
20100125699 | Flash memory device and reading method thereof - Provided are a flash memory device and a reading method of the flash memory device. A multi-level cell flash memory device includes: a memory cell array comprising main memory cells storing main data, and indicator cells storing indicate data indicating one of a first mode and a second mode in which the main data of the main memory cell, to which the indicate cells correspond, is written; and an output unit outputting in response to a control signal corresponding to the indicate data, one of main data read from the memory cell array and forced data forcing some bit values of the main data to bit values of mode specific data, as reading data. | 05-20-2010 |
20100125700 | DISK DRIVE AND METHOD OF CHANGING A PROGRAM THEREFOR - A method of changing a program for controlling a disk drive that includes an EEPROM. The method includes storing a program block to a disk area such that the program block is associated with a second area for storing the program block that is not utilized for a read operation from the disk area. The method also includes storing a program block that is associated with a first area to an area that includes at least a portion of the second area in the EEPROM such that the first area contained a program block that is utilized for a read operation from the disk area. In addition, the method includes changing the program block in the first area after storing to the second area. Moreover, the method includes storing to the second area the program block that is not utilized for a read operation from the disk area after storing to the first area. | 05-20-2010 |
20100125701 | Multi-Level Non-Volatile Memory Device, Memory System Including the Same, and Method of Operating the Same - Methods of programming nonvolatile memory devices include programming a plurality of nonvolatile multi-state memory cells in the non-volatile memory device with state-converted data derived from non-state-converted data. This state-converted data may be associated with a greater number of erased states relative to the non-state-converted data, when programmed into the plurality of nonvolatile memory cells. The methods also include generating a flag having a value that indicates which ones of the plurality of nonvolatile memory cells have been programmed with data that is swapped with data in other ones of the plurality of nonvolatile memory cells. This flag may also be programmed into the nonvolatile memory device. Operations may also be performed to read the state-converted data (and flag) from the plurality of nonvolatile memory cells and then decode the state-converted data into the non-state-converted data, based on the value of the flag. | 05-20-2010 |
20100125702 | Non-Volatile Memory System and Access Method Thereof - Disclosed is a method for accessing a non-volatile memory device using a flash translation layer. The method includes receiving a write request for data from a file system and recording the data in the non-volatile memory device in response to the write request. The flash translation layer is informed whether a confirm mark for the data is recorded or not from the file system. | 05-20-2010 |
20100131695 | Method for Utilizing a Memory Interface to Control Partitioning of a Memory Module - Apparatuses and methods for implementing partitioning in memory cards and modules where conventional memory cards or modules have only a single partition. A representative memory card/module in accordance with the invention includes a memory devices), and a memory interface which includes a data bus, a command line and a clock line. The memory card/module further includes a memory controller coupled to the memory device(s) and to the memory interface. The memory card/module includes means for controlling the partitioning of the memory device(s), and the memory controller is configured to operate the memory device(s) in accordance with the partition information. | 05-27-2010 |
20100131696 | System and Method for Information Handling System Data Redundancy - Flash memory integrated in a hard disk drive chassis maintains a back-up copy of data stored on the hard disk drive between back-ups of the hard disk drive data to separate storage devices. If the hard disk drive fails, the data on the flash memory provides a back-up of changes made since the previous hard disk drive back-up. When a back-up is made of data stored on the hard disk drive to an external storage device, the back-up on the flash memory device is erased to make room for subsequent back-up data. If back-up data stored on the flash memory approaches the capacity of the flash memory, a notice is provided to an end user that a back-up is needed. | 05-27-2010 |
20100131697 | METHODS FOR TAG-GROUPING OF BLOCKS IN STORAGE DEVICES - Embodiments described herein disclose methods, devices, and media for storing data. Methods including the steps of: receiving data to be stored in a memory that includes at least three blocks, wherein each block, for storing the data, has at least one metadata value, associated with each block, that is dependent upon a writing time of each block; grouping at least three blocks into at least two block groups, wherein at least one block group contains at least two blocks; associating a respective metadata value with each block group; and associating the respective metadata value of a respective block group with each block storing the data contained in the respective block group, without storing a dedicated copy of at least one metadata value for each block. In some embodiments, at least one metadata value is stored in a block-group table. | 05-27-2010 |
20100131698 | MEMORY SHARING METHOD FOR FLASH DRIVER - A memory sharing method for flash driver includes determining a target memory size corresponding to a target flash driver, and loading a target flash program included in the target flash driver into a stack memory allocated in a specific memory device when an unused size of the stack memory available for data storage is greater than the target memory size. Additionally, the step of determining the target memory size includes determining a specific flash program having a maximum size among a plurality of flash programs included in the target flash driver, and setting the target memory size equal to the maximum size of the specific flash program. | 05-27-2010 |
20100131699 | METHODS, APPARATUSES, AND COMPUTER PROGRAM PRODUCTS FOR ENHANCING MEMORY ERASE FUNCTIONALITY - A method, apparatus, and computer program product are provided for enhancing memory erase functionality. An apparatus may include a block-based mass memory and a controller configured to receive an erase command from a host device comprising an indication of a location of a block in the mass memory storing memory allocation data. The controller may be further configured to access the memory allocation data based at least in part upon the indicated location. The controller may additionally be configured to determine, based at least in part upon the memory allocation data, blocks within the mass memory that have been freed by the host device. The controller may also be configured to erase the freed blocks. Corresponding methods and computer program products are also provided. | 05-27-2010 |
20100131700 | MEMORY INDEXING SYSTEM AND PROCESS - The invention relates to a memory index management system. The said system comprises an indexed storage memory, a memory zone containing the index and a microprocessor. The index is built in the form of a hierarchical tree structure and comprises at least two nodes. A node contains an identifier associated with a pointer that references either a node of the index or a memory zone in the storage memory. The content of a node is distributed over a first and a second memory zone that are separate in the memory zone. The first space has a first specific pointer that points to the second space and the second space has a second specific pointer whose value has a blank state. | 05-27-2010 |
20100131701 | NONVOLATILE MEMORY DEVICE WITH PREPARATION/STRESS SEQUENCE CONTROL - Provided is a nonvolatile memory device which includes a command buffer configured to receive and store a sequence of first and second commands, a memory including an array of nonvolatile memory cells, and an operation controller configured to control the execution of first and second operations in the memory as respectively defined by the first and second commands, wherein each one of the first and second operations comprises a preparation sequence followed by a stress sequence, and execution of the preparation sequence for the second operation is parallel with the stress sequence of the first operation. | 05-27-2010 |
20100131702 | SINGLE SEGMENT DATA OBJECT MANAGEMENT - A single segment data structure and method for storing data objects employing a single segment data object having a header and a data record. The header includes a segment length field describing the length of memory reserved for the data record and the data record contains at least one data instance object. Each of the data instance objects has a data instance header and data field. The header includes a data instance state field and a data instance length field. The data instance length field contains data representing the length of the data instance data field allowing for variable length “in place” updating. The data instance state field contains data representing an object state of the instance data. Only one of the data instance objects of the data record of the single segment data object has a valid object state. The state field facilitates a power loss recovery process. | 05-27-2010 |
20100138588 | MEMORY CONTROLLER AND A METHOD OF OPERATING AN ELECTRICALLY ALTERABLE NON-VOLATILE MEMORY DEVICE - A controller operates a NAND non-volatile memory device which has an array of non-volatile memory cells. The array of non-volatile memory cells is susceptible to suffering loss of data stored in one or more memory cells of the array. The controller interfaces with a host device and receives from the host device a time-stamp signal. The controller comprises a processor, and a memory having program code stored therein for execution by the processor. The program code is configured to receive by the controller the time stamp signal from the host device; to compare the received time stamp signal with a stored signal wherein the stored signal is a time stamp signal received earlier in time by the controller from the host device; and to determine when to perform a data retention and refresh operation for data stored in the memory array based upon the comparing step. | 06-03-2010 |
20100138589 | STORAGE OPTIMIZATIONS BY DIRECTORY COMPACTION IN A FAT FILE SYSTEM - Storage optimizations by directory compaction in a file allocation table (FAT) file system. The method comprises determining if a cluster comprises a deleted content, indicating that the deleted content is deleted, and updating an entry of a FAT associated with the cluster to indicate that the cluster is free. The method may also comprise indicating that the deleted content is deleted and modifying a metadata of at least one of a file of the cluster and a directory of the cluster according to a specified protocol. | 06-03-2010 |
20100138590 | CONTROL APPARATUS FOR CONTROLLING PERIPHERAL DEVICE, NON-VOLATILE STORAGE ELEMENT, AND METHOD THEREOF - A control apparatus for controlling at least one peripheral device includes a non-volatile storage element and a controller. The non-volatile storage element is used for storing at least one control information set. The controller is externally coupled to the non-volatile storage element and includes a read-only storage element which stores a segment of program code. The controller loads the segment of program code to execute the segment of program code for reading at least one portion of the control information set from the non-volatile storage element to control the operation of the peripheral device. | 06-03-2010 |
20100138591 | MEMORY SYSTEM - A memory system includes a volatile first storing unit, a nonvolatile second storing unit, and a controller. The controller stores management information of data stored in the second storing unit during a startup operation into the first storing unit and performs data management while updating the management information. The management information in a latest state stored into the first storing unit is also stored in the second storing unit. The management information includes a pre-log before and after change generated before a change occurs in the management information and a post-log, which is generated after the change occurs in the management information, concerning the change in the management information. The pre-log and the post-log are stored in the same areas of different blocks. | 06-03-2010 |
20100138592 | Memory device, memory system and mapping information recovering method - Disclosed is a memory device which comprises a data storing part having plural physical storage spaces; and a control part for storing data in the data storing part, wherein each of the physical storage spaces comprises a main area for storing user data at a write operation and a spare area for storing additional data other than the user data, the additional data including a logical address corresponding to a physical storage space and a link value indicating a physical storage space to be accessed next. | 06-03-2010 |
20100138593 | MEMORY CONTROLLER, SEMICONDUCTOR RECORDING DEVICE, AND METHOD FOR NOTIFYING THE NUMBER OF TIMES OF REWRITING - User data transferred from a host apparatus and a first information table | 06-03-2010 |
20100138594 | FLASH MEMORY DATA READ/WRITE PROCESSING METHOD - A flash memory data read/write processing method is provided. The method includes the following steps. An encoding process is performed on the data to be written so that a number of a specific value in the encoded data is reduced compared with that in the original data, and the encoded data is written into a flash memory chip. The encoded data in the flash memory chip is read out, then a decoding process corresponding to the encoding process in Step 1 is performed on the read data, and finally, the decoded data is output. This method may reduce the consumption of a flash memory chip due to writing and erasing operations, thereby prolonging the operating life span of the flash memory chip. This method may also increase the efficiency of writing and erasing operations, reduce the operating time, as well as reduce the power consumption of flash memory operations. | 06-03-2010 |
20100138595 | SEMICONDUCTOR DEVICE COMPRISING FLASH MEMORY AND ADDRESS MAPPING METHOD - A semiconductor device with flash memory includes; a log type determining unit configured to select log type from among a plurality of log types with respect to a log block storing program data requested to be programmed in the flash memory and generate a control signal indicating information indicating the selected log type, and a plurality of log units configured to store program data in the log block having a corresponding log type in response to the control signal, wherein the log type determining unit converts a first type log block formed by a first log type and included in a first type log unit from among the plurality of log units into second type log block formed by a second log type and converts the log block included in a second type log unit from among the plurality of log units into the first type log blocks, the first loge type being different from the second log type. | 06-03-2010 |
20100146186 | Program Control of a non-volatile memory - A method of storing data onto a non-volatile memory includes receiving, from a host, first data that is originally assigned to a first storage area, programming the first data to a second storage area, receiving second data from the host, and while receiving the second data from the host, programming, to the first storage area, the first data that has been programmed to the second storage area, wherein the second data is received from the host simultaneously with the first data being programmed to the first storage area. The second storage area is capable of having data stored thereon faster than the first storage area. | 06-10-2010 |
20100146187 | ENDURANCE MANAGEMENT TECHNIQUE - According to embodiments of the present invention, endurance management techniques are disclosures. Adherence to endurance and data retention ratings are ensured by managing write accesses to a memory device. | 06-10-2010 |
20100146188 | REPLICATED FILE SYSTEM FOR ELECTRONIC DEVICES - Disclosed is a method, system, and computer readable medium for correcting corrupted data in an embedded file system (EFS) within a non-volatile memory (NVM) system. The NVM System further includes a replicated file system (RFS). A memory comparison is performed between EFS memory sectors and corresponding RFS memory sectors to identify any RFS memory sectors that are out of sync with their corresponding EFS memory sectors. Those memory sectors that are out of sync are then erased and rewritten. | 06-10-2010 |
20100146189 | Programming Non Volatile Memories - Non volatile memories and methods of programming thereof are disclosed. In one embodiment, the method of programming a memory array includes receiving a series of data blocks, each data block having a number of bits that are to be programmed, determining the number of bits that are to be programmed in a first data block, determining the number of bits that are to be programmed in a second data block, and writing the first and the second data blocks into a memory array in parallel if the sum of the number of bits that are to be programmed in the first data block and the second data block is not greater than a maximum value. | 06-10-2010 |
20100146190 | FLASH MEMORY STORAGE SYSTEM, AND CONTROLLER AND METHOD FOR ANTI-FALSIFYING DATA THEREOF - A flash memory storage system is provided. The flash memory storage system includes a controller having a rewritable non-volatile memory and a flash memory chip. The rewritable non-volatile memory stores a data token and the flash memory chip stores a security data and a message digest. When the security data in the flash memory chip is updated, the controller updates the data token and generates an eigenvalue, and updates the message digest according to the updated data token and the updated eigenvalue by using a one-way hash function, respectively. When the security data in the flash memory chip is processed by the controller, the controller determinates whether the security data is falsified according to the data token, the eigenvalue and the message digest. In such a way, the security data stored in the flash memory storage system can be effectively protected. | 06-10-2010 |
20100146191 | SYSTEM AND METHODS EMPLOYING MOCK THRESHOLDS TO GENERATE ACTUAL READING THRESHOLDS IN FLASH MEMORY DEVICES - A method for reading at least one page within an erase sector of a flash memory device, the method comprising computing at least one mock reading threshold; using the at least one mock reading threshold to perform at least one mock read operation of at least a portion of at least one page within the erase sector, thereby to generate a plurality of logical values; defining a set of reading thresholds based at least partly on the plurality of logical values; and reading at least one page in the erase sector using the set of reading thresholds. | 06-10-2010 |
20100146192 | METHODS FOR ADAPTIVELY PROGRAMMING FLASH MEMORY DEVICES AND FLASH MEMORY SYSTEMS INCORPORATING SAME - A method for programming a plurality of data sequences into a corresponding plurality of flash memory functional units using a programming process having at least one selectable programming duration-controlling parameter controlling the duration of the programming process for a given data sequence, the method comprising providing at least one indication of at least one varying situational characteristic and determining a value for said at least one selectable programming duration-controlling parameter controlling the duration of the programming process for a given data sequence, for each flash memory functional unit, depending at least partly on said indication of said varying characteristic; and, for each individual flash memory functional unit from among said plurality of flash memory functional units, programming a sequence of bits into said individual flash memory functional unit using a programming process having at least one selectable parameter, said at least one selectable parameter being set at said value determined for said individual flash memory functional unit. | 06-10-2010 |
20100146193 | SYSTEM AND METHOD FOR CACHE SYNCHRONIZATION - A system for cache synchronization includes a data managing unit and a storage medium. The data managing unit is configured to control storing of data of a buffer cache of the storage medium, in response to an event signal received from a host, by classifying the data of the buffer cache into random data and sequential data. The storage medium includes a first area and a second area, and is configured to store the random data and an address information map in the first area, and to store the sequential data in the second area. | 06-10-2010 |
20100146194 | Storage Device And Data Management Method - A storage device includes two flash memories of different flash memory types, and respectively including multiple data blocks. Each data block corresponds to a physical and a logical block address. The storage device further includes a processing module including a controller, which is capable of accessing two mapping tables respectively corresponding to the two flash memories and respectively recording the physical block addresses and the logical block addresses that correspond to the data blocks of the two flash memories. The controller is configured to determine, upon receipt of a command that contains a target logical block address therein, a selected one of the flash memories according to the target logical block address, and to locate a selected one of the physical block addresses by searching one of the mapping tables that corresponds to the selected one of the flash memories with reference to the target logical block address. | 06-10-2010 |
20100146195 | Defragmentation Method For A Machine-Readable Storage Device - A defragmentation method includes the steps of: a) configuring a processor to determine a type of a target machine-readable storage device coupled electrically to the processor; b) configuring the processor to select, from among a plurality of pre-established defragmentation algorithms respectively for performing defragmentation on different types of machine-readable storage devices, a defragmentation algorithm that corresponds to the type of the target machine-readable storage device as determined in step a); and c) configuring the processor to perform defragmentation on the target machine-readable storage device according to the defragmentation algorithm as selected in step b). | 06-10-2010 |
20100146196 | MEMORY SYSTEM HAVING A PLURALITY OF TYPES OF MEMORY CHIPS AND A MEMORY CONTROLLER FOR CONTROLLING THE MEMORY CHIPS - A memory controller converts controller output signals output from a controller into memory input signals according to the operation specifications of memory chips to operate, and outputs the resultant to the memory chips through a common bus. The memory controller also receives memory output signals output from the memory chips through the common bus, and converts the received signals into controller input signals receivable to the controller. This allows the single memory controller to access the plurality of types of memory chips. As a result, the memory controller can be reduced in chip size, lowering the cost of the memory system. | 06-10-2010 |
20100146197 | Non-Volatile Memory And Method With Memory Allocation For A Directly Mapped File Storage System - In a memory system with a file storage system, a scheme for allocating memory locations for a write operation is to write the files substantially contiguously in a memory block one after another rather than to start a new file in a new block. In this way, they are more efficiently packed into the blocks by being written contiguously one after another. In a preferred embodiment, an incrementing write pointer points to the write location in memory for the next data for a file, which is independent of the offset address of the data within the file. When a current write block becomes filled with file data, an erased block is allocated, and the write pointer is moved to this block. Similarly a relocation pointer is used for data relocation during garbage collection or data compaction operations. | 06-10-2010 |
20100153620 | Storage system snapshot assisted by SSD technology - A method and apparatus for taking a snapshot of a storage system employing a solid state disk (SSD). A plurality of mapping tables in the SSD store data needed to create a one or more point in time snapshots and a current view of the SSD. In response to a write command, the SSD executes its normal write process and updates its mapping tables to indicate the current view of the SSD and additionally retains the original data in a table of pointers to the original data, as the snapshot of an earlier state of the SSD. In the preferred embodiment, the innate ability of SSDs to write data to a new location is used to perform a point-in-time copy with little or no loss in performance in performing the snapshot. | 06-17-2010 |
20100153621 | METHODS, COMPUTER PROGRAM PRODUCTS, AND SYSTEMS FOR PROVIDING AN UPGRADEABLE HARD DISK - Methods, computer program products and systems for providing an upgradeable hard disk. The system includes a plurality of memory card slots and a controller. The controller includes a host interface in communication with a host computer, a memory card interface in communication with one or more memory cards located in one or more of the memory card slots, and a detection mechanism. The detection mechanism monitors the memory card slots for newly added memory cards; and in response to detecting a newly added memory card determines characteristics of the newly added memory card and updates the data placement strategy in response to the characteristics of the newly added memory card. The data placement strategy is utilized by the controller to determine write locations for write data received from the host computer via the host interface. | 06-17-2010 |
20100153622 | Data Access Controller and Data Accessing Method - A data access controller and data accessing method is provided. The data access controller includes: a flash memory configuration register unit for storing information used for data access in a flash memory; a flash memory control unit for generating a control signal for data access to a block and a page in the flash memory according to the information used for data access stored in the flash memory configuration register unit; and a temporary memory control unit under the control of the flash memory control unit, adapted to generate a control signal for temporary storage of data. In the inventive solution, data access in the flash memory is under the control of the data access controller, thereby reducing CPU workload, improving operation speed and generality of the control on the data access in flash memory by storing the information for data access for at least one type of flash memory. | 06-17-2010 |
20100153623 | Data Managing Method for Flash Memory and Flash Memory Device Using the Same - A data management method for a flash memory apparatus, entailing a step for handling a plurality of flash chips, a step for enabling the flash chips in sequence, and a step for updating the first data in the first block on the first flash chip among the flash chips. Additionally there is a step for updating f writing of the first new data corresponding to the first data into a second block in a second flash chip among the flash chips, and a step merging the first block and the second block, wherein both of the first new data and the first data are corresponding to a first logical block address. | 06-17-2010 |
20100153624 | DATA MANAGING METHOD FOR NON-VOLATILE MEMORY AND NON-VOLATILE MEMORY DEVICE USING THE SAME - A data managing method for non-volatile memory which comprises a step for receiving a first logical block address and updated data, and a step for merging data in a plurality of physical blocks which have lowest usage rates according to usage parameters in a reference table when the first logical address doesn't exist in the reference table in a buffer memory and a number of pair blocks reaches a determined number. | 06-17-2010 |
20100153625 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor device including a plurality of flash memories, a connector for establishing connection with a host apparatus, a cache memory for data transmission between the flash memories and the host apparatus, a drive control circuit that controls the data transmission between the flash memories and the host apparatus, and a power supply circuit that converts an external power supply voltage into an internal power supply voltage, all mounted on a substrate. A fuse that protects at least the flash memories from an overcurrent is also provided on the substrate. | 06-17-2010 |
20100153626 | MEMORY SYSTEM - To provide a memory system that can surely restore management information even when a program error occurs during data writing. After “log writing ( | 06-17-2010 |
20100153627 | SYSTEM AND METHOD FOR MANAGING FILES IN FLASH MEMORY - A system and method for managing files in a flash memory. The flash memory has a first storage area and a second storage area for storing files. Each of the files has a file header and a data block. The method includes writing the file header of each of the files into the first storage area and setting the first storage area as a first mode, writing the data block of each of the files into the second storage area and setting the second area as a second mode. Responding to the data block of one of the files being completely written into the second storage area, a memory address of the data block stored in the second storage area is written to a corresponding file header. | 06-17-2010 |
20100153628 | METHOD OF FABRICATING SYSTEMS INCLUDING HEAT-SENSITIVE MEMORY DEVICES - A system code is stored in a first nonvolatile memory. The first nonvolatile memory and a second nonvolatile memory are heated during assembly of an electronic device including the first nonvolatile memory and a second nonvolatile memory. The heating is to a temperature sufficient to change a state of at least some memory cells in the second nonvolatile memory device. After the heating, the system code stored in the first nonvolatile memory is copied into the second nonvolatile memory. The first nonvolatile memory may he less vulnerable to temperature-related data alteration than the second nonvolatile memory. For example, the first nonvolatile memory may include a NAND flash memory and the second nonvolatile memory may include a variable resistance memory. | 06-17-2010 |
20100153629 | SEMICONDUCTOR MEMORY DEVICE - A command analyzer | 06-17-2010 |
20100153630 | Data storage system with complex memory and method of operating the same - A data storage system and a data storing method for the data storage system are provided. The data storage system includes a host unit, a storage unit, and a first input/output bus functioning as an interface between the host unit and the storage unit. The storage unit includes a non-volatile memory buffer unit and a flash memory unit. The non-volatile memory buffer unit includes a plurality of buffers arranged in parallel. The flash memory unit includes a plurality of data storage devices arranged in parallel to input and output data using a parallel method. In the method, a writing request is first classified into one of a plurality of grades according to a writing request frequency when there is a writing request and the writing requested data is stored in one of the non-volatile memory buffer unit and the flash memory unit according to the writing request frequency. | 06-17-2010 |
20100153631 | Method and data storage device for processing commands - A data storage device for processing a command includes a host interface and a controller. The host interface stores program information sent within the command from a host. The controller decodes the program information that indicates a memory type to be accessed for the command. In addition, the controller determines whether the specified memory type can be accessed according to the command. The controller performs the command by accessing the memory type when the memory type specified by the program information is available for access. | 06-17-2010 |
20100153632 | NON-VOLATILE MEMORY SYSTEM STORING DATA IN SINGLE-LEVEL CELL OR MULTI-LEVEL CELL ACCORDING TO DATA CHARACTERISTICS - Provided is a system storing data received from an application or file system in a non-volatile memory system of single-level cells and multi-level cells in accordance with one or more data characteristics. The non-volatile memory system includes a non-volatile memory cell array having a plurality of multi-level cells forming a MLC area and a plurality of single-level cells forming a SLC area, and an interface unit analyzing a characteristic of the write data and generating a corresponding data characteristic signal. A flash transition layer receives the data characteristic signal, and determines whether the write data should be stored in the MLC area or the SLC area based on whether or not the write data will be accessed by the file, or whether the address associated with the write data is frequently updated or not. | 06-17-2010 |
20100161877 | DEVICE AND METHOD FOR TRANSFERRING DATA TO A NON-VOLATILE MEMORY DEVICE - A semiconductor device for transferring input data to a non-volatile memory device. The semiconductor device comprises a virtual page buffer including a plurality of data elements; a mask buffer including a corresponding plurality of data elements; control logic circuitry for (i) setting each of the mask buffer data elements to a first logic state upon receipt of a trigger; (ii) causing input data to be written to selected virtual page buffer data elements; and (iii) causing those mask buffer data elements corresponding to the selected virtual page buffer data elements to be set to a different logic state; mask logic circuitry configured to generate masked output data by combining, for each of the virtual page buffer data elements, data read therefrom together with the logic state of the corresponding mask buffer data element; and an output interface configured to release the masked output data towards the non-volatile memory device. | 06-24-2010 |
20100161878 | METHOD OF UNLOCKING PORTABLE MEMORY DEVICE - A method of unlocking usable memory space of a portable memory device, such as a flash drive, includes connecting the portable memory device to a network access device, such as a computer. The network access device executes a control program and accesses a website through the network access device by execution of the control program. A specific task is executed at the website, which sends an unlocking code upon completion of the task. The usable memory space of the portable memory device is unlocked in response to receiving the unlocking code at the network access device. | 06-24-2010 |
20100161879 | Efficient and Secure Main Memory Sharing Across Multiple Processors - Various embodiments of the present invention provide systems and methods for using providing memory access across multiple virtual machines. For example, various embodiments of the present invention provide computing systems that include at least two processors each communicably coupled to a network switch via network interfaces. The computing systems further include a memory appliance communicably coupled to the network switch, and configured to operate as a main memory for the two or more processors. | 06-24-2010 |
20100161880 | FLASH INITIATIVE WEAR LEVELING ALGORITHM - A method and apparatus for initiative wear leveling for non-volatile memory. An embodiment of a method includes counting erase cycles for each of a set of multiple memory blocks of a non-volatile memory, the counting of erase cycles for each memory block including incrementing a first count for a physical block address of the memory block, and if the memory block is not a spare memory block, incrementing a second count for a logical block address of the memory block. The method also includes determining whether the non-volatile memory has uneven wear of memory blocks based at least in part on the counting of the erase cycles of the plurality of memory blocks. | 06-24-2010 |
20100161881 | MEMORY SYSTEM - A memory system ( | 06-24-2010 |
20100161882 | Methods for Executing a Command to Write Data from a Source Location to a Destination Location in a Memory Device - The embodiments described herein provide methods for executing a command to write data from a source location to a destination location in a memory device. In one embodiment, a memory device receives, from a host device, a command to write data from a source location to a destination location in the memory device. The memory device executes the command by changing the memory device's logical-to-physical address map without reading the data from the source location and writing the data to the destination location and without a need of further involvement of the host device after the host device sends the command to the memory device. | 06-24-2010 |
20100161883 | Nonvolatile Semiconductor Memory Drive and Data Management Method of Nonvolatile Semiconductor Memory Drive - According to one embodiment, a nonvolatile semiconductor memory drive includes a nonvolatile semiconductor memory, and a controller which controls a process of writing and reading data with respect to the nonvolatile semiconductor memory. The controller includes a logical address storage module which stores logical address information containing logical addresses indicating storage positions in a logical address space of the nonvolatile semiconductor memory in a redundant area of a page, and a data management module which creates parity data used to restore one logical address information items among n-1 logical address information items stored in redundant areas of n-1 pages based on the other n-2 logical address information items and writes the created second parity data to the redundant area of the n | 06-24-2010 |
20100161884 | Nonvolatile Semiconductor Memory Drive, Information Processing Apparatus and Management Method of Storage Area in Nonvolatile Semiconductor Memory Drive - According to one embodiment, a nonvolatile semiconductor memory drive includes a nonvolatile semiconductor memory, and a controller which controls a process of writing and reading data with respect to the nonvolatile semiconductor memory. The controller includes a compaction control module which acquires free groups set in an unused state by rearranging valid data scattered in n groups in groups of a number not larger than n−1 when the number of free groups remaining in a plurality of groups formed as a storage area management unit of the nonvolatile semiconductor memory becomes not larger than a predetermined number, and a compression control module which acquires free groups by compressing stored data in m groups in which access to stored valid data has not been made for a period longer than a predetermined period and rearranging the compressed data in groups of a number not larger than m−1. | 06-24-2010 |
20100161885 | SEMICONDUCTOR STORAGE DEVICE AND STORAGE CONTROLLING METHOD - A semiconductor storage device includes a first storage unit having a plurality of first blocks as data write regions; an instructing unit that issues a write instruction of writing data into the first blocks; a converting unit that converts an external address of input data to a memory position in the first block with reference to a conversion table in which external addresses of the data are associated with the memory positions of the data in the first blocks; and a judging unit that judges whether any of the first blocks store valid data associated with the external address based on the memory positions of the input data, wherein the instructing unit issues the write instruction of writing the data into the first block in which the valid data is not stored, when any of the first blocks does not store the valid data. | 06-24-2010 |
20100161886 | Architecture for Address Mapping of Managed Non-Volatile Memory - The disclosed architecture uses address mapping to map a block address on a host interface to an internal block address of a non-volatile memory (NVM) device. The block address is mapped to an internal chip select for selecting a Concurrently Addressable Unit (CAU) identified by the block address. The disclosed architecture supports generic NVM commands for read, write, erase and get status operations. The architecture also supports an extended command set for supporting read and write operations that leverage a multiple CAU architecture. | 06-24-2010 |
20100161887 | STORAGE DEVICE, CONTROL METHOD THEREOF, AND ELECTRONIC DEVICE USING STORAGE DEVICE - According to one embodiment, a storage device includes a physical address specifying module, a logical address group specifying module, a data writer, and a storage controller. The physical address specifying module specifies a physical address of write destination of data received together with a logical address among physical addresses each representing a block group including a block of each of flash memories connected in parallel the storage area of which is divided into a plurality of blocks for each sector. The logical address group specifying module specifies a logical address group including logical addresses based on the logical address. The data writer writes data of the logical addresses to blocks in the physical address. The storage controller stores the physical address where the data is written and the logical address group from which the data is written in an address conversion map in association with each other. | 06-24-2010 |
20100161888 | Data storage system with non-volatile memory using both page write and block program and block erase - An optimized data storage system including non-volatile re-writeable memory having both block program and erase and full or partial page write is disclosed. A memory controller of the system can use block data operations for large data transfers, and page data operations for small data transfers. Page data operations in the non-volatile re-writeable memory do not require block rewrites. One or more layers of the non-volatile re-writeable memory can be fabricated BEOL as two-terminal cross-point memory arrays that are fabricated over a substrate including active circuitry fabricated FEOL. Some or all of the active circuitry can be electrically coupled with the one or more layers of two-terminal cross-point memory arrays to perform data operations on the arrays, such as the block program and block erase and/or full or partial page writes. The arrays can include a plurality of two-terminal memory cells. | 06-24-2010 |
20100161889 | Delivering secured media using a portable memory device - In some embodiments an interface of a portable memory device is used to store content information in a hidden memory region of the portable memory device. The interface is also used to store information in a visible memory region of the portable memory device. The information stored in the visible memory region allows the content information stored in the hidden memory region to be accessed. Other embodiments are described and claimed. | 06-24-2010 |
20100161890 | CACHE MANAGEMENT METHOD AND CACHE DEVICE USING SECTOR SET - A cache management method and a cache device using a sector sets, are provided. The cache management method includes receiving at least one of a write request and a read request for predetermined data, from a host device. The cache determines whether a cache memory is allocated to a sector set including the predetermined sector, and selectively allocates the cache memory to the sector set based on the result of determination. The cache may store the data in the cache memory allocated to the sector set. | 06-24-2010 |
20100161891 | METHOD OF CONTROLLING CARD-SHAPED MEMORY DEVICE - Each of a plurality of memory areas includes a plurality of blocks. Each of the blocks includes a plurality of pages. Each of the memory areas also includes a data cache and a page buffer. A control unit controls a lower-limit value of the number of empty blocks in each of the plurality of memory areas. | 06-24-2010 |
20100169540 | METHOD AND APPARATUS FOR RELOCATING SELECTED DATA BETWEEN FLASH PARTITIONS IN A MEMORY DEVICE - A method and system for relocating selected groups of data in a storage device having a non-volatile memory consisting partitions with different types of non-volatile memory. The method may include determining whether data received a first partition meets one or more heightened read probability criteria and/or heightened delete probability criteria. If the criteria are not met, the received data is moved to a second partition, where the first partition has a higher endurance than the second partition. The system may include a first non-volatile memory partition and a second non-volatile memory partition having a lower endurance than the first, where a controller in communication with the first and second partitions determines if a heightened read probability and/or a heightened delete probability are present in received data. | 07-01-2010 |
20100169541 | METHOD AND APPARATUS FOR RETROACTIVE ADAPTATION OF DATA LOCATION - A method and system for organizing groups of data in a storage device having a non-volatile memory consisting of higher performance or endurance portion and a lower performance or endurance portion are disclosed. The method may include steps of determining a data usage status for a group of data in only one of the two portions, and if a data usage criterion is met, moving the group of data to the other of the two portions of the non-volatile memory. In another implementation, the method may include determining a data usage status of groups of data in both portions of the non-volatile memory and moving a group of data from one portion to the other if an appropriate data usage criterion is met so that groups of data may be maintained in a portion of the non-volatile memory most suited to their usage patterns. | 07-01-2010 |
20100169542 | DYNAMIC MAPPING OF LOGICAL RANGES TO WRITE BLOCKS - A method and system writes data to a memory device including dynamic assignment of logical block addresses (LBAs) to physical write blocks. The method includes receiving a request to write data for a logical block address within an LBA range to the memory device. The method assigns the LBA range to a particular write block exclusively or non-exclusively, depending on the existence of previously assigned write blocks and the availability of unwritten blocks. A data structure may be utilized to record the recent usage of blocks for assigning non-exclusive write blocks. An intermediate storage area may be included that implements the dynamic assignment of LBA ranges to physical write blocks. Data in the intermediate storage area may be consolidated and written to the main storage area. Lower fragmentation and write amplification ratios may result by using this method and system. | 07-01-2010 |
20100169543 | RECOVERY FOR NON-VOLATILE MEMORY AFTER POWER LOSS - Non-volatile memory array can be recovered after a power loss. In one example, pages of a memory array are scanned to find a first free page after the power loss. The first free page is marked as available, and the page marked as available is written to with the next write cycle | 07-01-2010 |
20100169544 | METHODS FOR DISTRIBUTING LOG BLOCK ASSOCIATIVITY FOR REAL-TIME SYSTEM AND FLASH MEMORY DEVICES PERFORMING THE SAME - A method for distributing log block associativity in log buffer-based flash translation layer (FTL) includes, if write request on page p is generated, checking whether log block associated with corresponding data block that write request is generated exists or not by checking log block mapping table storing mapping information between data blocks and log blocks, wherein the associativity of each log block to data block is set to equal to or less than predetermined value K in advance, and K is a natural number, if log block associated with corresponding data block that write request is generated exists, checking whether associated log block is random log block or sequential log block, and if associated log block is random log block, writing data that write request is generated in first free page of random log block. | 07-01-2010 |
20100169545 | HOST SYSTEM AND OPERATING METHOD THEREOF - The prevent invention provides a host system and an operating method thereof. The host system comprises: a peripheral device control circuit, for controlling operation of at least a peripheral device, the peripheral device comprising an embedded micro processor; and a host control circuit, coupled to the peripheral device control circuit via a transmission interface, the host control circuit comprising: a storage module, at least storing a firmware of the embedded micro processor; and a control module, coupled to the storage module, for controlling operation of the host control circuit, and the control module transmitting the firmware to the peripheral device control circuit via the transmission interface. The embedded micro processor executes the firmware provided by the host control circuit to control operation of the peripheral device control circuit. | 07-01-2010 |
20100169546 | FLASH MEMORY ACCESS CIRCUIT - A system comprises an instruction processor ( | 07-01-2010 |
20100169547 | METHOD FOR PREVENTING DATA LOSS DURING SOLDER REFLOW PROCESS AND MEMORY DEVICE USING THE SAME - The invention provides a method for preventing data loss in a flash memory during a solder reflow process. The flash memory includes a plurality of memory blocks and each memory block includes a plurality of strong pages and weak pages. Preloading data is first received and stored into the strong pages of at least one of first memory block within the flash memory. Then, the flash memory is heated for the solder reflow process. Next, the preloading data is reorganized according to a trigger signal and the strong pages and weak pages of at least one of second memory block within the flash memory are provided for storing the reorganized preloading data. | 07-01-2010 |
20100169548 | MEMORY CARD AND METHOD FOR CONTROLLING MEMORY CARD - According to one embodiment, a memory card configured to be installed in and removed from a card slot formed in an electronic apparatus, the memory card includes a memory section configured store at least one file, a close-proximity wireless transfer section configured to perform close-proximity wireless transfer, and a controller configured, every time communication between the close-proximity wireless transfer section and a different close-proximity wireless transfer device is enabled, to execute a process for using the close-proximity wireless transfer section to transmit the files stored in the memory section to the different close-proximity wireless transfer device. | 07-01-2010 |
20100169549 | MEMORY SYSTEM AND CONTROLLER - A controller sets, out of a data range that is specified in a read request from a host device, a predetermined size of a first data range that follows a top portion of the data range and a predetermined size of a second data range that follows the first data range, and after transfer, to the host device, of data corresponding to the first data range from a second storage unit or a third storage unit having smaller data output latency than the first storage unit in which read/write of data is performed is started, the controller searches for data corresponding to the second data range in the second storage unit or the third storage unit. | 07-01-2010 |
20100169550 | SEMICONDUCTOR MEMORY DEVICE, DATA TRANSFER DEVICE, AND METHOD OF CONTROLLING SEMICONDUCTOR MEMORY DEVICE - To provide a semiconductor memory device including a first controller that controls a first data transfer in which data are transferred from the first memory to a second memory in predetermined transfer units; a second controller that controls a second data transfer in which data are transferred from the second memory to a host device; and a control unit that outputs to the first controller a read instruction in which an address in the second memory is specified for each of the predetermined transfer units and creates a descriptor in which the addresses in the second memory are specified in order of transfer. The first controller outputs an end notification at each end of the first data transfer, and the second controller executes the second data transfer according to the specification in the descriptor after receiving the end notification. | 07-01-2010 |
20100169551 | MEMORY SYSTEM AND METHOD OF CONTROLLING MEMORY SYSTEM - A forward lookup address translation table and a reverse lookup address translation table stored in a nonvolatile second storing unit are transferred as a master table to a volatile first storing unit at a time of start-up. When an event occurs so that the master table needs to be updated, difference information before and after update of any one of the forward lookup address translation table and the reverse lookup address translation table is recorded in the first storing unit as a log, thereby reducing an amount of the log. | 07-01-2010 |
20100169552 | REMOVALBLE MULTIMEDIA MEMORY CARD AND METHOD OF USE - A method and system is disclosed for distributing multimedia information. The system and method comprises sending a plurality of multimedia files to at least one server; and recording the plurality of multimedia files on a removable memory device. The removable memory device has a format that includes a predetermined information set that is described and physically stored thereon. The method and system is a complete solution for the commercial multimedia (audio, video, picture, text) distribution. Also, the method and system can be used for commercial distribution of any kind digital data (programs, bank data, documents, control etc). The method and system uses individual unique keycode for customized access to internet and any other electronic devices. All multimedia data files are stored on a removable memory device as a physical, hardware device. | 07-01-2010 |
20100169553 | MEMORY SYSTEM, CONTROLLER, AND METHOD OF CONTROLLING MEMORY SYSTEM - A memory system according to an embodiment of the present invention includes a volatile first storing unit, a nonvolatile second storing unit, a controller that transfers data between a host apparatus and the second storing unit via the first storing unit. The memory system monitors whether data written from the host apparatus in the first storing unit has a specific pattern in management units. When data to be flushed to the second storing unit has the specific pattern, the memory system set an invalid address value that is not in use in the second storing unit to the data. | 07-01-2010 |
20100169554 | TERMINAL APPARATUS - A terminal apparatus acquires setting information for controlling whether a storage area held by the non-volatile storage medium is to be used or not, from an external apparatus connected via a network, when the terminal apparatus is activated. The terminal apparatus updates area definition information defining the structure of storage areas in the non-volatile storage medium so that the storage area the use of which is restricted is in a state which cannot be recognized by the operating system, if the acquired setting information indicates that the use of the storage area is restricted. The terminal apparatus performs activation processing of the operating system after the update processing of the area definition information ends, if the acquired setting information indicates that the use of the storage area is restricted. | 07-01-2010 |
20100169555 | METHOD OF WRITING DATA INTO FLASH MEMORY BASED ON FILE SYSTEM - A method of writing data into flash memory based on OS file system is provided. The method includes steps of: obtaining a data start position of a data area in a first partition of a flash memory; converting the data start position into a first block number and a first page number; calculating an offset and adding the offset to the first page number to be an updated first page number when the first page number is not an integer; and, setting the first block number and the updated first page number as a new data start position of the data area and writing a first data according to the new data start position. | 07-01-2010 |
20100169556 | NONVOLATILE STORAGE DEVICE, INFORMATION RECORDING SYSTEM, AND INFORMATION RECORDING METHOD - A nonvolatile storage device includes a nonvolatile memory configured to store user data and management information used to manage the user data on a file system, and a medium controller configured to determine whether a command input from a host device is used for the user data or the management information, the command describing content of processing performed for the user data or the management information, and switch between control methods used for the nonvolatile memory on the basis of the determination result. | 07-01-2010 |
20100169557 | USING NON-VOLATILE STORAGE TO TRACK STATUS CHANGES IN OBJECTS - A non-volatile storage device is used to track status changes in one or more items, where it is less costly to set bits in the non-volatile storage device than to reset bits. For each of the items to be tracked, at least two bits of storage space are allocated in the non-volatile storage device. One of the bits is set when the item changes status, and another of the bits is set when the item changes status again. | 07-01-2010 |
20100169558 | NONVOLATILE MEMORY DEVICE AND NONVOLATILE MEMORY SYSTEM - A nonvolatile storage device includes a controller and a nonvolatile memory. The controller has: a logical-physical address conversion part for converting a logical address designated by a host device into a physical address; and a boot code address conversion part for converting boot code address information designated by the host device into a physical address. After the power-on and before the logical-physical address conversion part becomes usable, a boot code is read from a part of region which can be accessed by designating a logical address from the host device by designating the boot code address information from the outside. Thus, it is possible to rapidly start the nonvolatile memory system after the power-on. In the state where the logical-physical address conversion part can be used, data-reading and data-writing are carried out by designating a logical address from the host device. | 07-01-2010 |
20100169559 | Removable Mother/Daughter Peripheral Card - A peripheral card having a Personal Computer (“PC”) card form factor and removably coupled externally to a host system is further partitioned into a mother card portion and a daughter card portion. The daughter card is removably coupled to the mother card. In the preferred embodiment, a low cost flash “floppy” is accomplished with the daughter card containing only flash EEPROM chips and being controlled by a memory controller residing on the mother card. Other aspects of the invention includes a comprehensive controller on the mother card able to control a predefined set of peripherals on daughter cards connectable to the mother card; relocation of some host resident hardware to the mother card to allow for a minimal host system; a mother card that can accommodate multiple daughter cards; daughter cards that also operates directly with hosts having embedded controllers; daughter cards carrying encoded data and information for decoding it; and daughter cards with security features. | 07-01-2010 |
20100169560 | Methods for Selectively Copying Data Files to Networked Storage and Devices for Initiating the Same - A data backup system comprises a USB flash drive that includes an emulation component and a flash memory. The emulation component is configured to represent the flash memory as if it were an auto-launch device. Accordingly, a data source, such as a personal computer, will interact with the flash memory as if it were the auto-launch device. As some operating systems are configured to recognize auto-launch devices upon connection and automatically execute applications stored thereon, merely connecting the USB flash drive to a data source running such an operating system will cause a backup application stored by the flash memory to automatically execute on the data source. Here, the backup application is configured to selectively back up data files from the data source to a networked storage such as a server of a commercial service provider. | 07-01-2010 |
20100169561 | Removable Mother/Daughter Peripheral Card - A peripheral card having a Personal Computer (“PC”) card form factor and removably coupled externally to a host system is further partitioned into a mother card portion and a daughter card portion. The daughter card is removably coupled to the mother card. In the preferred embodiment, a low cost flash “floppy” is accomplished with the daughter card containing only flash EEPROM chips and being controlled by a memory controller residing on the mother card. Other aspects of the invention includes a comprehensive controller on the mother card able to control a predefined set of peripherals on daughter cards connectable to the mother card; relocation of some host resident hardware to the mother card to allow for a minimal host system; a mother card that can accommodate multiple daughter cards; daughter cards that also operates directly with hosts having embedded controllers; daughter cards carrying encoded data and information for decoding it; and daughter cards with security features. | 07-01-2010 |
20100174845 | Wear Leveling for Non-Volatile Memories: Maintenance of Experience Count and Passive Techniques - Wear leveling techniques for re-programmable non-volatile memory systems, such as a flash EEPROM system, are described. One set of techniques uses “passive” arrangements, where, when a blocks are selected for writing, blocks with relatively low experience count are selected. This can be done by ordering the list of available free blocks based on experience count, with the “coldest” blocks placed at the front of the list, or by searching the free blocks to find a block that is “cold enough”. In another, complementary set of techniques, usable for more standard wear leveling operations as well as for “passive” techniques and other applications where the experience count is needed, the experience count of a block or meta-block is maintained as a block's attribute along its address in the data management structures, such as address tables. | 07-08-2010 |
20100174846 | Nonvolatile Memory With Write Cache Having Flush/Eviction Methods - A portion of a nonvolatile memory is partitioned from a main multi-level memory array to operate as a cache. The cache memory is configured to store at less capacity per memory cell and finer granularity of write units compared to the main memory. In a block-oriented memory architecture, the cache has multiple functions, not merely to improve access speed, but is an integral part of a sequential update block system. Decisions to archive data from the cache memory to the main memory depend on the attributes of the data to be archived, the state of the blocks in the main memory portion and the state of the blocks in the cache portion. | 07-08-2010 |
20100174847 | Non-Volatile Memory and Method With Write Cache Partition Management Methods - A portion of a nonvolatile memory is partitioned from a main multi-level memory array to operate as a cache. The cache memory is configured to store at less capacity per memory cell and finer granularity of write units compared to the main memory. In a block-oriented memory architecture, the cache has multiple functions, not merely to improve access speed, but is an integral part of a sequential update block system. The cache memory has a capacity dynamically increased by allocation of blocks from the main memory in response to a demand to increase the capacity. Preferably, a block with an endurance count higher than average is allocated. The logical addresses of data are partitioned into zones to limit the size of the indices for the cache. | 07-08-2010 |
20100174848 | DATA PROCESSING APPARATUS - A data processing apparatus comprises a monolithic integrated circuit having a data processor, a non-volatile memory storing at least one security code, and at least one interface at the boundary of the integrated circuit via which communication with the data processor can occur. Processing by the data processor of data received at the at least one interface is controlled by the at least one security code. | 07-08-2010 |
20100174849 | SYSTEMS AND METHODS FOR IMPROVING THE PERFORMANCE OF NON-VOLATILE MEMORY OPERATIONS - Disclosed herein are systems and methods that recognize and recapture potentially unused processing time in typical page program and block erase operations in non-volatile memory (NVM) devices. In one embodiment, a characterization module within a controller executes a characterization procedure by performing page program and block erase operations on one or more NVM devices in an array and storing execution time data of the operations in a calibration table. The procedure may be executed at start-up and/or periodically so that the time values are reflective of the actual physical condition of the individual NVM devices. A task manager uses the stored time values to estimate the time needed for completing certain memory operations in its task table. Based on the estimated time for completion, the task manager assigns tasks to be executed during page program and/or block erase cycles, so that otherwise unused processing time can be utilized. | 07-08-2010 |
20100174850 | DATA MOVING METHOD AND SYSTEM UTILIZING THE SAME - A data moving method includes: detecting if data to be written from at least first source data unit of a storage unit includes a specific pattern or not; and simplifying writing operation while writing the data from a second source data unit to a first target data unit if the data includes a specific pattern, wherein the second source data unit includes at least one first source data unit, and the first target data unit includes at least one second target data unit. | 07-08-2010 |
20100174851 | MEMORY SYSTEM CONTROLLER - The present disclosure includes methods and devices for a memory system controller. In one or more embodiments, a memory system controller includes a host interface communicatively coupled to a system controller. The system controller has a number of memory interfaces, and is configured for controlling a plurality of intelligent storage nodes communicatively coupled to the number of memory interfaces. The system controller includes logic configured to map between physical and logical memory addresses, and logic configured to manage wear level across the plurality of intelligent storage nodes. | 07-08-2010 |
20100174852 | METHOD FOR OPERATING NON-VOLATILE MEMORY AND DATA STORAGE SYSTEM USING THE SAME - A method for operating a non-volatile memory is provided. The non-volatile memory includes a plurality of physical blocks haing a plurality of data blocks and spare blocks. An index is obtained by comparing an average erase count of selected physical blocks with a first threshold. Each erase count for each physical block is the total number of the erase operations performed thereon. A performance capability status for the memory is determined according to the index. The performance capability status is set to a first status when the average erase count exceeds the first threshold. An indication is generated based on the performance capability status. A limp function is performed in response to the first status for configuring a minimum number of the at least some spare blocks reserved and used for data update operations. | 07-08-2010 |
20100174853 | USER DEVICE INCLUDING FLASH AND RANDOM WRITE CACHE AND METHOD WRITING DATA - A method of writing data to a flash memory in a system includes; receiving write data to be written in the flash memory, determining whether the received write data is random write data or sequential write data, if the received write data is sequential write data, then directly writing the received write data to the flash memory, and if the received write data is random write data, then writing the received write data to the random write cache, and flushing the random write data from the random write cache to the flash memory during idle periods for the flash memory. | 07-08-2010 |
20100174854 | NON-VOLATILE MEMORY WITH DYNAMIC MULTI-MODE OPERATION - A method and system for extending the life span of a flash memory device. The flash memory device is dynamically configurable to store data in the single bit per cell (SBC) storage mode or the multiple bit per cell (MBC) mode, such that both SBC data and MBC data co-exist within the same memory array. One or more tag bits stored in each page of the memory is used to indicate the type of storage mode used for storing the data in the corresponding subdivision, where a subdivision can be a bank, block or page. A controller monitors the number of program-erase cycles corresponding to each page for selectively changing the storage mode in order to maximize lifespan of any subdivision of the multi-mode flash memory device. | 07-08-2010 |
20100174855 | MEMORY DEVICE CONTROLLER - A controller for a memory device and methods are provided. The controller has an updateable register bank adapted to send a first signal to an analog/memory core of the memory device for controlling operation of the analog/memory core. The analog/memory core has an array of flash memory cells and supporting analog access circuitry. A bus controller is coupled to the register bank. The bus controller is adapted to receive a second signal from the register bank and to send a third signal to the register bank for updating the register bank. A select register is coupled to the register bank. A processor is coupled to the bus controller and the select register. | 07-08-2010 |
20100174856 | MULTI-INTERFACE AND MULTI-BUS STRUCTURED SOLID-STATE STORAGE SUBSYSTEM - A solid-state storage subsystem, such as a non-volatile memory card or drive, includes multiple interfaces and a memory area storing information used by a data arbiter to prioritize data commands received through the interfaces. As one example, the information may store a priority ranking of multiple host systems that are connected to the solid-state storage subsystem, such that the data arbiter may process concurrently received data transfer commands serially according to their priority ranking. A host software component may be configured to store and modify the priority control information in solid-state storage subsystem's memory area. | 07-08-2010 |
20100174857 | DATA PROCESSOR - A data processor ( | 07-08-2010 |
20100180065 | Systems And Methods For Non-Volatile Cache Control - In some embodiments, a method for controlling a cache having a volatile memory and a non-volatile memory during a power up sequence is provided. The method includes receiving, at a controller configured to control the cache and a storage device associated with the cache, a signal indicating whether the non-volatile memory includes dirty data copied from the volatile memory to the non-volatile memory during a power down sequence, the dirty data including data that has not been stored in the storage device. In response to the received signal, the dirty data is restored from the non-volatile memory to the volatile memory, and flushed from the volatile memory to the storage device. | 07-15-2010 |
20100180066 | ELECTRONICALLY ADDRESSED NON-VOLATILE MEMORY-BASED KERNEL DATA CACHE - An operating system on a computer system can comprise a user space, which can comprise a persistent data store, and a kernel space, which can be extended by loading kernel modules. As provided herein, the kernel space can utilize kernel designated electronically addressed non-volatile memory (e.g., flash memory) to cache data from the user space persistent store, for example, upon a boot event. The kernel space can further comprise a cache controller that can be used to populate the kernel electronically addressed non-volatile memory with kernel in-memory data caches that comprise user space persistently stored data. In one embodiment, the kernel space can further comprise kernel designated volatile main memory (e.g., RAM), which can be used in conjunction with the kernel electronically addressed non-volatile memory to cache user space persistently stored data. In this way, kernel modules may access user space persistent store data from the RAM and/or electronically addressed non-volatile kernel cache. | 07-15-2010 |
20100180067 | SYSTEM FOR EMULATING AND EXPANDING A SPI CONFIGURATION ROM FOR IO ENCLOSURE - The present disclosure is directed to a method for providing serial peripheral interface (SPI) access in an IO enclosure. The method may comprise receiving a SPI access request at a bus interface unit; sending the SPI access request to a register bus, the register bus connecting an internal ROM, at least one status register, and at least one control register; fetching from the internal ROM when the SPI access request is a read request for configuration information; reading from the at least one status register when the SPI access request is a read request for at least one of an indicator, a sensor, or a controller within the IO enclosure; and writing to the at least one control register when the SPI access request is a write request for at least one of the indicator, the sensor, or the controller within the IO enclosure. | 07-15-2010 |
20100180068 | STORAGE DEVICE - A storage device realizing an improvement in rewrite endurance of a nonvolatile memory and an improvement in data transfer rate of write and read is provided including a nonvolatile memory | 07-15-2010 |
20100180069 | BLOCK MANAGEMENT METHOD FOR FLASH MEMORY, AND STORAGE SYSTEM AND CONTROLLER USING THE SAME - A block management method for a flash memory of a storage system is provided, wherein the flash memory includes a plurality of physical blocks. The block management method includes grouping the physical blocks into a plurality of physical units, and grouping the physical units into a data area, a spare area, and a replacement area. The block management method further includes performing a first physical unit switch which switches the physical units between the data area and the spare area, and performing a second physical unit switch which switches the physical units between the spare area and the replacement area. Therefore, the block management method can uniformly use the physical blocks and thereby effectively prolong a lifespan of the storage system. | 07-15-2010 |
20100180070 | METHOD OF HANDLING I/O REQUEST AND SOLID STATE DRIVE USING THE SAME - A solid state drive (SSD) including a storage that includes a plurality of flash memories configured to be independently drivable and a controller to receive an input/output (I/O) request from a host, to split the I/O request into a plurality of sub-requests each having a size configured to be capable of being processed independently by each flash memory, and to process the I/O request based on the sub-requests. | 07-15-2010 |
20100180071 | METHOD FOR PROCESSING DATA OF FLASH MEMORY BY SEPARATING LEVELS AND FLASH MEMORY DEVICE THEREOF - The present invention discloses a method for processing data of a flash memory by differentiating levels, which includes steps of separating the communication between a host and a flash memory by a high-level translation layer (HTL) and a low-level abstraction layer (LAL). The HTL receives commands and logical addresses from the host and translates the received logical addresses to the physical addresses of the flash memory. The LAL executes data processing to the corresponding memory cells according to the commands and the physical addresses from the HTL. Since the LAL is disposed between the HTL and the flash memory, the HTL is irrelevant to the structure of the flash memory, and does not have to re-designed with the flash memory which is replaced with another new flash memory. | 07-15-2010 |
20100180072 | MEMORY CONTROLLER, NONVOLATILE MEMORY DEVICE, FILE SYSTEM, NONVOLATILE MEMORY SYSTEM, DATA WRITING METHOD AND DATA WRITING PROGRAM - A file system ( | 07-15-2010 |
20100180073 | FLASH MEMORY DEVICE WITH PHYSICAL CELL VALUE DETERIORATION ACCOMMODATION AND METHODS USEFUL IN CONJUNCTION THEREWITH - A method for determining thresholds useful for converting cell physical levels into cell logical values in an array of digital memory cells storing physical levels which diminish over time, the method comprising determining extent of deterioration of the physical levels and determining thresholds accordingly for at least an individual cell in said array; and reading the individual cell including reading a physical level in the cell and converting the physical level into a logical value using the thresholds, wherein the determining comprises storing predefined physical levels rather than data-determined physical levels in each of a plurality of cells and computing extent of deterioration by determining deterioration of the predefined physical levels. | 07-15-2010 |
20100185802 | SOLID STATE MEMORY FORMATTING - The present disclosure includes methods and devices for solid state drive formatting. One device embodiment includes control circuitry coupled to a number of memory arrays, wherein each memory array has multiple physical blocks of memory cells. The memory arrays are formatted by the control circuitry that is configured to write system data to the number of memory arrays, where the system data ends at a physical block boundary; and write user data to the number of memory arrays, where the user data starts at a physical block boundary. | 07-22-2010 |
20100185803 | METHOD AND APPARATUS FOR ADAPTIVE DATA CHUNK TRANSFER - A block memory device and method of transferring data to a block memory device are described. Various embodiments provide methods for transferring data to a block memory device by adaptive chunking. The data transfer method comprises receiving data in a data chunk. The data transfer method then determines that the data chunk is ready to be transferred to a block memory and transfers the data chunk to the block memory. The transfer occurs over duration, repeating the above steps until the transfer is complete. The data transfer method determines that the data chunk is ready to be transferred to the block memory based on at least in part on a duration of a previous transfer. | 07-22-2010 |
20100185804 | INFORMATION PROCESSING DEVICE THAT ACCESSES MEMORY, PROCESSOR AND MEMORY MANAGEMENT METHOD - An information processing device of an example of the invention comprises an address generation section that generates a write address indicating a write position in a nonvolatile memory so that the write position is shifted in order to suppress each number of times of overlapped writing for each position of the nonvolatile memory when a write operation to the nonvolatile memory from a processor is performed, an order generation section that generates order information indicating a generation order of the writing operation, and a write control section that stores write information to the write address, and stores the order information to the nonvolatile memory so that the order information is related to at least one of the stored write information and the write address. | 07-22-2010 |
20100185805 | Method And Apparatus For Performing Wear Leveling In Memory - The embodiment of the solution provides a method for performing wear leveling in a memory. The method includes: dividing the lifecycle of the memory which includes more than one physical blocks into at least one sampling interval; for each sampling interval, getting the first physical block by taking statistics of the degree of the wear leveling of each physical block in the memory in the current sampling interval; getting the second physical block by taking statistics of the updating times of each logical address in the current sampling interval; exchanging the logical addresses and data of the first physical block and the second physical block. The embodiment of the solution also provides an apparatus corresponding the method | 07-22-2010 |
20100185806 | CACHING SYSTEMS AND METHODS USING A SOLID STATE DISK - A system includes a control module, a location description module, and a page invalidation module. The control module is configured to write data received from a host to a storage medium, read data from the storage medium, and cache data from at least one of the host and the storage medium in a flash memory. The location description module is configured to map one of a valid and invalid state to a physical location of a subset of data in the flash memory. The page invalidation module is configured to receive a command from one of the host and the control module that includes an address corresponding to the subset and an instruction to set a state of the physical location to the invalid state. The page invalidation module is further configured to set the state of the physical location to the invalid state in response to the command. | 07-22-2010 |
20100185807 | DATA STORAGE PROCESSING METHOD, DATA SEARCHING METHOD AND DEVICES THEREOF - A data storage processing method, a data searching method, and devices thereof are provided. The data storage processing method includes: sequentially writing data to a data recording area in a flash; generating log information according to a physical address of the data in the data recording area and an identifier (ID) of the data, and sequentially writing the log information to a log area in the flash; and constructing a Bloom filter data for the log information in the log area, and sequentially writing the Bloom filter data to a log digest area in the flash. A flash storage structure including the data recording area, the log area, and the log digest area is adopted, thereby reducing the occupied storage space of the flash. In addition, since all the areas adopt a sequential storage mode, the data maintenance is quite simple. | 07-22-2010 |
20100185808 | METHODS AND SYSTEMS FOR STORING AND ACCESSING DATA IN UAS BASED FLASH-MEMORY DEVICE - Methods and systems for storing and accessing data in UAS based flash memory device are disclosed. UAS based flash memory device comprises a controller and a plurality of non-volatile memories (e.g., flash memory) it controls. Controller is configured for connecting to a UAS host via a physical layer (e.g., plug and wire based on USB 3.0) and for conducting data transfer operations via two sets of logical pipes. Controller further comprises a random-access-memory (RAM) buffer configured for enabling parallel and duplex data transfer operations through the sets of logical pipes. In addition, a Smart Storage Switch configured for connecting multiple non-volatile memory devices is included in the controller. Finally, a security module/engine/unit is provided for data security via user authentication data encryption/decryption of the device. Furthermore, the flash memory device includes an optical transceiver configured for optical connection to a host also configured with an optical transceiver. | 07-22-2010 |
20100191896 | Solid state drive controller with fast NVRAM buffer and non-volatile tables - Systems and methods for a SSD controller enabling data transfer between a host and flash memories have been achieved. A major component of the SSD controller is a non-volatile buffer memory, which interfaces fast disk drive protocols and slow write and read cycles of NAND flash. Preferably MRAM or Phase Change RAM can be used for the buffer memory. Non-volatile tables can also be implemented for storing dynamic logical to physical address translation, defective sector information and their spare sectors and/or SSD configuration parameters. data are kept in a buffer memory when the buffer memory is not powered | 07-29-2010 |
20100191897 | SYSTEM AND METHOD FOR WEAR LEVELING IN A DATA STORAGE DEVICE - The present disclosure provides a system and method for wear leveling. In one example, the method includes receiving first data to be stored to a first data storage medium and storing the first data to a first storage location in a nonvolatile data store of a second data storage medium comprising a solid-state memory. The method also includes setting a pointer to enable writing second data that is received to a next storage location in the nonvolatile data store. The next storage location comprises an address of the nonvolatile data store that is sequentially after an address of the first storage location. When the address of the first storage location is a last addressed location of the nonvolatile data store the pointer is set to enable writing the second data to a first addressed location of the nonvolatile data store. The method also includes writing the first data stored in the nonvolatile data store to the first data storage medium when a trigger occurs and preserving the pointer during the writing from the nonvolatile data store to the first data storage device such that the pointer enables writing the second data to the next storage location. | 07-29-2010 |
20100191898 | COMPLEX MEMORY DEVICE AND I/O PROCESSING METHOD USING THE SAME - A non-volatile mass storage memory and an input/output processing method using the memory are provided. The memory device includes a storage unit including a non-volatile random access memory and a flash memory and a controller to control the storage to process an input/output request. Accordingly, system memories having different purposes and functionalities, such as a flash memory and a dynamic random access memory (DRAM), may be integrated with each other. | 07-29-2010 |
20100191899 | Information Processing Apparatus and Data Storage Apparatus - According to one embodiment, an information processing apparatus includes an storage apparatus including a first storage and a second storage. The storage apparatus includes a first data management module which stores data which is required to be read in a the predetermined period in the second storage so that the data requested to be read in the predetermined period is distinguishable. The storage apparatus further includes a second data management module which performs replacement of the data in the second storage so that data should be stored in the second storage, in an order reverse to that in which the data is requested to be read, while retaining the data stored in the second storage by the first data management module. | 07-29-2010 |
20100191900 | NONVOLATILE MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A nonvolatile memory device includes memory chips driven in response to respective chip enable signals, and each of the memory chips includes a controller configured to generate and output information about an operation state, and a state information processor configured to calculate an expected consumption current when a target operation is performed based on the information about the operation states for the memory chips, and to output a control signal regarding whether to suspend or perform the target operation. | 07-29-2010 |
20100191901 | NON-VOLATILE STORAGE DEVICE, HOST DEVICE, NON-VOLATILE STORAGE SYSTEM, DATA RECORDING METHOD, AND PROGRAM - A memory controller, a non-volatile storage device, a host device, and a non-volatile storage system capable of performing real-time recording even in the case where normal data and file management information/auxiliary information are written in alternating manner are provided. The host device ( | 07-29-2010 |
20100191902 | STORAGE DEVICE EMPLOYING A FLASH MEMORY - A semiconductor disk wherein a flash memory into which data is rewritten in block unit is employed as a storage medium, the semiconductor disk including a data memory in which file data are stored, a substitutive memory which substitutes for blocks of errors in the data memory, an error memory in which error information of the data memory are stored, and a memory controller which reads data out of, writes data into and erases data from the data memory, the substitutive memory and the error memory. Since the write errors of the flash memory can be remedied, the service life of the semiconductor disk can be increased. | 07-29-2010 |
20100199019 | LOGICAL MEMORY BLOCKS - The present disclosure includes methods and devices for logical memory blocks. One method for operating a memory device includes receiving a command to operate X pages of the memory device, X being greater than Y, and executing the command by executing multiple subcommands, each subcommand operating on a logical memory block portion of the X pages, each logical memory block including at most Y pages. T is a timeout limit, N is a number of pages comprising a block of memory, and Y is number of pages that can be operated within time T. | 08-05-2010 |
20100199020 | NON-VOLATILE MEMORY SUBSYSTEM AND A MEMORY CONTROLLER THEREFOR - In the present invention a non-volatile memory subsystem comprises a non-volatile memory device and a memory controller. The memory controller controls the operation of the non-volatile memory device with the memory controller having a processor for executing computer program instructions for partitioning the non-volatile memory device into a plurality of partitions, with each partition having adjustable parameters for wear level and data retention. The memory subsystem also comprises a clock for supplying timing signals to the memory controller. | 08-05-2010 |
20100199021 | Firehose Dump of SRAM Write Cache Data to Non-Volatile Memory Using a Supercap - A mechanism is provided for firehose dumping modified data in a static random access memory of a hard disk drive to non-volatile memory of the hard disk drive during a power event. Responsive an indication of a power event in the hard disk drive, hard disk drive command processing is suspended. A token is set in the non-volatile storage indicating that flash memory in the non-volatile memory contains modified data. A portion of a static random access memory cache table containing information on the modified data in the static random access memory is copied to the flash memory. The modified data from the static random access memory is then copied to the flash memory. Responsive to a determination that the power event that initiated the copy of the modified data in the static random access memory to the flash memory is still present, the hard disk drive is shut down. | 08-05-2010 |
20100199022 | INFORMATION ACCESS METHOD WITH SHARING MECHANISM AND COMPUTER SYSTEM - An information access method and a computer system are provided. The computer system includes a system management bus (SMBus), a non-volatile memory, a plurality of hardware devices, a chipset, and a CPU. The hardware devices have a plurality of specific recognition information. The CPU performs a configuration process on the hardware devices through the chipset according to the standard for a SMBus protocol, so as to distribute a plurality of memory spaces in the non-volatile memory to the hardware devices. The hardware devices share the SMBus for accessing the plurality of specific recognition information in the memory spaces. | 08-05-2010 |
20100199023 | APPARATUS AND METHOD FOR MANAGING MEMORY - A memory management method and apparatus are disclosed. The memory management apparatus may compute a remaining storage capacity of a flash memory based on a number of bad blocks in a flash memory or a number of block-erases of each of a plurality of blocks, and may display the computed remaining storage capacity of the flash memory. | 08-05-2010 |
20100199024 | METHOD AND APPARATUS FOR MANAGING DATA OF FLASH MEMORY VIA ADDRESS MAPPING - A method of managing data of a flash memory is provided. The method comprises: assigning a logical area of the flash memory as a user block area in which user storage data is stored, and a free block area in which the user storage data is temporarily stored when changing the user storage data; and, when a first data unit of user storage data received from a host is different from a second data unit used while mapping a physical address and a logical address of the flash memory where the user storage data is stored, assigning a predetermined logical area of the flash memory as a cache block area in which the user storage data received from the host is temporarily stored. | 08-05-2010 |
20100199025 | MEMORY SYSTEM AND INTERLEAVING CONTROL METHOD OF MEMORY SYSTEM - A memory system comprising: a plurality of nonvolatile memory areas capable of operating individually; and a memory controller connected to each of the memory areas individually via a ready/busy signal for interleaving an operation in the memory areas by changing a memory area as a target of an operation command, every time the operation command is transmitted, wherein the memory controller includes a priority-level managing unit that manages a level of selection priority for each memory area, so that after transmission of an operation command, the memory controller selects a memory area with a highest level of selection priority from memory areas in a ready state, to change the selected memory area to a target of a next operation command, and shifts the level of selection priority of the selected memory area at a time of next selection to a lowest level by the priority-level managing unit. | 08-05-2010 |
20100199026 | Flash File System and Driving Method Thereof - The present invention discloses a flash file system and drive method thereof, characterized in that, after reception of an access function, it verifies the parameters in the access function and analyzes the file name of the file to be accessed included therein, then queries the starting position of the file to be accessed, and finally controls a physical driver module to access data from the flash according to the starting position and such parameters. The flash file system according to the present invention does not require FAT (File Allocation Table) file system and block interface, thereby simplifying the complexity of file system and enhancing system performance. | 08-05-2010 |
20100199027 | SYSTEM AND METHOD OF MANAGING INDEXATION OF FLASH MEMORY - The invention is a system of managing indexation of memory. Said system has a microprocessor, and a flash memory. Said flash memory has an indexed area comprising indexed items, and an index that is structured in a plurality of index areas comprising a plurality of entries. Said flash memory comprises an index summary comprising a plurality of elements. Each index summary element is linked to an index area of said index. Each index summary element is built from all entries belonging to said linked index area and is built using k hash functions, with 1≦k. | 08-05-2010 |
20100199028 | Non-volatile storage device with forgery-proof permanent storage option - The invention is related to non-volatile storage devices. | 08-05-2010 |
20100199029 | Storage device, computer system, and data writing method - A storage device that includes a flash memory device providing a storage medium, a cache memory for use with the flash memory device, and a control circuit. In the storage device, based on a write command and provided address information, the control circuit selects either the flash memory device or the cache memory as a writing destination of input data. | 08-05-2010 |
20100199030 | METHOD OF MANAGING FLASH MEMORY ALLOCATION IN AN ELECTRONI TOKEN - The invention is a method of managing flash memory-allocation in an electronic token. Said token has a memory comprising a list area and a managed area. Said managed area comprises allocated spaces and at least one free memory chunk. Said list area comprises at least one valid entry referencing a free memory chunk. Said valid entry comprises a state field. Said method comprises the step of selecting a free memory chunk further to an allocation request where said free memory chunk is referenced by an old entry, and the step of identifying a new allocated space in the selected free memory chunk. The state field of said valid entry is preset with a virgin state. Said method comprises the step of invalidating the old entry referencing the selected free memory chunk. | 08-05-2010 |
20100199031 | SYSTEM AND METHOD FOR CONTROLLING ACCESS TO A MEMORY DEVICE OF AN ELECTRONIC DEVICE - The invention relates to a system and method for controlling implementation of a command to a NAND memory device. The method comprises: monitoring an input/output (I/O) bus connected to the NAND memory device for an assertion of a write command for the NAND memory device. Upon detection of the write command, the method evaluates a destination address associated with the write command. If the destination address is not a restricted address for the NAND memory device, then the method allows the write command to modify the contents; and if the destination address is a restricted address for the NAND memory device, then the method prevents assertion of the write command on the contents. | 08-05-2010 |
20100199032 | ENHANCED DATA COMMUNICATION BY A NON-VOLATILE MEMORY CARD - A method of transmitting a stream of data bits from a memory card to a host device includes determining, at the memory card, a first number of data lines between the memory card and the host device, from one to a plurality of data lines. If the first number of data lines is determined to be a plurality of data lines, the method includes switching, at the memory card, the data stream between one of the first number of data lines and another of the first number of data lines after each occurrence of a second number of one or more bits of the data stream having passed toward the host device. The method also includes, if the first number of data lines is determined to be one data line, transmitting, from the memory card, the stream of data bits over the one data line to the host device. | 08-05-2010 |
20100205349 | SEGMENTED-MEMORY FLASH BACKED DRAM MODULE - A memory device for use with a primary power source, includes volatile memory including a plurality of memory segments defined by at least one starting addresses and a corresponding at least one ending address; an interface for connecting to a backup power source; a non-volatile memory; and a controller in communication with the volatile memory and the non-volatile memory programmed to detect a loss of power of the primary power source and in response to move data from the volatile memory to the non-volatile memory based on the at least one starting address and the at least one ending address. In some aspects, there is only one starting address and one ending address and only data that is stored in the volatile memory at addresses between the one starting address and one ending address is moved to the non-volatile memory. | 08-12-2010 |
20100205350 | SYSTEM AND METHOD OF HOST REQUEST MAPPING - Systems and methods for reading data are disclosed. In a particular embodiment, a data storage device includes a host interface that is adapted to couple the data storage device to a host. The host includes memory that is addressable by a host memory address space. The data storage device also includes a device address space that is independent from the host memory address space. The device address space includes a first address region and a second address region, where the second address region is distinct from the first address region. The data storage device also includes a non-volatile memory array and a controller coupled to the non-volatile memory array and further coupled to a mapped device. The controller is adapted to, in response to a first request from the host for access to the first address region of the device address space, perform a memory access operation at the non-volatile memory array. The controller is also adapted to, in response to a second request from the host for access to the second address region of the device address space, map the second request to the mapped device. | 08-12-2010 |
20100205351 | DATABASE JOIN OPTIMIZED FOR FLASH STORAGE - Computer-implemented systems and associated operating methods implement a fast join for databases which is adapted for usage with flash storage. A system comprises a processor that performs a join of two tables stored in a storage in pages processed in a column orientation wherein column values for all rows on a page are co-located in mini-pages within the page. The processor reduces input/output operations of the join by accessing only join columns and mini-pages containing join results. | 08-12-2010 |
20100205352 | MULTILEVEL CELL NAND FLASH MEMORY STORAGE SYSTEM, AND CONTROLLER AND ACCESS METHOD THEREOF - A multi level cell (MLC) NAND flash memory storage system is provided. A controller of the MLC NAND flash memory storage system declares it a signal level cell (SLC) NAND flash memory chip to a host system connected thereto and provides a plurality of SLC logical blocks to the host system. When the controller receives a write command and a user data from the host system, the controller writes the user data into a page of a MLC physical block and records the page of the SLC logical block corresponding to the page of the MLC physical block. When the controller receives an erase command from the host system, the controller writes a predetermined data into the page of the MLC physical block mapped to the SLC logical block to be erased, wherein the predetermined data has the same pattern as a pattern of the erased page. | 08-12-2010 |
20100205353 | MEMORY SYSTEM - A memory system according to an embodiment of the present invention comprises: a log overflow control unit that, when a third condition in which a second log accumulated in a log storage area exceeds a set value is satisfied, stops a recording operation of the second log in the log storage area by a log recording unit and causes a log recording unit to perform an update operation of a second management table in a master table and a recording operation of a first log in the log storage area, and that, when a first condition is satisfied next time, prohibits a commit operation by a log reflecting unit and causes a snapshot storing unit to perform a snapshot storing operation. | 08-12-2010 |
20100205354 | STORAGE DEVICE USING FLASH MEMORY - Provided is a system whose effective endurable number of rewrite times can be drastically improved in a storage device using a flash memory whose rewrite life is restricted. The logical address (LBA) of a sector in which data which is not used as a file system is accumulated is detected. Mapping information on a physical address (PBA) corresponding to the logical address is released. A block in which the mapping information on every logical address and physical address is released out of blocks of the flash memory is deleted and used as an alternative block for wear leveling. | 08-12-2010 |
20100205355 | MULTIPLEXING SECURE DIGITAL MEMORY - A method of storing data within a plurality of memory devices is disclosed. Each memory device of the plurality of memory devices comprises flash memory, and supports a first data transfer rate, A. Data is provided from a data interface to a multiplexer using a second data transfer rate, B, which is faster than the data transfer rate, A. Using the multiplexer, the data is divided into N data portions. Each one of the N data portions is provided to a different memory device of the plurality of memory devices using a third data transfer rate B/N, wherein B/N≦A. The N data portions are stored in parallel, each within a respective different memory device of the plurality of memory devices. | 08-12-2010 |
20100205356 | MEMORY CONTROLLER, MEMORY SYSTEM WITH MEMORY CONTROLLER, AND METHOD OF CONTROLLING FLASH MEMORY - In the control of the number of program-erase cycles, physical blocks (PBs) are divided into plural groups on a basis of the number of program-erase cycles and a search for a free PB is performed in the groups when assigning a logical block (LB) to the free PB. In the search, a free PB among a group covering a small number of program-erase cycles precedes that among a group covering a large number of program-erase cycles. Further, when searching out a free PB in the search, data stored in a PB (source PB) included in a group covering a smaller number of program-erase cycles than that covered by a group including the free PB searched out are transferred to the free PB if there is the source PB. The source PB is a PB to which a LB is assigned earliest among a group including it. | 08-12-2010 |
20100205357 | MEMORY CONTROLLER, MEMORY SYSTEM WITH MEMORY CONTROLLER, AND METHOD OF CONTROLLING FLASH MEMORY - In the control of the number of program-erase cycles, when assigning a logical block (LB) to a physical block (PB), the number of program-erase cycles of a first PB and that of a second PB are compared, which first PB is a free PB of which the number of program-erase cycles is the smallest among that of free PBs, which second PB is a PB earliest assigned a LB among PBs each assigned a LB. As a result, in a case where the number of program-erase cycles of the first PB is larger by a predetermined value or more than that of the second PB, data stored in the second PB are transferred to a free PB of which the number of program-erase cycles is the largest among free PBs, and then the LB is assigned to the second PB. | 08-12-2010 |
20100205358 | METHOD TO REWRITE FLASH MEMORY WITH EXCLUSIVELY ACTIVATED TWO BLOCKS AND OPTICAL TRANSCEIVER IMPLEMENTING CONTROLLER PERFORMING THE SAME - An effective algorithm for the CPU with a flash memory is disclosed to shorten a dead time to erase the flash memory and to write new data therein. The flash memory of the invention provides front and back blocks for the user data area. When the front block is filled, the back block is erased just after the front block is fully filled in advance to receive a new data next to be written. | 08-12-2010 |
20100205359 | Storage System Using Flash Memory Modules Logically Grouped for Wear-Leveling and Raid - A storage system using flash memories includes a storage controller and plural flash memory modules as storage media. Each flash memory module includes at least one flash memory chip and a memory controller for leveling erase counts of blocks belonging to the flash memory chip. The storage controller combines the plural flash memory modules into a first logical group, translates a first address used for accessing the flash memory modules belonging to the first logical group to a second address used for handling the first address in the storage controller, and combines the plural first logical groups into a second logical group. | 08-12-2010 |
20100205360 | Removable Mother/Daughter Peripheral Card - A peripheral card having a Personal Computer (“PC”) card form factor and removably coupled externally to a host system is further partitioned into a mother card portion and a daughter card portion. The daughter card is removably coupled to the mother card. In the preferred embodiment, a low cost flash “floppy” is accomplished with the daughter card containing only flash EEPROM chips and being controlled by a memory controller residing on the mother card. Other aspects of the invention includes a comprehensive controller on the mother card able to control a predefined set of peripherals on daughter cards connectable to the mother card; relocation of some host resident hardware to the mother card to allow for a minimal host system; a mother card that can accommodate multiple daughter cards; daughter cards that also operates directly with hosts having embedded controllers; daughter cards carrying encoded data and information for decoding it; and daughter cards with security features. | 08-12-2010 |
20100205361 | SEMICONDUCTOR MEMORY CARD ACCESS APPARATUS, A COMPUTER-READABLE RECORDING MEDIUM, AN INITIALIZATION METHOD, AND A SEMICONDUCTOR MEMORY CARD - A predetermined number of erasable blocks positioned at a start of a volume area in a semiconductor memory card are provided so as to include volume management information. A user area following the volume management information includes a plurality of clusters. | 08-12-2010 |
20100205362 | Cache Control in a Non-Volatile Memory Device - A flash memory device includes a storage area having a main memory portion and a cache memory portion storing at least one bit per cell less than the main memory portion; and a controller that manages data transfer between the cache memory portion and the main memory portion according to at least one caching command received from a host. The management of data transfer, by the controller, includes transferring new data from the host to the cache memory portion, copying the data from the cache memory portion to the main memory portion and controlling (enabling/disabling) the scheduling of cache cleaning operations. | 08-12-2010 |
20100211721 | MEMORY NETWORK METHODS, APPARATUS, AND SYSTEMS - Apparatus and systems may include a first node group include a first network node coupled to a memory, the first network node including a first port, a second port, a processor port, and a hop port. Network node group may include a second network node coupled to a memory, the second network node including a first port, a second port, a processor port, and a hop port, the hop port of the second network node coupled to the hop port of the first network node and configured to communicate between the first network node and the second network node. Network node group may include a processor coupled to the processor port of the first network node and coupled to the processor port of the second network node, the processor configured to access the first memory through the first network node and the second memory through the second network node. Other apparatus, systems, and methods are disclosed. | 08-19-2010 |
20100211722 | METHOD FOR TRANSMITTING SPECIAL COMMANDS TO FLASH STORAGE DEVICE - The invention provides a data storage system. In one embodiment, the data storage system comprises a host and a flash storage device. The host sends a series of first access commands for accessing a plurality of special files to the flash storage device. The flash storage device having the stored plurality of special files and a command-symbol mapping table, sequentially generates a plurality of first digits respectively corresponding to the special files accessed by the first access commands to obtain a first data stream, converts the first data stream to a plurality of first special commands according to the command-symbol mapping table, and performs operations according to the first special commands. Each of the special files corresponds to a digit, the command-symbol mapping table records a corresponding relationship between a plurality of symbols and a plurality of special commands, and each of the symbols comprises a plurality of digits. | 08-19-2010 |
20100211723 | Memory controller, memory system with memory controller, and method of controlling flash memory - Access to flash memories is controlled so that efficiency of data writing and effective utilization of storage area go together. In the access control, priority order, for physical blocks each storing effective data, is managed so that a position of a physical block in the assignment order becomes higher according as assignment of a logical block to the physical block is performed more recently. When assigning a logical block to a free physical block, a determination is made whether a position of a previous physical block is higher than a predetermined position in the priority order. The previous physical block is a physical block, then, corresponding to the same logical block as the free physical block. When the determination is negative, effective data stored in the previous physical block is transferred to the free physical block. | 08-19-2010 |
20100211725 | INFORMATION PROCESSING SYSTEM - An information processing system comprises a main memory operative to store data, and a control circuit operative to access the main memory for data. The main memory includes a nonvolatile semiconductor memory device containing electrically erasable programmable nonvolatile memory cells each using a variable resistor, and a DRAM arranged as a cache memory between the control circuit and the nonvolatile semiconductor memory device. The nonvolatile semiconductor memory device has a refresh mode of rewriting stored data. The control circuit activates the nonvolatile semiconductor memory device in said refresh mode based on the number of accesses to the nonvolatile semiconductor memory device. | 08-19-2010 |
20100211726 | METHOD FOR MANIPULATING STATE MACHINE STORAGE IN A SMALL MEMORY SPACE - A method includes configuring a flash memory device including a first memory sector having a primary memory sector correspondence, a second memory sector having an alternate memory sector correspondence, and a third memory sector having a free memory sector correspondence, copying a portion of the primary memory sector to the free memory sector, erasing the primary memory sector, and changing a correspondence of each of the first memory sector, the second memory sector, and the third memory sector. | 08-19-2010 |
20100217917 | SYSTEM AND METHOD OF FINALIZING SEMICONDUCTOR MEMORY - Systems and methods of finalizing a semiconductor memory are disclosed. A method includes receiving an instruction to finalize data at a data storage device that includes a controller coupled to a semiconductor memory. The data storage device also includes a status indicator to indicate a finalize status of the semiconductor memory. In response to receiving the instruction to finalize the data at the data storage device, the status indicator is set to a finalize value. Write to the semiconductor memory operations are prevented by the controller in response to the status indicator having the finalize value. | 08-26-2010 |
20100217918 | DATA STORAGE DEVICE AND METHOD FOR ACCESSING FLASH MEMORY - The invention provides a method for accessing a flash memory. In one embodiment, the flash memory comprises a plurality of memory units, each of the memory units has a physical address, and an address link table records a mapping relationship between a plurality of logical addresses and a plurality of physical addresses. First, first data to be written to a first logical address is received from a host. Whether the first data is predetermined data is the determined. Whether the first logical address is mapped to a null physical address is then determined according to the address link table. When the first data is the predetermined data and the first logical address is not mapped to the null physical address according to the address link table, the address link table is modified to map the first logical address to the null physical address. | 08-26-2010 |
20100217919 | MEMORY CONTROLLER, SEMICONDUCTOR MEMORY DEVICE AND CONTROL METHOD THEREOF - A memory controller includes logical-physical address conversion table, an access number storing section configured to store the number of accesses to read out data from a memory cell in association with a logical address, a storage state checking section configured to check a storage state of data stored in the memory cell at every predetermined number of accesses, and a refresh processing section configured to perform refresh processing to restore the data stored in the memory cell if the storage state of the data is in a predetermined degraded state. | 08-26-2010 |
20100217920 | Memory system and address allocating method of flash translation layer thereof - The memory system includes a flash memory and a memory controller. The flash memory has at least two addresses with different program times. The memory controller is configured to control the flash memory. The memory controller is configured to assign an address corresponding to a shorter program time from among the at least two addresses for a write operation executed at interruption of a power supply to the flash memory. The assigned address is used to store data of the memory controller in the flash memory. | 08-26-2010 |
20100217921 | Memory system and data processing method thereof - A method of processing data of a nonvolatile memory includes performing a randomization operation on a data unit including page data to be programmed into the nonvolatile memory and page metadata corresponding to the page data and generating a random seed; and programming the randomized data unit, and the random seed into the nonvolatile memory, the randomized data unit including the randomized page data and the randomized page metadata. The random seed is programmed within the page metadata and a position at which the random seed is programmed is based on a characteristic of the page data. | 08-26-2010 |
20100217922 | ACCESS MODULE, STORAGE MODULE, MUSICAL SOUND GENERATING SYSTEM AND DATA WRITING MODULE - An access module is connected to a storage module which stores multiplexed musical sound data in a non-compressed form. Based on a read request status of each sounding channel and access status of the nonvolatile storage module as a read target, a read instructing part transfers a read instruction to the storage module and reads musical sound data in parallel from the storage modules. In this musical sound generating system, since a plurality of pieces of musical sound data can be read from a plurality of nonvolatile storage modules in parallel, a sounding delay time can be made smaller than an acceptable time. For this reason, a prevailing mass NAND flash memory can be used as a memory for the musical sound data, thereby realizing a high sound quality and compact musical sound generating system. | 08-26-2010 |
20100217923 | STORAGE DEVICE WITH FLASH MEMORY - According to one embodiment, a write detector detects a predetermined state where a flash memory contains an area to which write data subject to a write request from a host is to be written and from which data has been erased. A data reception controller allows a data buffer to receive the requested write data in accordance with the detection of the predetermined state. | 08-26-2010 |
20100217924 | HYBRID MEMORY DEVICE WITH SINGLE INTERFACE - Described is a technology by which a memory controller is a component of a hybrid memory device having different types of memory therein (e.g., SDRAM and flash memory), in which the controller operates such that the memory device has only a single memory interface with respect to voltage and access protocols defined for one type of memory. For example, the controller allows a memory device with a standard SDRAM interface to provide access to both SDRAM and non-volatile memory with the non-volatile memory overlaid in one or more designated blocks of the volatile memory address space (or vice-versa). A command protocol maps memory pages to the volatile memory interface address space, for example, permitting a single pin compatible multi-chip package to replace an existing volatile memory device in any computing device that wants to provide non-volatile storage, while only requiring software changes to the device to access the flash. | 08-26-2010 |
20100217925 | BLOCK MANAGEMENT FOR MASS STORAGE - An embodiment of the present invention includes a nonvolatile memory system comprising nonvolatile memory for storing sector information, the nonvolatile memory being organized into blocks with each block including a plurality of sectors, each sector identified by a logical block address and for storing sector information. A controller is coupled to the nonvolatile memory for writing sector information to the latter and for updating the sector information, wherein upon updating sector information, the controller writes to the next free or available sector(s) of a block such that upon multiple re-writes or updating of sector information, a plurality of blocks are substantially filled with sector information and upon such time, the controller rearranges the updated sector information in sequential order based on their respective logical block addresses thereby increasing system performance and improving manufacturing costs of the controller. | 08-26-2010 |
20100217926 | Direct Data File Storage Implementation Techniques in Flash Memories - Host system data files are written directly to a large erase block flash memory system with a unique identification of each file and offsets of data within the file but without the use of any intermediate logical addresses or a virtual address space for the memory. Directory information of where the files are stored in the memory is maintained within the memory system by its controller, rather than by the host. The file based interface between the host and memory systems allows the memory system controller to utilize the data storage blocks within the memory with increased efficiency. | 08-26-2010 |
20100217927 | STORAGE DEVICE AND USER DEVICE INCLUDING THE SAME - A storage device includes a host interface, a buffer memory, a storage medium, and a controller. The host interface is configured to receive storage data and an invalidation command, where the invalidation command is indicative of invalid data among the storage data received by the host interface. The buffer memory is configured to temporarily store the storage data received by the host interface. The controller is configured to execute a transcribe operation in which the storage data temporarily stored in the buffer memory is selectively stored in the storage medium. Further, the controller is responsive to receipt of the invalidation command to execute a logging process when a memory capacity of the invalid data indicated by the invalidation command is equal to or greater than a reference capacity, and to execute an invalidation process when the memory capacity of the invalid data is less than the reference capacity. The logging process includes logging a location of the invalid data, and the invalidation process includes invalidating the invalid data. | 08-26-2010 |
20100223420 | Memory system and data management method of flash translation layer thereof - A data management method includes determining the size of input data, storing the input data in a log block if the size of the input data is determined to be a write unit, and storing the input data in a partial block if the size of the input data is determined to be smaller than the write unit. The log block is a temporary block storing data of same addresses and the partial block is a temporary block storing data regardless of their addresses. The memory system includes a nonvolatile memory and a memory controller configured to control the nonvolatile memory. The memory controller is configured to temporarily store input data smaller than a write unit in a selected memory block even when the input data have different addresses. | 09-02-2010 |
20100223421 | User device including flash memory storing index and index accessing method thereof - A user device includes a flash memory configured to store an index including a plurality of index nodes and a controller configured to control the flash memory. The controller is configured to detect a pointer ID corresponding to a selected key of a first index node, translate the detected pointer ID to an index address by using a pointer table, and access a second index node corresponding to the selected key by using the index address. | 09-02-2010 |
20100223422 | Advanced Dynamic Disk Memory Module - Memory modules address the growing gap between main memory performance and disk drive performance in computational apparatus such as personal computers. Memory modules disclosed herein fill the need for substantially higher storage capacity in end-user add-in memory modules. Such memory modules accelerate the availability of applications, and data for those applications. An exemplary application of such memory modules is as a high capacity consumer memory product that can be used in Hi-Definition video recorders. In various embodiments, memory modules include a volatile memory, a non-volatile memory, and a command interpreter that includes interfaces to the memories and to various busses. The first memory acts as an accelerating buffer for the second memory, and the second memory provides non-volatile backup for the first memory. In some embodiments data transfer from the first memory to the second memory may be interrupted to provide read access to the second memory. | 09-02-2010 |
20100223423 | Direct File Data Programming and Deletion in Flash Memories - Host system data files are written directly to a large erase block flash memory system with a unique identification of each file and offsets of data within the file but without the use of any intermediate logical addresses or a virtual address space for the memory. Directory information of where the files are stored in the memory is maintained within the memory system by its controller, rather than by the host. The file based interface between the host and memory systems allows the memory system controller to utilize the data storage blocks within the memory with increased efficiency. | 09-02-2010 |
20100223424 | MEMORY SYSTEM AND CONTROL METHOD THEREOF - A memory system includes a nonvolatile memory including a plurality of blocks as data erase units, a measuring unit which measures an erase time at which data of each block is erased, and a block controller which writes data supplied from at least an exterior into a first block which is set in a free state and whose erase time is oldest. | 09-02-2010 |
20100228905 | MEMORY CONTROLLER, MEMORY CARD, AND NONVOLATILE MEMORY SYSTEM - A nonvolatile memory system includes a memory card ( | 09-09-2010 |
20100228906 | Managing Data in a Non-Volatile Memory System - Management of data in a non-volatile memory system is disclosed. A write command may be received that indicates a logical block address for writing data associated with the write command. The logical block address may be within a logical zone. The logical zone may be one of a plurality of logical zones within the non-volatile memory, wherein each of the plurality of logical zones comprises a different range of logical block addresses than the rest of the plurality of logical zones. The logical zone may further comprise a temporary storage block. The data associated with the write command may be written to the temporary storage block of the logical zone when a size of the data associated with the write command does not exceed a threshold. The data associated with the write command may be transferred from the temporary storage block to the logical block address in response to a trigger event. | 09-09-2010 |
20100228907 | METHOD OF EVENLY USING A PLURALITY OF BLOCKS OF A FLASH MEMORY, AND ASSOCIATED MEMORY DEVICE AND CONTROLLER THEREOF - A method of evenly using a plurality of blocks of a Flash memory comprises: providing at least one threshold value, which is utilized for sieving out blocks suitable for use from the plurality of blocks according to erase counts of the plurality of blocks; and by comparing erase counts of at least a portion of the plurality of blocks with the threshold value, sieving out a specific block for use from the plurality of blocks according to a purpose of use. An associated memory device and a controller thereof are also provided, where the controller comprises: a ROM arranged to store a program code, wherein the controller is provided with the at least one threshold value through the program code; and a microprocessor arranged to execute the program code to control the access to the Flash memory. The controller sieves out the specific block according to the purpose of use. | 09-09-2010 |
20100228908 | MULTI-PORT MEMORY DEVICES AND METHODS - An integrated circuit device may include a first integrated circuit (IC) portion having a single memory port to access at least one memory array, the single port including a first set of address, control and data paths; and a second IC portion comprising at least a first memory port and a second memory port for providing access to the memory locations of the first IC portion through the single port of the first IC portion. | 09-09-2010 |
20100228909 | Caching Performance Optimization - A method for managing data storage is described. The method includes receiving data from an external host at a peripheral storage device, detecting a file system type of the external host, and adapting a caching policy for transmitting the data to a memory accessible by the storage device, wherein the caching policy is based on the detected file system type. The detection of the file system type can be based on the received data. The detection bases can include a size of the received data. In some implementations, the detection of the file system type can be based on accessing the memory for file system type indicators that are associated with a unique file system type. Adapting the caching policy can reduce a number of data transmissions to the memory. The detected file system type can be a file allocation table (FAT) system type. | 09-09-2010 |
20100235563 | METHOD FOR ENHANCING PERFORMANCE OF A FLASH MEMORY, AND ASSOCIATED PORTABLE MEMORY DEVICE AND CONTROLLER THEREOF - A method for enhancing performance of a Flash memory includes: providing a random access memory (RAM); utilizing the RAM to temporarily store at least one virtual Flash block; and selectively moving data of the virtual Flash block to the Flash memory in order to write at least one new page in the Flash memory. An associated portable memory device and a controller thereof are also provided, where the controller includes: a read only memory (ROM) arranged to store a program code; and a microprocessor arranged to execute the program code to control the access to the Flash memory. In addition, the controller that executes the program code by utilizing the microprocessor selectively moves the data of the virtual Flash block to the Flash memory in order to write at least one new page in the Flash memory. | 09-16-2010 |
20100235564 | SEMICONDUCTOR MEMORY DEVICE - First conversion from a logical address to a physical address is performed, and data is written in to a region in a first storage region specified by the first conversion. Second conversion from a logical address to a physical address which is different from the first conversion is performed, and data is written into a region in a second storage region specified by the second conversion. When the controller detects sequential writing having a predetermined length or more, it shifts to a first write mode that data is written into the first storage region. When the controller detects that a difference between a logical address at the end of a previous write operation and a logical address at the start of a subsequent write operation is not present in a predetermined range, it shifts to a second write mode that data is written into the second storage region. | 09-16-2010 |
20100235565 | APPARATUS AND METHOD TO PROTECT METADATA AGAINST UNEXPECTED POWER DOWN - A system includes first memory configured to store first metadata to associate logical addresses with physical addresses. Second memory is configured to include the physical addresses, to store first data based on the physical addresses, and to store portions of the first metadata when a status of a predetermined group of the physical addresses is changed. A recovery module is configured to update the first metadata based on the portions of the first metadata stored in the second memory. | 09-16-2010 |
20100235566 | FLASH MEMORY APPARATUS AND METHOD OF CONTROLLING THE SAME - Described herein is a flash memory apparatus and method controlling the same. The flash memory apparatus includes a processor and one or more flash memory units. The processor controls one or more memory operations performed in the one or more flash memory units. The processor stops controlling a memory operation in a flash memory unit when the memory operation is performed, and continues performing the memory operation in the flash memory unit when the flash memory unit generates an interrupt signal. | 09-16-2010 |
20100235567 | AIRCRAFT INCLUDING DATA DESTRUCTION MEANS - The aircraft includes:
| 09-16-2010 |
20100235568 | STORAGE DEVICE USING NON-VOLATILE MEMORY - According to one embodiment, a storage device includes a plurality of writable non-volatile memory devices, a buffer memory, a memory controller, and a spare non-volatile memory device. The buffer memory temporarily stores write data from a host. The memory controller writes the write data in the buffer memory to the non-volatile memory devices in a distributed manner. The memory controller writes write data in the buffer memory not having been written to the non-volatile memory devices to the spare non-volatile memory device when detecting a power down, and writes the write data having been written to the spare non-volatile memory device to the buffer memory when the power is restored. | 09-16-2010 |
20100235569 | Storage Optimization System - A method and apparatus optimizes storage on solid-state memory devices. The system aggregates object storage write requests. The system determines whether objects associated with the object storage requests that have been aggregated fit in a block of the solid-state memory device within a defined tolerance. Upon the aggregation of object storage write requests that fit in a block of the solid-state memory device, the system writes the objects associated with the aggregated object storage write requests to the solid-state memory device | 09-16-2010 |
20100235570 | COMMAND CONTROLLER, PREFETCH BUFFER AND METHODS FOR ACCESSING A SERIAL FLASH IN AN EMBEDDED SYSTEM - The invention relates to a command controller and a prefetch buffer, and in particular, to a command controller and a prefetch buffer for accessing a serial flash in an embedded system. An embedded system comprises a serial flash, a processor, a plurality of access devices, and a prefetch buffer. The processor and the plurality of access devices send various commands to read data from or write data to the serial flash. The prefetch buffer temporarily stores a predetermined amount of data before data being read from or written to the serial flash. | 09-16-2010 |
20100241786 | Apparatus and method for optimized NAND flash memory management for devices with limited resources - An apparatus and method for managing memory in low-end electronic devices is provided. The apparatus includes a memory management unit. The memory management unit configured to allocate a portion of random access memory and a portion of flash memory as swap areas. The memory management unit performs swapping operations by swapping pages of content between the random access memory swap area and one or more blocks of the flash memory swap area. Thereafter, a page of content can be loaded from the flash memory swap area. The memory management unit also allocates a portion of flash memory as a garbage collection area. The memory management unit transfers dirty pages from the flash swap area to the garbage collection unit to free up flash memory swap area blocks. | 09-23-2010 |
20100241787 | SENSOR PROTECTION USING A NON-VOLATILE MEMORY CELL - A method and apparatus for protecting an electrical device using a non-volatile memory cell, such as an STRAM or RRAM memory cell. In some embodiments, a memory element is connected in parallel with a sensor element, where the memory element is configured to be repetitively reprogrammable between a high resistance state and a low resistance state. The memory element is programmed to the low resistance state when the sensor element is in a non-operational state and reprogrammed to the high resistance state when the sensor element is in an operational state. | 09-23-2010 |
20100241788 | FLASH MEMORY WRITING MTHEOD AND STROAGE SYSTEM AND CONTROLLER USING THE SAME - A flash memory writing method for writing data into a flash memory storage system is provided. In the present method, a big data usage number and a small data usage number are counted for each logical unit in the flash memory storage system, so as to respectively represent the numbers of writing a big data and a small data into each the logical unit. When a host system writes new data into a logical unit in the flash memory storage system, the new data is written through different writing processes according to the big data usage number and the small data usage number of the logical unit. Thereby, the data writing efficiency is improved and the lifespan of the flash memory storage system is prolonged. | 09-23-2010 |
20100241789 | DATA STORAGE METHOD FOR FLASH MEMORY AND DATA STORAGE SYSTEM USING THE SAME - A data storage method for a flash memory storage device is provided. The method includes disposing a pattern identification unit in the flash memory storage device and disposing a pattern analysis unit in a host connected to the flash memory storage device. The method further includes analyzing a usage pattern of each flash memory storage address in the flash memory storage device by using the pattern analysis unit, receiving information from the pattern analysis unit through the pattern identification unit to identify the usage pattern of each flash memory storage address, and storing data into each flash memory storage address through a corresponding process according to the usage pattern of the flash memory storage address. Thereby, data can be stored according to the usage pattern of each flash memory storage address, and accordingly the speed of storing data into the flash memory storage device can be effectively increased. | 09-23-2010 |
20100241790 | METHOD OF STORING DATA INTO FLASH MEMORY IN A DBMS-INDEPENDENT MANNER USING THE PAGE-DIFFERENTIAL - The present invention proposes an effective and efficient method of storing data called page-differential logging for flash-based storage systems. The primary characteristics of the invention are: (1) it writes only the page-differential that is defined as the difference between an original page in flash memory and an up-to-date page in memory; (2) it computes and writes the page-differential only when an updated page needs to be reflected into flash memory. When an updated page needs to be reflected into flash memory, the present invention stores the page into a base page and a differential page in flash memory. When a page is recreated from flash memory, it reads the base page and the differential page, and then, creates the page by merging the base page with its page-differential in the differential page. This invention significantly improves I/O performance of flash-based storage systems compared with existing page-based and log-based methods. | 09-23-2010 |
20100241791 | CONTROLLER WHICH CONTROLS OPERATION OF NONVOLATILE SEMICONDUCTOR MEMORY AND SEMICONDUCTOR MEMORY DEVICE INCLUDING NONVOLATILE SEMICONDUCTOR MEMORY AND CONTROLLER THEREFORE - A controller includes an instruction table memory, a program counter, a first decoder, and a first executing unit. The instruction table memory stores an instruction code obtained by coding a sequence to access a nonvolatile semiconductor memory. A read address in the instruction table memory is set to the program counter. The first decoder decodes the instruction code read from the instruction table memory to output a first decode signal. The first executing unit executes access to the nonvolatile semiconductor memory on the basis of the first decode signal output from the first decoder. | 09-23-2010 |
20100241792 | STORAGE DEVICE AND METHOD OF MANAGING A BUFFER MEMORY OF THE STORAGE DEVICE - A storage device including a processor to transmit N pages of data from one or more pages in a buffer memory where N is a natural number. The storage device also includes a flash memory to program in parallel the N pages of data to N flash chips. The N pages may be transmitted via one or more channels. | 09-23-2010 |
20100241793 | STORAGE SYSTEM AND METHOD FOR CONTROLLING STORAGE SYSTEM - The present invention efficiently uses the storage capacity in a storage system that has flash memory as a storage medium. | 09-23-2010 |
20100241794 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device according to one aspect of the present invention includes: a memory cell array provided to perform programming in page units; and a control circuit provided to control the programming. The control circuit includes: means that performs a first detection for memory cells in a part provided as a unit smaller than a page, concurrently with programming to memory cells to be written in a page; and means that subjects the memory cells in the page to a second detection that takes into consideration a failure relief due to a redundant region, when the number of memory cells of unwritten state in the part as detected by the first detection becomes equal to or less than a first constant, and that ends the program operation when the number of memory cells of unwritten state in the page becomes equal to or less than a second constant. | 09-23-2010 |
20100241795 | NONVOLATILE MEMORY SYSTEM, AND DATA READ/WRITE METHOD FOR NONVOLATILE MEMORY SYSTEM - A nonvolatile memory system comprises a nonvolatile memory having a plurality of data areas; and a memory controller operative to control read and write operations to the nonvolatile memory. The memory controller successively executes read/write operations to plural sectors within a selected data area in the nonvolatile memory in accordance with a command and a sector count and sector address fed from a host device. | 09-23-2010 |
20100241796 | MEMORY SYSTEM PROTECTED FROM ERRORS DUE TO READ DISTURBANCE AND READING METHOD THEREOF - A method of reading a memory system including a flash memory includes: reading data from a page in a first block of the flash memory, incrementing a counter each time data is read from the page to store a corresponding number of read-out cycles of the flash memory, and copying data from the first block of the flash memory to a second block of the flash memory when the counter exceeds a reference number of read-out cycles. The data from the first block includes data from the page. | 09-23-2010 |
20100241797 | STORAGE DEVICE AND STORING METHOD - To enable a capacity of an entire storage device to be kept by adding a flash drive or a flash module in the flash drive for a flash memory that has a failure, even if the storage device using the flash memory has a failure in its part such as a part of flash memory chip has a failure, for example, the flash memory chip has run out of its lifetime. In a storage device equipped with two or more memory device units with a plurality of semiconductor memory devices, each of which has a functional capacity unit smaller than a capacity of an entire semiconductor memory device and has a writing lifetime for each functional capacity unit, only a functional capacity unit whose writing lifetime is run out to be determined as unable to be written is substituted by a functional capacity unit in a memory device of the other memory device unit to keep a predetermined capacity of the entire device. | 09-23-2010 |
20100241798 | ROBUST INDEX STORAGE FOR NON-VOLATILE MEMORY - A non-volatile memory data address translation scheme is described that utilizes a hierarchal address translation system that is stored in the non-volatile memory itself. Embodiments of the present invention utilize a hierarchal address data and translation system wherein the address translation data entries are stored in one or more data structures/tables in the hierarchy, one or more of which can be updated in-place multiple times without having to overwrite data. This hierarchal address translation data structure and multiple update of data entries in the individual tables/data structures allow the hierarchal address translation data structure to be efficiently stored in a non-volatile memory array without markedly inducing write fatigue or adversely affecting the lifetime of the part. The hierarchal address translation of embodiments of the present invention also allow for an address translation layer that does not have to be resident in system RAM for operation. | 09-23-2010 |
20100250826 | MEMORY SYSTEMS WITH A PLURALITY OF STRUCTURES AND METHODS FOR OPERATING THE SAME - Memory systems, such as solid state drives, and methods of operating such memory systems are disclosed, such as those adapted to provide parallel processing of data using redundant array techniques. Individual flash devices or channels containing multiple flash devices are operated as individual drives in an array of redundant drives. Ranges of physical addresses corresponding to logical addresses are provided to a host for performing read and write operations on different channels, such as to improve read variability. | 09-30-2010 |
20100250827 | Apparatus for Enhancing Flash Memory Access - An apparatus for interfacing between a CPU and Flash memory units, enabling optimized sequential access to the Flash memory units. The apparatus interfaces between the address, control and data buses of the CPU and the address, control and data lines of the Flash memory units. The apparatus anticipates the subsequent memory accesses, and interleaves them between the Flash memory units. An optimization of the read access is therefore provided, thereby improving Flash memory throughput and reducing the latency. Specifically, the apparatus enables improved Flash access in embedded CPUs incorporated in a System-On-Chip (SOC) device. | 09-30-2010 |
20100250828 | CONTROL SIGNAL OUTPUT PIN TO INDICATE MEMORY INTERFACE CONTROL FLOW - Embodiments include but are not limited to apparatuses and systems including a memory array including a plurality of non-volatile memory cells, and a control signal output pin operatively coupled to the memory array. The control signal output pin may be configured to provide a control signal indicative of the memory interface control flow including, for example, an availability of the memory array for reading or writing. Other embodiments may be described and claimed. | 09-30-2010 |
20100250829 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR SENDING LOGICAL BLOCK ADDRESS DE-ALLOCATION STATUS INFORMATION - A system, method, and computer program product are provided for sending de-allocation status information. In use, a de-allocation status of at least a portion of memory associated with a logical block address is determined. Additionally, de-allocation status information is generated, based on the determination. Furthermore, the de-allocation status information is sent to a device. | 09-30-2010 |
20100250830 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR HARDENING DATA STORED ON A SOLID STATE DISK - A system, method, and computer program product are provided for hardening data stored on a solid state disk. In operation, it is determined whether a solid state disk is to be powered off. Furthermore, data stored on the solid state disk is hardened if it is determined that the solid state disk is to be powered off. | 09-30-2010 |
20100250831 | DATA STORAGE SYSTEM MANAGER AND METHOD FOR MANAGING A DATA STORAGE SYSTEM - A data storage system manager includes one or more servers, at least one data collector deployed on at least one of the servers, at least one policy engine deployed on at least one of the servers, and at least one configuration manager deployed on at least one the servers. The at least one data collector is configured to collect resource utilization information including data storage wear rate of data storage system data storage modules. The at least one policy engine is configured to evaluate the collected information and to initiate changes to a configuration of the data storage system based on data storage wear rate and work load distribution policies. The at least one configuration manager is configured to implement the changes initiated by the at least one policy engine to control the data storage wear rate and a skew of the work load distribution within the data storage system. | 09-30-2010 |
20100250832 | STORAGE SERVICE DEVICE WITH DUAL CONTROLLER AND BACKUP METHOD THEREOF - A storage service device with a dual controller and a backup method thereof are applicable to provide the same view service to an event-login log and a configuration file of a server. The storage service device includes a first control module, a second control module, a battery unit, a basic input/output system (BIOS), and a backup procedure. Once a power failure occurs to the server, the following backup procedure is performed a hardware interrupt signal is sent to the battery unit, so as to provide an operation power to a first memory module and a second memory module; an index page of the first memory module is synchronized with that of the second memory module; and the updated index pages are recorded into a first flash memory and a second flash memory respectively. | 09-30-2010 |
20100250833 | TECHNIQUES TO PERFORM POWER FAIL-SAFE CACHING WITHOUT ATOMIC METADATA - A method and system to allow power fail-safe write-back or write-through caching of data in a persistent storage device into one or more cache lines of a caching device. No metadata associated with any of the cache lines is written atomically into the caching device when the data in the storage device is cached. As such, specialized cache hardware to allow atomic writing of metadata during the caching of data is not required. | 09-30-2010 |
20100250834 | METHOD AND SYSTEM TO PERFORM CACHING BASED ON FILE-LEVEL HEURISTICS - A method and system to perform caching based at least on one or more file-level heuristics. The caching of a storage medium in a caching device is performed by a cache policy engine. The cache policy engine receives file-level information of input/output access of data of the storage medium and caches or evicts the data of the storage medium in the caching device based on the received file-level information. By utilizing information about the files and file operations associated with the disk sectors or logical block addresses of the storage medium, the cache policy engine can make a better decision on the data selection of the storage medium to be cached in or evicted from the caching device in one embodiment of the invention. Higher cache hit rates can be achieved and the performance of the system utilizing the cache policy engine is improved. | 09-30-2010 |
20100250835 | METHOD FOR PROTECTING SENSITIVE DATA ON A STORAGE DEVICE HAVING WEAR LEVELING - Disclosed is a method for protecting sensitive data in a storage device having wear leveling. In the method, a write command, with an associated sensitive write signal indicating that sensitive data is associated with the write command, is received. The sensitive data is further associated with at least one address pointing to a storage location within an initial physical storage block. The write command is executed by writing to at least one storage location within an available physical storage block, pointing the at least one address to the at least one storage location within the available physical storage block, and erasing the initial physical storage block to complete execution of the write command. | 09-30-2010 |
20100250836 | Use of Host System Resources by Memory Controller - A method for data storage includes, in a system that includes a host having a host memory and a memory controller that is separate from the host and stores data for the host in a non-volatile memory including multiple analog memory cells, storing in the host memory information items relating to respective groups of the analog memory cells of the non-volatile memory. A command that causes the memory controller to access a given group of the analog memory cells is received from the host. In response to the command, a respective information item relating to the given group of the analog memory cells is retrieved from the host memory by the memory controller, and the given group of the analog memory cells is accessed using the retrieved information item. | 09-30-2010 |
20100250837 | Method for Addressing Page-Oriented Non-Volatile Memories - A method for addressing memory pages of a non-volatile memory in a memory system with a memory controller and a further volatile memory. The non-volatile memory is organized in erasable memory blocks with a multiplicity of memory pages, and each memory page, containing a number of sectors, can be written individually. The volatile memory holds an address translation table specifying an assignment of logical memory page addresses to physical memory page addresses. By way of the memory controller, a reconstruction table is stored as a copy of the address translation table in one or more memory blocks in the non-volatile memory, a log book table with data records containing changed assignments of logical memory page addresses to physical memory page addresses, is carried in the volatile memory and, if the log book table exceeds a predetermined size, a changed reconstruction table is stored in the non-volatile memory. | 09-30-2010 |
20100250838 | PORTABLE DATA CARRIER COMPRISING A WEB SERVER - In a method for providing data for a data processing device ( | 09-30-2010 |
20100250839 | METHOD FOR CONTROLLING MEMORY CARD AND METHOD FOR CONTROLLING NONVOLATILE SEMICONDUCTOR MEMORY - A method for controlling a memory card which includes a nonvolatile semiconductor memory whose memory area includes a plurality of write areas is disclosed. A first area which is a part of the plurality of write areas is set in accordance with management executed by a first file system. The first file system sequentially writes data along a direction in which addresses of the plurality of write areas increase. A second area which is a part of the plurality of write areas is set in accordance with management executed by a second file system. The second file system writes data in an order which does not depend on the addresses. | 09-30-2010 |
20100250840 | VERSION BASED NON-VOLATILE MEMORY TRANSLATION LAYER - A non-volatile memory and erase block/data block/sector/cluster update and address translation scheme utilizing a version number is detailed that enhances data updating and helps reduce program disturb of the memory cells of the non-volatile memory device. The various embodiments utilize a version number associated with each erase block, data block, sector, and/or cluster. This allows for determination of currently valid data block, sector and/or cluster associated with the logical ID of the data grouping by locating the most recent version associated with the logical ID. With this approach, old data need not be invalidated by programming a valid/invalid flag, avoiding the risk of program disturb in the surrounding data rows. | 09-30-2010 |
20100262752 | STORAGE VIRTUAL CONTAINERS - A controller of a Solid State Device (SSD) defines a mapping from memory devices, such as flash packages, that make up the SSD to one or more storage virtual containers. The storage virtual containers are exposed to an operating system by the controller through an interface. The operating system may then make operation requests to the one or more storage virtual containers, and the controller may use the mapping to fulfill the operation requests from the corresponding flash packages. The storage virtual containers are mapped to the flash packages to take advantage of the parallelism of the flash packages in the SSD so that the controller may fulfill operation requests received from the operating system in parallel. | 10-14-2010 |
20100262753 | METHOD AND APPARATUS FOR CONNECTING MULTIPLE MEMORY DEVICES TO A CONTROLLER - A control system includes a controller having shared pins and unique pins for receiving and outputting signals from and to first and second memory devices. The first memory device includes signal lines which are electrically connected to shared pins, and the second memory device includes signal lines which are electrically connected to the shared pins together with the signal lines from the first memory device. The controller selectively inputs signals from and output signals to the first memory device and second memory device through the select shared pins. | 10-14-2010 |
20100262754 | CPU DATA BUS PLD/FPGA INTERFACE USING DUAL PORT RAM STRUCTURE BUILT IN PLD - A programmable logic device and a system and method using the programmable logic device are disclosed. The programmable logic device may include first and second ports in data communication with a memory block including a pair of address areas. The system may include the programmable logic device in data communication with a central processing unit and a controller. The method may include generating a command from the central processing unit based on data read from one of the address areas and written to the second address area wherein the address areas are associated with a common memory address. | 10-14-2010 |
20100262755 | MEMORY SYSTEMS FOR COMPUTING DEVICES AND SYSTEMS - Memory systems and devices are provided. One memory system includes a controller configured to be coupled to a plurality of computing devices, a plurality of Multi-Level Cell (MLC) devices coupled to the controller, and a Single-Level Cell (SLC) device coupled to the controller and the plurality of MLC devices. The MLC devices are configured to split the storage of data across the plurality of MLC devices and the SLC device is configured to function as a parity device for the data. A memory device includes a controller, a plurality of MLC FLASH devices, and a SLC FLASH device. The MLC FLASH devices are configured to split the storage of data across the plurality of MLC FLASH devices and the SLC FLASH device is configured to function as a parity device for the data. Also provided are computing devices including the above memory device. | 10-14-2010 |
20100262756 | METHOD FOR WRITING TO AND ERASING A NON-VOLATILE MEMORY - A method for writing to and erasing a non-volatile memory is described. The method includes determining the size of a command window for use in n write operations for the non-volatile memory, each write operation having the same time period. A long latency erase command is sliced by a factor of n to provide a plurality of erase slices, each erase slice having the same time period. The method further includes executing n commands to the non-volatile memory, each command composed of the combination of one of the n write operations and one of the erase slices. The total of the time period of one erase slice added to the time period of one write operation is less than or equal to the size of the command window. | 10-14-2010 |
20100262757 | DATA STORAGE DEVICE - A data storage device may include a first memory board having multiple memory chips and a controller board that is arranged and configured to operably connect to the first memory board. The controller board may include an interface to a host and a controller that is arranged and configured to control command processing for multiple different types of memory chips, automatically recognize a type of the memory chips on the first memory board, receive commands from the host using the interface, and execute the commands using the memory chips. | 10-14-2010 |
20100262758 | DATA STORAGE DEVICE - A data storage device may include a first memory board including multiple memory chips and a controller board that is arranged and configured to operably connect to the first memory board. The controller board may include an interface to a host and a controller that includes a power module and that is arranged and configured to control command processing for multiple memory chips having different voltages, automatically recognize a voltage of the memory chips on the first memory board, configure the power module to operate at the recognized voltage of the memory chips, receive commands from the host using the interface and execute the commands using the memory chips. | 10-14-2010 |
20100262759 | DATA STORAGE DEVICE - A data storage device may include a first memory board and a second memory board, where the first memory board and the second memory board each comprise multiple memory chips. The data storage device may include a controller board that is arranged and configured to operably connect to the first memory board and the second memory board, where the controller board includes a high speed interface and a controller that is arranged and configured to receive commands from a host using the high speed interface and to execute the commands, where the first memory board and the second memory board are each separately removable from the controller board. | 10-14-2010 |
20100262760 | COMMAND PROCESSOR FOR A DATA STORAGE DEVICE - An apparatus for queuing and ordering commands for a data storage device may include a slot tracker module that is arranged and configured to track available slots for commands from a host, a command transfer module that is operably coupled to the slot tracker module and that is arranged and configured to retrieve commands from the host based on a number of the available slots, a pending command module that is operably coupled to the command transfer module and that is arranged and configured to queue and order the commands from the host for processing using an ordered list that is based on an age of the commands and a task dispatch module that is operably coupled to the pending command module and that is arranged and configured to dispatch the commands for processing using the ordered list from the pending command module and an availability of storage locations. | 10-14-2010 |
20100262761 | PARTITIONING A FLASH MEMORY DATA STORAGE DEVICE - A method of partitioning a data storage device that has a plurality of memory chips includes determining a number memory chips in the data storage device, defining, via a host coupled to the data storage device, a first partition of the data storage device, where the first partition includes a first subset of the plurality of memory chips, defining a second partition of the data storage device via the host where the second partition includes a second subset of the plurality of memory chips, such that the first subset does not include any memory chips of the second subset and wherein the second subset does not include any memory chips of the first subset. | 10-14-2010 |
20100262762 | RAID CONFIGURATION IN A FLASH MEMORY DATA STORAGE DEVICE - A method of storing data in a flash memory data storage device that includes a plurality of memory chips is disclosed. The method includes determining a number of memory chips in the data storage device, defining, via a host coupled to the data storage device, a first partition of the data storage device, where the first partition includes a first subset of the plurality of memory chips and defining a second partition of the data storage device via a host coupled to the data storage device, where the second partition includes a second subset of the plurality of memory chips. First data is written to the first partition while reading data from the second partition, and first data is written to the second partition while reading data from the first partition. | 10-14-2010 |
20100262763 | DATA ACCESS METHOD EMPLOYED IN MULTI-CHANNEL FLASH MEMORY SYSTEM AND DATA ACCESS APPARATUS THEREOF - A data access method used in a multi-channel flash memory system includes: respectively writing a plurality of data into a plurality of buffer areas of a buffer unit through direct memory accessing; and sequentially reading the plurality of data from the plurality of buffer areas, and respectively and synchronously storing the plurality of read data into the plurality of flash memory units, wherein each of the plurality of data is a data block protected by an error correction code (ECC). | 10-14-2010 |
20100262764 | METHOD FOR ACCESSING STORAGE APPARATUS AND RELATED CONTROL CIRCUIT - A storage apparatus includes a first storage unit and at least a second storage unit. A method for accessing the storage apparatus generates a plurality of bad block lists regarding the plurality of the storage units, respectively, and according to at least one bad block indicated by a bad block list of the first storage unit, configures at least a good block in each second storage unit corresponding to the at least one bad block of the first storage unit as a replacement block of each second storage unit. Accordingly, the method generates a mapping result of each second storage unit according to a bad block list of the second storage unit and each replacement block, and accesses the storage apparatus according to the bad block list of the first storage unit and each mapping result. | 10-14-2010 |
20100262765 | STORAGE APPARATUS, COMPUTER SYSTEM HAVING THE SAME, AND METHODS THEREOF - A storage apparatus includes a memory unit and a controller to set up a memory space of the memory unit as a user data space and a spare space according to a signal representing at least one of the user data space and spare space. An electronic apparatus controls the storage apparatus, and a method controls at least one of the storage apparatus and the electronic apparatus to control a memory space of the storage apparatus. | 10-14-2010 |
20100262766 | GARBAGE COLLECTION FOR FAILURE PREDICTION AND REPARTITIONING - A method of formatting a data storage device that includes a plurality of flash memory chips includes monitoring a failure rate of memory blocks of one or more flash memory chips of a storage device that has a first usable size for user space applications, estimating a future usable size of the data storage device based on the monitored failure rate, and defining, via a host coupled to the data storage device, a second usable size of the data storage device for user space applications based on the monitored failure rate. | 10-14-2010 |
20100262767 | DATA STORAGE DEVICE - A data storage device may include a command bus, a status bus, multiple memory devices that are operably coupled to the command bus and to the status bus, and a controller including multiple channel controllers, where the channel controllers are operably coupled to the command bus and to the status bus and each of the channel controllers is arranged and configured to control one or more of the memory devices. The data storage device may include multiple programmable logic devices that are operably coupled to the status bus, where each of the programmable logic devices is configured to retrieve a ready/busy signal from each of the memory devices under control of one of the channel controllers using the status bus, serialize the ready/busy signals and communicate the serialized ready/busy signals to the channel controllers. | 10-14-2010 |
20100262768 | CONFIGURABLE FLASH MEMORY CONTROLLER AND METHOD OF USE - A FLASH memory controller is disclosed. The controller comprises a microcontroller. The microcontroller including firmware for providing different mappings for different types of FLASH memory chips. The controller also includes FLASH control logic for communicating with the microcontroller and adapted to communicate via a FLASH data bus to at least one FLASH memory chip. The FLASH control logic including mapping logic for configuring the FLASH data bus based upon the type of FLASH memory chip coupled thereto. A method and system in accordance with the present invention provides the following advantages: Configurable data bus on the FLASH memory controller through software to simplify routing complexity. Configurable chip select and control bus for flexibility of FLASH memory placement. Elimination of external resistor network for layout simplicity. A scalable architecture for higher data bus bandwidth support. Auto-detection of FLASH memory type and capacity configuration. | 10-14-2010 |
20100268864 | Logical-to-Physical Address Translation for a Removable Data Storage Device - A method for making memory more reliable involves accessing data stored in a removable storage device by translating a logical memory address provided by a host digital device to a physical memory address in the device. A logical memory address is received from the host digital device. The logical memory address corresponds to a location of data stored on the removable storage device. A physical memory address corresponding to the local address is determined by accessing a lookup table corresponding to the logical zone. | 10-21-2010 |
20100268865 | Static Wear Leveling - Methods for extending the service life of a data storage device and devices operable to perform those methods are presented. A master lookup table block may comprise lookup table blocks and store an erase count indicator for each lookup table block. Each lookup table block may be associated with a logical zone of a memory and comprise entries. Each entry may be associated with a logical block and comprise an erase count for a physical block corresponding to that logical block. A physical block erasure may be performed on a first physical block in the memory. The physical block erasure may be tracked by incrementally increasing a first erase count. An actual erase count may be determined for the first physical block. The entry for a logical block corresponding to the first physical block may be exchanged with another entry within a different lookup table block when the actual erase count for the first physical block exceeds a threshold. The different lookup table block may have a lower erase count indicator relative to that of the lookup table block comprising the entry for the logical block corresponding to the first physical block. | 10-21-2010 |
20100268866 | SYSTEMS AND METHODS FOR OPERATING A DISK DRIVE - System and methods for storing data to a storage device are provided. In embodiments, the storage device may include a disk drive with a solid-state memory for storing certain frequently updated information. In some embodiments, the solid-state memory may be used to store journaling information. | 10-21-2010 |
20100268867 | METHOD AND APPARATUS FOR UPDATING FIRMWARE AS A BACKGROUND TASK - A method comprising storing data in a first memory that includes a first portion that has read-only access during a normal mode of operation; and during a update mode of operation: copying at least one data structure from the first memory to a second memory where it is available for use during the update mode; and updating data in the first portion of the first memory. | 10-21-2010 |
20100268868 | FLASH STORAGE DEVICE AND OPERATING METHOD THEREOF - The invention also provides a flash storage device. In one embodiment, the flash storage device is coupled to a host, and comprises a random access memory and a controller. The random access memory stores a plurality of link tables therein, wherein each of the link tables corresponds to one of a plurality of management units of at least one flash memory, and the link tables store corresponding relationships between logical addresses and physical addresses of the corresponding management units. The controller receives an access logical address from the host, determines an access physical address corresponding to the access logical address according to the link tables stored in the random access memory, and accesses data from the flash memory according to the access physical address. | 10-21-2010 |
20100268869 | MEMORY SYSTEM COMPRISING NONVOLATILE MEMORY DEVICE AND CONTROLLER - A memory system comprises a nonvolatile memory device and a controller. The controller comprises a working memory and is configured to control the nonvolatile memory device. The nonvolatile memory device is configured to store drive data required to access the nonvolatile memory device. When an initialization operation of the memory system is performed, the controller activates an operation standby signal after loading a portion of the drive data stored in the nonvolatile memory device into the working memory. | 10-21-2010 |
20100268870 | DATA STORAGE DEVICE AND DATA STORAGE SYSTEM INCLUDING THE SAME - A data storage device includes a flash memory including a plurality of data blocks and a flash translation layer that divides the plurality of data blocks into a data block of a first group and a data block of a second group, and that records the data signal to a data block of the first group or a data block of the second group which is extended from a data block of the first group. | 10-21-2010 |
20100268871 | NON-VOLATILE MEMORY CONTROLLER PROCESSING NEW REQUEST BEFORE COMPLETING CURRENT OPERATION, SYSTEM INCLUDING SAME, AND METHOD - A non-volatile memory controller, system and method capable of processing a next request as an interrupt before completing a current operation are disclosed. The non-volatile memory system includes a first memory storing meta data loaded from a flash memory; a second memory storing the meta data copied from the first memory; and a flash memory controller copying the meta data from the first memory to the second memory, changing the meta data in the second memory, and then re-copying the changed meta data from the second memory to the first memory during a first-type operation that requires changes in the meta data. | 10-21-2010 |
20100268872 | DATA STORAGE SYSTEM COMPRISING MEMORY CONTROLLER AND NONVOLATILE MEMORY - A data storage system comprising a storage device comprising at least one nonvolatile memory, and a controller connected to the storage device through a channel. The memory controller sends part or all of a command, address and data for a next operation to the nonvolatile memory while the nonvolatile memory device is in a busy state. The memory controller then performs a background operation while the nonvolatile memory device remains in the busy state. | 10-21-2010 |
20100268873 | FLASH MEMORY CONTROLLER UTILIZING MULTIPLE VOLTAGES AND A METHOD OF USE - A Flash memory controller is disclosed. The Flash memory controller comprises a host interface, a Flash memory interface, controller logic coupled between the host interface, the controller logic handling a plurality of voltages. The controller also includes a mechanism for allowing a multiple voltage host to interface with a high voltage or a multiple voltage Flash memory. A multiple voltage Flash memory controller in accordance with the present invention provides the following advantages over conventional Flash memory controllers: (1) a voltage host is allowed to interface with multiple Flash memory components that operate at different voltages in any combination; (2) power consumption efficiency is improved by integrating the programmable voltage regulator, and voltage comparator mechanism with the Flash memory controller; (3) External jumper selection is eliminated for power source configuration; and (4) Flash memory controller power source interface pin-outs are simplified. | 10-21-2010 |
20100274949 | DATA ACCESS METHOD FOR FLASH MEMORY AND STORAGE SYSTEM AND CONTROLLER USING THE SAME - A data access method for accessing a flash memory storage system, a storage system and a controller using the same are provided. A flash memory has a plurality of physical blocks, which are grouped into a system area, a data area, and a spare area. One or more variable tables are established to record transient information of each set of mother-child blocks of the data area and the spare area. The number of the variable table could be adjusted adaptively according to time required for writing the variable table into the system area, such that an overall data access efficiency of the flash memory storage system is enhanced. | 10-28-2010 |
20100274950 | MEMORY SYSTEM - A controller executes first processing for writing a plurality of data in a sector unit in the first storing area; second processing for flushing the data stored in the first storing area to the first input buffer in a first management unit twice or larger natural number times as large as the sector unit; third processing for flushing the data stored in the first storing area to the second input buffer in a second management unit twice or larger natural number times as large as the first management unit; fourth processing for relocating a logical block in which all pages are written in the first input buffer to the second storing area; fifth processing for relocating a logical block in which all pages are written in the second input buffer to the third storing area; and sixth processing for flushing a plurality of data stored in the second storing area to the second input buffer in the second management unit. | 10-28-2010 |
20100274951 | ELECTRONIC STORAGE DEVICE WITH IMPROVED STORAGE METHOD - An electronic storage device includes a first memory segment having at least one source block to store information, a second memory segment having at least one backup block corresponding to the source block to make a backup of the information in a LSB memory page of the source block and a control unit connecting with said first memory segment and second memory segment. The control unit reads/writes the first memory segment and second memory segment through two different signal channels respectively. The information can be simultaneously written into the first and second memory segment to get a backup of the information so that the information can be stored safely. The control unit recycles the backup block of the second memory segment not only after the source block of the first memory segment entirely finishes writing the information but also after the source block is erased up in order to release the storage space of the backup block. | 10-28-2010 |
20100274952 | CONTROLLER, DATA STORAGE DEVICE AND DATA STORAGE SYSTEM HAVING THE CONTROLLER, AND DATA PROCESSING METHOD - A controller, a data storage device and a data storage system including the controller, and a data processing method are provided. The controller may process a plurality of instructions in parallel by including a plurality of address translation central processing units (CPUs) in a multi-channel parallel array structure, thereby improving the performance of a semiconductor memory system. | 10-28-2010 |
20100274953 | DATA STORAGE DEVICE AND INFORMATION PROCESSING SYSTEM INCORPORATING DATA STORAGE DEVICE - A data storage device comprises a plurality of memory devices and a memory controller. The memory controller exchanges data with the memory devices via a plurality of channels. The memory controller decodes an external command to generate a driving power mode and accesses the memory devices according to the driving power mode. | 10-28-2010 |
20100274954 | PROGRAM UPDATE SYSTEM AND ELECTRONIC DEVICE WITH PROGRAM UPDATE FUNCTION - A manufacturing cost of an integrated circuit chip used in a program update system or in an electronic device with program update function is reduced. A first integrated circuit chip has a USB interface circuit, a compression decoder, a CPU and a mask ROM. The first integrated circuit chip is a single chip consolidating a microcomputer with a USB host function and the compression decoder. A second integrated circuit chip has a CPU and an FROM, and serves as a system microcomputer to control the whole system of a car audio. A control program stored in the mask ROM is updated using the FROM incorporated in the second integrated circuit chip. | 10-28-2010 |
20100274955 | Flash Memory Storage System and Method - A flash memory storage system includes a memory array containing a plurality of memory cells and a controller for controlling the flash memory array. The controller dedicates a first group of memory cells to operate with a first number of bits per cell and a second, separate group of memory cells to operate with a second number of bits per cell. A mechanism is provided to apply wear leveling techniques separately to the two groups of cells to evenly wear out the memory cells. | 10-28-2010 |
20100274956 | SYSTEMS AND APPARATUS FOR MAIN MEMORY - A computing system is disclosed that includes a memory controller in a processor socket normally reserved for a processor. A plurality of non-volatile memory modules may be plugged into memory sockets normally reserved for DRAM memory modules. The non-volatile memory modules may be accessed using a data communication protocol to access the non-volatile memory modules. The memory controller controls read and write accesses to the non-volatile memory modules. The memory sockets are coupled to the processor socket by printed circuit board traces. The data communication protocol to access the non-volatile memory modules is communicated over the printed circuit board traces and through the sockets normally used to access DRAM type memory modules. | 10-28-2010 |
20100274957 | SYSTEM AND APPARATUS WITH A MEMORY CONTROLLER CONFIGURED TO CONTROL ACCESS TO RANDOMLY ACCESSIBLE NON-VOLATILE MEMORY - An apparatus includes a printed circuit board with a plurality of printed circuit board traces, a memory controller mounted on the printed circuit board coupled to one or more of the plurality of printed circuit board traces, a plurality of non-volatile type of memory integrated circuits coupled to the printed circuit board, and a plurality of support integrated circuits coupled between the memory controller and the plurality of non-volatile type of memory integrated circuits. | 10-28-2010 |
20100274958 | METHODS OF ASSEMBLY OF A COMPUTER SYSTEM WITH RANDOMLY ACCESSIBLE NON-VOLATILE MEMORY - An apparatus includes a printed circuit board with a plurality of printed circuit board traces, a memory controller mounted on the printed circuit board coupled to one or more of the plurality of printed circuit board traces, a plurality of non-volatile type of memory integrated circuits coupled to the printed circuit board, and a plurality of support integrated circuits coupled between the memory controller and the plurality of non-volatile type of memory integrated circuits. | 10-28-2010 |
20100281202 | WEAR-LEVELING AND BAD BLOCK MANAGEMENT OF LIMITED LIFETIME MEMORY DEVICES - Performing wear-leveling and bad block management of limited lifetime memory devices. A method for performing wear-leveling in a memory includes receiving logical memory addresses and applying a randomizing function to the logical memory addresses to generate intermediate addresses within a range of intermediate addresses. The intermediate addresses are mapped into physical addresses of a memory using an algebraic mapping. The physical addresses are within a range of physical addresses that include at least one more location than the range of intermediate addresses. The physical addresses are output for use in accessing the memory. The mapping between the intermediate addresses and the physical addresses is periodically shifted. In addition, contents of bad blocks are replaced with redundantly encoded redirection addresses. | 11-04-2010 |
20100281203 | Nonvolatile Memory Device and Method for Operating the Same - A nonvolatile memory device includes a selecting unit configured to select one of a read data or a program signal indicating a program period, an output unit configured to output an output signal of the selecting unit to the outside of a chip, and an output pin connected to the output unit. | 11-04-2010 |
20100281204 | MEMORY SYSTEM - A memory system includes a WC | 11-04-2010 |
20100281205 | Micro Control Module For Universal Connection And Universal Connection Method Thereof - A micro control module for universal connection and a universal connection method thereof are provided. The micro control module includes a supporting interface module, a micro control unit, and a memory unit. The micro control unit is configured to read interface-setting data saved in the supporting interface module and save the interface-setting data into the memory unit. When a wireless transmission module is electrically connected to the micro control module, the micro control unit generates an identification result, selects the appropriate interface-setting data from the memory unit, and reads the corresponding initialization data from the supporting interface module, so as to initialize the wireless transmission module. | 11-04-2010 |
20100281206 | METHOD OF CUSTOMIZING A MEMORY LIFESPAN MANAGEMENT POLICY IN AN ELECTRONIC TOKEN - The invention is a method of customizing a memory lifespan management policy of an electronic token. The electronic token is intended to be connected to a device able to establish a wireless channel. The electronic token has a microprocessor, a communication interface, a first memory intended to comprise said memory lifespan management policy, first means for exchanging data with a distant machine by means of a wireless channel established by said connected device, second means for applying said memory lifespan management policy in said electronic token, and third means for updating said memory lifespan management policy. Said method comprises the steps of—sending data from the distant machine to the electronic token by means of a wireless channel,—updating said memory lifespan management policy as a function of data received from said distant machine. | 11-04-2010 |
20100281207 | FLASH-BASED DATA ARCHIVE STORAGE SYSTEM - A flash-based data archive storage system having a large capacity storage array constructed from a plurality of dense flash devices is provided. The flash devices are illustratively multi-level cell (MLC) flash devices that are tightly packaged to provide a low-power, high-performance data archive system having substantially more capacity per cubic inch than more dense tape or disk drives. The flash-based data archive system may be adapted to employ conventional data de-duplication and compression methods to compactly store data. Furthermore, the flash-based archive system has a smaller footprint and consumes less power than the tape and/or disk archive system. | 11-04-2010 |
20100281208 | System and Method for Data Storage - A data storage architecture is composed of an array of a flash memory solid state disk and a hard disk drive or any nonvolatile random access storage that are intelligently coupled by an intelligent processing unit such as a multi-core graphic processing unit. The solid state disk stores seldom-changed and mostly read reference data blocks while the hard disk drive stores compressed deltas between currently accessed I/O blocks and their corresponding reference blocks in the solid state disk so that random writes are not performed on the solid state disk during online I/O operations. The solid state disk and hard disk drive are controlled by the intelligent processing unit, which carries out high speed computations including similarity detection and delta compression/decompression. The architecture exploits the fast read performance of solid state disks and the high speed computation of graphic processing units to replace mechanical operations on hard disk drives while avoiding slow and wearing solid state drive writes. | 11-04-2010 |
20100281209 | Press-Push Flash Drive Apparatus With Metal Tubular Casing And Snap-Coupled Plastic Sleeve - A press-push type computer peripheral “flash drive” device includes an elongated (e.g., metal) tubular casing containing a PCBA having a plug connector. A plastic housing assembly includes front and rear cap portions mounted over the open ends of the tubular casing, and a fixed plastic sleeve portion disposed in the tubular casing. The PCBA is secured to a plastic sliding rack structure that is disposed in the tubular casing and includes an actuating button protruding through a slot formed in a wall of the tubular casing. When the actuating button is manually pushed and slid along the slot, a portion of the sliding rack structure slides against the plastic sleeve portion in deploying and retracting the USB connector out of the device. | 11-04-2010 |
20100287328 | WEAR LEVELING TECHNIQUE FOR STORAGE DEVICES - A method for managing wear levels in a storage device having a plurality of data blocks, the method comprising moving data to data blocks having higher erasure counts based on a constraint on static wear levelness that tightens over at least a portion of the lives of the plurality of data blocks. | 11-11-2010 |
20100287329 | Partial Page Operations for Non-Volatile Memory Systems - A read command initiates reads of pages or portions of pages of non-volatile memory using a memory address that specifies a row, column and length. A host controller can use the read command with a read operation or status request. In some implementations, the memory address further specifies a die or plane and a block. | 11-11-2010 |
20100287330 | METHOD FOR WRITING DATA INTO FLASH MEMORY - Method for writing data into flash memory is disclosed. The method includes storing the frequently updated data and the not-aligned data collectively into some of the physical memory blocks of the flash memory. In other words, the method collectively writes those data into the same physical memory blocks of the flash memory as far as possible. By doing this, the invalid physical memory pages in the physical memory blocks can be generated collectively. As a result, the storage releasing efficiency of garbage collection can be greatly improved. | 11-11-2010 |
20100287331 | ELECTRONIC DEVICE AND METHOD FOR RECORDING POWER-ON TIME THEREOF - An electronic device and a method for recording power-on time include a flash memory to store a plurality of bits used to record power-on time. The electronic device sets the plurality of bits stored in the flash memory to a first value, sets a changing interval, and copies the plurality of bits from the flash memory to a random access memory (RAM). The electronic device further searches for a first bit of the first value from the plurality of bits in the RAM, and records an index of the first bit of the first value in a variable. The electronic device further changes the bit corresponding to the variable to a second value and increases the variable by 1 when the changing interval arrives. The electronic device further writes the bit changed to the second value from the RAM to the flash memory. | 11-11-2010 |
20100287332 | DATA STORING SYSTEM, DATA STORING METHOD, EXECUTING DEVICE, CONTROL METHOD THEREOF, CONTROL DEVICE, AND CONTROL METHOD THEREOF - A data storing system including: a non-volatile memory configured to have a plurality of memory blocks each capable of independently operating and allow random access to each of addresses; a controller configured to control writing of data to the non-volatile memory; and an executing unit configured to execute a predetermined application, wherein the executing unit decides the number of interleaves indicating the number of memory blocks operated in parallel among the plurality of memory blocks, and the executing unit notifies the controller of the decided number of interleaves. | 11-11-2010 |
20100287333 | DATA STORAGE DEVICE AND RELATED METHOD OF OPERATION - A data storage device comprises a plurality of memory devices, a buffer memory, and a controller. The plurality of memory devices are connected to a plurality of channels and a plurality of ways. The buffer memory temporarily stores data to be written in the memory devices. The controller stores the data in the buffer memory based on channel and way information of the memory devices. | 11-11-2010 |
20100287334 | ADDRESSING SCHEME TO ALLOW FLEXIBLE MAPPING OF FUNCTIONS IN A PROGRAMMABLE LOGIC ARRAY - A programmable processing device comprises a plurality of universal digital blocks (UDBs) in a UDB linear array. Each register in each UDB is associated with a plurality of memory addresses, where each memory address is from each of the different memory address spaces associated with different access mode widths of different digital peripheral functions. A digital peripheral function of an access mode width is mapped to one or more contiguous UDBs starting with a first UDB in the UDB linear array. Based on the access mode width, one of the associated memory addresses is chosen for the first UDB. | 11-11-2010 |
20100287335 | Read Enable Signal Adjusting Flash Memory Device and Read Control Method of Flash Memory Device - Disclosed is a flash memory device for adjusting a read signal timing and read control method of the flash memory device. The flash memory device includes a plurality of flash memory units, a common input/output bus connected with each of the plurality of flash memory units, and a controller to propagate the read control signal to a flash memory unit selected from among the plurality of flash memories and to receive data read from the selected flash memory unit via the common input/output bus, the controller being connected with the common input/output bus, wherein the controller adjusts a propagation timing of the read control signal unit based on a propagation delay corresponding to the selected flash memory unit, and thereby controlling a timing optimized for each flash memory unit. | 11-11-2010 |
20100293317 | PCM MEMORIES FOR STORAGE BUS INTERFACES - A memory controller for a phase change memory (PCM) that can be used on a storage bus interface is described. In one example, the memory controller includes an external bus interface coupled to an external bus to communicate read and write instructions with an external device, a memory array interface coupled to a memory array to perform reads and writes on a memory array, and an overwrite module to write a desired value to a desired address of the memory array. | 11-18-2010 |
20100293318 | METHOD FOR MEMORY MANAGEMENT - The invention relates to a method for memory management, in which memory usage data relating to the use of the memory is recorded. The memory usage data is determined in response to a number of memory write and/or read accesses. | 11-18-2010 |
20100293319 | Solid state drive device - The solid state drive device includes a memory device including a plurality of flash memories and a memory controller connected with a host and configured to control the memory device. The memory controller includes first and second cores, a host interface configured to interface with the host, and a flash memory controller configured to control the plurality of flash memories. The first core is configured to control transmission and reception of data to and from the host. The second core is configured to control transmission and reception of data to and from the memory device. | 11-18-2010 |
20100293320 | METHOD AND APPARATUS FOR BYTE-ACCESS IN BLOCK-BASED FLASH MEMORY - Techniques are described herein for managing data in a block-based flash memory device which avoid the need to perform sector erase operations each time data stored in the flash memory device is updated. As a result, a large number of write operations can be performed before a sector erase operation is needed. In addition, the block-based flash memory can emulate both programming and erasing on a byte-by-byte basis, like that provided by an EEPROM. | 11-18-2010 |
20100293321 | SYSTEMS AND METHOD FOR FLASH MEMORY MANAGEMENT - A system and method for merging sectors of a flash memory module, the method includes: receiving multiple sectors, each received sector is associated with a current erase block out of multiple (L) erase blocks; accumulating the received sectors in a sector buffer, the sector buffer is stored in a non-volatile memory module; maintaining a merged sector map indicative of a sectors of the sector buffer that have been merged and sectors of the sector buffer waiting to be merged; finding a first sector waiting to be merged according to the merged sector map; merging the first sector and other sectors that belong to a same erase block as the first sector; and updating the merged sector map to indicate that that the first second and the other sectors that belonged to the same erase block were merged. | 11-18-2010 |
20100293322 | SEMICONDUCTOR RECORDING APPARATUS AND SEMICONDUCTOR RECORDING SYSTEM - A semiconductor recording apparatus includes a logical-to-physical conversion table | 11-18-2010 |
20100293323 | Semiconductor and Flash Memory Systems - A flash memory device and a flash memory system are disclosed. The flash memory device includes a first non-volatile memory including a plurality of page data cells, storing page data, and reading and outputting the stored page data when a read command is applied from an external portion; and a second non-volatile memory including a plurality of spare data cells respectively adjacent to the plurality of page data cells, storing spare data, scanning the spare data and temporarily storing corresponding information when a file system is mounted, reading and outputting the stored spare data when the read command is applied. | 11-18-2010 |
20100293324 | DIRECT LOGICAL BLOCK ADDRESSING FLASH MEMORY MASS STORAGE ARCHITECTURE - A nonvolatile semiconductor mass storage system and architecture can be substituted for a rotating hard disk. The system and architecture avoid an erase cycle each time information stored in the mass storage is changed. Erase cycles are avoided by programming an altered data file into an empty mass storage block rather than over itself as a hard disk would. Periodically, the mass storage will need to be cleaned up. These advantages are achieved through the use of several flags, and a map to correlate a logical block address of a block to a physical address of that block. In particular, flags are provided for defective blocks, used blocks, and old versions of a block. An array of volatile memory is addressable according to the logical address and stores the physical address. | 11-18-2010 |
20100299474 | INFORMATION PROCESSING APPARATUS, MEDIA DRIVE AND MEDIA DATA CACHING MANAGEMENT METHOD IN INFORMATION PROCESSING APPARATUS - According to one embodiment, an information processing apparatus includes a first caching processing module which starts a caching moving image data stored in a storage medium in a memory device when the storage medium is loaded in a media drive, and a second caching processing module which erases all of moving image data items cached in the memory device when the storage medium is ejected from the media drive. | 11-25-2010 |
20100299475 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND WRITE-IN METHOD THEREOF - A non-volatile semiconductor memory device, comprising: a non-volatile memory array, storing multi-values by setting a plurality of different threshold voltages for each memory cell, and a control circuit, controlling a write-in operation to the memory cell array. When data have been written into the memory cell, the control circuit selects an adjacent word line, uses an erasing level to perform write-in which is weaker than the data write-in, and verifies soft programming of the amount of one page, such that a narrow-banded erasing level distribution is realized in an adjacent memory cell. | 11-25-2010 |
20100299476 | MASS MEMORY DEVICE AND STORAGE SYSTEM - A mass memory device is disclosed as including a memory module, a management module for physical management of the memory module, and a control module for controlling the management module. The management module is connected for communication with the control module by an MII-family bus. | 11-25-2010 |
20100306447 | DATA UPDATING AND RECOVERING METHODS FOR A NON-VOLATILE MEMORY ARRAY - Methods for updating and recovering user data of a non-volatile memory array such as a flash memory are disclosed. An indication for indicating a mapping relationship for a logical address is established when original user data of the logical addresses is updated into new user data. The indication records new pointers, which record the mapping relationships between logical addresses and physical addresses storing the new user data of the logical addresses. Alternatively, the indication records memory positions of the non-volatile memory array which are defined as designated memory positions and a sequence for using these designated memory positions. | 12-02-2010 |
20100306448 | CACHE AUTO-FLUSH IN A SOLID STATE MEMORY DEVICE - A device, system and method in which data in a write cache, that must at some point be written to non-volatile memory, is written to non-volatile memory after expiration of a threshold time period during which no new host commands are received. If either the last dirty entry is written back or a host command is received during the write-back process, the time threshold time period and auto-flush process is restarted. | 12-02-2010 |
20100306449 | Transportable Cache Module for a Host-Based Raid Controller - In accordance with the present disclosure, a system and method for an information handling system having transportable cache module is disclosed herein. The information handling system has a memory controller coupled to a central processing unit and a plurality of memory modules. The transportable cache module has a protected memory module, a nonvolatile memory module, a module controller, and an independent power source. The module controller is operative to copy a protected memory region from the protected memory module to a nonvolatile memory region on the nonvolatile memory module. The independent power source is operative to supply power to the protected memory module, the nonvolatile memory module, and the module controller. | 12-02-2010 |
20100306450 | SECURE DELIVERY OF DIGITAL MEDIA VIA FLASH DEVICE - A flash device for secure delivery of media content is provided. The flash device can include a controller module and a memory module. The controller module can include at least one local central processing unit, at least one register having factory initialized data written therein, and at least one memory module interface. The factory initialized data can include: a vendor identification (“VID”) string, a product identification (“PID”) string, and a manufacturer identification string. The memory module can include at least one read-only partition having digital data disposed therein, where at least a portion of the digital data comprises at least one machine executable instruction set. | 12-02-2010 |
20100306451 | ARCHITECTURE FOR NAND FLASH CONSTRAINT ENFORCEMENT - Described embodiments provide for constraint checking for constraints imposed on NAND flash devices. An exemplary implementation of a computing environment comprises at least one NAND data storage device. In the illustrative implementation, the data processing and storage management paradigm allows for the storage of data according using a selected constraint enforcement algorithm. A NAND data storage constraint checking module can be operable to enforce one or more selected device constraints with one or more co-operating components to the NAND data store. | 12-02-2010 |
20100306452 | MULTI-MAPPED FLASH RAID - Disclosed is a storage system. The storage system includes a redundant array of inexpensive disks (RAID) controller. The RAID controller includes a flash memory controller coupled to a flash memory. The flash memory controller may perform background management tasks. These include logging and error reporting, address translation, cache table management, bad block management, defect management, wear leveling, and garbage collection. The array controller also allows the flash memory to be divided into multiple mappings. | 12-02-2010 |
20100306453 | METHOD FOR OPERATING A PORTION OF AN EXECUTABLE PROGRAM IN AN EXECUTABLE NON-VOLATILE MEMORY - A method for operating at least a portion of an executable program in an executable non-volatile memory is described. The method includes determining, by a user input, at least a portion of an executable program for pinning in the executable non-volatile memory. The portion of the executable program is pinned to the executable non-volatile memory. The portion of the executable program is then executed from the executable non-volatile memory. | 12-02-2010 |
20100306454 | ELECTRONIC DEVICES AND OPERATION METHODS OF A FILE SYSTEM - An operation method of file system includes retrieving the first header of the first file, adding the auxiliary data to the first header to generate the second header, writing the dummy data into the second header to adjust the data length of the second header, thereby serving as the third header, and modifying the link relation of clusters recorded in the file allocation table such that the third header and the second data segment are linked together, thereby generating the second file. | 12-02-2010 |
20100306455 | METHOD FOR MANAGING A PLURALITY OF BLOCKS OF A FLASH MEMORY, AND ASSOCIATED MEMORY DEVICE AND CONTROLLER THEREOF - A method for managing a plurality of blocks of a Flash memory includes: sieving out at least one first block having invalid pages from the plurality of blocks; and moving data of a portion of valid pages of the first block to a second block, where data of all valid pages of the first block is not moved to the second block at a time. An associated memory device and a controller thereof are also provided, where the controller includes: a ROM arranged to store a program code; and a microprocessor arranged to execute the program code to control the access to the Flash memory and manage the plurality of blocks. The controller that executes the program code by utilizing the microprocessor sieves out the first block from the plurality of blocks, and moves the data of the portion of valid pages of the first block to the second block. | 12-02-2010 |
20100306456 | METHOD FOR EVEN UTILIZATION OF A PLURALITY OF FLASH MEMORY CHIPS - A method for addressing a memory having a plurality of flash memory chips organized in erasable blocks, which in turn contain writable sectors, and where an erase counter is associated with each memory block. The overwriting of the sectors occurs by way of alternative memory blocks searched in the same chip for low erase counter values, as long as a threshold value of the erase counter is not exceeded. The copying operations are conducted efficiently using a copy command internal to the memory chip. As soon as the threshold value is exceeded, alternative memory blocks are searched in other memory chips as well. | 12-02-2010 |
20100312947 | Apparatus and method to share host system ram with mass storage memory ram - A method includes, in one non-limiting embodiment, sending a request from a mass memory storage device to a host device, the request being one to allocate memory in the host device; writing data from the mass memory storage device to allocated memory of the host device; and subsequently reading the data from the allocated memory to the mass memory storage device. The memory may be embodied as flash memory, and the data may be related to a file system stored in the flash memory. The method enables the mass memory storage device to extend its internal volatile RAM to include RAM of the host device, enabling the internal RAM to be powered off while preserving data and context stored in the internal RAM. | 12-09-2010 |
20100312948 | MEMORY SYSTEM - A memory system includes a DRAM | 12-09-2010 |
20100312951 | METHOD, DEVICE AND DATA STRUCTURE FOR DATA STORAGE ON MEMORY DEVICES - A method is provided for storing data on memory devices comprising a plurality of erasable units, wherein the size of said erasable units is an integer multiple of a first integer value, comprising providing a data structure comprising a plurality of data units each including a data unit header, wherein the size of said data units is equal to said first integer value, a plurality of data items and corresponding data item headers within each data unit, associating at least one data unit to each erasable unit, storing said data in said data items and storing data item status information in the corresponding data item headers, and storing data unit status information in said data unit headers. | 12-09-2010 |
20100312952 | Multiprocessor System Having an Input/Output (I/O) Bridge Circuit for Transferring Data Between Volatile and Non-Volatile Memory - A disclosed circuit includes circuitry for coupling to a volatile memory, circuitry for coupling to a nonvolatile NAND flash memory, and circuitry that: (i) receives a volatile memory request from a processor and satisfies the volatile memory request by accessing the volatile memory, and (ii) receives a nonvolatile NOR flash memory read request from the processor and satisfies the NOR read request by accessing both the NAND flash memory and the volatile memory. The circuit may also include circuitry that receives a volatile memory request from another processor and satisfies the volatile memory request from the other processor by accessing the volatile memory, and circuitry that receives a NAND flash memory read request from the other processor and satisfies the NAND read request by accessing the NAND flash memory. Multiprocessor systems including the circuit are described, as is a method for satisfying a NOR flash memory read request. | 12-09-2010 |
20100312953 | METHOD AND APPARATUS FOR REDUCING WRITE CYCLES IN NAND-BASED FLASH MEMORY DEVICES - A NAND-based flash memory device and a method of its operation that extends the life of the device by reducing the number of unnecessary write cycles to the device. The memory device includes blocks, pages contained by each of the blocks, and a page abstraction layer containing a look-up table for translating logical page numbers into physical page numbers. A certain number of the pages in at least one of the blocks is preferably reserved so as not to be used in default data storage mode but instead used to shuffle data within the at least one block using a dynamic page address scheme, whereby data are dynamically moved from one page to an empty page in the same block using dynamic page mapping. | 12-09-2010 |
20100312954 | Multi-Chip Semiconductor Devices Having Non-Volatile Memory Devices Therein - A flash memory device and a flash memory system are disclosed. The flash memory device includes a first non-volatile memory including a plurality of page data cells, storing page data, and reading and outputting the stored page data when a read command is applied from an external portion; and a second non-volatile memory including a plurality of spare data cells respectively adjacent to the plurality of page data cells, storing spare data, scanning the spare data and temporarily storing corresponding information when a file system is mounted, reading and outputting the stored spare data when the read command is applied. | 12-09-2010 |
20100318718 | MEMORY DEVICE FOR A HIERARCHICAL MEMORY ARCHITECTURE - A hierarchical memory device having multiple interfaces with different memory formats includes a Phase Change Memory (PCM). An input port and an output port connect the hierarchical memory device in a daisy-chain hierarchy or a hierarchical tree structure with other memories. Standard non-hierarchical memory devices can also attach to the output port of the hierarchical memory device. | 12-16-2010 |
20100318719 | METHODS, MEMORY CONTROLLERS AND DEVICES FOR WEAR LEVELING A MEMORY - The present disclosure includes methods, memory controllers and devices for wear leveling a memory. One method embodiment includes selecting, in at least a substantially random manner, a number of memory locations as at least a portion of a sample subset, the sample subset including fewer than all memory locations of the memory. A memory location having a particular wear level characteristic is identified from among the sample subset of memory locations, and data is written to the memory location identified from among the sample subset. | 12-16-2010 |
20100318720 | Multi-Bank Non-Volatile Memory System with Satellite File System - A multi-bank non-volatile memory system is presented. A first of the banks has a main copy of the file system and each of the other banks has a satellite copy of the file system. The back end firmware of the controller executes a thread for each of the banks. After the boot process, during normal memory operations, each of the threads can operate using its own copy of the file system without interrupting the other threads in order to access the file system. | 12-16-2010 |
20100318721 | PROGRAM FAILURE HANDLING IN NONVOLATILE MEMORY - In a nonvolatile memory system, data received from a host by a memory controller is transferred to an on-chip cache, and new data from the host displaces the previous data before it is written to the nonvolatile memory array. A safe copy is maintained in on-chip cache so that if a program failure occurs, the data can be recovered and written to an alternative location in the nonvolatile memory array. | 12-16-2010 |
20100318722 | DATA INTERLEAVING METHOD FOR STORAGE DEVICE AND RELATED STORAGE DEVICE - The present invention provides a data interleaving method for a storage device and a related storage device. The storage device comprises a plurality of non-volatile memory units, a buffer, and a processing unit. The method comprises: transmitting a plurality of first data required to be written to the plurality of non-volatile memory units to the buffer one by one; and respectively performing a plurality of interleaving operations to transmit the plurality of first data received by the buffer in sequence to the plurality of non-volatile memory units, respectively. The data interleaving method and the related storage device of the present invention only has to use one buffer, and thus the data interleaving method and the related storage device of the present invention can reduce requirement of buffer memory. | 12-16-2010 |
20100318723 | MEMORY CONTROLLER, NONVOLATILE MEMORY DEVICE, AND NONVOLATILE MEMORY SYSTEM - A nonvolatile memory device includes a plurality of memory controllers. Each of the memory controllers has an aggregation processing part and an aggregation synchronization part. Based on a signal from the aggregation synchronization part, the aggregation processing part aggregates valid data of a temporary physical block into another physical block. When one of the memory controllers requires an aggregation process, the aggregation synchronization part sends a synchronization signal to the other memory controller, so that the aggregation process is simultaneously carried out by the other memory controller. Thus, in the nonvolatile memory device having a plurality of memory controllers, it is possible to reduce the time required for the aggregation process and carry out a high-speed writing process. | 12-16-2010 |
20100318724 | FLASH MEMORY CONTROL CIRCUIT, FLASH MEMORY STORAGE SYSTEM, AND DATA TRANSFER METHOD - A flash memory control circuit including a microprocessor unit, a first interface unit, a second interface unit, a buffer memory, a memory management unit, and a data read/write unit is provided. The memory management unit manages a plurality of flash memory units, wherein each of the flash memory units has a plurality of flash memories, each of the flash memories has a plurality of memory cell arrays, and each of the memory cell arrays at least has an upper page and a lower page. The memory management unit groups the memory cell arrays of the corresponding flash memories into a plurality of data transfer unit sets (DTUSs). The data read/write unit interleavingly transfers data to the flash memory units in units of the DTUSs. Thereby, the flash memory control circuit can transfer the data stably and the usage of the buffer memory can be reduced. | 12-16-2010 |
20100318725 | Multi-Processor System Having Function of Preventing Data Loss During Power-Off in Memory Link Architecture - Exemplary embodiments relate to a multi-processor system including: a first processor for writing a power-off check command to a first mail box, reading a power-off wait message or a power-off allowance message written to a second mail box, and waiting or turning off the multi-processor system, in a power-off operation mode; a second processor for indicating whether data is completely stored during a current processing operation in response to the power-off check command in the first mail box and writing the power-off wait message or the power-off allowance message to the second mail box according to the indication result; and a multi-port semiconductor memory device having an internal register that includes the first and second mail boxes and dedicated and shared memory areas for data processing. The first and second mail boxes serve as latch storage units, and the dedicated and shared memory areas are accessed by the first and second processors. | 12-16-2010 |
20100318726 | MEMORY SYSTEM AND MEMORY SYSTEM MANAGING METHOD - Correspondences between logical blocks and physical blocks of first and second memories are controlled such that an identical logical block is subject to correspondence with a physical block of the first memory and to a physical block of the second memory, and data is stored in the physical blocks subject to correspondence with the identical logical block such that pages that contain data do not overlap between the physical blocks so that operation performed on the first memory and operation performed on the second memory can be performed in parallel, thereby achieving speedup and an increase in efficiency in data writing to non-volatile memory, to which overwriting is inapplicable and to which writing involves block-to-block data move. | 12-16-2010 |
20100318727 | MEMORY SYSTEM AND RELATED METHOD OF LOADING CODE - A memory system comprises a processor, a main memory comprising a volatile random access memory (RAM) that stores data to be accessed by the processor and a nonvolatile memory that provides a swap space for the RAM, and a disk that provides data transfer to the RAM with a greater latency than the nonvolatile memory. | 12-16-2010 |
20100318728 | SOLID STATE DRIVE DEVICE - A solid state drive (SSD) device is provided. The SSD device includes: a first memory device storing data; a memory controller, connected to a host, and controlling the memory device; and a security device encoding and storing the data using a key and decoding the stored data using the key, wherein the security device stores the key and is detachable from the memory controller. | 12-16-2010 |
20100318729 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A NAND type flash memory having a program verifying function is provided, which can search for stored data at high speed. The flash memory reads search data that corresponds to stored data stored in a block in a front page of the block in a reverse-order search mode, compares the search data with the non-search data from a controller, and returns a block address and a page address of the search data that matches with the non-search data to the controller. At this time, the flash memory checks the match between the search data and the non-search data by comparing “0” data using the program verifying function provided in the flash memory itself. | 12-16-2010 |
20100318730 | Dual Channel Memory Architecture Having Reduced Interface Pin Requirements Using a Double Data Rate Scheme for the Address/Control Signals - Apparatuses and methods for dual channel memory architecture with reduced interface pin requirements are presented. One memory architecture includes a memory controller, a first memory device coupled to the memory controller by a shared address bus and a first clock signal, and a second memory device coupled to the memory controller by the shared address bus and a second clock signal, where the polarity of the second clock signal is opposite of the first clock signal. A method for performing data transactions is presented. The method includes providing addressing signals over a shared address bus to a first memory device and a second memory device, providing clock signals to the memory devices which are reversed in polarity, where the clock signals are derived from a common clock signal, and transferring data to the memory devices over separate narrow data buses in an alternating manner based upon the clock signals. | 12-16-2010 |
20100325339 | STORAGE SYSTEM AND METHOD FOR CONTROLLING THE SAME - Optimum load distribution processing is selected and executed based on settings made by a user in consideration of load changes caused by load distribution in a plurality of asymmetric cores. | 12-23-2010 |
20100325340 | Memory Wear Control - The disclosure is related to systems and methods of controlling wear of a memory. In a particular embodiment, a system is disclosed that comprises a memory and a performance governor circuit coupled to the memory. The performance governor circuit is adapted to control a wear of the memory as a function of time. | 12-23-2010 |
20100325341 | Memory Device and Memory Interface - Memory devices and memory interfaces are disclosed. In an implementation a memory controller of a memory device is configured to receive a first part of an address for memory access, and to perform a memory access based on said first part and a part of a previously received address. | 12-23-2010 |
20100325342 | MEMORY CONTROLLER AND NONVOLATILE STORAGE DEVICE USING SAME - In a controller (memory controller) ( | 12-23-2010 |
20100325343 | MEMORY SYSTEM - This disclosure concerns a memory system including: chips (MC | 12-23-2010 |
20100325344 | DATA WRITING METHOD FOR FLASH MEMORY AND CONTROL CIRCUIT AND STORAGE SYSTEM USING THE SAME - A data writing method for writing data into a flash memory chip is provided, wherein the flash memory chip includes a plurality of physical units. The data writing method includes providing a flash memory control circuit and configuring a plurality of logical units, wherein each logical unit is mapped to at least one physical unit. The data writing method also includes configuring a plurality of logical addresses and mapping the logical addresses to the logical units, wherein at least one logical unit is mapped to at least two non-continuous logical addresses. The data writing method further includes writing the data from a host system into the corresponding physical units according to the logical units mapped to the logical addresses through the flash memory control circuit. Thereby, the data to be moved while writing data into the physical units is reduced, and accordingly the data writing speed is effectively increased. | 12-23-2010 |
20100325345 | METHOD FOR MANAGING STORAGE SYSTEM USING FLASH MEMORY, AND COMPUTER - To facilitate the management of a storage system that uses a flash memory as a storage area. A controller of the storage system provided with a flash memory chip manages a surplus capacity value of the flash memory chip, and transmits a value based on the surplus capacity value to a management server, on the basis of at least one of a definition of a parity group, a definition of an internal LU, and a definition of a logical unit. The management server displays a state of the storage system by using the received value based on the surplus capacity value. | 12-23-2010 |
20100325346 | PARALLEL FLASH MEMORY CONTROLLER, CHIP AND CONTROL METHOD THEREOF - A parallel flash memory controller, a chip, and a control method thereof are disclosed. First, an on-chip control bus sends flash memory control instructions in parallel to instruction parsing units ( | 12-23-2010 |
20100325347 | APPARATUS FOR CONTROLLING NAND FLASH MEMORY - Provided is an apparatus for controlling NAND flash memory. The apparatus for controlling NAND flash memory includes: a register unit in which a start address of a macro-command to be executed, selected from macro-commands included in a command script in which at least one macro-command in which a plurality of micro-commands for controlling a unit operation of NAND flash memory are arranged in an array shape, is described, is recorded; a command fetch unit, if a start address of the macro-command to be executed is recorded in the register unit, accessing first memory connected based on the start address of the macro-command to be executed and sequentially reading the plurality of micro-commands from the start address of the macro-command to be executed; a command interpretation unit interpreting the read micro-commands and outputting the result of interpretation including types of the micro-commands and command parameters; and a command execution unit generating interface signals for controlling an operation of NAND flash memory according to each of the micro-commands based on the result of interpretation. Time required for data transmission and NAND flash control can be reduced, and a high performance can be obtained. | 12-23-2010 |
20100325348 | DEVICE OF FLASH MODULES ARRAY - This invention provides a device of Flash Modules Array or Flash Array (FA) for short, with a higher capacity, higher speed and lower power consumption. A device of flash array comprises: a one or more physical I/O interfaces, for performing data transmission with the outside or upstream; one or more ports for flash modules consisting of multiple flash memory modules, a flash array controller, set between the physical I/O interface and the flash modules, further including: a block mapping unit, for performing the address mapping between the logical address which is transmitted between the physical I/O interface and the outside and the physical address which is transmitted between the physical I/O interface and the flash array. The invention is applied in the field of flexible solid state storage device. | 12-23-2010 |
20100325349 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device, includes a plurality of flash memories and a controller for the flash memories. The flash memory includes a data cache operable to hold data for at least one record page in writing, the flash memory includes a plurality of erasure blocks each having a plurality of record pages, the record page is classified into a first record page and a second record page of which write time is longer than a write time of the first record page, and the controller for the flash memories is configured to: divide the plurality of flash memories into at least two groups; perform write control by interleaving data in the groups for each record page; determine whether a page to be written data is of the first record page or the second record page; and when it is determined that the page to be written data is the first record page, after a lapse of a first predetermined time from start of writing data of one of the groups, the controller starts writing data of another one of the groups, and when it is determined that the page to be written data is the second record page, after a lapse of a second predetermined time being longer than the first predetermined time from start of writing data of one of the groups, the controller starts writing data of another one of the groups. | 12-23-2010 |
20100325350 | SEMICONDUCTOR DEVICE - In executing an EEPROM emulation by a flash memory incorporated in a semiconductor device, there is a problem that the data holding period of the flash memory is shorter than the EEPROM. The flash memory manages data by block unit. Therefore, it is required to securely perform a block change before the specification of the data holding period of the flash memory passes. For satisfying this problem, for an EEPROM substitution area in a flash memory, a data level check voltage is set between an internal verification voltage and a read-out voltage. When data level becomes below the data level check voltage, the block change is performed. | 12-23-2010 |
20100325351 | MEMORY SYSTEM HAVING PERSISTENT GARBAGE COLLECTION - Non-volatile memory systems such as those using NAND FLASH technology have a property that a memory location can be written to only once prior to being erased, and a contiguous group of memory locations need to be erased simultaneously. The process of recovering space that is no longer being used for storage of current data, called garbage collection, may interfere with the rapid access to data in other memory locations of the memory system during the erase period. The effects of garbage collection on system performance may be mitigated by performing portions of the process contemporaneously with the user initiated reading and writing operations. The memory circuits and the data may also be configured such that the data is stored in stripes of a RAID array and the scheduling of the erase operations may be arranged so that the erase operations for garbage collection are hidden from the user operations. | 12-23-2010 |
20100325352 | HIERARCHICALLY STRUCTURED MASS STORAGE DEVICE AND METHOD - A hierarchically-structured computer mass storage system and method. The mass storage system includes a mass storage memory drive, control logic on the mass storage memory drive that includes a controller and one or more devices for executing a hierarchical storage management technique, a volatile memory cache configured to be accessed by the control logic, and first and second non-volatile storage arrays on the mass storage memory drive and comprising, respectively, first and second non-volatile memory devices. The first and second non-volatile memory devices have properties including access times and write endurance, and at least one of the access time and the write endurance of the first non-volatile memory devices is faster or higher, respectively, than the second non-volatile memory devices. Desired data storage localities on the storage arrays are determined through access patterns and selectively utilizing the properties of the memory devices to match the data storage requirements. | 12-23-2010 |
20100325353 | FLASH MEMORY SYSTEM CONTROL SCHEME - A Flash memory system architecture having serially connected Flash memory devices to achieve high speed programming of data. High speed programming of data is achieved by interleaving pages of the data to be programmed amongst the memory devices in the system, such that different pages of data are stored in different memory devices. A memory controller issues program commands for each memory device. As each memory device receives a program command, it either begins a programming operation or passes the command to the next memory device. Therefore, the memory devices in the Flash system sequentially program pages of data one after the other, thereby minimizing delay in programming each page of data into the Flash memory system. The memory controller can execute a wear leveling algorithm to maximize the endurance of each memory device, or to optimize programming performance and endurance for data of any size. | 12-23-2010 |
20100325354 | MECHANISM TO HANDLE EVENTS IN A MACHINE WITH ISOLATED EXECUTION - A platform and method for secure handling of events in an isolated environment. A processor executing in isolated execution “IsoX” mode may leak data when an event occurs as a result of the event being handled in a traditional manner based on the exception vector. By defining a class of events to be handled in IsoX mode, and switching between a normal memory map and an IsoX memory map dynamically in response to receipt of an event of the class, data security may be maintained in the face of such events. | 12-23-2010 |
20100332725 | PINNING CONTENT IN NONVOLATILE MEMORY - Systems and methods relating to pinning selected data to sectors in non-volatile memory. A graphical user interface allows a user to specify certain data (e.g., directories or files) to be pinned. A list of pinned sectors can be stored so that a driver or controller that operates on a sector basis and not a file or directory basis can identify data to be pinned. | 12-30-2010 |
20100332726 | STRUCTURE AND METHOD FOR MANAGING WRITING OPERATION ON MLC FLASH MEMORY - A method for managing a writing operation for a multi-level cell (MLC) nonvolatile memory by a host is provided. The MLC nonvolatile memory has a plurality of MLC blocks, each MLC cell of each MLC block can store multiple logical data bits. The method includes forming a turbo writing unit from the spare block pool; writing a data sent by the host to the turbo writing unit; and changing the role of the turbo writing unit into a turbo data unit. The turbo writing unit is formed with at least one of the MLC blocks, each MLC cell of the at least one of the MLC blocks stores a portion of the logical data bits the MLC cell is capable of storing. | 12-30-2010 |
20100332727 | EXTENDED MAIN MEMORY HIERARCHY HAVING FLASH MEMORY FOR PAGE FAULT HANDLING - A computer system with flash memory in the main memory hierarchy is disclosed. In an embodiment, the computer system includes at least one processor, a memory management unit coupled to the at least one processor, and a random access memory (RAM) coupled to the memory management unit. The computer system may also include a flash memory coupled to the memory management unit, wherein the computer system is configured to store at least a subset of a plurality of pages in the flash memory during operation. Responsive to a page fault, the memory management unit may determine, without invoking an I/O driver, if a requested page associated with the page fault is stored in the flash memory and further configured to, if the page is stored in the flash memory, transfer the page into RAM. | 12-30-2010 |
20100332728 | SYSTEM AND METHOD OF SELECTING A FILE PATH OF A REMOVABLE STORAGE DEVICE - Systems and methods of identifying a file path of a removable storage device are disclosed. A method includes, at a host device that is coupled to the removable storage device, selecting a file path that is associated with the removable storage device by accessing a size associated with a root directory accessible to the host device, where the root directory corresponds to the removable storage device. The file path is selected based upon the size associated with the root directory. The selected file path is verified by initiating a memory access operation using the selected file path. | 12-30-2010 |
20100332729 | MEMORY OPERATIONS USING LOCATION-BASED PARAMETERS - Systems and methods of performing memory operations using location-based parameters are disclosed. A method includes identifying a first set of parameter values associated with a first physical block of a memory array. The first set of parameter values is identified based on a first physical location of the first physical block. A memory access operation is initiated with respect to the first physical block in accordance with the first set of parameter values. | 12-30-2010 |
20100332730 | METHOD AND SYSTEM FOR MANAGING A NAND FLASH MEMORY - A method and system to facilitate paging of one or more segments of a logical-to-physical (LTP) address mapping structure to a non-volatile memory. The LTP address mapping structure is part of an indirection system map associated with the non-volatile memory in one embodiment of the invention. By allowing one or more segments of the LTP address mapping structure to be paged to the non-volatile memory, the amount of volatile memory required to store the LTP address mapping structure is reduced while maintaining the benefits of the LTP address mapping structure in one embodiment of the invention. | 12-30-2010 |
20100332731 | FLASH MEMORY APPARATUS AND METHOD FOR OPERATING THE SAME AND DATA STORAGE SYSTEM - A flash memory apparatus is provided. In one embodiment, the flash memory apparatus with a plurality of operation states is coupled to a host and includes a controller having an engine and a register array. A state machine logic circuit of the engine is provided for transition of the operation states and the register array provides state transition information. When a command is received from the host, the engine obtains the state transition information from the register array according to a first operation state and determines whether the valid command is one of a plurality of valid commands corresponding to the first operation state. The state machine logic circuit determines transition to the operation states according to the state transition information. The transition of the first operation state to the second operation state is performed in response to the valid command. | 12-30-2010 |
20100332732 | MEMORY SYSTEMS AND MAPPING METHODS THEREOF - Memory systems and mapping methods thereof are provided. In one embodiment of a memory system, an interface device is coupled between a flash memory and a host and stores a flash translation layer. The flash translation layer utilizes a data block mapping table and a page mapping table to manage data blocks and log blocks of the flash memory by a page mapping scheme and utilizes a random write page mapping table independent from the block mapping table and the page mapping table to manage the random write blocks by a random write mapping scheme. When a first predetermined condition is satisfied, the flash translation layer converts one of the data blocks (and one of the log block corresponding to the converted data block if any) into random write block(s) and utilizes the random write mapping schemes to manage the random write block(s). When a second predetermined condition is satisfied, the flash translation layer merges and converts random write block(s) into a data block and utilizes the page mapping scheme to manage the converted random write block(s). | 12-30-2010 |
20100332733 | MATERIAL SERVER AND METHOD OF STORING MATERIAL - According to one embodiment, a material server that includes a NAND flash memory which stores material that includes one or all of moving image data, audio data, and ANC data. A material ID detector detects a material ID in inputted material when such material is inputted into the material server. A block allocation unit in the material server allocates a block for storing the material each material ID. A plurality of buffers in the material server buffer the material each inputted material ID. A buffering data monitor in the material server monitors buffering data size in the buffers. A memory accessing unit in the material server writes buffered material to the NAND memory when a buffering data monitor detects that the buffering data size amounts to one page size. | 12-30-2010 |
20100332734 | FLASH MEMORY DEVICES AND METHODS FOR CONTROLLING A FLASH MEMORY DEVICE - A flash memory device includes a memory array and a memory control circuit. The memory array includes memory modules. Each memory module is located in a memory channel and includes a predetermined number of memory cells. The memory control circuit is coupled to the memory array via an address latch enable (ALE) pin and a command latch enable (CLE) pin. The ALE pin and the CLE pin are coupled to all of the memory cells and shared by all of the memory cells in the memory array. | 12-30-2010 |
20100332735 | FLASH MEMORY DEVICE AND METHOD FOR PROGRAMMING FLASH MEMORY DEVICE - A flash memory device resilient to bit errors and a programming method suitable for the flash memory are provided. The flash memory device stores data in a parallel manner in a superpage which is generated by grouping a plurality of physical pages into a logical page. The flash memory device spreads input data using a predetermined spreading code to generate spread data. The spread data is stored on a superpage-by-superpage basis. | 12-30-2010 |
20100332736 | METHOD OF OPERATING NONVOLATILE MEMORY DEVICE - A method of programming a nonvolatile memory device comprises storing first data of a first memory block in a page buffer unit, and then programming the first data into a redundant memory block coupled to the page buffer unit, storing second data of a second memory block in the page buffer unit, and then programming the second data into the first memory block, storing third data of a third memory block in the page buffer unit, and then programming the third data into the second memory block, storing the second data of the first memory block in the page buffer unit, and then programming the stored second data into the third memory block, and storing the first data stored in the redundant memory block in the page buffer unit, and then programming the stored first data into the first memory block. | 12-30-2010 |
20100332737 | FLASH MEMORY PREPROCESSING SYSTEM AND METHOD - A flash memory preprocessing system comprises at least one flash memory device, a memory controller controlling program and read operations of the at least one flash memory device, and a flash preprocessor receiving program data from an external source, generating preprocessed data by converting the received program data, and outputting the preprocessed data to the memory controller. The memory controller controls the at least one flash memory device to perform a program operation on the at least one flash memory device according to the preprocessed data. | 12-30-2010 |
20100332738 | STORAGE DEVICE AND DATA PROCESSING METHOD - A storage device for connecting to a host system includes a flash memory and a controller coupled to the flash memory. The flash memory includes a plurality of memory blocks. The controller writes test data to the flash memory, and compares the test data read from the flash memory with the original test data to generate a bit error message corresponding to the flash memory. Then, the controller chooses and labels a quick read block from the plurality of memory blocks according to the bit error message, and finally writes a specific file to the quick read block. | 12-30-2010 |
20100332739 | Storage device, storage controlling device, and storage controlling method - A storage device includes a programmable device into which predetermined control data is written, a control data storing unit that stores therein write control data and read control data, the write control data being control data for realizing a function to save data stored in a cache memory into a nonvolatile memory when an abnormal shut-down occurs and the read control data being control data for realizing a function to restore the data saved in the nonvolatile memory into the cache memory when an electric power source is turned on after the abnormal shut-down, a writing unit that, when an electric power source is turned on after occurrence of the abnormal shut-down of the storage device, writes the read control data into the programmable device, and a restoring instructing unit that instructs the programmable device to restore the data saved in the nonvolatile memory into the cache memory. | 12-30-2010 |
20100332740 | ZONED INITIALIZATION OF A SOLID STATE DRIVE - Zoned initialization of a solid state drive is provided. A solid state memory device includes a controller for controlling storage and retrieval of data to and from the device. A set of solid state memory components electrically coupled to the controller. The set is electrically divided into a first zone and a second zone, wherein the first zone is at least partially initialized independent from the second zone. An interface is coupled between the controller and the set of solid state memory components to facilitate transfer of data between the set of solid state memory components and the controller. | 12-30-2010 |
20100332741 | Interleaving Policies for Flash Memory - Articles and associated methods and systems relate to selecting read interleaving policies independently of selecting write interleaving policies. In various implementations, the selection may be static or dynamic during operation. In implementations that dynamically select read interleaving policies and write interleaving policies, the selection may be based on various operating conditions, such as temperature, power source, battery voltage, and operating mode. Examples of operating modes may include (1) reading or writing to flash memory when connected to an external power source, (2) reading from flash memory when powered by portable power source (e.g., battery), and (3) writing to flash memory when powered by a portable power source. | 12-30-2010 |
20100332742 | DEVICE AND METHOD FOR MONITORING AND USING INTERNAL SIGNALS IN A PROGRAMMABLE SYSTEM - The invention relates to a device for monitoring and using internal signals in a programmable system ( | 12-30-2010 |
20110004720 | METHOD AND APPARATUS FOR PERFORMING FULL RANGE RANDOM WRITING ON A NON-VOLATILE MEMORY - A method for performing random writing on a NV memory includes: writing page mapping information regarding a portion of a full range of addresses of the NV memory and providing at least one page mapping table corresponding to a predetermined size; and accessing the NV memory according to the page mapping information. An apparatus for performing full range random writing on an NV memory includes: a controller arranged to perform the full range random writing; and a program code, at least a portion of which is embedded within the controller or received from outside the controller. The controller executing the program code writes page mapping information regarding at least a portion of a full range of addresses of the NV memory and provides at least one page mapping table corresponding to a predetermined size. The controller executing the program code accesses the NV memory according to the page mapping information. | 01-06-2011 |
20110004721 | LOADING SECURE CODE INTO A MEMORY - A method and system of controlling access to a programmable memory including: allowing code to be written to the programmable memory in a first access mode; preventing execution of the code stored in the programmable memory in the first access mode; verifying the integrity of the code stored in the programmable memory; if the integrity of the code stored in the programmable memory is verified, setting a second access mode, wherein in the second access mode, further code is prevented from being written to the programmable memory, and execution of the code stored in the programmable memory is allowed. | 01-06-2011 |
20110004722 | DATA TRANSFER MANAGEMENT - Methods, controllers, and systems for managing data transfer, such as those in solid state drives (SSDs), are described. In some embodiments, the data transfer between a host and a memory is monitored and then assessed to provide an assessment result. A number of storage units of the memory allocated to service another data transfer is adjusted based on the assessment result. Additional methods and systems are also described. | 01-06-2011 |
20110004723 | DATA WRITING METHOD FOR FLASH MEMORY AND CONTROL CIRCUIT AND STORAGE SYSTEM USING THE SAME - A data writing method for a flash memory and a control circuit and a storage system using the same are provided. The data writing method includes determining whether the size of data to be stored by a host system is smaller than a predetermined value according to a write command received from the host system, when the size of the data is smaller than the predetermined value, the data is written into a corresponding buffer physical block or a corresponding spare buffer physical block. The data writing method further includes combining valid data belonging to the same logical block during the executions of several write commands. Accordingly, the response time during the execution of each write command is shortened, and the problem of timeout is avoided. | 01-06-2011 |
20110004724 | METHOD AND SYSTEM FOR MANIPULATING DATA - A method of manipulating data includes receiving a data manipulation command for corresponding data, which corresponds to a first logical block address, to a second logical block address. The method further includes mapping the second logical block address to a physical block address, which is mapped to the first logical block address, in response to the data manipulation command. A system for manipulating data includes a host and a flash translation layer. The host transmits a data manipulation command for corresponding data, which corresponds to a first logical block address, to a second logical block address. The flash translation layer maps the second logical block address to a physical block address, which is mapped to the first logical block address, in response to the data manipulation command. | 01-06-2011 |
20110004725 | DATA STORAGE DEVICE AND METHOD - According to one embodiment, a data storage device, includes: a recording medium, statuses of storage areas of the recording medium being managed by groups; a managing table storage module storing a managing table in which bit information pieces are associated to indexes representing the groups, the bit information pieces indicating the statuses of the storage areas initially set to an erased status; a transfer controller storing, upon receiving a write command, data in the storage areas; and a controller updates the bit information pieces of one of the groups to which the storage areas belongs to a stored status. Upon receiving an erase command, the transfer controller overwrites the storage areas by predetermined data. The main controller is configured to update the bit information pieces to the erased status. | 01-06-2011 |
20110004726 | PIECEWISE ERASURE OF FLASH MEMORY - Embodiments of a circuit are described. This circuit includes control logic that generates multiple piecewise-erase commands to erase information stored in a storage cell of a memory device formed within another circuit. Note that execution of a single one of the multiple piecewise-erase commands within the memory device may be insufficient to erase the information stored in the storage cell. Moreover, the first circuit includes an interface that receives the multiple piecewise-erase commands from the control logic and that transmits the multiple piecewise-erase commands to the memory device. | 01-06-2011 |
20110010484 | OPTIMIZED PAGE PROGRAMMING ORDER FOR NON-VOLATILE MEMORY - During a programming data transfer process in a non-volatile storage system, recording units of data are transferred from a host to a memory device, such as a memory card. For each recording unit, pages of data are arranged in an order such that a page which takes longer to write to a memory array of the memory device is provided before a page which takes less time to write. Overall programming time for the recording unit is reduced since a greater degree of parallel processing occurs. While the page which takes longer to program is being programmed to the memory array, the page which takes less time to program is being transferred to the memory device. After programming is completed, the memory device signals the host to transfer a next recording unit. The pages of data may include lower, middle and upper pages. | 01-13-2011 |
20110010485 | Flash Memory Control Device - A flash memory control device includes a controller and an expansion device. The expansion device is electrically connected to the controller and one and more flash memory devices for temporarily storing data, integrating data and presenting processing status, wherein the controller orders the expansion device to transform data to the one and more flash memory devices or receive data from the one and more flash memory devices according to processing status. | 01-13-2011 |
20110010486 | REALTIME LINE OF RESPONSE POSITION CONFIDENCE MEASUREMENT - A PET event position calculation method using a combination angular and radial event map wherein identification of the radial distance of the event from the centroid of the scintillation crystal with which the event is associated as well as angular information is performed. The radial distance can be converted to a statistical confidence interval, which information can be used in downstream processing. More sophisticated reconstruction algorithms can use the confidence interval information selectively, to generate higher fidelity images with higher confidence information, and to improve statistics in dynamic imaging with lower confidence information. | 01-13-2011 |
20110010487 | Health Reporting From Non-Volatile Block Storage Device to Processing Device - Methods and devices are provided for adapting an I/O pattern, with respect to a processing device using a non-volatile block storage device based on feedback from the non-volatile block storage device. The feedback may include information indicating a status of the non-volatile block storage device. In response to receiving the feedback, a storage subsystem, included in an operating system executing on processing device, may change a behavior with respect to the non-volatile block storage device in order to avoid, or reduce, a negative impact to the non-volatile block storage device or to enhance an aspect of the non-volatile block storage device. The feedback may include performance information and/or operating environmental information of the non-volatile block storage device. When the non-volatile block storage device is not capable of providing the feedback, the processing device may request information about the non-volatile block storage device from a database service. | 01-13-2011 |
20110010488 | SOLID STATE DRIVE DATA STORAGE SYSTEM AND METHOD - The present disclosure relates to a data storage system and method that includes at least two solid state devices that can be classified in at least two different efficiency levels, wherein data progression is used to allocate data to the most cost-appropriate device according to the nature of the data. | 01-13-2011 |
20110010489 | LOGICAL BLOCK MANAGEMENT METHOD FOR A FLASH MEMORY AND CONTROL CIRCUIT STORAGE SYSTEM USING THE SAME - A logical block management method for managing a plurality of logical blocks of a flash memory device is provided. The logical block management method includes providing a flash memory controller, grouping the logical blocks into a plurality of logical zones, wherein each logical block maps to one of the logical zones. The logical block management method also includes counting a use count value for each logical block, and dynamically adjusting mapping relations between the logical blocks and the logical zones according to the use count values. Accordingly, the logical block management method can effectively utilizing the logical zones to determine usage patterns of the logical blocks and use different mechanisms to write data, so as to increase the performance of the flash memory storage device. | 01-13-2011 |
20110010490 | SOLID STATE DRIVE AND RELATED METHOD OF OPERATION - A solid state drive (SSD) comprises an input/output interface and a memory controller. The input/output interface stores a plurality of input/output commands. The memory controller comprises first and second input/output contexts and an input/output scheduler. The first and second input/output contexts process input/output commands from the input/output interface in an alternating sequence. The input/output scheduler schedules operations of the first and second input/output contexts. In particular, the input/output scheduler suspends execution of a first input/output command by the first input/output context upon determining that an execution time of the first input/output command exceeds an interval before a deadline time. After suspending execution of the first input/output command, the input/output scheduler transmits a second input/output command to the second input/output context. | 01-13-2011 |
20110010491 | DATA STORAGE DEVICE - A data storage device comprising: at least two flash devices for storing data; a circuit board, wherein each of the flash devices are integrated on the circuit board; a controller integrated on the circuit board for reading and writing to each flash devices, wherein the controller interfaces each flash devices; at least one NOR Flash device in communication with the controller through a host bus; at least one host bus memory device in communication with the controller and at least one NOR Flash device through the host bus; at least one interface in communication with the controller and adapted to physically and electrically couple to a system, receive and store data therefrom and retrieve and transmit data to the system. | 01-13-2011 |
20110010492 | Data Protection for Non-Volatile Semiconductor Memory Using Block Protection Flags - Receiving a request for canceling setting, a control circuit erases data stored in a corresponding block, changes a value of a protection flag, and cancels protection setting. When an overall protection is set for any block, the control circuit prohibits access to all blocks, except when it is an operation mode for activating a memory program contained in the microcomputer. Further, control circuit permits an access to a block M only when partial protection is set, CPU is in the mode for activating a memory program contained in the microcomputer and the access is for reading an instruction code in accordance with an instruction fetch. | 01-13-2011 |
20110010493 | NONVOLATILE STORAGE GATE, OPERATION METHOD FOR THE SAME, AND NONVOLATILE STORAGE GATE EMBEDDED LOGIC CIRCUIT, AND OPERATION METHOD FOR THE SAME - Provided is a nonvolatile storage gate embedded logic circuit embedding a nonvolatile storage gate which can hold data after power supply cutoff and can cut off a power supply at the same time shifting into a standby state. The nonvolatile storage gate embedded logic circuit includes a logic calculation unit having a logic gate, and a nonvolatile storage gate having a nonvolatile storage element, a data interface control unit disposed so as to be adjoining to the nonvolatile storage element, and receiving a nonvolatile storage control signal for data read-out from the nonvolatile storage element and data write-in to the nonvolatile storage element, and a volatile storage element disposed so as to be adjoining to the nonvolatile storage element, receiving a data input signal and a clock signal, and outputting a data output signal. | 01-13-2011 |
20110016260 | MANAGING BACKUP DEVICE METADATA IN A HIGH AVAILABILITY DISK SUBSYSTEM - A system includes a data storage device, a controller coupled with the data storage device, a backup device coupled with the controller for backing up a modified portion of data and volatile memory metadata stored by the controller, and a backup power source for powering the controller. The controller includes a pre-specified region of volatile memory for storing backup device metadata for managing a modified portion of data, the metadata comprising one or more intents corresponding to modified data written back to the data storage device. The controller is configured to invalidate the one or more intents. During a restore operation, the controller is configured to store the backup device metadata in the pre-specified region of volatile memory when a charge on the backup power source is at least a minimum threshold charge and to store the updated backup device metadata in the backup device during an interruption of power. | 01-20-2011 |
20110016261 | PARALLEL PROCESSING ARCHITECTURE OF FLASH MEMORY AND METHOD THEREOF - A parallel processing architecture of flash memory and method thereof are described. A processing unit classifies a plurality of commands to generate a first command group and a second command group respectively. The processing unit executes the first command group and the second command group. A first control unit performs the first command group to access the data stored in the first memory unit, and a second control unit simultaneously performs the second command group to access the data stored in the second memory unit for processing the data stored in the first and the second memory units in parallel. | 01-20-2011 |
20110016262 | STORAGE AND METHOD FOR PERFORMING DATA BACKUP USING THE STORAGE - A method for performing data backup using a storage device starts a backup battery when an electronic device is powered off, reads data from a memory of the electronic device by a system on chip (SoC) of the storage device, and writes the data into a field programmable gate array (FPGA) of the storage device. The method further encodes the data by the FPGA, and stores the encoded data into a flash memory of the storage device. | 01-20-2011 |
20110016263 | METHOD FOR PERFORMING DATA PATTERN MANAGEMENT REGARDING DATA ACCESSED BY A CONTROLLER OF A FLASH MEMORY, AND ASSOCIATED MEMORY DEVICE AND CONTROLLER THEREOF - A method for performing data pattern management regarding data accessed by a controller of a Flash memory includes: when the controller receives a write command, generating a first random function, where the write command is utilized for instructing the controller to write the data into the Flash memory; and adjusting a plurality of bits of the data bit by bit to generate a pseudo-random bit sequence, and writing the pseudo-random bit sequence into the Flash memory to represent the data, whereby data pattern distribution of the data is adjusted. An associated memory device and the controller thereof are also provided, where the controller includes: a ROM arranged to store a program code; a microprocessor arranged to execute the program code to control the access to the Flash memory and manage a plurality of blocks; and a randomizer arranged to generate a random function. The controller can perform data pattern management. | 01-20-2011 |
20110016264 | METHOD AND APPARATUS FOR CACHE CONTROL IN A DATA STORAGE DEVICE - According to one embodiment, a data storage device is provided, which has a cache controller that performs cache control, by using a buffer memory divided into segments, which are managed. The cache controller performs sequential hit judge on each segment, in accordance with the requested access range designated by a read or write command coming from a host system. The cache controller updates the hit upper-limit LBA set for each segment if the result of the hit judge is a mishit. | 01-20-2011 |
20110016265 | STORAGE DEVICE AND DATA PROCESS METHOD - A storage device includes a flash memory, a temporary storage unit, and a control unit. The flash memory includes a number of memory blocks, each of which has a number of pages. The temporary storage unit receives and stores a number of written commands transferred from a host system. Each written command is corresponding to user information. The control unit is coupled with the temporary storage unit and the flash memory, and adjusts executing sequence of the written commands according to a volume of the user information and unused pages in the memory block. | 01-20-2011 |
20110016266 | SEMICONDUCTOR DEVICE - On a single semiconductor package PK | 01-20-2011 |
20110016267 | Low-Power USB Flash Card Reader Using Bulk-Pipe Streaming with UAS Command Re-Ordering and Channel Separation - A flash-card reader improves transmission efficiency by using bulk streaming of multiple pipes. A bulk data-out pipe carries host write data to the card reader and can operate in parallel with a bulk data-in pipe that carries host read data that was read from a flash card attached to the card reader. Status packets do not block data packets since the he status packets are buffered through a separate status pipe, and commands are buffered through a command pipe. Flash data from multiple flash cards are interleaved as separate endpoints that share the bulk data-in pipe. A data in/out streaming state machine controls streaming bulk data through the bulk data-in and data-out pipes, while a status streaming state machine controls streaming status packets through the status pipe. Transaction overhead is reduced using bulk streaming where packets for several commands are combined into the same bulk streams. | 01-20-2011 |
20110022776 | DATA RELIABILITY IN STORAGE ARCHITECTURES - Among other subject matter, storage architectures are provided that store data reliably in connection with a system. The storage architecture ( | 01-27-2011 |
20110022777 | SYSTEM AND METHOD FOR DIRECT MEMORY ACCESS IN A FLASH STORAGE - A flash storage device provides direct memory access based on a first communication protocol. A host selects the first communication protocol and provides a request to the flash storage device for a direct memory access. Additionally, the host provides data blocks to the flash storage device for the direct memory access. In the first communication protocol, the host need not provide an address to the flash storage device for the direct memory access. The flash storage device stores the data blocks at sequential addresses starting at a predetermined address in the flash storage device. Another host may then select a second communication protocol and transfer the data blocks in the flash storage by using the second communication protocol. | 01-27-2011 |
20110022778 | Garbage Collection for Solid State Disks - Described embodiments provide a method of recovering storage space on a solid state disk (SSD). An index and valid page count are determined for each block of a segment of an SSD. If the valid page count of at least one block in the segment is zero, a quick clean is performed. A quick clean deallocates blocks having zero valid pages and places them in a queue for erasure. Otherwise, a deep clean is performed. A deep clean determines a compaction ratio, N-M, wherein N is a number of partially valid blocks and M is a number of free blocks required to compact the valid data from the N partially valid blocks into M entirely valid blocks. At least one data structure of the SSD is modified to refer to the M entirely valid blocks, and the N partially valid blocks are placed in the queue for erasure. | 01-27-2011 |
20110022779 | Skip Operations for Solid State Disks - Described embodiments provide skip operations for transferring data to or from a plurality of non-contiguous sectors of a solid-state memory. A host layer module sends data to, and receives commands from, a communication link. Received commands are one of read requests or write requests, with commands including i) a starting sector address, ii) a skip mask indicating the span of all sector addresses in the request and the sectors to be transferred, iii) a total number of sectors to be transferred; and, for write requests, iv) the data to be written to the sectors. A buffer stores data for transfer to or from the solid-state memory. A buffer layer module i) manages the buffer, ii) segments the span of the request into a plurality of chunks, and iii) determines, based on the skip mask, a number of chunks to be transferred to or from the solid-state memory. | 01-27-2011 |
20110022780 | RESTORE INDEX PAGE - Techniques for restoring index pages stored in non-volatile memory are disclosed where the index pages map logical sectors into physical pages. Additional data structures in volatile and non-volatile memory can be used by the techniques for restoring index pages. In some implementations, a lookup table associated with data blocks in non-volatile memory can be used to provide information regarding the mapping of logical sectors into physical pages. In some implementations, a lookup table associated with data blocks and a range of logical sectors and/or index pages can be used. | 01-27-2011 |
20110022781 | CONTROLLER FOR OPTIMIZING THROUGHPUT OF READ OPERATIONS - A controller, techniques, systems, and devices for optimizing throughput of read operations in flash memory are disclosed. Various optimizations of throughput for read operations can be performed using a controller. In some implementations, read operations for a multi-die flash memory device or system can be optimized to perform a read request with a highest priority (e.g., an earliest received read request) as soon as the read request is ready. In some implementations, the controller can enable optimized reading from multiple flash memory dies by monitoring a read/busy state for each die and switching between dies when a higher priority read operation is ready to begin. | 01-27-2011 |
20110022782 | FLASH STORAGE WITH ARRAY OF ATTACHED DEVICES - A flash storage system includes a flash storage controller coupled to storage modules of a flash storage array via universal serial buses. Each storage module includes at least one flash memory device. The flash storage controller receives a programming command of a communication protocol and generates universal serial bus commands based on the programming command. The flash storage controller issues the universal serial bus commands to storage modules in the flash storage array via the universal serial buses. The storage modules process the universal serial bus commands to access data in the flash storage devices of the storage modules. | 01-27-2011 |
20110022783 | FLASH STORAGE WITH INCREASED THROUGHPUT - A flash storage system includes a flash storage controller coupled to storage modules of a flash storage array via universal serial buses. Each storage module includes at least one flash memory device. The flash storage controller receives a programming command of a communication protocol and generates universal serial bus commands based on the programming command. The flash storage controller issues the universal serial bus commands to storage modules in the flash storage array via the universal serial buses. The storage modules process the universal serial bus commands to access data in the flash storage devices of the storage modules. | 01-27-2011 |
20110022784 | MEMORY SYSTEM - A memory system according to an embodiment of the present invention comprises: a memory amount required for management table creation is reduced by adopting a nonvolatile semiconductor memory including a plurality of parallel operation elements respectively having a plurality of physical blocks as units of data erasing and a controller that can drive the parallel operation elements in parallel and has a number-of-times-of-erasing managing unit that manages the number of times of erasing in logical block units associated with a plurality of physical blocks driven in parallel. | 01-27-2011 |
20110022785 | METHOD FOR PROGRAMMING A MEMORY-PROGRAMMABLE CONTROLLER WITH RESISTANT STORAGE OF DATA IN MEMORY - The invention relates to a method for programming and/or diagnosis of a memory-programmable controller, having at least one memory-programmable function component. For programming, a predetermined programming system is used. In the context of this programming system variables are predetermined, and information exchange sequences are used for the programming. Results of the programming are output during at least one programming mode via an output device, and input information is at least in part stored permanently in memory. | 01-27-2011 |
20110022786 | FLASH MEMORY STORAGE APPARATUS, FLASH MEMORY CONTROLLER, AND SWITCHING METHOD THEREOF - A flash memory storage apparatus including a multi level cell (MLC) NAND flash memory, a flash memory controller, and a host transmission bus is provided. The MLC NAND flash memory includes a plurality of blocks for storing data, wherein each of the blocks has an upper page and a lower page, and the writing speed of the lower page is faster than that of the upper page. The flash memory controller is electrically connected to the MLC NAND flash memory and is used for executing storage mode switching steps. The host transmission bus is electrically connected to the flash memory controller and is used for communicating with a host. The flash memory storage apparatus provided by the present invention can provide multiple storage modes in order to store different data. | 01-27-2011 |
20110022787 | DATA WRITING METHOD FOR NON-VOLATILE MEMORY AND CONTROLLER USING THE SAME - A data writing method for a non-volatile memory is provided, wherein the non-volatile memory includes a data area and a spare area. In the data writing method, a plurality of blocks in a substitution area of the non-volatile memory is respectively used for substituting a plurality of blocks in the data area, wherein data to be written into the blocks in the data area is written into the blocks in the substitution area, and the blocks in the substitution area are selected from the spare area of the non-volatile memory. A plurality of temporary blocks of the non-volatile memory is used as a temporary area of the blocks in the substitution area, wherein the temporary area is used for temporarily storing the data to be written into the blocks in the substitution area. | 01-27-2011 |
20110022788 | INTEGRATING DATA FROM SYMMETRIC AND ASYMMETRIC MEMORY - Data stored within symmetric and asymmetric memory components of main memory is integrated by identifying a first data as having access characteristics suitable for storing in an asymmetric memory component. The first data is included among a collection of data to be written to the asymmetric memory component. An amount of data is identified within the collection of data to be written to the asymmetric memory component. The amount of data is compared within the collection of data to a volume threshold to determine whether a block write to the asymmetric memory component is justified by the amount of data. If justified, the collection of data is loaded to the asymmetric memory component. | 01-27-2011 |
20110022789 | MEMORY DEVICE, HOST DEVICE, MEMORY SYSTEM, MEMORY DEVICE CONTROL METHOD, HOST DEVICE CONTROL METHOD AND MEMORY SYSTEM CONTROL METHOD - A memory card | 01-27-2011 |
20110029715 | WRITE-ERASE ENDURANCE LIFETIME OF MEMORY STORAGE DEVICES - A memory management system and method for managing memory blocks of a memory device of a computer. The system includes a free block data structure including free memory blocks for writing, and sorting the free memory blocks in a predetermined order based on block write-erase endurance cycle count and receiving new user-write requests to update existing data and relocation write requests to relocate existing data separately, a user-write block pool for receiving youngest blocks holding user-write data (i.e., any page being updated frequently) from the free block data structure, a relocation block pool for receiving oldest blocks holding relocation data (i.e., any page being updated infrequently) from the free block data structure, and a garbage collection pool structure for selecting at least one of user-write blocks and relocation blocks for garbage collection, wherein the selected block is moved back to the free block data structure upon being relocated and erased. | 02-03-2011 |
20110029716 | SYSTEM AND METHOD OF RECOVERING DATA IN A FLASH STORAGE SYSTEM - A flash storage system includes a system controller that generates redundant data based on data stored in flash storage devices of the flash storage system. The system controller stores the redundant data in one or more of the flash storage devices. Additionally, the system controller identifies data that has become unavailable in one or more of the flash storage device, recovers the unavailable data based on the redundant data, and stores the recovered data into one or more other flash storage devices of the flash storage system. | 02-03-2011 |
20110029717 | FLASH STORAGE DEVICE WITH FLEXIBLE DATA FORMAT - A flash storage device includes a flash storage for storing data and a controller for receiving a command containing data and selecting a sector size for the data. The controller allocates the data among data sectors having the sector size and writes the data sectors to the flash storage. In some embodiments, the controller generates system data and stores the system data in the data sectors or a system sector, or both. | 02-03-2011 |
20110029718 | METHOD AND SYSTEM TO IMPROVE THE PERFORMANCE OF A MULTI-LEVEL CELL (MLC) NAND FLASH MEMORY - A method and system to improve the performance of a multi-level cell (MLC) NAND flash memory. In one embodiment of the invention, the metadata associated with the data stored in a MLC NAND flash memory is stored only in one or more lower pages of the MLC NAND flash memory. The MLC NAND flash memory has lower and upper pages, where the lower pages have a faster programming time or rate than the upper pages in one embodiment of the invention. By storing the metadata only in the pages of the MLC NAND flash memory that have low latencies of programming, the quality of service (QoS) of the MLC NAND flash memory can be improved. | 02-03-2011 |
20110029719 | DATA WRITING METHOD FOR FLASH MEMORY AND CONTROL CIRCUIT AND STORAGE SYSTEM USING THE SAME - A data writing method for moving data in a plurality of flash memory modules during a write command of a host system is executed is provided, wherein each of the flash memory modules has a plurality of physical blocks. The present data writing method includes transferring first data received from the host system to one of the flash memory modules and writing the first data into the physical blocks of the flash memory module according to the write command. The present data writing method also includes moving at least one second data in the physical blocks of another one of the flash memory modules during the first data is written. Thereby, when the host system is about to write data into the other flash memory module, the time for executing the write command is effectively reduced. | 02-03-2011 |
20110029720 | Flash Storage Device and Operation Method Thereof - The invention provides a flash storage device. In one embodiment, the flash storage device comprises a flash memory and a controller. The flash memory comprises a plurality of blocks, wherein each of the plurality of blocks comprises a plurality of pages for storing data, and each of the plurality of pages has a physical address. The controller divides a plurality of logical addresses into a plurality of logical address ranges, records a plurality of partial link tables respectively storing a mapping relationship between logical addresses of a corresponding logical address range and corresponding physical addresses, stores the partial link tables in the flash memory, combines the partial link tables to obtain a link table, and converts logical addresses sent by a host to physical addresses according to the link table. | 02-03-2011 |
20110029721 | Cascaded combination structure of flash disks to create security function - Disclosed is a cascaded combination structure of flash disks to create security function, comprising of a plurality of data disks and a key disk. Each of the data disks includes a public zone and a private zone matched with the key disk. When the key disk is series-connected with the data disks, the private zone can be displayed and load/save by a public program in the key disk. Accordingly, there can be secured and hid the data in the private zone so that the data in the private zone is unable to be embezzled by other illegal users. | 02-03-2011 |
20110029722 | ELECTRONIC CONTROL APPARATUS INCLUDING ELECTRICALLY REWRITABLE NON-VOLATILE MEMORY - The electronic control apparatus includes an electrically rewritable non-volatile memory, a writing voltage there of being larger in absolute value than a reading voltage thereof, and a control section configured to access the non-volatile memory to perform data writing or data reading. The non-volatile memory includes a first terminal to receive the writing voltage generated by a voltage generating means disposed outside the electronic control apparatus, the first terminal being electrically isolated from the external voltage generating means. | 02-03-2011 |
20110029723 | Non-Volatile Memory Based Computer Systems - Non-volatile memory based computer systems and methods are described. According to one aspect of the invention, at least one non-volatile memory module is coupled to a computer system as main storage. The non-volatile memory module is controlled by a northbridge controller configured to control the non-volatile memory as main memory. The page size of the at least one non-volatile memory module is configured to be the size of one of the cache lines associated with a microprocessor of the computer system. According to another aspect, at least one non-volatile memory module is coupled to a computer system as data read/write buffer of one or more hard disk drives. The non-volatile memory module is controlled by a southbridge controller configured to control the non-volatile memory as an input/out device. The page size of the at least one non-volatile memory module is configured in proportion to characteristics of the hard disk drives. | 02-03-2011 |
20110029724 | Partial Block Data Programming And Reading Operations In A Non-Volatile Memory - Data in less than all of the pages of a non-volatile memory block are updated by programming the new data in unused pages of either the same or another block. In order to prevent having to copy unchanged pages of data into the new block, or to program flags into superceded pages of data, the pages of new data are identified by the same logical address as the pages of data which they superceded and a time stamp is added to note when each page was written. When reading the data, the most recent pages of data are used and the older superceded pages of data are ignored. This technique is also applied to metablocks that include one block from each of several different units of a memory array, by directing all page updates to a single unused block in one of the units. | 02-03-2011 |
20110029725 | Switching Drivers Between Processors - Systems, methods, and computer software for operating a device can be used to operate the device in multiple modes. The device can be operated in a first operating mode adapted for processing data, in which a first processor executes a driver for a nonvolatile memory and a second processor performs processing of data stored in files on the nonvolatile memory. An instruction can be received to switch the device to a second operating mode adapted for reading and/or writing files from or to the nonvolatile memory. The driver for the nonvolatile memory can be switched from the first processor to the second processor in response to the instruction, and the driver for the nonvolatile memory can be executed on the second processor after performing the switch. A communications driver can be executed on the first processor in response to the instruction to switch the device to the second operating mode. | 02-03-2011 |
20110029726 | DATA UPDATING METHOD, MEMORY SYSTEM AND MEMORY DEVICE - A data updating method, a memory system and a memory device in which the memory device is connectable to a host device and has a memory section and a memory controller, the memory section consists of a first memory section which can be divided into partitions having multiple different attributes, and a work space which is managed by the memory controller, and the method of updating data which is stored in the memory device uses one of the writing methods which has been selected from among multiple different writing methods of writing data into the partition, depending on the attribute of the partition, to perform an updating process, and can securely update the data. | 02-03-2011 |
20110035534 | Dual-scope directory for a non-volatile memory storage system - A device, system, and method are disclosed. In one embodiment the device includes a non-volatile memory (NVM) storage array to store a plurality of storage elements. The device also includes a dual-scope directory structure having a background space and a foreground space. The structure is capable of storing several entries that each correspond to a location in the NVM storage array storing a storage element. The background space includes entries for storage elements written into the array without any partial overwrites of a previously stored storage element in the background space. The foreground space includes entries for storage elements written into the array with at least one partial overwrite of one or more previously stored storage elements in the background space. | 02-10-2011 |
20110035535 | Tracking a lifetime of write operations to a non-volatile memory storage - A method, device, and system are disclosed. In one embodiment method begins by incrementing a count of a total number of write operations to a non-volatile memory storage for each write operation to the non-volatile memory storage. The method then receives a request for the total count of lifetime write operations from a requestor. Finally, the method sends the total count of lifetime write operations to the requestor. | 02-10-2011 |
20110035536 | NON-VOLATILE MEMORY DEVICE GENERATING WEAR-LEVELING INFORMATION AND METHOD OF OPERATING THE SAME - A non-volatile memory device which includes a non-volatile memory core including a memory cell array and a controller configured to generate wear-leveling information from internal operation information of the memory cell array after a write operation, independent of a request from an external device. The wear-leveling information is selectively provided to the external device. | 02-10-2011 |
20110035537 | MULTIPROCESSOR SYSTEM HAVING MULTI-COMMAND SET OPERATION AND PRIORITY COMMAND OPERATION - A multiprocessor system comprises a multi-port semiconductor memory device, a first processor, and a memory link architecture. The multi-port semiconductor memory device comprises a mailbox area and a shared memory area accessible through a plurality of ports. The first processor is configured to write a multi-command set comprising multiple commands for multiple read/write operations to a command area of the shared memory, and to write a message to the mailbox area to indicate the writing of the multi-command set. The memory link architecture comprises a second processor connected to the multi-port semiconductor memory device, and a nonvolatile semiconductor memory device connected to the second processor. The second processor is configured to read the multi-command set from the mailbox area and to sequentially perform the multiple read/write operations according to the multi-command set. | 02-10-2011 |
20110035538 | NONVOLATILE MEMORY SYSTEM USING DATA INTERLEAVING SCHEME - A memory system comprises a plurality of nonvolatile memory devices configured for interleaved access. Programming times are measured and recorded for various memory cell regions of the nonvolatile memory devices, and interleaving units are formed by memory cell regions having different programming times. | 02-10-2011 |
20110035539 | STORAGE DEVICE, AND MEMORY CONTROLLER - The memory controller of a storage device includes a scramble pattern generator, a scramble processor, a logical and physical address conversion table, a memory interface, and a controller, in which the physical page is managed by dividing to a data section and a management section. For the data section, the controller controls the scramble pattern generator to generate a scramble pattern on the basis of a logical address specific to the data section, and controls the scramble processor to scramble the data of the data section corresponding to the logical address by using the scramble pattern, and for the management section, the controller controls the scramble pattern generator to generate a scramble pattern on the basis of a physical address as the write destination of the management section, and scrambling the management data by the scramble processor by using the scramble pattern, so that data is written and reading to and from the semiconductor memory. | 02-10-2011 |
20110035540 | FLASH BLADE SYSTEM ARCHITECTURE AND METHOD - A flash blade and associated methods enable improved areal density of information storage, reduced power consumption, decreased cost, increased IOPS, and/or elimination of unnecessary legacy components. In various embodiments, a flash blade comprises a host blade controller, a switched fabric, and one or more storage elements configured as flash DIMMs. Storage space provided by the flash DIMMs may be presented to a user in a configurable manner. Flash DIMMs, rather than magnetic disk drives or solid state drives, are the field-replaceable unit, enabling improved customization and cost savings. | 02-10-2011 |
20110035541 | STORAGE DEVICE AND DEDUPLICATION METHOD - This storage device performs deduplication of eliminating duplicated data by storing a logical address of one or more corresponding logical unit memory areas in a prescribed management information storage area of a physical unit memory area defined in the storage area provided by the flash memory chip, and executes a reclamation process of managing a use degree as the total number of the logical addresses used stored in the management information storage area and a duplication degree as the number of valid logical addresses corresponding to the physical unit memory area for each of the physical unit memory areas, and returning the physical unit memory area to an unused status when the difference of the use degree and the duplication degree exceeds a default value in the physical unit memory area. | 02-10-2011 |
20110035542 | ASIC including vertically stacked embedded non-flash re-writable non-volatile memory - A multiple-type memory is disclosed. The multiple-type memory includes memory blocks in communication with control logic blocks. The memory blocks and the control logic blocks are configured to emulate a plurality of memory types. The memory blocks can be configured into a plurality of memory planes that are vertically stacked upon one another. The vertically stacked memory planes may be used to increase data storage density and/or the number of memory types that can be emulated by the multiple-type memory. Each memory plane can emulate one or more memory types. The control logic blocks can be formed in a substrate (e.g., a silicon substrate including CMOS circuitry) and the memory blocks or the plurality of memory planes can be positioned over the substrate and in communication with the control logic blocks. The multiple-type memory may be non-volatile so that stored data is retained in the absence of power. | 02-10-2011 |
20110035543 | MEMORY DRIVE THAT CAN BE OPERATED LIKE OPTICAL DISK DRIVE AND METHOD FOR VIRTUALIZING MEMORY DRIVE AS OPTICAL DISK DRIVE - The present invention relates to a memory drive that can be virtualized as an optical disk drive and a virtualizing method thereof. One embodiment of the present invention discloses a method for virtualizing a memory drive as an optical disk drive, the memory drive comprising a storage memory and a storage memory controller, which reads or writes data from and to the storage memory. Therefore, according to one embodiment of the present invention, a solid-state which comprises a flash memory and a flash memory controller can be used like an optical disk. | 02-10-2011 |
20110040924 | Controller and Method for Detecting a Transmission Error Over a NAND Interface Using Error Detection Code - The embodiments described herein provide a controller and method for detecting a transmission error over a NAND interface using error detection code. In one embodiment, a controller receives a write command, data, and an error detection code associated with the data from a host through a first NAND interface of the controller using a NAND interface protocol. The controller uses the error detection code to detect if a transmission error occurred. In another embodiment, a controller generates an error detection code based on data read from a flash memory device and provides the data and error detection code to a host through a first NAND interface of the controller, so the host can detect if a transmission error occurred. | 02-17-2011 |
20110040925 | Method and Apparatus for Addressing Actual or Predicted Failures in a FLASH-Based Storage System - Methods and apparatuses for enhanced protection of data stored in a FLASH memory system involve a controller capable of adapting to the failure of one or more FLASH memory devices in the memory system. The controller stores data in the form of page stripes, each page stripe composed of data pages, and each data page stored in a different FLASH memory device. The controller also detects failure of a FLASH memory device in which a data page of a particular page stripe is stored, reconstructs the data page, and stores the reconstructed data page in a new page stripe, where the number of data pages in the new page stripe is less than the number of data pages in the particular page stripe, and where no page of the new page stripe is stored in a memory location within the failed FLASH memory device. | 02-17-2011 |
20110040926 | FLASH-based Memory System With Variable Length Page Stripes Including Data Protection Information - Methods and apparatuses for enhanced protection of data stored in a FLASH memory system involve a controller capable of protecting data using different size page stripes. The controller is configured to store data in FLASH memory devices in the form of page stripes, each page stripe comprising a plurality of pages of information, each page of information being stored in a different FLASH memory chip. The controller stores the data in a manner such that the pages making up each page stripe includes a plurality of data pages and at least one data protection page. In one implementation, the page stripes stored by the controller include a first page stripe having N data pages and one data protection page, and a second page stripe having M data pages and one data protection page, where N is an integer greater than three and M is an integer less than N. | 02-17-2011 |
20110040927 | Method and Apparatus for Performing Enhanced Read and Write Operations in a FLASH Memory System - Methods and apparatus for enhanced READ and WRITE operations in a FLASH-based solid state storage system that includes a logical to physical translation table where the logical to physical translation table can include entries associating a logical block address with one or more data identifiers, where each data identifier is associated with a data string. | 02-17-2011 |
20110040928 | METHOD FOR IDENTIFYING A PAGE OF A BLOCK OF FLASH MEMORY, AND ASSOCIATED MEMORY DEVICE - A memory device includes a flash memory and a controller. The flash memory includes a plurality of blocks, and each block includes a plurality of pages. The controller is utilized for reading a plurality of bits from an identification region of a page, and determining whether the page is blank or not according to the plurality of bits. | 02-17-2011 |
20110040929 | METHOD AND APPARATUS FOR MODIFYING DATA SEQUENCES STORED IN MEMORY DEVICE - A method of modifying data sequences in a memory system comprises receiving program data having a first data sequence, and determining whether the received first data sequence matches one of “m” predefined sequences stored in the memory system. The method further comprises replacing the received first data sequence with a replacement sequence upon determining that the received first data sequence matches one of the “m” predefined sequences, and outputting the replacement sequence from the memory system. The replacement sequence typically comprises pattern bits indicating a pattern of the first data sequence and location bits indicating a start location of the first data sequence. | 02-17-2011 |
20110040930 | Method for Accessing Flash Memory Device and Memory System Including the Same - Provided are a method for accessing a flash memory device and a memory system including the same. In the method, first and second storage regions of a memory block of the flash memory device are set to free blocks, and each of the first and second storage regions are set to a data block independently. | 02-17-2011 |
20110040931 | MEMORY CONTROL METHOD AND DEVICE, MEMORY ACCESS CONTROL METHOD, COMPUTER PROGRAM, AND RECORDING MEDIUM - To dramatically increase the number of times data can be written into a flash memory. | 02-17-2011 |
20110040932 | Efficient Reduction of Read Disturb Errors in NAND FLASH Memory - Methods and apparatuses for reduction of Read Disturb errors in a NAND FLASH memory system comprise a controller configured to organize FLASH memory devices into blocks, each block having a plurality of pages, and each page defining an individually addressable physical memory location. The controller is further configured to accumulate a Block READ Count corresponding to the number of times any pages in a first block of pages have been read since the first block was last erased. Once the READ count reaches a predetermined number, the controller responds to subsequent READ requests for pages within the first block by moving data associated with a requested page to a page in a second, different block without moving data associated with other pages in the first block, and modifying a logical-to-physical translation table to associate the moved data with the physical address of the page in the second block. | 02-17-2011 |
20110047316 | SOLID STATE MEMORY DEVICE POWER OPTIMIZATION - Memory device power optimization includes operating a memory device, wherein the memory device includes a plurality of data channels and each of the plurality of data channels includes a plurality of data storage units. A controller receives a command to enable a power saving feature and determines a frequency of accessing of data stored in the data storage units, sorts the data into the data channels according to the frequency of the accessing of the data and powers down the data channels that are storing data with a frequency of accessing the data that is below a pre-determined threshold value. | 02-24-2011 |
20110047317 | SYSTEM AND METHOD OF CACHING INFORMATION - A system and method is provided wherein, in one aspect, a currently-requested item of information is stored in a cache based on whether it has been previously requested and, if so, the time of the previous request. If the item has not been previously requested, it may not be stored in the cache. If the subject item has been previously requested, it may or may not be cached based on a comparison of durations, namely (1) the duration of time between the current request and the previous request for the subject item and (2) for each other item in the cache, the duration of time between the current request and the previous request for the other item. If the duration associated with the subject item is less than the duration of another item in the cache, the subject item may be stored in the cache. | 02-24-2011 |
20110047318 | Reducing capacitive load in a large memory array - In various embodiments, field-effect transistors (FETs) or other high-resistance electronic switches may be used to take a large group of parallel-connected memory devices and separate them into smaller groups of parallel-connected devices, so that the signal lines in each group may be electrically isolated from the signals lines in the other groups. In this way, when one memory device is selected for an operation, only the other memory devices in that group will contribute to the capacitive load on the signal lines to the memory controller, while the capacitive load from the memory devices in the other groups will be electrically isolated by having their associated FETs turned off. The resultant reduced capacitive load may permit higher operating speeds and higher data rates for read or write operations with the memory devices. | 02-24-2011 |
20110047319 | Memory devices and systems including write leveling operations and methods of performing write leveling operations in memory devices and systems - A memory device controller having a write leveling mode of operation comprises: a clock generator that generates a periodic clock signal for transmission to a memory device; a data strobe generator that generates a data strobe signal for transmission to the memory device; and a control unit that generates command signals for transmission to the memory device, the controller, during operation in the write leveling mode, generating a command signal and a write leveling control signal for transmission to the memory device. | 02-24-2011 |
20110047320 | SYSTEM AND METHOD FOR PERFORMING PROGRAM OPERATION ON NONVOLATILE MEMORY DEVICE - A data processing system performs a data processing method by receiving and interpreting a command packet corresponding to a program operation, identifying a size of data to be programmed in the program operation, and programming the data using a buffered or un-buffered program operation based on the size of the data. | 02-24-2011 |
20110047321 | STORAGE PERFORMANCE MANAGEMENT METHOD - The computer system having a storage subsystem for storing data in a logical storage extent created in a physical storage device constituted of a physical storage medium, a host computer for reading/writing data from/to the logical storage extent via a network, and a management computer for managing the storage subsystem. The management computer records components of the storage subsystem, a connection relation between the components included in a network path, a correlation between the logical storage extent and the components, and a load of each component, specifies components included in a leading path from an interface through which the storage subsystem is connected with the network to the physical storage medium, measures loads of the specified components to improve performance. | 02-24-2011 |
20110047322 | METHODS, SYSTEMS AND DEVICES FOR INCREASING DATA RETENTION ON SOLID-STATE MASS STORAGE DEVICES - Methods, systems and devices for increasing the reliability of solid state drives containing one or more NAND flash memory arrays. The methods, systems and devices take into account usage patterns that can be employed to initiate proactive scrubbing on demand, wherein the demand is automatically generated by a risk index that can be based on one or more of various factors that typically contribute to loss of data retention in NAND flash memory devices. | 02-24-2011 |
20110047323 | MEMORY SYSTEM, MULTI-BIT FLASH MEMORY DEVICE, AND ASSOCIATED METHODS - A memory system includes a multi-bit flash memory device and a flash controller configured to control the multi-bit flash memory device. The flash controller is configured to output a series of commands, pointers, and addresses to the multi-bit flash memory device for read/program operations. | 02-24-2011 |
20110047324 | Memory device with vertically embedded non-Flash non-volatile memory for emulation of nand flash memory - A system and a method for emulating a NAND memory system are disclosed. In the method, a command associated with a NAND memory is received. After receipt of the command, a vertically configured non-volatile memory array is accessed based on the command. In the system, a vertically configured non-volatile memory array is connected with an input/output controller and a memory controller. The memory controller is also connected with the input/output controller. The memory controller is operative to interface with a command associated with a NAND memory and based on the command, to access the vertically configured non-volatile memory array for a data operation, such as a read operation or write operation. An erase operation on the vertically configured non-volatile memory array is not required prior to the write operation. The vertically configured non-volatile memory array can be partitioned into planes, blocks, and sub-planes, for example. | 02-24-2011 |
20110047325 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND SIGNAL PROCESSING SYSTEM - A nonvolatile semiconductor memory device includes: memory cells regularly arranged in a matrix pattern, and having as a charge storage medium a nonconductive nitride film capable of configuring two physical bits in each memory cell; and bit lines connecting in common a source or drain of one of two memory cells adjoining in a row direction with a source or drain of the other memory cell. One of two bits in each memory cell having the nonconductive nitride film is accessed by a first address group allocated to a first function, and the other bit is accessed by a second address group allocated to a second function. | 02-24-2011 |
20110055453 | INTERRUPTIBLE NAND FLASH MEMORY - A NAND flash memory logical unit. The NAND flash memory logical unit includes a control circuit that responds to commands and permits program and/or erase commands to be interruptible by read commands. The control circuit includes a set of internal registers for performing the current command, and a set of external registers for receiving commands. The control circuit also includes a set of supplemental registers that allow the NAND flash memory logical unit to have redundancy to properly hold state of an interrupted program or erase command. When the interrupted program or erase command is to resume, the NAND flash memory logical unit thus can quickly resume the paused program or erase operation. This provides significant improvement to read response times in the context of a NAND flash memory logical unit. | 03-03-2011 |
20110055454 | SYSTEMS AND METHODS FOR DETERMINING THE STATUS OF MEMORY LOCATIONS IN A NON-VOLATILE MEMORY - Systems and methods are provided for storing data in a portion of a non-volatile memory (“NVM”) such that the status of the NVM portion can be determined with high probability on a subsequent read. An NVM interface, which may receive write commands to store user data in the NVM, can store a fixed predetermined sequence (“FPS”) with the user data. The FPS may ensure that a successful read operation on a NVM portion is not misinterpreted as a failed read operation or as an erased NVM portion. For example, if the NVM returns an all-zero vector when a read request fails, the FPS can include at least one “1” or one “0”, as appropriate, to differentiate between successful and unsuccessful read operations. In some embodiments, the FPS may also be used to differentiate between disturbed data, which passes an error correction check, and correct data. | 03-03-2011 |
20110055455 | INCREMENTAL GARBAGE COLLECTION FOR NON-VOLATILE MEMORIES - Systems and methods are provided for performing incremental garbage collection for non-volatile memories (“NVMs”), such as flash memory. In some embodiments, an electronic device including the NVM may perform incremental garbage collection to free up and erase a programmed block of the NVM. The programmed block may include valid data and invalid data, and the electronic device may be configured to copy the valid data from the programmed block to an erased block in portions. In between programming each portion of the valid data to the erased block, the electronic device can program host data to the erased block. This way, the electronic device can stagger the garbage collection operations and prevent a user from having to experience one long garbage collection operation. | 03-03-2011 |
20110055456 | METHOD FOR GIVING READ COMMANDS AND READING DATA, AND CONTROLLER AND STORAGE SYSTEM USING THE SAME - A method for giving a read command to a flash memory chip to read data to be accessed by a host system is provided. The method includes receiving a host read command; determining whether the received host read command follows a last host read command; if yes, giving a cache read command to read data from the flash memory chip; and if no, giving a general read command and the cache read command to read data from the flash memory chip. Accordingly, the method can effectively reduce time needed for executing the host read commands by using the cache read command to combine the host read commands which access continuous physical addresses and pre-read data stored in a next physical address. | 03-03-2011 |
20110055457 | METHOD FOR GIVING PROGRAM COMMANDS TO FLASH MEMORY, AND CONTROLLER AND STORAGE SYSTEM USING THE SAME - A method for giving program commands to a flash memory chip is provided, the method is suitable for writing data from a host system into the flash memory chip. In the present method, a plurality of host write commands and data corresponding to the host write commands are received from the host system by using a native command queuing (NCQ) protocol, and cache program commands are gived to the flash memory chip to write the data into the flash memory chip. Accordingly, the time for executing the host write commands is effectively shortened by writing the data through the cache program commands and the NCQ protocol. | 03-03-2011 |
20110055458 | Page based management of flash storage - Methods and circuits for page based management of an array of Flash RAM nonvolatile memory devices provide paged base reading and writing and block erasure of a flash storage system. The memory management system includes a management processor, a page buffer, and a logical-to-physical translation table. The management processor is in communication with an array of nonvolatile memory devices within the flash storage system to provide control signals for the programming of selected pages, erasing selected blocks, and reading selected pages of the array of nonvolatile memory devices. | 03-03-2011 |
20110055459 | METHOD FOR MANAGING A PLURALITY OF BLOCKS OF A FLASH MEMORY, AND ASSOCIATED MEMORY DEVICE AND CONTROLLER THEREOF - A method for managing a plurality of blocks of a Flash memory includes: dynamically determining a link type regarding a logical block address according to at least one criterion, where the link type is selected from a plurality of predetermined link types; and regarding the logical block address, recording/updating the link type and linking information corresponding to the link type. An associated memory device and a controller thereof are also provided, where the controller includes: a ROM arranged to store a program code; and a microprocessor arranged to execute the program code to control the access to the Flash memory and manage the plurality of blocks. | 03-03-2011 |
20110055460 | METHOD FOR MANAGING A PLURALITY OF BLOCKS OF A FLASH MEMORY, AND ASSOCIATED MEMORY DEVICE AND CONTROLLER THEREOF - A method for managing a plurality of blocks of a Flash memory includes: recording/updating linking information regarding a logical block address, wherein the linking information includes a plurality of physical block addresses linking to the logical block address, and each physical block address represents a block of the plurality of blocks; and when a block represented by a physical block address of the plurality of physical block addresses has no any valid page, selectively erasing the block and removing the physical block address from the linking information. An associated memory device and a controller thereof are also provided, where the controller includes: a ROM arranged to store a program code; and a microprocessor arranged to execute the program code to control the access to the Flash memory and manage the plurality of blocks. | 03-03-2011 |
20110055461 | SYSTEMS AND METHODS FOR PRE-EQUALIZATION AND CODE DESIGN FOR A FLASH MEMORY - A system, computer readable program, and method for programming flash memory, the method includes: providing multiple pairs of most significant bit (MSB) page uncoded bit error rates (UBERs) and least significant bit (LSB) page UBERs; selecting a selected MSB page code rate and a selected LSB page code rate so that a selected MSB page UBER associated with the selected MSB page code rate and a selected LSB page UBER associated with the selected LSB page code rate support a highest average UBER out of the multiple pairs of MSB page UBERs and LSB page UBERs, wherein the selected MSB page code rate and the selected LSB page code rate are obtainable under a desired code rate constraint; and determining an encoding and programming scheme that may be based on the selected MSB page UBER, the selected MSB code rate, the selected LSB page UBER and the selected LSB code rate. | 03-03-2011 |
20110055462 | MEMORY SYSTEM, CONTROLLER, AND DATA TRANSFER METHOD - According to one embodiment, a memory system includes a nonvolatile first memory, a nonvolatile second memory, a data-copy processing unit and a data invalidation processing unit. The first memory has a storage capacity for n (n≧2) pages per word line. The nonvolatile second memory temporarily stores user data write-requested from a host apparatus. The data-copy processing unit executes data copy processing including reading out, in page units, the user data stored in the second memory and sequentially writing the read-out user data in page units in the first memory. The data invalidation processing unit selects, after the execution of the data copy processing, based on whether the memory cell group per word line stores user data for n pages, user data requiring backup out of the user data subjected to the data copy processing and leaves the selected user data in the second memory as backup data. | 03-03-2011 |
20110055463 | SEMICONDUCTOR DEVICE AND DRIVING METHOD THE SAME - It is an object to prevent miswriting by radio in a relatively easy way in a semiconductor device which is capable of data communication (reception/transmission) through wireless communication, in particular, in an RFID tag provided with an OTP memory or a write-once memory. Alternatively, it is an object to prevent data from being tampered. Further alternatively, it is an object to inhibit access to a memory in a relatively easy way and to inhibit reading of data in a semiconductor device which is capable of data communication (reception/transmission) through wireless communication. In a semiconductor device including a control circuit and an OTP memory, a memory includes at least a sector for preventing additional writing and an information sector. When data for preventing additional writing is written to the sector for preventing additional writing and information is written to the information sector which is electrically connected to the sector for preventing additional writing, additional writing to the information sector to which the information is written is impossible. | 03-03-2011 |
20110055464 | Device driver including a flash memory file system and method thereof and a flash memory device and method thereof - A device driver including a flash memory file system and method thereof and a flash memory device and method thereof are provided. The example device driver may include a flash memory file system configured to receive data scheduled to be written into the flash memory device, the flash memory file system selecting one of a first data storage area and a second data storage area within the flash memory device to write the received data to based upon an expected frequency of updating for the received data, the first data storage area configured to store data which is expected to be updated more often than the second data storage area. The example flash memory device may include a first data storage area configured to store first data, the first data having a first expected frequency for updating and a second data storage area configured to store second data, the second data having a second expected frequency of updating, the first expected frequency being higher than the second expected frequency. | 03-03-2011 |
20110055465 | NONVOLATILE SEMICONDUCTOR STORAGE DEVICE - A nonvolatile semiconductor storage device capable of storing a plurality of bits of data in one memory cell by assigning multivalued data having a higher-order bit selected from one of a pair of data in a first unit and a lower-order bit selected from the other of the pair of data to each threshold voltage of the memory cell, wherein in a first write operation that processes data in the first unit, the logic of one of the higher-order bit and the lower-order bit is fixed, and two pieces of multivalued data that maximize the difference between the threshold voltages are assigned, thereby storing one bit of input data in the one memory cell in a pseudo binary state, and in a second write operation that processes data in a second unit larger than the first unit, a plurality of bits of input data is stored in the one memory cell in a multivalued state, and parity data for error correction in the second unit is stored in the memory cell. | 03-03-2011 |
20110055466 | NONVOLATILE MEMORY SYSTEM, AND DATA READ/WRITE METHOD FOR NONVOLATILE MEMORY SYSTEM - A nonvolatile memory system comprises a nonvolatile memory having a plurality of data areas; and a memory controller operative to control read and write operations to the nonvolatile memory. The memory controller successively executes read/write operations to plural sectors within a selected data area in the nonvolatile memory in accordance with a command and a sector count and sector address fed from a host device. | 03-03-2011 |
20110055467 | DATA AREA MANAGING METHOD IN INFORMATION RECORDING MEDIUM AND INFORMATION PROCESSOR EMPLOYING DATA AREA MANAGING METHOD - Area management information is cached in a cache memory by controlling the access size when an information processor accesses the area management information in an information recording medium. When the processing content of the information processor is to retrieve a free area from the area management information, a physical management block size determined from the physical characteristics of the information recording medium is used. When the processing content is to acquire a link destination from the area management information, minimum access unit of the information recording medium is used. Consequently, overhead can be lessened when the area management information is accessed. | 03-03-2011 |
20110055468 | Flash Memory Data Correction and Scrub Techniques - In order to maintain the integrity of data stored in a flash memory that are susceptible to being disturbed by operations in adjacent regions of the memory, disturb events cause the data to be read, corrected and re-written before becoming so corrupted that valid data cannot be recovered. The sometimes conflicting needs to maintain data integrity and system performance are balanced by deferring execution of some of the corrective action when the memory system has other high priority operations to perform. In a memory system utilizing very large units of erase, the corrective process is executed in a manner that is consistent with efficiently rewriting an amount of data much less than the capacity of a unit of erase. | 03-03-2011 |
20110060861 | Systems and Methods for Variable Level Use of a Multi-Level Flash Memory - Various embodiments of the present invention provide systems, methods and circuits for use of a memory system. As one example, an electronics system is disclosed that includes a memory bank, a memory access controller circuit, and an encoding circuit. The memory bank includes a plurality of multi-bit memory cells that each is operable to hold at least two bits. The memory access controller circuit is operable to determine a use frequency of a data set maintained in the memory bank. The encoding circuit is operable to encode the data set to yield an encoded output for writing to the memory bank. The encoding level for the data set is selected based at least in part on the use frequency of the data set. | 03-10-2011 |
20110060862 | Systems and Methods for Switchable Memory Configuration - Various embodiments of the disclosure provide systems, methods and circuits for implementation and use of a memory system. As one example, a memory system is disclosed that includes a plurality of memory devices and a configuration circuit. The configuration circuit includes at least one input, a plurality of outputs, and a programmable control circuit. The plurality of outputs are communicably coupled to the plurality of memory devices, and the programmable control circuit is operable to selectably couple the input to at least one of the plurality of outputs. | 03-10-2011 |
20110060863 | CONTROLLER - A controller stores therein a sector address set indicating logical storage positions within a nonvolatile-memory storage area; page addresses indicating, in units of pages, physical storage positions within the nonvolatile-memory storage area; and pieces of management information each indicating whether one or more special sectors each being either a bad sector or a trimmed sector trimmed by a TRIM command are present in the corresponding page, while associating them with each other. When an access to a specified sector address is requested, the device refers to the piece of management information and judges whether any special sector is present in the page identified by the page address corresponding to the sector address. The device generates predetermined response data if the page contains one or more special sectors and accesses the nonvolatile-memory storage position corresponding to the sector address if the page contains no special sector. | 03-10-2011 |
20110060864 | CONTROLLER AND DATA STORAGE DEVICE - A volatile management memory stores management information for managing a use state of a storage medium. A management information storing unit divides the management information into plural division pieces and individually stores them in the storage medium. A main controller receives a command from a host device while the division pieces are being stored, performs data processing for the storage medium in response to the command between each division piece is stored, updates the management information divided into the division pieces according to the data processing content, and creates a log representing an update content of the management information. A log storing unit stores the log in the storage medium. A restoring unit reads the division pieces stored in the storage medium to the management memory as the management information, updates the management information according to the log stored in the storage medium, and restores the updated management information. | 03-10-2011 |
20110060865 | Systems and Methods for Flash Memory Utilization - Various embodiments of the present invention provide systems, methods and circuits for memories and utilization thereof. As one example, a memory system is disclosed that includes a non-volatile memory, a flash memory, and a read/write controller circuit. The read/write controller circuit is coupled to both the flash memory and the non-volatile memory, and is operable to receive a data set directed to the flash memory and to direct the data set to the random access memory. | 03-10-2011 |
20110060866 | MEMORY SYSTEM - According to one embodiment, a memory system includes a first memory chip includes a first temporary memory and a first block, a second memory chip includes a second temporary memory and a second block, and a memory controller that controls writing of logical pages to the first and second memory chips. The memory controller forms a second unit having the same page number as the first unit by the first temporary memory and the lowermost physical page in the first block, forms a third unit having the same page number as the first unit by the second temporary memory and the lowermost physical page in the second block, and writes the logical pages by an interleave operation in order of the second unit, the third unit, the first unit in the first block, and the first unit in the second block. | 03-10-2011 |
20110060867 | DATA STORAGE DEVICE AND COMPUTER SYSTEM INCORPORATING SAME - A data storage device is configured to operate as an internal device of a first host system or an external device of a second host system, depending on whether it is connected to the second host system. A connection detector detects connections between the data storage device and the second host system and facilitates communication between the data storage device and the second host system upon detecting such connections. | 03-10-2011 |
20110060868 | MULTI-BANK FLASH MEMORY ARCHITECTURE WITH ASSIGNABLE RESOURCES - This disclosure has described embodiments of a nonvolatile memory that includes at least two concurrently accessible memory banks ( | 03-10-2011 |
20110060869 | LARGE CAPACITY SOLID-STATE STORAGE DEVICES AND METHODS THEREFOR - Non-volatile storage devices and methods capable of achieving large capacity SSDs containing multiple banks of memory devices. The storage devices include a printed circuit board, at least two banks of non-volatile solid-state memory devices, bank switching circuitry, a connector, and optionally a memory controller. The bank switching circuitry is functionally interposed between the banks of memory devices and either the connector or the memory controller. The bank switching circuitry operates to switch accesses by a system logic or the memory controller among the at least two banks. | 03-10-2011 |
20110060870 | NONVOLATILE MEMORY SYSTEMS WITH EMBEDDED FAST READ AND WRITE MEMORIES - A nonvolatile memory system is described with novel architecture coupling nonvolatile storage memory with random access volatile memory. New commands are included to enhance the read and write performance of the memory system. | 03-10-2011 |
20110060871 | SEMICONDUCTOR STORAGE DEVICE AND METHOD OF CONTROLLING THE SAME - A semiconductor storage device includes a first nonvolatile memory to store user data of a file, a second nonvolatile memory to store management data of the file, the second nonvolatile memory being different in type from the first nonvolatile memory, and a controller to control read/write of data with respect to the first and second nonvolatile memories. | 03-10-2011 |
20110060872 | SEMICONDUCTOR STORAGE DEVICE AND METHOD OF CONTROLLING THE SAME - A semiconductor storage device includes a first nonvolatile memory to store user data of a file, a second nonvolatile memory to store management data of the file, the second nonvolatile memory being different in type from the first nonvolatile memory, and a controller to control read/write of data with respect to the first and second nonvolatile memories. | 03-10-2011 |
20110060873 | SEMICONDUCTOR STORAGE DEVICE AND METHOD OF CONTROLLING THE SAME - A semiconductor storage device includes a first nonvolatile memory to store user data of a file, a second nonvolatile memory to store management data of the file, the second nonvolatile memory being different in type from the first nonvolatile memory, and a controller to control read/write of data with respect to the first and second nonvolatile memories. | 03-10-2011 |
20110060874 | SEMICONDUCTOR STORAGE DEVICE AND METHOD OF CONTROLLING THE SAME - A semiconductor storage device includes a first nonvolatile memory to store user data of a file, a second nonvolatile memory to store management data of the file, the second nonvolatile memory being different in type from the first nonvolatile memory, and a controller to control read/write of data with respect to the first and second nonvolatile memories. | 03-10-2011 |
20110060875 | FRACTIONAL PROGRAM COMMANDS FOR MEMORY DEVICES - A memory system ( | 03-10-2011 |
20110066787 | METHOD AND SYSTEM FOR SECURELY PROGRAMMING OTP MEMORY - A semiconductor chip may be operable to receive and copy an OTP programming vector presented by the semiconductor chip programming device into its memory after it boots up from the boot read-only memory (ROM). The OTP programming vector which is a computer program may comprise an encrypted data to be programmed into the one-time programmable (OTP) memory in the semiconductor chip and may be signed with an electronic signature. The semiconductor chip may be operable to authenticate the OTP programming vector in the memory. The authenticated OTP programming vector in the memory may be executed to decrypt the data and program the data in a random data format into the OTP memory and then report the status via one or more general purpose input/output (GPIO) pins on the semiconductor chip. | 03-17-2011 |
20110066788 | CONTAINER MARKER SCHEME FOR REDUCING WRITE AMPLIFICATION IN SOLID STATE DEVICES - A solid state storage device and method are provided. Multiple blocks are configured as storage memory for a solid state storage device, and each block includes multiple pages. A controller is configured to operate the solid state storage device. A free block of the multiple blocks is assigned a marker level by the controller. For a particular page of the multiple pages, each particular page of data is written to a block of the multiple blocks with a marker level corresponding to a level of dynamicity calculated by the controller for that particular page. | 03-17-2011 |
20110066789 | FILE SYSTEM DERIVED METADATA FOR MANAGEMENT OF NON-VOLATILE MEMORY - A file system programs metadata on a non-volatile memory device. The metadata can include data associating files with ranges of logical block addresses. During a garbage collection process, the data can be used to determine portions of physical blocks of the non-volatile memory device that are associated with files that have been deleted. Using the programmed metadata during garbage collection results in erasure of larger portions of blocks and improved wear leveling. | 03-17-2011 |
20110066790 | MAIN MEMORY WITH NON-VOLATILE MEMORY AND DRAM - One embodiment is main memory that includes a combination of non-volatile memory (NVM) and dynamic random access memory (DRAM). An operating system migrates data between the NVM and the DRAM. | 03-17-2011 |
20110066791 | CACHING DATA BETWEEN A DATABASE SERVER AND A STORAGE SYSTEM - Techniques are provided for using an intermediate cache between the shared cache of a database server and the non-volatile storage of a storage system. The intermediate cache may be local to the machine upon which the database server is executing, or may be implemented within the storage system. In one embodiment, the database system includes both a DB server-side intermediate cache, and a storage-side intermediate cache. The caching policies used to populate the intermediate cache are intelligent, taking into account factors that may include which database object an item belongs to, the item type of the item, a characteristic of the item; or the database operation in which the item is involved. | 03-17-2011 |
20110066792 | Segmentation Of Flash Memory For Partial Volatile Storage - This disclosure provides a method and system that segment flash memory to have differently managed regions. More particularly, flash memory is segmented into a “non-volatile” region, where program counts are restricted to preserve baseline retention assumptions, and a “volatile” region, where program counts are unrestricted. Contrary to conventional wisdom, wear leveling is not performed on all flash memory, as the volatile region is regarded as degraded, and as the non-volatile region has program counts restricted to promote long-term retention. More than two regions may also be created; each of these may be associated with intermediate program counts and volatility expectations, and wear leveling may be applied to each of these on an independent basis if desired. Refresh procedures may optionally be applied to the region of flash memory which is treated as volatile memory. | 03-17-2011 |
20110066793 | Implementing RAID In Solid State Memory - The present disclosure includes systems and techniques relating to implementing fault tolerant data storage in solid state memory. In some implementations, a method includes receiving data to be stored, dividing data into logical data blocks, assigning the blocks to a logical block grouping comprising at least one physical data storage block from two or more of multiple solid state physical memory devices, storing the blocks in physical data storage blocks, determining a code that corresponds to the persisted data, and storing the code that corresponds to the data stored in the logical block grouping. Blocks of damaged stored data may be recovered by identifying the logical data block and logical block grouping corresponding to the damaged physical data storage block, reading the data and the code stored in the identified grouping, and comparing the code to the read data other than the data stored in the damaged block. | 03-17-2011 |
20110066794 | SEMICONDUCTOR DEVICE AND METHOD OF CONTROLLING THE SAME - A semiconductor device comprises a board, a first semiconductor storage device placed on the board, and a second semiconductor storage device placed on the board. Each of the first and second semiconductor storage devices has a first pad for inputting a chip enable signal, a second pad for inputting a write enable signal, a third pad for inputting an output enable signal, a fourth pad for inputting an address signal, and a fifth pad for inputting data. The first semiconductor storage device has a sixth pad which is electrically connected to the first pad of the second semiconductor device, and the second semiconductor storage device has a seventh pad which is electrically connected to the first pad of the first semiconductor device. | 03-17-2011 |
20110072189 | METADATA REDUNDANCY SCHEMES FOR NON-VOLATILE MEMORIES - Systems and methods are provided for storing data to or reading data from a non-volatile memory (“NVM”), such as flash memory, using a metadata redundancy scheme. In some embodiments, an electronic device, which includes an NVM, may also include a memory interface for controlling access to the NVM. The memory interface may receive requests to write user data to the NVM. The user data from each request may be associated with metadata, such as a logical address, flags, or other data. In response to a write request, the NVM interface may store the user data and its associated metadata in a first memory location (e.g., page), and may store a redundant copy of the metadata in a second memory location. This way, even if the first memory location becomes inaccessible, the memory interface can still recover the metadata from the backup copy stored in the second memory location. | 03-24-2011 |
20110072190 | MEMORY DEVICE AND METHOD - A device is disclosed having a memory module that comprises a first memory block, a second memory block, a programmable storage location, and a memory controller. The first memory block of non-volatile memory comprises a plurality of word locations and an address decoder coupled to a first access port of the memory controller. The address decoder to select one of the plurality of word locations for access in response to receiving address information via the first access port. The second memory block comprising a plurality of word locations and an address decoder coupled to a second access port of the memory controller. The address decoder to select one of the plurality of word locations for access in response to receiving address information via the second access port. The memory controller comprising an input coupled to the programmable storage location, and to access, in response to the programmable configuration information having a first value, a first portion of the first memory block and a first portion of the second memory block as interleaved memory, a second portion of the first memory block as non-interleaved memory, and a second portion of the second memory block as non-interleaved memory. | 03-24-2011 |
20110072191 | Uniform Coding System for a Flash Memory - A uniform coding system for a flash memory is disclosed. A statistic decision unit determines a coding word according to a plurality of inputs. An inverse unit controllably inverts input data to be encoded. The input data are then encoded into encoded data according to a statistic determined by the statistic decision unit. | 03-24-2011 |
20110072192 | SOLID STATE MEMORY WEAR CONCENTRATION - A memory system includes a volatile memory and a non-volatile memory. The volatile memory is configured as a random access memory or cache for the nonvolatile memory. Wear concentration logic targets one or more selected devices of the nonvolatile memory for accelerated wear. | 03-24-2011 |
20110072193 | DATA READ METHOD, AND FLASH MEMORY CONTROLLER AND STORAGE SYSTEM USING THE SAME - A data read method for reading data to be accessed by a host system from a plurality of flash memory modules is provided. The data read method includes receiving command queuing information related to a plurality of host read commands from the host system, each of the host read commands is corresponding to one of a plurality of data input/output buses coupled to the flash memory modules. The data read method also includes re-arranging the host read commands and generating a command giving sequence according to the data input/output buses corresponding to the host read commands. The data read method further includes sequentially receiving and processing the host read commands from the host system according to the command giving sequence and pre-reading data corresponding to a second host read command. Thereby, the time for executing the host read commands can be effectively shortened. | 03-24-2011 |
20110072194 | Logical-to-Physical Address Translation for Solid State Disks - Described embodiments provide logical-to-physical address translation for data stored on a storage device having sectors organized into blocks and superblocks. A flash translation layer maps a physical address in the storage device to a logical sector address. The logical sector address corresponds to mapping data that includes i) a page index, ii) a block index, and iii) a superblock number. The mapping data is stored in at least one summary page corresponding to the superblock containing the physical address. A block index and a page index of a next empty page in the superblock are stored in a page global directory corresponding to the superblock. A block index and a page index of the at least one summary page and the at least one active block table for each superblock are stored in at least one active block table of the storage device. | 03-24-2011 |
20110072195 | METHOD FOR MANAGING A MEMORY DEVICE HAVING MULTIPLE CHANNELS AND MULTIPLE WAYS, AND ASSOCIATED MEMORY DEVICE AND CONTROLLER THEREOF - A method for managing a memory device having multiple channels and multiple ways includes: with regard to a logical page, finding a Flash memory chip for being written from a plurality of Flash memory chips according to a predetermined order of the Flash memory chips, and during finding the Flash memory chip, omitting any Flash memory chip that is busy or not suitable for writing; and writing data belonging to the logical page and a serial number for indicating a writing order into a corresponding physical page within a block of the Flash memory chip that is found. An associated memory device and a controller thereof are also provided, where the controller includes: a ROM arranged to store a program code; and a microprocessor arranged to execute the program code to control the access to the Flash memory chips. | 03-24-2011 |
20110072196 | Cache Synchronization for Solid State Disks - Described embodiments provide a media controller that synchronizes data cached in a buffer and corresponding data stored in one or more sectors of a storage device. A buffer layer module of the media controller caches data transferred between the buffer and the storage device. One or more contiguous sectors are associated with one or more chunks. The buffer layer module updates a status corresponding to each chunk of the cached data and scans the status corresponding to a first chunk of cached data. If, based on the status, the first chunk of cached data is more recent than the corresponding data stored on the storage device, a media layer module synchronizes the data on the storage device with the cached data. The status corresponding to the group of one or more sectors is updated. The media layer module scans a next chunk of cached data, if present. | 03-24-2011 |
20110072197 | Buffering of Data Transfers for Direct Access Block Devices - Described embodiments provide a method of transferring, by a media controller, data associated with a host data transfer between a host device and a storage media. A buffer layer module of the media controller segments the host data transfer into one or more data transfer segments. Each data transfer segment corresponds to at least a portion of the data. The buffer layer module allocates a number of physical buffers to a virtual circular buffer for buffering the one or more data transfer segments. The buffer layer module transfers, by the virtual circular buffer, each of the data transfer segments between the host device and the storage media through the allocated physical buffers. | 03-24-2011 |
20110072198 | ACCESSING LOGICAL-TO-PHYSICAL ADDRESS TRANSLATION DATA FOR SOLID STATE DISKS - Described embodiments provide a media controller for a storage device having sectors, the sectors organized into blocks and superblocks. The media controller stores, on the storage device, logical-to-physical address translation data in N summary pages, where N corresponds to the number of superblocks of the storage device. A buffer layer module of the media controller initializes a summary page cache in a buffer. The summary page cache has space for M summary page entries, where M is less than or equal to N. For operations that access a summary page, the media controller searches the summary page cache for the summary page. If the summary page is stored in the summary page cache, the buffer layer module retrieves the summary page from the summary page cache. Otherwise, the buffer layer module retrieves the summary page from the storage device and stores the retrieved summary page to the summary page cache. | 03-24-2011 |
20110072199 | STARTUP RECONSTRUCTION OF LOGICAL-TO-PHYSICAL ADDRESS TRANSLATION DATA FOR SOLID STATE DISKS - Described embodiments provide reconstruction of logical-to-physical address mapping data for one or more sectors of a storage device at startup of a media controller. The sectors of the storage device are organized into blocks and superblocks and the address mapping data is stored in a volatile memory. At a startup condition of the media controller, a buffer layer module of the media controller allocates space in the volatile memory for one or more logical-to-physical address mapping data structures. A media layer module of the media controller determines a block type of each block of the storage device and places each block of the storage device into corresponding groups based on the determined block type of each block. The one or more blocks of each group are processed, and one or more address mapping data structures for the storage device are constructed in the allocated space in the volatile memory. | 03-24-2011 |
20110072200 | Novel NAND-based hybrid NVM design that integrates NAND and NOR in 1-die with parallel interface - A nonvolatile memory device includes multiple independent nonvolatile memory arrays that concurrently for parallel reading and writing the nonvolatile memory arrays. A parallel interface communicates commands, address, device status, and data between a master device and nonvolatile memory arrays for concurrently reading and writing of the nonvolatile memory arrays and sub-arrays. Data is transferred on the parallel interface at the rising edge and the falling edge of the synchronizing clock. The parallel interface transmits a command code and an address code from a master device and transfers a data code between the master device and the nonvolatile memory device, wherein the data code has a length that is determined by the command code and a location determined by the address code. Reading one nonvolatile memory array may be interrupted for reading another. One reading operation has two sub-addresses with one transferred prior to a command. | 03-24-2011 |
20110072201 | Novel NAND-based hybrid NVM design that integrates NAND and NOR in 1-die with serial interface - A nonvolatile memory device includes multiple independent nonvolatile memory arrays that concurrently for parallel reading and writing the nonvolatile memory arrays. A serial interface communicates commands, address, device status, and data between a master device and nonvolatile memory arrays for concurrently reading and writing of the nonvolatile memory arrays and sub-arrays. Data is transferred on the serial interface at the rising edge and the falling edge of the synchronizing clock. The serial interface transmits a command code and an address code from a master device and transfers a data code between the master device and the nonvolatile memory device, wherein the data code has a length that is determined by the command code and a location determined by the address code. Reading one nonvolatile memory array may be interrupted for reading another. One reading operation has two sub-addresses with one transferred prior to a command. | 03-24-2011 |
20110072202 | METHOD FOR WEAR LEVELING IN A NONVOLATILE MEMORY - A method for writing and reading data memory cells, comprising: defining in a first memory zone erasable data pages and programmable data blocks; and, in response to write commands of data, writing data in erased blocks of the first memory zone, and writing, in a second memory zone, metadata structures associated with data pages and comprising, for each data page, a wear counter containing a value representative of the number of times that the page has been erased. | 03-24-2011 |
20110072203 | METHOD AND DEVICES FOR INSTALLING AND RETRIEVING LINKED MIFARE APPLICATIONS - A method for installing linked MIFARE applications (TK | 03-24-2011 |
20110072204 | MEMORY SERVER - A memory server providing remote memory for servers independent from the memory server. The memory server includes memory modules and a page table. A memory controller for the memory server allocates memory in the memory modules for each of the servers and manages remote memory accesses for the servers. The page table includes entries identifying the memory module and locations in the memory module storing data for the servers. | 03-24-2011 |
20110078362 | OPERATING AN EMULATED ELECTRICALLY ERASABLE (EEE) MEMORY - An emulated electrically erasable memory system includes a random access memory (RAM) and a non-volatile memory (NVM). A write access to the RAM is received which provides first write data and a first address, where the first write data is stored in the RAM at the first address, and a currently filling sector of the NVM is updated to store both the first write data and the first address as a first record. In response to the write access, based on whether there are any remaining active records in an oldest filled sector of the NVM, a portion of an erase process or a transfer of up to a predetermined number of active records from the oldest filled sector to the currently filling sector is performed. The predetermined number of active records is less than a maximum number of total records that may be stored within the oldest filled sector. | 03-31-2011 |
20110078363 | BLOCK MANAGEMENT METHOD FOR A FLASH MEMORY AND FLASH MEMORY CONTROLLER AND STORAGE SYSTEM USING THE SAME - A block management method for managing a plurality of physical blocks of a flash memory chip is provided. The block management method includes configuring a plurality of logical addresses; mapping the logical addresses to a plurality of logical blocks; and mapping the logical blocks to the physical blocks. Additionally, the block management method also includes obtaining deleting records related to a plurality of deleted logical addresses from a host system, wherein data stored in the deleted logical addresses is recognized as invalid by the host system. And, the block management method further includes obtaining a deleted logical block, marking each of the logical addresses mapped to the deleted logical block as a bad logical address, and linking the physical block mapped to the deleted logical block to a spare area. Accordingly, the block management method can effectively prolong the lifespan of a flash memory chip. | 03-31-2011 |
20110078364 | SOLID STATE STORAGE SYSTEM FOR CONTROLLING RESERVED AREA FLEXIBLY AND METHOD FOR CONTROLLING THE SAME - A solid state storage system includes a flash memory area and a memory controller. The flash memory area includes memory blocks and replacement blocks configured to replace bad blocks occurring within the memory blocks. The memory controller is configured to perform a logical-to-physical address mapping on logical blocks including the replacement blocks, and select the replacement blocks using logical addresses of the logical blocks corresponding to the bad blocks. | 03-31-2011 |
20110078365 | DATA ACCESS METHOD OF A MEMORY DEVICE - The invention provides a data access method of a memory device. In one embodiment, the memory device comprises a plurality of memories. First, a plurality of commands sequentially received from a host is stored in a command queue. A target command is then retrieved from the command queue. A target memory accessed by the target command is then determined. Whether the target memory is in a busy state is then determined. When the target memory is not in a busy state, access operations requested by the target command are then performed. When the target memory is in a busy state, a substitute command is selected from a plurality of subsequent commands stored in the command queue and access operations requested by the substitute command are performed, wherein the sequence of the subsequent commands in the command queue is subsequent to the target command. | 03-31-2011 |
20110078366 | Semiconductor device with non-volatile memory and random access memory - A semiconductor device including a large capacity non-volatile memory and at least one random access memory, said the access time of said device being matched to the access time of each random access memory. The semiconductor memory device is comprised of: a non-volatile memory FLASH having a first reading time; a random access memory DRAM having a second reading time which is more than 100 times shorter than the first reading time; a circuit that includes a control circuit connected to both the FLASH and the DRAM and enabled to control accesses to those FLASH and DRAM; and a plurality of I/O terminals connected to the circuit. As a result, FLASH data is transferred to the DRAM before the DRAM is accessed, thereby matching the access time between the FLASH and the DRAM. Data is written back from the DRAM to the FLASH as needed, thereby keeping data matched between the FLASH and the DRAM and storing the data. | 03-31-2011 |
20110082963 | POWER INTERRUPT MANAGEMENT - The present disclosure includes methods for operating a memory system, and memory systems. One such method includes updating transaction log information in a transaction log using write look ahead information; and updating a logical address (LA) table using the transaction log. | 04-07-2011 |
20110082964 | PARTITIONING PROCESS TO IMPROVE MEMORY CELL RETENTION - Subject matter disclosed herein relates to improving memory cell retention for non-volatile flash memory. | 04-07-2011 |
20110082965 | PROCESSOR-BUS-CONNECTED FLASH STORAGE MODULE - A system includes multiple nodes coupled using a network of processor buses. The multiple nodes include a first processor node, including one or more processing cores and main memory, and a flash memory node coupled to the first processor node via a first processor bus of the network of processor buses. The flash memory node includes a flash memory including flash pages, a first memory including a cache partition for storing cached flash pages for the flash pages in the flash memory and a control partition for storing cache control data and contexts of requests to access the flash pages, and a logic module including a direct memory access (DMA) register and configured to receive a first request from the first processor node via the first processor bus to access the flash pages. | 04-07-2011 |
20110082966 | Authentication and Securing of Write-Once, Read-Many (WORM) Memory Devices - These embodiments relate to authentication and securing of write-once, read-many (WORM) memory devices. In one embodiment, a memory device comprises a controller operable in first and second modes of operation after stored security information is validated, wherein in the first mode of operation, the memory device operates in a read-only mode, and wherein in the second mode of operation, the memory device operates in a write-once, read-many (WORM) mode. In another embodiment, the controller is operative to perform security methods. | 04-07-2011 |
20110082967 | Data Caching In Non-Volatile Memory - Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, can perform data caching. In some implementations, a method and system include receiving information that includes a logical address, allocating a physical page in a non-volatile memory structure, mapping the logical address to a physical address of the physical page, and writing, based on the physical address, data to the non-volatile memory structure to cache information associated with the logical address. The logical address can include an identifier of a data storage device and a logical page number. | 04-07-2011 |
20110082968 | NONVOLATILE MEMORY SYSTEM, AND DATA READ/WRITE METHOD FOR NONVOLATILE MEMORY SYSTEM - A nonvolatile memory system comprises a nonvolatile memory having a plurality of data areas; and a memory controller operative to control read and write operations to the nonvolatile memory. The memory controller successively executes read/write operations to plural sectors within a selected data area in the nonvolatile memory in accordance with a command and a sector count and sector address fed from a host device. | 04-07-2011 |
20110082969 | Associative data storage devices for authentication of collectable objects - In one embodiment of the present invention, an associative data storage device for authentication of collectable objects is described. A non-volatile electronic data storage device is used in combination with at least one collectable object. The non-volatile electronic data storage device is detached from the collectable object and electronically configured to store at least one immutable digital image of at least one unique appearance characteristic of the collectable object. The data storage device is provided with tamper resistant visual markings that are associative with visual markings of the collectable object so as to provide association of the data storage device with the collectable object. The non-volatile electronic data storage device is compatible with a standard computer system for a user to view one or more digital images of the unique appearance characteristics of the collectable object for authentication and identification of the collectable object. In preferred embodiments, the non-volatile data storage device is a solid-state Flash Memory type data storage device. | 04-07-2011 |
20110087823 | APPARATUS AND METHOD FOR PRODUCING IDS FOR INTERCONNECTED DEVICES OF MIXED TYPE - A plurality of memory devices of mixed type (e.g., DRAMs, SRAMs, MRAMs, and NAND-, NOR-, AND-type Flash memories) are serially interconnected. Each device has device type information on its device type. A specific device type (DT) and a device identifier (ID) contained in a serial input are fed to one device of the serial interconnection configuration. The device determines whether the fed DT matches the DT of the device. In a case of match, a calculator included in the device performs calculation to generate an ID for another device and the fed ID is latched in a register of the device. The generated ID is transferred to another device of the serial interconnection. In a case of no match, the ID generation is skipped and no ID is generated for another device. Such a device type match determination and ID generation or skip are performed in all devices of the serial interconnection. | 04-14-2011 |
20110087824 | FLASH MEMORY ACCESSING APPARATUS AND METHOD THEREOF - A flash memory accessing apparatus is disclosed. The flash memory accessing apparatus includes a controller, a first channel memory set and a second channel memory set. The first channel memory set includes a first flash memory and at least one first memory expanding socket. The second channel memory set includes a second flash memory and at least one second memory expanding socket. The controller determines the accessing method to be implemented on the first memory and second flash memory according to whether there is any flash memory inserted into the first memory expanding socket and the second memory expanding socket. | 04-14-2011 |
20110087825 | Electronic Device with Removable USB Flash Drive and USB Flash Drive with Added Functionality - A USB flash drive for removable connection to another device such as a cell phone, camera, computer, gaming system and photo printer, for example. In one embodiment, a cell phone having a USB port is provided wherein the USB flash drive configured to connect into a slot in the cell phone housing. A user may then quickly transfer data downloaded to the USB flash drive when connected to the cell phone, and another device such as a photo printer, for example. One or more optional additional functionality is incorporated into the USB flash drive such as, for example, a camera, internet card and MP3 player. | 04-14-2011 |
20110087826 | FLASH MEMORY ACCESSING APPARATUS AND ACCESSING METHOD THEREOF - A flash memory accessing apparatus is disclosed. The flash memory accessing apparatus includes a memory controller, a first open NAND flash interface (ONFI) and an expanding flash memory module. The first ONFI is used for connecting a main flash memory module. The memory controller obtains a detecting result by, detecting whether the main flash memory module and the expanding flash memory module are single side or double side. The memory controller further configures an accessing method of the main flash memory module and the expanding flash memory module according to the detecting result. | 04-14-2011 |
20110087827 | DATA WRITING METHOD FOR A FLASH MEMORY, AND CONTROLLER AND STORAGE SYSTEM USING THE SAME - A data writing method for writing data from a host system into a flash memory chip is provided. The method includes configuring a plurality of logical page addresses, grouping the logical page addresses into a plurality of logical blocks, and recording the data dispersion degree of each of the logical blocks. The method also includes receiving write-in data from the host system, identifying a logical block that a logical page address to be written by the host system belongs to, and writing the write-in data into the flash memory chip according to the data dispersion degree of the logical block, wherein the data dispersion degree of each of the logical blocks is not larger than a logical block data dispersion degree threshold value. Accordingly, the method can effectively reduce the time for executing a host write command. | 04-14-2011 |
20110087828 | METHOD FOR ENHANCING PERFORMANCE OF ACCESSING A FLASH MEMORY, AND ASSOCIATED MEMORY DEVICE AND CONTROLLER THEREOF - A method for enhancing performance of accessing a Flash memory, which includes a plurality of blocks and is positioned in a memory device, includes: during writing data into the Flash memory, establishing/updating at least one linking table in a random access memory (RAM) of the memory device, wherein regarding the Flash memory, the linking table indicates linking relationships between logical addresses and physical addresses, or indicates linking relationships between physical addresses and logical addresses; and writing the linking table into the Flash memory only when it is detected that a flush cache command is sent from a host device. An associated memory device and a controller thereof are also provided, where the controller includes: a read only memory (ROM) arranged to store a program code; and a microprocessor arranged to execute the program code to control the access to the Flash memory. | 04-14-2011 |
20110087829 | DATA STORAGE DEVICE AND DATA ACCESS METHOD - The invention provides a data storage device. In one embodiment, the data storage device comprises a storage medium, a random access memory, and a controller. The storage medium stores a plurality of link tables. The random access memory comprises a plurality of storage units respectively corresponding to a plurality of logical address ranges. The controller receives a target logical address from the host, determines a target link table corresponding to a logical address set comprising the target logical address, determines a target storage unit corresponding to a logical address range comprising the target logical address, determines whether the target storage unit has stored the target link table, and when the target storage unit has stored the target link table, determines a target physical address mapped to the target logical address according to a mapping relationship stored in the target link table, and accesses data stored in the storage medium according to the target physical address. | 04-14-2011 |
20110087830 | SYSTEM, METHOD AND APPARATUS FOR EMBEDDED FIRMWARE CODE UPDATE - A wireless module is provided for wirelessly updating code to any appropriate peripheral device and may allow for wireless communication with the desired peripheral device to update an operating software code. The wireless module has the similar size, shape, and form factor as the current Memory Stick™. In one embodiment, the method of updating code to the wireless module and/or the desired peripheral devices includes providing a fail-safe code to the peripheral device, updating the peripheral device with a new code utilizing the wireless module, and executing a primary code for operation of the peripheral device. Further, the wireless module may be provided to any number of peripheral devices compatible with the Memory Stick™ removable data storage media. The wireless module is removably connected to the desired peripheral device and provides the peripheral device with a fail-safe system, method and apparatus for updating the embedded operational software code without recalling and servicing the peripheral device. | 04-14-2011 |
20110087831 | MEMORY SYSTEM AND METHOD OF WRITING INTO NONVOLATILE SEMICONDUCTOR MEMORY - A memory system includes a nonvolatile semiconductor memory which includes a first original block composed of n (n being natural number) write unit areas and a first subblock composed of a plurality of write unit areas. A controller writes data having one of first to p-th (p being natural number smaller than n) addresses into the first original block. The controller writes data which has a first write address of one of the first to p-th addresses into the first subblock when the controller receives request to write data having the first write address and data having the first write address exists in the first original block. | 04-14-2011 |
20110087832 | WEAR LEVELING IN STORAGE DEVICES BASED ON FLASH MEMORIES AND RELATED CIRCUIT, SYSTEM, AND METHOD - A wear leveling solution is proposed for use in a storage device based on a flash memory. The flash memory includes a plurality of physical blocks, which are adapted to be erased individually. A corresponding method starts with the step for erasing one of the physical blocks. One of the physical blocks being allocated for storing data is selected; this operation is performed in response to the reaching of a threshold by an indication of a difference between a number of erasures of the erased physical block and a number of erasures of the selected physical block. At least the data of the selected physical block being valid is copied into the erased physical block. The selected physical block is then erased. | 04-14-2011 |
20110093646 | PROCESSOR-BUS ATTACHED FLASH MAIN-MEMORY MODULE - A method for processing a read request identifying an address. The method includes receiving, at a module including a flash memory and a memory buffer, the read request from a requesting processor, mapping, using a coherence directory controller within the module, the address to a cache line in a cache memory associated with a remote processor, and sending a coherency message from the module to the remote processor to change a state of the cache line in the cache memory. The method further includes receiving, at the module, the cache line from the remote processor, sending, using processor bus and in response to the read request, the cache line to the requesting processor, identifying a requested page stored within the flash memory based on the address, storing a copy of the requested page in the memory buffer, and writing the cache line to the copy of the requested page. | 04-21-2011 |
20110093647 | System And Method For Controlling Flash Memory - A system and method for controlling flash memory is provided, so that the flash memory controller can, without using the RB signal, use control interface to read the state register of at least a flash memory with received data for operation to detect whether the flash memory has already finishing operation on the received data, and when the operation on received data is to read, the controller can execute the state data switch so that the IO of flash memory can output correct flash memory data for read, or when the operation on received data is to write, the controller can execute another data operation to save time and accelerate the data operation speed of the flash memory. | 04-21-2011 |
20110093648 | ACHIEVING A HIGH THROUGHPUT IN A STORAGE CACHE APPLICATION USING A FLASH SOLID STATE DISK - According to one embodiment, a method for using flash memory in a storage cache comprises receiving data to be cached in flash memory of a storage cache, at least some of the received data being received from at least one of a host system and a storage medium, selecting a block of the flash memory for receiving the data, buffering the received data until sufficient data has been received to fill the block, and overwriting existing data in the selected block with the buffered data. According to another embodiment, a method comprises receiving data, at least some of the data being from a host system and/or a storage medium, and sequentially overwriting sequential blocks of the flash memory with the received data. Other devices and methods for working with flash memory in a storage cache according to various embodiments are included and described herein. | 04-21-2011 |
20110093649 | METHOD FOR MANAGING A PLURALITY OF BLOCKS OF A FLASH MEMORY, AND ASSOCIATED MEMORY DEVICE AND CONTROLLER THEREOF - A method for managing a plurality of blocks of a Flash memory includes: providing at least one logical-to-physical block linking table within the Flash memory, wherein regarding a plurality of logical block addresses, the logical-to-physical block linking table initially stores at least one initial value falling outside a range of respective physical block addresses of the Flash memory to prevent the logical block addresses from being initially linked to the physical block addresses; and when it is required to write data belonging to a logical block address into the Flash memory, writing a physical block address of the physical block addresses into an updated version of the logical-to-physical block linking table in order to link the logical block address to the physical block address. An associated memory device and a controller thereof are also provided, where the controller includes: a ROM; and a microprocessor. | 04-21-2011 |
20110093650 | NONVOLATILE MEMORY SYSTEM AND RELATED METHOD OF PRESERVING STORED DATA DURING POWER INTERRUPTION - A nonvolatile memory system comprises a temporary power supply that supplies power in the event of an unexpected power interruption. The temporary power supply provides power while metadata stored in one or more buffers is compressed and transferred to a nonvolatile memory device. | 04-21-2011 |
20110093651 | DATA STORAGE APPARATUS AND CONTROLLING METHOD OF THE DATA STORAGE APPARATUS - According to one embodiment, a data storage apparatus includes a first nonvolatile storage, a second nonvolatile storage and a controller. The controller is configured to control data writing and data reading for the first and second nonvolatile storage. The controller includes an allocation control module. The allocation control module is configured to allocate part of a storage area of the first nonvolatile storage to a logical address space and to allocate part or all of a storage area of the second nonvolatile storage to the logical address space in order to use the part of the storage area of the first nonvolatile storage allocated to the logical address space as storage area of substantial data, and to use part or whole of a remaining part of the storage area of the first nonvolatile storage not allocated to the logical address space as nonvolatile cache for the second nonvolatile storage. | 04-21-2011 |
20110093652 | MULTI-BIT-PER-CELL FLASH MEMORY DEVICE WITH NON-BIJECTIVE MAPPING - To store input data in a plurality of memory cells, a mapping function of bit sequences to physical parameter states of the cells is provided. The cells are programmed, in accordance with the mapping function, to store the input data, in a way that would store uniformly distributed data with a programming state distribution other than any native state distribution of the mapping function. To store input data in a single memory cell, a mapping function of bit sequences to states of a physical parameter of the cell, such that if uniformly distributed data were stored in a plurality of such memory cells then the states of the physical parameter of the cells would be distributed non-uniformly, is provided. The memory cell is programmed to store the input data in accordance with the mapping function. | 04-21-2011 |
20110093653 | MEMORY ADDRESS MANAGEMENT SYSTEMS IN A LARGE CAPACITY MULTI-LEVEL CELL (MLC) BASED FLASH MEMORY DEVICE - Methods and systems of managing memory addresses in a large capacity multi-level cell based flash memory device are described. According to one aspect, a flash memory device comprises a processing unit to manage logical-to-physical address correlation using an indexing scheme. The flash memory is partitioned into N sets. Each set includes a plurality of entries (i.e., blocks). N sets of partial logical entry number to physical block number and associated page usage information (hereinafter ‘PLTPPUI’) are stored in the reserved area of the MLC based flash memory. Only one the N sets is loaded to address correlation and page usage memory (ACPUM), which is a limited size random access memory (RAM). In one embodiment, static RAM (SRAM) is implemented for fast access time for the address correlation. LSA received together with the data transfer request dictates which one of the N sets of PLTPPUI is loaded into ACPUM. | 04-21-2011 |
20110099320 | Solid State Drive with Adjustable Drive Life and Capacity - A method for adjusting a drive life and a capacity of a solid state drive (SSD), the SSD comprising a plurality of memory devices includes determining a desired drive life for the SSD; determining a utilization for the SSD; and allocating a portion of the plurality of memory devices as available memory and a portion of the plurality of memory devices as spare memory based on the desired drive life and the utilization. An SSD with an adjustable drive life and capacity includes a plurality of memory devices; and a memory allocation module configured to: determine a desired drive life for the SSD; determine a utilization for the SSD; and allocate a portion of the plurality of memory devices as available memory and a portion of the plurality of memory devices as spare memory based on the desired drive life and the utilization. | 04-28-2011 |
20110099321 | ENABLING SPANNING FOR A STORAGE DEVICE - A storage device, e.g., an SSD, is configured to enable spanning for a logical block between pages of the device. In one example, a device includes a data storage module to receive data to be stored, wherein the data comprises a plurality of logical blocks, and wherein a size of the plurality of logical blocks exceeds a size of a first page of the device, and a spanning determination module to determine whether to partition one of the plurality of logical blocks into a first partition and a second partition, wherein the data storage module is configured to partition the one of the plurality of logical blocks into the first partition and the second partition and to store the first partition in the first page and the second partition in a second, different page when the spanning determination module determines to partition the one of the plurality of logical blocks. | 04-28-2011 |
20110099322 | DATA STORAGE DEVICE WITH INTEGRATED DNA STORAGE MEDIA - An integral digital memory storage device having a standard form factor to be received by and communicating with a computing device and having memory capability for storage of digital data. An integral multiwell DNA sample tray is carried in a body of the memory storage device for protection and exposed by manipulation of the case for receiving DNA samples. | 04-28-2011 |
20110099323 | NON-VOLATILE SEMICONDUCTOR MEMORY SEGREGATING SEQUENTIAL, RANDOM, AND SYSTEM DATA TO REDUCE GARBAGE COLLECTION FOR PAGE BASED MAPPING - A non-volatile semiconductor memory is disclosed comprising a memory device having a memory array including a plurality of memory segments. A plurality of sequential access write commands and random access write commands are received from a host, wherein each write command identifies at least one logical block address (LBA). The LBAs for the sequential access write commands are mapped to a plurality of the memory segments to generate sequential mapping data, and the sequential mapping data is mapped to a first one of the zones. The LBAs for the random access write commands are mapped to a plurality of the memory segments to generate random mapping data, and the random mapping data is mapped to a second one of the zones. | 04-28-2011 |
20110099324 | FLASH MEMORY STORAGE SYSTEM AND FLASH MEMORY CONTROLLER AND DATA PROCESSING METHOD THEREOF - A flash memory storage system including a flash memory chip, a connector, and a flash memory controller is provided. The flash memory controller configures a plurality of logical addresses and maps the logical addresses to a part of the physical addresses in the flash memory chip, and a host system uses a file system to access the logical addresses. Besides, the flash memory controller identifies a deleted logical address among the logical addresses and marks data in the physical address mapped to the deleted logical address as invalid data. Thereby, the flash memory storage system can identify data deleted by the host system in the physical addresses, so that the time for sorting data can be effectively reduced. | 04-28-2011 |
20110099325 | USER DEVICE AND MAPPING DATA MANAGEMENT METHOD THEREOF - In the mapping data management method, data that is being used by a host is stored in response to a power-off command from a user. The host generates a power-off notification signal to a storage device. The storage device stores mapping data of a volatile memory in a nonvolatile memory in response to the power-off notification signal. | 04-28-2011 |
20110099326 | FLASH MEMORY SYSTEM AND DEFRAGMENTATION METHOD - Provided is a flash memory system supporting flash defragmentation. The flash memory system includes a host and a flash storage device. In response to a flash defragmentation command by the host, the flash storage device performs flash defragmentation by grouping fragments stored in fragmented blocks of a flash memory on a flash memory management unit basis. The flash memory management unit may be a memory block or page. The flash storage device performs the flash defragmentation regardless of the arrangement order of fragmented files stored in the flash memory. | 04-28-2011 |
20110107009 | NON-VOLATILE MEMORY CONTROLLER DEVICE AND METHOD THEREFOR - A method of storing information at a non-volatile memory includes storing a status bit prior to storing data at the memory. A second status bit is stored after storing of the data. Because the storage of data is interleaved with the storage of the status bits, a brownout or other corrupting event during storage of the data will likely result in a failure to store the second status bit. Therefore, the first and second status bits can be compared to determine if the data was properly stored at the non-volatile memory. | 05-05-2011 |
20110107010 | ONE-TIME PROGRAMMABLE MEMORY DEVICE AND METHODS THEREOF - A portion of a programmable memory device is configured as a one-time programmable (OTP) memory, where in response to a write access to the memory device, a memory controller determines whether the write access is associated with a memory location designated as an OTP memory location. If so, the memory controller performs a read of the memory location, and allows the write access only if each memory cell of the memory location is in an un-programmed state. Thus, only a single write access to an OTP memory location is permitted, and subsequent write attempts are disallowed. Further, to enhance detection of programmed cells, the read of the OTP memory location is performed with a lower read voltage than a read voltage associated with a write access to a non-OTP memory location, thereby improving detection of programmed memory cells in the OTP memory location. | 05-05-2011 |
20110107011 | DATA DEFRAGMENTATION OF SOLID-STATE MEMORY - A method and apparatus for improving the performance of a computer system having a solid-state (flash) memory device as the main system memory. After weeks or months of frequent use, solid-state memories can become badly fragmented, and although every memory cell has basically the same access time to retrieve or to write data from or into that cell, vendors have found that self-defragging utilities within the memory device often improves overall performance. Yet if such defragging utilities are automatically run when other applications are running simultaneously, the drain on system performance can be very detrimental. To avoid the occurrence of unwanted self-defragging of these solid-state memory devices, we inhibit under some circumstances such functionality until it is deemed safe to do so. | 05-05-2011 |
20110107012 | NON-VOLATILE SEMICONDUCTOR MEMORY COMPRISING POWER FAIL CIRCUITRY FOR FLUSHING WRITE DATA IN RESPONSE TO A POWER FAIL SIGNAL - A non-volatile semiconductor memory is disclosed comprising a first memory device having a memory array including a plurality of memory segments, and a data register for storing write data prior to being written to one of the memory segments. A memory controller comprises a microprocessor for executing access commands received from a host. Interface circuitry generates control signals that enable the microprocessor to communicate with the first memory device. Power fail circuitry transmits a flush command to the first memory device through the interface circuitry in response to a power fail signal, wherein the first memory device responds to the flush command by transferring the write data stored in the data register to the memory segment. | 05-05-2011 |
20110107013 | High Throughput Flash Memory System - There is disclosed a memory system and method. The memory system may include a plurality of memory planes including two or more data memory areas, and a memory controller adapted to controlling reading, writing, and erasing of the plurality of memory planes. When any one of the data memory areas is occupied with one of a write operation and an erase operation, the controller may reconstruct data stored in the one occupied data memory area by reading parity information and data stored in the plurality of memory areas other than the one occupied data memory area. | 05-05-2011 |
20110107014 | MEMORY DEVICE PAGE BUFFER CONFIGURATION AND METHODS - Memory devices and methods are described that include communication circuitry between page buffers in a memory array. Examples include communication circuitry that provide status information of page buffers that are directly adjacent to a given page buffer. The exchanged information can be used to adjust a given page buffer to compensate for effects in directly adjacent data lines that are being operated at the same time. | 05-05-2011 |
20110107015 | DATA WRITING METHOD FOR A FLASH MEMORY, AND FLASH MEMORY CONTROLLER AND FLASH MEMORY STORAGE SYSTEM USING THE SAME - A data writing method for writing data from a host system into a flash memory chip having a plurality of physical blocks is provided. The method includes configuring a plurality of logical access addresses and recording address centers and address radiuses for the physical blocks. The method also includes receiving data to be written in logical access addresses, determining opened physical blocks among the physical blocks, and writing the data into the flash memory chip based on the logical access addresses, and the address centers and the address radiuses of the opened physical blocks. Accordingly, the method can effectively reduce the degree of data dispersion of each of the physical blocks, reduce the time for organizing valid data, and increase the speed for writing data. | 05-05-2011 |
20110107016 | SOLID STATE STORAGE SYSTEMS AND METHODS FOR FLEXIBLY CONTROLLING WEAR LEVELING - Solid-state storage systems and methods are provided for controlling a wear leveling process for uniform use of the memory cells that replaces worn memory blocks with less frequently used memory blocks. The wear leveling process is performed by changing the physical locations of the storage cells within each memory zone or plane. Reference values of target memory block erase counts and worn memory block erase counts are used for searching target memory blocks to be used as replacements. | 05-05-2011 |
20110107017 | Storage Apparatus and Data Access Method Thereof - A storage apparatus includes a first data section, a second data section, and a common data section. The first data section stores first data, the second data section stores second data, and the common data section stores common data. The storage apparatus stores a single copy of the common data. The common data and the first data correspond to a first memory bank. The common data and the second data correspond to a second memory bank. | 05-05-2011 |
20110107018 | PLURAL-PARTITIONED TYPE NONVOLATILE STORAGE DEVICE AND SYSTEM - A plural-partitioned type nonvolatile storage device which solves the problem that a memory card composed of a flash memory and a controller, when a storage area is divided into a plurality of partitions, cannot be correctly used with a conventional host apparatus incapable of recognizing plural partitions. The memory card includes, as its storage areas, a device characteristic data storage area, a division table storage area, and a device storage area, where the device storage area is partitioned into plural partitions. The memory card can have different, modes for adapting different accesses from the external host, and allows the external host to access partitions corresponding to the mode. Division information as to a dividing method for the plural partitions, and access information as to the host-accessible partitions corresponding to each individual mode are stored in the division table storage area. Plural types of device characteristic data corresponding to mode, respectively, are stored in the device characteristic data storage area. | 05-05-2011 |
20110113183 | Method for Managing a Non-Violate Memory and Computer Readable Medium Thereof - A method for managing a non-violate memory is provided. The non-violate memory has a number of blocks, and each block has a number of sub-blocks. The method includes a number of steps. First, a last physical address is obtained. The last physical address corresponds to a sub-block which is close to another sub-block where data is newly stored. Next, it is determined, for each sub-block of at least one block, the validity of data being stored. The at least one block is at least one neighboring block of a block containing the corresponding sub-block of the last physical address. Then, a mapping table is produced according to the step of determining the validity of data. | 05-12-2011 |
20110113184 | DATA BACKUP METHOD FOR A FLASH MEMORY AND CONTROLLER AND STORAGE SYSTEM USING THE SAME - A data backup method for backing up data temporarily stored in a cache memory of a flash memory storage device is provided, where the flash memory storage device has a plurality of physical units. The data backup method includes logically grouping a portion of the physical units into a data area and a cache area. The data backup method also includes determining whether a trigger signal is received; and when the trigger signal is received, copying the data temporarily stored in the cache memory into the cache area. Accordingly, the data backup method can quickly write the data temporarily stored in the cache memory into the physical units, thereby preventing a time out problem which may occur in the flash memory storage device. | 05-12-2011 |
20110113185 | MEMORY APPARATUS AND MEMORY CONTROLLER FOR ACCESSING NON-VOLATILE MEMORY - A memory apparatus includes a non-volatile memory and a memory controller, where the memory controller is coupled to the non-volatile memory and is utilized for accessing the non-volatile memory, and the memory controller and the non-volatile memory are positioned in two independent chips, respectively. When external data is intended to be written into the non-volatile memory, the memory controller compresses the external data and stores compressed external data into the non-volatile memory. | 05-12-2011 |
20110113186 | REDUCING ERASE CYCLES IN AN ELECTRONIC STORAGE DEVICE THAT USES AT LEAST ONE ERASE-LIMITED MEMORY DEVICE - A solution for reducing erase cycles in an electronic storage device that uses at least one erase-limited memory device is disclosed. | 05-12-2011 |
20110113187 | SEMICONDUCTOR DEVICE AND METHOD FOR CONTROLLING THE SAME - According to one embodiment, a semiconductor device includes a NAND flash memory, an SRAM, and a controller. The NAND flash memory includes a plurality of blocks with a plurality of memory cells and a decoder which selects the blocks. The NAND flash memory is capable of erasing data in a plurality of the blocks simultaneously during a multi-block erase operation. The decoder stores bad-block information at least during a read operation and a write operation and stores information on a plurality of erase target blocks during the multi-block erase operation. The SRAM stores the information on the erase target blocks. The controller reads information on the erase target blocks from the SRAM to set the information into the decoder in a multi-block erase operation. | 05-12-2011 |
20110113188 | MEMORY CARD AND HOST DEVICE THEREOF - A memory card is attached to a host device, and includes a data control circuit which transfers data with respect to the host device in synchronism with a rise edge and a fall edge of a clock signal. | 05-12-2011 |
20110119428 | Method of duplicating data to multiple random accessible storage devices - A method of duplicating data to multiple random accessible storage devices has steps of reading one segment of source data having multiple segments, continuously detecting newly-connected random accessible storage devices, duplicating same segments to all connected random accessible storage devices, stopping duplicating the source data to any random accessible storage device that has stored all segments of the source data and repeating the steps from the beginning. When duplicating the source data to all connected random accessible storage devices, same segments of the source data are written to all connected random accessible storage devices. Therefore, a single writing task is proceeded in each writing session. The source data can be written to all random accessible storage devices at high speed. Consequently, efficiency of asynchronously duplicating data to multiple random accessible storage devices is increased. | 05-19-2011 |
20110119429 | NONVOLATILE MEMORY CONTROLLER AND METHOD FOR WRITING DATA TO NONVOLATILE MEMORY - The invention provides a nonvolatile memory controller. In one embodiment, the nonvolatile memory controller receives new data for writing a nonvolatile memory from a host, and comprises a signature calculating circuit, a signature buffer, a signature comparison circuit, a data comparison circuit, and a nonvolatile memory interface circuit. The signature calculating circuit calculates a first signature according to the new data. The signature buffer outputs a second signature corresponding to old data stored in the nonvolatile memory, wherein the old data has the same logical address as that of the new data. The signature comparison circuit determines whether the first signature is identical to the second signature. The nonvolatile memory interface circuit writes the new data to the nonvolatile memory when the first signature is determined to be different from the second signature by the signature comparison circuit. | 05-19-2011 |
20110119430 | METHODS FOR MEASURING USABLE LIFESPAN AND REPLACING AN IN-SYSTEM PROGRAMMING CODE OF A MEMORY DEVICE, AND DATA STORAGE SYSEM USING THE SAME - A data storage system comprises a host and a flash memory device having a non-non-volatile memory. A controller of the flash memory device calculates an average erase count of the flash memory to obtaining a remaining period of time indicating usable lifespan of the flash memory device. The host obtains an index by comparing the average erase count with a first threshold and determines a performance capability status for the flash memory device. The performance capability status is set to a first status when the average erase count exceeds the first threshold. The host generates an indication based on the performance capability status and performs a limp function responsive to the first status. The limp function loads a predetermined in-system programming code for replacing an original one to configure a minimum number of at least some spare blocks of the flash memory reserved and used for data update operations. | 05-19-2011 |
20110119431 | MEMORY SYSTEM WITH READ-DISTURB SUPPRESSED AND CONTROL METHOD FOR THE SAME - According to one embodiment, a memory system includes a memory and a controller. The memory includes NAND strings. Each of the NAND strings includes memory cells. The memory cells capable of holding data. The memory writing and reading data in units of a page corresponding to a set of the memory cells and erasing data in units of a block corresponding to a set of the NAND strings. The controller controls the memory. The controller includes a holding unit and a control unit. The holding unit holds a table in which information on a check page is recorded, for each zone corresponding to a set of the blocks. The control unit references the table to calculate a read error and instructs the memory to write the data in the block including the check page to another block in the memory, if the occurrence rate exceeds a preset threshold. | 05-19-2011 |
20110119432 | NONVOLATILE MEMORY DEVICES HAVING IMPROVED READ PERFORMANCE RESULTING FROM DATA RANDOMIZATION DURING WRITE OPERATIONS - Memory devices include an array of non-volatile memory cells and a memory control circuit. The memory control circuit, which is electrically coupled to the array of non-volatile memory cells, includes a pseudo-random data coder/decoder circuit. This pseudo-random data coder/decoder circuit is configured to convert a first block of input data to be written into the memory device into a second block of data. This second block of data is encoded as a two-dimensional pseudo-random distribution of data values, which are more uniformly distributed relative to data values in the first block of input data. The memory control circuit is further configured to write the second block of data into the array of non-volatile memory cells during a plurality of page write operations. | 05-19-2011 |
20110119433 | METHOD AND APPARATUS FOR EMULATING BYTE WISE PROGRAMMABLE FUNCTIONALITY INTO SECTOR WISE ERASABLE MEMORY - A method and system for emulating a byte-wise programmable memory in a sector-wise erasable memory, where emulating a byte-wise programmable memory in a sector-wise erasable memory is based on dividing the sector-wise erasable memory in a plurality of sectors, dividing each of the sectors into several memory locations suitable to store containers, with each container having a header and a payload portion, and storing a data value relating to an application in the payload portion of one of the containers and header information identifying the application in the header in an available container. The containers can be block containers, and the data portion can have two or more payload values. The storing action can be performed in such a way that the two or more payload values in the payload portion together uniquely represent the data value. | 05-19-2011 |
20110119434 | System And Method For Safely Updating Thin Client Operating System Over A Network - A method for updating a thin client image includes the steps of writing a service operating system (OS) from a network device to limited capacity memory of a thin client device, writing a large part of a new image from the network to the memory of the thin client in a series of portions, without writing over the service OS, and writing a final small part of the new image over the service OS. | 05-19-2011 |
20110119435 | FLASH MEMORY STORAGE SYSTEM - A flash memory storage system has a plurality of flash memory devices comprising a plurality of flash memories, and a controller having an I/O processing control unit for accessing a flash memory device specified by a designated access destination in an I/O request received from an external device from among the plurality of flash memory devices. A parity group can be configured of flash memory devices having identical internal configuration. | 05-19-2011 |
20110119436 | FLASH MEMORY SYSTEM AND DATA WRITING METHOD THEREOF - Provided are a flash memory system and a data reading method thereof, the method including serially reading groups of data and parity codes corresponding to each of the respective groups from a page buffer; calculating the parity for each serially read group; checking for errors in each serially read group by comparing each calculated parity with a corresponding serially read parity code, respectively; and providing an output signal indicative of any comparative parity errors detected, wherein the reading of each group of data is followed by the reading of the parity code for the group, and the checking for errors in each group of data is done during the serial reading operation. | 05-19-2011 |
20110125953 | FLASH MEMORY ORGANIZATION FOR REDUCED FAILURE RATE - A memory system includes logic to distribute bits of a data word from a first memory across multiple pages of a flash memory. | 05-26-2011 |
20110125954 | DATA STORAGE METHOD FOR FLASH MEMORY, AND FLASH MEMORY CONTROLLER AND FLASH MEMORY STORAGE SYSTEM USING THE SAME - A data storage method for storing data into a flash memory chip is provided. The flash memory chip has a plurality of physical addresses, and these physical addresses include a plurality of fast physical addresses and a plurality of slow physical addresses. In the data storage method, the usage rate of the physical addresses is monitored. When the usage rate is not larger than a usage rate threshold value, only the fast physical addresses are used for storing the data into the flash memory chip. When the usage rate is larger than the usage rate threshold value, the fast physical addresses and the slow physical addresses are used for storing the data into the flash memory chip. Thereby, the speed of storing data into the flash memory chip is effectively increased. | 05-26-2011 |
20110125955 | FLASH STORAGE DEVICE, DATA STORAGE SYSTEM, AND DATA WRITING METHOD - The invention provides a flash storage device. In one embodiment, the flash storage device comprises a flash memory and a controller. The flash memory comprises a plurality of storage units for data storage, wherein the total capacity of each of the storage units is equal to a storage unit capacity. When the flash storage device receives a read capacity command from a host, the controller determines the size of a logical block to be a specific multiple of the storage unit capacity, and sends information about the logical block size to the host in response to the read capacity command, wherein the specific multiple is a natural number. After the host receives the information from the flash storage device, the host retrieves the logical block size from the information, and sends only write data with an amount equal to a multiple of the logical block size to the flash storage device. | 05-26-2011 |
20110125956 | TECHNIQUES FOR MULTI-MEMORY DEVICE LIFETIME MANAGEMENT - Techniques are provided for identifying at least one aspect associated with a lifetime of each of a plurality of memory devices. Further, data is moved between the plurality of memory devices, based on the at least one aspect. | 05-26-2011 |
20110125957 | System for accessing non-volatile memory - Accessing a non-volatile memory array is described, including receiving a first data and a memory address associated with the first data, writing the first data to the non-volatile memory array at the memory address of the first data without erasing a second data stored in the non-volatile memory array at the memory address of the first data before writing the first data. | 05-26-2011 |
20110125958 | SEMICONDUCTOR MEMORY CARD ACCESS APPARATUS, A COMPUTER-READABLE RECORDING MEDIUM, AN INITIALIZATION METHOD, AND A SEMICONDUCTOR MEMORY CARD - A predetermined number of erasable blocks positioned at a start of a volume area in a semiconductor memory card are provided so as to include volume management information. A user area following the volume management information includes a plurality of clusters. A data length NOM of an area from a master boot record & partition table sector to a partition boot sector is determined so that the plurality of clusters in the user area are not arranged so as to straddle erasable block boundaries. Since cluster boundaries and erasable block boundaries in the user area are aligned, there is no need to perform wasteful processing in which two erasable blocks are erased to rewrite one cluster. | 05-26-2011 |
20110125959 | E/P DURABILITY BY USING A SUB-RANGE OF A FULL PROGRAMMING RANGE - A NAND flash memory system is controlled by determining whether to change a value of a voltage threshold. The voltage threshold is associated with an erase operation to a portion of a NAND flash memory chip. In the event it is determined to change the value of the voltage threshold, the value of the voltage threshold is changed and the changed value of the voltage threshold and an identifier associated with the portion of the NAND flash memory chip is stored. | 05-26-2011 |
20110131364 | REPROGRAMMING A NON-VOLATILE SOLID STATE MEMORY SYSTEM - A non-volatile memory system ( | 06-02-2011 |
20110131365 | Data Storage System and Method - A data storage system and method are disclosed. The data storage system includes a first and a second memory and a memory control unit. The first memory is non-volatile, and the second memory is designed to store dynamic information of the first memory. The memory control unit includes a snapshot module, a recording module and a power-off recovery module, and is operative to handle the data loss of the second memory when an unexpected power-off occurs. When the power of the system is recovered, an initial address stored in the first memory by the snapshot module and link information and updating information recorded in the first memory by the recording module are obtained by the power-off recovery module to recovery the second memory. | 06-02-2011 |
20110131366 | MEMORY MANAGEMENT UNIT AND MEMORY MANAGEMENT METHOD - According to one embodiment, a memory management unit which controls a first memory as a nonvolatile memory and a second memory as a volatile memory, the memory management unit includes, judging whether data in the first memory desired to be accessed is stored in the second memory, setting an error flag to issue error data when the data is not stored in the second memory, and reading, into a free space of the second memory, the data to be accessed in the first memory. | 06-02-2011 |
20110131367 | NONVOLATILE MEMORY DEVICE, MEMORY SYSTEM COMPRISING NONVOLATILE MEMORY DEVICE, AND WEAR LEVELING METHOD FOR NONVOLATILE MEMORY DEVICE - A nonvolatile memory device comprises a memory core and a controller for controlling the wear level of a memory block in the nonvolatile memory device. The controller determines the wear level of a memory block by obtaining data of an actual wear level from a charge measurement cell of a selected region of the memory cell, and stores the wear level of the selected region in an erase count table. | 06-02-2011 |
20110131368 | METHOD AND APPARATUS FOR MANAGING ERASE COUNT OF MEMORY DEVICE - A non-volatile memory device having a hidden cell located separate from data storage cells, and a method of effectively managing an erase count of the non-volatile memory device. The method includes preparing the non-volatile memory device that includes a hidden cell located separate from data storage cells and is not accessible to users of the data storage cells, and increasing an erase count stored in an erase count storing region of the hidden cell corresponding to at least one erased data storage cell when the at least one data storage cell is erased. | 06-02-2011 |
20110131369 | LOGIC DEVICE - A logic device for communicating with a memory package with a first protocol, communicating with a memory controller with a second protocol, and for performing a protocol conversion between the first and the second protocol. | 06-02-2011 |
20110138103 | INTRA-BLOCK MEMORY WEAR LEVELING - A method for intra-block wear leveling within solid-state memory subjected to wear, having a plurality of memory cells includes the step of writing to at least certain ones of the plurality of memory cells, in a non-uniform manner, such as to balance the wear of the at least certain ones of the plurality of memory cells within the solid-state memory, at intra-block level. For example, if a behavior of at least some of the plurality of memory cells is not characterized, then the method may comprise characterizing a behavior of at least some of the plurality of memory cells and writing to at least certain ones of the plurality of memory cells, based on the characterized behavior, and in a non-uniform manner. | 06-09-2011 |
20110138104 | MULTI-WRITE CODING OF NON-VOLATILE MEMORIES - Multi-write coding of non-volatile memories including a method that receives write data, and a write address of a memory page. The memory page is in either an erased state or a previously written state. If the memory page is in the erased state: selecting a first codeword from a code such that the first codeword encodes the write data and is consistent with a target set of distributions of electrical charge levels in the memory page; and writing the first codeword to the memory page. If the memory page is in the previously written state: selecting a coset from a linear code such that the coset encodes the write data and includes one or more words that are consistent with previously written content of the memory page; selecting a subsequent codeword from the one or more words in the coset; and writing the subsequent codeword to the memory page. | 06-09-2011 |
20110138105 | NON-VOLATILE MEMORIES WITH ENHANCED WRITE PERFORMANCE AND ENDURANCE - Enhanced write performance for non-volatile memories including a memory system that includes a receiver for receiving a data rate of a data sequence to be written to a non-volatile flash memory device. The memory system also includes a physical page selector for selecting a physical address of an invalid previously written memory page from a group of physical addresses of invalid previously written memory pages located on the non-volatile memory device, and for determining if the number of free bits in the invalid previously written memory page at the selected physical address is greater than or equal to the data rate. The memory system also includes a transmitter for outputting the selected physical address of the invalid previously written memory page, the outputting in response to the physical page selector determining that the number of free bits is greater than or equal to the data rate. | 06-09-2011 |
20110138106 | EXTENDING SSD LIFETIME USING HYBRID STORAGE - A hybrid storage device uses a write cache such as a hard disk drive, for example, to cache data to a solid state drive (SSD). Data is logged sequentially to the write cache and later migrated to the SSD. The SSD is a primary storage that stores data permanently. The write cache is a persistent durable cache that may store data of disk write operations temporarily in a log structured fashion. A migration policy may be used to determine how long to cache the data in the write cache before migrating the data to the SDD. The migration policy may be implemented using one or more migration triggers that cause the contents of the write cache to be flushed to the SSD. Migration triggers may include a timeout trigger, a read threshold trigger, and a migration size trigger, for example. | 06-09-2011 |
20110138107 | USB NON-VOLATILE MEMORY SYSTEM FOR AN ELECTRONIC ENGINE CONTROLLER - An electronic engine controller has a processor, a data controller, and a non-volatile memory. During an engine operation, power is supplied to the processor, data controller, and non-volatile memory from an engine power source. Sensor data is received at the processor which supplies the sensor data to the data controller. The data controller stores the sensor data in the non-volatile memory. During data retrieval, power is supplied to the data controller and the non-volatile memory from a USB communications channel. The data controller retrieves the saved sensor data from the non-volatile memory and provides it to the USB communications channel. | 06-09-2011 |
20110138108 | METHOD OF ACTIVE FLASH MANAGEMENT, AND ASSOCIATED MEMORY DEVICE AND CONTROLLER THEREOF - A method of active Flash management is provided. The method is applied to a controller of a memory device, where the controller is utilized for accessing a Flash memory in the memory device, and the Flash memory includes a plurality of blocks. The method includes: extracting high level information of a file system of the Flash memory from contents stored in the Flash memory; and according to the high level information, managing operations that the controller performs on the Flash memory, in order to optimize at least one portion of the operations. An associated memory device and the controller thereof are further provided. | 06-09-2011 |
20110138109 | METHOD FOR WEAR-LEVELING AND APPARATUS THEREOF - A method for Wear-Leveling includes: utilizing a comparison circuit to compare an average erase count with an erase count of a first data block; and utilizing a first free block as a replacement for storing data content of the first data block so as to make the first data block become a free block when the erase count of the first data block is smaller than the average erase count. | 06-09-2011 |
20110138110 | METHOD AND CONTROL UNIT FOR PERFORMING STORAGE MANAGEMENT UPON STORAGE APPARATUS AND RELATED STORAGE APPARATUS - A storage apparatus has a first storage unit and a second storage unit. A method for performing storage management upon the storage apparatus includes: storing an input data into the first storage unit; and, while the input data is being stored into the first storage unit, checking whether the input data is continuous, wherein a portion of the input data which is not stored into the first storage unit yet will be stored into the first storage unit if the input data is found to be continuous, and the portion of the input data which is not stored into the first storage unit yet will be stored into the second storage unit if the input data is found to not be continuous. | 06-09-2011 |
20110138111 | FLASH MEMORY DEVICE AND METHOD OF PROGRAMMING SAME - A flash memory device comprises a memory cell array comprising memory cells arranged in rows and columns. A first page of data is programmed in selected memory cells of the memory cell array, and a second page of data is subsequently programmed in the selected memory cells. The first page of data is programmed using a program voltage having a first start value, and the second page of data is programmed using a program voltage having a second start value determined by a programming characteristic of the selected memory cells. | 06-09-2011 |
20110138112 | Virtualization of Storage Devices - Systems and techniques relating to storage technologies are described. A described technique includes operating drives such as a solid state drive (SSD) and a disk drive, where the SSD and the disk drive are virtualized as a single logical drive having a logical address space, where the logical drive maps logical block addresses to the SSD and to the disk drive. The technique includes determining, based on a file to be written to the logical drive, a target logical address that corresponds to one of the SSD and the disk drive, and writing the file to the logical drive at the target logical address to effect storage on one of the SSD and the disk drive. | 06-09-2011 |
20110138113 | RAID STORAGE SYSTEMS HAVING ARRAYS OF SOLID-STATE DRIVES AND METHODS OF OPERATION - RAID storage systems and methods adapted to enable the use of NAND flash-based solid-state drives. The RAID storage system includes an array of solid-state drives and a controller operating to combine the solid-state drives into a logical unit. The controller utilizes data striping to form data stripe sets comprising data (stripe) blocks that are written to individual drives of the array, utilizes distributed parity to write parity data of the data stripe sets to individual drives of the array, and writes the data blocks and the parity data to different individual drives of the array. The RAID storage system detects the number of data blocks of at least one of the data stripe sets and then, depending on the number of data blocks detected, may invert bit values of the parity data or add a dummy data value of “1” to the parity value. | 06-09-2011 |
20110138114 | Methods and Apparatus For Interfacing Between a Flash Memory Controller and a Flash Memory Array - Methods and apparatus are provided for interfacing between a flash memory controller and a flash memory array. The interface comprises a communication channel between the flash memory controller and the flash memory array, wherein the communication channel carries data for a target cell in the flash memory array on a first edge of a clock signal and wherein the communication channel carries additional information for the target cell on a second edge of the clock signal. For an exemplary write access, the additional information comprises, for example, information about one or more aggressor cells associated with the target cell. For an exemplary read access, the additional information comprises, for example, soft information for the data for the target cell transmitted on the first edge. | 06-09-2011 |
20110138115 | SOLID STATE MEMORY (SSM), COMPUTER SYSTEM INCLUDING AN SSM, AND METHOD OF OPERATING AN SSM - In one aspect, data is stored in a solid state memory which includes first and second memory layers. A first assessment is executed to determine whether received data is hot data or cold data. Received data which is assessed as hot data during the first assessment is stored in the first memory layer, and received data which is first assessed as cold data during the first assessment is stored in the second memory layer. Further, a second assessment is executed to determine whether the data stored in the first memory layer is hot data or cold data. Data which is then assessed as cold data during the second assessment is migrated from the first memory layer to the second memory layer. | 06-09-2011 |
20110138116 | Direct-attached/network-attached Storage Device - A multi-port data storage device that can be used simultaneously by both a direct-attached device and a network-attached device, comprising a hard disk drive (HDD), a DAS port, an NAS port, and a controller for controlling access to the HDD by the DAS port and the NAS port. | 06-09-2011 |
20110138117 | MEMORY CONTROLLER, NONVOLATILE STORAGE DEVICE, ACCESSING DEVICE, NONVOLATILE STORAGE SYSTEM, AND METHOD AND PROGRAM FOR WRITING DATA - A digital still camera performs temporary high-speed writing when capturing a large number of images in a short time. Lengthy processing for erased block allocation or copying performed inside a nonvolatile storage device may disable the captured images to be written completely (may cause some frames to drop). A nonvolatile storage system includes an access device ( | 06-09-2011 |
20110145472 | METHOD FOR ADDRESS SPACE LAYOUT RANDOMIZATION IN EXECUTE-IN-PLACE CODE - A method for dynamically (i.e., upon boot) rewriting, in a failure resistant manner, of part of, or the entirety of, the flash memory for a device allows for a changing of location for logical blocks of execute-in-place code. Conveniently, the rewriting results in a randomization, of varying degree, of the address space layout upon each boot up cycle. | 06-16-2011 |
20110145473 | Flash Memory Cache for Data Storage Device - A storage device made up of multiple storage media is configured such that one such media serves as a cache for data stored on another of such media. The device includes a controller configured to manage the cache by consolidating information concerning obsolete data stored in the cache with information concerning data no longer desired to be stored in the cache, and erase segments of the cache containing one or more of the blocks of obsolete data and the blocks of data that are no longer desired to be stored in the cache to produce reclaimed segments of the cache. | 06-16-2011 |
20110145474 | Efficient Use Of Flash Memory In Flash Drives - A data storage device having non-volatile solid state memory permits efficient access by permitting multiple pending commands from a host device. A controller in the data storage device stores information about each command from the host device, and determines which stored command, if any, is presently able to be performed based on the portion of the non-volatile memory and the type of access of the command. The data storage device provides reduced access delays, improves read/write throughput, and avoids the cost of additional memory in the data storage device, by allowing accesses to idle portions of memory to proceed, and by signaling the host device when the data storage device is able to accept data to be written to portions of the non-volatile memory already active due to a previous command. | 06-16-2011 |
20110145475 | REDUCING ACCESS CONTENTION IN FLASH-BASED MEMORY SYSTEMS - Exemplary embodiments include a method for reducing access contention in a flash-based memory system, the method including selecting a chip stripe in a free state, from a memory device having a plurality of channels and a plurality of memory blocks, wherein the chip stripe includes a plurality of pages, setting the ship stripe to a write state, setting a write queue head in each of the plurality of channels, for each of the plurality of channels in the flash stripe, setting a write queue head to a first free page in a chip belonging to the channel from the chip stripe, allocating write requests according to a write allocation scheduler among the channels, generating a page write and in response to the page write, incrementing the write queue head, and setting the chip stripe into an on-line state when it is full. | 06-16-2011 |
20110145476 | Persistent Content in Nonvolatile Memory - Applications may request persistent storage in nonvolatile memory. The persistent storage is maintained across power events and application instantiations. Persistent storage may be maintained by systems with or without memory management units. | 06-16-2011 |
20110145477 | FLASH TRANSLATION LAYER USING PHASE CHANGE MEMORY - A FLASH translation layer (FTL) includes a translation table that is maintained in non-FLASH memory. The translation table maps logical addresses to physical addresses and may be maintained in phase change memory (PCM). A bad block table (BBT) may also be maintained in non-FLASH memory. | 06-16-2011 |
20110145478 | METHOD TO IMPROVE A SOLID STATE DISK PERFORMANCE BY USING A PROGRAMMABLE BUS ARBITER - A method to improve a solid state disk performance by using a programmable bus arbiter is generally presented. In this regard, in one embodiment, a method is introduced comprising delaying a request from a solid state drive for access to an interface for a time to allow a host to access the interface to transmit a command to the solid state drive. Other embodiments are described and claimed. | 06-16-2011 |
20110145479 | EFFICIENT USE OF HYBRID MEDIA IN CACHE ARCHITECTURES - A multi-tiered cache manager and methods for managing multi-tiered cache are described. Multi-tiered cache manager causes cached data to be initially stored in the RAM elements and selects portions of the cached data stored in the RAM elements to be moved to the flash elements. Each flash element is organized as a plurality of write blocks having a block size and wherein a predefined maximum number of writes is permitted to each write block. The portions of the cached data may be selected based on a maximum write rate calculated from the maximum number of writes allowed for the flash device and a specified lifetime of the cache system. | 06-16-2011 |
20110145480 | FLASH MEMORY STORAGE SYSTEM FOR SIMULATING REWRITABLE DISC DEVICE, FLASH MEMORY CONTROLLER, COMPUTER SYSTEM, AND METHOD THEREOF - A flash memory storage system including a flash memory chip, a connector, and a controller is provided. The flash memory chip has a plurality of physical blocks. The connector is configured to couple to a host system. The controller is coupled to the flash memory chip and the connector. The controller configures a plurality of logical blocks and maps the logical blocks to a portion of the physical blocks. In addition, the controller identifies rewritable disc commands from the host system and writes data from the host system into the physical blocks mapped to the logical blocks according to the rewritable disc commands. Thereby, a rewritable disc device is simulated by using the flash memory storage system. | 06-16-2011 |
20110145481 | FLASH MEMORY MANAGEMENT METHOD AND FLASH MEMORY CONTROLLER AND STORAGE SYSTEM USING THE SAME - A flash memory management method for managing a plurality of physical units of a flash memory chip is provided. The flash memory management method includes grouping a portion of the physical units into a data area and a spare area; configuring a plurality of logical units and setting mapping relationships between the logical units and the physical units of the data area. The flash memory management method further includes receiving data and writing the data into the physical unit mapped to a second logical unit among the logical units, and the data belongs to a first logical unit among logical units. Accordingly, the flash memory management method can effectively reduce the number of times for organizing valid data, thereby reducing the time for executing a host write-in command. | 06-16-2011 |
20110145482 | BLOCK MANAGEMENT METHOD FOR FLASH MEMORY, AND FLASH MEMORY CONTROLLER AND FLASH MEMORY STORAGE DEVICE USING THE SAME - A block management method for managing blocks of a flash memory storage device is provided. The flash memory storage device includes a flash memory controller. The block management method includes the following steps. At least a part of the blocks is grouped into a first partition and a second partition. Whether an authentication code exists is determined. When the authentication code exists, the blocks belonging to the first partition are provided for a host system to access, so the host system displays the first partition and hides the second partition. An authentication information is received from the host system. Whether the authentication information and the authentication code are identical is authenticated. When the authentication information and the authentication code are identical, the blocks belonging to the second partition are provided for the host system to access, so the host system displays the second partition and hides the first partition. | 06-16-2011 |
20110145483 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF PROCESSING DATA FOR ERASE OPERATION OF SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises a plurality of memory blocks, and erase flag storage block storing erase flag information to indicate erase states of the plurality of memory blocks. The erase flag information can be used to monitor completion of erase operations of the memory blocks and to update erase count information of the memory blocks. | 06-16-2011 |
20110145484 | Exhaustive Parameter Search Algorithm for Interface with Nand Flash Memory - The Exhaustive Parameter Search (EPS) algorithm of this invention enables communicating devices to access to a large variety of NAND Flash memories. The EPS algorithm exploits the fact that the parameters needed for successful initial communication with NAND Flash memory (block Size and page Size) have only few possible values. The EPS algorithm tries all possible values to find a magic number stored in the NAND Flash memory. The correct parameters for the particular NAND Flash memory are read after detection of the magic number. This ensures that accurate parameters are used after successful detection of the magic number detection. The OEM must write the known parameters of the NAND Flash memory in a predetermined location following the magic number. | 06-16-2011 |
20110145485 | METHOD FOR MANAGING ADDRESS MAPPING TABLE AND A MEMORY DEVICE USING THE METHOD - An address mapping table includes arrays each being allocated to a logical address and in which a physical address mapping the logical address is stored. In the case where the physical address mapped to the logical address is changed, a value of a difference between a pre-changed physical address and a physical address to be changed is stored in the address mapping table. When the logical address is mapped to the physical address, the mapped physical address is calculated by adding up the logical address and values stored in the arrays allocated to the logical address. The address mapping table is managed to decrease the number of erase counts of a memory device in which the address mapping table is stored. | 06-16-2011 |
20110145486 | MEMORY MANAGEMENT DEVICE AND METHOD - According to one embodiment, a device includes a determination unit, compression unit, selecting unit, write updating unit, writing unit. The determination unit determines whether to compress write data based on specific information. The specific information including at least one of the type, number of accesses, access frequency and importance level of the write data. The compression unit compresses the write data when determining to compress the write data. The selecting unit selects a write region for the write data in nonvolatile memory based on the specific information. The write updating unit updates the specific information. The writing unit writes compressed write data into the write region when determining to compress the write data. The writing unit writes uncompressed write data into the write region when not determining to compress the write data. | 06-16-2011 |
20110145487 | Methods and Apparatus for Soft Demapping and Intercell Interference Mitigation in Flash Memories - Methods and apparatus are provided for soft demapping and intercell interference mitigation in flash memories. In one variation, a target cell in a flash memory device capable of storing at least two data levels, s, per cell is read by obtaining a measured read value, r, for at least one target cell in the flash memory; obtaining a value, h, representing data stored for at least one aggressor cell in the flash memory; selecting one or more probability density functions based on a pattern of values stored in at least a portion of the flash memory, wherein the probability density functions comprises pattern-dependent disturbance of one or more aggressor cells on the at least one target cell in the flash memory; evaluating at least one selected probability density function based on the measured read value, r; and computing one or more log likelihood ratios based on a result of the evaluating step. | 06-16-2011 |
20110145488 | FLASH MEMORY MODULE, STORAGE APPARATUS USING FLASH MEMORY MODULE AS RECORDING MEDIUM AND ADDRESS TRANSLATION TABLE VERIFICATION METHOD FOR FLASH MEMORY MODULE - A purpose of the invention is to immediately return the operation in a flash memory module from low power consumption mode to regular mode. A flash memory controller having memory that stores an address translation table for translating between a logical page address and a physical page address in the flash memory chip controls regular mode and low power consumption mode of operating at lower power consumption than in regular mode by halting operation, or decreasing power supply voltage or lowering operating frequency. A flash memory module having the flash memory controller verifies data in the address translation table while low power consumption mode is set. | 06-16-2011 |
20110145489 | HYBRID STORAGE DEVICE - A hybrid storage device comprises both solid-state disk (SDD) and at least one hard disk drive (HDD). The hybrid storage device has at least two operational modes: concatenation and safe. According to one aspect, the total capacity of hybrid storage device is the sum of SSD and at least one HDD in a concatenation or big mode, while the total capacity is the capacity of the HDD in a safe mode. | 06-16-2011 |
20110145490 | DEVICE AND METHOD OF CONTROLLING FLASH MEMORY - Disclosed is a flash memory controlling method and controlling device. The flash memory controlling method including calculating a cost for each of available block recycling schemes based on a multi-block erase function when the multi-block erase function is supported, the multi-block erase function being a function that simultaneously erases data stored in a plurality of blocks of a flash memory and selecting at least one scheme from among the available block recycling schemes based on the calculated cost, and managing at least one block using the at least one method selected from among the available block recycling schemes. | 06-16-2011 |
20110153910 | Flash Memory-Interface - Flash-type memory access and control is facilitated (e.g., as random-access memory). According to an example embodiment, an interface communicates with and controls a flash memory circuit over a peripheral interface bus. The interface uses a FIFO buffer coupled to receive data from and store data for the flash memory circuit and to provide access to the stored data. An interface controller communicates with the flash memory circuit via the peripheral interface bus to initialize the flash memory circuit and to access data thereto, in response to requests from a processor. In some applications, the flash memory circuit is initialized by sending commands to it. The interface may be placed into a read-only mode in which data in the flash memory is accessed as part of main (computer) processor memory, using the FIFO to buffer data from the flash. | 06-23-2011 |
20110153911 | METHOD AND SYSTEM FOR ACHIEVING DIE PARALLELISM THROUGH BLOCK INTERLEAVING - A method and system for achieving die parallelism through block interleaving includes non-volatile memory having a multiple non-volatile memory dies, where each die has a cache storage area and a main storage area. A controller is configured to receive data and write sequentially addressed data to the cache storage area of a first die. The controller, after writing sequentially addressed data to the cache storage area of the first die equal to a block of the main storage area of the first die, writes additional data to a cache storage area of a next die until sequentially addressed data is written into the cache area of the next die equal to a block of the main storage area. The cache storage area may be copied to the main storage area on the first die while the cache storage area is written to on the next die. | 06-23-2011 |
20110153912 | Maintaining Updates of Multi-Level Non-Volatile Memory in Binary Non-Volatile Memory - A method of operating a memory system is presented. The memory system includes a controller and a non-volatile memory circuit, where the non-volatile memory circuit has a first portion, where data is stored in a binary format, and a second portion, where data is stored in a multi-state format. The controller manages the transfer of data to and from the memory system and the storage of data on the non-volatile memory circuit. The method includes receiving a first set of data and storing this first set of data in a first location in the second portion of the non-volatile memory circuit. The memory system subsequently receives updated data for a first subset of the first data set. The updated data is stored in a second location in the first portion of the non-volatile memory circuit, where the controller maintains a logical correspondence between the second location and the first subset of the first set of data. | 06-23-2011 |
20110153913 | Non-Volatile Memory with Multi-Gear Control Using On-Chip Folding of Data - A memory system and methods of its operation are presented. The memory system includes a controller and a non-volatile memory circuit, where the non-volatile memory circuit has a first section, where data is stored in a binary format, and a second section, where data is stored in a multi-state format. The memory system receives data from the host and performs a binary write operation of the received data to the first section of the non-volatile memory circuit. The memory system subsequently folds portions of the data from the first section of the non-volatile memory to the second section of the non-volatile memory, wherein a folding operation includes reading the portions of the data from the first section rewriting it into the second section of the non-volatile memory using a multi-state programming operation. The controller determines to operate the memory system according to one of multiple modes. The modes include a first mode, where the binary write operations to the first section of the memory are interleaved with folding operations at a first rate, and a second mode, where the number of folding operations relative to the number of the binary write operations to the first section of the memory are performed at a higher than in the first mode. The memory system then operates according to determined mode. The memory system may also include a third mode, where folding operations are background operations executed when the memory system is not receiving data from the host. | 06-23-2011 |
20110153914 | REPURPOSING NAND READY/BUSY PIN AS COMPLETION INTERRUPT - A system and method of controlling a flash memory device such as a NAND memory device may involve receiving a command to execute an operation. A Ready/Busy contact of the memory device may be pulsed low in response to determining that execution of the operation has completed. | 06-23-2011 |
20110153915 | READ PREAMBLE FOR DATA CAPTURE OPTIMIZATION - Systems and/or methods are provided that facilitate data capture optimization for devices accessing memories via a bus. In an aspect, a memory can output a read preamble prior to pushing data onto a bus. The read preamble can be a known sequence of one or more bits. A host device accessing the memory via the bus can analyze the read preamble and, particularly, timing characteristics of the read preamble. The timing characteristics can be utilized to identify an optimal capture point within a window of data validity. | 06-23-2011 |
20110153916 | HYBRID MEMORY ARCHITECTURES - Methods and apparatuses for providing a hybrid memory module having both volatile and non-volatile memories to replace a DDR channel in a processing system. | 06-23-2011 |
20110153917 | STORAGE APPARATUS AND ITS CONTROL METHOD - Proposed are a storage apparatus and its control method capable of performing power saving operations while covering the shortcomings of a flash memory such as the life being short and much time being required for rewriting data. This storage apparatus manages the storage areas provided by each of multiple nonvolatile memories as a pool, provides a virtual volume to a host computer, dynamically allocates the storage area from a virtual pool to the virtual volume according to a data write request from the host computer for writing data into the virtual volume, and places the data in the allocated storage area. In addition, the storage apparatus centralizes the placement destination of data from the host computer to a storage area provided by certain nonvolatile memories and stop the power supply to the nonvolatile memories that are unused, monitors the data rewrite count and/or access frequency to storage areas provided by the nonvolatile memories that are active, migrates data to another storage area if the data rewrite count increases, and distributes the data placement destination if the access frequency becomes excessive. | 06-23-2011 |
20110153918 | DATA WRITING METHOD AND DATA STORAGE DEVICE - The invention provides a data writing method for a flash memory. First, a write command, a write address, and write data are received from a host. When a total number of block pairs in the flash memory is equal to a threshold value, and execution of the write command increases the total number of block pairs, the write data is written to a data buffer block of the flash memory, and the write address is stored in an address storage table. A target block pair comprising a target mother block and a target child block is then selected from the block pairs for integration. The target mother block and the target child block are integrated into an integrated block during receiving intervals of a plurality of subsequent write commands. Finally, the write command is executed according to the write data stored in the data buffer block and the write address stored in the address storage table. | 06-23-2011 |
20110153919 | DEVICE, SYSTEM, AND METHOD FOR REDUCING PROGRAM/READ DISTURB IN FLASH ARRAYS - A method, device and computer readable medium for programming a nonvolatile memory block. The method may include programming information, by a memory controller, to the nonvolatile memory block by performing a sequence of programming phases of descending bit significances. The device may include a nonvolatile memory block; and a memory controller that may be configured to determine a bit significance level of the nonvolatile memory block; program the nonvolatile memory block by performing at least one programming phase; and program the nonvolatile memory block to an erase value that may be higher than the pre-erase value; wherein the erase value and the pre-erase value may be selected based on the bit significance level of the nonvolatile memory block. The method may include packing three single level cell (SLC) nonvolatile memory blocks to one three-bit per cell nonvolatile memory block in order of the three SLC bit significances. | 06-23-2011 |
20110153920 | ELECTRONIC APPARATUS OF RECORDING DATA USING NON-VOLATILE MEMORY - An electronic apparatus for recording data using a non-volatile memory is provided. The electronic apparatus includes a non-volatile memory and a controller. The non-volatile memory stores a plurality of sets of playing information of the electronic apparatus. The controller is coupled to the non-volatile memory for receiving an input data and transforming a data structure of the input data into a bitmapping data structure. The controller includes a bitmapping module that is capable of transforming the input data into data having at least one bit but less than one byte in a bitmapping manner. | 06-23-2011 |
20110153921 | System Embedding Plural Controller Sharing Nonvolatile Memory - An embedded memory card system includes a first CPU, a second CPU, a nonvolatile memory storing data, and a device busy state machine selecting one of the first CPU and the second CPU to access the nonvolatile memory. The nonvolatile memory is accessed by the one of the first CPU and the second CPU selected by the device busy state machine. | 06-23-2011 |
20110153922 | NON-VOLATILE MEMORY DEVICE HAVING ASSIGNABLE NETWORK IDENTIFICATION - Memory devices and methods disclosed such as a memory device having a plurality of memory dies where each die includes a network identification that uniquely identifies the memory die on a bus. Access for each memory die to the bus can be scheduled by a bus controller. | 06-23-2011 |
20110161551 | VIRTUAL AND HIDDEN SERVICE PARTITION AND DYNAMIC ENHANCED THIRD PARTY DATA STORE - A system reserves and manages a hidden service partition through components of the hardware platform of a computing device. The hidden partition is not accessible by way of a host operating system on the computing device. A hardware platform controller provisions a portion of nonvolatile storage through configuration settings of the hardware platform controller. When the host system requests settings related to storage in the system, the request is routed through the interfaces of the hardware platform, and the hardware platform controller reports in accordance with the configuration settings, hiding the service partition. The hidden partition is dynamically modifiable through secure remote access to the hardware platform controller, not through the host system such as operating system or BIOS. | 06-30-2011 |
20110161552 | Command Tracking for Direct Access Block Storage Devices - Described embodiments provide tracking and processing of commands received by a storage device. For each received command, the storage device determines one or more requested logical block addresses (LBAs), including a starting LBA and a length of one or more LBAs of the received command. The storage device determines whether command reordering is restricted. If command reordering is not restricted, the storage device processes the received commands. Otherwise, if command reordering is restricted, the storage device conflict checks each received command. If no conflict is detected, the storage device tracks and processes the received command. Otherwise, if a conflict is detected, the storage device queues the received command. | 06-30-2011 |
20110161553 | MEMORY DEVICE WEAR-LEVELING TECHNIQUES - The wear-leveling techniques include discovering a persistent state of one or more memory devices, or building and caching persistent state parameters for each logical unit of a given memory device if a persistent state is not discovered for a given memory device. The techniques may also include processing memory access commands utilizing the cached persistent state parameters. When processing memory access commands, the logical block address and length parameter of a logical address of a command may be translated to a plurality of physical addresses for accessing one or more memory devices, each physical address includes a device address, a logical unit address, a block address, and a page address, wherein the block address includes one or more interleaved address bits. | 06-30-2011 |
20110161554 | Method and Controller for Performing a Sequence of Commands - The embodiments described herein provide a method and controller for performing a sequence of commands. In one embodiment, a controller receives a command from a host to perform a memory operation in a flash memory device, wherein the command comprises at least one bit that indicates whether the command is a stand-alone command or is part of a sequence of commands. The controller analyzes the at least one bit to determine whether the at least one bit indicates that the command is a stand-alone command or is part of a sequence of commands. If the at least one bit indicates that the command is a stand-alone command, the controller performs the command. If the at least one bit indicates that the command is part of a sequence of commands, the controller performs the command as part of the sequence of commands. | 06-30-2011 |
20110161555 | DYNAMIC DATA FLOW MANAGEMENT IN A MULTIPLE CACHE ARCHITECTURE - The disclosure is related to systems and methods of dynamic dataflow in a multiple cache architecture. In an embodiment, a system having a data storage device with a multiple cache architecture may detect at least one attribute affecting a data storage workload or data storage performance. The system may select at least one of a plurality of data flow schemes based on the at least one attribute, which may be done to optimize the data storage workload for various conditions. In another embodiment, a data storage controller may automatically and dynamically select one of multiple data flow schemes within a data storage device having a multiple cache architecture. The data storage controller may monitor attributes to determine which data flow scheme to select for various workloads of the data storage device. | 06-30-2011 |
20110161556 | SYSTEMS AND METHODS FOR STORING DATA IN A MULTI-LEVEL CELL SOLID STATE STORAGE DEVICE - This disclosure is related to systems and methods for storing data in multi-level cell solid state storage devices, such as Flash memory devices. In one example, a multi-level cell memory array has programmable pages, a first page having a first programming time, and a second page having a second programming time that is different than the first programming time. In one embodiment, the first programming time is faster than the second programming time. Further, a controller coupled to the multi-level cell memory array may be configured to select the first page to store the data when a priority level of a write operation indicates a first priority level and select the second page to store the data when the priority level indicates a second priority level. | 06-30-2011 |
20110161557 | DISTRIBUTED MEDIA CACHE FOR DATA STORAGE SYSTEMS - This disclosure is related to distributed media cache for data storage systems, such as disc drives, flash devices, or hybrid devices. In one example, a data storage device comprises a data storage medium and a controller adapted to selectively divide a media cache into a plurality of physically separate media cache portions on the data storage medium based on a physical attribute of the data storage medium and to store data received from a host system into the media cache portions. | 06-30-2011 |
20110161558 | RECORD SORTING - A method, computer program product, and computing system for record sorting is described. The method may comprise splitting an incoming record into a separate key block and payload block. The method may further comprise storing the key block in a first memory. The method may also comprise assigning the payload block an address in a second memory at the beginning of a sort. Moreover, the method may store, with the key block in the first memory, the address of the payload block in the second memory. Additionally, the method may store the payload block at the address in the second memory. | 06-30-2011 |
20110161559 | PHYSICAL COMPRESSION OF DATA WITH FLAT OR SYSTEMATIC PATTERN - Systems and methods are disclosed to improve the performance of a memory system by freeing up physical memory areas that correspond to logical block address ranges that have repeated data patterns. A controller detects data patterns in incoming data. When a data pattern is detected, the data is not written to non-volatile storage area. Rather, the logical block address range of the data is marked in a data structure as having pattern data. The pattern may also be recorded in the data structure as a pattern descriptor. Because the data having the data pattern is not written to the non-volatile storage area, the freed up corresponding physical memory area may be utilized by the memory system for other purposes, thereby improving the overall performance and endurance of the memory system. | 06-30-2011 |
20110161560 | ERASE COMMAND CACHING TO IMPROVE ERASE PERFORMANCE ON FLASH MEMORY - Systems and methods are disclosed to reduce the number of partial logical groups that are erased by writing erase patterns to memory in a non-volatile memory system. When a non-aligned erase command is received, the logical addresses of data associated with the erase command may be marked as erased. If the logical group corresponds to the size of a physical metablock, the controller may also issue a physical erase command for complete logical groups within the erase command. For those parts of the erase command that encompass only partial logical groups, the ranges of the logical block addresses marked for erasure are stored. As subsequent erase commands are received the address ranges of the erase commands are added to the previously stored address ranges. When a set of erase commands spans an entire logical group, the logical group is marked for physical erasure in its entirety. | 06-30-2011 |
20110161561 | VIRTUALIZATION OF CHIP ENABLES - Virtual chip enable techniques perform memory access operations on virtual chip enables rather than physical chip enables. Each virtual chip enable is a construct that includes attributes that correspond to a unique physical or logical memory device. | 06-30-2011 |
20110161562 | REGION-BASED MANAGEMENT METHOD OF NON-VOLATILE MEMORY - A region-based management method of a non-volatile memory is provided. In the region-based management method, the storage space of all chips in the non-volatile memory is divided into physical regions, physical block sets, and physical page sets, and a logical space is divided into virtual regions, virtual blocks, and virtual pages. In the non-volatile memory, each physical block set is the smallest unit of space allocation and garbage collection, and each physical page set is the smallest unit of data access. The region-based management method includes a three-level address translation architecture for converting logical block addresses into physical block addresses. | 06-30-2011 |
20110161563 | BLOCK MANAGEMENT METHOD OF A NON-VOLATILE MEMORY - A block management method applicable to a non-volatile memory storage system is provided. The non-volatile memory storage system includes a plurality of chips. Each chip includes a plurality of physical blocks. The physical blocks form a plurality of physical block sets. Each logical block in a logical space corresponds to at most two physical block sets. In the block management method, when a logical block corresponds to two physical block sets filled with data and more data is to be written, a free physical block set is allocated for storing the data. Then, one of the two physical block sets corresponding to the logical block is selected according to a predetermined criterion. The valid data in the selected physical block set is copied into the free physical block set. Next, the selected physical block set is erased and collected to the pool of free physical block sets. | 06-30-2011 |
20110161564 | BLOCK MANAGEMENT AND DATA WRITING METHOD, AND FLASH MEMORY STORAGE SYSTEM AND CONTROLLER USING THE SAME - A block management method for managing a plurality of physical blocks is provided. The method includes grouping the physical blocks into a plurality of physical units, grouping a portion of the physical units into a data area and a spare area, configuring a plurality of logical units, and grouping the logical units into a plurality of logical unit groups and configuring another portion of the physical units as a plurality of global random physical units corresponding to the logical unit groups, wherein each of the global random physical units corresponds to one of the logical unit groups. The method further includes getting the physical units from the spare area as global random substitute physical units of the global random physical units. Accordingly, the method can store data in the global random physical units or the global random substitute physical units, thereby reducing the time for executing a host write command. | 06-30-2011 |
20110161565 | FLASH MEMORY STORAGE SYSTEM AND CONTROLLER AND DATA WRITING METHOD THEREOF - A flash memory storage system having a flash memory controller and a flash memory chip is provided. The flash memory controller configures a second physical unit of the flash memory chip as a midway cache physical unit corresponding to a first physical unit and temporarily stores first data corresponding to a first host write command and second data corresponding to a second host write command in the midway cache physical unit, wherein the first and second data corresponding to slow physical addresses of the first physical unit. Then, the flash memory controller synchronously copies the first and second data from the midway cache physical unit into the first physical unit, thereby shortening time for writing data into the flash memory chip. | 06-30-2011 |
20110161566 | WRITE TIMEOUT CONTROL METHODS FOR FLASH MEMORY AND MEMORY DEVICES USING THE SAME - A write timeout control method for a flash memory having a plurality of spare blocks and data blocks including a plurality of mother blocks is disclosed. The method includes the steps of: receiving a write command and a starting logical block address; determining an update mode according to a target mother block linked to the starting logical block address; determining whether a pre-clean operation is performed on a first mother block; if so, performing a post-clean operation on the first mother block during a first time period; re-configuring the first mother block as a spare block; performing a programming process to write data on the target mother block; determining whether the number of mother blocks exceeds a first threshold; and if so, performing the pre-clean operation on a second mother block. The first and second mother blocks are configured as blocks to be cleaned. | 06-30-2011 |
20110161567 | MEMORY DEVICE FOR REDUCING PROGRAMMING TIME - A non-volatile memory device includes: first and second planes each comprising a plurality of non-volatile memory cells; first and second buffer corresponding to the first and second planes, respectively; an input/output control unit configured to selectively control input/output paths of data stored in the first and second page buffers; a flash interface connected to the input/output control unit; and a host connected to the flash interface. | 06-30-2011 |
20110161568 | MULTILEVEL MEMORY BUS SYSTEM FOR SOLID-STATE MASS STORAGE - The present invention relates to a multilevel memory bus system for transferring information between at least one DMA controller and at least one solid-state semiconductor memory device, such as NAND flash memory devices or the like. This multilevel memory bus system includes at least one DMA controller coupled to an intermediate bus; a flash memory bus; and a flash buffer circuit between the intermediate bus and the flash memory bus. This multilevel memory bus system may be disposed to support: an n-bit wide bus width, such as nibble-wide or byte-wide bus widths; a selectable data sampling rate, such as a single or double sampling rate, on the intermediate bus; a configurable bus data rate, such as a single, double, quad, or octal data sampling rate; CRC protection; an exclusive busy mechanism; dedicated busy lines; or any combination of these. | 06-30-2011 |
20110161569 | MEMORY MODULE AND METHOD FOR EXCHANGING DATA IN MEMORY MODULE - The present application provides a memory module. The memory module includes one or more volatile memory devices, one or more non-volatile memory devices, and a data exchange controller. The data exchange controller controls data exchange between the volatile memory devices and the non-volatile memory devices. | 06-30-2011 |
20110161570 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICES, DATA UPDATING METHODS THEREOF, AND NONVOLATILE SEMICONDUCTOR MEMORY SYSTEMS - Integrated circuit memory devices utilize techniques to improve the timing of data update operations within a non-volatile memory, by more efficiently combining memory cell programming operations with threshold voltage adjust operations on erased memory cells. These adjust operations operate to narrow a threshold voltage distribution between memory cells that remain in an erased state after the programming operation has been performed. An integrated circuit memory device may include at least a first block of non-volatile memory cells and a volatile memory device, which has a data storage capacity equivalent to at least a capacity of the at least a first block of non-volatile memory cells. A memory controller is also provided, which is electrically coupled to the at least a first block of non-volatile memory cells and the volatile memory device. The memory controller is configured to, among other things, control data update operations within a block of data stored within the first block of non-volatile memory cells. | 06-30-2011 |
20110161571 | FLASH MEMORY DEVICE AND METHOD OF PROGRAMMING FLASH MEMORY DEVICE - A flash memory device performs a program operation using an incremental step pulse programming (ISPP) scheme comprising a plurality of program loops. In each of the program loops, a program pulse operation is performed to increase the threshold voltages of selected memory cells, and a program verify operation is performed to verify a program status of the selected memory cells. The program verify operation can be selectively skipped in some program loops based on a voltage increment of one or more of the program pulse operations, an amount by which threshold voltages of the selected memory cells are to be increased in the ISPP scheme, or a total number of program loops of the ISPP scheme. | 06-30-2011 |
20110161572 | Executing Applications From a Semiconductor Nonvolatile Memory - A processor-based device (e.g., a wireless device) may include a processor and a semiconductor nonvolatile memory to directly execute an application (e.g., an execute-in-place application) using an associated database. Within a flash memory, in one embodiment, an executable program may be separately stored in a non-fragmented manner from a resident database that includes program management information for use in an execution that does not involve a random access memory, saving time and resources. | 06-30-2011 |
20110161573 | DEVICE IDENTIFIERS FOR NONVOLATILE MEMORY MODULES - A memory card has a data scrambler that performs a data scrambling operation on data stored in the memory card according to a device ID associated with the memory card. The device ID is either set at the factory and permanently stored in the card, or configurable by a user or a host system. | 06-30-2011 |
20110167197 | Nonvolatile Storage with Disparate Memory Types - Disparate nonvolatile memory types are included in a system. Writes are performed in a first type of nonvolatile memory when the size of the write is below a threshold, and are performed in a second type of nonvolatile memory when the size of the write is above the threshold. The threshold may be a number of sectors. The disparate memory types may include FLASH memory and phase change memory (PCM). | 07-07-2011 |
20110167198 | NON-VOLATILE STORAGE ALTERATION TRACKING - A method for tracking alteration of a non-volatile storage includes receiving a request to modify a tracked region of the non-volatile storage. In response to the request, it is determined whether or not a modification of data stored in a non-erasable one-time programmable (NEOTP) alteration log region has occurred. In response to determining that the modification of the data stored in the NEOTP alteration log region has occurred, the tracked region of non-volatile storage is modified in response to the request. In response to determining that the modification of the data stored in the NEOTP alteration log region has not occurred, the request to modify the tracked region of the non-volatile memory is denied. | 07-07-2011 |
20110167199 | TECHNIQUES FOR PROLONGING A LIFETIME OF MEMORY BY CONTROLLING OPERATIONS THAT AFFECT THE LIFETIME OF THE MEMORY - Techniques are provided for prolonging a lifetime of memory by controlling operations that affect the lifetime of the memory. At least one aspect associated with the memory lifetime is identified and at least one of the operations is delayed, based on the at least one aspect. The operations include a write operation, an erase operation, a program operation, and/or any other operation that is capable of reducing the memory lifetime. | 07-07-2011 |
20110167200 | FLASH-AWARE STORAGE OPTIMIZED FOR MOBILE AND EMBEDDED DBMS ON NAND FLASH MEMORY - Reliable storage for database management systems (DBMS) running on memory devices such as NAND type flash memory utilizes minimum I/O overhead and provides maximum data durability. A virtual page map is utilized between the flash memory and a page access component to record changes to the DBMS pages and prevent overwriting or data loss. There is no need for journaling and logging, and performance is increased by reducing the write and erase counts on the flash memory. The logical page numbers of the DBMS are mapped to physical page numbers in the page map, such that the virtual page map allocates an available page from the physical pages when changes to a page occur, and the updated information is stored in the allocated page. The allocated page number is mapped to the logical page number of the original page, thus maintaining a modified page representation while preventing physical in-place updates. | 07-07-2011 |
20110167201 | EXPANDABLE CAPACITY SOLID STATE DRIVE - An expandable solid state drive is provided, comprising a main printed circuitboard, wherein the main printed circuitboard comprises a controller, an interface to a host, and connectors suitable to removably receive connectors mounted on a daughter card, the daughter card comprising at least one non-volatile flash memory chip, wherein when the daughter card is received by the main printed circuitboard, the form factor of the expandable solid state device is maintained. | 07-07-2011 |
20110167202 | ACCESS CONTROL APPARATUS - An access control apparatus includes a plurality of accesses. A plurality of accessors are respectively allocated to a plurality of operation modes in order to access a recording medium having a plurality of partitions and identification information which identifies a location of the plurality of partitions. An acceptor accepts a selection operation which selects any one of the plurality of operation modes. A first designator designates, based on the identification information provided in the recording medium, a part of partitions corresponding to the operation mode selected by the selection operation out of the plurality of partitions. A permitter permits an accessor corresponding to the operation mode selected by the selection operation out of the plurality of accessors to access the partition designated by the first designator. | 07-07-2011 |
20110167203 | METHOD AND APPARATUS FOR CACHE CONTROL IN A DATA STORAGE DEVICE - According to one embodiment, a data storage device is provided, which has a cache controller that performs cache control, by using a buffer memory divided into segments, which are managed. The cache controller performs sequential hit judge on each segment, in accordance with the requested access range designated by a read or write command coming from a host system. The cache controller updates the hit upper-limit LBA set for each segment if the result of the hit judge is a mishit. | 07-07-2011 |
20110167204 | MEMORY BLOCK IDENTIFIED BY GROUP OF LOGICAL BLOCK ADDRESSES, STORAGE DEVICE WITH MOVABLE SECTORS, AND METHODS - In an embodiment, a non-volatile memory has erasable blocks of memory cells. The one or more of the erasable blocks include a particular block to be identified by a particular group of logical block addresses corresponding to a predetermined group of sectors. | 07-07-2011 |
20110167205 | SEAMLESS APPLICATION ACCESS TO HYBRID MAIN MEMORY - A command from an application is received to access a data structure associated with one or more virtual addresses mapped to main memory. A first subset of the virtual addresses for the data structure having constituent addresses that are mapped to the symmetric memory components and a second subset of the virtual addresses for the data structure having constituent addresses that are mapped to the asymmetric memory components are identified. Data associated with the virtual address from the first physical addresses and data associated with the virtual addresses from the second physical addresses are accessed. The data associated with the symmetric and asymmetric memory components is accessed by the application without providing the application with an indication of whether the data is accessed within the symmetric memory component or the asymmetric memory component. | 07-07-2011 |
20110167206 | CONFIGURATION OF A MULTILEVEL FLASH MEMORY DEVICE - A multi-level flash memory device allows for a faster and more effective configuration of the operating parameters of the memory device for performing the different functioning algorithms of the memory. The identification of an optimal configuration of the operating parameters of the memory device during testing is simplified by allowing for a one-time processing of configuration bits into algorithm-friendly data that are stored in an embedded ancillary random access memory at every power-on of the memory device. This is done by executing a specific power-on algorithm code stored in the ancillary read only memory of the embedded microprocessor. | 07-07-2011 |
20110167207 | MEMORY SYSTEM AND METHOD HAVING VOLATILE AND NON-VOLATILE MEMORY DEVICES AT SAME HIERARCHICAL LEVEL - A processor-based system includes a processor coupled to core logic through a processor bus. This includes a dynamic random access memory (“DRAM”) memory buffer controller. The DRAM memory buffer controller is coupled through a memory bus to a plurality of a dynamic random access memory (“DRAM”) modules and a flash memory module, which are at the same hierarchical level from the processor. Each of the DRAM modules includes a memory buffer to the memory bus and to a plurality of dynamic random access memory devices. The flash memory module includes a flash memory buffer coupled to the memory bus and to at least one flash memory device. The flash memory buffer includes a DRAM-to-flash memory converter operable to convert the DRAM memory requests to flash memory requests, which are then applied to the flash memory device. | 07-07-2011 |
20110167208 | NONVOLATILE MEMORY DEVICE, ACCESS DEVICE, NONVOLATILE MEMORY SYSTEM, AND MEMORY CONTROLLER - The nonvolatile memory device prevents data writing from temporarily slowing down significantly in the middle of writing data to a block when an access device writes all the data in the block in units of a smaller size than the block. The nonvolatile memory device ( | 07-07-2011 |
20110167209 | MEMORY CONTROLLER, NONVOLATILE STORAGE DEVICE, ACCESSING DEVICE, AND NONVOLATILE STORAGE SYSTEM - A memory controller, a nonvolatile storage device, an access device, and a nonvolatile storage system enable the storage architecture to be changed flexibly for intended use that can be changed variously. A nonvolatile storage system ( | 07-07-2011 |
20110173373 | NON-VOLATILE MEMORY DEVICE AND METHOD THEREFOR - A method of storing information at a non-volatile memory includes storing a first status bit at a sector header of the memory prior to erasing a sector at the memory. A second status bit is stored after erasing of the sector. Because the erasure of the sector is interleaved with the storage of the status bits, a brownout or other corrupting event during erasure of the record will likely result in a failure to store the second status bit. Therefore, the first and second status bits can be compared to determine if the data was properly erased at the non-volatile memory. Further, multiple status bits can be employed to indicate the status of other memory sectors, so that a difference in the status bits for a particular sector can indicate a brownout or other corrupting event. | 07-14-2011 |
20110173374 | SOLID-STATE MEMORY MANAGEMENT - An exemplary method includes performing flash memory operations; receiving a signal from a voltage monitor as being associated with the performed flash memory operations; and, based at least in part on the received signal, setting a limit for performing subsequent flash memory operations. In such a method, the limit can act to avoid resetting flash memory responsive to current demand associated with subsequent flash memory operations. Various other apparatuses, systems, methods, etc., are also disclosed. | 07-14-2011 |
20110173375 | METHOD FOR ENHANCING FILE SYSTEM PERFORMANCE, AND ASSOCIATED MEMORY DEVICE AND CONTROLLER THEREOF - A method for enhancing file system performance includes: in a situation where operations of visiting a file system of a memory device according to a plurality of file names are performed, regarding each of the file names, extracting a characteristic value and full file name location information from file information that is first read, and temporarily storing the characteristic value and the full file name location information; and when visiting the file system according to a target file name, checking whether any of temporarily stored characteristic values matches the target file name, and determining accordingly whether to perform a file system operation corresponding to the target file name. An associated memory device and the controller thereof are further provided. | 07-14-2011 |
20110173376 | CACHE APPARATUS FOR INCREASING DATA ACCESSING SPEED OF STORAGE DEVICE - A cache apparatus for increasing data accessing speed of a storage device includes: a non-volatile memory, for storing data; a memory controller, coupled to the non-volatile memory, for controlling data accessing operations of the non-volatile memory; a first transmission interface, coupled to the memory controller, for electrically connecting the memory controller to the storage device; and a second transmission interface, coupled to the memory controller, for electrically connecting the memory controller to a user-end personal computer. | 07-14-2011 |
20110173377 | Secure portable data storage device - A portable memory device for use with a host device includes an array of non-volatile memory and a memory controller for performing memory access operations. A processor issues an authorization challenge to a host device prior to enabling external access to the memory. Upon receipt of a valid authorization from the host device, access is enabled. In one embodiment, the processor preconditions at least one signal in the interface between the host device and the memory controller. The preconditioning results in a desynchronization of synchronized signals applied at the memory device interface, thereby interfering with proper operation of the memory device. Attempts to access the memory device prior to authorization lead to intentional corruption of data stored in the memory. In alternative embodiment, a secure, machine-readable digital storage device is implemented as a boot device for a host machine. When booted off of the secure device operating system, the host machine's access to secure files on the secure digital storage device is restricted. When the secure digital storage device is accessed by a host device not booted off of the secure device's operating system, the secured files on the secure digital storage device are inaccessible. | 07-14-2011 |
20110173378 | COMPUTER SYSTEM WITH BACKUP FUNCTION AND METHOD THEREFOR - A solid-state mass storage device and method of anticipating a failure of the mass storage device resulting from a memory device of the mass storage device reaching a write endurance limit. A procedure is then initiated to back up data to a second mass storage device prior to failure. The method includes assigning at least a first memory block of the memory device as a wear indicator, using other memory blocks of the memory device as data blocks for data storage, performing program/erase (P/E) cycles and wear leveling on the data blocks, subjecting the wear indicator to more P/E cycles than the data blocks, performing integrity checks and monitoring the bit error rate of the wear indicator, and taking corrective action if the bit error rate increases, including the initiation of the backup procedure and generating a request to replace the device. | 07-14-2011 |
20110173379 | SEMICONDUCTOR DEVICE WITH DOUBLE PROGRAM PROHIBITION CONTROL - The present invention provides a semiconductor device and a method for controlling the semiconductor device, the semiconductor device including memory regions; program prohibition information units storing program prohibition information to be used for determining whether to prohibit or allow programming in the memory regions corresponding to the program prohibition information units; a first prohibition information control circuit that prohibits a change of the program prohibition information from a program prohibiting state with respect to a memory region based on first prohibition information; and a second prohibition information control circuit that prohibits a change of the program prohibition information from a program allowing state to a program prohibiting state with respect to the corresponding memory region based on second prohibition information with respect to the corresponding memory region. | 07-14-2011 |
20110173380 | MEMORY SYSTEM AND METHOD OF CONTROLLING MEMORY SYSTEM - A first log indicating that a system is running is recorded in a second storage unit before a first difference log is recorded in the second storage unit after system startup, and a second log indicating that the system halts is recorded in the second storage unit following the difference log, at the time of normal system halt, and it is judged whether normal system halt has been performed or an incorrect power-off sequence has been performed last time, based on a recorded state of the first and second logs in the second storage unit, at the time of system startup, thereby detecting an incorrect power-off easily and reliably. | 07-14-2011 |
20110173381 | SYSTEM AND APPARATUS FOR FLASH MEMORY DATA MANAGEMENT - The system and apparatus for managing flash memory data includes a host transmitting data, wherein when the data transmitted from the host have a first time transmission trait and the address for the data indicates a temporary address, temporary data are retrieved from the temporary address to an external buffer. A writing command is then executed and the temporary data having a destination address are written to a flash memory buffer. When the flash memory buffer is not full, the buffer data are written into a temporary block of the flash memory. The writing of buffer data into the temporary block includes using an address changing command, or executing a writing command to rewrite the external buffer data to the flash memory buffer so that the data are written into the temporary block. | 07-14-2011 |
20110173382 | NAND INTERFACE - A NAND interface having a reduced pin count configuration, in which all command and address functions and operations of the NAND are provided serially on a single serial command and address pin. | 07-14-2011 |
20110173383 | METHODS OF OPERATING A MEMORY SYSTEM - Methods of operating a memory system are useful in facilitating access to data. Where repetitive data patterns are detected among portions of received data, and an indication is provided, a portion of the data may be stored and/or subsequently retrieved without having to store and/or retrieve, respectively, all portions of the data. | 07-14-2011 |
20110179215 | PROGRAMMABLE READ PREAMBLE - The subject systems and/or methods relate to a high speed memory device that enables a preamble pattern to be updated after manufacture. A high speed memory device can include a FLASH module and a RAM module. The FLASH module can include an initial preamble pattern, wherein the initial preamble pattern is loaded during a power-up of the high speed memory. The RAM module can include a default preamble pattern, wherein the default preamble pattern is loaded after the power-up of the high speed memory. The initial preamble pattern or the default preamble pattern can be defined by a manufacture of the high speed memory or an OEM of the high speed memory. Additionally, the initial preamble pattern or the default preamble pattern can be updated with a customized preamble pattern based upon a target environment. | 07-21-2011 |
20110179216 | Data Storage Device and Data Access Method - The invention provides a data access method for a flash memory. First, a write command, a write address, and target data are received from a host. A target block corresponding to the write address is then determined. Whether a storage space with the write address in the target block stores data is then determined. When the storage space does not store data, the target data is written to the storage space of the target block. When the storage space stores data, whether a file allocation table (FAT) block mapped to the target block exists in the flash memory is then determined. When the FAT block exists, the target data is written to the FAT block. When the FAT block does not exist, whether a child block mapped to the target block exists in the flash memory is determined. When the child block exists, the target data is written to the child block. | 07-21-2011 |
20110179217 | Flash Storage Device and Data Access Method of Flash Memory - The invention provides a data access method of a flash memory. First, a write command, a write address, and target data are received from a host. A target block corresponding to the write address is then determined from the flash memory. Whether a storage space corresponding to the write address in the target block has stored data therein is then determined When the storage space of the target block does not have stored data therein, the target data is written into the storage space of the target block. When the storage space of the target block does have stored data therein, whether a child block mapped to the target block exists in the flash memory is determined. When the child block exists in the flash memory, the target data is written into the child block. | 07-21-2011 |
20110179218 | METHOD FOR READING A MULTILEVEL CELL IN A NON-VOLATILE MEMORY DEVICE - A non-volatile memory device has a memory array comprising a plurality of memory cells. The array can operate in either a multilevel cell or single level cell mode and each cell has a lower page and an upper page of data. The memory device has a data latch for storing flag data and a cache latch coupled to the data latch. A read method comprises initiating a lower page read of a memory cell and reading, from the data latch, flag data that indicates whether a lower page read operation is necessary. | 07-21-2011 |
20110179219 | HYBRID STORAGE DEVICE - A hybrid storage device comprises both solid-state disk (SDD) and at least one hard disk drive (HDD). The hybrid storage device has at least two operational modes: concatenation and safe. According to one aspect, the total capacity of hybrid storage device is the sum of SSD and at least one HDD in a concatenation or big mode, while the total capacity is the capacity of the HDD in a safe mode. In one embodiment, HDD is configured for storing a copy of the SSD's contents in a reserved area. In another, SSD comprises more than one identical flash memory devices controlled by a RAID controller. | 07-21-2011 |
20110185105 | MEMORY SYSTEM - A memory system in which speed of processing for searching through management tables is increased by providing a forward lookup table for searching for, respectively in track and cluster units, from a logical address, a storage device position where data corresponds to the logical address, and a reverse lookup table for searching for, from a position of the storage device, a logical address stored in the position. These forward and reverse lookup tables are linked. | 07-28-2011 |
20110185106 | MEMORY SYSTEM - A memory system includes a management-information restoring unit. The management-information restoring unit determines whether a short break has occurred referring to a pre-log or a post-log in a NAND memory. The management-information restoring unit determines that a short break has occurred when the pre-log or the post-log is present in the NAND memory. In that case, the management-information restoring unit determines timing of occurrence of the short break, and, after selecting a pre-log or a post-log used for restoration, performs restoration of the management information reflecting these logs on a snapshot. Thereafter, the management-information restoring unit applies recovery processing to all write-once blocks in the NAND memory, takes the snapshot again, and opens the snapshot and the logs in the past. | 07-28-2011 |
20110185107 | MEMORY SYSTEM - A memory system includes a volatile first storing unit, a nonvolatile second storing unit, and a controller. The controller performs data transfer, stores management information including a storage position of the data stored in the second storing unit into the first storing unit, and performs data management while updating the management information. The second storing unit has a management information storage area for storing management information storage information including management information in a latest state and a storage position of the management information. The storage position information is read by the controller during a startup operation of the memory system and includes a second pointer indicating a storage position of management information in a latest state in the management information storage area and a first pointer indicating a storage position of the second pointer. The first pointer is stored in a fixed area in the second storing unit and the second pointer is stored in an area excluding the fixed area in the second storing unit. | 07-28-2011 |
20110185108 | MEMORY SYSTEM - A memory system includes a volatile first storing unit, a nonvolatile second storing unit in which a plurality of memory cells that can store multi-value data are arranged, the memory cells having a plurality of pages, and a controller that performs data transfer between a host apparatus and the second storing unit via the first storing unit. The controller includes a save processing unit that backs up, when, before data is written in the second storing unit in a write-once manner, data is written in a lower order page of a memory cell same as that of a page in which the data is written, the data of the lower order page and a broken-information-restoration processing unit that restores, when the data in the lower order page is broken, the broken data using the backed-up data. | 07-28-2011 |
20110185109 | High Performance Data Rate System for Flash Devices - A Flash memory system includes N flash devices, where N is an integer, each flash device having a flash device interface consisting of a control signal line, a R/B signal line, and a I/O signal line, and wherein each flash device has an operating speed of s. A logic block is connected to each flash device interface, and is further connected to a controller which whose interfaces also has a control signal line, a R/B signal line, and a I/O signal line, so that controller operates at an operating speed of N times s, and wherein the logic block controls each flash device simultaneously. | 07-28-2011 |
20110185110 | METHOD AND DEVICE FOR PROTECTING INFORMATION CONTAINED IN AN INTEGRATED CIRCUIT - An integrated circuit and a method of protection of an integrated circuit provides for a test controller state machine (TCSM) to be coupled to a control structure and/or an input and/or an output of at least one data storage device of the integrated circuit. The TCSM monitors the state of the data storage device and, upon a test request to the integrated circuit, causes the information in the data storage device to be changed or blocked until the data storage device is deemed safe for access. Such an integrated circuit and method protects information contained in data storage devices of the integrated circuit from being revealed during testing of circuitry of the integrated circuit. | 07-28-2011 |
20110185111 | Systems and Methods for Extended Life Multi-Bit Memory Cells - Various embodiments of the present invention provide for extended life operation of multi-bit memory cells. As an example, some embodiments of the present invention provide electronic systems that include a plurality of multi-bit memory cells, an encoding circuit and a decoding circuit. Each of the plurality of multi-bit memory cells is operable to hold at least two bits. The encoding circuit is operable to receive a data input including at least two data bits, and to encode the two data bits as an encoded output to the plurality of multi-bit memory cells. The encoded output may be selected to be either a single two bit output representing the two bits, or a series of two two bit outputs representing the two bits. The decoding circuit is operable to reverse the encoding applied by the encoding circuit. | 07-28-2011 |
20110185112 | Verifying Whether Metadata Identifies a Most Current Version of Stored Data in a Memory Space - Method and apparatus for verifying whether metadata identifies a most current version of data stored in a memory space. In accordance with various embodiments, a physical location within a first portion of a solid-state memory space is identified by metadata as storing a current version of user data having a selected logical address. A reverse search is performed upon a second portion of the memory space to determine whether the physical address identified by the metadata stores a stale version of the user data, or whether the physical address stores the current version. | 07-28-2011 |
20110185113 | Maintaining Data Integrity in a Data Storage Device - Method and apparatus for maintaining data integrity in a data storage device. In accordance with some embodiments, a memory space has a plurality of garbage collection units (GCUs) each arranged to store user data identified by logical addresses. Each GCU has a metadata region that stores metadata that correlates the logical addresses LBAs with physical addresses and a header region that stores descriptor data that identifies LBAs stored in the associated GCU. A control circuit identifies an error in the metadata from the descriptor data of a selected GCU and rebuilds the metadata to indicate a storage location of a most current version of data associated with a selected logical address. | 07-28-2011 |
20110185114 | SYSTEM AND METHOD FOR READ-WHILE-WRITE WITH NAND MEMORY DEVICE - System, method, and program to perform simultaneous read and write operations in a NAND-type memory device, including: assigning a first partition in a NAND-type memory device, wherein the first partition is configured to perform read operations on high priority read content; assigning a second partition in the NAND-type memory device, wherein the second partition is configured to perform read operations and write operations, wherein the read operations are performed on non-high priority read content; and controlling the first partition and second partition to operate in a simultaneous manner. | 07-28-2011 |
20110185115 | METHOD AND DEVICE FOR PERFORMING DIAGNOSTICS ON A MOTOR VEHICLE MANAGEMENT SYSTEM - A device for recording data emitted from a motor vehicle management system, including a volatile memory, a non-volatile memory, and a data recording module configured to receive a signal concerning activation status emitted by the management system and to record the data in a first zone of the volatile memory on a rising edge of the activation status signal and in a second zone of the volatile memory on a falling edge of the activation status signal, and including a record management module configured to receive the activation status signal and to activate a command to record on a falling edge with the activation status signal, the recording module being further configured to receive the record command and to record the content of the two zones of the volatile memory into a zone of the non-volatile memory when the record command is activated. | 07-28-2011 |
20110185116 | Memory device with vertically embedded non-flash non-volatile memory for emulation of NAND flash memory - A system and a method for emulating a NAND memory system are disclosed. In the method, a command associated with a NAND memory is received. After receipt of the command, a vertically configured non-volatile memory array is accessed based on the command. In the system, a vertically configured non-volatile memory array is connected with an input/output controller and a memory controller. The memory controller is also connected with the input/output controller. The memory controller is operative to interface with a command associated with a NAND memory and based on the command, to access the vertically configured non-volatile memory array for a data operation, such as a read operation or write operation. An erase operation on the vertically configured non-volatile memory array is not required prior to the write operation. The vertically configured non-volatile memory array can be partitioned into planes, blocks, and sub-planes, for example. | 07-28-2011 |
20110191521 | FLASH MEMORY DEVICE - A controller in a flash memory device manages erase count of each physical block and manages the erase frequency of each logical block. The controller allocates a logical block whose erase frequency is high to one or more physical blocks whose erase count is low. | 08-04-2011 |
20110191522 | Managing Metadata and Page Replacement in a Persistent Cache in Flash Memory - A persistent cache is implemented in a flash memory that includes a journal section that stores metadata and a low frequency section and a high frequency section that store data entries. Writing new metadata to the persistent cache includes sequentially advancing to a next sector containing an invalid metadata entry, saving a working copy of the sector in RAM, writing metadata corresponding to one or more new data entries in the working copy, and overwriting the sector in the flash memory containing the invalid entry with the working copy. Writes to the low frequency and high frequency sections occur sequentially in the current locations of a low frequency section pointer and a high frequency section pointer, respectively. In a persistent cache, the reconstruction of a non-persistent cache utilizes the metadata entry that has the most recent timestamp. | 08-04-2011 |
20110191523 | Priority Ordered Multi-Medium Solid-State Storage System and Methods for Use - A hierarchical data-storage system has a volatile storage medium, a first non-volatile storage medium, and a controller including a ranking engine tracking data writes to each of the memory mediums. Each medium is associated with a pre-set capacity threshold, and the controller, upon the volatile medium reaching its pre-set threshold, identifies one or more blocks of data as least-frequently written to the volatile medium, copies the data in those blocks to the non-volatile medium, and marks those blocks as available for new data writes, and the controller, upon the non-volatile medium reaching its pre-set threshold, identifies one or more blocks of data as least-frequently written to the non-volatile medium, and marks those blocks as available for new data writes from the volatile medium. | 08-04-2011 |
20110191524 | FLASH MEMORY STORAGE DEVICE, CONTROLLER THEREOF, AND PROGRAM MANAGEMENT METHOD THEREOF - A flash memory storage device, a controller thereof, and a programming management method thereof are provide for the flash memory storage device including a flash memory chip, wherein at least a first thread and a second thread are to be implemented within the flash memory storage device. The method includes defining a predetermined programming unit and receiving a first write command sent by a host. The method also includes distributing a control right of the flash memory chip to the first thread if the first write command is determined to be executed by the first thread, and controlling the first thread to release the control right of the flash memory chip after the first thread finishes a programming operation of the predetermined programming unit. | 08-04-2011 |
20110191525 | FLASH MEMORY STORAGE DEVICE, CONTROLLER THEREOF, AND DATA PROGRAMMING METHOD THEREOF - A flash memory storage device, a controller thereof, and a data programming method are provided. The flash memory storage device has a flash memory comprising a plurality of physical blocks, each physical block includes a plurality of physical addresses, and the physical addresses comprises at least one fast physical address and at least one slow physical address. The method comprises at least grouping the physical blocks into a data area and a spare area; setting a predetermined block number; obtaining m physical blocks from the spare area, receiving a write command comprising a write data and a logical address, determining a logical address range of a buffer according to the logical address and the predetermined block number. When all logical addresses to be programmed with the write data are within the logical address range of the buffer, using a fast mode to program the data into the m physical blocks. | 08-04-2011 |
20110191526 | Flash Memory Timing Pre-Characterization - This disclosure provides a method of accurately determining expected transaction times associated with flash memory subdivisions, such as devices, blocks or pages. By performing a test transaction to program each bit of each such unit, the maximum expected programming time of each unit may be determined in advance and used for scheduling purposes. For example, in a straightforward implementation, a relatively accurate, empirically measured time limit may be identified and used to efficiently manage and schedule flash memory transactions without awaiting ultimate resolution of attempts to write to a non-responsive page. This disclosure also provides other uses of empirically-measured maximum flash memory transaction times, including via multiple memory modes and prioritized memory; for example, if a high performance mode is desired, low variation in flash memory transaction times may be tolerated, and units not satisfying these principles may be marked relatively quickly. A mechanism is also provided for recalibrating memory previously marked. By minimizing variability, flash memory can be applied to a broader range of designs and potentially to a broader set of main memory applications. | 08-04-2011 |
20110191527 | SEMICONDUCTOR STORAGE DEVICE AND CONTROL METHOD THEREOF - According to one embodiment, a semiconductor storage device comprises processors, a nonvolatile memory with channels, a list storage, and a command generator. The list storage is configured to store an erase address list includes erase addresses of each of the channels of the nonvolatile memory. The command generator is configured to continuously generate a series of erase commands concerning the erase addresses in the erase address list in response to a single erase request generated from any one of the processors. | 08-04-2011 |
20110191528 | SEMICONDUCTOR STORAGE DEVICE AND CONTROL METHOD THEREOF - According to one embodiment, a semiconductor storage device comprises a main memory, a request issue module, a delay module, and an access module. The main memory is configured to store candidate information for determining a compaction candidate for a nonvolatile memory. The request issue module is configured to issue an access request for the candidate information in the main memory. The delay module is configured to delay the access request issued from the request issue module. The access module is configured to access the candidate information in the main memory based on an access request delayed by the delay module. | 08-04-2011 |
20110191529 | SEMICONDUCTOR STORAGE DEVICE AND METHOD OF CONTROLLING SEMICONDUCTOR STORAGE DEVICE - According to one embodiment, a semiconductor storage device includes a queuing buffer, a read module, a separating module, a write command issuing module, and a write module. The write command issuing module is configured to add a write address indicated by write pointer information to the management data obtained by the separating module in order to issue a write command, and to automatically queue the write command into the queuing buffer. The write module is configured to supply the write command issued by the write command issuing module to the nonvolatile memory in order to write data into the nonvolatile memory. | 08-04-2011 |
20110191530 | Adaptive Deterministic Grouping of Blocks into Multi-Block Units - The present invention presents techniques for the linking of physical blocks of a non-volatile memory into composite logical structures or “metablocks”. After determining an initial linking of good physical blocks into metablocks, a record of the linking is maintained in the non-volatile memory where it can be readily accessed when needed. In one set of embodiments, the initially linking is deterministically formed according to an algorithm and can be optimized according to the pattern of any bad blocks in the memory. As additional bad blocks arise, the linking is updated using by replacing the bad blocks in a linking with good blocks, preferably in the same sub-array of the memory as the block that they are replacing. | 08-04-2011 |
20110191531 | MEMORY DEVICE AND CONTROL METHOD THEREOF - A control method of a memory device including a storage area formed of a nonvolatile semiconductor memory, includes updating a file stored in the storage area by using a file system which supports an incremental write method, recording, in the storage area, an allocation table representing a correlation between a logical address indicating a recording position of the file and a virtual address representing a virtual recording position of the file and management information of the allocation table, and recording position information representing a recording position of the management information in a position information area of the storage area. | 08-04-2011 |
20110197014 | MEMORY MANAGEMENT AND WRITING METHOD AND REWRITABLE NON-VOLATILE MEMORY CONTROLLER AND STORAGE SYSTEM USING THE SAME - A memory management and writing method for managing a plurality of physical units of a memory chip is provided. The present method includes grouping the physical units into a first physical unit group and a second physical unit group, recording and calculating a first erase count of the first physical unit group and a second erase count of the second physical unit group, and calculating an erase count difference between the first erase count and the second erase count. The present method also includes determining whether the erase count difference is larger than an erase count difference threshold when a write command is received. The method further includes executing a switched writing procedure to write data corresponding to the write command into the memory chip when the erase count difference is larger than the erase count difference threshold. Thereby, the lifespan of the memory chip is effectively prolonged. | 08-11-2011 |
20110197015 | Flash Memory Devices Having Multi-Bit Memory Cells Therein with Improved Read Reliability - Integrated circuit memory devices include an array of nonvolatile N-bit memory cells, where N is an integer greater than one. Control circuitry is also provided to reliably read data from the N-bit memory cells. This control circuitry, which is electrically coupled to the array, is configured to determine, among other things, a value of at least one bit of data stored in a selected N-bit memory cell in the array. This is done by decoding at least one hard data value and a plurality of soft data values (e.g., 6 data values) read from the selected N-bit memory cell using a corresponding plurality of unequal read voltages applied to the selected N-bit memory cell during a read operation. | 08-11-2011 |
20110197016 | Aggregation of Write Traffic to a Data Store - A method and a processing device are provided for sequentially aggregating data to a write log included in a volume of a random-access medium. When data of a received write request is determined to be suitable for sequentially aggregating to a write log, the data may be written to the write log and a remapping tree, for mapping originally intended destinations on the random-access medium to one or more corresponding entries in the write log, may be maintained and updated. At time periods, a checkpoint may be written to the write log. The checkpoint may include information describing entries of the write log. One or more of the checkpoints may be used to recover the write log, at least partially, after a dirty shutdown. Entries of the write log may be drained to respective originally intended destinations upon an occurrence of one of a number of conditions. | 08-11-2011 |
20110197017 | High Endurance Non-Volatile Memory Devices - High endurance non-volatile memory devices (NVMD) are described. A high endurance NVMD includes an I/O interface, a NVM controller, a CPU along with a volatile memory subsystem and at least one non-volatile memory (NVM) module. The volatile memory cache subsystem is configured as a data cache subsystem. The at least one NVM module is configured as a data storage when the NVMD is adapted to a host computer system. The I/O interface is configured to receive incoming data from the host to the data cache subsystem and to send request data from the data cache subsystem to the host. The at least one NVM module may comprise at least first and second types of NVM. The first type comprises SLC flash memory while the second type MLC flash. The first type of NVM is configured as a buffer between the data cache subsystem and the second type of NVM. | 08-11-2011 |
20110197018 | METHOD AND SYSTEM FOR PERPETUAL COMPUTING USING NON-VOLATILE RANDOM ACCESS MEMORY - Provided is a computing system and method that utilizes a non-volatile random access memory (NVRAM). A system including the NVRAM as a part of a memory or a whole memory may execute a program in the NVRAM, and, when the system is re-operated after being shut down, may restore a state and data of the program being executed in the NVRAM to an original state and thus, may provide a permanent computing environment. | 08-11-2011 |
20110202707 | NVMHCI ATTACHED HYBRID DATA STORAGE - A hybrid data storage device includes a solid-state memory device, a disc-type memory device and a hybrid data storage device controller in communication with the solid-state memory device and the disc-type memory device. The hybrid data storage device controller is configured to receive Non-Volatile Memory Host Controller Interface (NVMHCI) commands from a host and use logic to make decisions for the optimization and efficient performance of the solid-state memory device and the disc-type memory device. | 08-18-2011 |
20110202708 | Integrating A Flash Cache Into Large Storage Systems - An I/O enclosure module is provided with one or more I/O enclosures having a plurality of slots for receiving electronic devices. A host adapter is connected a first slot of the I/O enclosure module and is configured to connect a host to the I/O enclosure. A device adapter is connected to a second slot of the I/O enclosure module and is configured to connect a storage device to the I/O enclosure module. A flash cache is connected to a third slot of the I/O enclosure module and includes a flash-based memory configured to cache data associated with data requests handled through the I/O enclosure module. A primary processor complex manages data requests handled through the I/O enclosure module by communicating with the host adapter, device adapter, and flash cache to manage to the data requests. | 08-18-2011 |
20110202709 | OPTIMIZING STORAGE OF COMMON PATTERNS IN FLASH MEMORY - One embodiment of the present invention provides a method of operation within a flash memory system. During operation, the system receives write data and a corresponding logical address. The system then determines whether the write data matches a predetermined data pattern. If the write data does match the predetermined data pattern, instead of writing the data, the system records an indication that the predetermined data pattern corresponds to the logical address. | 08-18-2011 |
20110202710 | PROTECTION AGAINST DATA CORRUPTION FOR MULTI-LEVEL MEMORY CELL (MLC) FLASH MEMORY - Apparatus having corresponding methods and non-transitory computer-readable media comprise a flash controller configured to control a multi-level memory cell (MLC) flash memory, wherein the MLC flash memory includes a plurality of memory blocks, wherein each memory block includes a plurality of memory cells defining a plurality of pages, wherein each memory cell spans a group of the pages in one of the memory blocks, and wherein the flash controller comprises circuitry configured to receive data to be written to the MLC flash memory, select only one page, from each group of the pages, in one or to more of the memory blocks, and write the data only to the selected pages. | 08-18-2011 |
20110202711 | ADAPTIVE READ AND WRITE SYSTEMS AND METHODS FOR MEMORY CELLS - An apparatus including: a plurality of multi-level memory cells configured to store data, wherein one or more of the multi-level memory cells are designated as pilot memory cells, and wherein each pilot memory cell is configured to store known, pre-determined data; an estimation block configured to, based on the known, pre-determined data, determine (i) estimated mean values of level distributions of the multi-level memory cells and (ii) estimated standard deviation values of level distributions of the multi-level memory cells; and a computation block configured to compute at least optimal or near optimal detection threshold values of level distributions of the multi-level memory cells based, at least in part, on (i) the estimated mean values and (ii) the estimated standard deviation values, wherein the optimal or near optimal detection threshold values are to be used in order to facilitate reading of the data stored in the multi-level memory cells. | 08-18-2011 |
20110202712 | STORAGE DEVICE INCLUDING FLASH MEMORY AND CAPABLE OF PREDICTING STORAGE DEVICE PERFORMANCE - A storage device includes a semiconductor memory storing data. A controller instructs to write data to the semiconductor memory in accordance with a request the controller receives. A register holds performance class information showing one performance class required to allow the storage device to demonstrate best performance which the storage device supports, of performance classes specified in accordance with performance. | 08-18-2011 |
20110208895 | METHODS FOR MEMORY PROGRAMMING DURING PRODUCT ASSEMBLY - A method of writing data to an electronic device during assembly comprises attaching a resident memory element to one or more contact pads of a circuit board using a solder paste; reflowing the solder paste to affix the resident memory element to the contact pads; copying data from an external memory element to the resident memory element; and thereafter combining a device component with the circuit board to at least partially complete assembly of the electronic device. | 08-25-2011 |
20110208896 | DYNAMICALLY ALLOCATING NUMBER OF BITS PER CELL FOR MEMORY LOCATIONS OF A NON-VOLATILE MEMORY - Systems and methods are provided for dynamically allocating a number of bits per cell to memory locations of a non-volatile memory (“NVM”) device. In some embodiments, a host may determine whether to store data in the NVM device using SLC programming or MLC programming operations. The host may allocate an erased block as an SLC block or MLC block based on this determination regardless of whether the erased block was previously used as an SLC block, MLC block, or both. In some embodiments, to dynamically allocate a memory location as SLC or MLC, the host may provide an address vector to the NVM package, where the address vector may specify the memory location and the number of bits per cell to use for that memory location. | 08-25-2011 |
20110208897 | METHOD AND MEMORY SYSTEM USING A PRIORI PROBABILITY INFORMATION TO READ STORED DATA - A memory system comprises a non-volatile memory device that stores user data and state information regarding the user data. In a read operation of the non-volatile memory device, a memory controller calculates a priori probabilities for the user data based on the state information, calculates a posteriori probabilities based on the a priori probabilities, and performs a soft-decision operation to determine values of the user data based on the a posteriori probabilities. | 08-25-2011 |
20110208898 | STORAGE DEVICE, COMPUTING SYSTEM, AND DATA MANAGEMENT METHOD - A data storage device receives an invalidity command, and in response to the invalidity command, records information identifying a first region of a main storage unit. In a first interval, the data storage device copies valid data from the first region of the main storage unit to a second region of the main storage unit based on the recorded information. In a second interval after the first interval, the data storage device invalidates the first region. | 08-25-2011 |
20110208899 | MEMORY WRITING SYSTEM AND METHOD - Memory writing system and method determining an optimum data amount per one-time data transmission to one memory writer to enable optimization of communication efficiency and write speed, include: setting the amount of data to be transmitted per one-time transmission from a writer controller to different values for respective memory writers; transmitting data of each of the data amounts from the writer controller to a corresponding one of the memory writers; measuring, for each of the data amounts, a processing time required for the writer controller to transmit data to the corresponding memory writer and a data write time of the corresponding memory writer; obtaining, for each of the data amounts, a correlation between the processing time and the data write time based on respective measured values; setting an optimum data amount based on the correlation to satisfy a desired data write time condition; and, after the optimum data amount is set, sequentially transmitting data of the optimum data amount from the writer controller to the memory writers. | 08-25-2011 |
20110208900 | METHODS AND SYSTEMS UTILIZING NONVOLATILE MEMORY IN A COMPUTER SYSTEM MAIN MEMORY - Methods and systems capable of capitalizing on fast access capabilities (low initial access latencies) of nonvolatile memory technologies for use in a host system, such as computers and other processing apparatuses. The host system has a central processing unit, processor cache, and a system main memory. The system main memory includes first and second memory slots, a volatile memory subsystem having at least one DRAM-based memory module received in the first memory slot and addressed by the central processing unit, and a nonvolatile memory subsystem having at least a first nonvolatile-based memory module in the second memory slot and addressed by the central processing unit. At least one memory controller is integrated onto the central processing unit for controlling the processor cache, the volatile memory subsystem, and the nonvolatile memory subsystem. | 08-25-2011 |
20110208901 | Memory Systems and Methods of Operating the Same - A memory system includes a nonvolatile memory device, a memory controller for controlling the nonvolatile memory device and a virtual data interface layer that manages reading and/or writing of patterned data from/to the nonvolatile memory device. In a read operation, the virtual data interface layer generates patterned data that is requested to be read. Accordingly, a read speed of the memory system may be improved. | 08-25-2011 |
20110208902 | FILTERED REGISTER ARCHITECTURE TO GENERATE ACTUATOR SIGNALS - In various embodiments, apparatus and systems, as well as methods, may include an enhanced register to provide actuator signals to a memory array, the enhanced register including a first memory device including an first enable input, a first data input coupled to a register data input, and first memory device output, the first memory device output to couple to the memory array, and the enhances register to include a second memory device including a second enable input, a second data input coupled to the register data input, and a second memory device output, wherein the second memory device output provides a first output signal indicating when one or more of the actuator signals from the first memory device output are to be coupled to the register data input. | 08-25-2011 |
20110208903 | FLASH MEMORY DEVICE CAPABLE OF IMPROVING READ PERFORMANCE - A flash memory device, related system ad method are disclosed. The memory device includes a memory cell array a page buffer receiving read data, wherein the page buffer includes a main register transferring read data to a cache register during an read operation, and a control logic block controlling operation of the page buffer during the read operation, such that initialization of the main register continuously extends beyond a time period during which read data is transferred from the main register to the cache register. | 08-25-2011 |
20110208904 | SEMICONDUCTOR DEVICE - The semiconductor device includes a nonvolatile memory, having a memory array containing 1-bit twin cells, each composed of electrically rewritable first and second storage devices, the first and second storage devices holding binary data according to difference of their threshold voltages, and having different retention characteristics depending on difference of the binary data thereof; a read circuit for differentially amplifying complementary data output from the first and second storage devices of the twin cell selected for read, and judging information stored in the twin cell; and a control circuit. Two memory cells constituting a twin cell are arranged to hold different data. Therefore, even when the retention performance of one memory cell deteriorates, the difference between data held by the two memory cells can be maintained. Hence, differential amplification of such difference enables acquisition of proper stored information. Thus, retention performance of an electrically rewritable nonvolatile memory cell is improved. | 08-25-2011 |
20110208905 | Non-Volatile Memory Device For Concurrent And Pipelined Memory Operations - This disclosure provides a non-volatile memory device that concurrently processes multiple page reads, erases or writes involving the same memory space. The device relies upon a crossbar and a set of page buffers that may each be dynamically assigned to each read or write request. The device also separates memory array control from IO control, such that multiple cycle state change operations can be performed while the buffers are used to transfer data into and out of the buffers along an external data bus; using this structure, the memory device can accept multiple transactions where pages can be immediately loaded into buffers and then “pipelined” either for transfer to a write data register or to an external bus as appropriate. By significantly mitigating the substantial “busy time” associated with program and erase of non-volatile memory devices, especially flash devices, this disclosure greatly expands potential application of such devices. | 08-25-2011 |
20110213912 | MEMORY MANAGEMENT AND WRITING METHOD, AND MEMORY CONTROLLER AND MEMORY STORAGE SYSTEM USING THE SAME - A memory management and writing method for managing a memory module is provided. The memory module has a plurality of memory units and a plurality of data input/output buses corresponding to the memory units. The method includes configuring a plurality of logical units, dividing each of the logical units as a plurality of logical parts, and mapping the logical parts of each of the logical units to physical blocks of the memory units. The method also includes respectively establishing mapping tables corresponding to the data input/output buses, and only using one of the data input/output buses to write data from a host system into the corresponding memory unit according to the mapping table corresponding to the data input/output bus. Accordingly, the method can effectively increase the speed of writing data into the memory module. | 09-01-2011 |
20110213913 | MEMORY SYSTEM - According to one embodiment, a memory system includes a nonvolatile memory, a managing unit, an order rule holding unit, a position information storing unit, a list selecting unit, a block selecting unit, a writing unit, and an updating unit. The managing unit holds for each of storage areas of the nonvolatile memory a free block list indicating free blocks. The order rule holding unit holds an order rule used to determine an order of the free block lists. The position information storing unit stores position information indicating the position of the free block list in the order rule. The list selecting unit selects the free block list corresponding to the position indicated by the position information and the block selecting unit selects the free block therefrom. The updating unit updates after the list selection the position information in the position information storing unit with position information indicating the position of the subsequently selected free block list. | 09-01-2011 |
20110213914 | I-PEN - This patent consists of a USB flash drive that includes two USB connectors at the ends of the main body that perform different functions. This storage device also includes an LCD display, headphone jack, and internal or removable battery. | 09-01-2011 |
20110213915 | NONVOLATILE STORAGE DEVICE, ACCESS DEVICE AND NONVOLATILE STORAGE SYSTEM - A nonvolatile storage device includes a nonvolatile memory that stores data and a memory controller that controls the nonvolatile memory. The memory controller accepts a pause instruction to pause writing from the access device within a period in which data from the access device are written, and writes the data received from the access device to the nonvolatile memory within a predetermined time interval, then pauses the writing and accepts read and/or write of new data from the access device. | 09-01-2011 |
20110213916 | STORAGE CONTROL APPARATUS, DATA MANAGEMENT SYSTEM AND DATA MANAGEMENT METHOD - A storage control apparatus according to the present invention includes a plurality of connecting units connected to one or more host computers and one or more hard disk drives as storage media for storing data, one or more non-volatile storage media which are of a different type from the hard disk drives and which store data WRITE requested from the host computer, a plurality of processing units for processing WRITE and READ requests from the host computer by using the hard disk drives or the non-volatile storage media and, a plurality of memory units for storing control information to be by the processing units. | 09-01-2011 |
20110213917 | Methods and Systems for Improving Read Performance in Data De-Duplication Storage - The present invention is directed toward methods and systems for data de-duplication. More particularly, in various embodiments, the present invention provides systems and methods for data de-duplication that may utilize a data de-duplication system that retrieves data from a data storage device in an order based on the location of blocks on the data storage device. Some embodiments break a data stream into multiple blocks of data and store the blocks of data on a data storage device of a data de-duplication system, wherein a code representing a redundant block of data is stored in place of the block of data. A location for each block of data may be stored. Additionally, the blocks may be read in an order that is determined based on the location of the blocks. | 09-01-2011 |
20110213918 | METHOD OF STORING DATA ON A FLASH MEMORY DEVICE - Methods and apparatus are disclosed, such as those involving a flash memory device. One such method includes storing data on memory cells on a memory block including a plurality of word lines and a plurality of memory cells on the word lines. The word lines comprising one or more bottom edge word lines, one or more top edge word lines, and intermediate word lines between the bottom and top edge word lines. The data is stored first on memory cells on the intermediate word lines. Then, a remaining portion, if any, of the data is stored on memory cells on the bottom edge word lines and/or the top edge word lines. This method enhances the life of the flash memory by preventing a premature failure of memory cells on the bottom or top edge word lines, which can be more prone to failure. | 09-01-2011 |
20110213919 | FLASH-based Memory System with Static or Variable Length Page Stripes Including Data Protection Information and Auxiliary Protection Stripes - Methods and apparatuses for enhanced protection of data stored in a FLASH memory system involve a controller capable of protecting data using page stripes and auxiliary protection stripes. The controller stores the data in a manner such that the pages making up each page stripe include a plurality of data pages and at least one data protection page and the pages making up each auxiliary protection stripe include a plurality of data pages and an auxiliary protection page. At least a plurality of data pages are within one page stripe and one auxiliary protection stripe such that each data page is protected both by a data protection page in the page stripe and an auxiliary protection page in the auxiliary protection stripe. | 09-01-2011 |
20110213920 | FLASH-based Memory System with Static or Variable Length Page Stripes Including Data Protection Information and Auxiliary Protection Stripes - Methods and apparatuses for enhanced protection of data stored in a FLASH memory system involve a controller capable of protecting data using page stripes and auxiliary protection stripes. The controller stores the data in a manner such that the pages making up each page stripe include a plurality of data pages and at least one data protection page and the pages making up each auxiliary protection stripe include a plurality of data pages and an auxiliary protection page. At least a plurality of data pages are within one page stripe and one auxiliary protection stripe such that each data page is protected both by a data protection page in the page stripe and an auxiliary protection page in the auxiliary protection stripe. | 09-01-2011 |
20110213921 | Command Queuing Smart Storage Transfer Manager for Striping Data to Raw-NAND Flash Modules - A flash module has raw-NAND flash memory chips accessed over a physical-block address (PBA) bus by a NVM controller. The NVM controller is on the flash module or on a system board for a solid-state disk (SSD). The NVM controller converts logical block addresses (LBA) to physical block addresses (PBA). Data striping and interleaving among multiple channels of the flash modules is controlled at a high level by a smart storage transaction manager, while further interleaving and remapping within a channel may be performed by the NVM controllers. A SDRAM buffer is used by a smart storage switch to cache host data before writing to flash memory. A Q-R pointer table stores quotients and remainders of division of the host address. The remainder points to a location of the host data in the SDRAM. A command queue stores Q, R for host commands. | 09-01-2011 |
20110219168 | Flash Memory Hash Table - Implementations and techniques for flash memory-type hash tables are generally disclosed. | 09-08-2011 |
20110219169 | Buffer Pool Extension for Database Server - Aspects of the subject matter described herein relate to a buffer pool for a database system. In aspects, secondary memory such as solid state storage is used to extend the buffer pool of a database system. Thresholds such as hot, warm, and cold for classifying pages based on access history of the pages may be determined via a sampling algorithm. When a database system needs to free space in a buffer pool in main memory, a page may be evicted to the buffer pool in secondary memory or other storage based on how the page is classified and conditions of the secondary memory or other storage. | 09-08-2011 |
20110219170 | Method and Apparatus for Optimizing the Performance of a Storage System - Methods and apparatuses for optimizing the performance of a storage system comprise a FLASH storage system, a hard drive storage system, and a storage controller. The storage controller is adapted to receive READ and WRITE requests from an external host, and is coupled to the FLASH storage system and the hard drive storage system. The storage controller receives a WRITE request from an external host containing data and an address, forwards the received WRITE request to the FLASH storage system and associates the address provided in the WRITE request with a selected alternative address, and provides an alternative WRITE request, including the selected alternative address and the data received in the WRITE request, to the hard drive storage system, wherein the alternative address is selected to promote sequential WRITE operations within the hard drive storage system. | 09-08-2011 |
20110219171 | VIRTUAL CHANNEL SUPPORT IN A NONVOLATILE MEMORY CONTROLLER - A controller uses N dedicated ports to receive N signals from N non-volatile memories independent of each other, and uses a bus in a time shared manner to transfer data to and from the N non-volatile memories. The controller receives from a processor, multiple operations to perform data transfers, and stores the operations along with a valid bit set active by the processor. When a signal from a non-volatile memory is active indicating its readiness and when a corresponding operation has a valid bit active, the controller starts performance of the operation. When the readiness signal becomes inactive, the controller internally suspends the operation and starts performing another operation on another non-volatile memory whose readiness signal is active and for which an operation is valid. A suspended operation may be resumed any time after the corresponding readiness signal becomes active and on operation completion the valid bit is set inactive. | 09-08-2011 |
20110219172 | NON-VOLATILE MEMORY ACCESS METHOD AND SYSTEM, AND NON-VOLATILE MEMORY CONTROLLER - A non-volatile memory access method and system, and a non-volatile memory controller are provided for accessing a plurality of physical blocks in a non-volatile memory chip, and each physical block has a plurality of physical pages. The method includes determining whether there is enough space in a first physical block to write a plurality of specific physical pages when data stored in one of the specific physical pages are to be updated; and writing valid data and data to be updated into the first physical block when the first physical block has enough space to write the specific physical pages. | 09-08-2011 |
20110219173 | SEMICONDUCTOR MEMORY SYSTEM - According to one embodiment, there is provided a semiconductor memory system including a controller and a memory unit. The controller includes a generation unit, an association unit, a retaining unit, an encoding/decoding unit, and a determination unit. When the access request information is managed, the encoding/decoding unit performs, without generating an obfuscation information by the generation unit, an encoding processing or a decoding processing by using the obfuscation information retained in the retaining unit. And when the access request information is not managed, the encoding/decoding unit performs, after the generation unit generates obfuscation information based on the access request information, the encoding processing or the decoding processing. | 09-08-2011 |
20110219174 | Non-Volatile Memory and Method with Phased Program Failure Handling - In a memory with block management system, program failure in a block during a time-critical memory operation is handled by continuing the programming operation in a breakout block. Later, at a less critical time, the data recorded in the failed block prior to the interruption is transferred to another block, which could also be the breakout block. The failed block can then be discarded. In this way, when a defective block is encountered during programming, it can be handled without loss of data and without exceeding a specified time limit by having to transfer the stored data in the defective block on the spot. This error handling is especially critical for a garbage collection operation so that the entire operation need not be repeated on a fresh block during a critical time. Subsequently, at an opportune time, the data from the defective block can be salvaged by relocation to another block. | 09-08-2011 |
20110219175 | STORAGE CAPACITY STATUS - In one embodiment of the present invention, a memory device is disclosed to include memory organized into blocks, each block having a status associated therewith and all of the blocks of the nonvolatile memory having collectively a capacity status associated therewith and a display for showing the capacity status even when no power is being applied to the display. | 09-08-2011 |
20110219176 | FILE-COPYING APPARATUS OF PORTABLE STORAGE MEDIA - The present invention provides a portable file-copying apparatus which includes a first connecting unit, a second connecting unit, and a control unit. The first connecting unit can receive a first portable storage media which includes an original file. The second connecting unit can receive a second portable storage media. Furthermore, the control unit is connected to the first connecting unit, the second connecting unit, and a memory. The control unit is applied for storing the original file in the memory, and copying the file to the second portable storage media in accordance with a control signal. | 09-08-2011 |
20110219177 | MEMORY SYSTEM AND CONTROL METHOD THEREOF - A memory system includes a nonvolatile memory including blocks as data erase units, a measuring unit which measures an erase time at which data in each block is erased, a block controller having a block table which associates a state value indicating one of a free state and a used state with the erase time for each block, a detector which detects blocks in which rewrite has collectively occurred within a short period, a first selector which selects a free block having an old erase time as a first block, a second selector which selects a block in use having an old erase time as a second block, and a leveling unit which moves data in the second block to the first block if the first block is included in the blocks detected by the detector. | 09-08-2011 |
20110219178 | ERASE BLOCK DATA SPLITTING - A Flash memory device, system, and data handling routine is detailed with a distributed erase block sector user/overhead data scheme that splits the user data and overhead data and stores them in differing associated erase blocks. The erase blocks of the Flash memory are arranged into associated erase block pairs in “super blocks” such that when user data is written to/read from the user data area of a sector of an erase block of the super block pair, the overhead data is written to/read from the overhead data area of a sector of the other associated erase block. This data splitting enhances fault tolerance and reliability of the Flash memory device. | 09-08-2011 |
20110219179 | FLASH MEMORY DEVICE AND FLASH MEMORY SYSTEM INCLUDING BUFFER MEMORY - A flash memory device includes a flash memory and a buffer memory. The flash memory is divided into a main region and a spare region. The buffer memory is a random access memory and has the same structure as the flash memory. In addition, the flash memory device further includes control means for mapping an address of the flash memory applied from a host so as to divide a structure of the buffer memory into a main region and a spare region and for controlling the flash memory and the buffer memory to store data of the buffer memory in the flash memory or to store data of the flash memory in the buffer memory. | 09-08-2011 |
20110219180 | FLASH MEMORY DEVICE WITH MULTI-LEVEL CELLS AND METHOD OF WRITING DATA THEREIN - In one aspect, a method of writing data in a flash memory system is provided. The flash memory system forms an address mapping pattern according to a log block mapping scheme. The method includes determining a writing pattern of data to be written in a log block, and allocating one of SLC and MLC blocks to the log block in accordance with the writing pattern of the data. | 09-08-2011 |
20110225344 | Method for Dynamic Configuration of an Electronic System with Variable Input and Output Signals - To enable dynamic configuration of an electronic system ( | 09-15-2011 |
20110225345 | Storage System Having Volatile Memory and Non-Volatile Memory - The present invention allows a save target stored in a volatile memory, to be reliably saved to a non-volatile memory and reduces the time required for the save processing as much as possible. The charging state of a battery is regularly of irregularly checked. It is determined, according to the checked charging state, which information element stored in the volatile memory should be made a save target at the time of the occurrence of a power interruption. Among a plurality of information elements stored in the volatile memory, a predetermined information element is made a non-save target of save processing, according to a state related to the predetermined information element. | 09-15-2011 |
20110225346 | GARBAGE COLLECTION IN A STORAGE DEVICE - In general, this disclosure relates to garbage collection in a storage device. Aspects of this disclosure describe techniques to identify one or more candidate memory storage blocks that should be recycled during garbage collection. The one or more candidate memory storage blocks may be identified based at least on monitored soft metrics of the candidate memory storage blocks. During garbage collection, the identified one or more candidate memory storage blocks may be recycled to free up storage space. | 09-15-2011 |
20110225347 | LOGICAL BLOCK STORAGE IN A STORAGE DEVICE - In general, this disclosure relates to storage of logical blocks in a storage device. Aspects of this disclosure describe techniques to monitor the frequency of access of one or more logical blocks referenced by one or more logical block addresses. Based on the frequency of access, in non-limiting aspects of this disclosure, a controller may select one or more physical blocks of a common memory storage block. The storage device may store the logical blocks in the selected physical blocks. | 09-15-2011 |
20110225348 | ELECTRONIC DEVICES USING REMOVABLE AND PROGRAMMABLE ACTIVE PROCESSING MODULES - System and methods for assembling electronic devices ( | 09-15-2011 |
20110225349 | Firmware Flashing of a Portable Device Using a Serial Bus Hub - System and method for configuring a portable device. The portable device includes a serial bus hub, one or more processors coupled to the serial bus hub via a serial bus, and a flash memory coupled to the serial bus hub via the serial bus. A degraded signal is received to a serial bus hub included in the portable device via a serial bus, where the degraded signal includes code to be written to the flash memory to initialize or update firmware for the portable device. The serial bus hub restores the degraded signal, thereby generating a restored signal, and sends the restored signal to at least one of the one or more processors to initialize or update the firmware in the flash memory for the portable device. | 09-15-2011 |
20110225350 | Methods and Apparatus for Soft Data Generation for Memory Devices Based Using Reference Cells - Methods and apparatus are provided for soft data generation for memory devices using reference cells. At least one soft data value is generated in a memory device by writing a known data to one or more reference cells; reading one or more of the reference cells; obtaining a read statistic based on the read one or more reference cells; and obtaining the at least one soft data value based on the obtained read statistic. The read statistics can optionally be obtained for one or more desired locations of a memory array; or for a given pattern, PATT, in one or more aggressor cells. The read statistic can optionally comprise asymmetric statistics obtained for a plurality of possible values. | 09-15-2011 |
20110225351 | MEMORY CARD AND MEMORY SYSTEM HAVING THE SAME - A memory card includes: a first memory chip responding to all commands input externally; and a second memory chip responding to commands, among the commands input externally, relevant to reading, programming, and erasing operations with data. Card identification information stored in the first memory chip includes capacity information corresponding to a sum of sizes of the first and second memory chips. The plurality of memory chips of the memory card are useful in designing the memory card with storage capacity in various forms. | 09-15-2011 |
20110225352 | APPARATUS AND SYSTEM FOR OBJECT-BASED STORAGE SOLID-STATE DRIVE - An object-based storage system comprising a host system capable of executing applications for and with an object-based storage device (OSD). Exemplary configurations include a call interface, a physical layer interface, an object-based storage solid-state device (OSD-SSD), and are further characterized by the presence of a storage processor capable of processing object-based storage device algorithms interleaved with processing of physical storage device management. Embodiments include a storage controller capable of executing recognition, classification and tagging of application files, especially including image, music, and other media. Also disclosed are methods for initializing and configuring an OSD-SSD device. | 09-15-2011 |
20110225353 | REDUNDANT ARRAY OF INDEPENDENT DISKS (RAID) WRITE CACHE SUB-ASSEMBLY - In at least some embodiments, a computing system includes a processor and a communication bus external to the processor. The computing system also includes a Redundant Array of Independent Disks (RAID) write cache sub-assembly coupled to the communication bus, the RAID write cache sub-assembly having non-volatile memory. | 09-15-2011 |
20110231594 | STORAGE SYSTEM HAVING PLURALITY OF FLASH PACKAGES - The storage system comprises a plurality of flash packages configuring one or more RAID groups, and a controller coupled to the plurality of flash packages. Each flash package comprises a plurality of flash chips configured from a plurality of physical blocks. The controller identifies a target area related to an unnecessary area, unmaps a physical block allocated to a logical block belonging to this target area from this logical block, and manages the unmapped physical block as a free block. | 09-22-2011 |
20110231595 | SYSTEMS AND METHODS FOR HANDLING HIBERNATION DATA - Systems and methods are disclosed for storing hibernation data in a non-volatile memory (“NVM”). Hibernation data is data stored in volatile memory that is lost during a reduced power event, but is needed to restore the device to the operational state it was in prior to entering into the reduced power event. When a reduced power event occurs, the hibernation data is stored in the NVM. When the device “wakes up” the hibernation data is retrieved and used to restore the device to its prior operational state. | 09-22-2011 |
20110231596 | Multi-Tiered Metadata Scheme for a Data Storage Array - Method and apparatus for managing metadata associated with a data storage array. In accordance with various embodiments, a group of user data blocks are stored to memory cells at a selected physical address of the array. A multi-tiered metadata scheme is used to generate metadata which describes the selected physical address of the user data blocks. The multi-tiered metadata scheme provides an upper tier metadata format adapted for groups of N user data blocks, and a lower tier metadata format adapted for groups of M user data blocks where M is less than N. The generated metadata is formatted in accordance with a selected one of the upper or lower tier metadata formats in relation to a total number of the user data blocks in the group. | 09-22-2011 |
20110231597 | DATA ACCESS METHOD, MEMORY CONTROLLER AND MEMORY STORAGE SYSTEM - A data access method for accessing a non-volatile memory module is provided. The data access method includes configuring a plurality of logical addresses and grouping the logical addresses into logical blocks to map to the physical blocks of the non-volatile memory module, and a host system formats the logical addresses into one partition by using a file system and the partition stores at least one file and a file description block corresponding to the file. The data access method further includes searching an end mark corresponding to entry values of the file description block, setting logical addresses storing the end mark as default pattern addresses, and setting values stored in the logical addresses as default values corresponding to the default pattern addresses. Accordingly, the data access method can divide one partition into a write protect area and a writable area by updating data stored in the default pattern addresses. | 09-22-2011 |
20110231598 | MEMORY SYSTEM AND CONTROLLER - According to one embodiment, a memory system includes a first memory that is nonvolatile, a second memory, and a controller that performs data transfer between a host device and the first memory by using the second memory. The controller caches data of each write command transmitted from the host device in the second memory, and performs a first transfer of transferring the data of each write command, which is cached in the second memory, to the first memory while leaving a beginning portion at a predetermined timing. | 09-22-2011 |
20110231599 | STORAGE APPARATUS AND STORAGE SYSTEM - A storage apparatus includes: an input/output section configured to input and output data related to an external access; a memory for storing input data input by the input/output section by distributing the input data to a plurality of areas while making use of a cache area for temporarily storing the input data; and a control section configured to make an access to the memory on the basis of the external access and carry out a garbage correction operation on the areas including the cache area in order to release the cache area in the access made to the memory on the basis of the external access. | 09-22-2011 |
20110231600 | Storage System Comprising Flash Memory Modules Subject to Two Wear - Leveling Process - A storage system using flash memories includes a storage controller and plural flash memory modules as storage media. Each flash memory module includes at least one flash memory chip and a memory controller for leveling erase counts of blocks belonging to the flash memory chip. The storage controller combines the plural flash memory modules into a first logical group, translates a first address used for accessing the flash memory modules belonging to the first logical group to a second address used for handling the first address in the storage controller, and combines the plural first logical groups into a second logical group. | 09-22-2011 |
20110238885 | STORAGE SUBSYSTEM - Processing in accordance with the updating of data is carried out distributively by a control unit that controls a cache memory and by a memory controller that controls a nonvolatile semiconductor memory. When updating flash memory data, a main processor creates an XOR write command and transfers the same to a flash memory controller, a microprocessor of the flash memory controller parses the XOR write command, reads out an old parity from a page of a user area in the flash memory, creates a new parity by carrying out an exclusive OR operation using the read-out old parity, “b” data, which is the old data, and “d” data, which is the new data, and stores the created new parity in a page of a renewal area in a flash memory for storing parity. | 09-29-2011 |
20110238886 | GARBAGE COLLECTION SCHEMES FOR INDEX BLOCK - Systems and methods are provided for handling uncorrectable errors that may occur during garbage collection of an index page or block in non-volatile memory. | 09-29-2011 |
20110238887 | HYBRID-DEVICE STORAGE BASED ON ENVIRONMENTAL STATE - A hybrid storage device that includes a hard-disk drive (HDD) and a flash memory is described. When control logic in the hybrid storage device receives a request from an external device to write a block of data to a logical address in a first portion of an address space that maps to the HDD, the control logic writes the block of data to the HDD. However, if there is a change in environmental state information of the hybrid storage device during the write operation, the control logic writes at least a portion of the block of data to a logical address for the block of data in a second portion of the address space which maps to the flash memory. Note that the address space may be common to the external device and the hybrid storage device. | 09-29-2011 |
20110238888 | PROVIDING VERSIONING IN A STORAGE DEVICE - Provided are a computer program product, system and method for managing Input/Output (I/O) requests to a storage device. A write request is received having write data for a logical address in the storage device. A determination is made as to whether preserve mode is enabled. A first entry is located in a volume control table for the logical address indicating a version number of the data in the storage device for the logical address and a first physical location in the storage device having the data for the logical address. The write data is written to a second physical location in the storage device. A second entry is added to the volume control table for the logical address to write in response to determining that the preserve mode is enabled. In response to determining that the preserve mode is enabled, the volume control table is updated to have one of the first and second entry for the logical address point to the second physical location and have the version number indicate a current version and to have the first or second entry not indicating the current version to indicate the first physical location and the version number indicate a previous version. | 09-29-2011 |
20110238889 | SEMICONDUCTOR MEMORY DEVICE FROM WHICH DATA CAN BE READ AT LOW POWER - According to one embodiment, a semiconductor memory device includes a memory cell array and a control circuit. The memory cell array is composed of a plurality of memory cells arranged in a matrix pattern. The control circuit sets a first flag data in a second memory cell in order to write data to a plurality of first memory cells of memory cell array, the second memory cell having been selected at the same time as the first memory cells, determines whether the first flag data is set in the second memory cell before data is read from the first memory cells, and reads no data from the first memory cells and outputs data of first logic level if the first flag data is not set in the second memory cell, and reads data from the first memory cells if the first flag data is set in the second memory cell. | 09-29-2011 |
20110238890 | MEMORY CONTROLLER, MEMORY SYSTEM, PERSONAL COMPUTER, AND METHOD OF CONTROLLING MEMORY SYSTEM - According to one embodiment, a memory controller that performs control of a nonvolatile semiconductor memory includes a first management table that stores correspondence between logical block addresses and physical block addresses, a second management table that stores a number of times of data writing for each of the logical block addresses, and a third management table that stores a number of times of data erasing for each of the physical block addresses. The memory controller according to the embodiment includes a writing control unit that selects a spare block not associated with the logical block address and writes data in the spare block. The writing control unit levels, based on the number of times of data writing associated with the logical block addresses and the number of times of data erasing associated with the physical block addresses, numbers of times of data erasing among the blocks. | 09-29-2011 |
20110238891 | METHOD FOR SUPPRESSING ERRORS, AND ASSOCIATED MEMORY DEVICE AND CONTROLLER THEREOF - A method for suppressing errors is provided. The method is applied to a controller of a Flash memory, where the Flash memory includes a plurality of blocks. The method includes: according to an address of data to be written into or read from the Flash memory, determining whether to utilize an original seed as an input seed of a randomizer/derandomizer, where the randomizer/derandomizer is arranged to generate a random function according to the input seed, with the random function being utilized for adjusting a plurality of bits of the data bit by bit, and with regard to at least each block of the blocks, a value of the original seed remains unvaried; and when it is determined that the original seed should not be utilized as the input seed, generating the random function according to a new seed to adjust the data. | 09-29-2011 |
20110238892 | WEAR LEVELING METHOD OF NON-VOLATILE MEMORY - A method of wear leveling applied to a non-volatile memory is provided. The method comprises steps of: categorizing all blocks within the non-volatile memory to a first group with erased blocks having higher history numbers, a second group with erased blocks having lower history numbers, or a third group with blocks not either assigned to the first group or the second group; selecting a first block which contains a clod data from the third group; selecting a second block from the first group; copying the cold data from the first block into the second block and updating the history number of the second block; and erasing the first block. | 09-29-2011 |
20110238893 | FLASH BASED MEMORY COMPRISING A FLASH TRANSLATION LAYER AND METHOD FOR STORING A FILE THEREIN - A Flash based memory comprising a Flash translation layer which comprises first translation information associating a first logical address of a logical file system emulating a sectored storage medium, the logical address being a logical sector start address with a first physical address of said flash based memory. The logical file system comprises a number of logical stuffing bits expanding a logical size of data of a file stored in said Flash based memory such that the expanded logical size corresponds to an integer number of logical sectors and the Flash translation layer comprises second translation information associating a second logical address with a second physical address and depending on said number of logical stuffing bits, the file being stored in a contiguous physical address sequence starting at the first physical address and ending at the second physical address. | 09-29-2011 |
20110238894 | Non-Volatile Memory Devices and Control and Operation Thereof - An improved non-volatile erase block memory device apparatus and method is described that incorporates an improved addressing scheme to provide for extended addressing allowing redundant erase blocks that are not utilized to repair general use erase blocks of the main memory array to be accessed and utilized as additional storage space by an end user. The additional storage space formed by the unused redundant erase blocks and the specified storage space of the main memory array is presented to the end user as a single contiguous address space. Additionally, the redundant erase blocks can be utilized to repair any damaged erase block in the memory array of the non-volatile erase block memory or Flash memory device regardless of bank placement. | 09-29-2011 |
20110238895 | NONVOLATILE MEMORY CONTROLLER AND NONVOLATILE STORAGE DEVICE - A flash memory unit includes a plurality of physical blocks including a plurality of memory cells and serving as erase units of data, each of the memory cells is capable of recording information of 1 bit or more, degradation in the characteristics of the memory cells differs according to the amount of information that is recorded, a controller includes a control unit for controlling the reading, writing and erasure of data to and from the flash memory unit, and a degradation level table for recording a degradation level of the memory cells in physical block units, and the control unit stores, in the degradation level table, the degradation level of the memory cells according to the amount of information stored in the memory cells for each cycle of data erasure from the physical blocks. | 09-29-2011 |
20110238896 | DATA-PROCESSING METHOD, PROGRAM, AND SYSTEM - A data-processing method in a flash memory with a plurality of sectors, the method includes arranging first data which is not updated in a first sector at a leading portion of a second sector and adding a first identifier of the first data to the second sector by a memory control circuit when transferring data in the first sector to the second sector, the plurality of sectors including the first sector and the second sector. | 09-29-2011 |
20110238897 | MEMORY SYSTEM, PERSONAL COMPUTER, AND METHOD OF CONTROLLING THE MEMORY SYSTEM - According to one embodiment, a memory system includes: a nonvolatile semiconductor memory including a plurality of normal blocks and at least one dummy block, each of the normal blocks being a unit of data erasing; a writing control unit that rewrites the dummy block the number of times equal to or larger than a maximum number of times among the numbers of times of rewriting of the normal blocks; a monitor unit that monitors a data erasing time or a data writing time of the dummy block; and a wear-leveling control unit that averages the numbers of times of rewriting of the normal blocks. The memory system determines, based on a monitor result of the monitor unit, possibility of continuation of the rewriting of the normal blocks. | 09-29-2011 |
20110238898 | NONVOLATILE MEMORY CONTROLLER AND NONVOLATILE STORAGE DEVICE - A controller includes a control unit for controlling writing and/or reading of data to and from physical block based on a logical address from a host device, a logical defective cluster table for storing information concerning a logical address of a logical defective cluster which is one or more partial areas within the effective logical address range and an address conversion table for storing corresponding information of a logical address of the effective logical address range and a physical address of the physical block on the data stored in the physical block. Upon receiving a data write command from the host device for writing data to the logical address stored in the logical defective cluster table, the control unit disables the reflection of writing of data for the logical address to the physical block. | 09-29-2011 |
20110238899 | MEMORY SYSTEM, METHOD OF CONTROLLING MEMORY SYSTEM, AND INFORMATION PROCESSING APPARATUS - A WC resource usage is compared with an auto flush (AU) threshold Caf that is smaller than an upper limit Clmt, and when the WC resource usage exceeds the AF threshold Caf, the organizing state of a NAND memory | 09-29-2011 |
20110238900 | Method of managing a solid state drive, associated systems and implementations - In one embodiment, the method includes storing, by a status checking module, status information for a solid state drive, and determining a status state of the solid state drive based on the status information. The status state is one of a good state, an intermediate state and a bad state, and the intermediate state is a state between the good state and the bad state. | 09-29-2011 |
20110238901 | INFORMATION PROCESSING APPARATUS CAPABLE OF ENABLING SELECTION OF USER DATA ERASE METHOD, DATA PROCESSING METHOD, AND STORAGE MEDIUM - A mechanism which makes it possible to automatically and appropriately select an erase method of erasing user data in a shorter time such that the user data can by no means be reproduced, according to the type of a connected nonvolatile storage device. An information processing apparatus determines an erase method of erasing an erase area of the nonvolatile storage device according to a management table generated based on attribute information acquired from the nonvolatile storage device. Then, the image forming apparatus erases information stored in the erase area according to the determined erase method. | 09-29-2011 |
20110238902 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND DRIVING METHOD - A nonvolatile semiconductor memory device in which a memory cell life can be prolonged while making it possible to perform writing in units of bits. When command information represents writing, a comparing unit | 09-29-2011 |
20110238903 | METHOD AND DEVICE OF MANAGING A REDUCED WEAR MEMORY - A method of encoding and storing data. The method comprises providing digital data designated to be written in at least one memory element having a plurality of memory cells, encoding digital data so as to increase the prevalence of at least one memory cell state in relation to the prevalence of at least one other memory cell state by conditionally inverting the data bits in accordance with the count of a particular state in the data to be written, and programming the plurality of memory cells to store the encoded digital data. | 09-29-2011 |
20110246701 | STORAGE APPARATUS AND ITS DATA CONTROL METHOD - Efficient leveling among a plurality of FMPKs | 10-06-2011 |
20110246702 | Management Of Configuration Data Using Persistent Memories Requiring Block-Wise Erase Before Rewriting - According to an aspect, the values corresponding to each group of parameters are stored in successive memory locations of a set of blocks, and pointer locations are maintained to point to the area where the groups of values are stored. When a new value is received for a parameter of a group, the values of parameters (with the new value substituted for the corresponding old value) of the group are replicated to a new set of locations in the same set of blocks if sufficient number of successive unwritten memory locations are available. A pointer data from the prior set of locations to the new set of locations is also maintained. According to another aspect, when there is insufficient space for the replication, all the present valid values of all groups are first written to a new set of blocks, and then only the earlier set of blocks are erased. | 10-06-2011 |
20110246703 | CONSTRAINED CODING TO REDUCE FLOATING GATE COUPLING IN NON-VOLATILE MEMORIES - Constrained coding to reduce floating gate coupling in non-volatile memories including a method for storing data. The method includes receiving write data to be written to a flash memory device, selecting a codeword in response to the write data, and writing the codeword to the flash memory device. The codeword is selected to reduce floating gate coupling in the flash memory device by preventing specified symbol patterns from occurring in the codeword. | 10-06-2011 |
20110246704 | METHOD FOR OPERATING NON-VOLATILE FLASH MEMORY WITH WRITE PROTECTION MECHANISM - A method for operating a non-volatile flash memory with a write protection mechanism is provided. The method comprises the steps as follow. A command is issued. When the command is a safeguard information modification command, only when the safeguard information modification command matches the specific combination of the plurality of modification instructions, a safeguard information is allowed to be modified. When the command is a flash memory data modification command, only when both the status register protection information and the safeguard information indicate that the memory block/sector is not under write-protection, the memory block/sector is allowed to be modified according to the flash memory data modification command. | 10-06-2011 |
20110246705 | METHOD AND SYSTEM FOR WEAR LEVELING IN A SOLID STATE DRIVE - A method and system for wear leveling in a solid state drive by mapping the logical regions of the solid state drive that hold static content or information into the physical regions of the solid state drive that have erase counts more than an average erase count of all of the physical regions. By doing so, it allows the solid state drive to wear level itself naturally through continued usage. In one embodiment of the invention, the erase count of each physical region is incremented with every erasing operation of each physical region. The physical regions that have a high count of erase count operations are mapped with content of the logical regions with static content so that the possibility of future erase operations of these physical regions is reduced. | 10-06-2011 |
20110246706 | DISK ARRAY CONFIGURATION PROGRAM, COMPUTER, AND COMPUTER SYSTEM - To improve the data input/output performance of a disk array with a hybrid configuration of flash memory and HDDs. A computer that executes a disk array configuration program in accordance with the present invention, when relocating a file from a hard disk to flash memory, stores the file in cache memory without immediately writing the file to the flash memory if the file size is smaller than the block size of the flash memory. | 10-06-2011 |
20110246707 | SEMICONDUCTOR DEVICE AND DATA PROCESSING METHOD - A semiconductor device has: as security states to which the nonvolatile memory device can transition, an unprotected state in which, when secret information is not set in the nonvolatile memory device, rewriting the nonvolatile memory device is permitted, and reading the stored information is permitted; a protection unlocked state in which, when the secret information is set in the nonvolatile memory device, rewriting the nonvolatile memory device is permitted on condition that a result of authentication using the secret information is correct, and reading the stored information is permitted; and a protection locked state in which, when the secret information is set in the nonvolatile memory device, rewriting the nonvolatile memory device is inhibited until correctness as a result of authentication using the secret information is confirmed, and reading the stored information is inhibited under a predetermined condition. | 10-06-2011 |
20110246708 | METHOD AND APPARATUS FOR EXECUTING A PROGRAM BY AN SPI INTERFACE MEMORY(amended - A multi-channel SPI interface memory controller disposed between a CPU and a multi-channel SPI interface memory is provided in the present invention. The multi-channel SPI interface memory controller comprises: a data path interface coupled to a bus of the CPU; a control path interface coupled to the bus of the CPU; a master controller coupled to the multi-channel SPI interface memory; a register bank disposed between the master controller and the control path interface, wherein the master controller is in signal coupling with the data path interface, and in signal coupling through the register bank with the control path interface. The inventive multi-channel SPI interface memory controller can support direct execution of a program on the SPI interface memory. | 10-06-2011 |
20110246709 | MEMORY SYSTEM HAVING HYBRID DENSITY MEMORY AND METHODS FOR WEAR-LEVELING MANAGEMENT AND FILE DISTRIBUTION MANAGEMENT THEREOF - The present invention discloses a memory system having a hybrid density memory. The memory system includes a plurality of storage spaces whereby the storage spaces have respective levels of endurance and each storage space has a plurality of blocks and pre-determined weighting factors corresponding to the levels of endurance of the storage spaces. After executing a command of erasing a specific block, the system records the erase in accordance with the weighting factor of the storage space to which the specific block belongs. Whereby, the erase counts of all the blocks of different storage spaces are able to reach respective levels of endurance as simultaneously as possible. | 10-06-2011 |
20110246710 | Encoding and Decoding to Reduce Switching of Flash Memory Transistors - Methods of encoding data to and decoding data from flash memory devices are provided. User data having an unknown ratio of 1's to 0's is received. The user data is utilized in generating transformed data that has a predictable ratio of 1's to 0's. The transformed data is stored to flash memory. The transformed data is illustratively generate by either applying an “exclusive or” function to the user data or by converting the user data into a number having a greater number of bits. | 10-06-2011 |
20110246711 | STORAGE CONTROLLER AND METHOD FOR CONTROLLING THE SAME - A storage controller that can maintain its performance and reduce power consumption and thereby realize large capacity and low power consumption, and a method for controlling such a storage controller are provided. | 10-06-2011 |
20110252185 | Method Of Operating A NAND Memory Controller To Minimize Read Latency Time - A NAND memory chip has a plurality of blocks with each block having a certain amount of storage and wherein the amount of storage in each block is the minimum amount that is erasable as a group. A controller controls the NAND memory chip. The method of operating the controller comprises writing data into a block of the NAND memory chip to partially fill the block. Then the controller tracks the extent to which the block has been written. After the block is partially written, the step is stopped. The controller determines if a request to the NAND memory chip needs to be serviced. The controller resumes the writing into the block after servicing the request. The present invention also relates to a method for controlling, the operation of a memory device having a controller for interfacing with and controlling a NAND memory. The memory device is responsive to either serial or parallel ATA protocol commands supplied from a host. | 10-13-2011 |
20110252186 | MINIMIZING WRITE OPERATIONS TO A FLASH MEMORY-BASED OBJECT STORE - Approaches for minimizing the amount of write transactions issued to an object store maintained on a solid state device (SSD). Transactions requested against an object store maintained on a SSD may be committed once transaction information for the transaction is durably stored in a non-volatile dynamic random access memory (DRAM), which may be maintained in a HDD controller. Further, data blocks stored in a volatile cache of a database server that issues write requests to an object store maintained on one or more SSDs may be considered persistent stored once confirmation is received that the data blocks are written to a double-write buffer stored on a non-volatile medium, such as NV RAM in a HDD controller. Additionally, any data blocks that are to be written over in a non-volatile DRAM are first ensured to be no longer present within the volatile write cache maintained a the solid state device. | 10-13-2011 |
20110252187 | SYSTEM AND METHOD FOR OPERATING A NON-VOLATILE MEMORY INCLUDING A PORTION OPERATING AS A SINGLE-LEVEL CELL MEMORY AND A PORTION OPERATING AS A MULTI-LEVEL CELL MEMORY - System and method for storing data in a non-volatile memory including a multi-level cell and single-level cell memory portions. To write a dataset to the non-volatile memory, if the size of the dataset is equal to the size of pages in the multi-level cell memory portion, the dataset may be written directly to the multi-level cell memory portion to fill an integer number of pages in a single write operation. However, if the size of the dataset is different than the size of the multi-level cell memory pages, at least a portion of the dataset may be temporarily written to the single-level cell memory portion until data is accumulated in a plurality of write operations having a size equal the size of the multi-level cell memory pages. The accumulated data may fill an integer number of the pages in the multi-level cell memory portion in a single write operation. | 10-13-2011 |
20110252188 | SYSTEM AND METHOD FOR STORING INFORMATION IN A MULTI-LEVEL CELL MEMORY - A multi-level memory is used to store analog data by mapping a difference data using a mapping scheme that reduces the effect of errors caused by voltage level drift in the memory. | 10-13-2011 |
20110252189 | METHOD FOR GENERATING PHYSICAL IDENTIFIER IN STORAGE DEVICE AND MACHINE-READABLE STORAGE MEDIUM - A method and system for generating a physical identifier in a storage device that includes a plurality of storage regions is provided. The method includes determining a number of reference storage regions for uniquely identifying the storage device; comparing the number of reference storage regions to a threshold; generating auxiliary storage regions for uniquely identifying the storage device, such that a number of the auxiliary storage regions corresponds to a result of the comparison; generating location distribution information of the reference storage regions and auxiliary storage regions; and storing the location distribution information in the storage device. | 10-13-2011 |
20110252190 | Apparatus, System, and Method for Managing Data From a Requesting Device with an Empty Data Token Directive - An apparatus, system, and method are disclosed for managing data with an empty data segment directive at the requesting device. The apparatus, system, and method include a token directive generation module and a token directive transmission module. The token directive generation module generates a storage request with a token directive. The token directive includes a request to store on the storage device a data segment token. The token directive substitutes for a series of repeated, identical characters or a series of repeated, identical character strings to be stored as a data segment. The token directive includes at least a data segment identifier and a data segment length. The data segment token and the token directive are substantially free from data of the data segment. The token directive transmission module transmits the token directive to the storage device. | 10-13-2011 |
20110258363 | SUB-LUN INPUT/OUTPUT PROFILING FOR SSD DEVICES - Exemplary method, system, and computer program embodiments for profiling input/output (I/O) for solid state drive (SSD) devices in a computing storage environment by a processor device are provided. In one embodiment, a read/write ratio for each of a plurality of data segments classified in a hot category as hot data segments is determined. Each of the plurality of hot data segments is ordered by the read/write ratio in a descending order. Each of a plurality of available SSD devices is ordered by a remaining life expectancy in an ascending order. Those of the plurality of hot data segments are matched with those of the plurality of hot data segments with those of the plurality of available SSD devices such that a hot data segment having a higher read/write ratio is provided to an SSD device having a smaller remaining life expectancy than another hot data segment having a lower read/write ratio. | 10-20-2011 |
20110258364 | CONFIGURABLE MEMORY DEVICE - A method includes forming a memory device through providing an array of non-volatile memory cells including one or more non-volatile memory cell(s) and an array of volatile memory cells including one or more volatile memory cell(s) on a substrate. The method also includes appropriately programming an address translation logic associated with the memory device through a set of registers associated therewith to enable configurable mapping of an address associated with a sector of the memory device to any memory address space location in a computing system associated with the memory device. The address translation logic is configured to enable translation of an external virtual address associated with the sector of the memory device to a physical address associated therewith. | 10-20-2011 |
20110258365 | RAID CONTROLLER FOR A SEMICONDUCTOR STORAGE DEVICE - Provided is a RAID controlled storage device of a PCI-Express (PCI-e) type, which provides data storage/reading services through a PCI-Express interface. The RAID controller typically includes a disk mount coupled to a set of PCI-Express SSD memory disk units, the set of PCI-Express SSD memory disk units comprising: a set of volatile semiconductor memories; a disk monitoring unit coupled to the disk mount for monitoring the set of PCI-Express memory disk units; a disk plug and play controller coupled to the disk monitoring unit and the disk mount for controlling the disk mount; a high speed host interface coupled to the disk monitoring unit and the disk mount for providing high-speed host interface capabilities; a disk controller coupled to the high speed host interface and the disk monitoring unit; and | 10-20-2011 |
20110258366 | STATUS INDICATION IN A SYSTEM HAVING A PLURALITY OF MEMORY DEVICES - Status indication in a system having a plurality of memory devices is disclosed. A memory device in the system includes a plurality of data pins for connection to a data bus. The memory device also includes a status pin for connection to a status line that is independent from the data bus. The memory device also includes first circuitry for generating, upon completion of a memory operation having a first duration, a strobe pulse of a second duration much shorter than the first duration. The strobe pulse provides an indication of the completion of the memory operation. The memory device also includes second circuitry for outputting the strobe pulse onto the status line via the status pin. | 10-20-2011 |
20110258367 | MEMORY SYSTEM, CONTROL METHOD THEREOF, AND INFORMATION PROCESSING APPARATUS - According to the embodiment, a nonvolatile semiconductor memory that includes a plurality of banks capable of operating in parallel, a command analyzing unit that, upon receiving a power management command from a host, analyzes the received power management command, and a recording control unit that dynamically and variably controls an upper limit of the number of banks to be operated in parallel at a time of writing in accordance with an analysis result by the command analyzing unit are included, thereby suppressing the upper limit of a power consumption in accordance with an instruction from the host. | 10-20-2011 |
20110258368 | MEMORY SYSTEM AND OPERATING METHOD THEREOF - A memory system includes a non-volatile memory device including a plurality of pages and a controller connected electrically with the non-volatile memory device and configured to control the non-volatile memory device. The non-volatile memory device is configured to be capable of storing data from a set number of write operations before data erasing with respect to each page; and wherein the controller is configured to divide each page of the non-volatile memory device into first and second areas, to perform a write operation of the first area by the NOP, and to write an invalidation mark in the second area. | 10-20-2011 |
20110258369 | Data Writing Method and Data Storage Device - The invention provides a data writing method for a memory. In one embodiment, the memory comprises a data area and a spare area, the data area comprises a plurality of data blocks storing data, and the spare area comprises a plurality of spare blocks having no data stored therein. First, a write command for writing a write data to a first data block of the flash memory is received from a host. A first spare block with the earliest erase time index is then selected from the spare area. Whether an erase count of the first spare block is less than a first threshold is then determined When the erase count of the first spare block is less than the first threshold, the write data is written to the first spare block. Data is then erased from the first data block to convert the first data block to a spare block. | 10-20-2011 |
20110258370 | MULTIPLE PROGRAMMING OF FLASH MEMORY WITHOUT ERASE - To store, successively, in a plurality of memory cells, first and second pluralities of input bits that are equal in number, a first transformation transforms the first input bits into a first plurality of transformed bits. A first portion of the cells is programmed to store the first transformed bits according to a mapping of bit sequences to cell levels, but, if the first transformation has a variable output length, only if there are few enough first transformed bits to fit in the first cell portion. Then, without erasing a second cell portion that includes the first portion, if respective levels of the cells of the second portion, that represent a second plurality of transformed bits obtained by a second transformation of the second input bits, according to the mapping, are accessible from the current cell levels, the second portion is so programmed to store the second transformed bits. | 10-20-2011 |
20110258371 | METHOD FOR PERFORMING MEMORY ACCESS MANAGEMENT, AND ASSOCIATED MEMORY DEVICE AND CONTROLLER THEREOF - A method for performing memory access management includes: with regard to a same memory cell of a memory, according to a first digital value output by the memory, requesting the memory to output at least one second digital value, wherein the first digital value and the at least one second digital value are utilized for determining information of a same bit stored in the memory cell, and a number of various possible states of the memory cell is equal to a number of various possible combinations of all bit(s) stored in the memory cell; and based upon the at least one second digital value, generating/obtaining soft information of the memory cell, for use of performing soft decoding. An associated memory device and a controller thereof are also provided. | 10-20-2011 |
20110258372 | MEMORY DEVICE, HOST DEVICE, AND MEMORY SYSTEM - A memory device, a host device, and a memory system enable real-time recording of a plurality of files of data while preventing the buffer size of a host device from increasing. A memory device ( | 10-20-2011 |
20110258373 | Memory Module, Memory System,and Information Device - A memory system including ROM and RAM in which reading and writing are enabled. A memory system includes a non-volatile memory (FLASH), DRAM, a control circuit, and an information processing device. Data in FLASH is transferred to SRAM or DRAM in advance. Data transfer between the non-volatile memory and the DRAM can be performed in the background. The memory system including these plural chips is configured as a memory system module in which each chip is mutually laminated and each chip is wired via a ball grid array (BGA) and bonding wire between the chips. Data in FLASH can be read at the similar speed to that of DRAM by securing a region in which the data in FLASH can be copied in DRAM and transferring the data to DRAM in advance immediately after power is turned on or by a load instruction. | 10-20-2011 |
20110264842 | MEMORY CONTROLLER, NONVOLATILE MEMORY DEVICE, ACCESS DEVICE, AND NONVOLATILE MEMORY SYSTEM - A lifetime parameter generation part | 10-27-2011 |
20110264843 | DATA SEGREGATION IN A STORAGE DEVICE - An example method includes providing at least two data storage areas in a memory, providing a first amount of over-provisioning for a first of the at least two data storage areas and a second amount of over-provisioning for a second of the at least two data storage areas, categorizing data based on a characteristic of the data, and storing the data in one of the at least two data storage areas based on the categorization. | 10-27-2011 |
20110264844 | METHOD FOR TRANSMITTING PROGRAM CODES TO A MEMORY OF A CONTROL DEVICE, PARTICULARLY FOR MOTOR VEHICLES - A method is described for transmitting program codes to a program memory in a controller, particularly in a motor vehicle, having the following operations: a) connecting an interface in a controller to a programming appliance which contains the program codes, setting all the memory cells of the program memory in the controller to a standard value, compressing the program code in the programming appliance on the basis of a lossless data compression process, transmitting the compressed program code to the controller, decompressing the received program code in the controller, and storing the decompressed program code in the program memory in the controller. | 10-27-2011 |
20110264845 | NONVOLATILE MEMORY DEVICE HAVING OPERATION MODE CHANGE FUNCTION AND OPERATION MODE CHANGE METHOD - A nonvolatile semiconductor memory device changes an operation mode according to method type of operation to be performed. The semiconductor memory device includes a cache register for supporting a cache operation mode. The cache register and the memory cell array operate in the cache operation mode according to a first operation command. The memory cell array operates in an operation mode different from the cache operation mode according to a second operation command. | 10-27-2011 |
20110264846 | SYSTEM OF INTERCONNECTED NONVOLATILE MEMORIES HAVING AUTOMATIC STATUS PACKET - An interconnection arrangement of nonvolatile memory devices is disclosed. In the arrangement, a plurality of memory devices are series-connected. A status of at least one of the plurality of memory devices is provided. The status includes “ready”, “busy”. The memory devices includes nonvolatile memories, such as, for example, flash memories. | 10-27-2011 |
20110264847 | Data Writing Method and Data Storage Device - The invention provides a data writing method for a memory. In one embodiment, the memory comprises a data area and a spare area, the data area comprises a plurality of data blocks storing data, and the spare area comprises a plurality of spare blocks having no data stored therein. First, a write command for writing a write data to a first data block of the memory is received from a host. The spare blocks of the spare area are then sorted according to the erase counts of the spare blocks. A first spare block with the least erase counts is then selected from the spare blocks of the spare area. The write data is then written to the first spare block. Data is then erased from the first data block to convert the first data block to a spare block. | 10-27-2011 |
20110264848 | DATA RECORDING DEVICE - A data recording device is communicatable with a host device. A memory has a data recording area which is divided into a plurality of blocks. A controller is configured to perform writing of data with respect to the blocks in response to a data writing request from the host device and to perform rewriting of data in each blocks. When the controller performs the writing of data, the controller obtains update frequency information regarding the data to be written from the host device, selects one of the blocks based on the update frequency information, and writes the data to the one of the blocks. | 10-27-2011 |
20110264849 | PROTOCOL INCLUDING TIMING CALIBRATION BETWEEN MEMORY REQUEST AND DATA TRANSFER - The described embodiments provide a system for controlling an integrated circuit memory device by a memory controller. During operation, the system sends a memory-access request from the memory controller to the memory device using a first link. After sending the memory-access request, the memory controller sends to the memory device a command that specifies performing a timing-calibration operation for a second link. The system subsequently transfers data associated with the memory-access request using the second link, wherein the timing-calibration operation occurs between sending the memory-access request and transferring the data associated with the memory-access request. | 10-27-2011 |
20110264850 | Addressing, Command Protocol, and Electrical Interface for Non-Volatile Memories Utilized in Recording Usage Counts - Electrical interfaces, addressing schemes, and command protocols allow for communications with memory modules in computing devices such as imaging and printing devices. Memory modules may be assigned an address through a set of discrete voltages. One, multiple, or all of the memory modules may be addressed with a single command, which may be an increment counter command, a write command, a punch out bit field, or a cryptographic command. The commands may be transmitted using a broadcast scheme or a split transaction scheme. The status of the memory modules may be determined by sampling a single signal that may be at a low, high, or intermediate voltage level. | 10-27-2011 |
20110264851 | MEMORY SYSTEM AND DATA TRANSMITTING METHOD THEREOF - Disclosed is a data transfer method of a memory system which includes reading data from a first non-volatile memory having at least one first chip connected to a controller through a first channel; and transferring the read data to a second non-volatile memory having at least one second chip connected to the controller through a second channel, wherein each of the first and second channels has at least one line for activating a corresponding chip, wherein the first and second channels share at least one data line, and wherein data transfer operations in through the first and second channels are performed in response to data strobe signals. | 10-27-2011 |
20110264852 | Nandflash Controller and Data Transmission Method with Nandflash Controller - A Not and Flash (Nandflash) controller and a data transmission method with the Nandflash controller are provided. The Nandflash controller includes a parameter configuration device, configured to receive an operation command from outside, wherein the operation command indicates a current transmission type, execution times needed for transmitting data of size of a buffer in the Nandflash, and command parameters used by each execution; a transmission controlling device, configured to transmit data of a precoded size with the Nandflash during each data transmission according to the current transmission type and the command parameters used by this execution, until completing the execution times. The controller and method advantageously avoid configuring a command for the next operation each time the data of the precoded size is transmitted, save time and clock resources, and greatly improves transmission efficiency. | 10-27-2011 |
20110271034 | MULTIPLE PARTITIONED EMULATED ELECTRICALLY ERASABLE (EEE) MEMORY AND METHOD OF OPERATION - A method and system wherein a volatile memory is partitioned to have a first percentage of address space dedicated to a first classification of data which is data that is expected to have greater than a predetermined number of times of being modified and a second percentage of address space dedicated to a second classification of data which is data that is expected to have less than the predetermined probability of being modified. Address assignment of data to be stored in the volatile memory is made on a basis of predicted change of the data. Memory addresses of the first and second percentages of address space are respectively assigned to first and second sections of nonvolatile memory. The memory addresses of the first percentage initially consume a smaller percentage of an address map of the first section than the memory addresses of the second percentage of the second section. | 11-03-2011 |
20110271035 | EMULATED ELECTRICALLY ERASABLE (EEE) MEMORY AND METHOD OF OPERATION - A system has an emulation memory having a plurality of sectors for storing information. A controller calculates a number of addresses used divided by a number of valid records in a predetermined address range of the emulation memory. An amount of remaining addresses in a currently used space of the emulation memory which have not been used to store information is calculated. A determination is made whether the calculation is greater than a first predetermined number and whether the amount of remaining addresses is greater than a second predetermined number. If both the fraction is greater than the first predetermined number and the amount of remaining addresses is greater than the second predetermined number, any subsequent update requests are responded to using the currently used space of the emulation memory. Otherwise a compression of the emulation memory is required by copying valid data to an available sector. | 11-03-2011 |
20110271036 | PHASED NAND POWER-ON RESET - A method and system for phasing power-intensive operations is disclosed. A non-volatile storage device controller detects a power reset. The controller is in communication with non-volatile memories in the non-volatile storage device. In response to detecting a power reset, the controller determines a current consumption necessary to reset the non-volatile memories in the non-volatile storage device. The controller simultaneously resets all of the non-volatile memories when the determined current consumption is less than a current consumption threshold. If the determined current consumption is greater than the current consumption threshold, the controller resets a first subset of the plurality of non-volatile memories, and after a predetermined delay, resets a second subset of the non-volatile memories. Therefore, a power-intensive operation may be performed without exceeding a current consumption threshold by dividing the operation into a sequence of steps that do not exceed the threshold. | 11-03-2011 |
20110271037 | STORAGE DEVICE PERFORMING DATA INVALIDATION OPERATION AND DATA INVALIDATION METHOD THEREOF - A storage device of one aspect includes a data storage medium including a plurality of memory blocks, and a storage controller which outputs a free memory block signal to a host device, and which is responsive to an externally received invalidation command from the host device to selectively invalidate data stored in the memory blocks of the storage medium. The free memory block signal is in accordance with a free memory block status of the data storage medium. | 11-03-2011 |
20110271038 | INDEXED REGISTER ACCESS FOR MEMORY DEVICE - Example embodiments of a non-volatile memory device may comprise receiving an index value at one or more input terminals of a memory device and storing the index value in a first register of the memory device. The first register may be implemented in a first clock domain, and the index value may identify a second register of the memory device implemented in a second clock domain. | 11-03-2011 |
20110271039 | APPARATUS AND METHOD FOR FLASH MEMORY ADDRESS TRANSLATION - Provided is a flash memory address translation method that may maintain at least one chip that may be divided based on at least one horizontal bank and at least one vertical channel, and may divide the at least one bank by at least one stripe partition, managing an error of a chip without deterioration in a performance of a small writing. | 11-03-2011 |
20110271040 | MEMORY SYSTEM HAVING NONVOLATILE SEMICONDUCTOR STORAGE DEVICES - According to an embodiment, a memory system includes a memory unit, a memory controller, a timer and a timer control unit. The memory unit has nonvolatile first and second chips capable of holding data. The memory controller transfers data received from host equipment simultaneously to the first and second chips. The timer measures a lapse of preset shift time. The timer control unit starts writing of data into the second chip immediately after the lapse of the shift time. | 11-03-2011 |
20110271041 | ELECTRONIC DEVICE COMPRISING FLASH MEMORY AND RELATED METHOD OF HANDLING PROGRAM FAILURES - A storage device performs a program operation to store program data in a selected memory block of a flash memory. The storage device allocates a reserved area of the flash memory as a free block upon detecting that a program failure has occurred in the program operation, reads the program data from a cache latch in a page buffer of the flash memory, copies valid data stored in the selected memory block to a first area of the free block, and reprograms the program data read from the cache latch to a second area of the free block. | 11-03-2011 |
20110271042 | METHOD FOR WRITING INTO AND READING FROM AN ATOMICITY MEMORY - A method for writing data into a reprogrammable non-volatile memory, wherein a marking pattern including several bits is added at the beginning of the data and the set formed of the marking pattern and of the data is written from an address in the memory varying from one write operation to another, the marking pattern being identical for each write operation. | 11-03-2011 |
20110271043 | SYSTEM AND METHOD FOR ALLOCATING AND USING SPARE BLOCKS IN A FLASH MEMORY - A method for using a single spare block pool in flash memory comprising: allocating a plurality of flash memory arrays, wherein each flash memory array comprises a plurality of flash memory blocks; within a main flash memory array: allocating a used block pool comprising a plurality of used blocks and allocating a main spare block pool comprising a plurality of spare blocks; within each of the other flash memory arrays: allocating a used block pool comprising multiple used blocks; allocating a minimum spare block pool comprising a minimum number of spare blocks; allocating the main spare block pool and each of the minimum spare block pools to a single spare block pool; transferring a spare block from the main spare block pool to one of the minimum spare block pools; and transferring a spare block from a first minimum spare block pool to a second minimum spare block pool. | 11-03-2011 |
20110271044 | MEMORY CARD HAVING ONE OR MORE SECURE ELEMENTS ACCESSED WITH HIDDEN COMMANDS - A memory card compatible token includes one or more secure elements accessed using secure element commands hidden in a memory card access command. A mobile computing device such as a mobile phone accesses the non-memory components by including a hidden command value as part of the memory card access command. Any set or subset of all possible secure element commands may be routed to one or more secure elements based on the hidden command value. | 11-03-2011 |
20110271045 | Controller for One Type of NAND Flash Memory for Emulating Another Type of NAND Flash Memory - A method of executing an erasing instruction to erase host data from a flash memory device is provided. The method initiates with receiving from a host device an erase instruction to erase host data from an array of NAND flash memory cells grouped into separately-erasable device blocks, each device block including multiple device pages, the host data being a portion of device data that is stored in a device block. The host data is marked as erased, and a message is sent to the host device indicating that the host data has been erased. | 11-03-2011 |
20110271046 | WEAR LEVELING FOR LOW-WEAR AREAS OF LOW-LATENCY RANDOM READ MEMORY - Described herein are method and apparatus for performing wear leveling of erase-units of an LLRRM device that considers all active erase-units. Wear counts of all active erase-units (containing client data) and free erase-units (not containing client data) are tracked. Wear counts are used to determine low-wear active erase-units having relatively low wear counts and high-wear free erase-units having relatively high wear counts. In some embodiments, data contents of low-wear active erase-units are transferred to high-wear free erase-units, whereby the low-wear active erase-units are converted to free erase-units and may later store different client data which may increase the current rate of wear for the erase-unit. The high-wear free erase-units are converted to active erase-units that store client data that is infrequently erased/written, which may reduce the current rate of wear for the erase-unit. As such, wear is spread more evenly among erase-units of the LLRRM device. | 11-03-2011 |
20110276744 | FLASH MEMORY CACHE INCLUDING FOR USE WITH PERSISTENT KEY-VALUE STORE - Described is using flash memory, RAM-based data structures and mechanisms to provide a flash store for caching data items (e.g., key-value pairs) in flash pages. A RAM-based index maps data items to flash pages, and a RAM-based write buffer maintains data items to be written to the flash store, e.g., when a full page can be written. A recycle mechanism makes used pages in the flash store available by destaging a data item to a hard disk or reinserting it into the write buffer, based on its access pattern. The flash store may be used in a data deduplication system, in which the data items comprise chunk-identifier, metadata pairs, in which each chunk-identifier corresponds to a hash of a chunk of data that indicates. The RAM and flash are accessed with the chunk-identifier (e.g., as a key) to determine whether a chunk is a new chunk or a duplicate. | 11-10-2011 |
20110276745 | TECHNIQUES FOR WRITING DATA TO DIFFERENT PORTIONS OF STORAGE DEVICES BASED ON WRITE FREQUENCY - Techniques for writing data to different portions of storage devices based on write frequencies are disclosed. Frequencies of data writes to various portions of a memory are monitored. The memory includes various storage technologies. Each portion includes one of the storage technologies and has a respective lifetime. An order that the portions are written into and recycled is dynamically managed to equalize respective life expectancies of the portions in view of differences in endurance values of the portions, the monitored frequencies of data writes, and the lifetimes. In some embodiments, the storage technologies include Single-Level Cell (SLC) flash memory storage technology and Multi-Level Cell (MLC) flash memory storage technology. The SLC and MLC flash memory storage technologies are optionally integrated in one device. In some embodiments, the storage technologies include two or more different types of SLC flash memory storage technologies, optionally integrated in one device. | 11-10-2011 |
20110276746 | CACHING STORAGE ADAPTER ARCHITECTURE - An interface adapter includes a storage module including non-volatile random access memory (RAM), and a lookup module. The storage module is configured to store metadata in the non-volatile RAM. The metadata identifies data from an external storage device cached in a solid-state storage device. The lookup module is configured to receive a read request. The lookup module is further configured to, based on the metadata and in response to the read request, selectively provide cached data from the solid-state storage device or provide second data retrieved from the external storage device. | 11-10-2011 |
20110276747 | SOFTWARE MANAGEMENT WITH HARDWARE TRAVERSAL OF FRAGMENTED LLR MEMORY - Certain aspects of the present disclosure relate to a method and apparatus for processing wireless communications. According to certain aspects, a linked list of chunks of memory used to store logarithmic likelihood ratio (LLR) values for a transport block is generated. Each chunk holds LLR values for a code block of the transport block. The linked list is then provided to a hardware circuit for traversal. According to certain aspects, the hardware circuit may be an application specific integrated circuit (ASIC) processor or field programmable gate array (FPGA) configured to traverse the linked list of chunks of memory used to store LLR values. | 11-10-2011 |
20110276748 | NON-VOLATILE STORAGE DEVICE, HOST DEVICE, STORAGE SYSTEM, DATA COMMUNICATION METHOD AND PROGRAM - In a memory system including a host device and one or more nonvolatile memory devices, the host device reads, from a nonvolatile memory device connected in the system, a boot code used to operate a CPU of the host device before the CPU is activated. The boot code reading process is required to be performed with a simple method. A host device ( | 11-10-2011 |
20110276749 | MULTI-BIT-PER-CELL FLASH MEMORY DEVICE WITH NON-BIJECTIVE MAPPING - To store a plurality of input bits, the bits are mapped to a corresponding programmed state of one or more memory cells and the cell(s) is/are programmed to that corresponding programmed state. The mapping may be many-to-one or may be an “into” generalized Gray mapping. The cell(s) is/are read to provide a read state value that is transformed into a plurality of output bits, for example by maximum likelihood decoding or by mapping the read state value into a plurality of soft bits and then decoding the soft bits. | 11-10-2011 |
20110276750 | APPARATUS AND METHOD FOR PROCESSING DATA OF FLASH MEMORY - An memory device including a data region storing a main data, a first index region storing a count data, and a second index region storing an inverted count data, where the data region, the first index region, and the second index region are included in one logical address. | 11-10-2011 |
20110283046 | STORAGE DEVICE - The present invention aims to improve the performance of accessing flash memory used as a storage medium in a storage device. In the storage device in accordance with the present invention, a storage controller, before accessing the flash memory, queries a flash controller as to whether the flash memory is accessible (see FIG. | 11-17-2011 |
20110283047 | HYBRID STORAGE SYSTEM FOR A MULTI-LEVEL RAID ARCHITECTURE - Embodiments of the present invention provide a hybrid storage system for a multi-level RAID architecture. Specifically, embodiments of this invention provide a hybrid RAID controller coupled to a system control board. Coupled to the hybrid RAID controller are a DDR RAID controller and a HDD/Flash RAID controller. A set of DDR RAID control blocks are coupled to the DDR RAID controller, each of the set of DDR RAID control blocks include a set of DDR memory disks. Further, a set of HDD RAID control blocks are coupled to the HDD/Flash RAID controller, each of the set of HDD RAID control blocks include a set of HDD/Flash SSD Units. | 11-17-2011 |
20110283048 | STRUCTURED MAPPING SYSTEM FOR A MEMORY DEVICE - This disclosure is related to systems and methods for a structured mapping system for a memory device, such as a solid state data storage device. In one example, a data storage device may include a multi-level address mapping system. The multi-level address mapping system may be implemented completely independent of a host computer and a host computer operating system. Also, the multi-level mapping system may be stored to allow each level, or subsets of each level, to be re-written independently of the other levels or the other subsets. | 11-17-2011 |
20110283049 | SYSTEM AND METHOD FOR MANAGING GARBAGE COLLECTION IN SOLID-STATE MEMORY - Embodiments of the invention are directed to optimizing the selection of memory blocks for garbage collection to maximize the amount of memory freed by garbage collection operations. The systems and methods disclosed herein provide for the efficient selection of optimal or near-optimal garbage collection candidate blocks, with the most optimal selection defined as block(s) with the most invalid pages. In one embodiment, a controller classifies memory blocks into various invalid block pools by the amount of invalid pages each block contains. When garbage collection is performed, the controller selects a block from a non-empty pool of blocks with the highest minimum amount of invalid pages. The pools facilitate the optimal or near-optimal selection of garbage collection candidate blocks in an efficient manner and the data structure of the pools can be implemented with bitmasks, which take minimal space in memory. | 11-17-2011 |
20110283050 | MEMORY BUFFER HAVING ACCESSIBLE INFORMATION AFTER A PROGRAM-FAIL - Subject matter disclosed herein relates to a memory device, and a method of operating same, including a memory buffer to maintain information to be available after a failure to program the information to a memory array. | 11-17-2011 |
20110283051 | MOVING EXECUTABLE CODE FROM A FIRST REGION OF A NON-VOLATILE MEMORY TO A SECOND REGION OF THE NON-VOLATILE MEMORY - A data storage device includes a controller and a non-volatile memory coupled to the controller. The non-volatile memory includes executable boot code that is executable by a processor associated with the data storage device. The controller is configured to read a first portion of the executable boot code from a first region of the non-volatile memory, and in response to detecting a condition, move a second portion of the executable boot code in a second region of the non-volatile memory to a third region of the non-volatile memory. | 11-17-2011 |
20110283052 | MEMORY CONTROLLER, FLASH MEMORY SYSTEM WITH MEMORY CONTROLLER, AND METHOD OF CONTROLLING FLASH MEMORY - The object of the present invention is to efficiently perform access to a physical block corresponding to a logical block often designated by an access request. To realize it, predetermined number of pieces of logical block information each for access to a physical block corresponding to logical block, until then, designated by an access request is held. In holding the predetermined pieces of logical block information, a piece of logical block information having high priority precede a piece of logical block information having low priority in priority order. In management of the priority order, priority of a piece of logical block information corresponding to a logical block often designated by an access request becomes high. When an access request is received, if logical block information corresponding to the logical block designated by the access request is held, access to the physical block corresponding to the designated logical block is performed based on the held logical block information. | 11-17-2011 |
20110283053 | SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR MEMORY SYSTEM - A semiconductor memory device that stores information includes: a flash memory that is managed by a predetermined file system having a parameter dependent on the semiconductor memory device; a rewrite frequency storage unit that stores a rewrite frequency of the flash memory; an ID detection unit that detects whether or not first identification information associated with the rewrite frequency is stored in the flash memory as the parameter; and a control unit that, when the ID detection unit detects that the first identification information is stored, reflects the rewrite frequency stored in the rewrite frequency storage unit, on a storage area corresponding to the first identification information. | 11-17-2011 |
20110283054 | NONVOLATILE MEMORY - For a nonvolatile memory permitting electrical writing and erasing of information to be stored, such as a flash memory, the load on the system developer is to be reduced, and it is to be made possible to avoid, even if such important data for the system as management and address translation information are damaged, an abnormal state in which the system becomes unable to operate. The nonvolatile memory is provided with a replacing function to replace a group of memory cells including defective memory cells which are incapable of normal writing or erasion with a group of memory cells including no defective memory cell, a numbers of rewrites averaging function to grasp the number of data rewrites in each group of memory cells and to so perform replacement of memory cell groups that there may arise no substantial difference in the number of rewrites among a plurality of memory cell groups, and an error correcting function to detect and correct any error in data stored in the memory array, wherein first address translation information deriving from the replacing function and second address translation information deriving from the numbers of rewrites averaging function are stored in respectively prescribed areas in the memory array, and the first address translation information and second address translation information concerning the same memory cell group are stored in a plurality of sets in a time series. | 11-17-2011 |
20110283055 | Exclusive-Option Chips and Methods with All-Options-Active Test Mode - A multi-interface integrated circuit in which, during the chip's lifetime in use, only one interface is active at a time. However, special test logic powers up all of the on-chip interface modules at once, so that a complete test cycle can be performed. All of the interfaces are exercised in one test program. Since some pads are inactive in some interface modes, mask bits are used to select which pads are monitored during which test cycles. | 11-17-2011 |
20110283056 | INFORMATION MANAGEMENT APPARATUS AND INFORMATION MANAGING METHOD - An information management apparatus for managing data includes a rewritable nonvolatile memory, and a memory controller configured to control inputting information into and outputting information from the nonvolatile memory. The memory controller overwrites a data, which includes a first validity check information, a first data body, a second validity check information, a second data body having the same data as the first data body and a third validity check information arranged in this order, in a designated address area in the nonvolatile memory when the memory controller performs a writing control in which the memory controller writes data in the nonvolatile memory. | 11-17-2011 |
20110283057 | Microcontroller Programmable System on a Chip - Embodiments of the present invention are directed to a microcontroller device having a microprocessor, programmable memory components, and programmable analog and digital blocks. The programmable analog and digital blocks are configurable based on programming information stored in the memory components. Programmable interconnect logic, also programmable from the memory components, is used to couple the programmable analog and digital blocks as needed. The advanced microcontroller design also includes programmable input/output blocks for coupling selected signals to external pins. The memory components also include user programs that the embedded microprocessor executes. These programs may include instructions for programming the digital and analog blocks “on-the-fly,” e.g., dynamically. In one implementation, there are a plurality of programmable digital blocks and a plurality of programmable analog blocks. | 11-17-2011 |
20110283058 | STORAGE APPARATUS AND METHOD OF MANAGING DATA STORAGE AREA - To extend endurance and reduce bit cost, a method and a storage apparatus are provided, which storage apparatus includes a controller and a semiconductor storage media that includes a first storage device and a second storage device having an upper limit of an erase count of data smaller than the first storage device. Area conversion information includes correspondence of a first address to be specified as a data storage destination and a second address of an area in which data is to be stored. A rewrite frequency of stored data is recorded for each area. The controller selects an area corresponding to the first address, determines whether or not the rewrite frequency of the selected area is equal to or larger than a first threshold value, when the rewrite frequency is equal to or larger than the threshold value, selects an area to be provided by the first storage device, and when the rewrite frequency is smaller than the threshold value, selects an area to be provided by the second storage device and maps the address of the selected area to the first address. | 11-17-2011 |
20110289259 | MEMORY SYSTEM CAPABLE OF ENHANCING WRITING PROTECTION AND RELATED METHOD - A memory system is disclosed. The memory system includes a memory device, a first control unit, and a second control unit. The memory device is utilized for storing data. The first control unit is coupled to the memory device for prohibiting a data writing process performed on the memory device during a writing protection period. The second control unit is coupled to the memory device for allowing the data writing process to be performed in the memory device according to a writing period after the writing protection period, wherein the writing period is related to the data writing process. | 11-24-2011 |
20110289260 | METHOD FOR PERFORMING BLOCK MANAGEMENT USING DYNAMIC THRESHOLD, AND ASSOCIATED MEMORY DEVICE AND CONTROLLER THEREOF - A method for performing block management is provided. The method is applied to a controller of a Flash memory, where the Flash memory includes a plurality of blocks. The method includes: adjusting a dynamic threshold according to at least one condition; and comparing a valid/invalid page count of a specific block of the plurality of blocks with the dynamic threshold to determine whether to erase the specific block. An associated memory device and a controller thereof are also provided, where the memory device includes the Flash memory and the controller. In particular, the controller includes a read only memory (ROM) arranged to store a program code, and further includes a microprocessor arranged to execute the program code to control access to the Flash memory and manage the plurality of blocks, where under control of the microprocessor, the controller operates according to the method. | 11-24-2011 |
20110289261 | METHOD AND SYSTEM FOR A STORAGE AREA NETWORK - In a system and method for a storage area network (SAN), a first controller receives a write request for a SAN an communicates with a first nested storage array module (NSAM), the first NSAM manages storage of data onto a shelf and presents the shelf as a logical unit, a buffer stores a portion of a write request from the first controller and aggregates data from the write request for the shelf, from a shelf with a second NSAM, the second NSAM provides a portion of data from the buffer to a third NSAM, the third NSAM manages storage of the portion of data from the buffer to a physical storage unit, and a second controller coupled to the first controller handles requests for the SAN in response to a failure of the first controller. | 11-24-2011 |
20110289262 | CONTROLLER FOR SOLID STATE DISK, WHICH CONTROLS SIMULTANEOUS SWITCHING OF PADS - Provided is a controller for a solid state disk, to control simultaneous switching of pads. The controller for the solid state disk may control simultaneous switching of a plurality of output pads or a plurality of input pads that correspond to a plurality of channels. In particular, the controller may properly delay signals driven to the output pads or input pads, to reduce power supplied to the pads, and to prevent ground bouncing, as well as, maintain a quality of signals. | 11-24-2011 |
20110289263 | SYSTEM INCLUDING A FINE-GRAINED MEMORY AND A LESS-FINE-GRAINED MEMORY - A data processing system includes one or more nodes, each node including a memory sub-system. The sub-system includes a fine-grained, memory, and a less-fine-grained (e.g., page-based) memory. The fine-grained memory optionally serves as a cache and/or as a write buffer for the page-based memory. Software executing on the system uses a node address space which enables access to the page-based memories of all nodes. Each node optionally provides ACID memory properties for at least a portion of the space. In at least a portion of the space, memory elements are mapped to locations in the page-based memory. In various embodiments, some of the elements are compressed, the compressed elements are packed into pages, the pages are written into available locations in the page-based memory, and a map maintains an association between the some of the elements and the locations. | 11-24-2011 |
20110289264 | Memory System Having Nonvolatile and Buffer Memories, and Reading Method Thereof - Disclosed is a method for reading data in a memory system including a buffer memory and a nonvolatile memory, the method being comprised of: determining whether an input address in a read request is allocated to the buffer memory; determining whether a size of requested data is larger than a reference unless the input address is allocated to the buffer memory; and conducting a prefetch reading operation from the nonvolatile memory if the requested data size is larger than the reference. | 11-24-2011 |
20110289265 | STORAGE SYSTEM AND STORAGE MANAGEMENT METHOD FOR CONTROLLING OFF-LINE MODE AND ON-LINE OF FLASH MEMORY - An object of the present invention is to provide a storage system and storage management method, which prevent a problem in the operation of stored data from being caused by unknown states of volume information and life information, when flash memories are placed in off-line mode and again placed in on-line mode. According to the present invention, there is provided a storage system | 11-24-2011 |
20110289266 | GARBAGE COLLECTION IN STORAGE DEVICES BASED ON FLASH MEMORIES - A solution for managing a storage device based on a flash memory is proposed. A corresponding method starts with the step for mapping a logical memory space of the storage device (including a plurality of logical blocks) on a physical memory space of the flash memory (including a plurality of physical blocks, which are adapted to be erased individually). The physical blocks include a set of first physical blocks (corresponding to the logical blocks) and a set of second—or spare—physical blocks (for replacing each bad physical block that is unusable). The method continues by detecting each bad physical block. Each bad physical block is then discarded, so to prevent using the bad physical block for mapping the logical memory space. | 11-24-2011 |
20110289267 | APPARATUS, SYSTEM, AND METHOD FOR SOLID-STATE STORAGE AS CACHE FOR HIGH-CAPACITY, NON-VOLATILE STORAGE - An apparatus, system, and method are disclosed for solid-state storage as cache for high-capacity, non-volatile storage. The apparatus, system, and method are provided with a plurality of modules including a cache front-end module and a cache back-end module. The cache front-end module manages data transfers associated with a storage request. The data transfers between a requesting device and solid-state storage function as cache for one or more HCNV storage devices, and the data transfers may include one or more of data, metadata, and metadata indexes. The solid-state storage may include an array of non-volatile, solid-state data storage elements. The cache back-end module manages data transfers between the solid-state storage and the one or more HCNV storage devices. | 11-24-2011 |
20110296079 | System and Method for Emulating Preconditioning of Solid-State Device - Systems and methods for reducing problems and disadvantages associated with traditional approaches to preconditioning solid-state devices are provided. A method may include storing at least one preconditioning status parameter indicative of at least one variable associated with preconditioning emulation of a solid state device (SSD) including a flash memory. The method may also include modifying a mapping table based on the at least one preconditioning status parameter to emulate preconditioning of the SSD, the mapping table including information for translating virtual logical block addresses (LBAs) of the SSD as seen by the processor into physical LBAs of the flash memory. | 12-01-2011 |
20110296080 | Method Of Writing To A NAND Memory Block Based File System With Log Based Buffering - A method of operating a controller for controlling the programming of a NAND memory chip is shown. The NAND memory chip has a plurality of blocks with each block having a certain amount of storage, wherein the amount of storage in each block is the minimum erasable unit. The method comprising storing in a temporary storage a first plurality of groups of data, wherein each of the groups of data is to be stored in a block of the NAND memory chip. Each group of data is indexed to the block with which it is to be stored. Finally, the groups of data associated with the same block are programmed into the same block in the same programming operation. | 12-01-2011 |
20110296081 | DATA ACCESSING METHOD AND RELATED CONTROL SYSTEM - A data access method and a related control system are provided according to embodiments of the present invention, which enhances the read/write performance of a data storage unit by performing pre-accessing operations upon the data storage unit. The data access method includes receiving a plurality of access requests and a plurality of corresponding addresses to access a plurality of data corresponding to the plurality of access requests from a storage unit; and performing a pre-accessing operation upon the storage unit according to the uniformity of the plurality of access requests and the continuity between the plurality of addresses. | 12-01-2011 |
20110296082 | Method for Improving Service Life of Flash - A method for increasing service life of flash is provided. The method comprises the following steps: reading a data {T} from the flash, calculating and obtaining the corresponding old original data Bi according to the mapping relationship, wherein i is a natural number, j=(n−1)˜0, n is an even number; determining whether the data Bi to be written in is the same as the old original data Bi by comparison, if they are the same, it is not necessary to update the data of this byte in the flash; if the value of the data Bi to be written in is not the same as the value of the old original data Bi, checking whether it is possible to write into the flash directly; if possible, writing into the flash directly; and if it is impossible to write into the flash directly, performing the operation of erasing block. | 12-01-2011 |
20110296083 | DATA STORAGE APPARATUS AND METHOD OF CALIBRATING MEMORY - According to one embodiment, a data storage apparatus includes an interface module and a controller. The interface module is configured to control rewritable nonvolatile memories provided for the respective channels. The controller is configured to write calibration data to the nonvolatile memories of any channel designated, through the interface module at the same time, in order to perform calibration. | 12-01-2011 |
20110296084 | DATA STORAGE APPARATUS AND METHOD OF WRITING DATA - According to one embodiment, a data storage apparatus includes a flash memory and a controller for controlling the flash memory. The flash memory is configured to store data is written in units of a prescribed size. In order to write data smaller than the prescribe size, the controller first isolates attribute data from each save data item of the prescribed size, which has been read from any flash memory, and then stores the attribute data to an attribute data memory, and finally transfers the user data contained in the save data, to a save data memory. | 12-01-2011 |
20110296085 | CACHE MEMORY MANAGEMENT IN A FLASH CACHE ARCHITECTURE - Provided are a system, method, and computer program product for managing cache memory to cache data units in at least one storage device. A cache controller is coupled to at least two flash bricks, each comprising a flash memory. Metadata indicates a mapping of the data units to the flash bricks caching the data units, wherein the metadata is used to determine the flash bricks on which the cache controller caches received data units. The metadata is updated to indicate the flash brick having the flash memory on which data units are cached. | 12-01-2011 |
20110296086 | FLASH MEMORY HAVING TEST MODE FUNCTION AND CONNECTION TEST METHOD FOR FLASH MEMORY - A flash memory including a controller, the controller including: a state machine; a state decoder that determines whether a state of the state machine is in a specified mode; a command decoder that determines whether an input signal received through an external pin specifies a write operation for writing a specific value into a specific address; and a test mode setting circuit that sets a test mode while the specified mode is maintained when the state decoder determines that the state of the state machine is in the specified mode and when the command decoder determines that the input signal received through the external pin specifies a write operation for writing a specific value into a specific address. | 12-01-2011 |
20110296087 | METHOD OF MERGING BLOCKS IN A SEMICONDUCTOR MEMORY DEVICE, AND SEMICONDUCTOR MEMORY DEVICE TO PERFORM A METHOD OF MERGING BLOCKS - In a method of merging blocks in a semiconductor memory device according to example embodiments, a plurality of data are written into one or more first blocks using a first program method. One or more merge target blocks that are required to be merged are selected among the one or more first blocks. A merge-performing block for a block merge operation is selected among the one or more first blocks and one or more second blocks. A plurality of merge target data are written from the merge target blocks into the merge-performing block using a second program method that is different from the first program method. | 12-01-2011 |
20110296088 | MEMORY MANAGEMENT STORAGE TO A HOST DEVICE - Systems and methods of memory management storage to a host device are disclosed. A method is performed in a data storage device with a non-volatile memory and a controller operative to manage the non-volatile memory and to generate management data for managing the non-volatile memory. The method includes performing, at a given time, originating at the controller data management transfer to a host device or originating at the controller data management retrieval from the host device. | 12-01-2011 |
20110296089 | PROGRAMMING METHOD AND DEVICE FOR A BUFFER CACHE IN A SOLID-STATE DISK SYSTEM - Provided are a method and apparatus for programming a buffer cache in a Solid State Disk (SSD) system. The buffer cache programming apparatus in the SSD system may include a buffer cache unit to store pages, a memory unit including a plurality of memory chips, and a control unit to select at least one of the page as a victim page, based on a delay occurring when a page is stored in at least one target memory chip among the plurality of memory chips. | 12-01-2011 |
20110296090 | Combining Memory Operations - Systems and processes may include a memory coupled to a memory controller. Command signals for performing memory access operations may be received. Attributes of the command signals, such as type, time lapsed since receipt, and relatedness to other command signals, may be determined. Command signals may be sequenced in a sequence of execution based on the attributes. Command signals may be executed in the sequence of execution. | 12-01-2011 |
20110296091 | STORAGE SYSTEM WHICH UTILIZES TWO KINDS OF MEMORY DEVICES AS ITS CACHE MEMORY AND METHOD OF CONTROLLING THE STORAGE SYSTEM - Provide is a storage system including one or more disk drives, and one or more cache memories for temporarily storing data read from the disk drives or data to be written to the disk drives, in which: the cache memories includes volatile first memories and non-volatile second memories; and the storage system receives a data write request, stores the requested data in the volatile first memories, selects one of memory areas of the volatile first memories if a total capacity of free memory areas contained in the volatile first memories is less than a predetermined threshold, write data stored in the selected memory area in the non-volatile second memories, and changes the selected memory area to a free memory area. Accordingly, there can be realized capacity enlarging of the cache memory using a non-volatile memory device while realizing a high speed similar to that of a volatile memory device. | 12-01-2011 |
20110296092 | Storing a Driver for Controlling a Memory - Systems and techniques for accessing a memory, such as a NAND or NOR flash memory, involve storing an operating application for a computing device in a first memory and storing a driver containing software operable to control the first memory in a second memory that is independently accessible from the first memory. By storing the driver in a second memory that is independently accessible from the first memory, changes to the driver and/or the first memory can be made without altering the operating application. | 12-01-2011 |
20110296093 | PROGRAM AND SENSE OPERATIONS IN A NON-VOLATILE MEMORY DEVICE - Methods for programming and sensing in a memory device, a data cache, and a memory device are disclosed. In one such method, all of the bit lines of a memory block are programmed or sensed during the same program or sense operation by alternately multiplexing the odd or even page bit lines to the dynamic data cache. The dynamic data cache comprises dual SDC, PDC, DDC1, and DDC2 circuits such that one set of circuits is coupled to the odd page bit lines and the other set of circuits is coupled to the even page bit lines. | 12-01-2011 |
20110296094 | CIRCULAR WEAR LEVELING - A method for flash memory management comprises providing a head pointer configured to define a first location in a flash memory, and a tail pointer configured to define a second location in a flash memory. The head pointer and tail pointer define a payload data area. Payload data is received from a host, and written to the flash memory in the order it was received. The head pointer and tail pointer are updated such that the payload data area moves in a circular manner within the flash memory. | 12-01-2011 |
20110302353 | NON-VOLATILE MEMORY WITH EXTENDED OPERATING TEMPERATURE RANGE - A method and apparatus are described for measuring a temperature within a non-volatile memory and refreshing at least a portion of the non-volatile memory when the temperature exceeds a threshold temperature for an amount of time. | 12-08-2011 |
20110302354 | SYSTEMS AND METHODS FOR RELIABLE MULTI-LEVEL CELL FLASH STORAGE - Multi-level cell (MLC) flash memory has become widely used due to their capacity to store more information in the same area as a single-level cell (SLC) flash memory. This makes MLC flash memory very attractive for storing media. Flash has also traditionally been used in electronic devices for firmware, but MLC flash is less reliable than SLC flash. For critical memory operations, MLC flash memory can be made as reliable as SLC flash by mapping one binary value to an MLC state corresponding to the highest threshold voltage and the other binary value to the MLC state corresponding the lowest threshold voltage when writing to the MLC flash, and by mapping all MLC states with corresponding threshold voltages above a central cutoff threshold voltage to one binary value and by mapping all MLC states with corresponding threshold voltages below a central cutoff threshold voltage to the other binary value. | 12-08-2011 |
20110302355 | MAPPING AND WRITTING METHOD IN MEMORY DEVICE WITH MULTIPLE MEMORY CHIPS - The invention is directed to a mapping method in a memory device with a plurality of memory chips in a sequence of 0 to K, K≧1. Each of the memory chips has a plurality of data blocks. The mapping method includes setting a block sequence number “(K+1)*n” to the (n+1) | 12-08-2011 |
20110302356 | SCALABLE MEMORY INTERFACE SYSTEM - A memory interface system can include a memory controller configured to operate at a first operating frequency. A physical interface block can be coupled to the memory controller. The physical interface block can be configured to communicate with the memory controller at the first operating frequency and communicate with a memory device at a second operating frequency that is independent of the first operating frequency. | 12-08-2011 |
20110302357 | SYSTEMS AND METHODS FOR DYNAMIC MULTI-LINK COMPILATION PARTITIONING - Systems and methods for dynamic multi-link compilation partitioning. In particular, some implementations of the present invention relate to systems and methods for connecting a computer processing unit to a video display through the use of a wide variety of video display connectors. The present invention further relates to a dynamic interface incorporating USB, PCI-express, SATA, I | 12-08-2011 |
20110302358 | Flash-Memory Device with RAID-type Controller - A smart flash drive has one or more levels of smart storage switches and a lower level of single-chip flash devices (SCFD's). A SCFD contains flash memory and controllers that perform low-level bad-block mapping and wear-leveling and logical-to-physical block mapping. The SCFD report their capacity, arrangement, and maximum wear-level count (WLC) and bad block number (BBN) to the upstream smart storage switch, which stores this information in a structure register. The smart storage switch selects the SCFD with the maximum BBN as the target and the SCFD with the lowest maximum WLC as the source of a swap for wear leveling when a WLC exceeds a threshold that rises over time. A top-level smart storage switch receives consolidated capacity, arrangement, WLC, and BBN information from lower-level smart storage switch. Data is striped and optionally scrambled by Redundant Array of Individual Disks (RAID) controllers in all levels of smart storage switches. | 12-08-2011 |
20110302359 | METHOD FOR MANAGING FLASH MEMORIES HAVING MIXED MEMORY TYPES - A method manages a flash memory having a plurality of physical blocks. The blocks of the memory are addressed by logic block addresses which are converted into physical block addresses. In each block a deletion counter is run in which the number of deletions of the block is counted, and two regions having different types of flash chips are present. A first region contains single-level flash chips with a large maximum deletion frequency, and a second region contains multi-level flash chips with a lower maximum deletion frequency. When writing to the memory the address conversion of the logic addresses into physical addresses is carried out such that all blocks of the first region are written, when all blocks of the first region have been written and a further writing process is initiated, the block in the first region having the lowest deletion counter is copied into a blank block in the second region. | 12-08-2011 |
20110302360 | METHODS AND APPARATUS FOR REALLOCATING ADDRESSABLE SPACES WITHIN MEMORY DEVICES - Integrated circuit systems include a non-volatile memory device (e.g, flash EEPROM device) and a memory processing circuit. The memory processing circuit is electrically coupled to the non-volatile memory device. The memory processing circuit is configured to reallocate addressable space within the non-volatile memory device. This reallocation is performed by increasing a number of physical addresses within the non-volatile memory device that are reserved as redundant memory addresses, in response to a capacity adjust command received by the memory processing circuit. | 12-08-2011 |
20110302361 | MEMORY SYSTEM AND METHOD OF CONTROLLING MEMORY SYSTEM - A plurality of free-block management lists for respectively managing a logical block with a same bank number, a same chip number, and a same plane number as a free block, and a free block selecting unit that selects a required number of free-block management lists from the free-block management lists to obtain a free block from the selected free-block management lists are provided, thereby improving writing efficiency. | 12-08-2011 |
20110302362 | SYSTEM AND METHOD OF CACHING INFORMATION - A system and method is provided wherein, in one aspect, a currently-requested item of information is stored in a cache based on whether it has been previously requested and, if so, the time of the previous request. If the item has not been previously requested, it may not be stored in the cache. If the subject item has been previously requested, it may or may not be cached based on a comparison of durations, namely (1) the duration of time between the current request and the previous request for the subject item and (2) for each other item in the cache, the duration of time between the current request and the previous request for the other item. If the duration associated with the subject item is less than the duration of another item in the cache, the subject item may be stored in the cache. | 12-08-2011 |
20110302363 | NON-VOLATILE MEMORIES, CARDS, AND SYSTEMS INCLUDING SHALLOW TRENCH ISOLATION STRUCTURES WITH BURIED BIT LINES - A non-volatile memory device can include a buried bit line in a substrate of a non-volatile memory device and a self-aligned shallow trench isolation region in the substrate that is self-aligned to the buried bit line. | 12-08-2011 |
20110302364 | DATA WRITING METHOD FOR NON-VOLATILE MEMORY AND CONTROLLER USING THE SAME - A data writing method for a non-volatile memory is provided, wherein the non-volatile memory includes a data area and a spare area. In the data writing method, a plurality of blocks in a substitution area of the non-volatile memory is respectively used for substituting a plurality of blocks in the data area, wherein data to be written into the blocks in the data area is written into the blocks in the substitution area, and the blocks in the substitution area are selected from the spare area of the non-volatile memory. A plurality of temporary blocks of the non-volatile memory is used as a temporary area of the blocks in the substitution area, wherein the temporary area is used for temporarily storing the data to be written into the blocks in the substitution area. | 12-08-2011 |
20110307644 | SWITCH-BASED HYBRID STORAGE SYSTEM - The present invention relates to semiconductor storage systems (SSDs). Specifically, the present invention relates to a switch-based hybrid storage system. In a typical embodiment, a first RAID controller is coupled to a system control board, and a double data rate semiconductor storage device (DDR SSD) module is coupled to the first RAID controller. The DDR SSD module typically includes a set of DDR SSD units. Also coupled to the system control board are a first switch and a second switch. A second RAID controller is coupled to the first switch, while a hard disk drive (HDD) module coupled to the second RAID controller. The HDD module typically includes a set of HDD/Flash SDD units. Also coupled to the second switch is a communications module having a set (at least one) of ports. | 12-15-2011 |
20110307645 | IMPLEMENTING ENHANCED HOST TO PHYSICAL STORAGE MAPPING USING NUMERICAL COMPOSITIONS FOR PERSISTENT MEDIA - A method and a storage system are provided for implementing host to physical mapping for persistent media including flash memory. Numerical compositions at multiple granularities are used to store the host to physical mappings. A plurality of groupings, each grouping including a fixed number of blocks is encoded using recursive composition, eliminating the need to store separate lengths. | 12-15-2011 |
20110307646 | Memory system and method of accessing a semiconductor memory device - A memory system is provided with a processor, a main memory, and a flash memory. Performance of the memory system is improved through achievement of speed-up and high data reliability. The memory system includes a nonvolatile memory device and a controller configured to drive a control program to control the nonvolatile memory device. The control program executes a second access operation for the nonvolatile memory device even before a first access operation to the nonvolatile memory device is completed. | 12-15-2011 |
20110307647 | SYSTEMS AND METHODS FOR RAPID PROCESSING AND STORAGE OF DATA - Systems and methods of building massively parallel computing systems using low power computing complexes in accordance with embodiments of the invention are disclosed. A massively parallel computing system in accordance with one embodiment of the invention includes at least one Solid State Blade configured to communicate via a high performance network fabric. In addition, each Solid State Blade includes a processor configured to communicate with a plurality of low power computing complexes interconnected by a router, and each low power computing complex includes at least one general processing core, an accelerator, an I/O interface, and cache memory and is configured to communicate with non-volatile solid state memory. | 12-15-2011 |
20110307648 | Map Data Product, Map Data Processing Program Product, Map Data Processing Method and Map Data Processing Device - A first data product that can be read into a computer or a map data processing apparatus, contains therein map data having map-related information of a map. The map data includes: a structure having the map-related information divided into units of a plurality of divisions into which the map is divided; and a structure having management information for the map-related information divided into units of the divisions, and: the map-related information obtained by the computer or the map data processing apparatus can be updated in units of the individual divisions by using the management information. | 12-15-2011 |
20110307649 | MULTIPLE LEVEL CELL MEMORY DEVICE WITH SINGLE BIT PER CELL, RE-MAPPABLE MEMORY BLOCK - A system having a non-volatile memory device has a plurality of memory cells that are organized into memory blocks. Blocks can operate in either a multiple bit per cell mode or a single bit per cell mode. A processor controls the system and selects blocks to operate in the multiple bit per cell mode and single bit per cell mode. One dedicated memory block is capable of operating only in the single bit per cell mode. If the dedicated memory block is found to be defective, a defect-free block can be remapped to that dedicated memory block location to act only in the single bit per cell mode. | 12-15-2011 |
20110307650 | Method for Securing Electronic Device Data Processing - A method for securing electronic device processes against attacks (e.g. side channel attacks) during the processing of sensitive and/or confidential data by a Central Processing Unit (CPU) to the volatile memory (e.g. RAM) of an electronic device such as, for example, a smart card, a PDA or a cellular phone is described herein. The method involves the storage of the confidential data to a dynamically and randomly assigned memory location, thereby rendering more difficult the analysis and subsequently the attacks (e.g. side channel attacks). | 12-15-2011 |
20110307651 | ROBUST INDEX STORAGE FOR NON-VOLATILE MEMORY - A non-volatile memory data address translation scheme is described that utilizes a hierarchal address translation system that is stored in the non-volatile memory itself. Embodiments of the present invention utilize a hierarchal address data and translation system wherein the address translation data entries are stored in one or more data structures/tables in the hierarchy, one or more of which can be updated in-place multiple times without having to overwrite data. This hierarchal address translation data structure and multiple update of data entries in the individual tables/data structures allow the hierarchal address translation data structure to be efficiently stored in a non-volatile memory array without markedly inducing write fatigue or adversely affecting the lifetime of the part. The hierarchal address translation of embodiments of the present invention also allow for an address translation layer that does not have to be resident in system RAM for operation. | 12-15-2011 |
20110314204 | SEMICONDUCTOR STORAGE DEVICE, CONTROL METHOD THEREOF, AND INFORMATION PROCESSING APPARATUS - According to the embodiments, a first storing unit as a cache, second and third storing units included in a nonvolatile semiconductor memories, and a controller are included, in which the controller includes an organizing unit that increases a resource by organizing data in the nonvolatile semiconductor memories, and an organizing-state notifying unit that, when an organizing-state notification request is input from a host, outputs an organizing state by the organizing unit to the host as an organizing-state notification, thereby improving a command response speed and the writing efficiency. | 12-22-2011 |
20110314205 | STORAGE SYSTEM - A storage system includes a first storage device, and a second storage device retrieving stored data at higher speeds than the first storage device. The storage system further includes a feature calculation unit calculating feature data based on a data content of storage target data, a data management unit storing the storage target data and managing a storing position thereof based on the feature data calculated from the storage target data, and a duplication determination unit determining whether or not the same storage target data as the storage target data to be newly stored is already stored in the first storage device. In a case that the same storage target data as the storage target data to be newly stored is already stored in the first storage device, the data management unit stores the storage target data already stored in the first storage device into the second device. | 12-22-2011 |
20110314206 | APPARATUS AND METHOD FOR USING A PAGE BUFFER OF A MEMORY DEVICE AS A TEMPORARY CACHE - An apparatus and method are provided for using a page buffer of a memory device as a temporary cache for data. A memory controller writes data to the page buffer and later reads out the data without programming the data into the memory cells of the memory device. This allows the memory controller to use the page buffer as temporary cache so that the data does not have to occupy space within the memory controller's local data storage elements. Therefore, the memory controller can use the space in its own storage elements for other operations. | 12-22-2011 |
20110314207 | MEMORY SYSTEM, PROGRAM METHOD THEREOF, AND COMPUTING SYSTEM INCLUDING THE SAME - Disclosed is a memory system and a method of programming a multi-bit flash memory device which includes memory cells configured to store multi-bit data, where the method includes and the system is configured for determining whether data to be stored in a selected memory cell is an LSB data; and if data to be stored in a selected memory cell is not an LSB data, backing up lower data stored in the selected memory cell to a backup memory block of the multi-bit flash memory device. | 12-22-2011 |
20110314208 | CONTENT-AWARE DIGITAL MEDIA STORAGE DEVICE AND METHODS OF USING THE SAME - A content-aware digital media storage device includes a host device interface for exchanging digital information with a host device, a memory array for storing digital information received from the host device via the host interface, a peripheral module configured to communicate the digital information stored in the memory array to a receiver located remote from the digital media storage device, and a controller communicatively coupled to the host device interface, the memory array and the peripheral module and configured to interpret directory information associated with the digital information stored in the memory array so as to selectively access said digital information and communicate such accessed digital information to the peripheral module for transmission to the remote receiver. Digital images stored in the memory array may be transmitted to a remote host via a wireless network access point with which the peripheral module of the storage device is associated. | 12-22-2011 |
20110320684 | Techniques of Maintaining Logical to Physical Mapping Information in Non-Volatile Memory Systems - A non-volatile memory system writes logical to physical conversion data to the same memory blocks as user data, and as part of the same page as a segment of user data, as data segments are received and written. When a data block is subsequently compacted and obsolete data removed, the user data from the block is written to a one block and some or all of the logical to physical conversion data from the block is written to another block dedicated for the storage of such logical to physical mapping data. | 12-29-2011 |
20110320685 | Use of Guard Bands and Phased Maintenance Operations to Avoid Exceeding Maximum Latency Requirements in Non-Volatile Memory Systems - Techniques are presented for performing maintenance operations, such as garbage collection, on non-volatile memory systems will still respecting the maximum latency, or time-out, requirements of a protocol. A safety guard band in the space available for storing host data, control data, or both, is provided. If, on an access of the memory, it is determined that the guard band space is exceeded, the system uses a recovery back to the base state by triggering and prioritising clean-up operations to re-establish all safety guard bands without breaking the timing requirements. To respect these timing requirements, the operations are split into portions and done in a phased manner during allowed latency periods. | 12-29-2011 |
20110320686 | FRDY PULL-UP RESISTOR ACTIVATION - A method and apparatus for reducing power consumption during an operation in a non-volatile storage device is disclosed. A non-volatile storage device controller that is in communication with a non-volatile memory in the non-volatile storage device receives a characteristic corresponding to a time duration required for the non-volatile memory to complete an operation. The controller disables a circuit that indicates when an operation by the non-volatile memory is complete. The controller then initiates the operation in the non-volatile memory, and maintains the circuit in a disabled state for a first predetermined time that is a portion of the time duration. The controller enables the circuit upon expiration of the first predetermined time and prior to the completion of the operation. The controller receives an indication of the completion of the operation via the circuit. | 12-29-2011 |
20110320687 | REDUCING WRITE AMPLIFICATION IN A CACHE WITH FLASH MEMORY USED AS A WRITE CACHE - Embodiments of the invention are directed to reducing write amplification in a cache with flash memory used as a write cache. An embodiment of the invention includes partitioning at least one flash memory device in the cache into a plurality of logical partitions. Each of the plurality of logical partitions is a logical subdivision of one of the at least one flash memory device and comprises a plurality of memory pages. Data are buffered in a buffer. The data includes data to be cached, and data to be destaged from the cache to a storage subsystem. Data to be cached are written from the buffer to the at least one flash memory device. A processor coupled to the buffer is provided with access to the data written to the at least one flash memory device from the buffer, and a location of the data written to the at least one flash memory device within the plurality of logical partitions. The data written to the at least one flash memory device are destaged from the buffer to the storage subsystem. | 12-29-2011 |
20110320688 | Memory Systems And Wear Leveling Methods - Wear leveling methods in memory systems with nonvolatile memory devices including a plurality of physical blocks and memory controllers controlling the nonvolatile memory devices. The wear leveling method increases a stress index of the physical blocks according to operations the physical blocks have undergone and performs wear leveling of the physical block on the basis of the stress index. | 12-29-2011 |
20110320689 | Data Storage Devices and Data Management Methods for Processing Mapping Tables - Methods of operating integrated circuit devices include updating a mapping table with physical address information by reading forward link information from a plurality of spare sectors in a corresponding plurality of pages within a nonvolatile memory device and then writing mapping table information derived from the forward link information into the mapping table. This forward link information may be configured as absolute address information (e.g., next physical address) and/or relative address information (e.g., change in physical address). This updating of the mapping table may include updating a mapping table within a volatile memory, in response to a resumption of power within the integrated circuit device. This resumption of power may follow a power failure during which the contents of the volatile memory are lost. | 12-29-2011 |
20110320690 | MASS STORAGE SYSTEM AND METHOD USING HARD DISK AND SOLID-STATE MEDIA - Methods and systems for mass storage of data over two or more tiers of mass storage media that include nonvolatile solid-state memory devices, hard disk devices, and optionally volatile memory devices or nonvolatile MRAM in an SDRAM configuration. The mass storage media interface with a host through one or more PCIe lanes on a single printed circuit board. | 12-29-2011 |
20110320691 | MEMORY SYSTEM, MULTI-BIT FLASH MEMORY DEVICE, AND ASSOCIATED METHODS - A memory system includes a multi-bit flash memory device and a flash controller configured to control the multi-bit flash memory device. The flash controller is configured to output a series of commands, pointers, and addresses to the multi-bit flash memory device for read/program operations. | 12-29-2011 |
20110320692 | ACCESS DEVICE, INFORMATION RECORDING DEVICE, CONTROLLER, REAL TIME INFORMATION RECORDING SYSTEM, ACCESS METHOD, AND PROGRAM - Provided is a method for stabilizing and increasing the speed of processing for writing a plurality of different-sized files such as a video file and a management file in parallel in the case where the area in a non-volatile memory of an information recording module is managed by a file system. An access module ( | 12-29-2011 |
20120005402 | STORAGE SYSTEM HAVING A PLURALITY OF FLASH PACKAGES - A storage system | 01-05-2012 |
20120005403 | RECOVERY SCHEME FOR AN EMULATED MEMORY SYSTEM - In a system having an emulation memory having a first sector of non-volatile memory for storing information, wherein the non-volatile memory includes a plurality of records, a method includes determining if a last record written of the plurality of records is a compromised record; if the last record written is not a compromised record, performing a next write to a record of the plurality of records that is next to the last record written; and if the last record written is a comprised record: determining an address of the compromised record; writing valid data for the address of the compromised record into the record of the plurality of records that is next to the compromised record; and writing data into a record that is next to the record of the plurality of records that is next to the compromised record. | 01-05-2012 |
20120005404 | STATUS INDICATION WHEN A MAINTENANCE OPERATION IS TO BE PERFORMED AT A MEMORY DEVICE - Data storage devices and methods are disclosed that provide a status indication when a maintenance operation is to be performed prior to completion of a write command. A method includes receiving a write command from a host device to write data to the non-volatile memory while the data storage device is operatively coupled to the host device. In response to determining that a maintenance operation is to be performed prior to the completion of the write command, an indication is sent to the host device that the write command has a status of incomplete. | 01-05-2012 |
20120005405 | Pre-Emptive Garbage Collection of Memory Blocks - A method and system pre-emptively perform garbage collection operations of a forced amount on update blocks in a memory device. The amount of garbage collection needed by a certain data write is monitored and adjusted to match the forced amount if necessary. Update blocks may be selected on the basis of their recent usage or the amount of garbage collection required. Another method and system may store control information about update blocks in a temporary storage area so that a greater number of update blocks are utilized. The sequential write performance measured by the Speed Class test may be optimized by using this method and system. | 01-05-2012 |
20120005406 | Garbage Collection of Memory Blocks Using Volatile Memory - A method and system for performing garbage collection operations on update blocks in a memory device using volatile memory is disclosed. When performing a garbage collection operation, a first part of the data related to the garbage collection operation is written to a volatile memory in the memory device, and a second part of the data related to the garbage collection operation is written to a non-volatile memory in the memory device. The first part of the data that is written to the volatile memory (such as a random access memory) may comprise control information (such as mapping information of the logical addressable unit to a physical metablock). The second part of the data related to the garbage collection that is written to the non-volatile memory (such as a flash memory) may comprise the consolidated data in the update block. | 01-05-2012 |
20120005407 | REVOLVING DATA MANAGEMENT METHOD - The invention relates to a method of managing data to be written several times into a memory organized in sectors, each sector requiring complete erasure to allow a new write operation in the sector. To manage the data in a revolving manner, the method includes: ordering the sectors of the memory, the sector ordering taking place in a revolving manner, the sector following the last sector being the first sector; reserving, for each sector, a header zone intended to receive a first word that defines the filling of the sector; defining, in each sector, locations each intended to receive a data item; and associating part of the header zone with each data location, the part of the header zone written when a data item is stored in the corresponding data location. | 01-05-2012 |
20120005408 | SECURING THE ERASURE OF A FLASHPROM MEMORY - The invention relates to a method of managing data to be written several times into a memory organized in sectors, each sector requiring complete erasure to allow a new write operation in the sector. To secure the erasure of this type of memory, the method includes ordering the sectors of the memory and in reserving, for each sector, a header zone to receive a first word indicating that the latest erasure of the sector was carried out correctly, and a second word indicating that an erasure procedure for the preceding sector is in process. | 01-05-2012 |
20120005409 | METHOD FOR PERFORMING DATA SHAPING, AND ASSOCIATED MEMORY DEVICE AND CONTROLLER THEREOF - A method for performing data shaping is provided. The method is applied to a controller of a Flash memory, where the Flash memory includes a plurality of blocks. The method includes: according to contents of data to be written into or read from the Flash memory, generating/recovering an input seed of at least one randomizer/derandomizer; and utilizing the randomizer/derandomizer to generate a random function according to the input seed, for use of adjusting a plurality of bits of the data bit by bit. An associated memory device and a controller thereof are also provided. | 01-05-2012 |
20120005410 | Information Processing Apparatus, Raid Controller Card, and a Mirroring Method - According to one embodiment, an information processing apparatus includes a controller configured to write, first data to a first storage device from a first address to a second address according to a size of the first data, to write second data having a part of the first data to a second storage device from the first address, a size of the second data being equal to n times a page size, to write, to a cache memory, third data which is equal to the first data except the second data, and to write, when the controller receives a writing instruction includes third address being adjacent to the second address and fourth data, fifth data to the second storage device, the fifth data having the third data and at least part of fourth data, and a size of the fifth data is equal to the page size. | 01-05-2012 |
20120005411 | NON-VOLATILE CONFIGURATION FOR SERIAL NON-VOLATILE MEMORY - Example embodiments for configuring a serial non-volatile memory device may comprise a non-volatile configuration register to store a configuration value received from the processor, the configuration value to specify one or more attributes of a memory access operation. The configuration value may be read at least in part in response to power being applied to the memory device. | 01-05-2012 |
20120005412 | Memory Controller for Non-Homogeneous Memory System - A memory controller includes at least one interface adapted to be coupled to one or more first memory devices of a first memory type having a first set of attributes, and to one or more second memory devices of a second memory type having a second set of attributes. The first and second sets of attributes have at least one differing attribute. The controller also includes interface logic configured to direct memory transactions having a predefined first characteristic to the first memory devices and to direct memory transactions having a predefined second characteristic to the second memory devices. Pages having a usage characteristic of large volumes of write operations may be mapped to the one or more first memory devices, while pages having a read-only or read-mostly usage characteristic may be mapped to the one or more second memory devices. | 01-05-2012 |
20120005413 | Information Processing Apparatus and Data Restoration Method - According to one embodiment, an information processing apparatus includes a main memory, a first storage, a second storage, a first writing module, and a second writing module. A first storage is configured to store a file for executing an operating system. A first writing module is configured to write writing position information which indicates a writing position of data written in the second storage and is written to a predetermined position to the second storage, to the main memory. The second writing module is configured to write, to the first storage, the writing position information in the main memory to a predetermined write area in the first storage in a case of a crash of the operating system. The third writing module is configured to write the writing position information to the predetermined position in the second storage. | 01-05-2012 |
20120005414 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF READING DATA FROM AND WRITING DATA INTO A PLURALITY OF STORAGE UNITS - According to one embodiment, a semiconductor memory device includes a command processing module, a plurality of storage units, a plurality of control modules, an adjustment circuit, and a setting register. The adjustment circuit is configured to exclude the control module connected to the storage unit of a second group from a write operation in accordance with identification data, and to cause the control module connected to the storage unit of the second group to perform a read operation in a period overlapping the write operation performed by the control module connected to the storage unit of a first group. | 01-05-2012 |
20120005415 | MEMORY SYSTEM SELECTING WRITE MODE OF DATA BLOCK AND DATA WRITE METHOD THEREOF - A method of performing a write operation in a nonvolatile memory device comprises storing write data in a log block used to update a data block, determining whether a write pattern stored in the log block is a sequential write pattern or a random write pattern, and selecting a new data block for storing merged data in the data block and the log block. The new data block is determined to be a single-level cell block or a multi-level cell block according to the determined write pattern. | 01-05-2012 |
20120005416 | DATA RECORDING METHOD AND DATA RECODING DEVICE TO IMPROVE OPERATIONAL RELIABILITY OF NAND FLASH MEMORY - A data recording method and data recoding device to improve operational reliability of NAND flash memory includes calculating an address to record data, extracting information regarding a memory cell corresponding to the calculated address, selecting a data scrambling method based on the information regarding the memory cell, scrambling the data according to the data scrambling method, and recording the scrambled data on the memory cell. The information regarding the memory cell includes a logical block address, a logical page address, a physical block address, a physical page address of the memory cell, and a program/erase cycle of a memory block corresponding to the memory cell. | 01-05-2012 |
20120005417 | ARITHMETIC PROCESSING DEVICE AND DATA ERASING METHOD - Predetermined information is received from an external device and when receiving the information, an area in which the data stored in the first memory shall be erased is determined corresponding to a battery residual quantity of a power supply unit of the arithmetic processing device, and a data erasing process is controlled and executed with respect to the thus-determined area. | 01-05-2012 |
20120005418 | Hierarchical On-chip Memory - A hierarchical on-chip memory ( | 01-05-2012 |
20120011299 | Memory device with dynamic controllable physical logical mapping table loading - An apparatus includes a processor and a memory that includes computer program code. The memory and the computer program code are configured to, with the processor, cause the apparatus at least to send information from a host device to a mass storage memory device that is connected with the host device, the information including an indication of at least one default logical address range for a mass memory of the mass storage memory device. The memory and the computer program code are further configured, with the processor, to cause the apparatus, during operation of the host device with the mass storage memory device, and in response to at least one trigger condition being satisfied, to initiate a load of a portion of a logical-physical address conversion table that is stored in a memory of the mass storage memory device to another memory of the mass storage memory device as a local logical-physical address conversion table, where the portion corresponds to the at least one default logical address range. Also disclosed are corresponding methods and computer-readable storage medium, as well as a mass memory device or module that operates and is constructed in accordance with the exemplary embodiments of this invention. | 01-12-2012 |
20120011300 | METHOD AND APPARATUS FOR HIGH-SPEED BYTE-ACCESS IN BLOCK-BASED FLASH MEMORY - Techniques utilizing an erase-once, program-many progressive indexing structure manage data in a flash memory device which avoids the need to perform sector erase operations each time data stored in the flash memory device is updated. As a result, a large number of write operations can be performed before a sector erase operation is needed. Consequently, block-based flash memory can be used for high-speed byte access. | 01-12-2012 |
20120011301 | DYNAMICALLY CONTROLLING AN OPERATION EXECUTION TIME FOR A STORAGE DEVICE - In general, this disclosure is directed to techniques for adjusting the timing of operations for a storage device. According to one aspect of the disclosure, a method includes receiving, with at least one device, a workload indicator. The method further includes adjusting, with the at least one device, an operation execution time for the storage device responsive to at least the workload indicator. In some examples, the workload indicator may include a host demand indicator. In additional examples, the workload indicator may include a resource utilization indicator. In further examples, the operation execution time may be one of a write operation execution time or a read operation execution time. | 01-12-2012 |
20120011302 | NON-VOLATILE SOLID-STATE STORAGE SYSTEM SUPPORTING HIGH BANDWIDTH AND RANDOM ACCESS - Approaches for a non-volatile, solid-state storage system that is capable of supporting high bandwidth and/or random read/write access. The storage system may include a chassis having a bus slot and a disk bay, a master card mounted in the bus slot, and a flash memory card stacked in the disk bay and cabled to the master card. The master card enables one or more flash memory cards to be communicatively coupled to a single PCI Express bus. The master card may split a multi-lane PCI Express bus into a plurality of lanes, where one or more of the flash memory cards communicate over each of the plurality of lanes. Alternately, the master card may includes active circuitry for processing, switching, routing, reformatting, and/or converting the PCI Express bus into one or more busses for a plurality of flash memory cards. The stacked flash memory card is not in an enclosure. | 01-12-2012 |
20120011303 | MEMORY CONTROL DEVICE, MEMORY DEVICE, AND SHUTDOWN CONTROL METHOD - According to one embodiment, a memory control device includes a controller, a command queue module, a plurality of stage processors, and a skip module. The controller controls a data access command to a nonvolatile memory from a host. The command queue module queues a transfer request command corresponding to the data access command. The stage processors each perform stage processing related to the transfer request command queued by the command queue module. The skip module skips the stage processing by the stage processors in response to a shutdown command from the controller. | 01-12-2012 |
20120011304 | ENHANCED ADDRESSABILITY FOR SERIAL NON-VOLATILE MEMORY - Example embodiments for providing enhanced addressability for a serial non-volatile memory device may comprise accessing a storage location based, at least in part, on an extended address value and an address, the extended address value to identify a subset of storage locations from a plurality of storage locations, the address to identify the storage location within the subset of storage locations. | 01-12-2012 |
20120011305 | INFORMATION PROCESSING APPARATUS, CONTROL METHOD OF THE INFORMATION PROCESSING APPARATUS AND PROGRAM - An apparatus includes a first storage unit, a second storage unit, a setting unit configured to set a level of data deletion used for executing a job, an identification unit configured to identify a storage unit to be used for the job, and a control unit configured to, if the set level is a predetermined level and the identified storage unit is the first storage unit, store data of the job into the first storage unit and overwrite the stored data when the job is executed, and configured to, if the set level is the predetermined level and the identified storage unit is the second storage unit, encrypt data of the job and store the encrypted data into the second storage unit when the job is executed. | 01-12-2012 |
20120011306 | NONVOLATILE MEMORY DEVICE AND PROGRAM METHOD THEREOF - A program method of a nonvolatile memory device includes programming data of a first bit into a target page of a plurality of pages in a memory cell array, sensing the programmed data and storing the sensed data in a page buffer coupled to the memory cell array, erasing data of the target page, inputting data of a second bit to the page buffer and generating program data by combining the data of the second bit and the data of the first bit stored in the page buffer, and programming the program data into the target page. | 01-12-2012 |
20120011307 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage apparatus is coupled with a system bus to receive a write request accompanied with first and second blocks of data, which are stored in nonvolatile semiconductor memories. A control device sends a first erase command to one of the nonvolatile memories to initiate a first internal erase operation of data within the nonvolatile memories. After the first erase command has been sent, the control device sends a second erase command to another one of the nonvolatile memories, to initiate a second internal erase operation of data within the other nonvolatile memory. | 01-12-2012 |
20120011308 | CONTROL DEVICE OF A STORAGE SYSTEM COMPRISING STORAGE DEVICES OF A PLURALITY OF TYPES - A control device of a storage system that includes a plurality of storage devices including a first type of storage device, including: a memory which stores an archive deadline of archive target data which are a target of archiving by the storage system and a warranty deadline which is a quality warranty deadline of parity groups configured by two or more of the first type of storage devices; a controller which stores the archive target data in the parity groups configured by two or more of the first type of storage device, and wherein the parity group storing the archive target data is a parity group whose warranty deadline is near the archive deadline of the archive target data, among a plurality of the parity groups. | 01-12-2012 |
20120011309 | METHOD FOR PREVENTING READ-DISTURB HAPPENED IN NON-VOLATILE MEMORY AND CONTROLLER THEREOF - A method for preventing read-disturb happened in non-volatile memory and a controller thereof are disclosed. The non-volatile memory includes a plurality of blocks, and each block includes a plurality of pages. The method includes storing a program code executed by a controller of the non-volatile memory storage device for controlling the non-volatile memory storage device into at least a first block of the blocks; and copying the program code stored in the first block into at least a second block of the blocks when power is supplied to the non-volatile memory storage device. | 01-12-2012 |
20120017033 | STORAGE SYSTEM AND STORAGE CONTROL APPARATUS PROVIDED WITH CACHE MEMORY GROUP INCLUDING VOLATILE MEMORY AND NONVOLATILE MEMORY - A storage system is provided with a plurality of physical storage devices and a storage control apparatus that is coupled to the plurality of physical storage devices. The storage control apparatus is provided with a first cache memory group provided with a first volatile memory and a first nonvolatile memory and a second cache memory group provided with a second volatile memory and a second nonvolatile memory. The storage control apparatus executes a double write for writing the write target data from the host device to both of the first volatile memory and the second volatile memory, and notifies the host device of the write completion in the case in which the double write is completed. The storage control apparatus backs up data from the first volatile memory to the first nonvolatile memory while an electrical power is supplied from the primary power source. The storage control apparatus backs up data from the second volatile memory to the second nonvolatile memory while an electrical power is supplied from the secondary power source to the second volatile memory in the case in which an electrical power supply from the primary power source is stopped. | 01-19-2012 |
20120017034 | METHODS AND SYSTEMS FOR REDUCING CHURN IN FLASH-BASED CACHE - A storage device includes a flash memory-based cache for a hard disk-based storage device and a controller that is configured to limit the rate of cache updates through a variety of mechanisms, including determinations that the data is not likely to be read back from the storage device within a time period that justifies its storage in the cache, compressing data prior to its storage in the cache, precluding storage of sequentially-accessed data in the cache, and/or throttling storage of data to the cache within predetermined write periods and/or according to user instruction. | 01-19-2012 |
20120017035 | RUNTIME REPROGRAMMING OF A PROCESSOR CODE SPACE MEMORY AREA - In a first embodiment of the present invention, a method for allowing a microprocessor to access a flash memory is provided, the method comprising: fetching code instructions and data from the flash memory via a unidirectional code bus coupled to a flash controller, which is coupled to a databus interface, which is coupled to the flash memory; executing the code instructions in a manner that is substantially similar to that as used for a read only memory (ROM) coupled to the microprocessor; and writing data to the flash memory via a bidirectional databus separate from the unidirectional code bus, wherein the bidirectional databus is coupled to the databus interface and to a scratch memory, wherein the writing comprises using write flash procedures located in the ROM, the write flash procedures comprising instructions for reading and using parameter values stored in the scratch memory and for erasing memory locations and writing data to memory locations in the flash memory. | 01-19-2012 |
20120017036 | HYBRID STORAGE SYSTEM FOR A MULTI-LEVEL RAID ARCHITECTURE - The present invention relates to semiconductor storage systems (SSDs). Specifically, the present invention relates to a switch-based hybrid storage system. In a typical embodiment, a set of double data rate semiconductor storage device (DDR SSD) RAID controllers is coupled to a system control board, and a set of DDR SSD modules to the set of DDR SSD RAID controllers. The set of DDR SSD modules typically comprises a set of DDR SSD units. In addition, a set of HDD/Flash SSD RAID controllers is also coupled to the system control board, and a set of hard disk drive (HDD) modules are coupled to the set of HDD/Flash SSD RAID controllers. The set of HDD modules typically comprises a set of HDD/Flash SDD units. | 01-19-2012 |
20120017037 | CLUSTER OF PROCESSING NODES WITH DISTRIBUTED GLOBAL FLASH MEMORY USING COMMODITY SERVER TECHNOLOGY - Approaches for a distributed storage system that comprises a plurality of nodes. Each node, of the plurality of nodes, executes one or more application processes which are capable of accessing persistent shared memory. The persistent shared memory is implemented by solid state devices physically maintained on each of the plurality of nodes. Each the one or more application processes, maintained on a particular node, of the plurality of nodes, communicates with a shared data fabric (SDF) to access the persistent shared memory. The persistent shared memory comprises a scoreboard implemented in shared DRAM memory that is mapped to a persistent storage. The scoreboard provides a crash tolerant mechanism for enabling application processes to communicate with the shared data fabric (SDF). | 01-19-2012 |
20120017038 | Non-Volatile Memory And Method With Control Data Management - In a nonvolatile memory with block management system, critical data such as control data for the block management system is maintained in duplicates. Various methods are described for robustly writing and reading two copies of critical data in multi-state memory. In another aspect of the invention, a preemptive garbage collection on memory block containing control data avoids an undesirable situation where a large number of such memory blocks need be garbage collected at the same time. | 01-19-2012 |
20120023282 | Multi-Tier Address Mapping in Flash Memory - A user data portion of a flash memory arrangement is grouped into a plurality of mapping units. Each of the mapping units includes a user data memory portion and a metadata portion. The mapping units form a plurality of groups that are associated with at least one lower tier of a forward memory map. For each of the groups, a last written mapping unit within the group is determined. The last written mapping unit includes mapping data in the metadata portion that facilitates determining a physical address of other mapping units within the group. A top tier of the forward memory map is formed that includes at least physical memory locations of the last written mapping units of each of the groups. A physical address of a targeted memory is determined using the top tier and the metadata of the at least one lower tier. | 01-26-2012 |
20120023283 | Flash Memory Device and Method for Managing Flash memory Device - A flash memory device includes a flash memory and a controller. The flash memory includes a single level memory module and a multi level memory module. The single level memory module includes a first data bus and at least one single level cell flash memory. Each memory cell of the single level cell flash memory stores one bit of data. The multi level memory module includes a second data bus and at least one multi level cell flash memory. Each memory cell of the multi level cell flash memory stores more than one bit of data. The first data bus is coupled to the second data bus. During a write operation, the controller writes data to the single level memory module, and the single level memory module further transmits the data to the multi level memory module through the first and second data buses coupled therebetween without passing the data through the controller. | 01-26-2012 |
20120023284 | Nonvolatile Memory System - A memory system including a nonvolatile memory, and a memory control module. The nonvolatile memory includes a plurality of memory cells arranged among a plurality of physical memory blocks, wherein each physical memory block is of a predetermined size. The memory control module includes a write path module and a read path module. In response to the memory control module receiving data in a first format such that the data is evenly distributable among the plurality of physical memory blocks, the write path module modifies the first format of the data into a second format prior to writing the data to the plurality of physical memory blocks. The second format of the data is such that the data is no longer evenly distributable among the plurality of physical memory blocks. The read path module is configured to read the data from the nonvolatile memory in accordance with the second format. | 01-26-2012 |
20120023285 | NON-VOLATILE MEMORY WITH DYNAMIC MULTI-MODE OPERATION - A method and system for extending the life span of a flash memory device. The flash memory device is dynamically configurable to store data in the single bit per cell (SBC) storage mode or the multiple bit per cell (MBC) mode, such that both SBC data and MBC data co-exist within the same memory array. One or more tag bits stored in each page of the memory is used to indicate the type of storage mode used for storing the data in the corresponding subdivision, where a subdivision can be a bank, block or page. A controller monitors the number of program-erase cycles corresponding to each page for selectively changing the storage mode in order to maximize lifespan of any subdivision of the multi-mode flash memory device. | 01-26-2012 |
20120023286 | APPARATUS AND METHOD OF PAGE PROGRAM OPERATION FOR MEMORY DEVICES WITH MIRROR BACK-UP OF DATA - An apparatus and method of page program operation is provided. When performing a page program operation with a selected memory device, a memory controller loads the data into the page buffer of one selected memory device and also into the page buffer of another selected memory device in order to store a back-up copy of the data. In the event that the data is not successfully programmed into the memory cells of the one selected memory device, then the memory controller recovers the data from the page buffer of the other memory device. Since a copy of the data is stored in the page buffer of the other memory device, the memory controller does not need to locally store the data in its data storage elements. | 01-26-2012 |
20120023287 | STORAGE APPARATUS AND CONTROL METHOD THEREOF - This storage apparatus has a disk-shaped storage device for storing data sent from a host system, and includes a nonvolatile memory device for storing the data, a controller for controlling the reading or writing of the data sent from the host system from or into the disk-shaped storage device, and a device controller for controlling the nonvolatile memory device and the disk-shaped storage device. The device controller replicates data stored in the disk-shaped storage device to the nonvolatile memory device according to the usage of the disk-shaped storage device. The controller reads data from the nonvolatile memory device when the controller receives a data read request from the host system and corresponding data is stored in the nonvolatile memory device. | 01-26-2012 |
20120023288 | System For Accessing Non Volatile Memory - Accessing a non-volatile memory array is described, including receiving a first data and a memory address associated with the first data, writing the first data to the non-volatile memory array at the memory address of the first data without erasing a second data stored in the non-volatile memory array at the memory address of the first data before writing the first data. | 01-26-2012 |
20120030409 | INITIATING WEAR LEVELING FOR A NON-VOLATILE MEMORY - Systems and methods are provided for initiating wear leveling on block-aligned boundaries for non-volatile memories (“NVMs”), such as flash memory. In some embodiments, an electronic device including the NVM may suspend the programming of data upon reaching the end of a dynamic block. The electronic device may then perform wear leveling on a low-cycled block of the NVM. The electronic device may thus be configured to copy static data from the low-cycled block to another block of the NVM. After wear leveling has completed, the memory interface can program a second portion of the data to a new dynamic block of the NVM. This way, the electronic device can improve the efficiency of garbage collection. In addition, the electronic device can decrease the programming time for user generated writes, the wearing of the NVM, and overall power consumption. | 02-02-2012 |
20120030410 | HYBRID RAID CONTROLLER - Provided is a hybrid RAID controller for a storage device of a PCI-Express (PCI-e) type that supports a low-speed data processing speed for a host. Specifically, embodiments of this invention provide a hybrid RAID controller coupled to one or more (i.e., a set of) semiconductor storage device (SSD) memory disk units and one or more hard disk drive (HDD)/Flash memory units. Among other things, the SSD memory disk units and/or HDD/Flash memory units adjust a synchronization of a data signal transmitted/received between the host and a memory disk during data communications between the host and the memory disk through a PCI-Express interface and simultaneously support a high-speed data processing speed for the memory disk, thereby supporting the performance of the memory to enable high-speed processing in an existing interface environment at the maximum. | 02-02-2012 |
20120030411 | DATA PROTECTING METHOD, MEMORY CONTROLLER AND PORTABLE MEMORY STORAGE APPARATUS - A data protecting method for a portable memory storage apparatus is provided. The method includes determining whether a mode signal is at a data protecting mode, and performing a file hiding procedure to change a file allocation table if the mode signal is at the data protecting mode, wherein a host system coupled to the portable memory storage device is allowed to only access a portion of logical addresses of the portable memory storage apparatus according to the changed file allocation table and files stored in the portable memory storage apparatus before the file hiding procedure are written into another portion of the logical addresses. Additionally, the method still includes performing a file showing procedure to change the file allocation table if the mode signal is not at the data protecting mode, wherein the host system may access all the logical addresses according to the changed file allocation table. | 02-02-2012 |
20120030412 | Systems and Methods for Implementing a Programming Sequence to Enhance Die Interleave - Systems and methods for sequentially writing data to a memory device such as a universal serial bus (USB) memory device are disclosed. A system controller of a memory device including a first die and a second die, each of the first die and the second die including a plurality of pages, writes a first portion of a set of data to a lower page of a second die. The system controller then writes a second portion of the set of data to an upper page of the second die after writing the first portion of the set of data to the lower page of the second die. | 02-02-2012 |
20120030413 | MEMORY MANAGEMENT DEVICE, INFORMATION PROCESSING DEVICE, AND MEMORY MANAGEMENT METHOD - According to one embodiment, a memory management device configured to manage a main memory including a nonvolatile semiconductor memory, the memory management device includes a sort module configured to sort, at a time of a data write operation in the nonvolatile semiconductor memory, data to write areas of the nonvolatile semiconductor memory, based on information of a frequency of write which is determined by a data attribute of the data, and a control module configured to write the sorted data in the nonvolatile semiconductor memory by an incremental-write type. | 02-02-2012 |
20120030414 | NON VOLATILE MEMORY APPARATUS, DATA CONTROLLING METHOD THEREOF, AND DEVICES HAVING THE SAME - A memory apparatus includes a local bus, a plurality of non-volatile memories, a first buffer, and a main controller. The non-volatile memories share the local bus. The first buffer is connected to the plurality of non-volatile memories via the local bus. The first buffer buffers data stored in the plurality of non-volatile memories. The main controller is configured to generate a control signal for controlling the first buffer to buffer data stored in a source memory of the plurality of non-volatile memories and transmit the data to a target memory. | 02-02-2012 |
20120030415 | MASS-STORAGE SYSTEM UTILIZING AUXILIARY SOLID-STATE STORAGE SUBSYSTEM - A mass storage system including main and auxiliary storage subsystems and a controller Main storage provides physical storage space and includes non-solid-state storage devices (“NSSDs”) NSSDs provide physical locations, and main storage includes physical storage locations provided by NSSDs Controller is coupled to main storage and may be configured for mapping logical addresses to physical locations, giving rise to a logical storage space The auxiliary subsystem includes a solid-state data retention device (“SSDRD”) capable of permanently storing data and provides a physical location, giving rise to auxiliary space Controller is coupled to the auxiliary subsystem and may override a mapping of logical addresses to physical locations, with a mapping of logical address to physical locations within the auxiliary space, overriding physical storage locations Controller is adapted for loading a snapshot of the data currently stored in the overridden physical storage locations. | 02-02-2012 |
20120030416 | DATA STORAGE DEVICE - A data storage device includes an interface that is configured to interface with a host, a command bus, multiple memory devices that are operably coupled to the command bus and a controller that is operably coupled to the interface and to the command bus. The controller is configured to receive a bad block scan command for a specified one of the memory devices from the host using the interface, scan the specified memory device for bad blocks, generate a map of the bad blocks and communicate the map to the host using the interface. | 02-02-2012 |
20120036309 | COORDINATED GARBAGE COLLECTION FOR RAID ARRAY OF SOLID STATE DISKS - An optimized redundant array of solid state devices may include an array of one or more optimized solid-state devices and a controller coupled to the solid-state devices for managing the solid-state devices. The controller may be configured to globally coordinate the garbage collection activities of each of said optimized solid-state devices, for instance, to minimize the degraded performance time and increase the optimal performance time of the entire array of devices. | 02-09-2012 |
20120036310 | DATA PROCESSING DEVICE - A data processing device is provided enabling faster read access to data in an on-chip EEPROM with relative ease, without increasing the area occupied by the chip and its power consumption. The on-chip nonvolatile memory included in the data processing device is provided with a pre-read cache which latches all or part of data, once having been read to bit lines from an array of nonvolatile memory cells by selecting a row address, and a selecting circuit which selects a portion of the data latched by the pre-read cache by selecting a portion of columns. Control is performed to retain address information for data latched by the pre-read cache, inhibit latching new data into the pre-read cache for read access to data in the nonvolatile memory according to the same address as the retained address information, and cause the selecting circuit to select the data latched by the pre-read cache. | 02-09-2012 |
20120036311 | CACHE AND DISK MANAGEMENT METHOD, AND A CONTROLLER USING THE METHOD - A cache and disk management method is provided. In the cache and disk management method, a command to delete all valid data stored in a cache, or specific data corresponding to a (*portion? part of the valid data may be transmitted to a plurality of member disks. That is, all of the valid data or the specific data may exist in the cache only, and may be deleted from the plurality of member disks. Accordingly, the plurality of member disks may secure more space, an internal copy overhead may be reduced, and more particularly, solid state disks may achieve better performance. | 02-09-2012 |
20120036312 | Wear Leveling Technique for Storage Devices - A method for managing wear levels in a storage device having a plurality of data blocks, the method comprising moving data to data blocks having higher erasure counts based on a constraint on static wear levelness that tightens over at least a portion of the lives of the plurality of data blocks. | 02-09-2012 |
20120036313 | METHOD FOR CONTROLLING MEMORY CARD AND METHOD FOR CONTROLLING NONVOLATILE SEMICONDUCTOR MEMORY - A method for controlling a memory card which includes a nonvolatile semiconductor memory whose memory area includes a plurality of write areas is disclosed. A first area which is a part of the plurality of write areas is set in accordance with management executed by a first file system. The first file system sequentially writes data along a direction in which addresses of the plurality of write areas increase. A second area which is a part of the plurality of write areas is set in accordance with management executed by a second file system. The second file system writes data in an order which does not depend on the addresses. | 02-09-2012 |
20120036314 | MEMORY DEVICES HAVING PROGRAMMABLE ELEMENTS WITH ACCURATE OPERATINGPARAMETERS STORED THEREON - A system with a memory device having programmable elements used to configure a memory system. More specifically, programmable elements, such as antifuses, located on a memory device are programmed during fabrication with measured operating parameters corresponding to the memory device. Operating parameters may include, for example, operating current values, operating voltages, or timing parameters. The memory device is incorporated into a system. Once the memory device is incorporated into a system, the programmable elements may be accessed by a processor such that the memory system can be configured to optimally operate in accordance with the operating parameters measured for the memory device in the system. | 02-09-2012 |
20120042117 | BOOT SYSTEM - A boot system of an electronic device includes a central processing unit (CPU), a NAND flash, a synchronous dynamic random access memory (SDRAM), and a pulse count unit. The NAND flash and the SDRAM are electronically connected with the CPU. The pulse count unit is electronically connected with the CPU and the NAND flash. The pulse count unit may initialize and enable the NAND flash. The CPU reads a pre-boot loader stored in the NAND flash and loads the pre-boot loader in the SDRAM. The CPU executes the pre-boot loader stored in the SDRAM to boot the electronic device. | 02-16-2012 |
20120042118 | Method for Flash Memory and Associated Controller - A method is disclosed for a flash memory including a plurality of data units includes determining whether to refresh data of the data units according to number of time the data units that are being read when the flash memory is read. The present invention provides methods for flash memory devices and a specialized controller to utilize values stored in counters relating to the number of read instances of corresponding blocks of data units for the selective control of refreshing data blocks when associated counter values exceed a threshold value. | 02-16-2012 |
20120042119 | SEMICONDUCTOR STORAGE DEVICE AND CONTROL METHOD THEREOF - According to one embodiment, a semiconductor storage device comprises a main memory, a request issue module, a delay module, and an access module. The main memory is configured to store candidate information for determining a compaction candidate for a nonvolatile memory. The request issue module is configured to issue an access request for the candidate information in the main memory. The delay module is configured to delay the access request issued from the request issue module. The access module is configured to access the candidate information in the main memory based on an access request delayed by the delay module. | 02-16-2012 |
20120042120 | BACKWARD COMPATIBLE EXTENDED USB PLUG AND RECEPTACLE WITH DUAL PERSONALITY - An extended Universal-Serial-Bus (USB) connector plug and socket each have a pin substrate with one surface that supports the four metal contact pins for the standard USB interface. An extension of the pin substrate carries another 8 extension metal contact pins that mate when both the connector plug and socket are extended. The extension can be an increased length of the plug's and socket's pin substrate or a reverse side of the substrate. Standard USB connectors do not make contact with the extension metal contacts that are recessed, retracted by a mechanical switch, or on the extension of the socket's pin substrate that a standard USB connector cannot reach. Standard USB sockets do not make contact with the extension metal contacts because the extended connector's extension contacts are recessed, or on the extension of the connector pin substrate that does not fit inside a standard USB socket. | 02-16-2012 |
20120047314 | DATA BACKUP METHOD FOR FLASH MEMORY MODULE AND SOLID STATE DRIVE - A data backup method for a flash memory module is provided. The flash memory module includes a plurality of flash memory units. In the data backup method, a controller is first provided to receive a backup function enabling signal. The controller then configures the flash memory units according to the backup function enabling signal such that at least one of the flash memory units is configured as a backup storage area and the flash memory units that are not in the backup storage area are configured as a main storage area. The controller then checks and receives an updated status of important data in the main storage area and backs up the important data into the backup storage area according to the updated status. Accessing to the backup storage area and accessing to the main storage area by the controller are independent. | 02-23-2012 |
20120047315 | ADAPTIVE WRITE BEHAVIOR FOR A SYSTEM HAVING NON-VOLATILE MEMORY - Systems and methods are disclosed for adaptive writing behavior for a system having non-volatile memory (“NVM”). A memory interface of a system can be configured to determine whether a write preference of the system is skip-sequential. In response to determining that the write preference is skip-sequential, the memory interface can sequentially program data to a first set of pages of a block of the NVM. In addition, the memory interface can sequentially pre-merge gaps between the first set of pages with one or more pages of a data block. Moreover, the memory interface can be configured to switch to an alternative programming state in response to determining that at least one condition has been satisfied. For example, the memory interface can stop programming data sequentially, and instead program data in the order that the data is received from a file system. | 02-23-2012 |
20120047316 | EFFICIENT ALLOCATION POLICIES FOR A SYSTEM HAVING NON-VOLATILE MEMORY - Systems and methods are disclosed for efficient allocation policies for a system having non-volatile memory. A file system allocator of the system can be configured to allocate memory regions that are aligned with one or more logical blocks of a logical space (e.g., one or more super block-aligned regions). In some embodiments, the file system allocator can monitor the number of free sectors corresponding to each logical block. In other embodiments, the file system allocator can monitor a ratio of free space to total space corresponding to each logical block. The file system allocator can select a logical block based at least in part on the number of free sectors of the logical block. In some cases, the file system allocator can allocate the free sectors of the logical block in a sequential order. | 02-23-2012 |
20120047317 | SEMICONDUCTOR STORAGE DEVICE AND METHOD OF THROTTLING PERFORMANCE OF THE SAME - A semiconductor storage device and a method of throttling performance of the same are provided. The semiconductor storage device includes a non-volatile memory device configured to store data in a non-volatile state; and a controller configured to control the non-volatile memory device. The controller calculates a new performance level, compares the calculated performance level with a predetermined reference, and determines the calculated performance level as an updated performance level according to the comparison result. | 02-23-2012 |
20120047318 | SEMICONDUCTOR STORAGE DEVICE AND METHOD OF THROTTLING PERFORMANCE OF THE SAME - A semiconductor storage device and a method of throttling performance of the same are provided. The semiconductor storage device includes a non-volatile memory device; and a controller configured to receive a write command from a host and program write data received from the host to the non-volatile memory device in response to the write command. The controller inserts idle time after receiving the write data from the host and/or after programming the write data to the non-volatile memory device. | 02-23-2012 |
20120047319 | SEMICONDUCTOR STORAGE DEVICE AND METHOD OF THROTTLING PERFORMANCE OF THE SAME - A semiconductor storage device (SSD) and a method of throttling performance of the SSD. The method can include gathering at least two workload data items related with a workload of the semiconductor storage device, estimating the workload using the at least two workload data items, and throttling the performance of the semiconductor storage device according to the estimated workload. Accordingly, a workload that the semiconductor storage device will undergo can be estimated. | 02-23-2012 |
20120047320 | METHOD AND APPARATUS TO INTERFACE SEMICONDUCTOR STORAGE DEVICE AND HOST TO PROVIDE PERFORMANCE THROTTLING OF SEMICONDUCTOR STORAGE DEVICE - A method and apparatus to interface a semiconductor storage device and a host in order to provide performance throttling of the semiconductor storage device. In the method, the semiconductor storage can receive a setting request command from the host. The semiconductor storage device sets a performance throttling parameter to a particular value in response to the setting request command. The semiconductor storage device can send to the host a setting response signal indicating completion of the setting of the performance throttling parameter. | 02-23-2012 |
20120047321 | Address Scheduling Methods For Non-Volatile Memory Devices With Three-Dimensional Memory Cell Arrays - At least one address scheduling method includes selecting a first bit line, selecting a first string connected to the first bit line, performing address scheduling on N pages of each of multi-level cells in the first string sequentially from a bottom word line to a top word line, and after completing the address scheduling on all word lines in the first string, performing address scheduling on second to k-th strings sequentially in the same manner as performed with respect to the first string, where “k” is 2 or a natural number greater than 2. | 02-23-2012 |
20120047322 | Method and System of Using One-Time Programmable Memory as Multi-Time Programmable in Code Memory of Processors - A method, device and system of using an One-Time-Programmable (OTP) memory as an Multiple-Time Programming (MTP) memory equivalent is disclosed. The use of OTP memory in this manner allows code to be updated one or more times and yet remain small in size and relatively easy to process (fabricate). The code can be program code for a processor, such as boot code, boot code kernel or other instruction code. According to one aspect, an OTP memory is able to functionally operate as if it were a MTP memory through intelligent use of NOPs, which are no operations. Subsequently, if a particular subroutine or function in the program code needs to be modified, an instruction (e.g., JUMP instruction) can be programmed into the NOP so that certain existing instructions can be bypassed and the execution of instructions of a new module can be performed. | 02-23-2012 |
20120047323 | BOOT MANAGEMENT OF NON-VOLATILE MEMORY - A BIOS may provide bad block and wear-leveling services to a flash memory during a boot cycle until a full-functioned memory controller, such as a software memory controller, is available. After the full-functioned memory controller is available, the controller may use data passed by the BIOS to determine what, if any, steps to take to account for write activity during the boot process. Alternatively, the BIOS may use a reserved portion of flash memory so that wear leveling for boot-related data, such as a shut-down flag, is not needed. | 02-23-2012 |
20120059974 | METHOD AND APPARATUS FOR IMPROVING COMPUTER SYSTEM PERFORMANCE BY ISOLATING SYSTEM AND USER DATA - An apparatus comprising a logic unit to separate system data and user data from host data to be processed by a processor; a first memory to store the system data separated by the logic unit; and a second memory to store the user data separated by the logic unit, wherein the first memory is a non-volatile memory which is physically located closer to the processor than the second memory. | 03-08-2012 |
20120059975 | PROCESSOR INDEPENDENT LOOP ENTRY CACHE - A memory controller is configured to receive read requests from a processor and return memory words from memory. The memory controller comprises an address comparator and a loop entry cache. The address comparator is configured to determine a difference between a previous read request address and a current read request address. The address comparator is also configured to determine whether the difference is positive and less than a certain address difference and, if so, indicate a limited backwards jump. The loop entry cache is configured to store a current memory word for the current read request address when the address comparator indicates a limited backwards jump. | 03-08-2012 |
20120059976 | STORAGE ARRAY CONTROLLER FOR SOLID-STATE STORAGE DEVICES - A storage array controller provides a method and system for autonomously issuing trim commands to one or more solid-state storage devices in a storage array. The storage array controller is separate from any operating system running on a host system and separate from any controller in the solid-state storage device(s). The trim commands allow the solid-state storage device to operate more efficiently. | 03-08-2012 |
20120059977 | ELECTRONIC DEVICE, CONTROLLER FOR ACCESSING A PLURALITY OF CHIPS VIA AT LEAST ONE BUS, AND METHOD FOR ACCESSING A PLURALITY OF CHIPS VIA AT LEAST ONE BUS - An electronic device includes a plurality of chips, at least a bus and a controller, where the plurality of chips include a first chip and a second chip, the bus includes a plurality of data lines, the controller couples to the plurality of chips via the bus, and the controller is utilized for accessing the plurality of chips. The controller determines an allocation for data transmission of external data according to information about which chip the external data will be written to, where the allocation for data transmission is an arrangement of a plurality of bits of the external data transmitted on the plurality of data lines, and a first allocation for data transmission corresponding to the first chip is different from a second allocation for data transmission corresponding to the second chip. | 03-08-2012 |
20120059978 | Storage array controller for flash-based storage devices - The invention is an improved storage array controller that adds a level of indirection between host system and storage array. The storage array controller controls a storage array comprising at least one solid-state storage device. The storage array controller improvements include: garbage collection, sequentialization of writes, combining of writes, aggregation of writes, increased reliability, improved performance, and addition of resources and functions to a computer system with a storage subsystem. | 03-08-2012 |
20120059979 | MEMORY MANAGEMENT APPARATUS AND MEMORY MANAGEMENT METHOD - A terminal apparatus including a non-volatile memory for which writing is performed in units of blocks; and a control unit configured to perform a first method of managing bad blocks in the non-volatile memory with respect to blocks corresponding to an information management table in a file system of the non-volatile memory, and to perform a second method of managing bad blocks in the non-volatile memory with respect to blocks corresponding to user data in the file system. | 03-08-2012 |
20120059980 | SOLID STATE STORAGE DEVICE CONTROLLER WITH EXPANSION MODE - Solid state storage device controllers, solid state storage devices, and methods for operation of solid state storage device controllers are disclosed. In one such solid state storage device, the controller can operate in either an expansion DRAM mode or a non-volatile memory mode. In the DRAM expansion mode, one or more of the memory communication channels normally used to communicate with non-volatile memory devices is used to communicate with an expansion DRAM device. | 03-08-2012 |
20120059981 | APPARATUS, SYSTEM, AND METHOD FOR STORAGE SPACE RECOVERY - An apparatus, system, and method are disclosed for storage space recovery. A storage division selection module selects a first storage division for recovery. The first storage division comprises a portion of solid-state storage in a solid-state storage device. A data recovery module reads valid data from the first storage division in response to selecting the first storage division for recovery. The data recovery module stores the valid data in a second storage division of the solid-state storage device. The data recovery module passes the valid data through at least a portion of a write data pipeline for the solid-state storage device without passing the valid data to a host device and/or without routing the valid data outside of a solid-state storage controller for the solid-state storage device. | 03-08-2012 |
20120066433 | Apparatus and method for read preamble disable - A memory device is provided. The memory device includes a preamble disable memory and a memory controller. The preamble disable memory is arranged to store preamble disable data. The preamble disable data includes an indication as to whether a read preamble should be enabled or disabled. In response to a read command, if the preamble disable data includes an indication that the read preamble should be enabled, the memory controller provides the read preamble. Alternatively, in response to the read command, if the preamble disable data includes an indication that the read preamble should be disabled, the memory controller disables the read preamble. | 03-15-2012 |
20120066434 | APPARATUS, METHOD, AND MANUFACTURE FOR USING A READ PREAMBLE TO OPTIMIZE DATA CAPTURE - A memory controller is provided. In response to a burst read command that includes a target address, the memory controller provides, to one or more busses, data stored in memory at the target address after dummy clock cycles have occurred. The memory controller also provides a preamble on the bus(ses) during some of the dummy clock cycles. The preamble includes a data training pattern. | 03-15-2012 |
20120066435 | SCHEDULING OF I/O WRITES IN A STORAGE ENVIRONMENT - A system and method for effectively scheduling read and write operations among a plurality of solid-state storage devices. A computer system comprises client computers and data storage arrays coupled to one another via a network. A data storage array utilizes solid-state drives and Flash memory cells for data storage. A storage controller within a data storage array comprises an I/O scheduler. The data storage controller is configured to receive requests targeted to the data storage medium, said requests including a first type of operation and a second type of operation. The controller is further configured to schedule requests of the first type for immediate processing by said plurality of storage devices, and queue requests of the second type for later processing by the plurality of storage devices. Operations of the first type may correspond to operations with an expected relatively low latency, and operations of the second type may correspond to operations with an expected relatively high latency. | 03-15-2012 |
20120066436 | METHOD FOR PERFORMING DATA SHAPING, AND ASSOCIATED MEMORY DEVICE AND CONTROLLER THEREOF - A method for performing data shaping is provided. The method is applied to a controller of a Flash memory, where the Flash memory includes a plurality of blocks. The method includes: performing a program optimization operation according to original data and a plurality of shaping codes, in order to generate trace back information corresponding to a Trellis diagram and utilize the trace back information as side information; and dynamically selecting at least one shaping code from the shaping codes according to the side information to perform data shaping on the original data. An associated memory device and a controller thereof are also provided. | 03-15-2012 |
20120066437 | DATA PROGRAMMING CIRCUIT AND METHOD FOR OTP MEMORY - A data programming circuit is provided. A one-time-programmable (OTP) stores a first version of encoding data corresponding to a first version of a read-only memory (ROM) code. A control unit stores a second version of the ROM code into the OTP memory, wherein the control unit obtains a matching table according to the first version of the encoding data and the second version of the ROM code. The control unit obtains a first data segment of the first version of the encoding data and a second data segment of the second version of the ROM code that have the same content, according to the matching table. The control unit encodes the second data segment as a specific address, and the specific address points to the first data segment of the first version of the encoding data in the OTP memory. | 03-15-2012 |
20120066438 | NON-VOLATILE MEMORY DEVICE, OPERATION METHOD THEREOF, AND DEVICE HAVING THE SAME - A memory device includes a control module to determine first data blocks needing a garbage collection, to determine second data blocks needing memory refresh among the determined first data blocks, and to execute the garbage collection first on the second data blocks. | 03-15-2012 |
20120066439 | APPARATUS, SYSTEM, AND METHOD FOR MANAGING LIFETIME OF A STORAGE DEVICE - An apparatus, system, and method are disclosed for managing lifetime for a data storage device. A target module determines a write bandwidth target for a data storage device. An audit module monitors write bandwidth of the data storage device relative to the write bandwidth target. A throttle module adjusts execution of one or more write operations on the data storage device in response to the write bandwidth of the data storage device failing to satisfy the write bandwidth target. | 03-15-2012 |
20120066440 | APPARATUS AND METHOD FOR MIRRORING DATA BETWEEN NONVOLATILE MEMORY AND A HARD DISK DRIVE - This storage apparatus that provides to a host computer a logical device for storing data sent from the host computer includes a nonvolatile memory for storing the data, a disk-shaped memory device for storing the data, and a controller for controlling the nonvolatile memory and the disk-shaped memory device. The controller redundantly configures the logical device with the nonvolatile memory and the disk-shaped memory device. | 03-15-2012 |
20120066441 | SYSTEMS AND METHODS FOR AVERAGING ERROR RATES IN NON-VOLATILE DEVICES AND STORAGE SYSTEMS - A system for storing a plurality of logical pages in a set of at least one flash device, each flash device including a set of at least one erase block, the system comprising apparatus for distributing at least one of the plurality of logical pages over substantially all of the erase blocks in substantially all of the flash devices, thereby to define, for at least one logical page, a sequence of pagelets thereof together including all information on the logical page and each being stored within a different erase block in the set of erase blocks; and apparatus for reading each individual page from among the plurality of logical pages including apparatus for calling and ordering the sequence of pagelets from different erase blocks in the set of erase blocks. | 03-15-2012 |
20120066442 | SYSTEM AND METHOD OF PAGE BUFFER OPERATION FOR MEMORY DEVICES - Systems and methods are provided for using page buffers of memory devices connected to a memory controller through a common bus. A page buffer of a memory device is used as a temporary cache for data which is written to the memory cells of the memory device. This can allow the memory controller to use memory devices as temporary caches so that the memory controller can free up space in its own memory. | 03-15-2012 |
20120066443 | READING/WRITING CONTROL METHOD AND SYSTEM FOR NONVOLATILE MEMORY STORAGE DEVICE - The present invention is adapted to data storage technology field, and provides a reading/writing control method and system for nonvolatile memory, the method including the following steps: dividing valid blocks in the nonvolatile memory into different zones, the zones including at least one data zone having fixed number of valid blocks and one exchange zone having at least two valid blocks; creating a mapping table of logic blocks and physical blocks in each zone; establishing a mapping table of logic pages and physical pages in the blocks based on redundant area information of pages in the blocks, and storing the mapping table of the logic blocks and physical blocks in each zone and the mapping table of logic pages and physical pages in each block in a private data area; and writing data segments in an idle page of the blocks of the data zones in sequence, or reading data segments from valid pages in the data zones, thus the data reading/writing speed and efficiency is promoted. | 03-15-2012 |
20120072639 | Selection of Units for Garbage Collection in Flash Memory - A data structure is formed that references a garbage collection metric for each of a plurality of associated garbage collection units of a flash memory device. Each garbage collection metric is based on one or more device state characteristics of the associated garbage collection unit. In response to a threshold change in the one or more device state variables, a region of interest within the data structure is sorted based on the garbage collection metrics. One or more garbage collection units are selected for garbage collection operations from the sorted region of interest. | 03-22-2012 |
20120072640 | TRANSFERRING LEARNING METADATA BETWEEN STORAGE SERVERS HAVING CLUSTERS VIA COPY SERVICES OPERATIONS ON A SHARED VIRTUAL LOGICAL UNIT THAT STORES THE LEARNING METADATA - A virtual logical unit that stores learning metadata is allocated in a first storage server having a first plurality of clusters, wherein the learning metadata indicates a type of storage device in which selected data of the first plurality of clusters of the first storage server are stored. A copy services command is received to copy the selected data from the first storage server to a second storage server having a second plurality of clusters. The virtual logical unit that stores the learning metadata is copied, from the first storage server to the second storage server, via the copy services command. Selected logical units corresponding to the selected data are copied from the first storage server to the second storage server, and the learning metadata is used to place the selected data in the type of storage device indicated by the learning metadata. | 03-22-2012 |
20120072641 | SEMICONDUCTOR STORAGE DEVICE AND DATA CONTROL METHOD THEREOF - The flash memory controller compresses data in response to a write request. On condition that there is a compression effect with respect to the compressed data, the flash memory controller writes the compressed data to the base area of a physical block of a flash memory. As physical pages assigned to the physical block, the flash memory controller reduces the physical pages assigned to the base area from 102 down to 59, and increases the physical pages assigned to the update area from 26 up to 69. Therefore, it is possible to suppress exhaustion of physical pages which are assigned to the update area, to reduce the number of erases of the physical block, and to consequently prolong device operating life. | 03-22-2012 |
20120072642 | STORAGE APPARATUS AND CONTROL METHOD OF STORAGE APPARATUS - Storage drives of a plurality of types are mounted on a storage device together. A storage apparatus includes: an I/O controller that receives an access request sent from an information apparatus and writes data to or reads data from a storage drive; a storage drive mounting unit in which the storage drive is detachably mounted; a drive power supplying unit that supplies drive power to the storage drive mounted in the storage drive mounting unit; and a drive voltage identifying unit that identifies a voltage allowing data write to or data read from the storage drive mounted in the storage drive mounting unit, by raising a drive voltage applied to the storage drive from a voltage below a rated drive voltage of the storage drive. When the I/O controller writes data to or reads data from the storage drive, the drive power supplying unit applies the identified voltage to the storage drive to drive the storage drive. | 03-22-2012 |
20120072643 | METHOD OF MANAGING DATA IN A PORTABLE ELECTRONIC DEVICE HAVING A PLURALITY OF CONTROLLERS - The invention is a method of managing data in a portable electronic device comprising first and second controllers. The first controller comprises a first microprocessor and a first non volatile memory. The first microprocessor comprises a first piece of code. The second controller comprises a second microprocessor and a second non volatile memory. The second non volatile memory comprises a first executable data. The method comprises the following steps of: a) loading and activating the first piece of code in the first microprocessor, b) sending by the first controller a first request for retrieving the first executable data from the second non volatile memory, c) loading the first executable data into the first controller, and d) executing the first executable data by the first microprocessor. | 03-22-2012 |
20120072644 | SEMICONDUCTOR MEMORY CONTROLLING DEVICE - According to one embodiment, upon request from an information processor, a semiconductor storage controller writes pieces of data in predetermined units into storage locations in which no data has been written in erased areas within a semiconductor chip's storage area. A third table and a second table which is a subset thereof include physical addresses each indicating a storage location of each of pieces of the data within the semiconductor chip. The first table includes either information specifying a second table entry or information specifying a third table entry. The semiconductor storage controller records the first and the second tables into a volatile memory or records the first table into a volatile memory and the third table into a nonvolatile memory. | 03-22-2012 |
20120072645 | NONVOLATILE SEMICONDUCTOR MEMORY - According to one embodiment, a nonvolatile semiconductor memory includes a memory cell array with a block including word lines, and each word line connected to memory cells, a controller which controls a data erase of the memory cells in the block, and a verify circuit which verifies whether or not the data erase is completed. The controller comprises being executed a verification by the verify circuit after being executed a first block erase in a predetermined condition, being executed a second block erase continuously when the number of memory cells which are judged by the verification as a completion of the data erase is n (n is a natural number) or less, and being executed a page erase continuously when the number of memory cells which are judged by the verification as a completion of the data erase is more than n. | 03-22-2012 |
20120072646 | SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF CONTROLLING MEMORY - According to one embodiment, a semiconductor integrated circuit device includes a non-volatile memory, a storing module, and a processing module. The non-volatile memory is having a first area and a second area. The storing module is configured to store a second program for downloading a first program from an outside to the first area. The processing module is configured to execute the first and the second programs. The non-volatile memory is having a first area and a second area. The storing module is configured to store a second program for downloading a first program from an outside to the first area. The processing module is configured to execute the first and the second programs. The first area is capable of being written and erased by the first program, and the second area is not capable of being erased by the first program. | 03-22-2012 |
20120072647 | Different types of memory integrated in one chip by using a novel protocol - A semiconductor chip contains four different memory types, EEPROM, NAND Flash, NOR Flash and SRAM, and a plurality of major serial/parallel interfaces such as I | 03-22-2012 |
20120072648 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device in accordance with an embodiment includes: a memory cell array having electrically rewritable nonvolatile memory cells; and a control unit. The control unit performs control of repeating a write operation, a write verify operation, and a step-up operation, the write verify operation being an operation to verify whether data write is completed or not, and the step-up operation being an operation to raise the write pulse voltage if data write is not completed. The control unit, during the write operation, raises a first write pulse voltage with a first gradient, and then raises a second write pulse voltage with a second gradient, thereby executing the write operation, the first write pulse voltage including at least a write pulse voltage generated at first, the second write pulse voltage being generated after the first write pulse voltage, and the second gradient being larger than the first gradient. | 03-22-2012 |
20120072649 | NONVOLATILE MEMORY SYSTEM, AND DATA READ/WRITE METHOD FOR NONVOLATILE MEMORY SYSTEM - A nonvolatile memory system comprises a nonvolatile memory having a plurality of data areas; and a memory controller operative to control read and write operations to the nonvolatile memory. The memory controller successively executes read/write operations to plural sectors within a selected data area in the nonvolatile memory in accordance with a command and a sector count and sector address fed from a host device. | 03-22-2012 |
20120072650 | MEMORY SYSTEM AND DRAM CONTROLLER - According to one embodiment, a DRAM controller includes a clock generating and switching unit for supplying a first clock to a DRAM in a normal operation and generating a second clock having a lower speed than the first clock and supplying the generated second clock to the DRAM in an initialization processing, and a DRAM access circuit having a DLL circuit for regulating a fetch timing of data output from the DRAM based on the first clock, and fetching, in a fetch timing regulated by the DLL circuit, data output from the DRAM in a timing based on the second clock in relation to the initialization processing and the transfer data output from the DRAM in a timing based on the first clock in the initialization processing and the normal processing, respectively. | 03-22-2012 |
20120072651 | MEMORY CONTROLLER INTERFACE - A memory controller interface, mobile device and method are provided. The memory controller interface can allow a processor designed and configured to operate with NOR flash and static random access memory SRAM devices to instead operate using NAND flash and synchronous dynamic random access memory SDRAM. The system accomplishes this by caching sectors out of NAND flash into SDRAM, where the data can be randomly accessed by the processor as though it were accessing data from NOR flash/SRAM. Sectors containing data required by the processor are read out of NAND flash and written into SDRAM, where the data can be randomly accessed by the processor. Boot code is stored in memory accessible to the processor and is read out of the memory for execution. The boot code is scanned for a predetermined signature, and if the predetermined signature is found, a portion of the memory is write-protected. | 03-22-2012 |
20120072652 | MULTI-LEVEL BUFFER POOL EXTENSIONS - A buffer manager that manages blocks of memory amongst multiple levels of buffer pools. For instance, there may be a first level buffer pool for blocks in first level memory, and a second level buffer pool for blocks in second level memory. The first level buffer pool evicts blocks to the second level buffer pool if the blocks are not used above a first threshold level. The second level buffer pool evicts blocks to a yet lower level if they have not used above a second threshold level. The first level memory may be dynamic random access memory, whereas the second level memory may be storage class memory, such as a solid state disk. By using such a storage class memory, the working block set of the buffer manager may be increased without resorting to lower efficiency random block access from yet lower level memory such as disk. | 03-22-2012 |
20120072653 | MEMORY DEVICE WITH USER CONFIGURABLE DENSITY/PERFORMANCE - The memory device is comprised of a memory array having a plurality of memory cells that are organized into memory blocks. Each memory cell is capable of storing a selectable quantity of data bits (e.g., multiple level cells or a single bit per cell). Control circuitry controls the density configuration of read or write operations to the memory blocks in response to a configuration command. In one embodiment, the configuration command is part of the read or write command. In another embodiment, the configuration command is read from a configuration register. | 03-22-2012 |
20120072654 | Flash Memory Controller Garbage Collection Operations Performed Independently In Multiple Flash Memory Groups - A flash memory controller connected to multiple flash memory groups performs independent garbage collection operations in each group. For each group, the controller independently determines the amount of free space and performs garbage collection operations if the amount falls below a threshold. | 03-22-2012 |
20120072655 | STORAGE DEVICE AND ACCESS CONTROL SYSTEM THEREOF, SD CARD AND DATA ACCESS CONTROL METHOD THEREOF - The present disclosure relates to smart card technology, and provides a SD card and a data access control method thereof. The SD card includes an interface module, a control module, and a storage module including a public storage unit and a private storage unit. The control module includes a SD card direct access unit for controlling an external device to access the public storage unit, a storage isolating firmware unit for stopping the external device from unauthorized accessing the private storage unit, and a virtual machine operating system unit for installing some applications according to the requirements of user, and perform the application in a protected mode combined with the storage isolating firmware unit. The present disclosure can guarantee convenience of accession and stored of large capacity SD data, and installs some applications according to the requirements, performs the applications, storeds and accesses the data in a protected mode. | 03-22-2012 |
20120079166 | ELECTRONIC DEVICE AND METHOD FOR INITIALIZING DATA STORAGE - An electronic device for initializing a data storage is provided. The data storage has been accessed. The data storage includes a plurality blocks, which comprise some bad blocks. Each block comprising a block marking area for writing a block identifier. The block identifier is for marking whether the block is a bad block or a good block. After the data storage is accessed, a bad-block table for recording the block identifier of each block is stored at a predetermined location of the data storage. When initializing the data storage, the electronic device accesses the bad-block table from the predetermined location of the data storage, erases data stored on the data storage, obtains the block identifier of each block from the bad-block table; and writes the block identifier to the block marking area of each block. | 03-29-2012 |
20120079167 | MEMORY SYSTEM - According to one embodiment, a memory system includes a non-volatile semiconductor memory, a block management unit, and a transcription unit. The semiconductor memory includes a plurality of blocks to which data can be written in both the first mode and the second mode. The block management unit manages a block that stores therein no valid data as a free block. When the number of free blocks managed by the block management unit is smaller than or equal to a predetermined threshold value, the transcription unit selects one or more used blocks that stores therein valid data as transcription source blocks and transcribes valid data stored in the transcription source blocks to free blocks in the second mode. | 03-29-2012 |
20120079168 | METHOD FOR PERFORMING BLOCK MANAGEMENT, AND ASSOCIATED MEMORY DEVICE AND CONTROLLER THEREOF - A method for performing block management is provided. The method is applied to a controller of a Flash memory having multiple channels. The Flash memory includes a plurality of blocks respectively corresponding to the channels. The method includes: temporarily storing at least one index of at least one good block that is not grouped into any meta block into a spare good block table, where the good block is a block that is not determined as a bad block within the plurality of blocks; and when it is detected that a specific block corresponding to a specific channel within blocks currently grouped into meta blocks is a bad block, dynamically updating the spare good block table for use of block management. In particular, when needed, the good block is utilized for replacing a block grouped into a meta block. An associated memory device and a controller thereof are also provided. | 03-29-2012 |
20120079169 | METHOD FOR PERFORMING META BLOCK MANAGEMENT, AND ASSOCIATED MEMORY DEVICE AND CONTROLLER THEREOF - A method for performing meta block management is provided. The method is applied to a controller of a Flash memory having multiple channels, where the Flash memory includes a plurality of blocks respectively corresponding to the channels. The method includes: utilizing a meta block mapping table to store block grouping relationships respectively corresponding to a plurality of meta blocks, where blocks in each meta block respectively correspond to the channels; and when it is detected that a specific block corresponding to a specific channel within a meta block does not have remaining space for programming, according to the meta block mapping table, utilizing at least one blank block corresponding to the specific channel within at least one other meta block as extension of the specific block, for use of further programming. An associated memory device and a controller thereof are also provided. | 03-29-2012 |
20120079170 | METHOD FOR PERFORMING BLOCK MANAGEMENT, AND ASSOCIATED MEMORY DEVICE AND CONTROLLER THEREOF - A method for performing block management is provided. The method is applied to a controller of a Flash memory having multiple channels, where the Flash memory includes a plurality of blocks respectively corresponding to the channels. The method includes: obtaining at least one portion of a plurality of address-to-channel mapping relationships, for use of writing/programming operations; and according to at least one address-to-channel mapping relationship of the plurality of address-to-channel mapping relationships, programming at least one page of data into the Flash memory through at least one channel in a page mode. An associated memory device and a controller thereof are also provided. | 03-29-2012 |
20120079171 | Non-volatile memory systems and methods of managing power of the same - A non-volatile memory system and a method of managing the power of the same are provided. The non-volatile memory system includes a non-volatile memory configured to store a first mapping table comprising a list of a logical address and a physical address corresponding to the logical address with respect to a code region and a list of a logical address and a physical address corresponding to the logical address with respect to a general purpose (GP) region, and a controller configured to load the first mapping table from the non-volatile memory to a first memory and load the second mapping table from the non-volatile memory to a second memory. Power-up of the second memory is delayed with respect to power-up of the non-volatile memory system and the first or second memory is powered down if a condition is satisfied, so that power consumption of the non-volatile memory system is reduced. | 03-29-2012 |
20120079172 | MEMORY SYSTEM - Created is transfer order information indicating an order of transfer from multiple memory areas in accordance with an order of logical addresses and memory locations which are specified by read commands. Readout from the multiple memory areas in accordance with the transfer order information is performed by controlling memory controllers in accordance with the created transfer order information. | 03-29-2012 |
20120079173 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE WITH ADVANCED MULTI-PAGE PROGRAM OPERATION - A nonvolatile semiconductor memory device includes a memory cell array having a plurality of banks and a cache block corresponding to each of the plurality of banks. The cache block has a predetermined data storage capacity. A page buffer is included which corresponds to each of the plurality of banks. A programming circuit programs all of the plurality of banks except a last of said banks with page data. The page data is loaded through each page buffer and programmed into each cache block such that when page data for the last bank is loaded into the page buffer, the loaded page data and the page data programmed into the respective cache blocks are programmed into respective corresponding banks. | 03-29-2012 |
20120079174 | APPARATUS, SYSTEM, AND METHOD FOR A DIRECT INTERFACE BETWEEN A MEMORY CONTROLLER AND NON-VOLATILE MEMORY USING A COMMAND PROTOCOL - A method for a direct interface between a memory controller and a non-volatile memory controller using a command protocol includes receiving a command from a memory controller to a non-volatile memory controller over a wire interface by way of a command protocol. The memory controller is coupled to one or more processors and the non-volatile memory controller, in one embodiment, is coupled to non-volatile memory media. The command protocol includes a control path that enables the memory controller to distinguish among different memory modules. The non-volatile memory controller stores data sequentially on the non-volatile memory media to preserve an ordered sequence of memory operations performed on the non-volatile memory media. The method includes executing the command within the non-volatile memory controller in response to determining that the non-volatile memory controller is capable of satisfying the command. | 03-29-2012 |
20120079175 | APPARATUS, SYSTEM, AND METHOD FOR DATA TRANSFORMATIONS WITHIN A DATA STORAGE DEVICE - An apparatus, system, and method are disclosed for executing data transformations for a data storage device. A storage controller module executes a storage operation for a set of data within a data storage device. A transformation module determines to apply a data transformation to the set of data in response to a transformation indicator. A processing module applies the data transformation to the set of data internally on the data storage device prior to completing the storage operation. | 03-29-2012 |
20120079176 | MEMORY DEVICE - A multi-channel flash memory device comprising die-stacked flash memory dies. The flash memory device is compact due to the stacked dies arrangement while providing high speed performance due to its multiple data channel arrangement. A specific example is a flash memory comprising 4 stacked flash memory dies with 4 parallel data channels. This invention alleviates the bottle neck problems of know die-stacked flash memory devices. | 03-29-2012 |
20120079177 | MEMORY INTERLEAVE FOR HETEROGENEOUS COMPUTING - A memory interleave system for providing memory interleave for a heterogeneous computing system is provided. The memory interleave system effectively interleaves memory that is accessed by heterogeneous compute elements in different ways, such as via cache-block accesses by certain compute elements and via non-cache-block accesses by certain other compute elements. The heterogeneous computing system may comprise one or more cache-block oriented compute elements and one or more non-cache-block oriented compute elements that share access to a common main memory. The cache-block oriented compute elements access the memory via cache-block accesses (e.g., 64 bytes, per access), while the non-cache-block oriented compute elements access memory via sub-cache-block accesses (e.g., 8 bytes, per access). A memory interleave system is provided to optimize the interleaving across the system's memory banks to minimize hot spots resulting from the cache-block oriented and non-cache-block oriented accesses of the heterogeneous computing system. | 03-29-2012 |
20120079178 | METHOD AND SYSTEM FOR ADAPTIVE CODING IN FLASH MEMORIES - To store bits in one or more cells, an adaptive mapping of bits to ranges of a physical parameter of the cell(s) is provided, in accordance with respective initial values of the physical parameter, by steps including encoding the bits as a codeword by partitioning the bits into subsets and finding a factor bit string such that the codeword is a concatenation of the factor bit string and separate Galois field products of all the subsets with the factor bit string. The initial values of the physical parameter are adjusted accordingly as needed. | 03-29-2012 |
20120084489 | SYNCHRONIZED MAINTENANCE OPERATIONS IN A MULTI-BANK STORAGE SYSTEM - A method and system for managing maintenance operations in a multi-bank non-volatile storage device is disclosed. The method includes receiving a data write command and associated data from a host system for storage in the non-volatile storage device and directing a head of the data write command to a first bank in the and a tail of the data write command to a second bank, where the head of the data write command only includes data having logical block addresses preceding logical block addresses of data in the tail of the data write command. When a status of the first bank delays execution of the data write command the controller executes a second bank maintenance procedure in the second bank while the data write command directed to the first and second banks is pending. The system includes a plurality of banks, where each bank may be associated with the same or different controllers, and the one or more controllers are adapted to execute the method noted above. | 04-05-2012 |
20120084490 | METHOD FOR CHANGING READ PARAMETER FOR IMPROVING READ PERFORMANCE AND APPARATUSES USING THE SAME - A memory system including a non-volatile memory device and a memory controller is provided. When a read operation on a first data initially output from the non-volatile memory device during a first read operation is successful, the memory controller may change a read voltage for reading a second data stored in the non-volatile memory device during a second read operation. | 04-05-2012 |
20120084491 | Flash Memory for Code and Data Storage - A flash memory for code and data storage includes a code memory array having fast read access and suitability for execute in place, a data memory array having the characteristics of low bit cost and high density storage, and a suitable interface to provide access to both the code and data. The code memory array may be a NOR array or a performance-enhanced NAND array. The memory may be implemented in a single chip package or multi-chip package solution. | 04-05-2012 |
20120084492 | STORAGE SYSTEM LOGICAL BLOCK ADDRESS DE-ALLOCATION MANAGEMENT AND DATA HARDENING - Storage system Logical Block Address (LBA) de-allocation management and data hardening provide improvements in performance, efficiency, and utility of use. Optionally, LBA de-allocation information in a first format (e.g. associated with a first protocol) is converted to a second format (e.g. associated with a second protocol). An example of the first protocol is a Small Computer System Interface (SCSI) protocol, and an example of the second protocol is an Advanced Technology Attachment (ATA) protocol. Optionally, LBA de-allocation status information is determined by a storage device, such as a Solid-State Disk (SSD), and communicated to another device such as an initiator, expander, or bridge. Optionally, data stored on an SSD is hardened, such as in response to determining that the SSD is to be powered off. The hardening is via power supplied by an energy storage element, such as a super capacitor or a battery. | 04-05-2012 |
20120084493 | NON-VOLATILE MEMORY DEVICE HAVING ASSIGNABLE NETWORK IDENTIFICATION - Memory devices and methods disclosed such as a memory device having a plurality of memory dies where each die includes a network identification that uniquely identifies the memory die on a bus. Access for each memory die to the bus can be scheduled by a bus controller. | 04-05-2012 |
20120084494 | MEMORY FOR ACCESSING MULTIPLE SECTORS OF INFORMATION SUBSTANTIALLY CONCURRENTLY - A memory storage system of an embodiment includes a non-volatile memory unit and memory control circuitry coupled to the memory unit. The memory control circuitry is configured to access multiple sectors of information substantially concurrently. | 04-05-2012 |
20120084495 | SEMICONDUCTOR PROGRAMMABLE DEVICE - An ePLX unit includes a logic unit having an SRAM and a MUX, and a switch unit having an SRAM and a TG for establishing wiring connection in the logic unit. When a composite module is set in the first mode, an Add/Flag control unit uses the SRAMs as a data field and a flag field, respectively, to autonomously control the read address of each of the data field and the flag field in accordance with a control flag stored in the flag field. Furthermore, when the composite module is set in the second mode, the Add/Flag control unit writes configuration information into each of the SRAMs to reconfigure a logic circuit. Consequently, the granularity of the circuit configuration can be rendered variable, which allows improvement in flexibility when configuring a function. | 04-05-2012 |
20120089765 | METHOD FOR PERFORMING AUTOMATIC BOUNDARY ALIGNMENT AND RELATED NON-VOLATILE MEMORY DEVICE - A non-volatile memory device is configured to perform automatic boundary alignment between logical access units of a file system and physical access units of the non-volatile memory device. The file system of the non-volatile memory device is configured to include a partition having a system data area and a user data area which comprises a plurality of logical access units. The boundaries of the logical access units in the partition are aligned with the boundaries of physical access units of the non-volatile memory device. Unnecessary data access may be reduced without introducing an additional mapping table or re-formatting storage space in the partition. | 04-12-2012 |
20120089766 | NON-VOLATILE MEMORY STORAGE APPARATUS, MEMORY CONTROLLER AND DATA STORING METHOD - A non-volatile memory storage apparatus having a connector, an energy storage circuit, a power regulator and supply circuit, a non-volatile memory module, a memory controller and a buffer memory is provided. The power regulator and supply circuit is configured for transforming an output voltage from the energy storage circuit into a first voltage used for the non-volatile memory module and a second voltage used for the memory controller and the buffer memory. The memory controller is configured for writing data stored temporarily in the buffer memory into the non-volatile memory module with a special writing mode when receiving a detecting signal indicating that an input voltage is continuously smaller than a predetermined voltage for a predetermined period or receiving a detecting signal indicating that an inactive status of the connector or receiving a suspend mode signal, a warm reset signal or a hot reset signal from a host system. | 04-12-2012 |
20120089767 | STORAGE DEVICE AND RELATED LOCK MODE MANAGEMENT METHOD - A storage device comprises at least one nonvolatile memory and a lock mode management module. The lock mode management module places the storage device in a soft lock mode in which only predetermined writing operations are allowed, upon determining that a number of reserved blocks in a flash memory is less than or equal to a reference value. | 04-12-2012 |
20120089768 | STATIC WEAR LEVELING - Methods permitting erasures to be performed evenly over time in memory, thereby extending the service life of a data storage device, and devices operable to perform those methods. Erasures performed on a given physical block in memory are tracked by incrementing a corresponding erase count included in an entry associated with a logical block correlated with that physical block. Each of a plurality of physical blocks included in the memory is associated with logical zones such that each logical zone comprises a different portion of the physical blocks. An erase count indicator is determined for each logical zone. When the total number of erasures for the given physical block reaches a limit, the entry associated with the logical block correlated with that physical block is exchanged with another entry associated with a logical block correlated with a physical block in a logical zone having a lower count indicator. | 04-12-2012 |
20120089769 | METHOD AND APPARATUS FOR DISPLAY OF WINDOWING APPLICATION PROGRAMS ON A TERMINAL - An apparatus may include a network interface to facilitate communication with a second apparatus, and one or more machine-readable media with instructions executable by one or more processors to perform facilitating accessing a windows application resident on the second apparatus without executing locally the windows application resident on the second apparatus. An apparatus may facilitate providing windowing functionality to permit use of a windows application resident on the apparatus without requiring more than windowing information of the windows application to be provided. An apparatus may facilitate providing windowing information for display. An apparatus may facilitate provision of windowing information associated with a program executable on the apparatus configured to run a multi-user operating system, the program resident on the apparatus. One or more non-transitory machine-readable media are also disclosed. | 04-12-2012 |
20120089770 | FLASH MEMORY DEVICES WITH HIGH DATA TRANSMISSION RATES AND MEMORY SYSTEMS INCLUDING SUCH FLASH MEMORY DEVICES - A flash memory device includes a memory cell array, a clock signal input, an input for receiving a signal designating a writing operating mode, a plurality of data input/output pads, and a data input/output buffer circuit that is electrically connected to the clock signal input and to the plurality of data input/output pads. The data input/output buffer circuit is configured to receive data that is to be written to the memory cell array through the data input/output pads in synchronization with a clock signal that is applied to the clock signal input in response to activation of the signal designating the writing operating mode. | 04-12-2012 |
20120096214 | Working Method for Information Security Device with CF Interface and Working System Thereof - A working method for information security device with CF interface and working system thereof are disclosed in the invention. The method includes that the card reading apparatus sends instruction to the information security device with CF interface, and the information security device with CF interface determines the object being operated by the instruction, if the object is flash module in the information security device with CF interface, the information security device with CF interface operates the flash module as normal, or else if the object is information security chip of the information security device with CF interface, the information security device with CF interface performs information security operation on the information security chip;
| 04-19-2012 |
20120096215 | MEMORY CONTROLLER AND METHOD FOR ACCESSING A PLURALITY OF NON-VOLATILE MEMORY ARRAYS - A memory controller ( | 04-19-2012 |
20120096216 | Indexing Method for Flash Memory - An indexing method is based on a tree structure of a flash memory, which includes a plurality of pages. The indexing method stores an entry in the leaf node and an entry in an index node designating the leaf node, in the same page, and changes the maximum number of entries that are stored in the leaf node of the page and the maximum number of entries that are stored in the index node of the page on the basis of the number of entries in the leaf node and the number of entries in the index node, respectively. | 04-19-2012 |
20120096217 | FILE SYSTEM-AWARE SOLID-STATE STORAGE MANAGEMENT SYSTEM - A file system-aware SSD management system including an SSD management module that incorporates both file system information and information related to the underlying physical solid-state storage media into its operations is described. Also described are related methods for performing data management operations in a file system-aware manner. By incorporating both file system and physical storage information, the system may achieve various advantages over conventional systems, such as enhanced I/O performance, simplified SSD firmware, and extended SSD lifespan. Moreover, by moving solid-state management functions above the firmware level, the system may enable the simultaneous management of a pool of multiple SSDs. | 04-19-2012 |
20120096218 | APPARATUS AND METHODS FOR TUNING A MEMORY INTERFACE - The disclosure relates to an integrated circuit including programmable control logic configured to generate at least one data pattern sequence from a number of stored data patterns and using the generated at least one data pattern sequence to at least one of read from and write to at least one memory device. A method includes generating at least one data pattern sequence from a number of stored data patterns and writing and reading the data pattern sequence from and to a memory device. | 04-19-2012 |
20120102259 | Predictive Read Channel Configuration - The read channel of a solid state non-volatile memory may be configured to compensate for shifts in the threshold voltages of memory cells of the memory. A log of write time information and write temperature information from one or more write operations is stored in a data unit header. The read channel configuration, which may include reference voltages used for the read operation, is determined using the write time information and the write temperature information. Memory cells of the data unit are read using the configured read channel. A historical profile spanning multiple write operations may also be developed and used to configure the read channel. | 04-26-2012 |
20120102260 | STORAGE APPARATUS AND DATA CONTROL METHOD - Data capacity efficiency is improved by de-duplicating data assigned with a code that is different for each data. | 04-26-2012 |
20120102261 | Systems and Methods for Tiered Non-Volatile Storage - Various embodiments of the present invention provide systems and methods for tiered non-volatile storage. As an example, a multi-tiered non-volatile storage device is disclosed that includes a hard disk storage; a solid state, non-volatile storage that caches a subset of data included on the hard disk storage; and a controller circuit that is operable to control data transfer between the solid state, non-volatile storage and the hard disk storage | 04-26-2012 |
20120102262 | MEMORY CONTROL DEVICE, STORAGE DEVICE, AND MEMORY CONTROL METHOD - According to one embodiment, a memory control device includes: queues in channels; first controller; generator; and second controller. The queues hold write commands for data pieces. The first controller causes: (i) when a read command is received, and until the write commands are held in the queues, the channels are synchronized with each other, and processes of the write commands become ready to be performed, a read process based on the read command prior to the write commands; and, (ii) when the processes of write commands become ready to be performed, synchronization of the channels and write processes for the data pieces based on the write commands. The generator generates error correction codes based on the data pieces when the channels are synchronized with each other and the processes based on the write commands are performed. The second controller writes the error correction codes on the storage medium. | 04-26-2012 |
20120102263 | Solid State Drive Architecture - Embodiments of apparatuses, methods and systems of solid state drive are disclosed. One embodiment of a solid state drive includes a non-blocking fabric, wherein the non-blocking fabric comprises a plurality of ports, wherein a subset of the plurality of ports are each connected to a flash controller that is connected to at least one array of flash memory. Further, this embodiment includes a flash scheduler for scheduling data traffic through the non-blocking fabric, wherein the data traffic comprises a plurality of data packets, wherein the flash scheduler extracts flash fabric header information from each of the data packets and schedules the data traffic through the non-blocking fabric based on the extracted flash fabric header information. The scheduled data traffic provides transfer of data packets through the non-blocking fabric from at least one array of flash memory to at least one other array of flash memory. | 04-26-2012 |
20120102264 | MEMORY CONTROLLER, NONVOLATILE MEMORY DEVICE, ACCESS DEVICE, AND NONVOLATILE MEMORY SYSTEM - Without corresponding to different address spaces between an access device and a nonvolatile memory device, the access device designates a file ID to manage a data storing state only in a physical address space in the nonvolatile memory device. The access device sends the nonvolatile memory device a transfer rate through a transfer rate transmitting unit. A filling-up rate calculating unit calculates a filling-up rate of a physical block corresponding to an assurance speed required by the access device. A remaining amount corresponding to the transfer rate is sought by using the calculated filling-up rate and is transmitted to a remaining amount receiving unit of the access device. | 04-26-2012 |
20120102265 | Aggregation of Write Traffic to a Data Store - A method and a processing device are provided for sequentially aggregating data to a write log included in a volume of a random-access medium. When data of a received write request is determined to be suitable for sequentially aggregating to a write log, the data may be written to the write log and a remapping tree, for mapping originally intended destinations on the random-access medium to one or more corresponding entries in the write log, may be maintained and updated. At time periods, a checkpoint may be written to the write log. The checkpoint may include information describing entries of the write log. One or more of the checkpoints may be used to recover the write log, at least partially, after a dirty shutdown. Entries of the write log may be drained to respective originally intended destinations upon an occurrence of one of a number of conditions. | 04-26-2012 |
20120102266 | Method And System For Storage Of Data - A method and a system are disclosed for storing initial data from an image detecting device in a camera system initial storage medium and making the data accessible. The initial data is stored consecutively in blocks, where file specific pointers representing the starting address for each stored file and file sequence, and dynamic memory pointers that points out the next writable address, are managed and stored during real time writing of the data. The data is made accessible through a virtual representation of the data in a virtual file system with a format known by an external storage medium controller, the virtual representation being related to the file specific pointers. | 04-26-2012 |
20120110239 | Causing Related Data to be Written Together to Non-Volatile, Solid State Memory - A first write request that is associated with a first logical address is received via a collection of write requests targeted to a non-volatile, solid state memory. It is determined whether the logical address is related to logical addresses of one or more other write requests of the collection that are not proximately ordered with the first write request in the collection. In response to this determination, the first write request and the one or more other write requests are written together to the memory. | 05-03-2012 |
20120110240 | Method and System for Memory Controller Calibration - A method for calibration of a memory controller may include determining if an unused memory location exists in memory. The method may include writing a first pattern to the unused memory location in response to a determination that the unused memory location exists. The method may include determining if a second pattern exists in the memory in response to a determination that the unused memory location does not exist. The method may include iteratively modifying a first delay of a first delay control module among a plurality of delay values. The method may include reading from a memory location including the first pattern or the second pattern for each iteration of modification of the first delay. The method may include modifying one or more second delays, each second delay associated with one of one or more second delay control modules, based on the results of reading from the memory location. | 05-03-2012 |
20120110241 | SYSTEM FOR NAND FLASH PARAMETER AUTO-DETECTION - A system comprising a NAND flash memory device having a multiplicity of parameters; a flash controller configured to perform a NAND flash memory parameter automatic detection process including reading a device identifier of the NAND flash memory device and proceeding if a valid device identifier value is returned, detecting an address cycle and a block type of the NAND flash memory device, detecting a page size of the NAND flash memory device, detecting a spare size of the NAND flash memory device, detecting a memory size of the NAND flash memory device, and detecting a block size of the NAND flash memory device. | 05-03-2012 |
20120110242 | PROGRAMMABLE MEMORY CONTROLLER - A memory controller, in one embodiment, includes a command translation data structure, a front end and a back end. The command translation data structure maps command operations to primitives, wherein the primitives are decomposed from command operations determined for one or more memory devices. The front end receives command operations from a processing unit and translates each command operation to a set of one or more corresponding primitives using the command translation data structure. The back end outputs the set of one or more corresponding primitives for each received command operation to a given memory device. | 05-03-2012 |
20120110243 | DATA WRITING METHOD, MEMORY CONTROLLER, AND MEMORY STORAGE APPARATUS - A data writing method for a rewritable non-volatile memory module is provided, the rewritable non-volatile memory module has a plurality of physical blocks, each of the physical blocks has a plurality of physical pages, a portion of the physical blocks are mapped to a plurality of logical blocks, and each of the logical blocks has a plurality of logical pages. The data writing method includes receiving data, and the data has a plurality of data bits and belongs to one of the logical pages. The data writing method also includes determining whether each of the data bits is a specific value. The data writing method further includes not writing the data into the physical pages when each of the data bits is the specific value. Thereby, the performance of a memory storage apparatus is improved. | 05-03-2012 |
20120110244 | COPYBACK OPERATIONS - Methods and systems for copyback operations are described. One or more methods include reading data from a first memory unit of a memory device responsive to a copyback command, performing signal processing on the data using a signal processing component local to the memory device, and programming the data to a second memory unit of the memory device. | 05-03-2012 |
20120110245 | Data writing method and writing device for an electronic erasable read only dynamic memory - A data writing method for an EEPROM in an electronic device is performed by a writing device. The electronic device includes a system unit generating a system voltage and a write-protection voltage. The writing device includes a processor stored with data to be written, and connected electrically to a connector with the same interface as that of an expansion connector of the electronic device. When the connector is connected electrically to the expansion connector, the processor generates a write-enable voltage greater than the system voltage upon receipt of the system voltage from the electronic device, and outputs the write-enable voltage to the system unit. The system unit raises the system voltage in response to the write-enable voltage such that the write-protection voltage is smaller than the raised system voltage to thereby enable the EEPROM to operate in a write state, where the processing unit writes the data into the EEPROM. | 05-03-2012 |
20120110246 | EXECUTE-IN-PLACE MODE CONFIGURATION FOR SERIAL NON-VOLATILE MEMORY - Example embodiments for configuring a serial non-volatile memory device for an execute-in-place mode may comprise a non-volatile configuration register to store an execute-in-place mode value that may be read at least in part in response to power being applied to the memory device. | 05-03-2012 |
20120110247 | MANAGEMENT OF CACHE MEMORY IN A FLASH CACHE ARCHITECTURE - A method for managing cache memory in a flash cache architecture. The method includes providing a storage cache controller, at least a flash memory comprising a flash controller, and at least a backend storage device, and maintaining read cache metadata for tracking on the flash memory cached data to be read, and write cache metadata for tracking on the flash memory data expected to be cached. | 05-03-2012 |
20120110248 | ELECTRONIC FLASH MEMORY EXTERNAL STORAGE METHOD AND DEVICE - An electronic flash memory external storage method and device for data processing system includes firmware which directly controls the access of electronic storage media and implements standard interface functions, adopts particular reading and writing formats of the external storage media, receives power via USB, externally stores data by flash memory and access control circuit with the cooperation of the firmware and the driver with the operating system, and has write-protection so that the data can be safely transferred. The method according to present invention is highly efficient and all parts involved are assembled as a monolithic piece so that it has large-capacity with small size and high speed. The device operates in static state and is driven by software. It is plug-and-play and adapted to data processing system. | 05-03-2012 |
20120110249 | MEMORY SYSTEM, DATA STORAGE DEVICE, USER DEVICE AND DATA MANAGEMENT METHOD THEREOF - A data management method of a data storage device having a data management unit different from a data management unit of a user device receives information regarding a storage area of a file to be deleted, from the user device, selects a storage area which matches with the data management unit of the data storage device, from among the storage area of the deleted file, and performs an erasing operation on the selected storage area which matches with the data management unit. | 05-03-2012 |
20120110250 | MEETHOD, SYSTEM AND COMPUTER READABLE MEDIUM FOR COPY BACK - Systems, computer readable media and methods for updating a flash memory device involve procedures for transferring, from a flash memory device to an external controller, only a portion of a data entity; and determining, by the external controller, based upon the portion of the data entity, whether to complete a copy back operation of the data entity or to correct errors of the data entity. If it is determined to correct errors of the data entity, then the procedure includes (a) completing a transfer of the data entity to the external controller; (b) error correcting the data entity to provide an amended data entity; and (c) writing the amended data entity to the flash memory device. If, however, it is determined to complete the copy back operation then the procedures includes completing the copy back operation of the data entity by transferring the data entity within the flash memory device. | 05-03-2012 |
20120110251 | PROCESSOR-BUS-CONNECTED FLASH STORAGE MODULE - A system includes multiple nodes coupled using a network of processor buses. The multiple nodes include a first processor node, including one or more processing cores and main memory, and a flash memory node coupled to the first processor node via a first processor bus of the network of processor buses. The flash memory node includes a flash memory including flash pages, a first memory including a cache partition for storing cached flash pages for the flash pages in the flash memory and a control partition for storing cache control data and contexts of requests to access the flash pages, and a logic module including a direct memory access (DMA) register and configured to receive a first request from the first processor node via the first processor bus to access the flash pages. | 05-03-2012 |
20120110252 | System and Method for Providing Performance-Enhanced Rebuild of a Solid-State Drive (SSD) in a Solid-State Drive Hard Disk Drive (SSD HDD) Redundant Array of Inexpensive Disks 1 (Raid 1) Pair - The present invention is a method for implementing a storage system. The storage system may include a disk array having a disk drive pair which includes a solid-state disk drive and a hard disk drive. The method may include the step of copying a data subset of a data set from the hard disk drive to a spare solid-state disk drive during a solid-state disk drive rebuild process. The data subset includes a first amount of data and the data set includes a second amount of data, where the first amount of data is less than the second amount of data. The method may further include the step of receiving a read request from a host server requesting the data subset. The method further includes the step of directing the read command to the spare solid-state disk drive. | 05-03-2012 |
20120110253 | COMBINED MEMORY AND STORAGE DEVICE IN AN APPARATUS FOR DATA PROCESSING - The invention concerns an apparatus for data processing comprising a central processing unit and a non volatile random access memory. The central processing unit and the non volatile random access memory are connected via a memory bus. The data related to an operating system for running said apparatus is at least partly stored in said non volatile random access memory and the memory used by the operating system for operating said apparatus is at least partly said non volatile memory. | 05-03-2012 |
20120117303 | METADATA STORAGE ASSOCIATED WITH FLASH TRANSLATION LAYER - Subject matter disclosed herein relates to storing information via a NAND flash translation layer. | 05-10-2012 |
20120117304 | MANAGING MEMORY WITH LIMITED WRITE CYCLES IN HETEROGENEOUS MEMORY SYSTEMS - A method and a memory manager for managing data storage in a plurality of types of memories. The types of memories may comprise a primary memory, such as DRAM, and a secondary memory, such as a phase change memory (PCM) or Flash memory, which may have a limited lifetime. The memory manager may be part of an operating system and may manage the memories as part of a unified address space. Characteristics of data to be stored in the memories may be used to select between the primary and secondary memories to store the data and move data between the memories. When the data is to be stored in the secondary memory, health information on the secondary memory and characteristics of the data to be stored may be used to select a location within the secondary memory to store the data. | 05-10-2012 |
20120117305 | Method Of Storing Blocks Of Data In A Plurality Of Memory Devices For High Speed Sequential Read, A Memory Controller And A Memory System - A method for controlling the storage of a plurality of blocks of sequential data in a plurality of independent NAND memory devices, where each NAND memory device can be independently written to or read from in a block of data, with the block as the minimum unit of storage to be written to or read from. The method includes assigning a different NAND memory device to each different block of data received for storage and for storing the plurality of blocks of data in the plurality of different NAND memory devices. Efficiency of readout of sequential blocks of data is improved. The present invention also comprises a memory controller having a processor and a non-volatile memory for storing programming code that can perform the foregoing method. Finally, the present invention is a memory system that has a plurality of NAND memory devices device that can be independently written to or read from in a block of data, with the block as the minimum unit of storage to be written to or read from. The memory system further has a memory controller that has a processor and non-volatile memory for storing programming code that can be executed by the processor in accordance with the foregoing described method. | 05-10-2012 |
20120117306 | SENSE OPERATION FLAGS IN A MEMORY DEVICE - Memory devices, methods for programming sense flags, methods for sensing flags, and memory systems are disclosed. In one such memory device, the odd bit lines of a flag memory cell array are connected with a short circuit to a dynamic data cache. The even bit lines of the flag memory cell array are disconnected from the dynamic data cache. When an even page of a main memory cell array is read, the odd flag memory cells, comprising flag data, are read at the same time so that it can be determined whether the odd page of the main memory cell array has been programmed. If the flag data indicates that the odd page has not been programmed, threshold voltage windows can be adjusted to determine the states of the sensed even memory cell page. | 05-10-2012 |
20120117307 | NON-VOLATILE MEMORY (NVM) ERASE OPERATION WITH BROWNOUT RECOVERY TECHNIQUE - A method for erasing a non-volatile memory includes: performing a first pre-erase program step on the non-volatile memory; determining that the non-volatile memory failed to program correctly during the first pre-erase program step; performing a first soft program step on the non-volatile memory in response to determining that the non-volatile memory failed to program correctly; determining that the non-volatile memory soft programmed correctly; performing a second pre-erase program step on the non-volatile memory in response to determining that the non-volatile memory soft programmed correctly during the first soft program step; and performing an erase step on the non-volatile memory. The method may be performed using a non-volatile memory controller. | 05-10-2012 |
20120117308 | DATA PROTECTION DEVICE AND METHOD THEREOF - A data protection device includes a basic input output system chip and a main control chip. The basic input output system chip stores basic input output system program and includes a write protection pin and a plurality of status registers. The main control chip includes a plurality of general purpose input output pins. One general purpose input output pin is electrically connected to the write protection pin of the basic input output system chip, the voltage level of the general purpose input output pin is controlled by performing different command programs of the basic input output system program, and the status registers and the basic input output system chip are selectable to be in a write protection mode or a writable mode under the control of the voltage level of the write protection pin of the basic input output system chip. | 05-10-2012 |
20120117309 | NAND FLASH-BASED SOLID STATE DRIVE AND METHOD OF OPERATION - A solid state drive that uses over-provisioning of NAND flash memory blocks as part of housekeeping functionality, including deduplication and coalescence of data for efficient usage of NAND flash memory devices and maintaining sufficient numbers of erased blocks to promote write performance. | 05-10-2012 |
20120117310 | USB FLASH DRIVE AND METHOD FOR SWITCHING FUNCTIONS OF THE USB FLASH DRIVE - A system and a method for switching functions of A Universal Serial Bus (USB) flash drive includes setting a bilateral switch under a first triggered status represents that the USB flash drive is in a boot mode, and under a second triggered status represents that the USB flash drive is in a memory mode. The switching method further includes a determination of whether the USB flash drive is in the boot mode, according to the triggered status of the bilateral switch. The switching method further includes controlling the host controller to access data in a flash memory in the USB flash drive, if the USB flash drive is in the boot mode; or controlling the host controller to access data in a main flash memory section in the flash memory if the USB flash drive is in the boot mode. | 05-10-2012 |
20120117311 | Memory System And Method Of Operating A Memory System - A memory system according to at least one example embodiment stores meta data in a cache register when the memory system enters a standby mode. Therefore, the memory system may reduce power consumption in the standby mode, and/or rapidly perform a mode switch. | 05-10-2012 |
20120117312 | Hybrid Server with Heterogeneous Memory - A method, hybrid server system, and computer program product, for managing access to data stored on the hybrid server system. A memory system residing at a server is partitioned into a first set of memory managed by the server and a second set of memory managed by a set of accelerator systems. The set of accelerator systems are communicatively coupled to the server. The memory system comprises heterogeneous memory types. A data set stored within at least one of the first set of memory and the second set of memory that is associated with at least one accelerator system in the set of accelerator systems is identified. The data set is transformed from a first format to a second format, wherein the second format is a format required by the at least one accelerator system. | 05-10-2012 |
20120117313 | MEMORY DEVICE PROGRAM WINDOW ADJUSTMENT - In one or more embodiments, a memory device is disclosed as having an adjustable programming window having a plurality of programmable levels. The programming window is moved to compensate for changes in reliable program and erase thresholds achievable as the memory device experiences factors such as erase/program cycles that change the program window. The initial programming window is determined prior to an initial erase/program cycle. The programming levels are then moved as the programming window changes, such that the plurality of programmable levels still remain within the program window and are tracked with the program window changes. | 05-10-2012 |
20120117314 | MEMORY DEVICES OPERATED WITHIN A COMMUNICATION PROTOCOL STANDARD TIMEOUT REQUIREMENT - The present disclosure includes methods and devices for logical memory blocks. One method for operating a memory device includes receiving a command to operate X pages of the memory device, X being greater than Y, and executing the command by executing multiple subcommands, each subcommand operating on a logical memory block portion of the X pages, each logical memory block including at most Y pages. T is a timeout limit, N is a number of pages comprising a block of memory, and Y is number of pages that can be operated within time T. | 05-10-2012 |
20120117315 | SEMICONDUCTOR MEMORY CARD - According to one embodiment, a semiconductor memory card includes a first pin group which includes a plurality of pins arranged in a line at an end portion on a side of an inserting direction into a connector and part of which is used both in a first and second modes; and a second pin group which includes a plurality of pins including at least two pin pairs for differential signal, is arranged so that a ground is positioned on both sides of each of the pin pairs for differential signal, and is used only in the second mode. In the second mode, among the respective pins configuring the first pin group, any of adjacent two pins are changed to a pin pair for differential clock signal, and a function of remaining pins of the first pin group is stopped. | 05-10-2012 |
20120117316 | SEMICONDUCTOR DEVICE HAVING STACKED ARRAY STRUCTURE, NAND FLASH MEMORY ARRAY USING THE SAME AND FABRICATION THEREOF - The present invention relates to a semiconductor device, a memory array and a fabrication method thereof, and more particularly to a semiconductor device having a stacked array structure (referred to as a STAR structure: a STacked ARray structure) applicable to not only a switch device but also a memory device, a NAND flash memory array using the same as a memory device and a fabrication method thereof. | 05-10-2012 |
20120117317 | ATOMIC MEMORY DEVICE - In an integrated-circuit memory device having a memory core, a first data value is retrieved from an address-specified location within the memory core in response to a memory access command. The first data value is output from the memory device in response to the memory access command, and a second data value is stored in the address-specified location within the memory core in response to the memory access command. | 05-10-2012 |
20120124272 | FLASH MEMORY APPARATUS - A flash memory apparatus including a command analysis unit, a first flash memory and a second flash memory is provided. The command analysis unit with a plurality of command buffers receives a plurality of command elements and queues the command elements in the command buffers in sequence. The command analysis unit transmits the command elements simultaneously to the first flash memory and the second flash memory through a command bus, and the flash memory device writes/reads the first flash memory and the second flash memory simultaneously through a first data bus and a second data bus different from the first data bus respectively to execute an operation. The flash memory device queues the command elements so as to enhance the command throughput, and the flash memories share the same command bus for dual channel operation. | 05-17-2012 |
20120124273 | Estimating Wear of Non-Volatile, Solid State Memory - Completion times of data storage operations targeted to a non-volatile, solid-state memory device are measured. Wear of the memory device is estimated using the measured completion times, and life cycle management operations are performed to affect subsequent wear of the memory device in accordance with the estimated wear. The life cycle management may include operations such as wear leveling, predicting an end of service life of the memory device, and removing worn blocks of the memory device from service. | 05-17-2012 |
20120124274 | Automatic guided flash disk and its operation method - The present invention provides an automatic guided flash disk and its operation method. When the present invention is plugged into a computer's port by a user, a request to connect a Human Interface Device (HID) is issued to a computer by a human interface device module in a control unit and the computer's status is determined by a system status decision module and taken as references of a character auto-entering module which regularly enables the computer's resident programs or activates a website by entering at least one character frequency. | 05-17-2012 |
20120124275 | MEMORY SYSTEM AND DATA STORAGE METHOD - According to one embodiment, a memory system includes a volatile memory, a first non-volatile memory connected to the volatile memory, a second non-volatile memory connected to the volatile semiconductor memory, and a memory controller. The memory controller is configured to store latest management information to the volatile memory, to store previous management information to the first non-volatile memory, and to store difference data between the latest management information and the previous management information to the second non-volatile memory. | 05-17-2012 |
20120124276 | DATA STORAGE DEVICE, USER DEVICE AND DATA WRITE METHOD - Disclosed is an address mapping method for a data storage device using a hybrid mapping scheme. The address mapping method determines whether write data includes a defined super sequential block (SSB), and selects an address mapping mode for the write data in accordance with whether or not a SSB is present. | 05-17-2012 |
20120124277 | SYSTEM AND METHOD FOR INCREASING CAPACITY, PERFORMANCE, AND FLEXIBILITY OF FLASH STORAGE - In one embodiment, an interface circuit is configured to couple to one or more flash memory devices and is further configured to couple to a host system. The interface circuit is configured to present at least one virtual flash memory device to the host system, wherein the interface circuit is configured to implement the virtual flash memory device using the one or more flash memory devices to which the interface circuit is coupled. | 05-17-2012 |
20120124278 | MEMORY SYSTEM FOR PORTABLE TELEPHONE - A memory system is constituted of a file storage flash memory storing a control program required for a control portion and a large amount of data, and a random access memory storing a program used by the control portion and functioning as a buffer memory for received data. Thus, a memory system for a portable telephone capable of storing a large amount of received data at high-speed and allowing reading of the stored data at high-speed is provided. | 05-17-2012 |
20120124279 | SYSTEM AND METHOD FOR SETTING ACCESS AND MODIFICATION FOR SYNCHRONOUS SERIAL INTERFACE NAND - The invention includes a system and method of modifying a setting of a NAND flash memory device using serial peripheral interface (SPI) communication from a master to the NAND flash memory device. One embodiment generally includes sending an enable signal to a first memory circuit input, sending a clock signal to a second memory circuit input, sending a command signal synchronized to the clock signal to a third memory circuit input, sending a memory register address signal synchronized to the clock signal to the third memory circuit input, and sending a setting signal synchronized to the clock signal to the third memory circuit input. | 05-17-2012 |
20120131261 | SUB-BLOCK ACCESSIBLE NONVOLATILE MEMORY CACHE - Subject matter disclosed herein relates to sub-block accessible cache memory. | 05-24-2012 |
20120131262 | Method and Apparatus for EEPROM Emulation for Preventing Data Loss in the Event of a Flash Block Failure - A defect resistant EEPROM emulator ( | 05-24-2012 |
20120131263 | MEMORY STORAGE DEVICE, MEMORY CONTROLLER THEREOF, AND METHOD FOR RESPONDING HOST COMMAND - A memory storage device, a memory controller thereof, and a method for responding host commands are provided. The memory storage device has a flash memory chip and a buffer memory. The present method includes receiving a write command issued by a host system and determining whether the write command causes the memory storage device to trigger a data moving procedure. If the write command does not cause the memory storage device to trigger the data moving procedure, the present method further includes sending an acknowledgement message corresponding to the write command to the host system after data corresponding to the write command is completely transferred to the buffer memory. | 05-24-2012 |
20120131264 | STORAGE DEVICE - According to one embodiment, a storage device comprises a first storage unit having blocks, each including pages, a second storage unit having a free block list, and a free page list, and a control unit. In write data in units of blocks, the control unit generates compressed data blocks by compressing the data in units of blocks, writes the compressed data blocks to the blocks which can be written in accordance with the information held in the free block list, holds, in the free page list, the information about pages existing in free areas which are provided in the blocks holding compressed data blocks and which holds no compressed data blocks. In write data in units of pages, the control unit writes the data in units of pages to pages existing in the free areas, in accordance with the information held in the free page list. | 05-24-2012 |
20120131265 | WRITE CACHE STRUCTURE IN A STORAGE SYSTEM - A method of writing data units to a storage device. The data units are cached in a first level cache sorted by logical address. A group (G | 05-24-2012 |
20120131266 | MEMORY CONTROLLER, DATA STORAGE SYSTEM INCLUDING THE SAME, METHOD OF PROCESSING DATA - A data storage system includes a controller configured to receive data and data information about the data from a host, analyze the data information, detect whether the data has been compressed, and compress the data according to a detection result; and a nonvolatile memory device configured to store the data compressed by the controller and information about whether the data has been compressed. The controller includes a buffer configured to temporarily store the data and the data information received from the host, an analyzer configured to output, based on an analysis result, a compression control flag that indicates whether the data has been compressed, and a compressor configured to selectively compress or bypass the data based on the compression control flag, and to transmit the data to the nonvolatile memory device. | 05-24-2012 |
20120131267 | MEMORY DEVICE DISTRIBUTED CONTROLLER SYSTEM - A memory device distributed controller circuit distributes memory control functions amongst a plurality of memory controllers. A master controller receives an interpreted command and activates the appropriate slave controllers depending on the command. The slave controllers can include a data cache controller that is coupled to and controls the data cache and an analog controller that is coupled to and controls the analog voltage generation circuit. The respective controllers have appropriate software/firmware instructions that determine the response the respective controllers take in response to the received command. | 05-24-2012 |
20120131268 | DATA STORAGE DEVICE - A data storage device comprising: at least two flash devices for storing data; a circuit board, wherein each of the flash devices are integrated on the circuit board; a controller integrated on the circuit board for reading and writing to each flash devices, wherein the controller interfaces each flash devices; at least one NOR Flash device in communication with the controller through a host bus; at least one host bus memory device in communication with the controller and at least one NOR Flash device through the host bus; at least one interface in communication with the controller and adapted to physically and electrically couple to a system, receive and store data therefrom and retrieve and transmit data to the system. | 05-24-2012 |
20120131269 | ADAPTIVE MEMORY SYSTEM FOR ENHANCING THE PERFORMANCE OF AN EXTERNAL COMPUTING DEVICE - An adaptive memory system is provided for improving the performance of an external computing device. The adaptive memory system includes a single controller, a first memory type (e.g., Static Random Access Memory or SRAM), a second memory type (e.g., Dynamic Random Access Memory or DRAM), a third memory type (e.g., Flash), an internal bus system, and an external bus interface. The single controller is configured to: (i) communicate with all three memory types using the internal bus system; (ii) communicate with the external computing device using the external bus interface; and (iii) allocate cache-data storage assignment to a storage space within the first memory type, and after the storage space within the first memory type is determined to be full, allocate cache-data storage assignment to a storage space within the second memory type. | 05-24-2012 |
20120131270 | STORAGE SYSTEM AND CONTROL METHOD THEREOF - Proposed are a storage system and its control method capable of dealing with the unique problems that arise when using a nonvolatile memory as the memory device while effectively preventing performance deterioration. This storage system is provided with a plurality of memory modules having one or more nonvolatile memory chips, and a controller for controlling the reading and writing of data from and in each memory module. The memory module decides the nonvolatile memory chip to become a copy destination of data stored in the nonvolatile memory when a failure occurs in the nonvolatile memory chip of a self memory module, and copies the data stored in the failed nonvolatile memory chip to the nonvolatile memory chip decided as the copy destination. | 05-24-2012 |
20120137047 | MEMORY SANITATION USING BIT-INVERTED DATA - Method and apparatus for sanitizing a memory using bit-inverted data. In accordance with various embodiments, a memory location is sanitized by sequential steps of reading a bit value stored in a selected memory cell of the memory, inverting the bit value, and writing the inverted bit value back to the selected memory cell. The memory cell may be erased between the reading and writing steps, as well as after the writing step. Random bit values may be generated and stored to the memory cell, and run-length limited constraints can be used to force bit-inversions. | 05-31-2012 |
20120137048 | METHOD AND APPARATUS FOR IMPROVING ENDURANCE OF FLASH MEMORIES - A method and apparatus for improving the endurance of flash memories. In one embodiment of the invention, a high electric field is provided to the control gate of a flash memory module. The high electric field applied to the flash memory module removes trapped charges between a control gate and an active area of the flash memory module. In one embodiment of the invention, the high electric field is applied to the control gate of the flash memory module prior to an erase operation of the flash memory module. By applying a high electric field to the control gate of the flash memory module, embodiments of the invention improve the Program/Erase cycling degradation of the single-level or multi-level cells of the flash memory module. | 05-31-2012 |
20120137049 | CODE PATCHING FOR NON-VOLATILE MEMORY - Example embodiments described herein may comprise a transfer of firmware execution within a non-volatile memory device to one or more replacement instructions at least in part in response to a match between a code fetch address and an address stored n a trap address register. | 05-31-2012 |
20120137050 | ELECTRONIC DEVICES WITH IMPROVED FLASH MEMORY COMPATIBILITY AND METHODS CORRESPONDING THERETO - An electronic device with improved flash memory compatibility and a method corresponding thereto are disclosed. The electronic device has a NAND flash, a processing unit and a program memory. The program memory stores application software and codes of an operating system, to be retrieved and executed by the processing unit. The application software requests for NAND flash access in accordance with a specific page size. The operating system acts as an intermediary between the application software and the NAND flash and provides a device driver which allocates a number of physical pages of the NAND flash to each virtual page of the specific page size for responding to NAND flash access requests from the application software by referring to the virtual pages. | 05-31-2012 |
20120137051 | MEMORY DEVICE CONFIGURED TO EXECUTE PLURAL ACCESS COMMANDS IN PARALLEL AND MEMORY ACCESS METHOD THEREFOR - According to one embodiment, a memory device includes a memory, a memory interface, a command generator, an access command returning module and a command progress manager. The memory interface accesses the memory in parallel in accordance with access commands. The command generator speculatively issues access commands to the memory interface. The access command returning module returns access commands already issued to the memory interface and unexecuted at a time of occurrence of an error, through corresponding purge responses. The command progress manager updates command progress management information such that the command progress management information indicates the oldest one of the unexecuted access commands. The command generator reissues the returned unexecuted access commands to the memory interface based on the updated command progress management information. | 05-31-2012 |
20120137052 | STORAGE DEVICE AND CONTROL METHOD - According to one embodiment, a storage device includes identification information storage module, location information storage module, determination module, and control module. The identification information storage module stores identification information identifying nonvolatile memories. The location information storage module stores location information identifying bad area in the nonvolatile memories. The determination module determines whether each of pieces of identification information stored in each of the nonvolatile memories matches with any one of the pieces of identification information stored in the identification information storage module. The control module controls one of the nonvolatile memories to prevent one of the pieces of location information from being used, and to prevent access from the host, when the determination module determines that the one of the pieces of identification information of the one of the nonvolatile memories does not match with any one of the pieces of identification information stored in the identification information storage module. | 05-31-2012 |
20120137053 | MICROPROCESSOR - A microprocessor to be connected with an external device is disclosed. The microprocessor includes a non-rewritable memory including a first interrupt vector table storing addresses of plural programs that allow plural types of interrupts, and an area storing a processing program in an address indicated by each of vectors in the first interrupt vector table; a rewritable non-volatile memory including a second interrupt vector table that includes contents identical to contents of the first interrupt vector table; an address changing section that conducts address change from an address for accessing the first interrupt vector table to another address for accessing the second interrupt vector table; a writing section that writes an address of an arbitrary vector of the second interrupt vector table and a processing program stored in the address indicated by the arbitrary vector in the rewritable non-volatile memory upon instruction supplied from the external device. | 05-31-2012 |
20120137054 | METHODS AND SYSTEMS FOR OBJECT LEVEL DE-DUPLICATION FOR SOLID STATE DEVICES - In one aspect, the present disclosure relates to a method of de-duplicating data in a solid state storage device. The method can include receiving a block of data to be written to a solid state storage device, wherein the block of data comprises header portion and a payload, wherein the header portion comprises context information; and determining whether the payload should be de-duplicated prior to storage, based on the context information stored within the header portion; if the payload is determined to be de-duplicated, de-duplicating the payload; and storing the de-duplicated payload to the solid state storage device. | 05-31-2012 |
20120137055 | HYBRID MEMORY SYSTEM AND METHOD MANAGING THE SAME - A hybrid memory system includes a central processing unit, a storage device configured to store user data and code data, and a main memory including a volatile memory and a nonvolatile memory, the main memory being configured to receive data necessary to perform an operation of the central processing unit from the storage device and to store the data, a part of the volatile memory being allocated for a cache for data stored in the nonvolatile memory. | 05-31-2012 |
20120137056 | METHODS AND APPARATUS READING ERASE BLOCK MANAGEMENT DATA - Methods of operating memory devices, and memory devices configured to perform such methods, including reading Erase Block Management (EBM) data from an erase block of an array of memory cells. The EBM data, corresponding to a state of the particular erase block, is stored in control data spaces of a subset of sectors of the particular erase block. | 05-31-2012 |
20120137057 | MEMORY DEVICE - A memory device includes a nonvolatile memory and a controller. The nonvolatile memory includes a storage area having a plurality of memory blocks each including a plurality of nonvolatile memory cells, and a buffer including a plurality of nonvolatile memory cells and configured to temporarily store data, and in which data is erased for each block. If a size of write data related to one write command is not more than a predetermined size, the controller writes the write data to the buffer. | 05-31-2012 |
20120137058 | SEMICONDUCTOR DEVICE - A high-speed large-capacity phase-change memory is achieved. A semiconductor device according to the present invention includes: a plurality of memory planes MP; a plurality of storage information register groups SDRBK paired with the plurality of memory planes; and a chip control circuit CPCTL. The plurality of memory planes include a plurality of memory cells. Also, the plurality of storage information register groups temporarily retain information to be stored in the plurality of memory planes. Further, the chip control circuit includes a register which temporarily stores a value indicating volume of the storage information, and a first storage information volume is smaller than a second storage information volume. When the first storage information volume is written, the plurality of memory planes and the plurality of storage information register groups are activated during a first period. When the second storage information volume is written, the plurality of memory planes and the plurality of storage information register groups are activated during a second period. By such a structure, the first period is shorter than the second period. | 05-31-2012 |
20120144092 | EFFICIENT CACHE MANAGEMENT - A method of managing memory of a computing device includes providing a first memory that can be allocated as cache memory or that can be used by a computing device component. A first memory segment can be allocated as cache memory in response to a cache miss. Cache size can be dynamically increased by allocating additional first memory segments as cache memory in response to subsequent cache misses. Cache memory size can be dynamically decreased by reallocating first memory cache segments for use by computing device components. The cache memory can be a cache for a second memory accessible to the computing device. The computing device can be a mobile device. The first memory can be an embedded memory and the second memory can comprise embedded, removable or external memory, or any combination thereof. The maximum size of the cache memory scales with the size of the first memory. | 06-07-2012 |
20120144093 | INTERLEAVING CODEWORD PORTIONS BETWEEN MULTIPLE PLANES AND/OR DIES OF A FLASH MEMORY DEVICE - A system, a method and non-transitory computer readable medium storing instructions for interleaving at least two portions of a first codeword of the group between at least two flash memory planes while violating at least one ordering rule out of (a) an even odd ordering rule, (b) a programming type ordering rule, and (c) a codeword portions ordering rule and interleaving different portions of other codewords of the group between multiple flash memory planes while maintaining the even odd ordering rule, the programming type ordering rule and the codeword portions ordering rule. | 06-07-2012 |
20120144094 | DATA STORAGE APPARATUS AND METHOD FOR CONTROLLING FLASH MEMORY - According to one embodiment, a data storage apparatus includes a write command module, a read command module, and a controller. The write command module is configured to process a write command for writing data to the nonvolatile memories for a plurality of channels, respectively. The read command module is configured to process a read command usually and to process a read command for read modify write (RMW) operation. The controller is configured to control the read command module, causing to execute the read command for the RMW operation, prior to the normal read command, thereby to execute a flush command, and to control the write command module, causing to execute a write flush process that includes the processing of a write command for the RMW operation after the read command for the RMW operation has been executed. | 06-07-2012 |
20120144095 | MEMORY SYSTEM PERFORMING INCREMENTAL MERGE OPERATION AND DATA WRITE METHOD - Disclosed is a method of executing a write operation in a nonvolatile memory system. The method includes receiving a write command indicating the write operation and write data associated with the write operation, and determining a selected merge size for use by a merge operation responsive to the write command by determining a number of free blocks and then determining a selected free block level (FBL) from among a plurality of FBLs in accordance with the number of free blocks. | 06-07-2012 |
20120144096 | MASS STORAGE SYSTEMS AND METHODS USING SOLID-STATE STORAGE MEDIA - A mass storage system comprising multiple memory cards, each with non-volatile memory components, a system bus interface for communicating with a system bus of a host system, and at least one ancillary interface. The ancillary interface is configured for direct communication of commands, addresses and data between the memory cards via a cross-link connector without accessing the system bus interface. | 06-07-2012 |
20120144097 | MEMORY SYSTEM AND DATA DELETING METHOD - According to one embodiment, a memory system includes: a memory area; a transfer processing unit that stores write data received from a host apparatus in the memory area; a delete notification buffer that accumulates a delete notification; and a delete notification processing unit. The delete notification processing unit collectively reads out a plurality of delete notifications from the delete notification buffer and classifies the read-out delete notifications for each unit area. The delete notification processing unit sequentially executes, for each unit area, processing for collectively invalidating write data related to one or more delete notifications classified in a same unit area and, in executing processing for one unit area in the processing sequentially executed for the each unit area, invalidates all write data stored in the one unit area after copying write data excluding write data to be invalidated stored in the one unit area to another unit area. | 06-07-2012 |
20120144098 | MULTIPLE LOCALITY-BASED CACHING IN A DATA STORAGE SYSTEM - A data storage caching architecture supports using native local memory such as host-based RAM, and if available, Solid State Disk (SSD) memory for storing pre-cache delta-compression based delta, reference, and independent data by exploiting content locality, temporal locality, and spatial locality of data accesses to primary (e.g. disk-based) storage. The architecture makes excellent use of the physical properties of the different types of memory available (fast r/w RAM, low cost fast read SSD, etc) by applying algorithms to determine what types of data to store in each type of memory. Algorithms include similarity detection, delta compression, least popularly used cache management, conservative insertion and promotion cache replacement, and the like. | 06-07-2012 |
20120144099 | DEVICE DRIVER DEPLOYMENT OF SIMILARITY-BASED DELTA COMPRESSION FOR USE IN A DATA STORAGE SYSTEM - A data storage caching architecture supports using native local memory such as host-based RAM, and if available, Solid State Disk (SSD) memory for storing pre-cache delta-compression based delta, reference, and independent data by exploiting content locality, temporal locality, and spatial locality of data accesses to primary (e.g. disk-based) storage. The architecture makes excellent use of the physical properties of the different types of memory available (fast r/w RAM, low cost fast read SSD, etc) by applying algorithms to determine what types of data to store in each type of memory. Algorithms include similarity detection, delta compression, least popularly used cache management, conservative insertion and promotion cache replacement, and the like. | 06-07-2012 |
20120144100 | MEMORY SYSTEM AND METHOD OF WRITING INTO NONVOLATILE SEMICONDUCTOR MEMORY - A memory system includes a nonvolatile semiconductor memory which includes a first original block composed of n (n being natural number) write unit areas and a first subblock composed of a plurality of write unit areas. A controller writes data having one of first to p-th (p being natural number smaller than n) addresses into the first original block. The controller writes data which has a first write address of one of the first to p-th addresses into the first subblock when the controller receives request to write data having the first write address and data having the first write address exists in the first original block. | 06-07-2012 |
20120144101 | PROGRAMMING MEMORY CELLS WITH ADDITIONAL DATA FOR INCREASED THRESHOLD VOLTAGE RESOLUTION - Methods for programming memory and memory devices are provided. According to at least one such method, additional data is appended to original data and the resulting data is programmed in a selected memory cell. The appended data increases the program threshold voltage margin of the original data. The appended data can be a duplicate of the original data or logical zeros. When the selected memory cell is read, the memory control circuitry can read just the original data in the MSB field or the memory control circuitry can read the entire programmed data and ignore the LSB field, for example. | 06-07-2012 |
20120144102 | FLASH MEMORY BASED STORAGE DEVICES UTILIZING MAGNETORESISTIVE RANDOM ACCESS MEMORY (MRAM) - A flash memory based storage device may utilize magnetoresistive random access memory (MRAM) as at least one of a device memory, a buffer, or high write volume storage. In some embodiments, a processor of the storage device may compare a logical block address of a data file to a plurality of logical block addresses stored in a write frequency file buffer table and causes the data file to be written to the high write volume MRAM when the logical block address of the data file matches at least one of the plurality of logical block addresses stored in the write frequency file buffer table. In other embodiments, upon cessation of power to the storage device, the MRAM buffer stores the data until power is restored, after which the processor causes the buffered data to be written to the flash memory under control of the flash memory controller. | 06-07-2012 |
20120151120 | SYSTEMS AND METHODS FOR HANDLING NON-VOLATILE MEMORY OPERATING AT A SUBSTANTIALLY FULL CAPACITY - This can relate to handling a non-volatile memory (“NVM”) operating at a substantially full memory. The non-volatile memory can report its physical capacity to an NVM driver. The NVM driver can scale-up the physical capacity a particular number of times to generate a “scaled physical capacity,” which is then reported to the file system. Because the scaled physical capacity is greater than the NVM's actual physical capacity, the file system allocates a logical space to the NVM that is substantially greater than the NVM's capacity. This can cause less crowding of the logical block addresses within the logical space, thus making it easier for the file system to operate and improving system performance. A commitment budget can also be reported to the file system that corresponds to the NVM's physical capacity, and which can define the amount of data the file system can commit for storage in the NVM. | 06-14-2012 |
20120151121 | Solid State Non-Volatile Storage Drives Having Self-Erase and Self-Destruct Functionality and Related Methods - Solid state storage drives for a host computer are provided that include a solid state memory cell array that includes a plurality of non-volatile memory cells, a first processor that is configured to control write and read operations to and from the solid state memory cell array, and to perform block erase operations on blocks of the solid state memory cell array, and a second processor that is configured to block erase all blocks of the solid state memory cell array in response to a user input self-erase command. These solid state storage drives may further include self-destruct functionality which can be used to render the drive unusable and to inhibit efforts to forensically recover data that was previously stored on the drive. | 06-14-2012 |
20120151122 | METHOD FOR OPERATING FLASH MEMORIES ON A BUS - Enable a read command of a first flash memory. After the read command of the first flash memory is enabled, a ready/busy signal of the first flash memory enters a busy waiting time, and a read command of a second flash memory starts to be enabled. Start to read data of the first flash memory when the busy waiting time is over. Enable the read command of the first flash memory again upon completion of reading the data of the first flash memory. Start to read data of the second flash memory after the read command of the first flash memory is enabled again. And enable the read command of the second flash memory again upon completion of reading the data of the second flash. | 06-14-2012 |
20120151123 | MEMORY SYSTEM AND MEMORY CONTROLLER - A memory system according to the embodiment comprises a memory device including plural memory cells capable of storing d bits of data and operative to read/write data at every page; and a memory controller operative to control the memory device. The memory controller includes a page buffer operative to hold page data to be read from/written in a page of the memory device and send/receive the page data to/from the memory device, a data processing unit operative to detect and correct an error in the page data by processing target data in a finite field Zp modulo p generated based on the page data (p is a prime that satisfies 2 | 06-14-2012 |
20120151124 | Non-Volatile Memory Device, Devices Having the Same, and Method of Operating the Same - A flash memory and a method of writing data to a flash memory during garbage collection of the flash memory is provided. First, a garbage collection process on a victim block of flash memory may be initiated. A garbage collection process may comprise a plurality of garbage collection operation. A program command and corresponding program data may be received. After a first garbage collection operation has finished and a portion of flash data from the victim block has been written to a free block, a portion of the program data may be written to that free block. If data remains in the victim block, a second garbage collection operation may be performed. | 06-14-2012 |
20120151125 | DATA PROCESSING METHOD FOR NONVOLATILE MEMORY SYSTEM - A data processing method for a nonvolatile memory system is described. In the method, a host CPU calls N data file segments, generates logical addresses, and then transfers the N data file segments and logical addresses to an ASIC. The ASIC then maps the logical addresses onto physical addresses of a nonvolatile memory, derives N payload data segments, and collectively generates corresponding metadata for all of the N payload data segments. Then, a single multi-segment transfer operation is performed to sequentially write the N payload data segments to a data block in the nonvolatile memory, and thereafter, write the corresponding metadata to a metadata block associated with the data block. | 06-14-2012 |
20120151126 | FLASH DRIVE WITH MULTIPLE CONNECTORS - A data storage stick is described that has a nonvolatile memory circuit disposed within a protective cover. Interface circuitry is coupled to the nonvolatile memory circuit and is configured to provide data access to the nonvolatile memory circuit. A first interface connector is coupled to the interface circuitry, penetrates the protective cover, and conforms to a first physical format. A second interface connector is coupled to the interface circuitry, penetrates the protective cover, and conforms to a second physical format. | 06-14-2012 |
20120151127 | METHOD OF STORING DATA IN A STORING DEVICE INCLUDING A VOLATILE MEMORY DEVICE - In a method of storing data in a storage device including a volatile memory device according to example embodiments, a swap address table containing address information about swap data are generated. The data are received from a host. Whether the received data are the swap data are determined based on the address information stored in the swap address table. The received data are selectively stored in the volatile memory device or in the nonvolatile memory device according to a result of the determination. | 06-14-2012 |
20120151128 | DATA SYSTEM WITH MEMORY LINK ARCHITECTURES AND METHOD WRITING DATA TO SAME - A system and method that transfers data from a ROM writer to memory socket assemblies (MSAs), each MSA capable of mechanically mounting and thereby electrically connecting a memory link architecture (MLA) and including a memory and a control device. Only after transferring the data from the ROM writer to at least one of the plurality of MSA but before mounting a corresponding MLA in each one of the plurality of MSAs, data is written from a memory in one MSA to a corresponding nonvolatile memory. | 06-14-2012 |
20120151129 | BOOT BLOCK FEATURES IN SYNCHRONOUS SERIAL INTERFACE NAND - Embodiments are provided for protecting boot block space in a NAND memory device connected to a host device via an SPI interface. One such method includes programming a boot block password into the NAND memory device such that the host device is required to provide the boot block password in order to access the boot block space. A counter may be provided to track the number of times the host device provides an incorrect password, permanently locking the boot block space if the counter reaches a predetermined value. A further method includes associating each of various areas of the boot block space with at least one write lock bit, setting the write lock bit to a lock enable or lock disable value, and locking or unlocking an area of the boot block space depending on the value of its associated write lock bit. | 06-14-2012 |
20120151130 | SYSTEMS AND METHODS FOR MEASURING THE USEFUL LIFE OF SOLID-STATE STORAGE DEVICES - A non-volatile solid-state storage subsystem, such as a non-volatile memory device, maintains usage statistics reflective of the wear state, and thus the remaining useful life, of the subsystem's memory array. A host system reads the usage statistics information, or data derived therefrom, from the subsystem to evaluate the subsystem's remaining life expectancy. The host system may use this information for various purposes, such as to (a) display or report information regarding the remaining life of the subsystem; (b) adjust the frequency with which data is written to the subsystem; and/or (c) select the type(s) of data written to the subsystem. | 06-14-2012 |
20120159040 | Auxiliary Interface for Non-Volatile Memory System - A non-volatile memory system is formed a plurality of memory banks and a controller, where the controller has an auxiliary memory interface for use with an additionally non-volatile memory bank, where the additional memory bank and interface are used for metadata, such as logical to physical translation data. The other banks are used for user data. In an exemplary embodiment, a non-volatile memory could include a controller and (N+1) NAND flash memories, where N of these memories would store user data, but the remaining memory with its own controller interface would be dedicated to the storage of metadata. This allows for the metadata to be kept in non-volatile memory, but still quite readily accessible relative to the typical paging/overlay arrangement for metadata that is typically used in many non-volatile memory system. | 06-21-2012 |
20120159041 | STORAGE DRIVE BASED ANTIMALWARE METHODS AND APPARATUSES - An anti-malware approach uses a storage drive with the capability to lock selected memory areas. Platform assets such as OS objects are stored in the locked areas and thus, unauthorized changes to them may not be made by an anti-malware entity. | 06-21-2012 |
20120159042 | DATA STORAGE DEVICE EXECUTING A UNITARY COMMAND COMPRISING TWO CIPHER KEYS TO ACCESS A SECTOR SPANNING TWO ENCRYPTION ZONES - A data storage device is disclosed comprising a non-volatile memory (NVM) including a plurality of sectors each having a sector size. An access command is received from a host, wherein the access command identifies a plurality of host blocks having a host block size less than the sector size. A plurality of the host blocks are mapped to a target sector. When the target sector spans an encryption zone boundary defined by the host blocks, a NVM command is generated identifying a first key corresponding to a first encryption zone and a second key corresponding to a second encryption zone. The NVM command is executed as a unitary operation to access a first part of the target sector using the first key and access a second part of the target sector using the second key. | 06-21-2012 |
20120159043 | DATA MANAGEMENT METHOD, MEMORY CONTROLLER AND MEMORY STORAGE APPARATUS - A data management method, a memory controller and a memory storage apparatus are provided. The method includes grouping a plurality of physical units of a rewritable non-volatile memory module into at least a data area and a free area. The method also includes configuring a plurality of logical units for mapping a part of the physical units. The method further includes receiving at least two pieces of update data, which are corresponding to different logical pages of the logical units. The method further includes getting a physical unit from the physical units. The method further includes writing the at least two pieces of update data into the same one physical page of the gotten physical unit. Accordingly, the use efficiency of the physical units could be improved. | 06-21-2012 |
20120159044 | NON-VOLATILE MEMORY SYSTEM WITH BLOCK PROTECTION FUNCTION AND BLOCK STATUS CONTROL METHOD - A non-volatile memory system with a block protection function includes a memory area including a first memory area including a plurality of blocks and a second memory area, and a controller configured to record data, which corresponds to status information on the plurality of blocks, in the second memory area, and read the data from the second memory area. | 06-21-2012 |
20120159045 | MEMORY BUS ARCHITECTURE FOR CONCURRENTLY SUPPORTING VOLATILE AND NON-VOLATILE MEMORY MODULES - A memory/storage module is provided that implements a solid state drive compatible with Serial Advanced Technology Attachment (SATA) or Serial Attached SCSI (SAS) signaling on a double-data-rate compatible socket. A detachable daughter card may be coupled to the memory module for converting a memory bus voltage to a second voltage for memory devices on the memory module. Additionally, a hybrid memory bus on a host system is provided that supports either DDR-compatible memory modules and/or SATA/SAS-compatible memory modules. In one example, the memory/storage module couples to a first bus (DDR3 compatible socket) to obtain voltage and/or other signals, but uses a second bus for data transfers. In another example, the memory module may repurpose/reuse electrical paths that typically carry non-data signals for data traffic to/from the memory/storage module. Such data traffic for the memory/storage module permits concurrent data traffic for other memory modules on the same memory bus. | 06-21-2012 |
20120159046 | MEMORY SYSTEM - According to one embodiment, a memory system includes a controller for controlling a data transfer between a nonvolatile memory and a host device. The controller writes, to the nonvolatile memory, management information to be used in the data transfer, a multiplexed pointer indicating a storage position, and a log indicating whether the writing of the pointer is successful, determines whether the multiplexing the pointer by the predetermined number is maintained according to at least one of the pointer and the log, and rewrites the multiplexed pointers to the nonvolatile memory when determining that the multiplexing the pointer by the predetermined number is not maintained. | 06-21-2012 |
20120159047 | COMPUTING DEVICE AND METHOD FOR MERGING STORAGE SPACE OF USB FLASH DRIVES - A method for merging storage space of multiple universal serial bus (USB) flash drives is applied in a computing device. The method detects USB flash drives plugged into USB ports of the computing device and checks respective storage capacities, stored files, and available storage space of the USB flash drives. A virtual USB flash drive including all the stored files of the USB flash drives is created. Files of the virtual USB flash drive are related to the USB flash drives. A file may be copied from a data processing device connected to the computing device to the virtual USB flash drive and split for storage between more than one USB flash drive, or a second file may be copied from one or more USB flash drives to the data processing device through the virtual USB flash drive. | 06-21-2012 |
20120159048 | NON-VOLATILE MEMORY DEVICE - A non-volatile memory device includes a first bank including a plurality of first page buffers, a second bank including a plurality of second page buffers, and an address counter configured to count a first address and a second address in response to a clock before a first time in a period for performing a read operation and count the first address and the second address in response to a bank address after the first time, wherein data of the first page buffers are sequentially outputted in response to the first address, and data of the second page buffers are sequentially outputted in response to the second address. | 06-21-2012 |
20120159049 | METHOD AND DEVICE OF CONTROLLING MEMORY AREA OF MULTI-PORT MEMORY DEVICE IN MEMORY LINK ARCHITECTURE - A memory area managing method of a multi-port memory device in a memory link architecture which includes a multi-port memory device, a memory controller, and a flash memory, the method including performing a data processing step in which data stored in a host CPU area of the multi-port memory device is processed by a host CPU connected with the multi-port memory device, the processed data being stored in a shared area; performing a file data generating step in which file data on the processed data stored in the shared area is generated according to a write command of the host CPU, the file data being stored in a memory controller area of the multi-port memory device; and performing a file data storing step in which the file data is read out from the memory controller area and the read file data is sent to the flash memory. | 06-21-2012 |
20120159050 | MEMORY SYSTEM AND DATA TRANSFER METHOD - According to one embodiment, a memory system comprises a nonvolatile memory including a memory cell array and a read buffer and a controller configured to receive a read request and to issue a first read command and a second read command to the memory. When issuing the first read command, the memory transfers data of the first size from the memory cell array to the read buffer and outputs the data from the read buffer to the controller. When issuing the second read command, the memory transfers first data of the first size from the memory cell array to the read buffer, outputs the first data from the read buffer to the controller, and transfers second data of the first size from the memory cell array to the read buffer. The controller selects one command from the two commands according to the read request. | 06-21-2012 |
20120159051 | MEMORY SYSTEM - According to one embodiment, a memory system includes a non-volatile memory, a resource managing unit that reclaims resources associated with the non-volatile memory and increases the resources, when the usage of the resources associated with the non-volatile memory reaches the predetermined amount, a transmission rate setting unit that calculates a setting value of the transmission rate to receive the write data from a host device, and a transmission control unit that receives the write data from the host device and transmits the received write data to the non-volatile memory. The transmission rate setting unit calculates a small setting value when the usage of the resources associated with the non-volatile memory increases. The transmission control unit executes the reception of the write data from the host device at the transmission rate of the setting value, while the resource managing unit reclaims the resources. | 06-21-2012 |
20120159052 | Descriptor Scheduler - Methods, systems and computer program products for providing a sequencer that schedules job descriptors are described. The sequencer can manage the scheduling of the job descriptors for execution based on the availability of their respective segments and channels. For example, the sequencer can check the status of the segments, and identify one or more segments that are in busy or full state, or one or more segments that are in non-busy or empty state. Based on the status check, the sequencer can execute job descriptors out of order, and in particular, give priorities to job descriptors whose associated segments are available over job descriptors whose associated segments are in busy or full state. In doing so, pending job descriptors can be processed quicker and unnecessary latency can be avoided. | 06-21-2012 |
20120159053 | STORAGE APPARATUS, MEMORY AREA MANAGING METHOD THEREOF, AND FLASH MEMORY PACKAGE - A storage apparatus for storing data transmitted from one or more host computers, including: one or more flash memory packages having a plurality of flash memory chips, a storage area provided by the one or more flash memory packages including a first area that is an area for storing actual data formed by one or more logical devices and a second area that is an area for storing a write log data based on a write instruction, the first and second areas being provided in each of the one or more flash memory packages; a monitoring section monitoring write performance of the write instruction from the host computer; and a changing section for changing the size of the second area according to the write performance. | 06-21-2012 |
20120159054 | FLASH MEMORY DEVICE WITH MULTI-LEVEL CELLS AND METHOD OF WRITING DATA THEREIN - In one aspect, a method of writing data in a flash memory system is provided. The flash memory system forms an address mapping pattern according to a log block mapping scheme. The method includes determining a writing pattern of data to be written in a log block, and allocating one of SLC and MLC blocks to the log block in accordance with the writing pattern of the data. | 06-21-2012 |
20120159055 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE WITH POWER SAVING FEATURE - A non-volatile semiconductor memory device, which comprises (i) an interface having an input for receiving an input clock and a set of data lines for receiving commands issued by a controller including an erase command; (ii) a module having circuit components in a feedback loop configuration and being driven by a reference clock; (iii) a clock control circuit capable of controllably switching between a first state in which the reference clock tracks the input clock and a second state in which the reference clock is decoupled from the input clock; and (iv) a command processing unit configured to recognize the commands and to cause the clock control circuit to switch from the first state to the second state in response to recognizing the erase command. The module consumes less power when the reference clock is decoupled from the input clock than when the reference clock tracks the input clock. | 06-21-2012 |
20120166707 | Data management in flash memory using probability of charge disturbances - A Flash memory system and a method for data management using the system's sensitivity to charge-disturbing operations and the history of charge-disturbing operations executed by the system are described. In an embodiment of the invention, the sensitivity to charge-disturbing operations is embodied in a disturb-strength matrix in which selected operations have an associated numerical value that is an estimate of the relative strength of that operation to cause disturbances in charge that result in data errors. The disturb-strength matrix should also include the direction of the error which indicates either a gain or loss of charge. The disturb-strength matrix can be determined by the device conducting a self-test in which changes in the measured dispersion value are provoked by executing a selected operation until a detectable change occurs. In alternative embodiments the disturb-strength matrix is determined by testing selected units from a homogeneous population. | 06-28-2012 |
20120166708 | FLASH MEMORY DEVICES, DATA RANDOMIZING METHODS OF THE SAME, MEMORY SYSTEMS INCLUDING THE SAME - Disclosed is a flash memory device which includes a memory cell array configured to store data, a randomizer configured to generate a random sequence, to interleave the random sequence using at least one of memory parameters associated with data to be programmed in the memory cell array, and a control logic circuit configured to provide the memory parameters to the randomizer and to control the randomizer. | 06-28-2012 |
20120166709 | FILE SYSTEM OF FLASH MEMORY - A file system of a flash memory includes: a file system layer; a physical erase block (PEB) layer configured to recognize a PEB of the flash memory by the unit of PEB address; and a logical erase block (LEB) layer positioned under the file system layer and over the PEB layer and configured to provide an LEB address mapped to the PEB to the file system layer. | 06-28-2012 |
20120166710 | Flash Memory Device and Data Access Method Thereof - In one embodiment, the flash memory device is coupled to a host, and comprises a flash memory and a controller. The flash memory is used for data storage. The controller receives write data and a write logical address from the host, calculates a running sum value according to the write data, determines whether target data with a running sum equal to the running sum value is stored in the flash memory, reads the target data from the flash memory when the target data is stored in the flash memory, determines whether the target data is identical to the write data, and records a mapping relationship between an original logical address of the target data and a write logical address of the write data in a remapping table without writing the write data to the flash memory when the target data is identical to the write data. | 06-28-2012 |
20120166711 | DATA STORAGE APPARATUS AND APPARATUS AND METHOD FOR CONTROLLING NONVOLATILE MEMORIES - According to one embodiment, a data storage apparatus comprises a channel controller, an encoding module, and a data controller. The channel controller is configured to control data input to, and output from, nonvolatile memories for channels. The encoding module is configured to generate encoded data for which an inter-channel error correction process, using data stored in each of the nonvolatile memories. The data controller is configured to manage the encoded data in units of logic blocks when the channel controller writes the encoded data in parallel to the channels, and to allocate parity data contained in the encoded data to one plane in each logic block. | 06-28-2012 |
20120166712 | HOT SHEET UPGRADE FACILITY - Method and apparatus for managing data in a multi-device data storage array. In accordance with various embodiments, a storage array of independent data storage devices are arranged to form a fast pool and a slow pool of said devices. A controller is adapted to migrate a distributed data set stored across a first plurality of said devices in the slow pool to a second plurality of said devices in the fast pool. The migration is carried out responsive to a return on investment (ROI) determination by the controller that an estimated cost of said migration will be outweighed by an overall improved data transfer capacity of the storage array over a predetermined minimum payback period of time. In some embodiments, the fast pool is formed from a plurality of solid-state drives (SSDs) and the slow pool is formed from a plurality of hard disc drives (HDD). | 06-28-2012 |
20120166713 | ADMINISTRATION DEVICE, ADMINISTRATION METHOD, AND PROGRAM - An administration device includes an administration section. The administration section administers writing, reading, and erasing of data in a nonvolatile memory, in which the data can be electrically written, read, and erased and the writing and the reading are performed on a page-by-page basis and the erasing is performed on a block-by-block basis, by translating a logical address into a physical address on a per translation unit basis; and performs fold processing of increasing unwritten physical translation units by the number of written invalid physical translation units, which are contained in a block of a copy source, by copying data of written valid physical translation units among the contents of the block into a block, in which the unwritten physical translation units reside, and by erasing the block of the copy source. | 06-28-2012 |
20120166714 | FLASH MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME - A method of controlling a memory, determining whether data access is random; generating a first random sequence (RS) data based on a first seed if data access is not random (column offset=0); mixing the first RS data with data read from the memory or data to be written to the memory; generating a second seed from a first seed if data access is random (column offset not=0); generating a second RS data based on the second seed; and mixing the second RS data with data read from the memory or data to be written to the memory. | 06-28-2012 |
20120166715 | Secure Flash-based Memory System with Fast Wipe Feature - A Flash-based storage system, card, and/or module comprises a Flash controller configured to encrypt the data pages of a page stripe by shuffling the data pages, including loading each data page into a data shuffling buffer in a sequential order relative to other data pages in the page stripe, and thereafter unloading each data page in a non-sequential order relative to other data pages in the page stripe. The Flash controller is also configured to scramble the data pages of the page stripe by performing a bitwise logical operation on the data pages that are unloaded from the data shuffling buffer. A user key and one or more system keys are used to perform the shuffling and scrambling. The Flash controller is further configured to flush the user key by bypassing the system's backup power supply and performing an emergency system shutdown without backing up system data. | 06-28-2012 |
20120166716 | METHODS, STORAGE DEVICES, AND SYSTEMS FOR PROMOTING THE ENDURANCE OF NON-VOLATILE SOLID-STATE MEMORY COMPONENTS - Solid-state mass storage devices, host computer systems, and methods of increasing the endurance of non-volatile solid-state memory components used therein. The memory components comprise memory cells organized in functional units that are adapted to receive units of data transferred from the host computer system and correspond to the functional units of the memory component. The level of programming for each cell is reduced by performing an analysis of the bit values of the units of data to be written to at least a first of the functional units of the memory component. Depending on the analysis of “0” and “1” bit values of the units of data to be written, the bit values are inverted before writing the units of data to the first memory component. | 06-28-2012 |
20120166717 | Data Storage Device and Operation Method Thereof - In one embodiment, a data storage device comprises a first flash memory, a second flash memory, and a controller. The first flash memory stores a first data shaping driver, wherein the first data shaping driver performs a data shaping function. The second flash memory stores user data. The controller enables the first flash memory and disables the second flash memory after the data storage device is turned on, detects whether a second data shaping driver has been installed on a host when the host is connected to the data storage device, installs the first data shaping driver to the host as the second data shaping driver if the second data shaping driver has not been installed on the host, and disables the first flash memory and enables the second flash memory after the first data shaping driver has been installed to the host. | 06-28-2012 |
20120166718 | Flash Storage Device and Data Writing Method Thereof - A flash storage device comprises a flash memory and a controller. The flash memory comprises a plurality of blocks comprising a plurality of ordinary pages and a plurality of reserved pages. The controller receives a current write command and write data from a host, determines a mother block and an FAT block corresponding to the write command, divides data of the mother block and data of the FAT block into a plurality of original data segments and a plurality of updating data segments, integrates the original data segments with the updating data segments to obtain integrated data segments, writes the integrated data segments to an integrated block respectively in a plurality of processing periods of a plurality of subsequent write commands, and writes the subsequent write data to the reserved pages of a plurality of subsequent blocks. | 06-28-2012 |
20120166719 | DATA COPY MANAGEMENT FOR FASTER READS - Multiple copy sets of data are maintained on one or more storage devices. Each copy set includes at least some of the same data units as other sets. Different sets optionally have data units stored in different orders on the storage device(s). A particular one of the sets of data is selected as the set to be accessed in response to detecting a particular scenario. | 06-28-2012 |
20120166720 | PROCESSORS FOR PROGRAMMING MULTILEVEL-CELL NAND MEMORY DEVICES - In an embodiment, a processor includes a storage device. The processor is configured to request first data from a first location of a memory device. The storage device is configured to receive and to store the first data from the memory device. The processor is configured to attempt to write second data to the first location of the memory device. The processor is configured to write the first data stored in the storage device and the second data to one or more other locations of the memory device if the attempt to write second data to the first location of the memory device fails. | 06-28-2012 |
20120173789 | ALBUM USB - The Daleth Album USB (Daleth) is an album applied to a USB used for the purpose of listening, storing and distributing music. The functionality is that the Daleth Album USB is to act as an audio record or compact disc (CD) for the music, and the outside is to act as an audio record cover or CD case in which it has the artist(s) image or the image to represent the album along with album title. The Daleth Album USB can be used in computers, exercise machines, vehicles with USB ports, radios with USB ports, and other devices with USB compatibility. | 07-05-2012 |
20120173790 | STORAGE SYSTEM CACHE WITH FLASH MEMORY IN A RAID CONFIGURATION - Embodiments of the invention relate to a storage system cache with flash memory units organized in a RAID configuration. An aspect of the invention includes a storage system comprising a storage system cache with flash memory in a RAID configuration. The storage cache comprises flash memory units organized in an array configuration. Each of the flash memory units comprises flash memory devices and a flash unit controller. Each flash unit controller manages data access and data operations for its corresponding flash memory devices. The storage system further includes an array controller, coupled to the flash memory units, and that manages data access and data operations for the flash memory units and organizes data as full array stripes. The storage system further includes a primary storage device, which is coupled to the array controller, and stores data for the storage system. The storage system further includes a storage cache controller, coupled to the array controller, and comprises a block line manager that buffers write data to be cached for a write operation until the storage cache controller has accumulated an array band, and commits write data to the array controller as full array stripes. The storage cache controller receives storage commands from at least one host system. The storage cache controller determines for a write data storage command, whether to store write data in the storage cache and/or in the primary storage device; and for a read data storage command, whether to access read data from the storage cache or from the primary storage device. | 07-05-2012 |
20120173791 | CONTROL METHOD AND ALLOCATION STRUCTURE FOR FLASH MEMORY DEVICE - A control method and an allocation structure for a flash memory device are provided herein. The flash memory device has a first memory module and a second memory module. Physical blocks of the first memory module and physical blocks of the second memory module are respectively divided into a plurality of groups, each of which has a plurality of the physical blocks. A first subunit and a second subunit of a first allocation unit are interleavingly written into a first group of the groups of the first memory module and a second group of the groups of the second memory chip respectively. Additionally, a first subunit and a second subunit of a second allocation unit are interleavingly written into a third group of the groups of the first memory module and the second group, respectively. | 07-05-2012 |
20120173792 | Controller and Method for Performing Background Operations - The embodiments described herein provide a controller and method for performing a background commands or operations. In one embodiment, a controller is provided with interfaces through which to communicate with a host and a plurality of flash memory devices. The controller contains a processor operative to perform a foreground command received from the host, wherein the processor performs the foreground command to completion without interruption. The processor is also operative to perform a background commands or operations stored in the controller's memory, wherein the processor performs the background command until completed or preempted by a foreground command. If the background command is preempted, the processor can resume performing the background command at a later time until completed. | 07-05-2012 |
20120173793 | MEMORY DEVICE USING EXTENDED INTERFACE COMMANDS - A memory device includes a serial interface buffer that receives a hardware-decodable command and an extended interface command. The memory device also includes a logic module that directs the hardware-decodable command to a register for execution by a microcontroller. The logic module additionally loads a command received following the extended interface command into a sub-op-code register, wherein the logic module remains passive after loading the command received following the extended interface command into the sub-op-code register. Also included is a microcontroller that interprets the command in the sub-op-code register. | 07-05-2012 |
20120173794 | DRIVE ASSISTED SYSTEM CHECKPOINTING - Systems and methods of managing computing system restore points may include an apparatus having logic to receive a command to start a restore point for a solid state drive (SSD). The logic may also conduct a context drop of an indirection table from a volatile memory of the SSD to a non-volatile memory of the SSD in response to the command to start the restore point. | 07-05-2012 |
20120173795 | SOLID STATE DRIVE WITH LOW WRITE AMPLIFICATION - A solid state drive having a non-volatile memory device and methods of operating the solid state drive to compare existing data stored on the memory device to subsequent data in an incoming data stream received by the solid state drive from a host system. If matching data are found, the solid state drive uses the existing data instead of writing the subsequent data to the memory device. Common data patterns can be shared among different files stored on the memory device. | 07-05-2012 |
20120173796 | METHOD FOR PERFORMING BLOCK MANAGEMENT, AND ASSOCIATED MEMORY DEVICE AND CONTROLLER THEREOF - A method for performing block management is provided, where the method is applied to a controller of a Flash memory that includes a plurality of blocks. The method includes: selecting a target block having a least erase count from at least one portion of blocks in a data region of the Flash memory, and utilizing the target block as a block to be erased, wherein serial numbers of the at least one portion of blocks correspond to order of last update of the at least one portion of blocks, respectively; and determining whether to move/copy valid data of the target block into a heavily worn block or a lightly worn block according to a serial number of the target block, where the degree of wear of the heavily worn block is higher than that of the lightly worn block. An associated memory device and a controller thereof are also provided. | 07-05-2012 |
20120173797 | METHOD FOR PERFORMING BLOCK MANAGEMENT/FLASH MEMORY MANAGEMENT, AND ASSOCIATED MEMORY DEVICE AND CONTROLLER THEREOF - A method for performing block management is provided. The method is applied to a controller of a Flash memory having multiple channels. The Flash memory includes a plurality of blocks respectively corresponding to the channels. The method includes: selecting at least one meta block having at least one valid page as at least one candidate meta block for being cleaned, and accumulating respective valid page counts of blocks respectively corresponding to the channels within the at least one candidate meta block, in order to generate a plurality of accumulated values respectively corresponding to the channels; and when it is detected that all of the accumulated values reach a threshold value, triggering a cleaning operation with regard to all candidate meta blocks, in order to simultaneously move/copy valid data respectively corresponding to the channels during the cleaning operation. An associated memory device and a controller thereof are also provided. | 07-05-2012 |
20120173798 | MEMORY CONTROLLER, MEMORY DEVICE AND METHOD FOR DETERMINING TYPE OF MEMORY DEVICE - A memory controller includes a clock detector and a microprocessor. The clock detector is utilized for detecting if a specific pin of the memory controller has a clock signal thereon to generate a detecting result. The microprocessor is coupled to the clock generator, and is utilized for determining which type of memory devices that the memory controller is applied to according to the detecting result. | 07-05-2012 |
20120173799 | DATA STORAGE APPARATUS, INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, AND PROGRAM - An information storage apparatus that includes a memory unit, a first controller that reads data from the memory unit, and a second controller included in the memory unit that reads a first identification and outputs the first identification in response to an external instruction, wherein the first identification may only be read by the second controller. | 07-05-2012 |
20120173800 | SYSTEM INCLUDING DATA STORAGE DEVICE, AND DATA STORAGE DEVICE INCLUDING FIRST AND SECOND MEMORY REGIONS - A data storage device includes a non-volatile memory device including a memory cell array, where the memory cell array includes a first region and a second region, and a memory controller configured to judge whether a size of data externally provided according to a write request exceeds a reference size, and to control the non-volatile memory device according to a judgment result. When the externally provided data exceeds the reference size, the memory controller controls the non-volatile memory device such that a portion of the externally provided data is stored in the second region via a main program operation and such that a remainder of the externally provided data is stored in the first region via a buffer program operation. | 07-05-2012 |
20120173801 | DATA PROCESSING DEVICE, DATA RECORDING METHOD AND DATA RECORDING PROGRAM - A data processing device has plural kinds of recording media and a data block management device. The data block management device classifies data blocks into plural groups and records each group on an appropriate recording medium. The data block management device has a memory unit, a group reconfiguration unit and a medium selection unit. Access trend information representing a trend of combinations of former groups and latter groups is stored in the memory unit. The group reconfiguration unit performs group reconfiguration processing by reference to the access trend information. Specifically, if a sequential access trend between two different groups is increased, they are integrated to generate a new group. If a sequential access trend within a certain group is decreased, the certain group is divided to generate a new group. The medium selection unit records the new group obtained as a result of the group reconfiguration on a corresponding recording medium. | 07-05-2012 |
20120173802 | FLASH MEMORY STORAGE SYSTEM - A flash memory storage system has a plurality of flash memory devices comprising a plurality of flash memories, and a controller having an I/O processing control unit for accessing a flash memory device specified by a designated access destination in an I/O request received from an external device from among the plurality of flash memory devices. A parity group can be configured of flash memory devices having identical internal configuration. | 07-05-2012 |
20120173803 | METHODS AND APPARATUS TO SHARE A THREAD TO RECLAIM MEMORY SPACE IN A NON-VOLATILE MEMORY FILE SYSTEM - A disclosed example method involves associating a shared reclaim thread with an on-board flash memory device to reclaim first memory space in the on-board flash memory device. The shared reclaim thread is associated with a removable flash memory device to reclaim second memory space in the removable flash memory device while the shared reclaim thread is also in association with the on-board flash memory device. Different priorities are assigned to the on-board flash memory device and the removable flash memory device to selectively reclaim the first and second memory spaces based on the different priorities. | 07-05-2012 |
20120173804 | METHODS OF OPERATING A MEMORY SYSTEM - Methods of operating a memory system are useful in facilitating access to data. Where repetitive data patterns are detected among portions of received data, and an indication is provided, a portion of the data may be stored and/or subsequently retrieved without having to store and/or retrieve, respectively, all portions of the data. | 07-05-2012 |
20120173805 | DATA ACCESSING METHOD FOR FLASH MEMORY STORAGE DEVICE HAVING DATA PERTURBATION MODULE, AND STORAGE SYSTEM AND CONTROLLER USING THE SAME - A data accessing method, and a storage system and a controller using the same are provided. The data accessing method is suitable for a flash memory storage system having a data perturbation module. The data accessing method includes receiving a read command from a host and obtaining a logical block to be read and a page to be read from the read command. The data accessing method also includes determining whether a physical block in a data area corresponding to the logical block to be read is a new block and transmitting a predetermined data to the host when the physical block corresponding to the logical block to be read is a new block. Thereby, the host is prevented from reading garbled code from the flash memory storage system having the data perturbation module. | 07-05-2012 |
20120173806 | SOLID STATE DISK CONTROLLER APPARATUS - A solid state disk controller apparatus comprises a first port; a second port having a plurality of channels; a central processing unit connected to a CPU bus; a buffer memory configured to store data to be transferred from the second port to the first port and from the first port to the second port; a buffer controller/arbiter block connected to the CPU bus and configured to control read and write operations of the buffer memory based on a control of the central processing unit; a first data transfer block connected between the first port and the buffer controller/arbiter block and configured to transfer data to be stored/read in/from the buffer memory bypassing the CPU bus; and a second data transfer block connected between the second port and the buffer controller/arbiter block and configured to transfer data to be stored/read in/from the buffer memory bypassing the CPU bus. | 07-05-2012 |
20120173807 | Cache Control in a Non-Volatile Memory Device - A flash memory device includes a storage area having a main memory portion and a cache memory portion storing at least one bit per cell less than the main memory portion; and a controller that manages data transfer between the cache memory portion and the main memory portion according to at least one caching command received from a host. The management of data transfer, by the controller, includes transferring new data from the host to the cache memory portion, copying the data from the cache memory portion to the main memory portion and controlling (enabling/disabling) the scheduling of cache cleaning operations. | 07-05-2012 |
20120173808 | MEMORY, COMPUTING SYSTEM AND METHOD FOR CHECKPOINTING - Embodiments of the present invention provide local checkpoint memories that are closely coupled to the processor of a computing system used during normal operation. The checkpoint memory may be coupled to the processor through a peripheral bus or a memory bus. The checkpoint memory may be located on a same semiconductor substrate or circuit board as the processor. The checkpoint memory may be located on a same semiconductor substrate as a main memory used by the processor during normal operation. The checkpoint memory may be included in a memory hub configuration, with a checkpoint memory hub provided for access to the checkpoint memory. | 07-05-2012 |
20120179856 | E-medstick, e-medstick, e-medstick EMR - A device stores a patient's medical records to solve the problems of incompatibility of electronic medical record systems, no patient information available at emergencies, lack of information sharing among physicians, and health care fraud. The device includes a flash drive configured to connect to a USB port and be read by a computer, a record of emergency patient data photo stored on the flash drive and displayed immediately by the computer when the flash drive is inserted into the USB port, and a record of detailed data stored on the flash drive and displayed upon entry of a correct password and identification. | 07-12-2012 |
20120179857 | TECHNIQUES TO TRUNCATE DATA FILES IN NONVOLATILE MEMORY - Various embodiments for performing truncate operations in nonvolatile memory are described. In one embodiment, an apparatus may include a nonvolatile memory to perform one or more truncate operations on a data file written to the nonvolatile memory and a volatile memory to track a truncate operation performed in the nonvolatile memory. Other embodiments are described and claimed. | 07-12-2012 |
20120179858 | MEMORY DEVICE - A memory card of the present embodiment includes a memory section configured to have a non-volatile semiconductor memory cell, an erasure setting section whose physical state changes irreversibly and a memory controller configured to perform total erasure processing of erasing all data stored in the memory section according to the physical state of the erasure setting section. | 07-12-2012 |
20120179859 | NONVOLATILE MEMORY APPARATUS PERFORMING FTL FUNCTION AND METHOD FOR CONTROLLING THE SAME - A nonvolatile memory apparatus includes: a memory controller coupled; and a memory area comprising a plurality of memory blocks controlled by the memory controller. The memory controller sets a plurality of physical blocks corresponding to the plurality of memory blocks, and sets a plurality of logical blocks which are mapping targets of the physical blocks such that a size of the logical blocks and a size of the physical blocks are asymmetrical. | 07-12-2012 |
20120179860 | SUSPENSION OF MEMORY OPERATIONS FOR REDUCED READ LATENCY IN MEMORY ARRAYS - Read latencies in a memory array can be reduced by suspending write operations. In one example, a process includes, writing a first data set into a memory, interrupting a second memory write operation, and reading the first data set from the memory after interrupting the second memory write operation. | 07-12-2012 |
20120179861 | SEMICONDUCTOR MEMORY SYSTEM HAVING A SNAPSHOT FUNCTION - In a semiconductor memory computer equipped with a flash memory, use of backed-up data is enabled. The semiconductor memory computer includes an address conversion table for detecting physical addresses of at least two pages storing data by designating a logical address from one of logical addresses to be designated by a reading request. The semiconductor memory computer includes a page status register for detecting one page status allocated to each page, and page statuses to be detected include the at least following four statuses: (1) a latest data storage status, (2) a not latest data storage status, (3) an invalid data storage status, and (4) an unwritten status. By using the address conversion table and the page status register, at least two data (latest data and past data) can be read for one designated logical address from a host computer. | 07-12-2012 |
20120179862 | System For Accessing Non-Volatile Memory - Accessing a non-volatile memory array is described, including receiving a first data and a memory address associated with the first data, writing the first data to the non-volatile memory array at the memory address of the first data without erasing a second data stored in the non-volatile memory array at the memory address of the first data before writing the first data. | 07-12-2012 |
20120179863 | MEMORY SYSTEM - A memory system includes a plurality of storage groups, each of which includes a nonvolatile first storing unit and a second storing unit as a buffer memory of the first storing unit and is capable of performing data transfer between the first storing unit and the second storing unit, and a plurality of MPUs. A first control for data transfer between the host device and the first storing unit via the second storing unit for one of the storage groups and a second control including a control for maintenance of the first storing unit for other storage groups are allocated to the MPUs to be performed independently by the MPUs. | 07-12-2012 |
20120179864 | METRICS AND MANAGEMENT FOR FLASH MEMORY STORAGE LIFE - According to one aspect of the invention, a method of evaluating reliability of flash memory media comprises managing a flash memory remaining life for each disk of a plurality of flash memory media disks provided in one or more flash memory media groups each of which has a configuration and a relationship between said each flash memory media group and the flash memory media disks in said each flash memory media group, wherein each flash memory media group is one of a RAID group or a thin provisioning pool; and calculating to obtain information of each flash memory media group based on the measured flash memory remaining life for each disk in said each flash memory media group, the configuration of said each flash memory media group, and the relationship between said each flash memory media group and the flash memory media disks in said each flash memory media group. | 07-12-2012 |
20120179865 | NONVOLATILE MEMORY SYSTEM, AND DATA READ/WRITE METHOD FOR NONVOLATILE MEMORY SYSTEM - A nonvolatile memory system comprises a nonvolatile memory having a plurality of data areas; and a memory controller operative to control read and write operations to the nonvolatile memory. The memory controller successively executes read/write operations to plural sectors within a selected data area in the nonvolatile memory in accordance with a command and a sector count and sector address fed from a host device. | 07-12-2012 |
20120185637 | RECOVERING FAILED WRITES TO VITAL PRODUCT DATA DEVICES - A method for maintaining vital product data (VPD) contained in an EEPROM (Electrically Erasable Programmable Read-Only Memory) on a field replaceable unit (FRU) of a computer system that has a cache. The method includes maintaining a copy of the VPD in the cache, retrieving the copy of the VPD from the cache upon receiving a read request of the VPD, and, upon receiving a write request to write data to the VPD, writing the data to the copy of the VPD, determining whether the VPD in the EEPROM is in synchronization with the copy of the VPD in the cache, and, if the VPD and the copy of the VPD are in synchronization, writing the data to the EEPROM. | 07-19-2012 |
20120185638 | METHOD AND SYSTEM FOR CACHE ENDURANCE MANAGEMENT - A system and method for cache endurance management is disclosed. The method may include the steps of querying a storage device with a host to acquire information relevant to a predicted remaining lifetime of the storage device, determining a download policy modification for the host in view of the predicted remaining lifetime of the storage device and updating the download policy database of a download manager in accordance with the determined download policy modification. | 07-19-2012 |
20120185639 | ELECTRONIC DEVICE, MEMORY CONTROLLING METHOD THEREOF AND ASSOCIATED COMPUTER-READABLE STORAGE MEDIUM - An electronic device including a NAND flash memory, an auxiliary memory, and a controller is provided. A code for detecting a read command sequence of the NAND flash memory is stored in the auxiliary memory. During a boot procedure of the electronic device, the controller reads the code from the auxiliary memory and executes the code to obtain the read command sequence of the NAND flash memory, so as to access content stored in the NAND flash memory according to the read command sequence. | 07-19-2012 |
20120185640 | CONTROLLER AND METHOD FOR CONTROLLING MEMORY AND MEMORY SYSTEM - A memory controller for multiple addressing modes is provided. The memory controller includes a transmitting unit and a control unit. The transmitting unit transmits an identification message to a non-volatile memory. According to whether the non-volatile memory feeds back an acknowledgement message in response to the identification message, the control unit determines an addressing mode to be used for communicating with the non-volatile memory. | 07-19-2012 |
20120185641 | Distributed Storage Service Systems and Architecture - Various methods, devices and systems are described for providing distributed storage services. A data storage device is capable of initiating a communication session with an external entity such as a local host computer (and vice versa) coupled directly to the data storage device, a remote server computer, or directly with remote data storage devices with or without intervention by a local host computer. | 07-19-2012 |
20120191897 | NON-VOLATILE MEMORY SYSTEM AND MANAGEMENT METHOD THEREOF - A non-volatile memory system includes a memory area including a plurality of non-volatile memory blocks, and a micro control unit configured to manage the memory blocks as a data block and a buffer block. As a write command is input, if no buffer block assigned to the data block exists and a free page exists in the data block, the micro control unit converts the data block to a self-buffer block. | 07-26-2012 |
20120191898 | DDR FLASH IMPLEMENTATION WITH DIRECT REGISTER ACCESS TO LEGACY FLASH FUNCTIONS - A Double Data Rate (DDR) nonvolatile memory for use with a wireless device. A host processor transfers commands and data through a DDR interface of the nonvolatile memory. The DDR nonvolatile memory implements legacy flash functions while maintaining DDR behavior. | 07-26-2012 |
20120191899 | Flexible Memory Protection and Translation Unit - A memory management and protection system that manages memory access requests from a number of requestors. Memory accesses are allowed or disallowed based on the privilege level of the requestor, based on a Privilege Identifier that accompanies each memory access request. An extended memory controller selects the appropriate set of segment registers based on the Privilege Identifier to insure that the request is compared to and translated by the segment register associated with the requestor originating the request. A set of mapping registers allow flexible mapping of each Privilege Identifier to the appropriate access permission. The segment registers translate the logical address from the requestor to a physical address within a larger address space. | 07-26-2012 |
20120191900 | MEMORY MANAGEMENT DEVICE - A memory management device of an example of the invention controls writing into and reading from a main memory including a nonvolatile semiconductor memory and a volatile semiconductor memory in response to a writing request and a reading request from a processor. The memory management device includes a coloring information storage unit that stores coloring information generated based on a data characteristic of write target data to be written into at least one of the nonvolatile semiconductor memory and the volatile semiconductor memory, and a writing management unit that references the coloring information to determines a region into which the write target data is written from the nonvolatile semiconductor memory and the volatile semiconductor memory. | 07-26-2012 |
20120191901 | METHOD AND APPARATUS FOR MEMORY MANAGEMENT - One or more circuits of a device may comprise a memory. A first portion of a first block of the memory may store program code and/or program data, a second portion of the first block may store an index associated with a second block of the memory, and a third portion of the first block may store an indication of a write status of the first portion. Each bit of the third portion of the first block may indicate whether an attempt to write data to a corresponding one or more words of the first portion of the first block has failed since the last erase of the corresponding one or more words of the first portion of the first block. Whether data to be written to a particular virtual address is written to the first block or the second block may depend on the write status of the first block and the second block. | 07-26-2012 |
20120191902 | One-Die Flotox-Based Combo Non-Volatile Memory - A memory access apparatus that controls access to at least one memory array has an array of programmable comparison cells that retain a programmed pass code and compare it with an access pass code. When there is a match between the access pass code and the programmed pass code, the memory access apparatus generates a match signal for allowing access to the at least one memory array. If there is no match, the data within the at least one memory array may be corrupted or destroyed. Each nonvolatile comparison cell has a pair of series connected charge retaining transistors. The programmed pass code is stored in the charge retaining transistors. Primary and complementary query pass codes are applied to the charge retaining transistors and are logically compared with the stored pass code and based on the programmed threshold voltage levels determine if the query pass code is correct. | 07-26-2012 |
20120191903 | STORAGE APPARATUS AND METHOD OF MANAGING DATA STORAGE AREA - To extend endurance and reduce bit cost, a storage apparatus includes a controller and a first storage device and a second storage device having a smaller erase count upper limit than the first storage device. Area conversion information includes correspondence of a first address of a data storage destination and a second address of a data storage area The controller selects an area corresponding to the first address, determines whether a rewrite frequency of the selected area is equal to or larger than a first threshold and, when the rewrite frequency is equal to or larger than the threshold, selects an area of the first storage device, and, when the rewrite frequency is smaller than the threshold, selects an area of the second storage device and maps the address of the selected area to the first address. | 07-26-2012 |
20120191904 | SECONDARY CACHE FOR WRITE ACCUMULATION AND COALESCING - A method for efficiently using a large secondary cache is disclosed herein. In certain embodiments, such a method may include accumulating, in a secondary cache, a plurality of data tracks. These data tracks may include modified data and/or unmodified data. The method may determine if a subset of the plurality of data tracks makes up a full stride. In the event the subset makes up a full stride, the method may destage the subset from the secondary cache. By destaging full strides, the method reduces the number of disk operations that are required to destage data from the secondary cache. A corresponding computer program product and apparatus are also disclosed herein. | 07-26-2012 |
20120191905 | SEMICONDUCTOR MEMORY CARD ACCESS APPARATUS, A COMPUTER-READABLE RECORDING MEDIUM, AN INITIALIZATION METHOD, AND A SEMICONDUCTOR MEMORY CARD - A predetermined number of erasable blocks positioned at a start of a volume area in a semiconductor memory card are provided so as to include volume management information. A user area following the volume management information includes a plurality of clusters. A data length NOM of an area from a master boot record & partition table sector to a partition boot sector is determined so that the plurality of clusters in the user area are not arranged so as to straddle erasable block boundaries. Since cluster boundaries and erasable block boundaries in the user area are aligned, there is no need to perform wasteful processing in which two erasable blocks are erased to rewrite one cluster. | 07-26-2012 |
20120191906 | FLASH MEMORY MODULE AND STORAGE SYSTEM - A storage controller manages address conversion information denoting the correspondence relationship between a logical address and a physical address of storage area (for example, a physical block) inside a flash memory. The storage controller uses the above-mentioned address conversion information to specify a physical address corresponding to a logical address specified by an I/O request from a higher-level device, and sends an I/O command including I/O-destination information based on the specified physical address to a memory controller inside a flash memory module. The memory controller carries out the I/O with respect to a storage area inside a flash memory specified from the I/O-destination information of the I/O command from the storage controller. | 07-26-2012 |
20120198123 | SYSTEMS AND METHODS FOR REDUNDANTLY STORING METADATA FOR NON-VOLATILE MEMORY - Systems and methods are provided for storing data to or reading data from a non-volatile memory (“NVM”), such as flash memory, using a metadata redundancy scheme. In some embodiments, an electronic device, which includes an NVM, may also include a memory interface for controlling access to the NVM. The memory interface may receive requests to write user data to the NVM. The user data from each request may be associated with metadata, such as a logical address, a directional flag, or other data. In response to a write request, the NVM interface may store the user data and its associated metadata in a first memory location (e.g., page), and may store a redundant copy of the metadata in a second memory location. The directional flag indicates the geometric relationship between the first memory location and the second memory location. Thus, if the first memory location becomes inaccessible, the memory interface can still recover the metadata from the backup copy stored in the second memory location. | 08-02-2012 |
20120198124 | METHODS AND SYSTEMS FOR OPTIMIZING READ OPERATIONS IN A NON-VOLATILE MEMORY - Systems and methods are disclosed for increasing efficiency of read operations by selectively re-ordering a sequence in which logical block addresses (“LBAs”) are read out of multi-level cell (“MLC”) non-volatile memory. In one embodiment, the LBAs can correspond to upper and lower pages. Because data stored in lower pages can be retrieved from NVM faster than data stored in upper pages, embodiments disclosed herein can selectively re-order the LBAs such that the first LBA to be read corresponds to a lower page. | 08-02-2012 |
20120198125 | METHODS AND SYSTEMS FOR PERFORMING EFFICIENT PAGE READS IN A NON-VOLATILE MEMORY - Systems and methods are disclosed for increasing efficiency of read operations by selectively adding pages from a pagelist to a batch, such that when the batch is executed as a read operation, each page in the batch can be concurrently accessed. The pagelist can include all the pages associated a read command received, for example, from a file system. Although the pages associated with the read command may have an original read order sequence, embodiments according to this invention re-order this original read order sequence by selectively adding pages to a batch. A page is added to the batch if it does not collide with any other page already added to the batch. A page collides with another page if neither page can be accessed simultaneously. One or more batches can be constructed in this manner until the pagelist is empty. | 08-02-2012 |
20120198126 | METHODS AND SYSTEMS FOR PERFORMING SELECTIVE BLOCK SWITCHING TO PERFORM READ OPERATIONS IN A NON-VOLATILE MEMORY - Systems and methods are disclosed for increasing efficiency of read operations by minimizing the number of block switching events necessary to read each page associated with a read command. According to embodiments of this invention, for any given block containing one or more pages that need to be read for a read command, each of those one or more pages is read before switching to another block, thereby eliminating potential time penalties in switching between blocks. A block switching module according to embodiments of the invention instructs a NVM controller to read all relevant pages out of a given block even if an original read order sequence of the pages to be read would otherwise normally cause NVM controller to switch to another block. | 08-02-2012 |
20120198127 | COMPOSITE SOLID STATE DRIVE CONTROL SYSTEM - A composite solid state drive control system, composed of a redundant array of independent disks (RAID) formed by SD Cards, and multi-channel Flash Memory. Wherein, at least a RAID control unit combines a plurality of relatively inexpensive SD Cards into a set of redundant arrays of independent disks (RAIDs), so that its storage capacity can reach or even surpass a costly and huge capacity SD Card. Through controlling data transmission and accessing between at least a flash memory control unit and at least a SD Card control unit, data read and write speeds can be increased, and back-up redundant data can be made, hereby achieving stable operations of an electronic computing device by means of highly stable Flash Memory. | 08-02-2012 |
20120198128 | CONTROL ARRANGEMENTS AND METHODS FOR ACCESSING BLOCK ORIENTED NONVOLATILE MEMORY - A read/write arrangement is described for use in accessing at least one nonvolatile memory device in read/write operations with the memory device being made up of a plurality of memory cells which memory cells are organized as a set of pages that are physically and sequentially addressable with each page having a page length such that a page boundary is defined between successive ones of the pages in the set. The read/write arrangement includes a control arrangement that is configured to store and access a group of data blocks that is associated with a given write operation in a successive series of pages of the memory such that at least an initial page in the series is filled and each block includes a block length that is different than the page length. | 08-02-2012 |
20120198129 | AT LEAST SEMI-AUTONOMOUS MODULES IN A MEMORY SYSTEM AND METHODS - A memory system for digital data communication with a host device is described to provide data storage capacity. The system can include a controller and a plurality of modules, each module including a nonvolatile memory device wherein the module is configured to perform a management function with respect to the module at least partially based on a parameter. The parameter is provided by the controller and/or the module. The system and modules, in one feature, can support multiple forms of concurrency with respect to data accesses involving the modules. | 08-02-2012 |
20120198130 | STORAGE SYSTEM AND DATA CONTROL METHOD THEREFOR - A package controller of a flash package, upon receiving an update data write request with respect to a first logical storage area corresponding to a first LU that is treated as a backup target, manages a first physical storage area as a backup storage area in a state where pre-update data is maintained, newly allocates a second physical storage area to the first logical storage area, and writes the update data to the second physical storage area. The package controller, upon receiving an update data write request with respect to a second logical storage area corresponding to a second LU that is treated as a non-backup target, manages a third physical storage area allocated to the second logical storage area as an invalid storage area, and writes the update data to a fourth physical storage area newly allocated to the second logical storage area. The package controller performs control so as to use the first physical storage area to provide backup data for the first LU, and delete pre-update data stored in the third physical storage area. | 08-02-2012 |
20120198131 | DATA WRITING METHOD FOR REWRITABLE NON-VOLATILE MEMORY, AND MEMORY CONTROLLER AND MEMORY STORAGE APPARATUS USING THE SAME - A data writing method for writing data into physical blocks of a memory storage apparatus, and a memory controller and a memory storage apparatus using the same are provided, the physical blocks are grouped into a plurality of physical units. The method includes switching the speed mode of the memory storage apparatus into a first speed mode or a second speed mode according to a command and a work frequency received from a host system. The method also includes selecting a first writing mode to write the data into the physical units when the speed mode is the first speed mode. The method further includes selecting a second writing mode to write the data into the physical units when the speed mode is the second speed mode. Accordingly, the method can effectively shorten the time of executing a write command from the host system. | 08-02-2012 |
20120198132 | NON-VOLATILE MEMORY SYSTEM AND APPARATUS, AND PROGRAM METHOD THEREOF - A non-volatile memory system includes a memory area including one or more non-volatile memory apparatuses, and a controller includes a buffer for storing program data, and is configured to transmit a program command and the program data to the memory area and delete the program data stored in the buffer as a program operation is started in the memory area. | 08-02-2012 |
20120198133 | ELECTRONIC DEVICE WITH EXPANDABLE MEMORY CAPACITY AND AN EXPANSION METHOD THEREOF - An electronic device includes a processor, an internal memory for storing system information and installing programs, and a memory expansion interface for connecting an expansion memory. The expansion memory is partitioned into at least one region to expand the internal memory. The internal memory is partitioned into a system region and a user region; the system region is used to store system information while the user region can be controlled and used by a user. The processor further includes a detection unit and a memory management unit. The detection unit detects the connection of the expansion memory to the memory expansion interface, and the memory management unit determines whether the expansion memory has been previously configured to expand the internal memory, and if not, the memory management unit associates the expansion memory with the internal memory to expand the internal memory. | 08-02-2012 |
20120198134 | MEMORY CONTROL APPARATUS THAT CONTROLS DATA WRITING INTO STORAGE, CONTROL METHOD AND STORAGE MEDIUM THEREFOR, AND IMAGE FORMING APPARATUS - A memory control apparatus capable of preventing the performance from being lowered at the time of data deletion. The memory control apparatus includes a CPU and a storage controller of a main controller and includes a memory controller of an SSD of the main controller. The memory controller selectively performs first write processing to write data into a flash memory of the SSD or second write processing to write data into the flash memory after unnecessary data recorded in the flash memory is deleted. In a case where a deletion mode to delete unnecessary data is set, the CPU causes the memory controller to perform the second write processing, if the capacity of data to be written exceeds a predetermined data capacity. | 08-02-2012 |
20120198135 | Mapping Data to Non-Volatile Memory - The present disclosure includes systems and techniques relating to non-volatile memory. A described system, for example, includes a non-volatile memory structure having a plurality of multi-level memory cells, a processing device, and a controller. The controller is configured to map a first portion of a first set of consecutive bits of a data segment to a first page associated with the plurality of multi-level memory cells, and map a second portion of the first set of consecutive bits of the data segment to a second page associated with the plurality of multi-level memory cells. The first page is associated with bits of a first significance, and the second page is associated with bits of a second significance. | 08-02-2012 |
20120198136 | FLASH BACKED DRAM MODULE INCLUDING LOGIC FOR ISOLATING THE DRAM - A memory device for use with a primary power source including: non-volatile memory; volatile memory; an interface for connecting to a backup power source; isolation logic for controlling access to the volatile memory by a host processor, said isolation logic having a first mode during which the isolation logic provides the host processor with access to the volatile memory for storing or reading data and a second mode during which the isolation logic isolates the volatile memory from access by the host processor; and a controller controlling the isolation logic, said controller programmed to place the isolation logic in the first mode when the volatile memory is being powered by the primary power source and, when power to the volatile memory from the primary power source is interrupted, to place the isolation logic in the second mode and transfer data from the volatile memory to the non-volatile memory. | 08-02-2012 |
20120198137 | Logical-to-Physical Address Translation for a Removable Data Storage Device - A method for making memory more reliable involves accessing data stored in a removable storage device by translating a logical memory address provided by a host digital device to a physical memory address in the device. A logical memory address is received from the host digital device. The logical memory address corresponds to a location of data stored on the removable storage device. A physical memory address corresponding to the local address is determined by accessing a lookup table corresponding to the logical zone. | 08-02-2012 |
20120198138 | Managing Memory Systems Containing Components with Asymmetric Characteristics - A memory controller (MC) is associated with a remapping table to enable access to content in a memory system that includes asymmetric memory. The MC receives a request for a memory read or an Input/Output (I/O) write from a central processing unit (CPU) for a physical address specified by the system's memory management unit (MMU). The CPU uses the MMU to manage memory operations for the CPU, by translating the virtual addresses associated with CPU instructions into physical addresses representing system memory or I/O locations. The MC for asymmetric memories is configured to process the MMU-specified physical addresses as an additional type of virtual addresses, creating a layer of abstraction between the physical address specified by the MMU and the physical memory address with which that address is associated by the MC. The MC shields the CPU from the computational complexities required to implement a memory system with asymmetric components. | 08-02-2012 |
20120198139 | STORAGE DEVICE AND DEDUPLICATION METHOD - This storage device performs deduplication of eliminating duplicated data by storing a logical address of one or more corresponding logical unit memory areas in a prescribed management information storage area of a physical unit memory area defined in the storage area provided by the flash memory chip, and executes a reclamation process of managing a use degree as the total number of the logical addresses used stored in the management information storage area and a duplication degree as the number of valid logical addresses corresponding to the physical unit memory area for each of the physical unit memory areas, and returning the physical unit memory area to an unused status when the difference of the use degree and the duplication degree exceeds a default value in the physical unit memory area. | 08-02-2012 |
20120198140 | ASYMMETRIC MEMORY MIGRATION IN HYBRID MAIN MEMORY - Main memory is managed by receiving a command from an application to read data associated with a virtual address that is mapped to the main memory. A memory controller determines that the virtual address is mapped to one of the symmetric memory components of the main memory, and accesses memory use characteristics indicating how the data associated with the virtual address has been accessed, The memory controller determines that the data associated with the virtual address has access characteristics suited to an asymmetric memory component of the main memory and loads the data associated with the virtual address to the asymmetric memory component of the main memory. After the loading and using the memory management unit, a command is received from the application to read the data associated with the virtual address, and the data associated with the virtual address is retrieved from the asymmetric memory component. | 08-02-2012 |
20120198141 | INTEGRATING DATA FROM SYMMETRIC AND ASYMMETRIC MEMORY - Data stored within symmetric and asymmetric memory components of main memory is integrated by identifying a first data as having access characteristics suitable for storing in an asymmetric memory component. The first data is included among a collection of data to be written to the asymmetric memory component. An amount of data is identified within the collection of data to be written to the asymmetric memory component. The amount of data is compared within the collection of data to a volume threshold to determine whether a block write to the asymmetric memory component is justified by the amount of data. If justified, the collection of data is loaded to the asymmetric memory component. | 08-02-2012 |
20120198142 | SYSTEM AND APPARATUS FOR FLASH MEMORY DATA MANAGEMENT - The system and apparatus for managing flash memory data includes a host transmitting data, wherein when the data transmitted from the host have a first time transmission trait and the address for the data indicates a temporary address, temporary data are retrieved from the temporary address to an external buffer. A writing command is then executed and the temporary data having a destination address are written to a flash memory buffer. When the flash memory buffer is not full, the buffer data are written into a temporary block of the flash memory. The writing of buffer data into the temporary block includes using an address changing command, or executing a writing command to rewrite the external buffer data to the flash memory buffer so that the data are written into the temporary block. | 08-02-2012 |
20120203952 | PROTECTING GROUPS OF MEMORY CELLS IN A MEMORY DEVICE - Methods for memory block protection and memory devices are disclosed. One such method for memory block protection includes programming protection data to protection bytes diagonally across different word lines of a particular memory block (e.g., Boot ROM). The protection data can be retrieved by an erase verify operation that can be performed at power-up of the memory device. | 08-09-2012 |
20120203953 | CONCURRENTLY SEARCHING MULTIPLE DEVICES OF A NON-VOLATILE SEMICONDUCTOR MEMORY - A non-volatile semiconductor memory is disclosed comprising N memory devices each comprising a plurality of blocks, wherein each block comprises a plurality of memory segments accessed through an address. A searched is performed by issuing a read command for each of the N memory devices, wherein an address of each read command is separated by a distance determined in response to the search range of addresses and N, and the search range of addresses is greater than N. Data read from at least one of the memory devices is evaluated to determine whether the search has finished. | 08-09-2012 |
20120203954 | DATA STORAGE DEVICE - A data storage device comprises a multichannel flash memory assembly which is constructed by stacking of flash memory members. The data storage device is compact due to the use of stacked flash memory members which provides high speed performance due to its multiple data channel arrangement. A specific example is the use of a flash memory assembly comprising 4 stacked flash memory dies with 4 parallel data channels. This invention is advantageous because it provides a data storage device having a high data storage capability at high data transfer rates while maintaining a compact construction due to the high-rise stacked architecture. | 08-09-2012 |
20120203955 | DATA PROCESSING DEVICE AND SYSTEM INCLUDING THE SAME - A data processing system includes a host and a data processing device configured to store data output from the host. The data processing device includes a compressor configured to compress the data and sort compressed data according to a size of the compressed data and a buffer block configured to store the compressed data that has been sorted. | 08-09-2012 |
20120203956 | RECORDING DEVICE, CONTROL METHOD FOR RECORDING DEVICE, AND RECORDING MEDIUM - A recording device with nonvolatile memory suppresses the number of times the nonvolatile memory is written, avoiding memory failure and increasing printer | 08-09-2012 |
20120203957 | SOLID STATE MEMORY-BASED MASS STORAGE DEVICE USING OPTICAL INPUT/OUTPUT LINKS - A solid state memory-based mass storage device and a method of transferring data between a memory controller and at least one memory device of the mass storage device through optical input/output links that transmit multiplexed optical data signals between the memory device and controller. | 08-09-2012 |
20120203958 | STORAGE CONTROL SYSTEM WITH CHANGE LOGGING MECHANISM AND METHOD OF OPERATION THEREOF - A method of operation of a storage control system including: providing a memory controller; accessing a volatile memory table by the memory controller; writing a non-volatile semiconductor memory for persisting changes in the volatile memory table; and restoring a logical-to-physical table in the volatile memory table, after a power cycle, by restoring a random access memory with a logical-to-physical partition from a most recently used list. | 08-09-2012 |
20120203959 | NON-VOLATILE MEMORY, SYSTEM INCLUDING THE SAME, AND METHOD OF PROGRAMMING THE SAME - A method of programming a non-volatile memory that includes dumping first page data loaded to a cache latch to a first data latch and backing up the first page data to a second data latch. | 08-09-2012 |
20120203960 | APPARATUS AND METHOD FOR MULTI-LEVEL CACHE UTILIZATION - In some embodiments, a non-volatile cache memory may include a multi-level non-volatile cache memory configured to be located between a system memory and a mass storage device of an electronic system and a controller coupled to the multi-level non-volatile cache memory, wherein the controller is configured to control utilization of the multi-level non-volatile cache memory. Other embodiments are disclosed and claimed. | 08-09-2012 |
20120210045 | DATA ACCESS METHOD, AND MEMORY CONTROLLER AND MEMORY STORAGE APPARATUS USING THE SAME - A data access method for accessing a rewritable non-volatile memory module via a data bus through a first and a second thread module, and a memory controller and a memory storage apparatus using the same are provided. In the present method, an access executing right is assigned to the second thread module to write page data. Whether an access command to be executed by the first thread module is received is determined when the second thread module writes a predetermined amount of page data into a predetermined number of physical pages. The access executing right is assigned to the first thread module when the access command is received, so that the first thread module executes the access command in a foreground mode and the second thread module executes an ongoing task in a background mode. Thereby, timeout caused by delayed response of the first thread module is effectively avoided. | 08-16-2012 |
20120210046 | MEMORY SYSTEM ALLOWING HOST TO EASILY TRANSMIT AND RECEIVE DATA - According to one embodiment, a memory system includes a non-volatile semiconductor memory device, a control unit, a memory as a work area, a wireless communication module, and an extension register. The control unit controls the non-volatile semiconductor memory device. The extension register is provided in the memory and has a data length by which a wireless communication function of the wireless communication module can be defined. The control unit causes the non-volatile semiconductor memory device to store, as a file, an HTTP request supplied from a host, causes the extension register, based on a first command supplied from the host, to register an HTTP transmission command transmitted together with the first command, and causes the wireless communication module to transmit the HTTP request stored in the non-volatile semiconductor memory device based on the transmission command registered in the extension register. | 08-16-2012 |
20120210047 | RAM Daemons - A method of managing a database system using a swarm database system that communicates a request to read data to at least a subset of nodes. Checking the identifier by each respective node in the subset of nodes to determine if the requested read data is stored in the node. Providing the read data to the first node if the respective node in the subset includes read data. | 08-16-2012 |
20120210048 | SEMICONDUCTOR MEMORY DEVICE CAPABLE OF COMPRESSION AND DECOMPRESSION - A semiconductor memory device capable of compression and decompression is disclosed. With the semiconductor memory device having a built-in compression function, once external digital data need to be written to the semiconductor memory device, the semiconductor memory device can compress the external digital data and write the compressed external digital data to a semiconductor memory cell array, thereby enhancing data storage capacity. Furthermore, with the semiconductor memory device having a built-in decompression function, once electronic devices need to read data of the semiconductor memory device, the semiconductor memory device can decompress the data and output the decompressed data to the electronic devices. | 08-16-2012 |
20120210049 | MEMORY MODULE AND VIDEO CAMERA - According to the embodiments, there are provided semiconductor memories that are mounted individually on two sides of a mounting board; a controller that is mounted either on an obverse side or a reverse side of the mounting board, and performs read and write control of the semiconductor memories; and a connector that is deviated in a lateral direction from the controller so as not to overlap the controller, is mounted either on the obverse side or the reverse side of the mounting board, and transfers a signal exchanged between the controller and outside. | 08-16-2012 |
20120210050 | Selection of Data Storage Medium Based on Write Characteristic - A hybrid hard disk drive includes a hard disk drive controller to receive a plurality of write commands from a host, a buffer to receive and store write data, which are input through the hard disk drive controller and correspond to each of the plurality of write commands, a command history tracker to receive the plurality of write commands and analyze a pattern of the plurality of write commands, and a CPU to control storage of the write data, which correspond to each of the plurality of write commands, on a disk or in a flash memory device based on the analysis result by the command history tracker. The drive may determine whether to store write data on the disk or in the flash memory device without operation system support. | 08-16-2012 |
20120210051 | DISK DRIVE WITH STATE-INFORMATION DATA BUFFER - A hard-disk drive (HDD) is described. During operation of the HDD, measured internal temperatures in the HDD may be stored in a first table, and state information specifying operational states of the HDD associated with ranges of internal temperatures may be stored in a second table. Note that a given operational state in the second table may be associated with a corresponding internal temperature in the first table. Furthermore, during operation of the HDD, the first table and/or the second table may be stored on: a rotatable medium in the HDD, a semiconductor memory in the HDD, or both. This stored table information may facilitate error detection and diagnosis. | 08-16-2012 |
20120210052 | INTEGRATED CIRCUIT WITH COMPRESS ENGINE - An integrated circuit and method for modifying data by compressing the data in third dimensional memory technology is disclosed. In a specific embodiment, an integrated circuit is configured to perform compression of data disposed in third dimensional memory. For example, the integrated circuit can include a third dimensional memory array configured to store an input independent of storing a compressed copy of the input, a processor configured to compress the input to form the compressed copy of the input, and a controller configured to control access between the processor and the third dimensional memory array. The third dimension memory array can include one or more layers of non-volatile re-writeable two-terminal cross-point memory arrays fabricated back-end-of-the-line (BEOL) over a logic layer fabricated front-end-of-the-line (FEOL). The logic layer includes active circuitry for data operations (e.g., read and write operations) and data compression operations on the third dimension memory array. | 08-16-2012 |
20120210053 | Securing Non Volatile Data In RRAM - The various embodiments of the invention relate generally to semiconductors and memory technology. More specifically, the various embodiment and examples of the invention relate to memory devices, systems, and methods that protect data stored in one or more memory devices from unauthorized access. The memory device may include third dimension memory that is positioned on top of a logic layer that includes active circuitry in communication with the third dimension memory. The third dimension memory may include multiple layers of memory that are vertically stacked upon each other. Each layer of memory may include a plurality of two-terminal memory elements and the two-terminal memory elements can be arranged in a two-terminal cross-point array configuration. At least a portion of one or more of the multiple layers of memory may include an obfuscation layer configured to conceal data stored in one or more of the multiple layers of memory. | 08-16-2012 |
20120210054 | DATA STORAGE MEDIUM HAVING SECURITY FUNCTION AND OUTPUT APPARATUS THEREFOR - Provided are a storage medium, which has a security function, for storing media content and an output apparatus for outputting data stored in the storage medium. The storage medium includes a controller for converting at least one of a position of pins of a connector and a storage position of media content in a memory unit in order to control transmission of the media content in the memory unit to the output apparatus. | 08-16-2012 |
20120215962 | PARTITIONING PAGES OF AN ELECTRONIC MEMORY - A method of partitioning a page of an electronic memory includes creating a first sub-page by interleaving a first user data section of the page with another section of a spare area of the page excluding a specified address in a section of the spare area that stores a bad block marker. The method also includes creating the sub-pages by interleaving the user data sections with sections of the spare area excluding the specified address until a last sub-page is to be created. Further, the method includes creating the last sub-page by interleaving a last user data section with the section of the spare area that includes the specified address in an interleaving sequence that retains the bad-block marker at the specified address. | 08-23-2012 |
20120215963 | Semiconductor Memory Systems that Include Data Randomizers and Related Devices, Controllers and Methods - A semiconductor memory system and a programming method performed by the same. The semiconductor memory system includes: a semiconductor memory device having a storage area; a memory controller for controlling programming and reading of the storage area of the semiconductor memory device; at least one first randomizer for changing program data to be programmed into the storage area to first random data by using a first sequence in a first period; and at least one second randomizer for changing the first random data to second random data by using a second sequence in a second period that is different from the first period. | 08-23-2012 |
20120215964 | MANAGEMENT DEVICE AND MANAGEMENT METHOD - There is provided a management device including a management unit that manages a nonvolatile memory configured to allow data to be written, read, or erased electrically, allow writing and reading to be performed in units of a page, and allow erasing to be performed in units of a block including a plurality of pages. The management unit divides a plurality of physical blocks of the nonvolatile memory into a virtual area including virtual blocks corresponding to the physical blocks, and an alternate area including alternate blocks for replacing defective physical blocks in the virtual area, manages the nonvolatile memory in management units of three stages including management of the physical blocks, management of the virtual blocks, and management of extended blocks, and writes to the nonvolatile memory first, second, and third management information for use in the management of the physical blocks, the virtual blocks, and the extended blocks, respectively. | 08-23-2012 |
20120215965 | Storage Device and Computer Using the Same - A nonvolatile memory stores therein a plurality of partitioned translation tables which are created by partitioning a logical-to-physical address translation table in a page unit. A RAM stores therein a logical-to-physical address translation table cache for storing at least the one or more partitioned translation tables, a translation-table management table for managing the partitioned translation tables, and a cache management table for managing the logical-to-physical address translation table cache. The translation-table management table includes a cache presence-or-absence flag and a cache entry number, the cache presence-or-absence flag being used for indicating that the partitioned translation tables are stored into the logical-to-physical address translation table cache, the cache entry number being used for indicating storage destinations of the partitioned translation tables in the logical-to-physical address translation table cache. Reading/writing processings of information in the logical-to-physical address translation table between the nonvolatile memory and the RAM are performed in the page unit. | 08-23-2012 |
20120215966 | DISK ARRAY UNIT AND CONTROL METHOD THEREOF - The invention proposes a disk array unit capable of improving access performance. The disk array unit according to the invention includes: a plurality of semiconductor memories for storing data received from a host computer; a plurality of disk devices for storing the data; and a controller that redundantly configures the semiconductor memories and the disk devices by using a RAID 1 and controls reading of the data from the semiconductor memories or the disk devices. The controller reads the data from the semiconductor memories, and transmits the data, which are read from the semiconductor memories, to the host computer, when the semiconductor memories and the disk devices are in a normal state, or when the semiconductor memories are in an abnormal state and data areas of the semiconductor memories in which the data are stored are completely recovered. | 08-23-2012 |
20120215967 | NON-VOLATILE MEMORY DEVICES AND CONTROL AND OPERATION THEREOF - An improved non-volatile erase block memory device apparatus and method is described that incorporates an improved addressing scheme to provide for extended addressing allowing redundant erase blocks that are not utilized to repair general use erase blocks of the main memory array to be accessed and utilized as additional storage space by an end user. The additional storage space formed by the unused redundant erase blocks and the specified storage space of the main memory array is presented to the end user as a single contiguous address space. Additionally, the redundant erase blocks can be utilized to repair any damaged erase block in the memory array of the non-volatile erase block memory or Flash memory device regardless of bank placement. | 08-23-2012 |
20120215968 | CONTROL APPARATUS FOR CONTROLLING DATA READING AND WRITING TO FLASH MEMORY - To record data in a flash memory, upon detecting that a current destination memory block is full, a control apparatus records data in a destination memory block one block by one block, with “in-advance” data erasure of the next memory block and by determining if data erasure of the next memory block is successful. When data erasure of the next memory block fails, such memory block is designated as broken, and such memory block is excluded from a group of blocks to be used as recording destination. After determining the data erasure result of a yet-next memory block is successful, the required data is copied to the yet-next memory block. Therefore, even when one of the blocks is broken, a sequential data recording in the flash memory is performed without increasing the number of data copy operations between blocks. | 08-23-2012 |
20120215969 | STORAGE DEVICE AND CONTROL METHOD THEREOF - According to one embodiment, a storage device includes: a backup unit configured to perform backup at the time of a power shutoff; a storage module configured to store information; a cache memory configured to perform caching of the storage module; and a controller configured to adjust a size of a cache to the cache memory according to exhaustion of the backup unit. | 08-23-2012 |
20120215970 | Storage Management and Acceleration of Storage Media in Clusters - Examples of described systems utilize a solid state device cache in one or more computing devices that may accelerate access to other storage media. In some embodiments, the solid state drive may be used as a log structured cache, may employ multi-level metadata management, and may use read and write gating, or combinations of these features. Cluster configurations are described that may include local solid state storage devices, shared solid state storage devices, or combinations thereof, which may provide high availability in the event of a server failure. | 08-23-2012 |
20120215971 | Firehose Dump of SRAM Write Cache Data to Non-Volatile Memory Using a Supercap - A mechanism is provided for firehose dumping modified data in a static random access memory of a hard disk drive to non-volatile memory of the hard disk drive during a power event. Responsive an indication of a power event in the hard disk drive, hard disk drive command processing is suspended. A token is set in the non-volatile storage indicating that flash memory in the non-volatile memory contains modified data. A portion of a static random access memory cache table containing information on the modified data in the static random access memory is copied to the flash memory. The modified data from the static random access memory is then copied to the flash memory. Responsive to a determination that the power event that initiated the copy of the modified data in the static random access memory to the flash memory is still present, the hard disk drive is shut down. | 08-23-2012 |
20120215972 | LOGICAL ADDRESS OFFSET IN RESPONSE TO DETECTING A MEMORY FORMATTING OPERATION - The present disclosure includes methods, devices, and systems for a logical address offset. One method embodiment includes detecting a memory unit formatting operation. Subsequently, in response to detecting the formatting operation, the method includes inspecting format information on the memory unit, calculating a logical address offset, and applying the offset to a host logical address. | 08-23-2012 |
20120215973 | Method Apparatus and System for a Redundant and Fault Tolerant Solid State Disk - A solid state drive includes a first solid state disc controller (SSDC), a second SSDC and a flash array. The flash array includes a first flash port and a second flash port. The first SSDC is configured to connect to the flash array through the first flash port and the second flash array is configured to connect to the flash array through the second flash port. The first SSDC and the second SSDC are both configured to connect to all memory within the flash array and the first SSDC, second SSDC, and flash array are within a common solid state drive. | 08-23-2012 |
20120215974 | MEMORY WITH OUTPUT CONTROL - An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices. | 08-23-2012 |
20120221766 | FLASH MEMORY APPARATUS WITH SERIAL INTERFACE AND RESET METHOD THEREOF - A flash memory apparatus with serial interface is disclosed. The flash memory apparatus includes a selector, a core circuit and a programmable data bank. The selector decides whether or not to connect one of a write protect pin and a hold pin to a reset signal line. The core circuit receives a reset signal transmitted by the reset signal line and activates a reset operation accordingly. A selecting data is written into the programmable data bank through a programming method and the programmable data bank outputs the selecting data to serve as a selecting signal. | 08-30-2012 |
20120221767 | EFFICIENT BUFFERING FOR A SYSTEM HAVING NON-VOLATILE MEMORY - Systems and methods are disclosed for efficient buffering for a system having non-volatile memory (“NVM”). In some embodiments, a control circuitry of a system can use heuristics to determine whether to perform buffering of one or more write commands received from a file system. In other embodiments, the control circuitry can minimize read energy and buffering overhead by efficiently re-ordering write commands in a queue along page-aligned boundaries of a buffer. In further embodiments, the control circuitry can optimally combine write commands from a buffer with write commands from a queue. After combining the commands, the control circuitry can dispatch the commands in a single transaction. | 08-30-2012 |
20120221768 | UNIVERSAL CACHE MANAGEMENT SYSTEM - Techniques for universal cache management are described. In an example embodiment, a plurality of caches are allocated, in volatile memory of a computing device, to a plurality of data-processing instances, where each one of the plurality of caches is exclusively allocated to a separate one of the plurality of data-processing instances. A common cache is allocated in the volatile memory of the computing device, where the common cache is shared by the plurality of data-processing instances. Each instance of the plurality of data-processing instances is configured to: indentify a data block in the particular cache allocated to that instance, where the data block has not been changed since the data block was last persistently written to one or more storage devices; cause the data block to be stored in the common cache; and remove the data block from the particular cache. Data blocks in the common cache are maintained without being persistently written to the one or more storage devices. | 08-30-2012 |
20120221769 | RECONFIGURABLE MEMORY CONTROLLER - Embodiments of a memory controller are described. This memory controller includes signal connectors, which are electrically coupled to a communication path that includes multiple links, and an interface circuit, which is electrically coupled to the signal connectors. In a first operating mode, the interface circuit communicates with a first memory device via the communication path using spatial multiplexing, in which there are dedicated command/address links and dedicated data links in the communication path. Moreover, in a second operating mode, the interface circuit communicates with a second memory device via the communication path using time multiplexing, in which at least some of the links in the communication path time interleave command/address information and data. | 08-30-2012 |
20120221770 | MEMORY SYSTEM CAPABLE OF PROHIBITING ACCESS TO APPLICATION SOFTWARE AND SYSTEM SOFTWARE - According to one embodiment, a memory system includes an application module, a storage module, and a control module. The storage module stores user data, application software configured to control operation of the application module, and management information used to manage the user data and the application software. The control module controls writing and erasing of the storage module. The control module masks information indicating an access-prohibited area included in the management information read from the storage module, the access-prohibited area includes the application software. | 08-30-2012 |
20120221771 | DATA STORAGE SYSTEM AND DATA MAPPING METHOD OF THE SAME - A data mapping method is performed by a memory controller in a data storage system configured to control a nonvolatile memory device having a plurality of channels, where each channel includes a plurality of nonvolatile memories. The data mapping method includes selecting channels of the plurality of channels to be active channels to which data input from a host are written in response to a request from the host, including nonvolatile memories corresponding to each of the active channels in a candidate zone list as active zones, and sequentially writing the data input from the host to the active zones included in the candidate zone list. | 08-30-2012 |
20120221772 | SEMICONDUCTOR MEMORY DEVICES, SYSTEMS INCLUDING NON-VOLATILE MEMORY READ THRESHOLD VOLTAGE DETERMINATION - A semiconductor memory system can include a memory device having a memory cell array that includes a plurality of memory cells. A memory controller can be configured to perform domain transformation on data written to and/or read from the plurality of memory cells to provide domain-transformed data and configured to perform signal processing on the domain-transformed data to output processed data or a control signal. | 08-30-2012 |
20120221773 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - The disclosed invention provides a technique for efficiently avoiding read disturbance. A nonvolatile semiconductor memory device includes a nonvolatile memory unit and a controller that can control refresh processing for rewriting data in a block of blocks assumed to be erasable units in the nonvolatile memory unit into anther block different from the block. The controller sets up a first area and a second area different from the first area in the nonvolatile memory unit and, each time a refresh trigger occurs, executes refresh processing for the first area and the second area, such that a refresh frequency of data in the first area will become higher than a refresh frequency of data in the second area. Thereby, it is possible to efficiently avoid read disturbance when read access is repeated. | 08-30-2012 |
20120221774 | APPARATUS, SYSTEM, AND METHOD FOR MANAGING CONTENTS OF A CACHE - An apparatus, system, and method are disclosed for managing contents of a cache. A storage request module monitors storage requests received by a cache. The storage requests include read requests and write requests. A read pool module adjusts a size of a read pool of the cache to maximize a read hit rate of the storage requests. A dirty write pool module adjusts a size of a dirty write pool of the cache to maximize a dirty write hit rate of the storage requests. | 08-30-2012 |
20120221775 | NON-VOLATILE MEMORY DEVICE AND READ METHOD THEREOF - An apparatus and a method for reading from a non-volatile memory whereby soft decision data is used to determine the reliability of hard decision data. The hard decision data read from the non-volatile memory is de-randomized and the soft decision data read from the non-volatile memory is not de-randomized. Using the soft decision data, the hard decision data is decoded. | 08-30-2012 |
20120221776 | SEMICONDUCTOR STORAGE DEVICE - According to the embodiments, a first storage area and a second storage area specified by a trim request is managed by a first management unit, and the second storage area specified by the trim request is managed by a second management unit. A block in which data of the first management unit are all specified by the trim request from the first or second storage areas and a block in which data of the second management unit are all specified by the trim request from the second storage area are released. | 08-30-2012 |
20120221777 | TRANSFERRING LEARNING METADATA BETWEEN STORAGE SERVERS HAVING CLUSTERS VIA COPY SERVICES OPERATIONS ON A SHARED VIRTUAL LOGICAL UNIT THAT STORES THE LEARNING METADATA - A virtual logical unit that stores learning metadata is allocated in a first storage server having a first plurality of clusters, wherein the learning metadata indicates a type of storage device in which selected data of the first plurality of clusters of the first storage server are stored. A copy services command is received to copy the selected data from the first storage server to a second storage server having a second plurality of clusters. The virtual logical unit that stores the learning metadata is copied, from the first storage server to the second storage server, via the copy services command. Selected logical units corresponding to the selected data are copied from the first storage server to the second storage server, and the learning metadata is used to place the selected data in the type of storage device indicated by the learning metadata. | 08-30-2012 |
20120221778 | SUB-LUN INPUT/OUTPUT PROFILING FOR SSD DEVICES - A read/write ratio for each of a plurality of data segments classified in a hot category as hot data segments is determined. Each of the plurality of hot data segments is ordered by the read/write ratio in a descending order. Each of a plurality of available SSD devices is ordered by a remaining life expectancy in an ascending order. Those of the plurality of hot data segments are matched with those of the plurality of hot data segments with those of the plurality of available SSD devices such that a hot data segment having a higher read/write ratio is provided to an SSD device having a smaller remaining life expectancy than another hot data segment having a lower read/write ratio. | 08-30-2012 |
20120221779 | PROGRAMMING MEMORY DEVICES - A target memory cell of a memory device is programmed by applying a programming voltage to a word line that includes the target memory cell, determining whether the target memory cell is programmed, and increasing the programming voltage by a step voltage if it is determined that the target memory cell is not programmed. An initial programming voltage and the step voltage are each selectable after fabrication of the memory device. | 08-30-2012 |
20120221780 | INCREASED NAND FLASH MEMORY READ THROUGHPUT - A method of reading sequential pages of flash memory from alternating memory blocks comprises loading data from a first page into a first primary data cache and a second page into a second primary data cache simultaneously, the first and second pages loaded from different blocks of flash memory. Data from the first primary data cache is stored in a first secondary data cache, and data from the second primary data cache is stored in a second secondary data cache. Data is sequentially provided from the first and second secondary data caches by a multiplexer coupled to the first and second data caches. | 08-30-2012 |
20120221781 | FLASH-BASED MEMORY SYSTEM WITH VARIABLE LENGTH PAGE STRIPES INCLUDING DATA PROTECTION INFORMATION - Methods and apparatuses for enhanced protection of data stored in a FLASH memory system involve a controller capable of adapting to the failure of one or more FLASH memory devices in the memory system. The controller stores data in the form of page stripes, each page stripe composed of data pages, and each data page stored in a different FLASH memory device. The controller also detects failure of a FLASH memory device in which a data page of a particular page stripe is stored, reconstructs the data page, and stores the reconstructed data page in a new page stripe, where the number of data pages in the new page stripe is less than the number of data pages in the particular page stripe, and where no page of the new page stripe is stored in a memory location within the failed FLASH memory device. | 08-30-2012 |
20120221782 | METHOD FOR MANAGING A MEMORY APPARATUS, AND ASSOCIATED MEMORY APPARATUS THEREOF - A method for managing a memory apparatus including at least one non-volatile (NV) memory element includes: recording usage information of at least one block, for use of managing the memory apparatus. For example, the method may further include: determining whether to erase a portion of blocks according to the usage information, where the usage information may include a valid/invalid page count table for recording valid/invalid page counts of the blocks, respectively. In another example, the method may further include: erasing at least a particular block of the blocks according to the usage information, where the usage information may include count information for representing valid/invalid page counts of the particular block, or include page count information for representing a number of effectively linked page of the particular block. Associated memory apparatus are also provided. | 08-30-2012 |
20120221783 | SYSTEM AND METHOD FOR ALLOCATING CAPACITY - For a storage apparatus where flash memory disks and hard disks coexist, high-density mounting of flash memory modules is achieved. The storage apparatus includes flash memories and a storage controller. A second storage apparatus including magnetic disks is connected to the storage apparatus. The storage controller can form a storage area using a flash memory or a magnetic disk to create a logical volume. When an input/output request is issued from a host computer, if a storage area is formed with a flash memory, the storage controller directly accesses the flash memory to handle the request. When the storage apparatus defines a storage area formed with a flash memory, the storage apparatus defines the storage area by adding up the capacity of a storage area to be provided for the host computer and a substitute area capacity determined in consideration of restrictions on the number deletions of the flash memory. | 08-30-2012 |
20120221784 | MEMORY CONTROLLER AND METHODS FOR ENHANCING WRITE PERFORMANCE OF A FLASH DEVICE - A memory controller and methods for managing efficient writing to a flash memory are presented. Fresh data is written to at least one block of the flash memory. During a space reclamation process, other data, previously written to the flash memory, is relocated to at least one other block of the flash memory, such that the fresh data and the relocated data always are maintained in separate blocks of the flash memory. During writing, an update frequency level is selected for the fresh data from among multiple update frequency levels and the fresh data is written to a block that is associated with the selected update frequency level. During space reclamation, a plurality of blocks, space of which is to be reclaimed, is selected and the valid pages thereof are copied to at least one destination block. | 08-30-2012 |
20120226851 | ISOLATION DEVICES FOR HIGH PERFORMANCE SOLID STATE DRIVES - Systems and methods are provided for coupling multiple flash devices to a shared bus utilizing isolation switches within a SSD device. The SSD device is operable at a speed of about 400 MT/s or higher with high signal integrity. The SSD device includes a controller, a channel in electrical communication with the controller, a plurality of isolation devices in electrical communication with channel, and a plurality of flash memory devices, wherein each flash memory device is in electrical communication with the channel and controller through the one of the isolation devices. | 09-06-2012 |
20120233380 | SYSTEMS, DEVICES, MEMORY CONTROLLERS, AND METHODS FOR CONTROLLING MEMORY - Systems, devices, memory controllers, and methods for controlling memory are described. One such method includes activating a memory unit of a memory device; after activating the memory unit, providing a command to the memory device; and returning the memory unit to a previous state if the command does not indicate a target memory volume, wherein the memory unit remains active if the command indicates a target memory volume associated with the memory unit. | 09-13-2012 |
20120233381 | REMAPPING FOR MEMORY WEAR LEVELING - A method and a corresponding apparatus provide for remapping for wear leveling of a memory ( | 09-13-2012 |
20120233382 | DATA STORAGE APPARATUS AND METHOD FOR TABLE MANAGEMENT - According to one embodiment, a data storage apparatus includes a first memory configured to store a first management table, a second memory configured to store a second management table, a counter table memory, and a controller. The first management table has address data representing a storage position of data stored in a flash memory. The second memory has address data representing valid data included in the data stored in the flash memory. The counter table memory stores a counter table showing the count value of valid data in units of addresses. The controller is configured to refer to the first management table, to compare the number of data valid in units of addresses acquired by referring to the first management table, and to perform a matching check process for determining matching between the first and second management tables from a result of the comparison. | 09-13-2012 |
20120233383 | MEMORY SYSTEM AND MEMORY CONTROLLER - A memory system according to the embodiment comprises a memory device including a plurality of memory cells operative to store storage data, the storage containing input data from external to which parity information is added; and a memory controller operative to convert between the input data and the storage data, the storage data containing information data corresponding to the input data, and a relationship between the information data and the input data being nonlinearly. | 09-13-2012 |
20120233384 | METHODS AND SYSTEM FOR ERASING DATA STORED IN NONVOLATILE MEMORY IN LOW POWER APPLICATIONS - The erasing of data stored in a nonvolatile memory is performed using multiple partial erase operations. Each partial erase operation has a time duration that is shorter than the minimum time duration of an erase operation that is needed to reliably erase the data stored in the storage location. However, the sum of the time durations of the multiple partial erase operations is sufficient to reliably erase the data in the storage location. In one example, during a partial erase operation, a voltage is applied to a memory storage transistor to remove some, but not necessarily all, of the charge stored on a charge storage layer of the transistor. Following multiple partial erase operations, sufficient charge is removed from the charge storage layer to ensure reliable data erasure. | 09-13-2012 |
20120233385 | HARD DISK DRIVE WITH OPTIONAL CACHE MEMORY - A computer system includes a hard disk drive, a processor coupled to the hard disk drive, and a cache interface coupled to the processor and detachably connectable to a cache memory. The processor is adapted, subsequent to an initial interrogation of the cache interface, to determine whether the cache memory is connected to the cache interface by inspecting an indication of the presence or the absence of the cache memory, the indication being stored in a register in the processor or in a memory associated with the processor such that the inspecting avoids repeat interrogation of the cache interface, to communicate with the cache memory and the hard disk drive such that the processor has access to the cache memory when the cache memory is connected to the cache interface, and to communicate with the hard disk drive when the cache memory is disconnected from the cache interface. | 09-13-2012 |
20120233386 | MULTI-INTERFACE SOLID STATE DISK, PROCESSING METHOD AND SYSTEM OF MULTI-INTERFACE SOLID STATE DISK - Embodiments of the present disclosure disclose a multi-interface solid state disk, and a processing method and system of the multi-interface solid state disk. The multi-interface solid state disk according to the present disclosure includes: plurality of interface control units, a command scheduling unit, a flash control unit and a flash chip. Each interface control unit corresponds to a communication interface respectively. The interface control unit receives an operating command through the communication interface. The command scheduling unit obtains, according to a scheduling rule, operating commands from the plurality of interface control units, puts the operating commands in a command queue, takes an operating command from the command queue, and sends the operating command to the flash control unit. The flash control unit converts the operating command into a flash operating command to operate the flash chip. | 09-13-2012 |
20120233387 | Copyback Optimization for Memory System - In a copyback or read operation for a non-volatile memory subsystem, data page change indicators are used to manage transfers of data pages between a register in non-volatile memory and a controller that is external to the non-volatile memory. | 09-13-2012 |
20120233388 | DATA WRITING METHOD FOR NON-VOLATILE MEMORY, AND CONTROLLER AND STORAGE SYSTEM USING THE SAME - A data writing method for writing data from a host system into a plurality of memory dies of a rewritable non-volatile memory storage apparatus is provided. The data writing method includes determining whether the data transmission interface of the host system complies with a first interface standard or a second interface standard. The data writing method also includes using a general mode to write the data into the memory dies when the data transmission interface of the host system complies with the first interface standard and using a power saving mode to write the data into the memory dies when the data transmission interface of the host system complies with the second interface standard. Accordingly, the data writing method can effectively prevent the stability of the rewritable non-volatile memory storage apparatus from reducing due to insufficient power supplied by the data transmission interface. | 09-13-2012 |
20120233389 | MULTI-HOST CONCURRENT WRITING TO MAGNETIC TAPE - According to one embodiment, a method for storing data on a magnetic tape comprises receiving data from two different hosts and simultaneously writing the data from the hosts to the magnetic tape using multiple transducers. In another approach, a method for storing data on a magnetic tape comprises receiving requests to establish a concurrent reservation from multiple hosts and allocating a unique stripe in a wrap to each of the hosts that sent the requests, wherein the wrap is a collection of data tracks to be written simultaneously in one direction of tape movement by multiple transducers of a tape head, and the wrap is logically divided into the stripes. Also, the method includes receiving data from the hosts and simultaneously writing the data from the hosts to the magnetic tape using the multiple transducers. Other systems and methods concerning storing data on magnetic tapes are described as well. | 09-13-2012 |
20120233390 | DATA UPDATE METHOD AND FLASH MEMORY APPARATUS UTILIZING THE SAME - A flash memory apparatus includes a plurality of blocks comprising a first block, wherein the first block comprises a first page; and a memory controller receiving a first data to be written into the first page of the first block, and when the first page has already been written to, the memory controller further selects one of the blocks as a first cache block, writes the first data into a first cache page of the first cache block and records a number of the first block and a number of the first page into the first cache page, and when receiving a command for updating the first block, the memory controller further updates the first block according to the number of the first block and the number of the first page recorded in the first cache page. A data update method for such a flash memory is also described. | 09-13-2012 |
20120233391 | Efficient Reduction of Read Disturb Errors in NAND FLASH Memory - Methods and apparatuses for reduction of Read Disturb errors in a NAND FLASH memory system comprise a controller configured to organize FLASH memory devices into blocks, each block having a plurality of pages, and each page defining an individually addressable physical memory location. The controller is further configured to accumulate a Block READ Count corresponding to the number of times any pages in a first block of pages have been read since the first block was last erased. Once the READ count reaches a predetermined number, the controller responds to subsequent READ requests for pages within the first block by moving data associated with a requested page to a page in a second, different block without moving data associated with other pages in the first block, and modifying a logical-to-physical translation table to associate the moved data with the physical address of the page in the second block. | 09-13-2012 |
20120233392 | SOLID STATE STORAGE DEVICE CONTROLLER WITH EXPANSION MODE - Solid state storage device controllers, solid state storage devices, and methods for operation of solid state storage device controllers are disclosed. In one such solid state storage device, the controller can operate in either an expansion DRAM mode or a non-volatile memory mode. In the DRAM expansion mode, one or more of the memory communication channels normally used to communicate with non-volatile memory devices is used to communicate with an expansion DRAM device. | 09-13-2012 |
20120239851 | PRIORITIZED ERASURE OF DATA BLOCKS IN A FLASH STORAGE DEVICE - Methods and systems for the prioritized erasure of data blocks in a flash storage device are provided. A data block in the flash storage device is selected for erasure based upon the number of valid data segments therein, thereby minimizing the number of data segments that are carried over to another data block before erasing the selected data block. The overhead of write operations in the flash storage device is therefore greatly reduced, and the overall performance thereof greatly increased. A method for managing memory operations in a flash storage device having a plurality of data blocks comprises the steps of selecting one of the plurality of data blocks for erasure based upon a number of valid data segments therein, and erasing the selected one of the plurality of data blocks. | 09-20-2012 |
20120239852 | HIGH SPEED INPUT/OUTPUT PERFORMANCE IN SOLID STATE DEVICES - A method of transferring data in a flash storage device comprising a random access memory and a plurality of channels of a flash array is provided. The method comprises receiving a plurality of data segments from a host system, storing the plurality of data segments in the random access memory, allocating the plurality of data segments among the plurality of channels of the flash array, and writing the allocated data segments from the random access memory to the respective channels of the flash array. | 09-20-2012 |
20120239853 | SOLID STATE DEVICE WITH ALLOCATED FLASH CACHE - A flash storage device, and methods for a flash storage device, having improved write performance are provided. Data is received from a host system, the data comprising a data segment, the data segment is temporarily stored in a data buffer of the random access memory, the data segment is assigned to a logical block address, and the data segment is written to an allocated cache portion of the flash memory. Subsequently, the data segment is written from the allocated cache portion of the flash memory to a main storage portion of the flash memory. | 09-20-2012 |
20120239854 | FLASH STORAGE DEVICE WITH READ CACHE - A flash storage device includes a first memory, a flash memory comprising a plurality of physical blocks, each of the plurality of physical blocks comprising a plurality of physical pages, and a controller. The controller is configured to store, in the first memory, copies of data read from the flash memory, map a logical address in a read request received from a host system to a virtual unit address and a virtual page address, and check a virtual unit cache tag table stored in the first memory based on the virtual unit address. If a hit is found in the virtual unit cache tag table, a virtual page cache tag sub-table stored in the first memory is checked based on the virtual page address, wherein the virtual page cache tag sub-table is associated with the virtual unit address. If a hit is found in the virtual page cache tag sub-table, data stored in the first memory mapped to the hit in the virtual page cache tag sub-table is read in response to the read request received from the host system. | 09-20-2012 |
20120239855 | SOLID-STATE STORAGE DEVICE WITH MULTI-LEVEL ADDRESSING - A solid-state storage device with multi-level addressing is provided. The solid-state storage device includes a plurality of flash memory devices, a volatile memory, and a controller. The controller is configured to store data received from a host in the plurality of flash memory devices in response to a write command and to read the data stored in the plurality of flash memory devices in response to a read command. The controller is further configured to maintain a multi-level address table that maps logical addresses received from the host identifying the data stored in the plurality of flash memory devices to physical addresses in the plurality of flash memory devices containing the data. A first level of the multi-level address table is maintained by the controller in the volatile memory and second and third levels of the multi-level address table are maintained by the controller in the plurality of flash memory devices. | 09-20-2012 |
20120239856 | HYBRID SYSTEM ARCHITECTURE FOR RANDOM ACCESS MEMORY - Embodiments of the present invention provide a hybrid system architecture random access memory (RAM) such as Phase-Change RAM (PRAM), Magnetoresistive RAM (MRAM) and/or Ferroelectric RAM (FRAM). Specifically, embodiments of this invention provide a hybrid RAID controller coupled to a system control board. Coupled to the hybrid RAID controller are a DDR RAID controller, a RAM RAID controller, and a HDD/Flash RAID controller. A DDR RAID control block is coupled to the DDR RAID controller and includes (among other things) a set of DDR memory disks. Further, a RAM control block is coupled to the RAM RAID controller and includes a set of RAM SSDs. Still yet, a HDD RAID control block is coupled to the HDD/Flash RAID controller and includes a set of HDD/Flash SSD Units. | 09-20-2012 |
20120239857 | SYSTEM AND METHOD TO EFFICIENTLY SCHEDULE AND/OR COMMIT WRITE DATA TO FLASH BASED SSDs ATTACHED TO AN ARRAY CONTROLLER - An apparatus comprising a controller and an array. The controller may be configured to generate control signals in response to one or more input requests. The array may comprise a plurality of solid state devices. The solid state devices may be configured to (i) read and/or write data in response to the control signals received from the controller and (ii) distribute writes across the plurality of solid state devices such that each of said solid state devices has a similar number of writes. | 09-20-2012 |
20120239858 | APPARATUS AND METHOD FOR DETERMINING AN OPERATING CONDITION OF A MEMORY CELL BASED ON CYCLE INFORMATION - Disclosed is an apparatus and method for determining a parameter for programming a non-volatile memory circuit. On receiving write or erase operation a parameter is determined as a function of a circuit characteristic associated with a memory block. An adjusted condition, for example, read or write time, or the standard deviation of voltage thresholds in a distribution of cells, is then determined as a function of the parameter, and a command provided to the memory circuit to use the parameter in the next write or erase operation performed on the memory block. The method can be triggered by an event such as P/E cycle times and the condition is dynamically adjusted to extend the life of the memory circuit. | 09-20-2012 |
20120239859 | APPLICATION PROFILING IN A DATA STORAGE ARRAY - Method and apparatus for application profiling in a multi-device data storage array. In accordance with various embodiments, a storage array is formed of independent data storage devices that form a fast pool and a slow pool of said devices, such as solid-state drives (SSDs) and hard disc drives (HDDs). A controller is adapted to migrate a distributed data set stored across a first plurality of the devices in the slow pool to a second plurality of said devices in the fast pool. The controller carries out the migration responsive to a hint that a selected application is about to be executed that utilizes the distributed data set, and responsive to a return on investment (ROI) determination that an estimated cost of said migration will be outweighed by an overall improved data transfer capacity of the storage array over a predetermined minimum payback period of time. | 09-20-2012 |
20120239860 | APPARATUS, SYSTEM, AND METHOD FOR PERSISTENT DATA MANAGEMENT ON A NON-VOLATILE STORAGE MEDIA - Data is stored on a non-volatile storage media in a sequential, log-based format. The formatted data defines an ordered sequence of storage operations performed on the non-volatile storage media. A virtual storage layer maintains volatile metadata, which may include a forward index associating logical identifiers with respective physical storage units on the non-volatile storage media. The volatile metadata may be reconstructed from the ordered sequence of storage operations. Persistent notes may be used to maintain consistency between the volatile metadata and the contents of the non-volatile storage media. Persistent notes may identify data that does not need to be retained on the non-volatile storage media and/or is no longer valid. | 09-20-2012 |
20120239861 | NONVOLATILE MEMORY DEVICES WITH PAGE FLAGS, METHODS OF OPERATION AND MEMORY SYSTEMS INCLUDING SAME - A method programming multi-bit data to multi-level non-volatile memory cells (MLC) includes; programming a first page of data to the MLC, programming a first page flag to an initial first flag state in response in the programming of the first page, programming a second page of data to the MLC, in response to programming the second page, determining whether the first page has been programmed and if the first page has been programmed, programming the first page flag to a final first flag state different from the initial first flag state in response to programming of the second page, and if the first page has not been programmed, inhibiting programming of the first page flag during programming of the second page. | 09-20-2012 |
20120239862 | MEMORY CONTROLLER CONTROLLING A NONVOLATILE MEMORY - Described is a memory controller interfacing with a host and a nonvolatile memory. The memory controller may include a buffer unit configured to store an input address table and a first hot address table; and a processing unit configured to judge whether an address from the host coincides with one of addresses stored in the input address table and to store the address from the host in the first hot address table according to the judgment. | 09-20-2012 |
20120239863 | NONVOLATILE MEMORY SYSTEMS WITH EMBEDDED FAST READ AND WRITE MEMORIES - A nonvolatile memory system is described with novel architecture coupling nonvolatile storage memory with random access volatile memory. New commands are included to enhance the read and write performance of the memory system. | 09-20-2012 |
20120239864 | CACHING SCHEME SYNERGY FOR EXTENT MIGRATION BETWEEN TIERS OF A STORAGE SYSTEM - A method according to one embodiment includes determining to move an extent from a source-tier in a storage system to a destination-tier in the storage system; determining whether any track from the set of tracks is presently being written to; designating to a write-stack associated with the source-tier each track that is presently being written to and designating to a read-stack associated with the source-tier remaining tracks from the set of tracks; removing oldest tracks from the read-stack and the write-stack until the read-stack and the write-stack have been depleted of tracks; when a parameter of the extent exceeds a migration threshold: populating a destination-tier cache with the tracks as they are removed from the read-stack and the write-stack using a predetermined read-to-write ratio and removing tracks from a source-tier cache that were removed from the read-stack and the write-stack; and migrating the extent from the source-tier to the destination-tier. | 09-20-2012 |
20120239865 | STORAGE DEVICE - A storage device realizing an improvement in rewrite endurance of a nonvolatile memory and an improvement in data transfer rate of write and read operations is provided including a nonvolatile memory; a volatile memory for storing file management information of the nonvolatile memory; a controller for controlling the nonvolatile memory and the volatile memory; and a power supply maintaining unit for supplying power to the nonvolatile memory, the volatile memory, or the controller upon power shutdown. The controller reads the file management information in the nonvolatile memory upon power-on and writes the same in the volatile memory, and read and write operations are performed based on the file management information in the volatile memory, and the file management information in the volatile memory is written in the nonvolatile memory upon power shutdown. | 09-20-2012 |
20120239866 | NON-VOLATILE MEMORY WITH ERROR CORRECTION FOR PAGE COPY OPERATION AND METHOD THEREOF - The disclosure is a NAND flash memory with the function of error checking and correction during a page copy operation. The NAND flash memory is able to prohibit transcription of erroneous bits to a duplicate page from a source page. Embodiments of the inventive flash memory include a correction circuit for correcting bit errors of source data stored in a page buffer, a circuit configured to provide the source data to the correction circuit and to provide correction data to the page buffer, and a copy circuit configured to copy the source data to the page buffer, and to store the correction data in the other page from the page buffer. | 09-20-2012 |
20120239867 | Flash Sector Seeding to Reduce Program Times - A non-volatile flash memory comprises a plurality of non-volatile memories where a first non-volatile memory is pre-programmed (erased) with all ones, and at least a second non-volatile memory is pre-programmed with a seed value that takes advantage of the reduced programming time for less than six zeros. When writing (programming) a data byte, the memory system looks up the data byte in one or more seed tables to determine a portion of non-volatile memory to which the memory system may write the data byte with a reduced programming time. The memory system then records the location,of the data byte in an address translation table so the data byte may be accessed. | 09-20-2012 |
20120239868 | Flash Memory Device and Control Method - The present invention is directed to a method for increasing the operational lifetime of a flash memory device, wherein, the method comprises varying the operating parameters of the flash memory device over the lifetime of the flash memory device. The advantage of providing a method which varies the operating parameters of a flash memory device is that the operational lifetime of the flash memory device will be increased. Relatively low voltages and relatively short voltage periods may be used initially to write to, read from and erase the flash cells in the flash memory device. As time passes, the flash cells in the flash memory device will begin to degrade and it will be necessary to increase the voltage and the period of the voltage applied to the flash memory device in order to ensure that the correct write, read and/or erase commands are carried out. The invention is also directed towards a flash memory device. | 09-20-2012 |
20120239869 | RANDOM WRITE OPTIMIZATION TECHNIQUES FOR FLASH DISKS - Disclosed is a method for managing logical block write requests for a flash drive. The method includes receiving a logical block write request from a file system; assigning a category to the logical block; and generating at least three writes from the logical block write request, a first write writes the logical block to an Erasure Unit (EU) according to the category assigned to each logical block, a second write inserts a Block Mapping Table (BMT) update entry to a BMT update log, and a third write commits the BMT update entry to an on-disk BMT, wherein the first and second writes are performed synchronously and the third write is performed asynchronously and in a batched fashion. | 09-20-2012 |
20120246384 | FLASH MEMORY AND FLASH MEMORY ACCESSING METHOD - A flash memory accessing method is provided. The method includes: firstly, dividing the flash memory into a primary storage area and a backup storage area, wherein the difference between a first start address of the primary storage area and a second start address of the backup storage area is an offset address not equal to zero; reading the flash memory according to a address pointer equal to the first start address so as to obtain the boot data; making the electronic apparatus perform a boot sequence according to the boot data; then, detecting whether the boot sequence is normal or not, and when the boot sequence is abnormal, providing the flash memory with changing the read pointer to the second start address according to an offset address to read the backup boot data. | 09-27-2012 |
20120246385 | EMULATING SPI OR 12C PROM/EPROM/EEPROM USING FLASH MEMORY OF MICROCONTROLLER - In one aspect, a microcontroller is disclosed. In one embodiment, the microcontroller includes a system memory that has an erasable memory of a first type, with a first storage partition and a second, different storage partition. The system memory also has a random access memory (RAM). The microcontroller further includes a network interface that is configured to communicate management commands over a communications link, and a programmable processor that is operatively connected to the system memory and the network interface. The communications link includes an interface bus and is configured for one or more of I2C, SPI, and system management bus communications. The programmable processor is programmed to perform functions that include receiving a first management command configured for the erasable memory of the first type, causing the second storage partition of the erasable memory of the first type to emulate a second type of erasable memory, and receiving a second management command configured for the second type of erasable memory. | 09-27-2012 |
20120246386 | STORAGE SYSTEM AND STORAGE AREA ALLOCATION METHOD - If a monitor measurement cycle is set as a long cycle, promotion in a short cycle cannot be performed; and even if the number of I/Os is very large in response to fluctuations of the number of I/Os in several minutes to several hours of normal work, pages will be promoted after waiting for several weeks. As a result, I/Os which could have normally accepted by an upper tier will be accepted by a lower tier, which results in a problem of worsening the performance efficiency. A monitoring system capable of preventing demotion due to temporary reduction of the number of I/Os for specific pages from a viewpoint of a long cycle and enabling prompt promotion in response to an increase of the number of U/Os for 3 | 09-27-2012 |
20120246387 | SEMICONDUCTOR MEMORY DEVICE AND CONTROLLING METHOD - According to an embodiment, a semiconductor memory device includes a nonvolatile memory; an input/output control unit to control input/output of data to/from the nonvolatile memory; an address translation table that associates first address information specifying a logical recording position of user data stored in the nonvolatile memory with second address information indicating a physical recording position in the nonvolatile memory; a translating unit to translate the first address information to the second address information according to the table; and a generating unit to generate redundant data for checking whether there is error in the user data and the first address information used as one data piece. The input/output control unit records, as data set, the user data, the first address information, and the redundant data, which are used as one data set, in the physical recording position in the nonvolatile memory indicated by the second address information. | 09-27-2012 |
20120246388 | MEMORY SYSTEM, NONVOLATILE STORAGE DEVICE, CONTROL METHOD, AND MEDIUM - According to one embodiment, a memory system includes a nonvolatile storage device and an information processing apparatus. The information processing apparatus includes a first control circuit configured to send a delete notification to the nonvolatile storage device to invalidate data in a first logical address area when read data corresponding to the first logical address area is the same as data expressed by a first function. The nonvolatile storage device include a nonvolatile storage medium, a management table configured to associate a logical address corresponding to valid data for the nonvolatile storage device with a physical address, and a second control circuit configured to update the management table to invalidate a logical address designated by the delete notification, and to send the data expressed by the first function to the information processing apparatus when a logical address included in a read instruction received from the information processing apparatus is invalid. | 09-27-2012 |
20120246389 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM - According to one embodiment, a nonvolatile semiconductor memory device includes a nonvolatile memory, and a controller having a first mode to perform data transfer in response to one of a rising edge and falling edge of a first control signal and a second mode to perform data transfer in response to both of a rising edge and falling edge of a second control signal. The controller switches the first and second modes in data input and data output. | 09-27-2012 |
20120246390 | INFORMATION PROCESSING APPARATUS, PROGRAM PRODUCT, AND DATA WRITING METHOD - According to one embodiment, an information processing apparatus includes an auxiliary storage unit, a non-volatile main storage unit, a secondary cell, a first writing unit, and a second writing unit. The non-volatile main storage unit includes a cache area to temporarily store therein data that is to be stored in the auxiliary storage unit. The first writing unit writes the data into the cache area. The second writing unit writes the data written in the cache area into the auxiliary storage unit when an amount of power in the secondary cell is greater than a predetermined first threshold. | 09-27-2012 |
20120246391 | BLOCK MANAGEMENT SCHEMES IN HYBRID SLC/MLC MEMORY - A method for data storage includes storing data in a memory including multiple analog memory cells arranged in blocks. A first subset of the blocks is defined for storing first data with a first storage density, and a second subset of the blocks is defined for storing second data with a second storage density, larger than the first storage density. In each of the first and second subsets, one or more blocks are allocated to serve as spare blocks and blocks that become faulty are replaced with the spare blocks. Upon detecting that a number of the spare blocks in the second subset has decreased below a predefined threshold, the data is copied from at least one block in the second subset to the first subset, and the at least one block is added to the spare blocks of the second subset. | 09-27-2012 |
20120246392 | STORAGE DEVICE WITH BUFFER MEMORY INCLUDING NON-VOLATILE RAM AND VOLATILE RAM - A storage device includes a flash memory, a buffer memory and a memory controller. The buffer memory is configured to temporarily store write data to be written in the flash memory, the buffer memory including volatile RAM and non-volatile RAM. The memory controller is configured to select one of the volatile RAM and the non-volatile RAM to temporally store the write data based on a write pattern of the write data, and to transmit a host command complete signal to a host when the write data is stored in the non-volatile RAM. | 09-27-2012 |
20120246393 | MEMORY SYSTEM AND CONTROL METHOD OF THE MEMORY SYSTEM - A memory system of a embodiments includes a first storing area having physical blocks and a second storing area recording a logical to physical translation table and an erasure count table keeping data erasure count in physical blocks. The memory system of the embodiments includes a controller which, when a logical address for deletion is notified, obtains data erasure count of a deletion physical block including a deletion area specified by the physical address corresponding to the logical address, and when a physical block having a small erasure count not more than a predetermined rate of the data erasure count exists in the erasure count table, reads out valid data for the memory system in the physical block having a small erasure count onto the second storing area, writes the above data into the deletion area, and invalidates the valid data in the physical block having a small erasure count. | 09-27-2012 |
20120246394 | Flash Memory Device and Data Writing Method for a Flash Memory - A data writing method for a flash memory. First, a plurality of blocks of a flash memory is classified into a plurality of block groups according to the erase counts of the blocks. A logical address range of a host is then divided into a plurality of logical address sections respectively corresponding to the block groups. Write data is then received from the host. A target logical address section to which the logical address of the write data belongs is then determined. A target block group corresponding to the target logical address section is then determined. A target block is then selected from the blocks of the target block group. The write data is then written to the target block. | 09-27-2012 |
20120246395 | MEMORY SYSTEM WITH INTERLEAVED ADDRESSING METHOD - Disclosed is a memory system which includes a nonvolatile memory device including a memory cell array having a plurality of word lines including a first set of word lines storing first data having a high bit error rate, and a second set of word lines storing second data having low bit error rate less than the high bit error rate, and a memory controller that during a program operation maps logical addresses for a portion of the first data and a portion of the second data onto a selected word line selected from the plurality of word lines. | 09-27-2012 |
20120246396 | NON-VOLATILE MEMORY DEVICE HAVING ASSIGNABLE NETWORK IDENTIFICATION - Memory devices and methods disclosed such as a memory device having a plurality of memory dies where each die includes a network identification that uniquely identifies the memory die on a bus. Access for each memory die to the bus can be scheduled by a bus controller. | 09-27-2012 |
20120246397 | STORAGE DEVICE MANAGEMENT DEVICE AND METHOD FOR MANAGING STORAGE DEVICE - According to one embodiment, a storage device management device is connected to a random access memory and a first storage device. When the random access memory includes a free region sufficient to store write data, the write data is stored onto the random access memory. Data on the random access memory selected in the descending order of elapsed time from the last access is sequentially copied onto the first storage device, and a region in the random access memory which has stored the copied data is released. When stored on the random access memory, the read data is read from the random access memory to the processor. When stored on the first storage device, the read data is copied onto the random access memory and read from the random access memory to the processor. | 09-27-2012 |
20120246398 | DISK ARRAY DEVICE AND ITS CONTROL METHOD - To shorten the time from power restoration to the resumption of business operation. During a power failure, a memory controller saves configuration information and directory information of a shared memory to a nonvolatile memory, and saves data of a cache memory to the nonvolatile memory. During power restoration from a power failure, the memory controller returns information of the nonvolatile memory to the shared memory so that it can be updated before the lapse of the initialization time, the micro processor executes online processing based on information of the shared memory, and the memory controller 70 controls the storage area of the cache memory so that it will become gradually writable according to the battery capacity of the battery if the battery capacity of the battery is still gradually increasing even after the lapse of the initialization time. | 09-27-2012 |
20120246399 | Storage Device and Memory Controller - Disclosed is a storage device using non-volatile semiconductor memory that achieves high performance and long life for the device. When managing the non-volatile semiconductor memory ( | 09-27-2012 |
20120254500 | SYSTEM ARCHITECTURE BASED ON DDR MEMORY - Embodiments of the present invention provide an SSD system architecture based on DDR memory. Specifically, embodiments of this invention provide a set of SSD RAID controllers coupled to a system control board. Coupled to each SSD RAID controller is a set of memory control units, each of the set of memory control units include an SSD controller and a set of DRAM memory units. | 10-04-2012 |
20120254501 | SYSTEM ARCHITECTURE BASED ON FLASH MEMORY - Embodiments of the present invention provide a semiconductor storage device (SSD) system architecture based on flash memory. Specifically, embodiments of this invention provide a set of SSD RAID controllers coupled to a system control board. A set of flash memory control units coupled to each of the set of SSD RAID controllers, each of the set of flash memory control units comprising an SSD controller and a set of flash memory units. | 10-04-2012 |
20120254502 | ADAPTIVE CACHE FOR A SEMICONDUCTOR STORAGE DEVICE-BASED SYSTEM - Embodiments of the present invention provide an adaptive cache system and an adaptive cache system for a hybrid storage system. Specifically, in a typical embodiment, an input/out (I/O) traffic analysis component is provided for monitoring data traffic and providing a traffic analysis based thereon. An adaptive cache algorithm component is coupled to the I/O traffic analysis component for applying a set of algorithms to determine a storage schema for handling the data traffic. Further, an adaptive cache policy component is coupled to the adaptive cache algorithm component. The adaptive cache policy component applies a set of caching policies and makes storage determinations based on the traffic analysis and the storage schema. Based on the storage determinations, data traffic can be stored (e.g., cached) among a set of storage devices coupled to the adaptive cache policy component. Such storage components can include one or more of the following: a low-high cache, a low-mid-high cache, a low speed storage component, a middle speed storage component and/or a high speed storage component. | 10-04-2012 |
20120254503 | POWER-SAFE DATA MANAGEMENT SYSTEM - Embodiments of the invention include systems and methods for recovering the system status and maintaining drive coherency after an unexpected power loss. In particular, these systems and methods reduce overhead for maintaining drive coherency by providing for pre-allocation of groups of write addresses and recording the pre-allocated groups of addresses to the non-volatile memory. Write processes can write to the pre-allocated group of addresses while the next group of addresses are pre-allocated and recorded to non-volatile memory. | 10-04-2012 |
20120254504 | FLASH MEMORY DEVICE COMPRISING HOST INTERFACE FOR PROCESSING A MULTI-COMMAND DESCRIPTOR BLOCK IN ORDER TO EXPLOIT CONCURRENCY - A flash memory device is disclosed comprising a flash controller for accessing a first flash memory over a first channel and a second flash memory over a second channel. A multi-command descriptor block is received from a host, wherein the multi-command descriptor block comprises identifiers for identifying a plurality of access commands that the host is preparing to request. A first group of the access commands are selected to execute concurrently and a second group of the access commands are selected to execute concurrently. The first group of access commands are received from the host and executed concurrently by accessing at least the first and second flash memories concurrently. The second group of access commands are received from the host and executed concurrently by accessing at least the first and second flash memories concurrently. | 10-04-2012 |
20120254505 | SYSTEM AND METHOD FOR MANAGING FLASH MEMORY - A system and method for flash memory management is provided. In particular, the system and methods herein provide for management of flash memory, particularly NAND flash memory, in a manner that potentially reduces the number of write/erase cycles typically experienced by a data storage device. When unsecure data records are to be written to the flash memory, the new or updated unsecure data records are stored in the first available location in the flash memory (e.g. a block) providing a best fit for the data records. Where the data records are updates, the updated version is stored with an incremented version number to indicate that the updated version is the current version. Older versions of the data records are deleted during garbage collection. When secure data records are to be written to the flash memory, new or updated secure data records are stored in the location in the flash memory with the most available space. Any older versions of secure data records are immediately deleted. | 10-04-2012 |
20120254506 | SYSTEM AND METHOD FOR PERFORMING SYSTEM MEMORY SAVE IN TIERED/CACHED STORAGE - In accordance with the present disclosure, a system and method for performing a system memory save in tiered or cached storage during transition to a decreased power state is disclosed. As disclosed herein, the system incorporating aspects of the present invention may include a flash or other nonvolatile memory such as a solid-state drive, volatile memory, and at least one alternate storage media. Upon transition to a decreased power state, at least some of the data in the solid-state drive, for example, may be transferred to the at least one alternate storage media. After the SSD data is transferred, data stored in volatile system memory, such as a system context, may be transferred to the SSD memory. With the system context saved in SSD memory, power to the volatile system memory may be turned off. | 10-04-2012 |
20120254507 | WRITE-ABSORBING BUFFER FOR NON-VOLATILE MEMORY - A write-absorbing, volatile memory buffer for use with a processor module and a non-volatile memory is disclosed. The write-absorbing buffer operates as a dirty cache that can be used to look up both read and write requests, although allocating new blocks only for write requests and not read requests. The blocks are small sized, and a write-only least-recently used cache replacement policy is used to transfer data in the blocks to the non-volatile memory. The write-absorbing buffer can be used to store copy-on-write pages for at least one virtual machine associated with the processor module and reduce write overhead to the non-volatile memory. | 10-04-2012 |
20120254508 | Using the Short Stroked Portion of Hard Disk Drives for a Mirrored Copy of Solid State Drives - Mechanisms for storing data to a storage system comprising a set of one or more solid state storage devices and a set of non-solid state storage devices are provided. A request to write data to the storage system is received and the data is written to the set of one or more solid state storage devices in response to receiving the request. Moreover, a mirror copy of the data is written to the set of non-solid state storage devices in response to receiving the request. Thus, the non-solid state storage devices serve as a mirror backup copy of the data stored to the solid state storage devices. | 10-04-2012 |
20120254509 | Extending Cache for an External Storage System into Individual Servers - Mechanisms are provided for extending cache for an external storage system into individual servers. Certain servers may have cards with cache in the form of dynamic random access memory (DRAM) and non-volatile storage, such as flash memory or solid-state drives (SSDs), which may be viewed as actual extensions of the external storage system. In this way, the storage system is distributed across the storage area network (SAN) into various servers. Several new semantics are used in communication between the cards and the storage system to keep the read caches coherent. | 10-04-2012 |
20120254510 | REFERENCE FREQUENCY SETTING METHOD, MEMORY CONTROLLER, AND FLASH MEMORY STORAGE APPARATUS - A reference frequency setting method of a flash memory storage apparatus is provided. The flash memory storage apparatus includes a flash memory module, a storage unit, and an oscillator circuit without a crystal. The reference frequency setting method includes following steps. Whether a setting code is stored in the flash memory module or the storage unit is determined, wherein the setting code includes information of a reference frequency. If the setting code is stored in the flash memory module, the setting code is read to allow the oscillator circuit to generate the reference frequency according to the setting code. A memory controller and a flash memory storage apparatus using the reference frequency setting method are also provided. | 10-04-2012 |
20120254511 | MEMORY STORAGE DEVICE, MEMORY CONTROLLER, AND DATA WRITING METHOD - A memory storage device, a memory controller, and a data writing method are provided. The memory storage device has a rewritable non-volatile memory chip including a plurality of physical units, and each of the physical units has a plurality of physical pages. The data writing method includes configuring a plurality of logical units to be mapped to a portion of the physical units, and each of the logical unit has a plurality of logical pages. The data writing method also includes receiving a first write data from a host system and writing the first write data into the i | 10-04-2012 |
20120254512 | MEMORY CONFIGURING METHOD, MEMORY CONTROLLER AND MEMORY STORAGE APPARATUS - A memory configuring method for a memory storage apparatus is provided, wherein a rewritable non-volatile memory module of the memory storage apparatus has a plurality of physical blocks. The method includes receiving a plurality of query commands from a host system, identifying a pattern corresponding to the query commands and recognizing a type of an operating system executed on the host system. The method further includes configuring the rewritable non-volatile memory module according to the type of the operating system and announcing a configuration of the memory storage apparatus to the host system. Accordingly, the method can configure the non-volatile memory module according different operating systems, and thereby the memory storage apparatus can successfully receive commands and re-set according to user's demand. | 10-04-2012 |
20120254513 | STORAGE SYSTEM AND DATA CONTROL METHOD THEREFOR - A storage system having multiple flash memory packages including flash memory chips and package controllers for controlling access to the flash memory chips is configured such that the package controller receives from a higher-level apparatus, which sends a write request, frequency prediction information that enables prediction of an update frequency with respect to data, which is to be a write target, and when writing data for which a write request has been issued from the higher-level apparatus, control is executed such that data, which is predicted to have a relatively high update frequency based on the frequency prediction information, is preferentially stored in a physical block with the large remaining number of erases in a flash memory chip of flash memory package of the package controller, or such that data, which is predicted to have a relatively low update frequency based on the frequency prediction information, is preferentially stored in a physical block with the small remaining number of erases in a flash memory chip of the flash memory package of the package controller. | 10-04-2012 |
20120254514 | MEMORY SYSTEM, CONTROLLER, AND METHOD FOR CONTROLLING MEMORY SYSTEM - According to one embodiment, a memory system includes nonvolatile memory and storage unit storing a translation table indicating, by a predetermined management unit, relationships between logical addresses specified by a host and physical addresses in the nonvolatile memory. A memory system of the embodiment includes a controller that when receiving from the host a delete notification indicating a delete area smaller than the management unit specified by a logical address, write a specified data pattern to an area of the nonvolatile memory having a physical address corresponding to the delete area. | 10-04-2012 |
20120254515 | ERASE-SUSPEND SYSTEM AND METHOD - A method for suspending an erase operation performed on a group of memory cells in a flash memory circuit is disclosed. One example method includes providing to the memory circuit a command to erase the group of memory cells via a plurality of erase pulses. After applying an erase pulse, if it is determined that another operation has a priority higher than a predetermined threshold, the method suspends the erase operation, performs the other operation, and then resumes the erase operation. | 10-04-2012 |
20120254516 | CONTROL DEVICE, STORAGE DEVICE, AND READING CONTROL METHOD - A control device includes an administration unit that administrates logical pages of respective logical blocks so that confirmation reading target pages are arranged in a manner to be dispersed in physical pages of first to nth non-volatile memories among a plurality of logical blocks, in a case where logical blocks including physical blocks of the first to nth non-volatile memories are formed, with respect to a storage device in which concurrent reading access can be performed to the first to nth non-volatile memories serving as non-volatile memories in which a physical block is composed of a plurality of physical pages, and a confirmation reading control unit that allows to perform concurrent reading of the confirmation reading target pages of the plurality of logical blocks by parallel access control with respect to the first to nth non-volatile memories, when the confirmation reading target pages are read respectively from the logical blocks. | 10-04-2012 |
20120254517 | PLC DATA LOG MODULE AND METHOD FOR STORING DATA IN THE SAME - Provided is a PLC data log module and method for storing data in the same, wherein, in a case one or more storages among a plurality of outside storages is attached, a log data is stored in the attached outside storage, the log data is stored in the storage and check is made as to whether the log data is normally stored in the attached outside storage. | 10-04-2012 |
20120254518 | MEMORY SYSTEM - A memory system includes: a plurality of word lines; a plurality of bit lines; a plurality of memory cells each having a control gate and a drain end, the control gate being connected to one of the word lines, the drain end being connected to one of the bit lines; a memory cell array including a plurality of blocks, each of the blocks including a plurality of pages, each of the pages being including a plurality of the memory cells; and a storage area configured to hold good block data identifying whether or not each of the blocks is a good block based on the number of fail bits in each page in the good block being less than or equal to a first threshold, wherein the first threshold is smaller than a second threshold used for identifying whether or not each of the blocks is a bad block. | 10-04-2012 |
20120254519 | DATA STORAGE SYSTEM WITH NON-VOLATILE MEMORY AND METHOD OF OPERATION THEREOF - A method of operation of a data storage system includes: identifying a target block; configuring a command setting for maximizing a data retention period of the target block for refreshing the target block; writing a pre-archived memory block to the target block based on the command setting; and updating an archive status for sending to a host device. | 10-04-2012 |
20120254520 | NON-VOLATILE MEMORY DEVICE, A DATA PROCESSING DEVICE USING THE SAME, AND A SWAPPING METHOD USED BY THE DATA PROCESSING AND NON-VOLATILE MEMORY DEVICES - A swapping method performed using a data processing device, which includes a processor including a plurality of cores, the swapping method including searching for an empty page of a swap memory in response to the swap memory being connected to the data processing device, the search being performed by using at least one core of the plurality of cores, selecting a page to be swapped from a main memory of the data processing device, the selection being performed by using the at least one core by accessing a corresponding main memory list among a plurality of main memory lists, and swapping data of the page selected to be swapped to the empty page, the swapping being performed by using the at least one core. | 10-04-2012 |
20120254521 | Backup Memory Administration - Methods, systems, and computer program products for backup memory administration are provided. Embodiments include storing in an active memory device, by a memory backup controller, blocks of computer data received from random access memory; recording in a change log, by the memory backup controller, identifications of each block of computer data that is stored in the active memory device; detecting, by the memory backup controller, a backup trigger event; and responsive to the detecting of the backup trigger event: copying, by the memory backup controller, from the active memory device, to a backup memory device, the blocks of data identified in the change log; and clearing, by the memory backup controller, the change log. | 10-04-2012 |
20120254522 | METHOD FOR GIVING READ COMMANDS AND READING DATA, AND CONTROLLER AND STORAGE SYSTEM USING THE SAME - A method for giving a read command to a flash memory chip to read data to be accessed by a host system is provided. The method includes receiving a host read command; determining whether the received host read command follows a last host read command; if yes, giving a cache read command to read data from the flash memory chip; and if no, giving a general read command and the cache read command to read data from the flash memory chip. Accordingly, the method can effectively reduce time needed for executing the host read commands by using the cache read command to combine the host read commands which access continuous physical addresses and pre-read data stored in a next physical address. | 10-04-2012 |
20120254523 | STORAGE SYSTEM WHICH UTILIZES TWO KINDS OF MEMORY DEVICES AS ITS CACHE MEMORY AND METHOD OF CONTROLLING THE STORAGE SYSTEM - Provide is a storage system including one or more disk drives, and one or more cache memories for temporarily storing data read from the disk drives or data to be written to the disk drives, in which: the cache memories includes volatile first memories and non-volatile second memories; and the storage system receives a data write request, stores the requested data in the volatile first memories, selects one of memory areas of the volatile first memories if a total capacity of free memory areas contained in the volatile first memories is less than a predetermined threshold, write data stored in the selected memory area in the non-volatile second memories, and changes the selected memory area to a free memory area. Accordingly, there can be realized capacity enlarging of the cache memory using a non-volatile memory device while realizing a high speed similar to that of a volatile memory device. | 10-04-2012 |
20120254524 | MEMORY DEVICE AND HOST DEVICE - A controller has a random write mode and a sequential write mode to which it transitions when receiving a start command. The controller in the sequential write mode identifies a data stream partially formed by a data item through a control command or a logical address. It also prepares free unit areas for respective data streams, and writes data items in successive storage areas in a corresponding unit area in an order identical to addresses of the data items. When the controller receives an end command, it performs end processing on a unit area for a corresponding data stream. The controller in the sequential write mode transitions to the random write mode when completing the end processing to all data streams or detects a random write request. | 10-04-2012 |
20120254525 | Methods for eliminating intermediate bussing and bridging requirements between a solid state memory device with PCI controller and a main system bus - A method is provided for enabling electronic representation of a removable or fixed data storage device having a non-volatile memory as an operating system-standard disk directly accessible to a main bus of a computing appliance having a peripheral component interface connector and a motherboard. The method includes the acts (a) providing a peripheral component interface ported to a memory controller on the device, the memory controller for controlling host access to the non-volatile memory, (b) providing disk control registers and or bus control registers including appropriate disk and or bus protocols and commands in the peripheral component interface on the device, and (c) connecting the device to the peripheral component interface connector of the computing appliance. | 10-04-2012 |
20120260020 | NON-VOLATILE SEMICONDUCTOR MEMORY MODULE ENABLING OUT OF ORDER HOST COMMAND CHUNK MEDIA ACCESS - A non-volatile semiconductor memory module is disclosed comprising a memory device and memory controller operably coupled to the memory device, wherein the memory controller is operable to receive a host command, split the host command into one or more chunks comprising a first chunk comprising at least one logical block address (LBA), and check the first chunk against an active chunk coherency list comprising one or more active chunks to determine whether the first chunk is an independent chunk, and ready to be submitted for access to the memory device, or a dependent chunk, and deferred access to the memory device until an associated dependency is cleared. | 10-11-2012 |
20120260021 | DATA DEDUPLICATION - The present disclosure includes devices and methods for data deduplication. One such method includes receiving a write command, transforming data associated with the write command, determining if a transformation value of the data exists in a transformation table, and responsive to a determination that the transformation value does not exist in the transformation table, writing the data associated with the write command to a memory device. | 10-11-2012 |
20120260022 | HANDLING COMMANDS WITHIN A WRITE-ONCE READ-MANY STORAGE DEVICE CONFIGURATION - A storage device with a memory, a controller, and a host interface, and a method of handling commands in a storage device are provided to execute commands in a storage device having a write-once read-many device configuration, transparently to a host device. The memory containing a database having entries each entry for a logical memory address and containing information for converting that logical memory address to a redirected logical memory address that represents a memory location where data associated with that logical memory address actually resides. The controller performs, when the host interface is operatively coupled to a host device, to receive a command specifying a logical memory address and interpret the command based on information extracted from the database. The controller executes the command according to the information, transparently to the host device. | 10-11-2012 |
20120260023 | STORAGE DEVICE, PROTECTION METHOD, AND ELECTRONIC APPARATUS - According to one embodiment, a storage device includes, when power is supplied to a storage unit, counting of an elapsed time is started. If a command is input from a host device, and the elapsed time from input of a previous command to input of a current command is calculated based on time information clocked by the host device and on a counter value counted until the corresponding command is input. Matching of the time information is determined based on a temporal relation between the adding result of adding the calculated elapsed time to the time information included in the previous command and the time information included in the current command. When the mismatching is determined, data in the storage unit is invalidated. | 10-11-2012 |
20120260024 | MEMORY BUFFER WITH ONE OR MORE AUXILIARY INTERFACES - The present memory system includes a memory buffer having an interface arranged to buffer data and/or command bytes being written to or read from the RAM chips residing on a DIMM by a host controller. The memory buffer further includes at least one additional interface arranged to buffer data and/or command bytes between the host controller or RAM chips and one or more external devices coupled to the at least one additional interface. For example, the memory buffer may include a SATA interface and be arranged to convey data between the host controller or RAM chips and FLASH memory devices coupled to the SATA interface. The additional interfaces may include, for example, a SATA interface, an Ethernet interface, an optical interface, and/or a radio interface. | 10-11-2012 |
20120260025 | METHOD FOR CONTROLLING MEMORY SYSTEM, INFORMATION PROCESSING APPARATUS, AND STORAGE MEDIUM - A method, to be executed by an application program according to an embodiment, for controlling a memory system provided with a nonvolatile memory includes: acquiring an unused memory area from an operating system installed in an information processing apparatus provided with the memory system; prohibiting the acquired unused memory area from being used by any application program other than the above application program; acquiring the address of the acquired unused memory area; and notifying the address of the acquired unused memory area to the memory system. In the method according to an embodiment for controlling a memory system, prohibition state put by the prohibiting is preserved until receiving a change instruction. | 10-11-2012 |
20120260026 | MERGING COMMAND SEQUENCES FOR MEMORY OPERATIONS - Systems and processes may include a memory coupled to a memory controller. Command signals for performing memory access operations may be received. Attributes of the command signals, such as type, time lapsed since receipt, and relatedness to other command signals, may be determined. Command signals may be sequenced in a sequence of execution based on the attributes. Command signals may be executed in the sequence of execution. | 10-11-2012 |
20120260027 | DEVICE BOOTUP FROM A NAND-TYPE NON-VOLATILE MEMORY - Systems and methods are provided for using a NAND-type non-volatile memory (“NVM”), such as NAND flash memory, to store NV pre-boot information for a bootloader (e.g., a second state bootloader) or an operating system. The NV pre-boot information can include, for example, environment variables storing the configuration or state of an electronic device. In some embodiments, an electronic device including the NAND-type NVM may allocate a portion of the super blocks in the NAND-type NVM to storing the NV pre-boot information. The electronic device may store a redundant copy of the NV pre-boot information into the allocated portion of each IC die of the NAND-type NVM. | 10-11-2012 |
20120260028 | SEMICONDUCTOR MEMORY SYSTEM HAVING SEMICONDUCTOR MEMORY DEVICES OF VARIOUS TYPES AND A CONTROL METHOD FOR THE SAME - Disclosed are a semiconductor memory system having semiconductor memory devices of various types and a control method for the same. A semiconductor memory system according to an embodiment of the present invention comprises a plurality of semiconductor memory devices; and a memory controller for controlling the read-out of data programs for the plurality of semiconductor memory devices and data from the plurality of semiconductor memory devices, wherein at least two of the plurality of semiconductor memory devices differ from each other in terms of one or more of the following: the number of bits of data programmed in memory cells, the degree of integration, the manufacturer, whether they are synchronized, and whether or not encoded data is stored. | 10-11-2012 |
20120260029 | WEAR LEVELING OF SOLID STATE DISKS BASED ON USAGE INFORMATION OF DATA AND PARITY RECEIVED FROM A RAID CONTROLLER - A controller configures a plurality of solid state disks as a redundant array of independent disks (RAID), wherein the plurality of solid state disks store a plurality of blocks, and wherein storage areas of the plurality of solid state disks corresponding to at least some blocks of the plurality of blocks have different amounts of estimated life expectancies. The controller includes in data structures associated with a block that is to be stored in the storage areas of the plurality of solid state disks an indication that the block includes parity information corresponding to the RAID, wherein parity information comprises information corresponding to an error correction mechanism to protect against a disk failure. The controller sends the data structures to the plurality of solid state disks, wherein the plurality of solid state disks allocate a storage area that is estimated to have a relatively greater life expectancy in comparison to other storage areas to store the block that includes the parity information. | 10-11-2012 |
20120260030 | SEAMLESS APPLICATION ACCESS TO HYBRID MAIN MEMORY - A command from an application is received to access a data structure associated with one or more virtual addresses mapped to main memory. A first subset of the virtual addresses for the data structure having constituent addresses that are mapped to the symmetric memory components and a second subset of the virtual addresses for the data structure having constituent addresses that are mapped to the asymmetric memory components are identified. Data associated with the virtual address from the first physical addresses and data associated with the virtual addresses from the second physical addresses are accessed. The data associated with the symmetric and asymmetric memory components is accessed by the application without providing the application with an indication of whether the data is accessed within the symmetric memory component or the asymmetric memory component. | 10-11-2012 |
20120265921 | BOOT DATA STORAGE SCHEMES FOR ELECTRONIC DEVICES - Systems and methods are provided for storing and retrieving boot data (e.g., a first stage bootloader) in and from a non-volatile memory (“NVM”), such as a NAND flash memory. To increase storage reliability, the boot data may be stored in a subset of the pages in a boot data storage area, such as in only lower pages. The subset may be selected based on the specific operating specifications and characteristics of the NVM. To prevent a boot ROM from having to maintain a NVM-specific map of which pages are used to store boot data, the map may be maintained in the NVM itself. For example, the map may be in the form of a linked list, where each page storing boot data can include a pointer that points to the next page that stores boot data. | 10-18-2012 |
20120265922 | STOCHASTIC BLOCK ALLOCATION FOR IMPROVED WEAR LEVELING - Systems and methods are disclosed for stochastic block allocation for improved wear leveling for a system having non-volatile memory (“NVM”). The system can probabilistically allocate a block or super block for wear leveling based on statistics associated with the block or super block. In some embodiments, the system can select a set of blocks or super blocks based on a pre-determined threshold of a number of cycles (e.g., erase cycles and/or write cycles). The block or super block can then be selected from the set of super blocks. In other embodiments, the system can use a fully stochastic approach by selecting a block or super block based on a biased random variable. The biased random variable may be generated based in part on the number of cycles associated with each block or super block of the NVM. | 10-18-2012 |
20120265923 | Program Method, Data Recovery Method, and Flash Memory Using the Same - A program method for a multi-level cell (MLC) flash memory is provided. The memory array includes a plurality of pages and a plurality of paired pages, which correspond to the respective pages. The program method includes the following steps. Firstly, a program address command is obtained. Next, whether the program address command corresponding to any one of the paired pages is determined. When the program address command corresponds to a first paired page, which corresponds to a first page among the pages, among the paired pages, data stored in the first page to a non-volatile memory are copied. After that, the first paired page is programmed. | 10-18-2012 |
20120265924 | ELASTIC DATA TECHNIQUES FOR MANAGING CACHE STORAGE USING RAM AND FLASH-BASED MEMORY - A set of data caching techniques are described which are used to seamlessly store data across both RAM and flash based memory. The techniques utilize a memory manager that includes a RAM journal and a flash journal to efficiently store the data and to make the management of the data across both mediums transparent to the user. The flash based journal works in conjunction with the RAM journal and takes the overflow of data from the RAM journal when certain capacity limits are reached. The resource manager uses journaling techniques to write data to the cache and manages the garbage collection created by the data journaling. | 10-18-2012 |
20120265925 | SEMICONDUCTOR DEVICE AND METHOD OF CONTROLLING NON-VOLATILE MEMORY DEVICE - A control circuit of a semiconductor device (memory module) realizes long life and others by a mechanism that suppresses and smoothes variations in use of a memory by equalizing the sizes of data write and data erase with respect to a data write request and sequentially allocating and using addresses of the memory in data write to an overwritable non-volatile memory device without carrying out an overwriting operation even in the case of an overwrite request. The control circuit realizes data write by a set of two types of operations of (a) an operation of erasing data of a first address or an operation of setting a flag value to an invalid state and (b) an operation of writing data to a second address different from the first address or an operation of setting a flag value to a valid state. | 10-18-2012 |
20120265926 | MANAGING A SOLID-STATE STORAGE DEVICE - A method, comprising: during a normal operating mode of a first solid-state storage device, reserving a portion of an available physical storage space of the first solid-state storage device, giving rise to a reserved portion and a user data portion; setting a user data capacity of the first solid-state storage device according to a size of the user data portion; using substantially the entire available physical storage space for storing user data within the first solid-state storage device; and upon receiving at the first solid-state storage device an instruction to switch to a data protection mode, switching the first solid-state storage device to the data protection mode and allocating part of the reserved portion to the user data portion, giving rise to an extended user data portion, and using the added user data capacity for backing up data that is or was stored on the second solid-state storage device. | 10-18-2012 |
20120265927 | METHOD OF OPERATING MEMORY CONTROLLER, MEMORY CONTROLLER, MEMORY DEVICE AND MEMORY SYSTEM - A method of operating a memory controller, a memory controller, a memory device and a memory system are provided. The method includes reading first data from a nonvolatile memory device using a first read voltage, the first data includes a uncorrectable error bit, reading second data from a nonvolatile memory device using a second read voltage different from the first read voltage, the second data includes an correctable error bit, and reprogramming the nonvolatile memory device according to the comparison result of the first read voltage and the second read voltage. | 10-18-2012 |
20120265928 | NON-VOLATILE MEMORY DEVICES, METHODS OF OPERATING NON-VOLATILE MEMORY DEVICES, AND SYSTEMS INCLUDING THE SAME - Random sequence data is sequentially generated based on a seed assigned to a selected memory space, and one of access-requested segments of the selected memory space is logically combined with the sequentially generated random sequence data to transfer the access-requested segment. The sequentially generating and the logically combining are iteratively performed until remaining access-requested segments all transferred. | 10-18-2012 |
20120265929 | INTEGRATED CIRCUITS TO CONTROL ACCESS TO MULTIPLE LAYERS OF MEMORY IN A SOLID STATE DRIVE - Circuits to control access to memory; for example, third dimension memory are disclosed. An integrated circuit (IC) may be configured to control access to memory cells. For example, the IC may include a memory having memory cells that are vertically disposed in multiple layers of memory. The IC may include a memory access circuit configured to control access to a first subset of the memory cells in response to access control data in a second subset of the memory cells. Each memory cell may include a non-volatile two-terminal memory element that stores data as a plurality of conductivity profiles that can be non-destructively sensed by applying a read voltage across the two terminals of the memory element. New data can be written by applying a write voltage across the two terminals of the memory element. The two-terminal memory elements can be arranged in a two-terminal cross-point array configuration. | 10-18-2012 |
20120271982 | INTELLIGENT FLASH REPROGRAMMING - Apparatus, methods, and computer-readable media for programming, reading, and servicing non-volatile storage device to improve data retention time and data density are disclosed. According to one embodiment, a method of managing a non-volatile memory storage device includes generating output values based on an expected pattern of discrete states stored in memory cells of the storage device, comparing output values for the memory cells to expected output values using a pre-selected threshold, and based on the comparing, programming other memory cells of the storage device to refresh the programming of the other memory cells. Methods of performing service and management operations for interrupting a host system coupled a non-volatile memory storage device are also disclosed. | 10-25-2012 |
20120271983 | COMPUTING DEVICE AND DATA SYNCHRONIZATION METHOD - A server includes a Southbridge chip, a first storage device, and a baseboard management controller (BMC) electrically connected to the Southbridge chip. A field replacement unit (FRU) is electrically connected to the BMC and the first storage device. The BMC reads data from a second storage device electrically connected to the BMC, writes the data into the FRU, sends a first control signal to a switch positioned between the BMC, the first storage device and the FRU, to switch on an electrical connection between the BMC and the first storage device for reading data stored within the first storage device. If the data stored within the first storage is different from the data stored within the FRU, the BMC reads the data from the FRU, and writes the data into the first storage device, to synchronize the data within the first storage device and the FRU. | 10-25-2012 |
20120271984 | MEMORY ELEMENT AND MEMORY DEVICE - An object is to provide a memory element having a novel structure where data can be held even after power supply is stopped. The memory element includes a latch circuit, a first selection circuit, a second selection circuit, a first nonvolatile memory circuit, and a second nonvolatile memory circuit. The first nonvolatile memory circuit and the second nonvolatile memory circuit each include a transistor and a capacitor. The transistor included in each of the first nonvolatile memory circuit and the second nonvolatile memory circuit is a transistor in which a channel is formed in an oxide semiconductor film. The off-state current of such a transistor is extremely small. The transistor is turned off after data is input to a node where the transistor and the capacitor are connected to each other, and data can be held for a long time even after supply of power supply voltage is stopped. | 10-25-2012 |
20120271985 | SEMICONDUCTOR MEMORY SYSTEM SELECTIVELY STORING DATA IN NON-VOLATILE MEMORIES BASED ON DATA CHARACTERSTICS - A semiconductor memory device includes a memory block and memory transmission and reception unit. The memory block includes a first non-volatile memory allocated to a first region having a first address range of physical addresses and a second non-volatile memory allocated to a second region having a second address range different from the first address range, which are mapped to logical addresses of a storing region in a host device. The memory transmission and reception unit performs data input and output operations between the host device and the first non-volatile memory using a first data input and output type, and performs data input and output operations between the host device and the second non-volatile memory using a second data input and output type. The first data input and output type performs the data input and output operations by access units corresponding to the first non-volatile memory. | 10-25-2012 |
20120271986 | Flash Memory Device and Data Protection Method Thereof - A data protection method for a flash memory device. In one embodiment, the flash memory device comprises a flash memory for storing protected data. After the flash memory device is coupled to a host, a plurality of current read addresses of a plurality of read commands sent from the host to the flash memory device are recorded. The current read addresses are then compared with a plurality of predetermined read addresses. When the current read addresses are not identical to the predetermined read addresses, the flash memory device is made to enter a data protection mode. When the flash memory device is in the data protection mode, if the flash memory device receives a plurality of data access commands, the data access commands are processed according to a protection mode setting parameter to prevent the protected data from being accessed by the host. | 10-25-2012 |
20120271987 | Memory Module, Memory System, and Inforamtion Device - A memory system including ROM and RAM in which reading and writing are enabled. A memory system includes a non-volatile memory (FLASH), DRAM, a control circuit, and an information processing device. Data in FLASH is transferred to SRAM or DRAM in advance. Data transfer between the non-volatile memory and the DRAM can be performed in the background. The memory system including these plural chips is configured as a memory system module in which each chip is mutually laminated and each chip is wired via a ball grid array (BGA) and bonding wire between the chips. Data in FLASH can be read at the similar speed to that of DRAM by securing a region in which the data in FLASH can be copied in DRAM and transferring the data to DRAM in advance immediately after power is turned on or by a load instruction. | 10-25-2012 |
20120271988 | METHODS CIRCUITS DATA-STRUCTURES DEVICES AND SYSTEM FOR OPERATING A NON-VOLATILE MEMORY DEVICE - Disclosed are methods, data-structures, circuits, devices and system for operating a non-volatile memory device. According to some embodiments, a controller may operate on different portions (e.g. clusters) of a NVM memory array differently, depending upon a designation of a given portion within a table stored on the array. Portions of the array may be operated in OTP page write mode, while other portions of the array may be operated in either bit level or byte level append modes. | 10-25-2012 |
20120271989 | SYSTEMS AND METHODS OF MEDIA MANAGEMENT, SUCH AS MANAGEMENT OF MEDIA TO AND FROM A MEDIA STORAGE LIBRARY, INCLUDING REMOVABLE MEDIA - A system and method for determining media to be exported out of a media library is described. In some examples, the system determines a media component to be exported, determines the media component is in the media library for a specific process, and exports the media component after the process is completed. | 10-25-2012 |
20120271990 | Non-Volatile Memory Module - Certain embodiments described herein include a memory system which can communicate with a host system such as a disk controller of a computer system. The memory system can include volatile and non-volatile memory and a controller which are configured such that the controller backs up the volatile memory using the non-volatile memory in the event of a trigger condition. In order to power the system in the event of a power failure or reduction, the memory system can include a secondary power source which is not a battery and may include, for example, a capacitor or capacitor array. The memory system can be configured such that the operation of the volatile memory is not adversely affected by the non-volatile memory or the controller when the volatile memory is interacting with the host system. | 10-25-2012 |
20120271991 | RELOCATING DATA IN A MEMORY DEVICE - Methods that can facilitate more optimized relocation of data associated with a memory are presented. In addition to a memory controller component, a memory manager component can be employed to increase available processing resources to facilitate more optimal execution of higher level functions. Higher level functions can be delegated to the memory manager component to allow execution of these higher level operations with reduced or no load on the memory controller component resources. A uni-bus or multi-bus architecture can be employed to further optimize data relocation operations. A first bus can be utilized for data access operations including read, write, erase, refresh, or combinations thereof, among others, while a second bus can be designated for higher level operations including data compaction, error code correction, wear leveling, or combinations thereof, among others. | 10-25-2012 |
20120271992 | STORAGE SYSTEM THAT EXECUTES PERFORMANCE OPTIMIZATION THAT MAINTAINS REDUNDANCY - One storage area is selected from two or more storage areas of a high load physical storage device, a physical storage device with a lower load than that of the physical storage device is selected, and it is judged whether the redundancy according to the RAID level corresponding to the logical volume decreases when the data elements stored in the selected storage area are transferred to the selected low load physical storage device. If the result of this judgment is that the redundancy does not decrease, the data elements stored in the selected storage area are transferred to a buffer area of the selected low load physical storage device and the logical address space of the logical volume that corresponds to the selected storage area is associated with the buffer area. | 10-25-2012 |
20120278526 | SYSTEM ARCHITECTURE BASED ON ASYMMETRIC RAID STORAGE - Embodiments of the present invention provide a semiconductor storage device (SSD) system based on asymmetric RAID storage. Specifically, embodiments of this invention provide a set of (at least one) of RAID controllers coupled to a host computer. A set of storage drives is coupled to each asymmetric RAID controller. The RAID method and configuration of each storage device are dynamically adapted based on user policy parameters and storage performance characteristics. | 11-01-2012 |
20120278527 | SYSTEM ARCHITECTURE BASED ON HYBRID RAID STORAGE - Embodiments of the present invention provide a semiconductor storage device (SSD) system based on hybrid RAID storage. Specifically, embodiments of this invention provide a set of (at least one) RAID controllers coupled to a host computer. A set of storage drives is coupled to each hybrid RAID controller. The RAID method and configuration of each storage device are dynamically adapted based on user policy parameters and storage performance characteristics. | 11-01-2012 |
20120278528 | IIMPLEMENTING STORAGE ADAPTER WITH ENHANCED FLASH BACKED DRAM MANAGEMENT - A method and controller for implementing enhanced flash backed dynamic random access memory (DRAM) management, and a design structure on which the subject controller circuit resides are provided. An input/output adapter (IOA) includes at least one super capacitor, a data store (DS) dynamic random access memory (DRAM), a flash memory, a non-volatile random access memory (NVRAM), and a flash backed DRAM controller. Responsive to an adapter reset, Data Store DRAM testing including restoring a DRAM image from Flash to DRAM and testing of DRAM is performed. Mirroring of RAID configuration data and RAID parity update footprints between the NVRAM and DRAM is performed. Save of DRAM contents to the flash memory is controllably enabled when super capacitors have been sufficiently recharged and the flash memory erased. | 11-01-2012 |
20120278529 | Selective Purge of Confidential Data From a Non-Volatile Memory - Method and apparatus for the non-destructive, selective purging of data from a non-volatile memory. In accordance with various embodiments, multiple copies of a selected set of confidential user data having a common logical address are stored to a confidential data portion of a non-volatile memory so that each copy is in a different location within the confidential data portion. A nondestructive purge of all said copies from the confidential data portion is carried out responsive to an externally supplied selective purge command so that all said copies are erased and other, non-purged confidential user data remain stored in the confidential data portion. | 11-01-2012 |
20120278530 | ENFORCING SYSTEM INTENTIONS DURING MEMORY SCHEDULING - A memory controller receives memory access requests from a host terminal, the memory access requests from the host terminal including one or both of host read requests and host write requests. The memory controller generates memory access requests. Priorities are assigned to the memory access requests. The memory access requests are segregated to memory unit queues of at least one set of memory unit queues, the set of memory unit queues associated with a memory unit. Each memory access request is sent to the memory unit according to a priority and an assigned memory unit queue of the memory access request. | 11-01-2012 |
20120278531 | SYSTEM AND METHOD FOR IMPROVED PARITY DETERMINATION WITHIN A DATA REDUNDANCY SCHEME IN A SOLID STATE MEMORY - Embodiments of the invention are directed to improving parity determination in a data redundancy scheme. In a block oriented storage system, where the storage element block size is an integer multiple of the block size used on the host interface, parity can be calculated on clean boundaries of the host block. However, this is not always the case and storage inefficiency occurs as a result. Embodiments of the invention optimize RAID parity calculation in a non-volatile solid state device by allowing the RAID stripe depth (also termed a “strip”) to be a non-integer multiple of the size of the individual storage element, i.e., the non-volatile memory program granularity. This enables efficient use of storage space where the host data size does not match the storage element size of the non-volatile memory while providing a straightforward way of handling parity generation and data recovery. | 11-01-2012 |
20120278532 | DYNAMICALLY CONFIGURABLE EMBEDDED FLASH MEMORY FOR ELECTRONIC DEVICES - Lifespan of embedded flash memory in an electronic device may be extended and efficient use of the MLC capabilities of the memory may be made by implementing an enhanced partition that stores content that is dynamically adjusted according to the memory usage of the device. The enhanced partition may be used to store data that has a relatively high frequency of updating as measured, for example, by write operations to corresponding memory addresses. In one embodiment, the size of the enhanced partition also may be adjusted in accordance with memory usage, such as basing the size of the enhanced partition on the frequently updated addresses. | 11-01-2012 |
20120278533 | SEMICONDUCTOR STORAGE APPARATUS AND METHOD FOR CONTROLLING SEMICONDUCTOR STORAGE APPARATUS - A reliability maintained period is calculated for each storage area based on the degree of deterioration and read frequency for each storage area of a flash memory, and refresh is executed on each storage area in a planned manner based on the calculated reliability maintained period. | 11-01-2012 |
20120278534 | Flash memory card-based storage devices with changeable capacity - A reconfigurable type of flash memory-based storage device is disclosed. The flash memory-based storage device provides a plurality of mechanisms to accommodate a number of flash memory cards. As the storage capacity of the flash memory cards is increased over the time, so does the flash memory-based storage device by replacing only the flash memory cards. | 11-01-2012 |
20120278535 | DATA WRITING METHOD, MEMORY CONTROLLER, AND MEMORY STORAGE APPARATUS - A data writing method for writing data belonging to a logical page into a rewritable non-volatile memory module is provided. In the data writing method, a mark count value is set for each logical page. Whether the mark count value corresponding to the logical page is greater than a predetermined threshold is determined If the mark count value corresponding to the logical page is not greater than the predetermined threshold, the mark count value corresponding to the logical page is counted, and the data and the mark count value corresponding to the logical page are written into a first storage area or a second storage area. Otherwise, the data and the mark count value corresponding to the logical page are written into the second storage area. Thereby, data stored in the rewritable non-volatile memory module can be effectively identified and data loss caused by power failure can be avoided. | 11-01-2012 |
20120278536 | MEMORY DEVICE CAPABLE OF PREVENTING SPECIFIC DATA FROM BEING ERASED - According to one embodiment, a memory device includes a nonvolatile semiconductor memory, and control section. The nonvolatile semiconductor memory includes a first memory area, and second memory area other than the first memory area. The control section receives a first command from a host, and permits use of the second memory area on the basis of the first command. The control section receives a second command from the host, and transmits a parameter indicating the capacity of the first memory area to the host on the basis of the second command. The control section further receives a third command from the host, and accesses the first memory area on the basis of the third command. When use of the second memory area is permitted, the control section receives the third command from the host, and accesses the second memory area on the basis of the third command. | 11-01-2012 |
20120278537 | METHOD AND APPARATUS FOR I/O SCHEDULING IN DATA STORAGE DEVICE - An input/output (I/O) scheduling device comprises a plurality of trans-descriptor operators each corresponding to one of a plurality of hosts and configured to sustain a trans-descriptor and transmit the trans-descriptor to a hardware module, a transmitting scheduler configured to schedule transmission of trans-descriptors through communication with the plurality of trans-descriptor operators, and a receiving scheduler configured to schedule reception of trans-descriptors through communication with the trans-descriptor operators. | 11-01-2012 |
20120278538 | DATA STORAGE APPARATUS, MEMORY CONTROL DEVICE, AND METHOD FOR CONTROLLING FLASH MEMORIES - According to one embodiment, a data storage apparatus includes a memory module and a controller. The memory module has a plurality of flash memory chips. Data is written to or read from each flash memory chip having a specific page size as access unit. The controller is configured to supply memory control signals, which are independent of the common signal containing the data and addresses, to the flash memory chips, respectively, in order to write data larger than the specific data size to the memory module. In the memory module, the respective flash memory chips store the data, each at the same address, in response to the memory control signals. | 11-01-2012 |
20120278539 | MEMORY APPARATUS, MEMORY CONTROL APPARATUS, AND MEMORY CONTROL METHOD - A memory apparatus includes: a plurality of flash memory sections connected to a common data line; and a control section configured to perform control for data read/write on the plurality of flash memory sections, wherein the control section performs control so as to give a read instruction to a first flash memory section among the plurality of flash memory sections to output read data from the first flash memory section onto the common data line, and to give a write instruction to a second flash memory section other than the first flash memory section to write the read data obtained on the common data line into the second flash memory section with timing in accordance with timing of outputting the read data from the first flash memory section. | 11-01-2012 |
20120278540 | METHOD FOR PERFORMING HOST-DIRECTED OPERATIONS, AND ASSOCIATED MEMORY DEVICE AND CONTROLLER THEREOF - A method for performing host-directed operations is provided, where the method is applied to a controller of a Flash memory that includes a plurality of blocks. The method includes: in a test mode of the controller, when receiving a host command from a host device, extracting at least one portion of associated information of the host command, where the at least one portion of the associated information is an encoded result that is generated by performing encoding on a host-directed operation command; and analyzing the at least one portion of the associated information according to at least one predetermined rule, in order to perform a host-directed operation corresponding to the host-directed operation command. An associated memory device and a controller thereof are also provided. | 11-01-2012 |
20120278541 | MEMORY SYSTEM WITH IMPROVED COMMAND RECEPTION - According to one embodiment, a memory system includes a nonvolatile memory, a buffer, an interface unit, and a buffer control unit including a counter. The nonvolatile memory stores data. The buffer temporarily holds at least one data to be written in the nonvolatile memory. The interface unit receives a request from a host device. The counter is incremented every time a flush request is received to write, in the nonvolatile memory at once, the at least one data held in the buffer. The buffer control unit transfers the at least one data held in the buffer to the nonvolatile memory based on the count value of the counter. The interface unit can receive the next request when the buffer control unit has received the flush request. | 11-01-2012 |
20120278542 | COMPUTER SYSTEM AND SLEEP CONTROL METHOD THEREOF - A computer system and a sleep control method thereof are provided. The method includes following steps: when a computer system enters a sleep mode, storing a system parameter into a dynamic random access memory (DRAM) via a central processing unit (CPU); storing the system parameter in the DRAM to a flash memory via a bridge unit; and entering the sleep mode or a power off mode. According to the disclosure, to wake up the computer system is more rapidly and power saving. | 11-01-2012 |
20120278543 | Flash-Memory Device with RAID-type Controller - A smart flash drive has one or more levels of smart storage switches and a lower level of single-chip flash devices (SCFD's). A SCFD contains flash memory and controllers that perform low-level bad-block mapping and wear-leveling and logical-to-physical block mapping. The SCFD report their capacity, arrangement, and maximum wear-level count (WLC) and bad block number (BBN) to the upstream smart storage switch, which stores this information in a structure register. The smart storage switch selects the SCFD with the maximum BBN as the target and the SCFD with the lowest maximum WLC as the source of a swap for wear leveling when a WLC exceeds a threshold that rises over time. A top-level smart storage switch receives consolidated capacity, arrangement, WLC, and BBN information from lower-level smart storage switch. Data is striped and optionally scrambled by Redundant Array of Individual Disks (RAID) controllers in all levels of smart storage switches. | 11-01-2012 |
20120278544 | FLASH MEMORY CONTROLLER - A Flash memory controller is coupled to a first Flash memory package through a first Flash memory interface and to a second Flash memory package through the first Flash memory interface. The Flash memory controller is designed to receive a first instruction relating to the first Flash memory package and to perform a first process depending on the first instruction. The Flash memory controller is further designed to receive a second instruction relating to the second Flash memory package and to perform a second process depending on the second instruction. The Flash memory controller is further adapted for splitting the first process into at least two first sub-steps and for splitting the second process into at least two second sub-steps. The Flash memory controller is further adapted for executing the first and second sub-steps, and for interleaving execution of first and second sub-steps. | 11-01-2012 |
20120278545 | NON-VOLATILE MEMORY DEVICE WITH NON-EVENLY DISTRIBUTABLE DATA ACCESS - A memory system including a nonvolatile memory, and a memory control module. The nonvolatile memory includes memory cells arranged among physical memory blocks, wherein each physical memory block is of a predetermined size. The memory control module includes a write path module and a read path module. In response to the memory control module receiving data in a first format such that the data is evenly distributable among the physical memory blocks, the write path module modifies the first format of the data into a second format prior to writing the data to the physical memory blocks. The second format of the data is such that the data is no longer evenly distributable among the physical memory blocks. The read path module is configured to read the data from the nonvolatile memory in accordance with the second format. | 11-01-2012 |
20120278546 | Authentication and Securing of Write-Once, Read-Many (WORM) Memory Devices - These embodiments relate to authentication and securing of write-once, read-many (WORM) memory devices. In one embodiment, a memory device comprises a controller operable in first and second modes of operation after stored security information is validated, wherein in the first mode of operation, the memory device operates in a read-only mode, and wherein in the second mode of operation, the memory device operates in a write-once, read-many (WORM) mode. In another embodiment, the controller is operative to perform security methods. | 11-01-2012 |
20120284450 | FLASH MEMORY SYSTEM AND MANAGING AND COLLECTING METHODS FOR FLASH MEMORY WITH INVALID PAGE MESSAGES THEREOF - A flash memory system and managing and collecting methods for flash memory with invalid page messages thereof are described. When the valid data pages of the flash memory are changed to invalid data pages, a recording area is used to record the message of the invalid data pages to effectively collect the occupied space of the invalid data pages in the flash memory. Further, while garbage collecting step is performed, a block is rapidly selected according to the message of the recording area and the valid data pages in the selected block are correctly identified, copied and removed. | 11-08-2012 |
20120284451 | Controller and Terminal Device Used for Multi-Storages and Start-Up and Access Method - A controller used for multi-storages is provided. The multi-storages include a first storage for storing the data of an operating system and at least a second storage for storing the data of user. The first storage and the second storage are formed into a virtual storage supporting the start-up of the operating system by the controller. | 11-08-2012 |
20120284452 | MEMORY SYSTEM, PROGRAM METHOD THEREOF, AND COMPUTING SYSTEM INCLUDING THE SAME - Disclosed is a memory system and a method of programming a multi-bit flash memory device which includes memory cells configured to store multi-bit data, where the method includes and the system is configured for determining whether data to be stored in a selected memory cell is an LSB data; and if data to be stored in a selected memory cell is not an LSB data, backing up lower data stored in the selected memory cell to a backup memory block of the multi-bit flash memory device. | 11-08-2012 |
20120284453 | INFORMATION PROCESSING DEVICE, EXTERNAL STORAGE DEVICE, HOST DEVICE, RELAY DEVICE, CONTROL PROGRAM, AND CONTROL METHOD OF INFORMATION PROCESSING DEVICE - According to the embodiments, an external storage device switches to an interface controller for supporting only a read operation of nonvolatile memory when a shift condition for shifting to a read only mode is met. A host device switches to an interface driver for supporting only the read operation of the nonvolatile memory when determining to recognize as read only memory based on information acquired from the external storage device. | 11-08-2012 |
20120284454 | SOLID STATE STORAGE DEVICE CONTROLLER WITH PARALLEL OPERATION MODE - A master memory controller comprises a plurality of memory communication channels. At least one of the memory communication channels is used to communicate with one or more slave memory controllers. The master and slave memory controllers can operate in a parallel operation mode to communicate with a plurality of memory devices coupled to the memory communication channels of each memory controller. | 11-08-2012 |
20120284455 | Storage Device for Mounting to a Host - A storage device comprising a non-volatile memory for storing data, and an input device that is operative to select an operating mode of the storage device prior to mounting the storage device, such that each operating mode represents a different type of storage device. A controller interfaces with the input device to establish the selected operating mode of the storage device once the storage device is mounted. | 11-08-2012 |
20120290767 | APPARATUS AND METHOD FOR PROVIDING APPLICATION SERVICE USING EXTERNAL MEMORY - An apparatus and a method for providing an application service using an external flash memory is provided. More specifically, the apparatus and method that enables a user to receive provisions of an application service without installing a corresponding application program on an application service providing device (such as an audio-display module) by directly executing a corresponding application program from a USB memory device in which an application program such as a navigation program or an electronic book program is connected therewith to provide an application service to a user. | 11-15-2012 |
20120290768 | SELECTIVE DATA STORAGE IN LSB AND MSB PAGES - A method for data storage includes providing a memory, which includes multiple groups of memory cells and is configured to concurrently store first data using a first storage configuration having a first access time, and second data using a second storage configuration having a second access time, longer than the first access time, such that each memory cell in each of the groups stores at least one bit of the first data and one or more bits of the second data. Data items are accepted for storage in the memory. The accepted data items are classified into a fast-access class and a normal-access class. The data items in the fast-access class are stored in the memory using the first storage configuration, and the data items in the normal-access class are stored in the memory using the second storage configuration. | 11-15-2012 |
20120290769 | FLASH MEMORY DEVICE, MEMORY CONTROL DEVICE, MEMORY CONTROL METHOD, AND STORAGE SYSTEM - A flash memory device includes a flash memory unit; and a control unit configured to perform control so that data having a size smaller than a block size of the flash memory unit is sequentially written to the flash memory unit. | 11-15-2012 |
20120290770 | FLASH MEMORY DEVICE - Different block management values that sequentially increase are set for a plurality of blocks to indicate active states of the blocks. For example, a first block management value “$1111” is stored in a first block, and a second management value “$1112” is stored in a second block. Thus, even when more than one block is in an active state, an updated value is read from the block that stores a larger block management value. This allows for the true updated value to be read. | 11-15-2012 |
20120290771 | FLASH BOOT AND RECOVERY AREA PROTECTION TO MEET GMR REQUIREMENTS - A system and method for protecting boot and recovery area of a flash memory in order to meet GMR requirements in radio system is disclosed. When the Core Engine Modem is installed in the factory test equipment, LOCK signal on the PoP module is logic high. At this time, the flash will be unlocked, and the boot and recovery code is written. The boot and recovery sectors will then be locked and the user area of the flash is left unlocked. When installed in the GLS DICE-T, LOCK signal on the PoP module is logic low. At this time, the flash device will ignore block lock commands, which prevent the unlocking of the protected sectors. The write enable signal from the GVA can now be utilized to enable writing to the user area of the flash despite of protecting boot and recovery areas. | 11-15-2012 |
20120290772 | STORAGE CONTROL APPARATUS FOR CONTROLLING DATA WRITING AND DELETION TO AND FROM SEMICONDUCTOR STORAGE DEVICE, AND CONTROL METHOD AND STORAGE MEDIUM THEREFOR - A storage control apparatus capable of properly deleting data dispersedly stored in a semiconductor storage device with wear leveling. The storage control apparatus converts an address given with a write instruction, among addresses of the semiconductor storage device, into another address, holds address conversion information that associates the before- and after-conversion addresses with each other, and controls the semiconductor storage device to write data into the after-conversion address. When a delete instruction is given, the storage control apparatus controls the semiconductor storage device in accordance with the address conversion information to delete data stored in an after-conversion address associated with an address given with the delete instruction. | 11-15-2012 |
20120290773 | INFORMATION PROCESSING DEVICE COMPRISING A READ-ONLY MEMORY AND A METHOD FOR PATCHING THE READ-ONLY MEMORY - Patching a read-only memory, including a program executable by a processor is performed with a MRAM-based CAM device connected to the address bus and comparing in the background the addresses requested by the processor with the elements of a vector of addresses. The match-in-place operation is done in parallel on all the elements of the vector and typically is performed in less than a clock cycle. If a match is found, the CAM device outputs a diversion address that's used to retrieve a substitution machine code element from a flash memory that is presented to the processor in lieu of the one addressed in the ROM. This patching scheme is totally transparent, has little overhead, and extreme granularity. | 11-15-2012 |
20120290774 | TECHNIQUES TO PERFORM POWER FAIL-SAFE CACHING WITHOUT ATOMIC METADATA - A method and system to allow power fail-safe write-back or write-through caching of data in a persistent storage device into one or more cache lines of a caching device. No metadata associated with any of the cache lines is written atomically into the caching device when the data in the storage device is cached. As such, specialized cache hardware to allow atomic writing of metadata during the caching of data is not required. | 11-15-2012 |
20120290775 | PROGRAMMABLE CONTROLLER SYSTEM AND DEVELOPMENT SYSTEM - To make it possible to perform efficient program development, a development system includes a label managing unit configured to update, when an execution program D | 11-15-2012 |
20120290776 | SECURE MEMORY DEVICES AND METHODS OF MANAGING SECURE MEMORY DEVICES - A computing device and method for managing security of a memory or storage device without the need for administer privileges. To access the secure memory, a host provides a data block containing a control command and authentication data to the memory device. The memory device includes a controller for controlling access to a secure memory in the memory device. The memory device identifies the control command in the data block, authenticates the control command based on the authentication data, and executes the control command to allow the host device to access the secure memory. | 11-15-2012 |
20120290777 | MANAGING SECURITY IN SOLID-STATE DEVICES - A computing device and method for managing security of a memory or storage device without the need for administer privileges. To access the secure memory, a host provides a data block containing a control command and authentication data to the memory device. The memory device includes a controller for controlling access to a secure memory in the memory device. The memory device identifies the control command in the data block, authenticates the control command bused on the authentication data, and executes the control command to allow the host device to access the secure memory. | 11-15-2012 |
20120290778 | INCREASED CAPACITY HETEROGENEOUS STORAGE ELEMENTS - Providing increased capacity in heterogeneous storage elements including a method for storing data in a heterogeneous memory that includes receiving a write message and a write address corresponding to a block of memory cells where at least two of the memory cells support different data levels, determining physical characteristics of the memory cells, and identifying virtual memories associated with the block of memory cells in response to the physical characteristics. The following is performed for each of the virtual memories: generating a constraint vector that describes the virtual cells in the virtual memory; and calculating a virtual write vector in response to the constraint vector and the write data, the calculating including writing the write data, bit by bit, in order, into the virtual memory, skipping locations known to be stuck to a particular value as indicated by the constraint vector. The virtual write vectors are combined into a write word and the write word is output to the block of memory cells. | 11-15-2012 |
20120290779 | DATA MANAGEMENT IN SOLID-STATE STORAGE DEVICES AND TIERED STORAGE SYSTEMS - A method for managing data in a data storage system having a solid-state storage device and alternative storage includes identifying data to be moved in the solid-state storage device for internal management of the solid-state storage; moving at least some of the identified data to the alternative storage instead of the solid-state storage; and maintaining metadata indicating the location of data in the solid-state storage device and the alternative storage. | 11-15-2012 |
20120297111 | Non-Volatile Memory And Method With Improved Data Scrambling - A memory device cooperating with a memory controller scrambles each unit of data using a selected scrambling key before storing it in an array of nonvolatile memory cells. This helps to reduce program disturbs, user read disturbs, and floating gate to floating gate coupling that result from repeated and long term storage of specific data patterns. For a given page of data having a logical address and for storing at a physical address, the key is selected from a finite sequence thereof as a function of both the logical address and the physical address. In a block management scheme the memory array is organized into erase blocks, the physical address is the relative page number in each block. When logical address are grouped into logical groups and manipulated as a group and each group is storable into a sub-block, the physical address is the relative page number in the sub-block. | 11-22-2012 |
20120297112 | DATA STORAGE METHODS AND APPARATUSES FOR REDUCING THE NUMBER OF WRITES TO FLASH-BASED STORAGE - Methods and apparatuses are provided for reducing the number of write operations to a flash-based storage system that stores and replaces data. The storage system includes a first storage implemented using non-flash storage and a second storage implemented using flash memory. Missed data is first stored in the first storage, which can be less sensitive than flash to write operations. The missed data is stored in the flash-based second storage only after the missed data satisfies a storage management algorithm. | 11-22-2012 |
20120297113 | OPTIMIZED FLASH BASED CACHE MEMORY - Embodiments of the invention relate to throttling accesses to a flash memory device. The flash memory device is part of a storage system that includes the flash memory device and a second memory device. The throttling is performed by logic that is external to the flash memory device and includes calculating a throttling factor responsive to an estimated remaining lifespan of the flash memory device. It is determined whether the throttling factor exceeds a threshold. Data is written to the flash memory device in response to determining that the throttling factor does not exceed the threshold. Data is written to the second memory device in response to determining that the throttling factor exceeds the threshold. | 11-22-2012 |
20120297114 | STORAGE CONTROL APPARATUS AND MANAGMENT METHOD FOR SEMICONDUCTOR-TYPE STORAGE DEVICE - The present invention is provided for maintaining and replacing storage devices systematically in accordance with schedule. A storage control apparatus | 11-22-2012 |
20120297115 | PROGRAM CODE LOADING AND ACCESSING METHOD, MEMORY CONTROLLER, AND MEMORY STORAGE APPARATUS - A method of loading a program code from a rewritable non-volatile memory module is provided, wherein the program code includes data segments and two program code copies corresponding to the program code are stored in the rewritable non-volatile memory module. The method includes loading a first data segment of a first program code copy and determining whether the first data segment contains any uncorrectable error bit. The method still includes, when the first data segment does not contain any uncorrectable error bit, loading a second data segment of the first program code copy. The method further includes, when the first data segment contains an uncorrectable error bit, loading a first data segment of a second program code copy, and then loading a second data segment of the first program code copy or the second program code copy. Thereby, the program code can be successfully loaded. | 11-22-2012 |
20120297116 | SPARSE PROGRAMMING OF ANALOG MEMORY CELLS - A method for data storage in a memory including an array of analog memory cells, includes selecting a group of the memory cells such that each memory cell in the group has one or more neighbor memory cells in the array that are excluded from the group. Data is stored in the group of the memory cells while excluding the neighbor memory cells from programming as long as the data is stored in the group of the memory cells. | 11-22-2012 |
20120297117 | DATA STORAGE DEVICE AND DATA MANAGEMENT METHOD THEREOF - Disclosed is a data managing method of a storage device including a nonvolatile memory device. The data managing method includes detecting an update count of update-requested page data and allocating the update-requested page data to a first memory block or a second memory block based upon the update count, an erase count of the second memory block being different from that of the first memory block. | 11-22-2012 |
20120297118 | FAST TRANSLATION INDICATOR TO REDUCE SECONDARY ADDRESS TABLE CHECKS IN A MEMORY DEVICE - A system and method for reducing the need to check both a secondary address table and a primary address table for logical to physical translation tasks is disclosed. The method may include generating a fast translation indicator, such as a logical group bitmap, indicating whether there is an entry in the secondary address table that contains desired information pertaining to a particular logical address. Upon a host request relating to the particular logical address, the storage device may check the bitmap to determine if retrieval and parsing of the secondary table is necessary. The system may include a storage device having RAM cache storage, flash storage and a controller configured to generate and maintain at least one fast translation indicator to reduce the need to check both secondary and primary address tables during logical to physical address translation operations of the storage device. | 11-22-2012 |
20120297119 | STORAGE SYSTEM AND STORAGE MANAGEMENT METHOD FOR CONTROLLING OFF-LINE MODE AND ON-LINE OF FLASH MEMORY - A method for drying workpieces includes immersing the workpieces in a liquid bath, raising the workpieces with a first holder until a central opening of the workpieces is visible above liquid surface, then using a dry second holder rod inserted through said central opening to continue raising process. Due to this, a drying portion of the workpieces is not held by a wet holding mechanism. | 11-22-2012 |
20120297120 | STACK PROCESSOR USING A FERROELECTRIC RANDOM ACCESS MEMORY (F-RAM) FOR CODE SPACE AND A PORTION OF THE STACK MEMORY SPACE HAVING AN INSTRUCTION SET OPTIMIZED TO MINIMIZE PROCESSOR STACK ACCESSES - A stack processor and method implemented using a ferroelectric random access memory (F-RAM) for code and a portion of the stack memory space having an instruction set optimized to minimize processor stack accesses and thus minimize program execution time. This is particularly advantageous in low power applications and those in which the power supply is only available for a finite period of time such as RFID implementations. Disclosed herein is a relatively small but complete set of instructions enabling a multitude of possible applications to be supported with a program execution time that is not too long. | 11-22-2012 |
20120297121 | Non-Volatile Memory and Method with Small Logical Groups Distributed Among Active SLC and MLC Memory Partitions - A non-volatile memory organized into flash erasable blocks receives data from host writes by first staging into logical groups before writing into the blocks. Each logical group contains data from a predefined set of order logical addresses and has a fixed size smaller than a block. The totality of logical groups are obtained by partitioning a logical address space of the host into non-overlapping sub-ranges of ordered logical addresses, each logical group having a predetermined size within a range delimited by a minimum size of at least one page and a maximum size of fitting at least two logical groups in a block and up to an order of magnitude higher than a typical size of a host write. In this way, excessive garbage collection due to operating a large logical group is avoided while the address space is reduced to minimize the size of a caching RAM. | 11-22-2012 |
20120297122 | Non-Volatile Memory and Method Having Block Management with Hot/Cold Data Sorting - A non-volatile memory organized into flash erasable blocks sorts units of data according to a temperature assigned to each unit of data, where a higher temperature indicates a higher probability that the unit of data will suffer subsequent rewrites due to garbage collection operations. The units of data either come from a host write or from a relocation operation. The data are sorted either for storing into different storage portions, such as SLC and MLC, or into different operating streams, depending on their temperatures. This allows data of similar temperature to be dealt with in a manner appropriate for its temperature in order to minimize rewrites. Examples of a unit of data include a logical group and a block. | 11-22-2012 |
20120297123 | WEAR LEVELING - A method for operating a computer memory. The memory is organized to store data in units of such memory. For each unit of a set of units a wear level of the unit is determined. A maximum wear level among the wear levels is determined. A suggestion of a subset of one or more units for being selected for data erasure is received and at least one unit in the subset is identified for subsequent data erasure, a wear level (c(i)) of which units (i) is less than the maximum wear level (c_max). | 11-22-2012 |
20120297124 | FLASH MEMORY DEVICE - In a flash memory device, after an updated value is copied from a first block to a second block, a block management value of the first block is set to an unused state, and maintenance is performed to erase data from the first block. When performing maintenance, the block management value of the first block B1 is rewritten from “$FFF0” to “$FFFF.” When a reset occurs and the power supply is deactivated during the maintenance, the digit of “$0” in the block management value may become “1” to “E” of the hexadecimal system. In this manner, when the block management value includes a single digit of “1” to “E” and three digits of “F,” the reading of an updated value from the block corresponding to the block management value is restricted. | 11-22-2012 |
20120297125 | SOLID-STATE DEVICE WITH LOAD ISOLATION - Systems and methods are provided for coupling multiple flash devices to a shared bus utilizing isolation switches within a SSD device. The SSD device is operable at a speed of about 400 MT/s or higher with high signal integrity. The SSD device includes a controller, a channel in electrical communication with the controller, a plurality of isolation devices in electrical communication with channel, and a plurality of flash memory devices, wherein each flash memory device is in electrical communication with the channel and controller through the one of the isolation devices. | 11-22-2012 |
20120297126 | INFORMATION PROCESSING APPARTUS, NON-TRANSITORY COMPUTER-READABLE MEDIUM STORING CONTROL PROGRAM AND CONTROL METHOD - An information processing apparatus includes a calculator configured to perform a calculation, a plurality of system boards, each of the plurality of system boards including a first storage unit that stores a first program of a first type, the first program being to be used to operate the calculator, a preliminary board including a plurality of second storage units, at least one of the plurality of second storage units storing a second program of a second type, the second program corresponding to the first programs, and a controller configured to compare any one of the first types of the first programs with the second type of the second program and to write, when any one of the first types does not match the second type, the first program of the any one of the first types into the second storage unit. | 11-22-2012 |
20120297127 | OPTIMIZED FLASH BASED CACHE MEMORY - Embodiments of the invention relate to throttling accesses to a flash memory device. The flash memory device is part of a storage system that includes the flash memory device and a second memory device. The throttling is performed by logic that is external to the flash memory device and includes calculating a throttling factor responsive to an estimated remaining lifespan of the flash memory device. It is determined whether the throttling factor exceeds a threshold. Data is written to the flash memory device in response to determining that the throttling factor does not exceed the threshold. Data is written to the second memory device in response to determining that the throttling factor exceeds the threshold. | 11-22-2012 |
20120297128 | REDUCING ACCESS CONTENTION IN FLASH-BASED MEMORY SYSTEMS - Exemplary embodiments include a method for reducing access contention in a flash-based memory system, the method including selecting a chip stripe in a free state, from a memory device having a plurality of channels and a plurality of memory blocks, wherein the chip stripe includes a plurality of pages, setting the ship stripe to a write state, setting a write queue head in each of the plurality of channels, for each of the plurality of channels in the flash stripe, setting a write queue head to a first free page in a chip belonging to the channel from the chip stripe, allocating write requests according to a write allocation scheduler among the channels, generating a page write and in response to the page write, incrementing the write queue head, and setting the chip stripe into an on-line state when it is full. | 11-22-2012 |
20120297129 | MEMORY SYSTEM AND METHOD HAVING VOLATILE AND NON-VOLATILE MEMORY DEVICES AT SAME HIERARCHICAL LEVEL - A processor-based system includes a processor coupled to core logic through a processor bus. This includes a dynamic random access memory (“DRAM”) memory buffer controller. The DRAM memory buffer controller is coupled through a memory bus to a plurality of a dynamic random access memory (“DRAM”) modules and a flash memory module, which are at the same hierarchical level from the processor. Each of the DRAM modules includes a memory buffer to the memory bus and to a plurality of dynamic random access memory devices. The flash memory module includes a flash memory buffer coupled to the memory bus and to at least one flash memory device. The flash memory buffer includes a DRAM-to-flash memory converter operable to convert the DRAM memory requests to flash memory requests, which are then applied to the flash memory device. | 11-22-2012 |
20120303861 | POPULATING STRIDES OF TRACKS TO DEMOTE FROM A FIRST CACHE TO A SECOND CACHE - Provided are a computer program product, system, and method for populating strides of tracks to demote from a first cache to a second cache. A first cache maintains modified and unmodified tracks from a storage system subject to Input/Output (I/O) requests. A determination is made to demote tracks from the first cache. A determination is made as to whether there are enough tracks ready to demote to form a stride, wherein tracks are written to a second cache in strides defined for a Redundant Array of Independent Disk (RAID) configuration. A stride is populated with tracks ready to demote in response to determining that there are enough tracks ready to demote to form the stride. The stride of tracks, to demote from the first cache, are promoted to the second cache. The tracks in the second cache that are modified are destaged to the storage system. | 11-29-2012 |
20120303862 | CACHING DATA IN A STORAGE SYSTEM HAVING MULTIPLE CACHES INCLUDING NON-VOLATILE STORAGE CACHE IN A SEQUENTIAL ACCESS STORAGE DEVICE - Provided are a computer program product, system, and method for caching data in a storage system having multiple caches. A sequential access storage device includes a sequential access storage medium and a non-volatile storage device integrated in the sequential access storage device, received modified tracks are cached in the non-volatile storage device, wherein the non-volatile storage device is a faster access device than the sequential access storage medium. A spatial index indicates the modified tracks in the non-volatile storage device in an ordering based on their physical location in the sequential access storage medium. The modified tracks are destaged from the non-volatile storage device by comparing a current position of a write head to physical locations of the modified tracks on the sequential access storage medium indicated in the spatial index to select a modified track to destage from the non-volatile storage device to the storage device. | 11-29-2012 |
20120303863 | USING AN ATTRIBUTE OF A WRITE REQUEST TO DETERMINE WHERE TO CACHE DATA IN A STORAGE SYSTEM HAVING MULTIPLE CACHES INCLUDING NON-VOLATILE STORAGE CACHE IN A SEQUENTIAL ACCESS STORAGE DEVICE - Provided are a computer program product, system, and method for using an attribute of a write request to determine where to cache data in a storage system having multiple caches including non-volatile storage cache in a sequential access storage device. Received modified tracks are cached in the non-volatile storage device integrated with the sequential access storage device in response to determining to cache the modified tracks. A write request having modified tracks is received. A determination is made as to whether an attribute of the received write request satisfies a condition. The received modified tracks for the write request are cached in the non-volatile storage device in response to determining that the determined attribute does not satisfy the condition. A destage request is added to a request queue for the received write request having the determined attribute not satisfying the condition. | 11-29-2012 |
20120303864 | CACHE MANAGEMENT OF TRACKS IN A FIRST CACHE AND A SECOND CACHE FOR A STORAGE - Provided a computer program product, system, and method for cache management of tracks in a first cache and a second cache for a storage. The first cache maintains modified and unmodified tracks in the storage subject to Input/Output (I/O) requests. Modified and unmodified tracks are demoted from the first cache. The modified and the unmodified tracks demoted from the first cache are promoted to the second cache. The unmodified tracks demoted from the second cache are discarded. The modified tracks in the second cache that are at proximate physical locations on the storage device are grouped and the grouped modified tracks are destaged from the second cache to the storage device. | 11-29-2012 |
20120303865 | Write Operation with Immediate Local Destruction of Old Content in Non-Volatile Memory - Method and apparatus for writing data to a non-volatile memory device, such as a solid state drive (SSD). In accordance with various embodiments, a host write command is serviced by writing a newer copy of user data to a first selected empty physical location in a non-volatile memory, and by concurrently overwriting an older copy of said user data previously stored to a different, second selected occupied physical location of the non-volatile memory. | 11-29-2012 |
20120303866 | Storage device with inline address indirection metadata storage - Methods are described that allow disk drives, such as shingle-written magnetic recording (SMR) drives, to recover an Indirection Address Table mapping of LBAs to PBAs after an emergency power off (EPO). Indirection Address Table (IAT) snapshots are periodically written inline with user data stores, and in one embodiment Cumulative Delta Lists (CDLs) with incremental address update information are stored between snapshots. In an embodiment of the invention, when an imminent loss of power is detected, the current CDL, covering IAT updates not yet written to disk, is saved to a nonvolatile memory. The IAT snapshots combined with the set of CDLs provide the information needed to recreate the current Indirection Address Table when power is restored after an emergency power loss. In an alternative embodiment the CDL is obviated by including metadata in the sector that encodes the address indirection mapping and the last snapshot ID. | 11-29-2012 |
20120303867 | IMPLEMENTING ENHANCED EPO PROTECTION FOR INDIRECTION DATA - A method and a storage system are provided for implementing indirection tables for persistent media or disk drives with enhanced emergency power outage (EPO) protection for the indirection data, such as shingled perpendicular magnetic recording (SMR) indirection tables. Chaining of indirection data is provided with one block pointing to another block of the indirection data stored to disk or flash memory. An EPO-safe buffer is used to store a metadata entry responsive to completing each host write command. Each metadata entry is added to a metadata block, a pointer is stored in the EPO-safe buffer to a current metadata block and a previous metadata block. For a next EPO-safe buffer update entries are removed for the previous metadata block, keeping the last two metadata pointers and last metadata block. | 11-29-2012 |
20120303868 | IDENTIFYING A LOCATION CONTAINING INVALID DATA IN A STORAGE MEDIA - A system includes storage media and control logic coupled to the storage media, where the control logic is configured to receive a write request and determine whether the write request specifies writing a predetermined pattern to a particular location of the storage media. In response to determining that the write request specifies writing the predetermined pattern to the particular location, the control logic is configured to identify with an indicator that the particular location contains invalid data. | 11-29-2012 |
20120303869 | HANDLING HIGH PRIROITY REQUESTS IN A SEQUENTIAL ACCESS STORAGE DEVICE HAVING A NON-VOLATILE STORAGE CACHE - Modified tracks for write requests to a sequential access storage medium in a sequential access storage device are cached in a non-volatile storage, which is a faster access device than the sequential access storage medium. A request queue includes destage requests to destage the modified tracks in the non-volatile storage device to the sequential access storage medium and read requests to access read requested tracks from the sequential access storage medium. A comparison is made of a current position of a read/write mechanism with respect to physical locations on the sequential access storage medium of the tracks subject to the destage requests indicated in the request queue. A determination is made of one of the destage requests to process based on the comparison. The modified track for the determined destage request is written from the non-volatile storage device to the sequential access storage medium. | 11-29-2012 |
20120303870 | MEMORY CHIP, MEMORY SYSTEM, AND METHOD OF ACCESSING THE MEMORY CHIP - A memory chip, a memory system, and a method of accessing the memory chip. The memory chip includes a substrate, a first storage unit, and a second storage unit. The first storage unit includes a plurality of first memory cells may have a first storage capacity of 2 | 11-29-2012 |
20120303871 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME - According to one embodiment, a semiconductor memory device includes a memory cell array including a plurality of memory cells, a first register configured to store data of the memory cells, and a sequence control circuit configured to control the memory cell array and the first register. In at least a data read operation of the memory cells, the sequence control circuit reads out, from the memory cell array, data including flag information representing whether the number of failed bits is in an allowable range. | 11-29-2012 |
20120303872 | CACHE MANAGEMENT OF TRACKS IN A FIRST CACHE AND A SECOND CACHE FOR A STORAGE - Provided a computer program product, system, and method for cache management of tracks in a first cache and a second cache for a storage. The first cache maintains modified and unmodified tracks in the storage subject to Input/Output (I/O) requests. Modified and unmodified tracks are demoted from the first cache. The modified and the unmodified tracks demoted from the first cache are promoted to the second cache. The unmodified tracks demoted from the second cache are discarded. The modified tracks in the second cache that are at proximate physical locations on the storage device are grouped and the grouped modified tracks are destaged from the second cache to the storage device. | 11-29-2012 |
20120303873 | METHOD FOR STORAGE DEVICES TO ACHIEVE LOW WRITE AMPLIFICATION WITH LOW OVER PROVISION - A solid state drive (SSD) includes an SSD control module configured to determine frequencies corresponding to how often data stored in respective logical addresses associated with the SSD is updated and form groups of the logical addresses according to the frequencies, and a memory control module configured to rewrite the data to physical addresses in blocks of an SSD storage region based on the groups. | 11-29-2012 |
20120303874 | INFORMATION PROCESSING UNIT AND INFORMATION PROCESSING METHOD - There are provided an information processing unit and an information processing method which are capable of reducing a startup time. The information processing unit includes: a volatile memory temporarily holding, as memory data, information which indicates a plurality of programs; a nonvolatile memory; and a page information generation section generating page information which identifies memory data for a plurality of predetermined pages from memory data stored in the volatile memory. The page information includes a memory address for each page in the volatile memory, and a program number of a program including memory data for each page. | 11-29-2012 |
20120303875 | POPULATING STRIDES OF TRACKS TO DEMOTE FROM A FIRST CACHE TO A SECOND CACHE - Provided are a computer program product, system, and method for populating strides of tracks to demote from a first cache to a second cache. A first cache maintains modified and unmodified tracks from a storage system subject to Input/Output (I/O) requests. A determination is made to demote tracks from the first cache. A determination is made as to whether there are enough tracks ready to demote to form a stride, wherein tracks are written to a second cache in strides defined for a Redundant Array of Independent Disk (RAID) configuration. A stride is populated with tracks ready to demote in response to determining that there are enough tracks ready to demote to form the stride. The stride of tracks, to demote from the first cache, are promoted to the second cache. The tracks in the second cache that are modified are destaged to the storage system. | 11-29-2012 |
20120303876 | CACHING DATA IN A STORAGE SYSTEM HAVING MULTIPLE CACHES INCLUDING NON-VOLATILE STORAGE CACHE IN A SEQUENTIAL ACCESS STORAGE DEVICE - Provided are a computer program product, system, and method for caching data in a storage system having multiple caches. A sequential access storage device includes a sequential access storage medium and a non-volatile storage device integrated in the sequential access storage device, received modified tracks are cached in the non-volatile storage device, wherein the non-volatile storage device is a faster access device than the sequential access storage medium. A spatial index indicates the modified tracks in the non-volatile storage device in an ordering based on their physical location in the sequential access storage medium. The modified tracks are destaged from the non-volatile storage device by comparing a current position of a write head to physical locations of the modified tracks on the sequential access storage medium indicated in the spatial index to select a modified track to destage from the non-volatile storage device to the storage device. | 11-29-2012 |
20120303877 | USING AN ATTRIBUTE OF A WRITE REQUEST TO DETERMINE WHERE TO CACHE DATA IN A STORAGE SYSTEM HAVING MULTIPLE CACHES INCLUDING NON-VOLATILE STORAGE CACHE IN A SEQUENTIAL ACCESS STORAGE DEVICE - Provided are a computer program product, system, and method for using an attribute of a write request to determine where to cache data in a storage system having multiple caches including non-volatile storage cache in a sequential access storage device. Received modified tracks are cached in the non-volatile storage device integrated with the sequential access storage device in response to determining to cache the modified tracks. A write request having modified tracks is received. A determination is made as to whether an attribute of the received write request satisfies a condition. The received modified tracks for the write request are cached in the non-volatile storage device in response to determining that the determined attribute does not satisfy the condition. A destage request is added to a request queue for the received write request having the determined attribute not satisfying the condition. | 11-29-2012 |
20120303878 | Method and Controller for Identifying a Unit in a Solid State Memory Device for Writing Data to - In a method for identifying a unit in a solid state memory device for writing data to a tier structure is maintained the tier structure comprising at least two tiers for assigning units available for writing data to. In response to receiving a request for writing data it is determined if a unit for writing data to is available in a first tier of the at least two tiers. In response to determining that a unit is available for writing data to in the first tier this unit is identified for writing data to, and in response to determining that no unit is available for writing the data to in the first tier it is determined if a unit is available for writing data to in a second tier of the at least two tiers subject to a priority of the write request. | 11-29-2012 |
20120303879 | Memory Device and Method for Programming Flash Memory Utilizing Spare Blocks - An access method for use in a memory device. The memory device comprises a data area having a plurality of data blocks and a spare area having a plurality of spare blocks. First, data from a host is received. A spare block is popped from the spare area and the received data is programmed into the popped spare block accordingly. A data block corresponding to the data is pushed to the spare area. The pushed data block is erased when the memory device is waiting for a specific instruction to be issued from the host. | 11-29-2012 |
20120303880 | METHOD AND APPARATUS FOR ENCRYPTING AND PROCESSING DATA IN FLASH TRANSLATION LAYER - A method and apparatus for preventing a user from interpreting optional stored data information even when the user extracts the optional stored data, by managing data associated with a flash memory in a flash translation layer, the method comprising searching at least one page of the flash memory when writing data to the flash memory, determining whether authority information corresponding to respective searched pages includes an encryption storage function, generating, corresponding to respective searched pages, a page key according to an encrypting function when the authority information includes the encryption storage function encrypting the data using the generated page key and storing the encrypted data in the respective searched pages, and storing the data in the respective searched pages without encryption when the authority information does not include the encryption storage function. | 11-29-2012 |
20120303881 | Method and Memory Device that Powers-Up in a Read-Only Mode and Is Switchable to a Read/Write Mode - One-time programmable (OTP) and write-once read-many (WORM) memory devices and methods for use therewith are provided. These embodiments can be used to provide compatibility between a memory device that uses an OTP (or few-time programmable (FTP)) memory array and host devices that use a file system, such as the DOS FAT file system, that expects to be able to rewrite to a memory address in the memory device. These embodiments can also be used to prevent accidental or deliberate overwrites, changes, or deletions to existing data in a WORM memory device. | 11-29-2012 |
20120303882 | USB MEMORY DEVICE - A flash memory drive comprising: a male USB connector; a female USB connector; a flash memory chip to store file data; a computing processor, operatively connected to the flash memory chip, to manage tranfers of data to and from the flash memory chip; and a changeover switch, operatively connected to the computing processor, to connect the computing processor to one of the male USB connector and the female USB connector; wherein there is no data communication link between the male USB connector and the female USB connector when the changeover switch is connected to one of the male USB connector and the female USB connector. | 11-29-2012 |
20120311230 | APPARATUS INCLUDING MEMORY SYSTEM CONTROLLERS AND RELATED METHODS - Memory system controllers can include a switch and non-volatile memory control circuitry coupled to the switch. The non-volatile memory control circuitry can include a channel control circuit coupled to logical units. The channel control circuitry can be configured to relay an erase command to a first one of the logical units and relay a particular command from the switch to a second one of the logical units while the erase command is being executed on the first one of the plurality of logical units. | 12-06-2012 |
20120311231 | APPARATUS INCLUDING MEMORY SYSTEM CONTROLLERS AND RELATED METHODS - Memory system controllers can include non-volatile memory control circuitry including a plurality of channel control circuits. Each of the plurality of channel control circuits can be configured to be coupled to a respective number of logical units (LUNs). Memory management circuitry can be coupled to the non-volatile memory control circuitry and configured to allocate a write block cluster for host writes based on an information width of a host bus and a protocol of the host bus. The write block cluster can include one block from fewer than all of the LUNs. | 12-06-2012 |
20120311232 | APPARATUS INCLUDING MEMORY SYSTEM CONTROLLERS AND RELATED METHODS - Memory controllers can include a switch and non-volatile memory control circuitry including channel control circuits coupled to the switch. The channel control circuits can coupled to logical units including blocks. Volatile memory and memory management circuitry including local memory can be coupled to the switch. The memory management circuitry can be configured to store health and status information for each of the blocks in a block table in the volatile memory, store a candidate block table that identifies a candidate block for a particular operation based on criteria in the local memory, update the health and status information for a particular block in the block table, compare the updated health and status information for the particular block with the candidate block according to the criteria, and update the candidate block table to identify the particular block in response to the comparison indicating that the particular block better satisfies the criteria. | 12-06-2012 |
20120311233 | SYSTEM AND METHOD FOR MANAGING A NON-VOLATILE MEMORY - A method, computer readable medium storing instructions and system for managing flash memory. Data sector are received and each is written into a data block of a buffer of a non-volatile memory device. Pointers in a data management structure are created for each data sector corresponding to an associated logical block and a storage location of the data sector in the buffer. When a predefined criterion is fulfilled before the buffer becomes full, a number of logical blocks to be merged is determined and data sectors corresponding to the number of logical blocks to be merged are written from the buffer to a primary non-volatile data storage memory of the non-volatile memory device. | 12-06-2012 |
20120311234 | INFORMATION PROCESSING APPARATUS AND CACHE CONTROL METHOD - According to one embodiment, an information processing apparatus includes a storage device, a volatile memory, and a processor. The storage device includes a controller, a first nonvolatile storage module, and a second nonvolatile storage module whose access speed is higher than an access speed of the first nonvolatile storage module. The processor is configured to execute an operating system and a cache driver that are loaded into the volatile memory. The cache driver uses at least part of an area in the second nonvolatile storage module as a cache for the first nonvolatile storage module. | 12-06-2012 |
20120311235 | MEMORY SYSTEM HAVING MULTIPLE CHANNELS AND METHOD OF GENERATING READ COMMANDS FOR COMPACTION IN MEMORY SYSTEM - According to one embodiment, a valid-cluster search module searches valid clusters included in first blocks, in each of channels, for compaction. A read command generator generates read commands used to read, in parallel, valid clusters to be migrated to a second block. The valid clusters searched in each of the channels comprise the valid clusters to be migrated. The valid clusters to be migrated correspond to a number of clusters simultaneously written to the second block and to a second number of channels in a first number of channels. A determination module determines the second number of channels corresponding to read commands to be generated next based on a situation of issuance of the read commands. | 12-06-2012 |
20120311236 | MEMORY SYSTEM, DATA CONTROL METHOD, AND DATA CONTROLLER - According to one embodiment, a memory system includes: a non-volatile memory; a storage configured to store therein data temporarily; a notifying module configured to notify a host of data transfer permission with a specified amount of data to be written in the storage; a transfer module configured to transfer data transferred from the host according to the data transfer permission to the storage, and to transfer the data stored in the storage to be written to the non-volatile memory; and a controller configured to inhibit notification of the data transfer permission by the notifying module until transfer of the data to the non-volatile memory by the transfer module is completed after an amount of data necessary to be written in the non-volatile memory is stored in the storage. | 12-06-2012 |
20120311237 | STORAGE DEVICE, STORAGE SYSTEM AND METHOD OF VIRTUALIZING A STORAGE DEVICE - A storage device includes a storage media including a one or more nonvolatile memories and a controller. The controller controls the nonvolatile memories, provides a virtual storage to an external host via at least one of the nonvolatile memories and erases a memory block of corresponding nonvolatile memory including data at physical addresses corresponding to data in the virtual storage. | 12-06-2012 |
20120311238 | MEMORY APPARATUS - A memory apparatus is provided. The memory apparatus includes a first memory chip, a second memory chip and a control unit configured to manage a first mapping table for the first memory chip and a second mapping table for the second memory chip. If a first physical address of the second memory chip is allocated to a first logical address of the first memory chip, the control unit is configured to update a second logical address of the second memory chip to correspond to the first physical address of the second memory chip in the second mapping table and update the first logical address of the first memory chip to correspond to the second logical address of the second memory chip in the first mapping table. | 12-06-2012 |
20120311239 | DATA INTERLEAVING SCHEME FOR AN EXTERNAL MEMORY OF A SECURE MICROCONTROLLER - The invention relates to methods of interleaving payload data and integrity control data in an external memory interfaced with a microcontroller to improve data integrity check, enhance data confidentiality and save internal memory. Data words and are received for storing in the external memory. Each data word is used to generate a respective integrity word, while an associated logic address is translated to two physical addresses in the external memory, one for the data word and the other for the integrity word. The two physical addresses for the data and integrity words are interleaved in the external memory, and sometimes, in a periodic scheme. In particular, each data word may be associated to an integrity sub-word included in an integrity word having the same length with that of a data word. The external memory may have dedicated regions for the data words and the integrity words, respectively. | 12-06-2012 |
20120311240 | INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, AND STORAGE MEDIUM - The hibernation start-up by the kernel function takes a long time due to a processing time required for a normal boot sequence. When starting an operating system, the information processing apparatus according to the present invention determines whether to perform the hibernation start-up processing before initialization of a memory management mechanism. When the hibernation start-up processing is performed, a size of the memory management mechanism is reduced to a minimum size necessary for initializing the kernel and a hibernation image is read in parallel with initialization of hardware. The limited memory management area can be restored to a state free from a limitation by reading the hibernation image. | 12-06-2012 |
20120311241 | SCHEDULER FOR MEMORY - A scheduler controls execution in a memory of operation requests received in an input request set (IRS) by providing a corresponding output request set (ORS). The scheduler includes zone standby units having a one-to-one relationship with corresponding zones such that each zone standby unit stores an operation request. The scheduler also includes an output processing unit that determines a processing sequence for the operation requests stored in the zone standby units to provide the ORS. | 12-06-2012 |
20120311242 | DATA PROCESSING SYSTEM - A data processing system is provided, which can realize speeding up and facilitation of data processing using a program and a parameter of a scale larger than the maximum storage capacity of an available on-chip nonvolatile memory. A program and a parameter of a scale larger than the maximum storage capacity of the on-chip nonvolatile memory are stored in a nonvolatile semiconductor memory device coupled to the exterior of a semiconductor data processing device, and responding to the determination result of the information supplied from the exterior, the semiconductor data processing device downloads an internally required program and parameter from the nonvolatile semiconductor memory device, and rewrites the on-chip nonvolatile memory. When the program is rewritten, software reset processing is performed to execute the program from a starting address. | 12-06-2012 |
20120311243 | METHOD FOR INCREASING RELIABILITY OF DATA ACCESSING FOR A MULTI-LEVEL CELL TYPE NON-VOLATILE MEMORY - The primary object of the present invention is to provide a data accessing method for a multi level cell type non-volatile memory, including a plurality of storage cells, each storage cell has 0 | 12-06-2012 |
20120311244 | Balanced Performance for On-Chip Folding of Non-Volatile Memories - A non-volatile memory system receives and stores host data. As the memory system receives host data, it initially writes the data in a binary format and then subsequently performs an on-chip folding operation on the data, storing the data in a multi-state format. The memory system interleaves the phases of the folding operations so that performance is made more uniform across allocation units, where the host stores data according to allocation units. The memory system also can perform the binary and subsequent on-chip folding operations on multiple memory planes in parallel, where the controller also balances the operations so that performance is made more uniform between planes with respect to allocation units as the data is received from the host. To further maintain performance, the memory system uses a free block list having a reserve portion that is only accessible for a specified set of commands. | 12-06-2012 |
20120311245 | SEMICONDUCTOR STORAGE DEVICE WITH VOLATILE AND NONVOLATILE MEMORIES - A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second and third memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data outputted from the first memory area by a first management unit in the second memory area, and a third processing for storing data outputted from the first memory area by a second management unit in the third memory area. | 12-06-2012 |
20120311246 | System Including a Fine-Grained Memory and a Less-Fine-Grained Memory - A data processing system includes one or more nodes, each node including a memory sub-system. The sub-system includes a fine-grained, memory, and a less-fine-grained (e.g., page-based) memory. The fine-grained memory optionally serves as a cache and/or as a write buffer for the page-based memory. Software executing on the system uses a node address space which enables access to the page-based memories of all nodes. Each node optionally provides ACID memory properties for at least a portion of the space. In at least a portion of the space, memory elements are mapped to locations in the page-based memory. In various embodiments, some of the elements are compressed, the compressed elements are packed into pages, the pages are written into available locations in the page-based memory, and a map maintains an association between the some of the elements and the locations. | 12-06-2012 |
20120311247 | DATA READ METHOD FOR A PLURALITY OF HOST READ COMMANDS, AND FLASH MEMORY CONTROLLER AND STORAGE SYSTEM USING THE SAME - A data read method for reading data to be accessed by a host system from a plurality of flash memory modules is provided. The data read method includes receiving command queuing information related to a plurality of host read commands from the host system, each of the host read commands is corresponding to one of a plurality of data input/output buses coupled to the flash memory modules. The data read method also includes re-arranging the host read commands and generating a command giving sequence according to the data input/output buses corresponding to the host read commands. The data read method further includes sequentially receiving and processing the host read commands from the host system according to the command giving sequence and pre-reading data corresponding to a second host read command. Thereby, the time for executing the host read commands can be effectively shortened. | 12-06-2012 |
20120317333 | STORAGE SYSTEM COMPRISING FLASH MEMORY, AND STORAGE CONTROL METHOD - A storage system has a plurality of flash packages, and a storage controller for receiving a write request from a host and sending a write-data write request based on data conforming to this write request to a write-destination flash package. A virtual capacity, which is larger than the physical capacity of the flash package, is defined in the storage controller. The storage system compresses the write data, and writes the compressed write data to the write-destination flash chip. | 12-13-2012 |
20120317334 | SEMICONDUCTOR STORAGE APPARATUS AND METHOD OF CONTROLLING SEMICONDUCTOR STORAGE APPARATUS - A semiconductor storage apparatus including a flash memory which provides a storage area, and a memory controller which controls the reading and writing of data from and to the flash memory, wherein the storage area of the flash memory is configured from a plurality of write areas, and wherein the memory controller divides the data into a size corresponding to the write area, and changes the starting location of writing the data each time the divided data is written into the write area. | 12-13-2012 |
20120317335 | RAID CONTROLLER WITH PROGRAMMABLE INTERFACE FOR A SEMICONDUCTOR STORAGE DEVICE - Provided is a RAID controlled storage device of a serial attached small computer system interface/serial advanced technology attachment (PCI-Express) type, which provides data storage/reading services through a PCI-Express interface. The RAID controller typically includes a hardware (H/W) disk connect coupled to a set of PCI-Express SSD memory disk units, the set of PCI-Express SSD memory disk units comprising a set of volatile semiconductor memories; a programmable disk mount coupled to the H/W disk connect; an adaptive disk mount controller coupled to the programmable disk mount; a disk monitoring unit coupled to the programmable disk mount for monitoring the set of PCI-Express memory disk units; a disk plug and play controller coupled to the disk monitoring unit and the programmable disk mount for controlling the programmable disk mount; a high speed host interface coupled to the disk monitoring unit and the programmable disk mount for providing high-speed host interface capabilities; a disk controller coupled to the high speed host interface and the disk monitoring unit; and a host interface coupled to the disk controller. | 12-13-2012 |
20120317336 | TWO-WAY RAID CONTROLLER FOR A SEMICONDUCTOR STORAGE DEVICE - Provided is a two-way RAID controlled storage device of a serial attached small computer system interface/serial advanced technology attachment (PCI-Express) type, which provides data storage/reading services through a PCI-Express interface. The RAID controller typically includes a plurality of disk mounts coupled disk connect controller, which itself is coupled to a set (e.g., at least one) of PCI-Express SSD memory disk units. In a typical embodiment, the plurality of PCI-Express SSD memory disk units comprising a plurality of volatile semiconductor memories. The RAID controller further comprises a plurality of disk monitoring units coupled to the plurality of disk mounts for monitoring the plurality of PCI-Express memory disk units; a plurality of disk plug and play controllers coupled to the plurality of disk monitoring units. A plurality of high-speed host interfaces are coupled to: the plurality of disk mounts, the plurality of disk monitoring units, and to a plurality of disk controllers. Further coupled to the plurality of disk controllers is a two-way RAID controller, which is also coupled to the disk connect controller and to a host connect controller. The host connect controller is further coupled to a plurality of host interfaces, which themselves are coupled to the plurality of disk controllers. | 12-13-2012 |
20120317337 | MANAGING DATA PLACEMENT ON FLASH-BASED STORAGE BY USE - A storage placement system is described herein that uses an operating system's knowledge related to how data is being used on a computing device to more effectively communicate with and manage flash-based storage devices. Cold data that is not frequently used can be differentiated from hot data clusters and placed in worn areas, while hot data that is frequently used can be kept readily accessible. By clustering hot data together and cold data in separate sections, the system is better able to perform wear leveling and prolong the usefulness of the flash medium. Storage of data in the cloud or other storage can intelligently persist data in a location for a short time before coalescing data to write in a block. Thus, the system leverages the operating system's knowledge of how data has been and will be used to place data on flash-based storage devices in an efficient way. | 12-13-2012 |
20120317338 | Solid-State Disk Caching the Top-K Hard-Disk Blocks Selected as a Function of Access Frequency and a Logarithmic System Time - A solid state disk (SSD) caches disk-based volumes in a heterogeneous storage system, improving the overall storage-system performance. The hottest data blocks are identified based on two factors: the frequency of access, and temporal locality. Temporal locality is computed using a logarithmic system time. IO latency is reduced by migrating these hottest data blocks from hard-disk-based volumes to the solid-state flash-memory disks. Some dedicated mapping metadata and a novel top-K B-tree structure are used to index the blocks. Data blocks are ranked by awarding a higher current value for recent accesses, but also by the frequency of accesses. A non-trivial value for accesses in the past is retained by accumulating the two factors over many time spans expressed as a logarithmic system time. Having two factors, access frequency and the logarithmic system time, provides for a more balanced caching system. | 12-13-2012 |
20120317339 | SYSTEM AND METHOD FOR CACHING DATA IN MEMORY AND ON DISK - A cache is configured as a hybrid disk-overflow system in which data sets generated by applications running in a distributed computing system are stored in a fast access memory portion of cache, e.g., in random access memory and are moved to a slower access memory portion of cache, e.g., persistent durable memory such as a solid state disk. Each data set includes application-defined key data and bulk data. The bulk data are moved to slab-allocated slower access memory while the key data are maintained in fast access memory. A pointer to the location within the slower access memory containing the bulk data is stored in the fast access memory in association with the key data. Applications call data sets within the cache using the key data, and the pointers facilitate access, management and manipulation of the associated bulk data. Access, management and manipulation occur asynchronously with the application calls. | 12-13-2012 |
20120317340 | MEMORY CONTROLLER AND NON-VOLATILE STORAGE DEVICE - A non-volatile storage device comprises non-volatile memories for storing data; and a memory controller for carrying out control of the non-volatile memory. The memory controller stores second error correcting code as well as first error correcting code stored in the same page of the data. The memory controller, when writing data smaller than a predefined size, does not add the second error correcting code, and stores duplexed data of the data and the first correcting code in a different page. The memory controller, when reading, corrects data using the first and/or second correcting code. The valid data management table manages which logical block stores valid data with respect to an identical logical address. | 12-13-2012 |
20120317341 | MEMORY CONTROLLER AND NON-VOLATILE STORAGE DEVICE - A non-volatile storage device, which communicates with an access device and carries out reading and/or writing of data in accordance with a command from the access device, the device comprises one or more non-volatile memories for storing data and a memory controller for carrying out control of the non-volatile memory. The memory controller writes data to the error correcting group and writes a provisional error correcting code with respect to the data to the parity table if a data size is smaller than the first size when writing the data. | 12-13-2012 |
20120317342 | WEAR LEVELING METHOD FOR NON-VOLATILE MEMORY - Provided is a wear leveling method for a non-volatile memory. A wear leveling method for a non-volatile memory comprising a base area in which address mapping for data access is performed on a block basis includes selecting a unit having a high wear value from among a plurality of units included in each of a plurality of blocks of the base area and mapping the selected unit of the base area to a unit included in a log area. The wear leveling method manages wear by mapping a physical address to a logical address on a block basis while performing mapping for wear leveling on a basis of a smaller unit than a block, thereby lengthening the lifespan of the memory without degrading the performance of the memory. | 12-13-2012 |
20120317343 | DATA PROCESSING APPARATUS - A data processing apparatus includes: a first storage including volatile storage media; a second storage including nonvolatile storage media; an electronic circuit unit including at least one volatile register; and a selector configured to select one of the first and the second storage to be accessed by the electronic circuit unit. The selector selects the first storage in a state where data processing performed by the electronic circuit unit is ongoing, and the second storage in a state where the data processing is stopped for a shutdown of electric power of the data processing apparatus. The electronic circuit unit stores register data in the storage selected by the selector, the register data being stored in the register at the time when the data processing is stopped for the shutdown. | 12-13-2012 |
20120317344 | METHOD OF AND APPARATUS FOR STORING DATA - An electronic device for storing data content by storing at least a portion of the data content in a rewritable memory device by storing an n bit count value associated with the status of the data content in a one time programmable memory. The n bit count value is written to the secure memory device along with the corresponding data content. Then the n bit count value is incremented and stored in the one time programmable memory each time there is a modification of the data content in the rewritable memory device. The number of bits of the one time programmable memory may correspond to the number of potential modifications of the stored data content. | 12-13-2012 |
20120317345 | WEAR LEVELING METHOD AND APPARATUS - The present invention discloses a wear leveling method; the method determines a pool mask for each physical block based on an erase number of each physical block. For different erase numbers, masks of the physical blocks are determined as cool pool mask CPM, normal pool mask NPM or hot pool mask HPM. When the pool mask of one physical block is changed from NPM to HPM, data of any physical block of which the pool mask is CPM is copied to the physical block of which the pool mask is HPM, and the physical block of which the pool mask is CPM is recycled as a garbage block. The present invention discloses a wear leveling apparatus, the method and apparatus can reduce additional wear caused by the wear leveling. | 12-13-2012 |
20120317346 | DATA STORING METHOD, AND MEMORY CONTROLLER AND MEMORY STORAGE APPARATUS USING THE SAME - A data storing method for a rewritable non-volatile memory module is provided. The method includes receiving page data to be stored in a first logical address. The method also includes determining whether a storage status of the rewritable non-volatile memory module is a predetermined status; if yes, using a first writing mode to write the page data into the rewritable non-volatile memory module; if no, using a second writing mode to write the page data into the rewritable non-volatile memory module. In the first writing mode, lower physical program units of the rewritable non-volatile memory module are applied for writing data, and upper physical program units of the rewritable non-volatile memory module are not applied for writing data; in the second writing mode, the upper physical program units and the lower physical program units are applied for writing data. | 12-13-2012 |
20120317347 | CONTROL AND OPERATION OF NON-VOLATILE MEMORY - Various embodiments comprise apparatuses and methods including a memory controller to control a non-volatile memory array. The memory controller includes a memory array interface coupled to the non-volatile memory array to perform reads and writes on the non-volatile memory array. An overwrite module is configured to write a desired bit value to a specific memory cell within the non-volatile memory array, after receiving the desired bit value and a logical address, regardless of an original value of the memory cell Additional apparatuses and methods are described. | 12-13-2012 |
20120317348 | MITIGATE FLASH WRITE LATENCY AND BANDWIDTH LIMITATION - A method of operating a memory system is provided. The method includes a controller that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the controller to regulate read and write access to the one or more FLASH devices. Wear leveling components along with read and write processing components are provided to facilitate efficient operations of the FLASH memory devices. | 12-13-2012 |
20120317349 | PROCESSING DEVICE AND WRITING METHOD FOR WRITING A FILE TO A STORAGE MEDIUM - An acquiring unit acquires, from a storage device capable of storing a file by dividing the file into a plurality of blocks, managing information indicating an address of each block configuring the file. A creating unit creates a table indicating a start address and a size of each continuous region by extracting the address of each block from the acquired managing information, and aggregating blocks having continuous addresses as a continuous region. A reading unit reads a file stored in a non-volatile memory. A dividing unit divides the read file into a plurality of blocks. A writing unit writes the divided file to the storage device in units of the continuous region, which is from the start address over the size, based on the table, so as to maintain the addresses indicated in the managing information. | 12-13-2012 |
20120324146 | Asymmetric Storage Device Wide Link - A wide link communicates information between a storage enclosure having plural storage devices and an information handling system by selectively configuring upstream and downstream paths of narrow links to communicate in the same direction. A link load analyzer detects predetermined conditions, such as over utilization or under utilization of narrow link capacity, which initiates a re-configuration of the direction of information through a path of a narrow link. A master link manager configures a narrow link path to manage communication of configuration information for one or more narrow link paths configured to communicate in a direction. | 12-20-2012 |
20120324147 | Read While Write Method for Serial Peripheral Interface Flash Memory - The present invention discloses a RWW method for SPI flash memory. The RWW method comprises executing a write command, halting the write command during receiving a read command, executing the reading, and internally restoring the write command when completing the read command. | 12-20-2012 |
20120324148 | SYSTEM AND METHOD OF PROTECTING METADATA FROM NAND FLASH FAILURES - Methods and systems are disclosed for protecting metadata from NAND flash failures. With data striped across multiple flash memory chips, the flash memory multiple chips may store multiple copies of metadata (and potentially ECC). The metadata stored in the multiple copies on the flash memory chips may be different from one another. For example, on a particular chip, a first copy of metadata is stored and a second copy of metadata is stored, with the second copy being a redundant copy of the metadata stored on a different chip. In this way, if one of the chips fails, a copy of the failed chips metadata is stored on another of the chips, and may be accessed. | 12-20-2012 |
20120324149 | METHODS AND APPARATUS FOR DATA ACCESS BY A REPROGRAMMABLE CIRCUIT MODULE - In some embodiments, an apparatus includes a set of memory modules configured to store data and a reprogrammable circuit module operatively coupled to the set of memory modules. The reprogrammable circuit module is configured to receive, from a host device, information associated with a search request. The reprogrammable circuit module is configured to change from a first configuration to a second configuration in response to receiving the information. The reprogrammable circuit module is configured to retrieve at least a portion of the data stored at the set of memory modules associated with the second configuration. The reprogrammable circuit module is configured to generate a search result based on the portion of the data, and transmit the search result to the host device. | 12-20-2012 |
20120324150 | SYSTEM AND METHOD OF RECOVERING DATA IN A FLASH STORAGE SYSTEM - A data storage method, comprising, receiving host data to be written to a plurality of flash storage devices, allocating the host data to one or more data units of a plurality of data units, allocating pad data to one or more data units of the plurality of data units that have not been filled with host data and generating redundant data in a redundant data unit based on the plurality of data units. In certain aspects, the method further comprises steps for writing the plurality of data units and the redundant data unit to a stripe across the plurality of flash storage devices, wherein each of the plurality of data units and the redundant data unit is written in the respective flash storage devices at a common physical address. | 12-20-2012 |
20120324151 | ENHANCED THROUGHPUT FOR SERIAL FLASH MEMORY - Example embodiments for providing enhanced throughput for a serial flash memory device may comprise enabling a streaming mode for read operations. | 12-20-2012 |
20120324152 | MEMORY CONTROLLER WITH BI-DIRECTIONAL BUFFER FOR ACHIEVING HIGH SPEED CAPABILITY AND RELATED METHOD THEREOF - A memory controller for accessing a serial Flash memory is disclosed. The memory controller includes a logic circuit; a bi-directional buffer, coupled to the logic circuit, for selectively reversing the direction of data flow according to a control signal generated from the logic circuit, the bi-directional buffer comprising: an input port, coupled to a data output port of the logic circuit; a control port, coupled to the logic circuit, for receiving the control signal; and an output port, coupled to a data input port of the logic circuit, the output port being utilized for coupling both an input data port and an output data port of the serial Flash memory. | 12-20-2012 |
20120324153 | Efficient mapping of data blocks in a flash cache - A storage device made up of multiple storage media is configured such that a flash memory serves as a cache for data stored on a backend storage device having one or more magnetic storage media. The storage device includes a controller configured to maintain a direct mapping from respective backend block addresses of the backend storage device to respective physical addresses of the flash memory. Such mapping is used to translate a backend block address of the backend storage device at which a first block is stored into a physical address of the flash memory at which the first block is cached. | 12-20-2012 |
20120324154 | DATA PROGRAMMING METHODS AND DEVICES - A data programming method for a data programming device having a non-volatile memory and a volatile memory, the method comprising determining whether data exceeds one page; if the data does not exceed one page and is insufficient for one page, storing the data into the volatile memory; determining whether next data is to be programmed into the same page as the data stored in the volatile memory; if the next data is to be programmed into the same page as the data stored in the volatile memory, programming the data and the next data into the non-volatile memory. | 12-20-2012 |
20120324155 | WEAR LEVELING - A method for operating a computer memory and a storage device. The memory is organized to store data in units of such memory. For each unit of a set of units a wear level of the unit is determined. A maximum wear level among the wear levels is determined. A suggestion of a subset of one or more units for being selected for data erasure is received and at least one unit in the subset is identified for subsequent data erasure, a wear level (c(i)) of which units (i) is less than the maximum wear level (c_max). | 12-20-2012 |
20120331207 | Controller, Storage Device, and Method for Power Throttling Memory Operations - The embodiments described herein provide a controller, storage device, and method for power throttling memory operations. In one embodiment, a controller is provided in a storage device with a plurality of flash memory devices. The controller determines how much power will be consumed (or heat will be generated) by each of a plurality of commands and dynamically alters when each of the commands operating on one or more of the flash memory devices is performed based on the determination of how much power would be consumed (or heat will be generated), so that performance of the plurality of commands does not exceed a predetermined average power limit over a period of time (or a predetermined temperature). In some embodiments, the storage device also has a thermal sensor, and a reading from the thermal sensor can be used, instead of or in addition to the power or thermal costs of each command, to dynamically alter when the commands are performed. | 12-27-2012 |
20120331208 | ADAPTIVE INTERNAL TABLE BACKUP FOR NON-VOLATILE MEMORY SYSTEM - Methods and apparatus for allowing tables to be adaptively backed up are disclosed. According to one aspect of the present invention, a method for operating a memory system with a non-volatile memory that includes a reserved memory area, a plurality of physical blocks and a plurality of data structures including an erase count block involves determining when contents associated with at least one data structure of the plurality of data structures are to be substantially backed up. A request to substantially back up the contents associated with the at least one data structure is executed when it is determined that the contents associated with the at least one data structure are to be substantially backed up. Executing the request allows contents associated with the at least one data structure are substantially backed up in the reserved memory area. | 12-27-2012 |
20120331209 | SEMICONDUCTOR STORAGE SYSTEM - A semiconductor storage system includes a plurality of buffer areas for receiving data from an external source via a first interface unit. A storage unit stores the data by writing the data received from the plurality of buffer areas via a second interface unit. A processor controls the plurality of buffer areas and the storage and includes a first processor controlling the first interface unit, and a second processor controlling the second interface unit. The first processor includes a delay unit delaying a time at which the plurality of buffer areas receives the data from the external source via the first interface unit. The time functions as a delay time corresponding to a difference between a data reception speed of the plurality of buffer areas via the first interface unit and a data reception speed of the storage via the second interface unit. | 12-27-2012 |
20120331210 | NON-VOLATILE MEMORY DEVICE AND RELATED METHOD OF OPERATION - A nonvolatile memory device comprises a cell array connected to a plurality of bit lines in an all bit line structure, a page buffer circuit connected to the plurality of bit lines, and control logic configured to control the page buffer circuit. The control logic controls the page buffer circuit to sense memory cells corresponding to both even-numbered and odd-numbered columns of a selected page in a first read mode and to sense memory cells corresponding to one of the even-numbered and odd-numbered columns of the selected page in a second read mode. A sensing operation is performed at least twice in the first read mode and once in the second read mode. | 12-27-2012 |
20120331211 | SEMICONDUCTOR DEVICE AND PARAMETER SETTING METHOD THEREOF - According to one embodiment, a semiconductor device includes a nonvolatile memory configured to store setting data including a parameter and an address in which the parameter is to be set, and a register control circuit configured to read the setting data from the nonvolatile memory at the start time and set the parameter in the address. The semiconductor device includes a signal processing circuit operated according to the parameter stored in the register control circuit and a control signal supplied from a first interface after the setting data is set in the register control circuit. | 12-27-2012 |
20120331212 | STATUS INFORMATION SAVING AMONG MULTIPLE COMPUTERS - Provided are techniques for status information saving among multiple computers. In one embodiment, a selected computer is operated using a plurality of input/output devices over switched input/output signal paths passing through a KVM (keyboard video mouse) switch positioned between the selected computer and the plurality of input/output devices. Status data is carried over signal paths passing through the KVM switch wherein the status data represents status information for a plurality of computers connected to the KVM switch. The status data passing through the KVM switch is stored in a memory coupled to the KVM switch. Other embodiments are described and claimed. Other embodiments are contemplated, depending upon the particular application. | 12-27-2012 |
20120331213 | TECHNIQUE AND APPARATUS FOR IDENTIFYING CACHE SEGMENTS FOR CACHING DATA TO BE WRITTEN TO MAIN MEMORY - A memory apparatus having a cache memory including cache segments, and memorizing validity data indicative of whether or not each of the sectors contained in each cache segment is a valid sector inclusive of valid data; and a cache controlling component for controlling access to the cache memory. The cache controlling component includes a detecting component for detecting, when writing a cache segment back to the main memory, areas having consecutive invalid sectors by accessing validity data corresponding to the cache segment, and a write-back controlling component issuing a read command to the main memory, the read command being for reading data into each area detected, making the area a valid sector, and writing the data in the cache segment back to the main memory. | 12-27-2012 |
20120331214 | Defragmentation Method For A Machine-Readable Storage Device - A defragmentation method includes the steps of: a) configuring a processor to determine a type of a target machine-readable storage device coupled electrically to the processor; b) configuring the processor to select, from among a plurality of pre-established defragmentation algorithms respectively for performing defragmentation on different types of machine-readable storage devices, a defragmentation algorithm that corresponds to the type of the target machine-readable storage device as determined in step a); and c) configuring the processor to perform defragmentation on the target machine-readable storage device according to the defragmentation algorithm as selected in step b). | 12-27-2012 |
20120331215 | METHOD FOR MANAGING A MEMORY APPARATUS, AND ASSOCIATED MEMORY APPARATUS THEREOF - A method for managing a memory apparatus including at least one non-volatile (NV) memory element includes: providing at least one block of the memory apparatus with at least one local page address linking table within the memory apparatus, wherein the local page address linking table includes linking relationships between physical page addresses and logical page addresses of a plurality of pages; and building a global page address linking table of the memory apparatus according to the local page address linking table. More particularly, the step of providing the block with the local page address linking table further includes: building a temporary local page address linking table for the local page address linking table corresponding to programming/writing operations of the memory apparatus; and temporarily storing the temporary local page address linking table in a volatile memory of the memory apparatus, and updating the temporary local page address linking table when needed. | 12-27-2012 |
20120331216 | METHOD FOR MANAGING A MEMORY APPARATUS, AND ASSOCIATED MEMORY APPARATUS THEREOF - A method for managing a memory apparatus including at least one non-volatile (NV) memory element includes: providing at least one block of the memory apparatus with at least one local page address linking table within the memory apparatus, wherein the at least one local page address linking table includes linking relationships between at least one physical page address of the at least one block and at least one logical page address; and building a global page address linking table of the memory apparatus according to the at least one local page address linking table. | 12-27-2012 |
20120331217 | MEMORY DEVICE PROGRAM WINDOW ADJUSTMENT - In one or more embodiments, a memory device has an adjustable programming window with a plurality of programmable levels. The programming window is moved to compensate for changes in reliable program and erase thresholds achievable as the memory device experiences factors such as erase/program cycles that change the program window. The initial programming window is determined prior to an initial erase/program cycle. The programming levels are then moved as the programming window changes, such that the plurality of programmable levels still remain within the program window and are tracked with the program window changes. | 12-27-2012 |
20120331218 | FLASH MEMORY STORAGE SYSTEM, AND CONTROLLER AND ANTI-FALSIFYING METHOD THEREOF - A flash memory storage system having a flash memory controller, a flash memory chip and a smart card chip is provided. The flash memory chip is configured to store security data. The flash memory controller generates a signature corresponding to the security data according to a private key and the security data with a one-way hash function, and stores the signature into the smart card chip. | 12-27-2012 |
20130007343 | Parameter Tracking for Memory Devices - Methods and systems involve collecting memory device parameters and using memory device parameters to determine memory wear information. A set of first parameters associated with wear of the memory device is monitored for at least one memory unit of the memory device. The first parameters are compared to respective trigger criterion. If the comparison reveals that one or more of the first parameters are beyond their trigger criterion, then collection of a second set of parameters is triggered. The second parameters are also indicative of the wear of the memory device. The set of first parameters may overlap the set of second parameters. The set of second parameters are used to develop memory wear information. In some implementations, the memory wear information may be configuration information used to configure the read/write channel to compensate for wear of the memory device. In some implementations, the memory wear information may be used to predict or estimate the lifetime of the device. | 01-03-2013 |
20130007344 | Apparatus, System, and Method for Refreshing Non-volatile Memory - Described herein are an apparatus, system, and method for refreshing a non-volatile memory. The method comprises loading a time stamp, corresponding to data in a data location of a non-volatile memory, to a register; determining an elapsed time, corresponding to the data in the data location, according to the loaded time stamp; and refreshing data of the data location for which it is determined that the elapsed time exceeds a refresh time associated with the non-volatile memory. | 01-03-2013 |
20130007345 | TECHNIQUES FOR MOVING DATA BETWEEN MEMORY TYPES - A two-level paging mechanism. The first level gathers data from reclaimable memory locations for a process and compacts the data into a single container. The second level sends the compact container's contents to a swap file and may use optimal I/O operations to the target memory device. On-demand paging is made possible by having a first pager locate the requested data in the compact container and then having a second pager retrieve the corresponding data from the swap file. | 01-03-2013 |
20130007346 | METHOD TO DETECT UNCOMPRESSIBLE DATA IN MASS STORAGE DEVICE - Described are embodiments of methods, apparatus, and systems for detecting incompressible data and selectively compressing compressible data without compressing the incompressible data. A method may include determining a first compressibility value of first data of a plurality of input data and a second compressibility value of second data of the plurality of input data, determining that the first data is incompressible based at least in part on the first compressibility value relative to a compressibility threshold, and compressing the second data of the plurality of input data. Other embodiments may be described and claimed. | 01-03-2013 |
20130007347 | Booting a Memory Device from a Host - In one implementation, a method includes receiving, at a memory device, an instruction to boot the memory device, wherein the memory device includes non-volatile memory accessible by a controller of the memory device; and, in response to receiving the instruction to boot the memory device, obtaining, by the memory device, firmware from a host device, wherein the host device is separate from and communicatively coupled to the memory device. The method can also include booting the memory device using the firmware from the host device, wherein the memory device boots separately from the host device, and the host device performs operations using data or instructions stored in the non-volatile memory and obtained through communication with the memory controller of the memory device. | 01-03-2013 |
20130007348 | Booting Raw Memory from a Host - In one implementation, a method includes receiving, at a memory device, an instruction to boot the memory device, wherein the memory device includes non-volatile memory; and, in response to receiving the instruction to boot the memory device, obtaining, by the memory device, one or more trim values from the host device, wherein the trim values define one or more parameters for accessing the non-volatile memory, and the host device is separate from and communicatively coupled to the memory device. The method can also include booting the memory device using the trim values from the host device, wherein the memory device boots separately from the host device, and the host device performs operations using data or instructions stored in the non-volatile memory and obtained by providing commands to the memory device. | 01-03-2013 |
20130007349 | SMART BRIDGE FOR MEMORY CORE - An apparatus includes a first semiconductor device including a NAND flash memory core. The apparatus also includes a second semiconductor device including periphery circuitry associated with the NAND flash memory core. | 01-03-2013 |
20130007350 | SMART BRIDGE FOR MEMORY CORE - An apparatus includes a first semiconductor device including a memory core. The apparatus also includes a second semiconductor device including periphery circuitry associated with the memory core. The second semiconductor device includes a second serializer/deserializer communication interface coupled to a first serializer/deserializer communication interface of a memory controller. | 01-03-2013 |
20130007351 | INFORMATION PROCESSOR, INFORMATION PROCESSING METHOD, AND COMPUTER PROGRAM PRODUCT - According to one embodiment, an information processor includes: a first storage comprising a nonvolatile semiconductor memory configured to store therein data specific to a user in association with identification information for identifying the user; a second storage used as a work area; a manager configured to copy the specific data stored in the first storage to the second storage at a predetermined timing; a logon module configured to allow a specific user to logon to the information processor by using the identification information; a determination module configured to determine whether the specific data corresponding to identification information of the logged-on user is stored in the second storage; and a processor configured to perform a predetermined process by using the specific data stored in the second storage when the first determination module determines the specific data corresponding to the identification information of the logged-on user is stored in the second storage. | 01-03-2013 |
20130007352 | HOST-ASSISTED COMPACTION OF MEMORY BLOCKS - In a system that includes a host and a memory controller that is separate from the host and stores data for the host in a non-volatile memory, a method for data storage includes transferring from the memory controller to the host one or more source blocks from the non-volatile memory for compaction. The source blocks are compacted in the host by copying valid data from the source blocks into one or more destination blocks. The destination blocks are transferred from the host to the memory controller, and the destination blocks are stored by the memory controller in the non-volatile memory. | 01-03-2013 |
20130007353 | CONTROL METHOD OF NONVOLATILE MEMORY DEVICE - According to example embodiments, a control method of a nonvolatile memory device, which includes a plurality of memory blocks on a substrate, each memory block including a plurality of sub blocks stacked in a direction perpendicular to the substrate and being configured to be erased independently and each sub block including a plurality of memory cells stacked in the direction perpendicular to the substrate. The control method includes comparing a count value of a first memory block with a reference value, the count value determined according to the number of program, read, or erase operations executed at the first memory block after data is programmed in the first memory block; and if the count value is greater than or equal to the reference value, performing a reprogram operation in which data programmed in first the memory block is read and the read data is programmed in a second memory block. | 01-03-2013 |
20130007354 | DATA RECORDING DEVICE AND DATA RECORDING METHOD - A data recording device according to the present invention includes a virtual device control unit that controls, as a single virtual device, at least a part of a memory area of the first flash memory recording medium and at least a part of a memory area of the second flash memory recording medium; and a file management unit that performs a programming process and an erasing process in parallel, the programming process for programming data in a memory area included in the virtual device and the first flash memory recording medium, and the erasing process for erasing data from a memory area included in the virtual device and the second flash memory recording medium. | 01-03-2013 |
20130007355 | DATA CONDITIONING TO IMPROVE FLASH MEMORY RELIABILITY - Methods and apparatus for managing data storage in memory devices utilizing memory arrays of varying density memory cells. Data can be initially stored in lower density memory. Data can be further read, compacted, conditioned and written to higher density memory as background operations. Methods of data conditioning to improve data reliability during storage to higher density memory and methods for managing data across multiple memory arrays are also disclosed. | 01-03-2013 |
20130013848 | REDUNDANT ARRAY OF INDEPENDENT DISK (RAID) CONTROLLED SEMICONDUCTOR STORAGE DEVICE (SSD)-BASED SYSTEM HAVING A HIGH-SPEED NON-VOLATILE HOST INTERFACE - Embodiments of the invention provide a RAID controlled SSD-based system having a high-speed, non-volatile host interface. Specifically, in a typical embodiment, a RAID-controlled device is provided that comprises a high-speed host interface that is coupled to a redundant array of independent disks (RAID) controller. The RAID controller itself is coupled to a set of controlled memory units that each comprises: a main controller coupled to cache memory; and a set of SSD memory units (each having a set of blocks of memory) coupled to the main controller. | 01-10-2013 |
20130013849 | Programmable Patch Architecture for ROM - A system according to one embodiment includes a host central processing unit (CPU); a first storage medium configured to be in communication with the host CPU and to store information associated with at least one address; a second storage medium configured to be in communication with the host CPU, to store patch information associated with the at least one address of the first storage medium; and selection circuitry configured to, in response to a fetch instruction from the host CPU, select the patch information from the second storage medium if the fetch instruction contains a destination address that matches the at least one address associated with the patch information. | 01-10-2013 |
20130013850 | RELATIVE HEAT INDEX BASED HOT DATA DETERMINATION FOR BLOCK BASED STORAGE TIERING - Disclosed is a process for determining a heat index for a block of data, such as an extent, for storage tiering. Weighted scores are used for read and write operations, since solid state devices operate better with read operations than write operations. The heat index associated with each extent is a function of a base score, rather than an absolute value. The base score is determined by adding the number of extents in a hot tier plus the access score, divided by the number of extents in the hot tier. In this fashion, the base score measures the weighted I/O activity relative to the size of the hot tier. | 01-10-2013 |
20130013851 | DATA STREAM DISPATCHING METHOD, MEMORY CONTROLLER, AND MEMORY STORAGE APPARATUS - A data stream dispatching method for a memory storage apparatus having a non-volatile memory module and a smart card chip is provided. The method includes configuring a plurality of logical block addresses for the non-volatile memory module, wherein a plurality of specific logical block addresses is used for storing a specific file. The method also includes receiving a response data unit from the smart card chip and storing the response data unit into a buffer memory. The method further includes when a logical block address corresponding to a read command issued by a host system is one of the specific logical block addresses and the response data unit is stored in the buffer memory, transmitting the response data unit to the host system by aligning an access unit. Thereby, the host system can correctly receive the response data unit from the smart card chip. | 01-10-2013 |
20130013852 | MEMORY CONTROLLING METHOD, MEMORY CONTROLLER AND MEMORY STORAGE APPARATUS - A memory controlling method, a memory controller and a memory storage apparatus are provided. The method includes identifying whether a transmission mode between the memory storage apparatus and a host system belongs to a first transmission mode or a second transmission mode and grouping memory dies of the memory storage apparatus into a plurality of memory die groups. The method also includes applying a first erasing mode to erase data stored in the memory dies when the transmission mode belongs to the first transmission mode and applying a second erasing mode to erase the data stored in the memory dies when the transmission mode belongs to the second transmission mode, wherein at least a part of the memory die groups are enabled simultaneously in the first erasing mode and any two of the memory die groups are not enabled simultaneously in the second erasing mode. | 01-10-2013 |
20130013853 | COMMAND EXECUTING METHOD, MEMORY CONTROLLER AND MEMORY STORAGE APPARATUS - A command executing method for a memory storage apparatus and a memory controller and the memory storage apparatus using the same are provided. The method includes, during a data merging operation, receiving a write command and a write data corresponding to the write command from a host system. The method also includes temporarily storing the write data into a buffer memory, and at a delay time point, transmitting a response message to the host, the delay time point is set by adding a dummy delay time to a time point that the operation of writing the write data into the buffer memory is completed. Accordingly, the method can effectively level the response times of executing write commands during the data merging operation, thereby shortening the maximum access time. | 01-10-2013 |
20130013854 | MEMORY CONTROLLER, METHOD THEREOF, AND ELECTRONIC DEVICES HAVING THE MEMORY CONTROLLER - A method for operating a memory controller is provided. The method includes generating a pseudo random number by using a seed included in a stored seed group corresponding to a page to be currently programmed, wherein the stored seed group is stored among a plurality of seed groups. Data to be programmed into the current page is randomizing by using the pseudo random number and the memory controller outputs the randomized data. A solid state drive (SSD) or other memory storage device such as a memory card includes the memory controller and includes a read only memory (ROM) storing the plurality of seed groups. The memory controller includes a micro-processor and a read only memory (ROM) storing executable code for causing the micro-processor to access the plurality of stored seed groups and to select a seed therefrom corresponding to a page to be currently programmed. | 01-10-2013 |
20130013855 | MEMORY CONTROLLERS AND MEMORY SYSTEMS INCLUDING THE SAME - A memory controller may include a cell state generator that is configured to generate a cell state for each of a plurality of multi-level cells included in a non-volatile memory device, using data of pages. The memory controller may also include a pseudo-random number generator that is configured to generate a pseudo-random number. The memory controller may further include an operator that is configured to change the cell state of each multi-level cell using the pseudo-random number, and that is configured to output a changed cell state for each multi-level cell. | 01-10-2013 |
20130013856 | FLASH MANAGEMENT TECHNIQUES - Various flash management techniques may be described. An apparatus may comprise a processor, a flash memory coupled to the processor, and a flash management module. The flash management module may be executed by the processor to receive a write request to write data to the flash memory, write a first control sector with a sequence number to the flash memory, and write the sequence number, an address for a logical sector, and data to at least one physical sector corresponding to the logical sector of the flash memory. Other embodiments are described and claimed. | 01-10-2013 |
20130019048 | Memory Access To A Dual In-line Memory Module Form Factor Flash MemoryAANM Bland; Patrick M.AACI RaleighAAST NCAACO USAAGP Bland; Patrick M. Raleigh NC USAANM Desai; Dhruv M.AACI CaryAAST NCAACO USAAGP Desai; Dhruv M. Cary NC USAANM Foster, SR.; Jimmy G.AACI MorrisvilleAAST NCAACO USAAGP Foster, SR.; Jimmy G. Morrisville NC USAANM Ono; MakotoAACI CaryAAST NCAACO USAAGP Ono; Makoto Cary NC US - Methods, apparatuses, and computer program products for memory access to a dual in-line memory module (DIMM) form factor flash memory are provided. Embodiments include receiving, by a controller from a processor through cacheable memory in the processor, a read request; transmitting, by the controller, the read request to the DIMM form factor flash memory; polling, by the controller, a read queue in the DIMM form factor flash memory until data is ready for the read request; copying from the DIMM form factor flash memory, by the controller, the data corresponding to the read request to a read queue in the controller; transmitting, by the controller on an interface between the controller and the processor, an invalidate command for the cacheable memory; and in response to receiving the invalidate command, reading by the processor the data stored in the read queue in the controller. | 01-17-2013 |
20130019049 | BLOCK MANAGEMENT METHOD, MEMORY CONTROLLER AND MEMORY STOARGE APPARATUSAANM Yeh; Chih-KangAACI Kinmen CountyAACO TWAAGP Yeh; Chih-Kang Kinmen County TW - A block management method for a rewritable non-volatile memory module having a plurality of physical blocks, and a memory controller and memory storage apparatus using the same are provided. The method includes logically grouping the physical blocks at least into a data area, a free area and a replacement area and configuring a plurality of logical blocks for mapping to the physical blocks of the data area. The method also includes assigning bad physical blocks into the data area and marking the logical blocks mapping to the bad physical blocks as bad logical addresses, thereby forbidding the access of the logical blocks mapping to the bad physical blocks. According, the method can effectively use the rewritable non-volatile memory module having too many bad physical blocks to store data. | 01-17-2013 |
20130019050 | FLEXIBLE FLASH COMMANDS - A method of controlling a flash media system. The method includes providing a flash lane controller having a processor control mode and creating and presenting soft contexts. The soft contexts generally place the flash lane controller into the processor control mode. In the processor control mode, the flash lane controller stores the entire soft context, finishes executing any outstanding contexts, suspends normal hardware automation, and then executes the soft context. | 01-17-2013 |
20130019051 | META DATA HANDLING WITHIN A FLASH MEDIA CONTROLLER - A method for handling meta data stored in a page of a flash memory within a flash media controller. The method generally includes (i) defining the meta data on a per context basis, where the context is defined on a per page basis, (ii) when a size of the meta data is less than or equal to a predefined threshold, storing the complete meta data within a structure of the context, and (iii) when the size of the meta data is greater than the predefined threshold, defining meta data pointers within the context. | 01-17-2013 |
20130019052 | EFFECTIVE UTILIZATION OF FLASH INTERFACE - An apparatus including a first circuit, a second circuit, and a third circuit. The first circuit may be configured to maintain die-based information used for operation of a flash lane controller (FLC). The second circuit may be configured to manage contexts that are actively being processed by the flash lane controller (FLC). The third circuit may be configured to perform pipeline execution of a plurality of the contexts managed by the second circuit. | 01-17-2013 |
20130019053 | FLASH CONTROLLER HARDWARE ARCHITECTURE FOR FLASH DEVICES - A flash media controller including one or more dedicated data transfer paths, one or more flash lane controllers, and one or more flash bus controllers. The one or more flash lane controllers are generally coupled to the one or more dedicated data transfer paths. The one or more flash bus controllers are generally coupled to the one or more flash lane controllers. | 01-17-2013 |
20130019054 | FLASH MEMORY DEVICE AND METHOD PERFORMING ERASE OPERATION USING OVER PROGRAMAANM JUNG; YOUNG-WOOAACI OSAN-SIAACO KRAAGP JUNG; YOUNG-WOO OSAN-SI KRAANM KIM; HWAN-CHUNGAACI NAMWON-SIAACO KRAAGP KIM; HWAN-CHUNG NAMWON-SI KRAANM SHIN; HEE-TAKAACI HWASEONG-SIAACO KRAAGP SHIN; HEE-TAK HWASEONG-SI KRAANM AHN; CHUN-SOOAACI SUWON-SIAACO KRAAGP AHN; CHUN-SOO SUWON-SI KRAANM JUNG; JIN-WOOAACI SEOULAACO KRAAGP JUNG; JIN-WOO SEOUL KR - A flash memory device performs an erase operation by execution of an over program. device. In response to an erase request directed to requested page data a logical page address is converted to a corresponding physical page address, an over program data pattern for an over program operation is generated, and the over program operation is executed using the PPA to change a threshold voltage distribution for at least one memory cell of the requested page data in accordance with the over program data pattern. | 01-17-2013 |
20130019055 | MEMORY CONTROL DEVICE AND METHODAANM KIM; Ji-minAACI Suwon-siAACO KRAAGP KIM; Ji-min Suwon-si KRAANM SEO; Yoon-bumAACI Seongnam-siAACO KRAAGP SEO; Yoon-bum Seongnam-si KR - A memory control device is provided. The memory control device includes a plurality of memories, a plurality of host control units which are connected to the plurality of memories, respectively, and a synchronization unit which collectively performs a data read or data write operation for the plurality of memories through the plurality of host control units. Accordingly, it is possible to simultaneously perform a data read or data write operation for a plurality of memory cards by simultaneously controlling the plurality of memory cards which perform the data read or data write operation at different points in time. | 01-17-2013 |
20130019056 | Data Storing Method and Apparatus Applied to Flash Memory Storage DeviceAANM Wang; Rui-qingAACI ShenzhenAACO CNAAGP Wang; Rui-qing Shenzhen CNAANM Li; Da-tengAACI ShenzhenAACO CNAAGP Li; Da-teng Shenzhen CNAANM Wu; WeiAACI ShenzhenAACO CNAAGP Wu; Wei Shenzhen CN - A data storage method applied to a flash memory storage device is provided. The method includes: identifying a first tag pointing to a storage unit storing a first data, the first data being a newly updated data; locating the storage unit storing the first data according to the first tag; storing a second data to another storage unit; pointing the first tag to the another storage unit storing the second data. A relationship between the first tag and the storage unit storing the first data is first built. The second data is stored to another storage unit different from the storage unit pointed by the first tag, and a relationship between the first tag and the another storage unit storage the second data is rebuilt. Therefore, data is efficiently stored by using a plurality of storage units to prolong a lifespan of the flash memory. | 01-17-2013 |
20130019057 | FLASH DISK ARRAY AND CONTROLLER - A data storage array is described, having a plurality of solid state disks configured as a RAID group. User data is mapped and managed on a page size scale by the controller, and the data is mapped on a block size scale by the solid state disk. The writing of data to the solid state disks of the RAID group is such that reading of data sufficient to reconstruct a RAID stripe is not inhibited by the erase operation of a disk to which data is being written. | 01-17-2013 |
20130019058 | MULTI-PARTITIONING OF MEMORIES - Various embodiments comprise apparatuses and methods including a method of reconfiguring partitions in a memory device as directed by a host. The method includes managing commands through a first interface controller to mapped portions of a first memory not having an attribute enhanced set, and mapping portions of a second memory having the attribute enhanced set through a second interface controller. Additional apparatuses and methods are described. | 01-17-2013 |
20130024600 | NON-VOLATILE TEMPORARY DATA HANDLING - Systems and methods are provided for handling temporary data that is stored in a non-volatile memory, such as NAND flash memory. The temporary data may include hibernation data or any other data needed for only one boot cycle of an electronic device. When storing the temporary data in one or more pages of the non-volatile memory, the electronic device can store a temporary marker as part of the metadata in at least one of the pages. This way, on the next bootup of the electronic device, the electronic device can use the temporary marker to determine that the associated page contains unneeded data. The electronic device can therefore invalidate the page and omit the page from its metadata tables. | 01-24-2013 |
20130024601 | User Selectable Balance Between Density and Reliability - A method for enabling users to select a configuration balance for a memory device is described. The method includes receiving an indication of a memory configuration for a mass memory including two or more of memory cells. One or more memory cells of the mass memory are selected based at least in part on 1) the indication, 2) a current configuration for each of the one or more memory cells and 3) a program-erase count for each of the one or more memory cells. The method also includes determining a new configuration for each of the selected one or more memory cells. For each of the selected one or more memory cells, the configuration of the memory cell is changed from the current configuration to the determined new configuration. Apparatus and computer readable media are also disclosed. | 01-24-2013 |
20130024602 | Universal Storage for Information Handling Systems - An information handling system (IHS) includes a processor and a single universal storage device with a system memory region and a mass storage region, wherein disk commands are executed by the processor as transfers between the system memory region and the mass storage region. | 01-24-2013 |
20130024603 | DEVICE PROGRAMMING SYSTEM WITH DATA BROADCAST AND METHOD OF OPERATION THEREOF - A method of operation of a device programming system includes: providing a target programmer, having a programming bus; coupling an electronic device, having a non-volatile memory, to the target programmer by the programming bus; and programming a data image into the non-volatile memory by the target programmer includes: subscribing to a broadcast message, receiving a logical block, of the data image, by the broadcast message for programming the non-volatile memory, and sending an unsubscribe message after receiving the logical blocks of the data image from the broadcast message. | 01-24-2013 |
20130024604 | DATA WRITING METHOD, MEMORY CONTROLLER, AND MEMORY STORAGE APPARATUS - A method for writing updated data into a flash memory module having a plurality of physical pages is provided, wherein each physical page is the smallest writing unit of the flash memory module. The method includes partitioning a physical page into storage segments and configuring a state mark for each storage segment, wherein the state marks indicate the validity of data stored in the storage segments. The method also includes writing the updated data into at least one of the storage segments and changing the state mark corresponding to the storage segment containing the updated data, wherein the state mark corresponding to the storage segment containing the updated data indicates a valid state, and the state marks corresponding to the other storage segments of the physical page not containing the updated data indicate an invalid state. Thereby, the time for writing data into a physical page is effectively shortened. | 01-24-2013 |
20130024605 | SYSTEMS AND METHODS OF STORING DATA - A method of writing data is performed in a data storage device with a controller and a memory. The memory includes latches and multiple storage elements and is operative to store a first number of bits in each storage element according to a first mapping of sequences of bits to states of the storage elements. The method includes loading data bits into the latches within the memory and generating manipulated data bits in the latches by manipulating designated data bits in the latches using one or more logical operations. The method also includes storing sets of the manipulated data bits to respective storage elements of the group of storage elements according to the first mapping. The designated data bits correspond to states of the respective storage elements according to a second mapping of sequences of bits to states. The second mapping is different than the first mapping. | 01-24-2013 |
20130024606 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a nonvolatile semiconductor memory device comprises a first memory block and a second memory block, and a control circuit. In read operation, when a read target block is the first memory block, the control circuit determines whether the first memory block is single-level or multi-level according to a first flag, and stores a first determination result thereof. While the read target block is the first memory block, the control circuit reads the first memory block as single-level or multi-level according to the first determination result. When the read target block is changed from the first memory block to the second memory block, the control circuit erases the first determination result. | 01-24-2013 |
20130024607 | MEMORY APPARATUS - A memory apparatus includes first memory chip and second memory chip; and a control unit configured to manage a global reserved area, a first virtual area for the first memory chip, and a second virtual area for the second memory chip, wherein the first virtual area includes a first user area and a first reserved area, the second virtual area includes a second user area and a second reserved area, the global reserved area includes a first plurality of reserved blocks corresponding to the first reserved area and a second plurality of reserved blocks corresponding to the second reserved area, and the control unit is configured to assign a second virtual block included in the global reserved area to the first user area if the control unit detects a first virtual block included in the first user area is a bad block. | 01-24-2013 |
20130024608 | FLASH MEMORY APPARATUS - A flash memory apparatus includes a flash memory and a control unit for controlling the flash memory. The flash memory includes multiple blocks, each block of the multiple blocks corresponding to multiple word lines, and each word line of the multiple word lines corresponding to a first bit page and at least one second bit page. The control unit is configured to map a logic address included in a host's write request received from a host to a first process page of multiple in a first process block of the multiple blocks, and to program the first process page. The first process page is only the first bit page. | 01-24-2013 |
20130024609 | Tracking and Handling of Super-Hot Data in Non-Volatile Memory Systems - A non-volatile memory organized into flash erasable blocks sorts units of data according to a temperature assigned to each unit of data, where a higher temperature indicates a higher probability that the unit of data will suffer subsequent rewrites due to garbage collection operations. The units of data either come from a host write or from a relocation operation. Among the units more likely to suffer subsequent rewrites, a smaller subset of data super-hot is determined. These super-hot data are then maintained in a dedicated portion of the memory, such as a resident binary zone in a memory system with both binary and MLC portions. | 01-24-2013 |
20130024610 | Method for Operating Non-Volatile Memory and Data Storage System Using the Same - A method for operating a non-volatile memory is provided. The non-volatile memory includes a plurality of physical blocks having a plurality of data blocks and spare blocks. An index is obtained by comparing an average erase count of selected physical blocks with a first threshold. Each erase count for each physical block is the total number of the erase operations performed thereon. A performance capability status for the memory is determined according to the index. The performance capability status is set to a first status when the average erase count exceeds the first threshold. An indication is generated based on the performance capability status. A limp function is performed in response to the first status for configuring a minimum number of the at least some spare blocks reserved and used for data update operations. | 01-24-2013 |
20130024611 | Controller for One Type of NAND Flash Memory for Emulating Another Type of NAND Flash Memory - A method of executing reading instruction to read host data from a flash memory device is provided. The method initiates with receiving from a host device a read instruction to read host data from an array of NAND flash memory cells grouped into separately-readable device pages, the host data being a portion of device data that is stored in a device page. The host data is parsed from device data, and the parsed host data is sent to the host device. | 01-24-2013 |
20130024612 | STORING ROW-MAJOR DATA WITH AN AFFINITY FOR COLUMNS - A method, device, and computer readable medium for striping rows of data across logical units of storage with an affinity for columns is provided. Alternately, a method, device, and computer readable medium for striping columns of data across logical units of storage with an affinity for rows is provided. When data of a logical slice is requested, a mapping may provide information for determining which logical unit is likely to store the logical slice. In one embodiment, data is retrieved from logical units that are predicted to store the logical slice. In another embodiment, data is retrieved from several logical units, and the data not mapped to the logical unit is removed from the retrieved data. | 01-24-2013 |
20130031297 | ADAPTIVE RECORD CACHING FOR SOLID STATE DISKS - A storage controller receives a request that corresponds to an access of a track. A determination is made as to whether the track corresponds to data stored in a solid state disk. Record staging to a cache from the solid state disk is performed, in response to determining that the track corresponds to data stored in the solid state disk, wherein each track is comprised of a plurality of records. | 01-31-2013 |
20130031298 | INCLUDING PERFORMANCE-RELATED HINTS IN REQUESTS TO COMPOSITE MEMORY - A composite memory device that includes different types of non-volatile memory devices, which have different performance characteristics, is described. This composite memory device may receive requests, a given one of which includes a command, a logical address for at least a block of data associated with the command, and a hint associated with the command. For the given request, the composite memory device executes the command on the block of data at the logical address in at least one of the types of non-volatile memory devices. Furthermore, the composite memory device conditionally executes the hint based on one or more criteria, such as: available memory in the types of non-volatile memory devices, traffic through an interface circuit in the composite memory device, operational states of the types of non-volatile memory devices, a target performance characteristic of the composite memory device, and an environmental condition of the composite memory device. | 01-31-2013 |
20130031299 | DISK INPUT/OUTPUT (I/O) LAYER ARCHITECTURE HAVING BLOCK LEVEL DEVICE DRIVER - In general, embodiments of the present invention provide a disk an I/O layer architecture having a customized block-level device driver. In a typical embodiment, the architecture described herein comprises a file system layer being configured to handle user data; a buffer cache layer, adjacent the file system layer, the buffer cache layer being configured to handle page data; a block device driver layer adjacent the buffer cache layer, the block device driver layer being configured to handle block data, and the block device driver layer comprising an I/O scheduler layer and a device driver layer; and a storage unit layer adjacent the block device driver layer, the storage unit layer being configured to hand command data. Moreover, the storage unit layer can comprise a set (e.g., at least one) of semiconductor storage device (SSD) memory units, and the I/O scheduler layer can be configured to handle memory-based devices (e.g. a flash SSD memory device, a dynamic random access memory (DRAM) SSD memory device, etc.). | 01-31-2013 |
20130031300 | NON-VOLATILE MEMORY DEVICE, METHOD OF OPERATING THE SAME, AND MEMORY SYSTEM HAVING THE NON-VOLATILE MEMORY DEVICE - According to an aspect of the inventive concepts, there is provided a non-volatile memory device including a memory array with at least one stripe. The at least one stripe includes at least one parity page and at least one data page. The non-volatile memory device further includes a chip controller. The chip controller includes an operation module configured to perform an operation on data input from the outside of the memory device, to store a result of the performing, and to program the result of the performing into the at least one parity page. The chip controller further includes a data buffer configured to store the input data and to program the input data into the at least one data page. | 01-31-2013 |
20130031301 | BACKEND ORGANIZATION OF STORED DATA - A data units received from a host system are divided and/or redistributed among a plurality of data payloads, wherein boundaries of the data units are not aligned with boundaries of the data payloads. The plurality of data payloads are encoded into a respective plurality of codewords, and the plurality of codewords stored in the flash memory. Boundaries of the codewords are aligned with boundaries of the pages in the flash memory. | 01-31-2013 |
20130031302 | SYSTEMS AND METHODS FOR DETERMINING THE STATUS OF MEMORY LOCATIONS IN A NON-VOLATILE MEMORY - Systems and methods are provided for storing data in a portion of a non-volatile memory (“NVM”) such that the status of the NVM portion can be determined with high probability on a subsequent read. An NVM interface, which may receive write commands to store user data in the NVM, can store a fixed predetermined sequence (“FPS”) with the user data. The FPS may ensure that a successful read operation on a NVM portion is not misinterpreted as a failed read operation or as an erased NVM portion. For example, if the NVM returns an all-zero vector when a read request fails, the FPS can include at least one “1” or one “0”, as appropriate, to differentiate between successful and unsuccessful read operations. In some embodiments, the FPS may also be used to differentiate between disturbed data, which passes an error correction check, and correct data. | 01-31-2013 |
20130031303 | STACKED MEMORY DEVICES, SYSTEMS, AND METHODS - Memory requests for information from a processor are received in an interface device, and the interface device is coupled to a stack including two or more memory devices. The interface device is operated to select a memory device from a number of memory devices including the stack, and to retrieve some or all of the information from the selected memory device for the processor. Additional apparatus, systems and methods are disclosed. | 01-31-2013 |
20130036251 | METHOD AND SYSTEM OF A TIMER BASED BUFFER USED FOR METROLOGY - Described herein are embodiments of methods and systems of using a timer based memory buffer for metrology. One embodiment of the method comprises receiving metrology data from one or more metrology sensors; writing at least part of the metrology data to a volatile memory; incrementing a write pointer to indicate the metrology data contained within the volatile memory; and repeating the above until a timer expires, then reading at least a portion of the metrology data from the volatile memory. | 02-07-2013 |
20130036252 | PRACTICAL CODE LIST CACHE FOR VALUE HELP - Methods and apparatus, including computer program products, are provided for providing value help. In one aspect, there is provided a computer-implemented method. The method may include receiving, at a code list provider, a request from a user interface for code list value help; determining, based on the request, whether to access at least one of a cache and a secondary storage; accessing, by the code list provider, a cache including at least a first code list, the cache implemented in memory, when the determination results in access to the cache; accessing a secondary storage including at least a second code list, when the determination results in access to the secondary storage; and sending, by the code list provider, at least one of the first code list and the second code list to a user interface to enable the user interface to provide code list value help. Related apparatus, systems, methods, and articles are also described. | 02-07-2013 |
20130036253 | WEAR LEVELING FOR A MEMORY DEVICE - Memory devices and methods to facilitate wear leveling operations in a memory device. In one such method, particular blocks of memory cells are excluded from experiencing wear leveling operations performed on the memory device. In at least one method, a user selects blocks of memory to be excluded from wear leveling operations performed on the remainder of blocks of the memory device. Selected blocks of memory are excluded from wear leveling operations responsive to a command initiated by a user identifying, either directly or indirectly, the selected blocks to be excluded. | 02-07-2013 |
20130036254 | DEBUGGING A MEMORY SUBSYSTEM - In one implementation, a memory subsystem includes non-volatile memory, a memory controller that is communicatively connected to the non-volatile memory over a first bus, a host interface through which the memory controller communicates with a host controller over a second bus, and a joint test action group (JTAG) interface that provides the host controller with access to state information associated with the memory controller. The memory subsystem can be configured to be coupled to a board-level memory device that includes the host controller. | 02-07-2013 |
20130036255 | TESTING MEMORY SUBSYSTEM CONNECTIVITY - In one implementation, a memory subsystem includes a plurality of non-volatile memory dies, a memory controller that is communicatively connected to each of the non-volatile memory dies over one or more first busses, a host interface through which the memory controller communicates with a host over a second bus, and a joint test action group (JTAG) interface through which the host performs a boundary scan of the memory subsystem including, at least, the non-volatile memory dies and the memory controller. The memory subsystem can be configured to be a subunit of a board-level memory device that includes the host. | 02-07-2013 |
20130036256 | METHOD AND APPARATUS OF SANITIZING STORAGE DEVICE - Systems and methods directed to erasing data and/or the sanitization of storage systems. In storage systems that utilize storage devices such as Flash Memory Devices or Hard Disk Drives (HDDs), systems and methods utilize the initializing function of the storage device to erase the data. Storage devices within the storage systems may have an initializing function that erases all blocks of the storage device. Systems and methods further check for the initializing function and the media type to determine if the initializing function is available to determine the optimal sanitizing process for the device. | 02-07-2013 |
20130036257 | MEMORY SYSTEM WHICH CAN AVOID UNAVAILABILITY DUE TO OPERATION ERROR BY USER - According to one embodiment, a memory system includes a nonvolatile semiconductor storage device and controller. The nonvolatile semiconductor storage device has a file system area including a file allocation table (FAT), a data write-once area including a plurality of clusters, and a management information area which stores a pointer indicating a rewrite inhibition area of the clusters. The controller reads the FAT from the file system area of the nonvolatile semiconductor storage device, and sets the pointer based on a cluster use status recorded in the FAT. | 02-07-2013 |
20130036258 | MEMORY STORAGE DEVICE, MEMORY CONTROLLER THEREOF, AND METHOD FOR PROGRAMMING DATA THEREOF - A memory storage device, a memory controller thereof, and a method for programming data thereof are provided. The memory storage device includes a buffer memory and a rewritable non-volatile memory chip, wherein the rewritable non-volatile memory chip includes a buffer unit and a plurality of physical blocks. The method includes storing first data received from a host system into the buffer memory, and generating a writing complete message for replying to the host system after the first data stored in the buffer memory is transmitted to the buffer unit by using a first data transmitting command. The method further includes programming the first data to a first physical block of the physical blocks. Meanwhile, if a data program failure is detected, the method also includes programming the first data maintained in the buffer unit to a second physical block by using a second data transmitting command. | 02-07-2013 |
20130036259 | SOLID STATE DRIVE AND DATA STORING METHOD THEREOF - A solid state drive includes a plurality of dies. The dies are divided into first-portion dies and second-portion dies. The first-portion dies are located at a user area. The second-portion dies are located at a reserved area. The solid state drive is in communication with a host. The data storing method of the solid state drive includes the following steps. Firstly, if the host generates a plurality of write data to the solid state drive, the plurality of write data are stored into the reserved area. If there is not accessing action between the host and the solid state drive and if the write data are in the reserved area, the write data are stored into the user area. Afterwards, error correction codes corresponding to the write data in the user area are calculated and stored into the reserved area. | 02-07-2013 |
20130036260 | INFORMATION PROCESSING APPARATUS AND CACHE METHOD - According to one embodiment, an information processing apparatus includes a controller and a cache module. The controller is configured to issue commands for a first storage device and a second storage device, and thereby perform data transmission. The cache module is configured to use the first storage device as a read cache of the second storage device, the cache module withholding issuance of a write command to write cache data in the first storage device to the controller, when commands issued by the controller to the first storage device exceed a preset number, until the issued commands becomes equal to or less than the preset number. | 02-07-2013 |
20130036261 | METHOD FOR OPERATING MEMORY CONTROLLER, AND MEMORY SYSTEM INCLUDING THE SAME - A method for operating a memory controller capable of controlling a maximum count of a read retry operation is disclosed. The method includes programming a first real time clock (RTC) value indicating a time-of-day when a program operation is performed when the program operation for programming a data to a storage region of a non-volatile memory, obtaining information for the storage region by using the first RTC value read from the non-volatile memory and a second RTC value indicating a time-of-day when a read operation is performed, when the read operation for the data programmed to the storage region is performed, and decreasing a maximum count of a read retry operation by using the information, when the read retry operation is performed for the storage region. | 02-07-2013 |
20130036262 | APPARATUS, SYSTEM, AND METHOD FOR TESTING PHYSICAL REGIONS IN A SOLID-STATE STORAGE DEVICE - An apparatus, system, and method are disclosed for testing physical regions in a solid-state storage device. The method includes defining a physical storage region on solid-state storage media of a solid-state storage device. The physical storage region includes a subset of storage capacity of the solid-state storage media. The method includes implementing the physical storage region definition on a storage controller such that memory operations are bounded to the physical storage region. The method includes testing wear of solid-state storage media associated with the physical storage region using memory operations bounded to the physical storage region. | 02-07-2013 |
20130042048 | Techniques to store configuration information in an option read-only memory - Method and apparatus to store configuration information in an option read-only memory are described. | 02-14-2013 |
20130042049 | ENHANCED COPY-ON-WRITE OPERATION FOR SOLID STATE DRIVES - A method for increasing the efficiency of a “copy-on-write” operation performed on an SSD to extend the life of the SSD is disclosed herein. In one embodiment, such a method includes receiving a first logical address specifying a logical location where new data should be written to an SSD. The first logical address maps to a first physical location, storing original data, on the SSD. The method further receives a second logical address specifying a logical location where the original data should be available on the SSD. The second logical address maps to a second physical location on the SSD. To efficiently perform the copy-on-write operation, the method writes the new data to a new physical location on the SSD, maps the first logical address to the new physical location, and maps the second logical address to the first physical location. A corresponding apparatus is also disclosed. | 02-14-2013 |
20130042050 | METHOD AND SYSTEM FOR EFFICIENTLY SWAPPING PIECES INTO AND OUT OF DRAM - A system and method for managing swaps of pieces of an address mapping table is disclosed. The method may include a controller of a storage device receiving a stream of requests for accesses to the mapping table, analyzing the stream of requests to determine at least one characteristic of the stream of requests, and determining whether to copy a piece of the mapping table stored in non-volatile memory into the volatile memory based on the determined at least one characteristic. The system may include a storage device with a controller configured to perform the method noted above. | 02-14-2013 |
20130042051 | PROGRAM METHOD FOR A NON-VOLATILE MEMORY - A program method for a non-volatile memory is disclosed. At least two blocks in the non-volatile memory are configured as 1-bit per cell (1-bpc) blocks. The data of the configured blocks are read and written to a target block in such a way that the data of each said configured block are moved to pages of a same significant bit. In another embodiment, the data of the configured blocks excluding one block are read and written to the excluded block. | 02-14-2013 |
20130042052 | LOGICAL SECTOR MAPPING IN A FLASH STORAGE ARRAY - A system and method for efficiently performing user storage virtualization for data stored in a storage system including a plurality of solid-state storage devices. A data storage subsystem supports multiple mapping tables. Records within a mapping table are arranged in multiple levels. Each level stores pairs of a key value and a pointer value. The levels are sorted by time. New records are inserted in a created newest (youngest) level. No edits are performed in-place. All levels other than the youngest may be read only. The system may further include an overlay table which identifies those keys within the mapping table that are invalid. | 02-14-2013 |
20130042053 | Method and Apparatus for Flexible RAID in SSD - A solid state drive (SSD) employing a redundant array of independent disks (RAID) scheme includes a flash memory chip, erasable blocks in the flash memory chip, and a flash controller. The erasable blocks are configured to store flash memory pages. The flash controller is operably coupled to the flash memory chip. The flash controller is also configured to organize certain of the flash memory pages into a RAID line group and to write RAID line group membership information to each of the flash memory pages in the RAID line group. | 02-14-2013 |
20130042054 | Methods of Managing Meta Data in a Memory System and Memory Systems Using the Same - A method of managing meta data can be provided by generating log entry information including log data in response to changes to meta data that includes a plurality of groups of the meta data. A group of the meta data can be selected from among the plurality of groups of the meta data to provide a selected group of meta data in response to detecting that a number of pieces of the log entry information is equal to or greater than a particular threshold value. The selected group of the meta data and associated log data can be stored in a non-volatile memory device. | 02-14-2013 |
20130042055 | MEMORY SYSTEM INCLUDING KEY-VALUE STORE - According to one embodiment, a memory system including a key-value store containing key-value data as a pair of a key and a value corresponding to the key, includes a first memory, a control circuit and a second memory. The first memory is configured to contain a data area for storing data, and a table area containing the key-value data. The control circuit is configured to perform write and read to the first memory by addressing, and execute a request based on the key-value store. The second memory is configured to store the key-value data in accordance with an instruction from the control circuit. The control circuit performs a set operation by using the key-value data stored in the first memory, and the key-value data stored in the second memory. | 02-14-2013 |
20130042056 | Cache Management Including Solid State Device Virtualization - A method of caching data is performed by a respective computer having one or more processors storing one or more storage management programs for execution by the one or more processors, non-volatile secondary storage and non-volatile cache memory. The method includes receiving from the non-volatile cache memory information identifying an amount of available storage in the non-volatile cache memory, and identifying a size of the management units in the non-volatile cache memory. The method further includes identifying write requests to write data to the non-volatile cache memory, sequentially writing to the non-volatile cache memory the write data for the identified write requests, to sequentially arranged locations in an address space of the non-volatile cache memory, and storing in memory metadata that maps the addresses or storage offsets of the write data to respective locations in the address space of the non-volatile cache memory. | 02-14-2013 |
20130042057 | Hybrid Non-Volatile Memory System - A hybrid non-volatile system uses non-volatile memories based on two or more different non-volatile memory technologies in order to exploit their relative advantages. In an exemplary embodiment, the memory system includes a controller and a flash memory, where the controller has a non-volatile RAM based on an alternate technology such as FeRAM. The flash memory is used for the storage of user data and the non-volatile RAM in the controller is used for system control data. The use of an alternate non-volatile memory technology in the controller allows for a non-volatile copy of the most recent control data to be accessed more quickly as it can be updated on a bit by bit basis. In another exemplary embodiment, the alternate non-volatile memory is used as a cache where data can safely be staged prior to its being written to the memory or read back to the host. | 02-14-2013 |
20130042058 | SOLID STATE MEMORY (SSM), COMPUTER SYSTEM INCLUDING AN SSM, AND METHOD OF OPERATING AN SSM - In one aspect, data is stored in a solid state memory which includes first and second memory layers. A first assessment is executed to determine whether received data is hot data or cold data. Received data which is assessed as hot data during the first assessment is stored in the first memory layer, and received data which is first assessed as cold data during the first assessment is stored in the second memory layer. Further, a second assessment is executed to determine whether the data stored in the first memory layer is hot data or cold data. Data which is then assessed as cold data during the second assessment is migrated from the first memory layer to the second memory layer. | 02-14-2013 |
20130046917 | FLASH MEMORY CONTROLLER - A flash memory controller includes a recording medium and a processing circuit. When the amount of stored data in a flash memory module is less than a first threshold, the processing circuit controls a read and write circuit of the flash memory module to program a target data block using program threshold voltages within a first voltage range so as to write data into the target data block. When the amount of stored data in the flash memory module is greater than a second threshold, the processing circuit controls the read and write circuit to program the target data block using program threshold voltages within a second voltage range so as to write data into the target data block, wherein the second threshold is greater than the first threshold and the first voltage range is less than 50% of the second voltage range. | 02-21-2013 |
20130046918 | METHOD WRITING META DATA WITH REDUCED FREQUENCY - A method of writing meta data in a semiconductor storage device in relation to a maximum number of written meta data pages N. The method stores write data in a buffer and loads meta data in a meta memory, writes the write data to the storage medium and updates the meta data. The updated meta data is stored upon determining a number of written meta data pages in an updated meta data region, and only exceeding the maximum number of written meta data pages N, a meta data write operation is performed. | 02-21-2013 |
20130046919 | NON-VOLATILE MEMORY SYSTEM - In one embodiment, a memory system includes a memory device with a first memory and a second memory, and a controller configured to control storing of data in the memory device. The controller is configured to control an (N− | 02-21-2013 |
20130046920 | NONVOLATILE MEMORY SYSTEM WITH MIGRATION MANAGER - Disclosed is a memory system that includes a nonvolatile memory having a main region and a cache region; and a memory controller having migration manager managing a migration operation that moves data from cache region to the main region by referencing a Most Recently Used/Least Recently Used (MRU/LRU) list. | 02-21-2013 |
20130046921 | METHOD OF CONFIGURING NON-VOLATILE MEMORY FOR A HYBRID DISK DRIVE - A system, method and machine-readable medium are provided to configure a non-volatile memory (NVM) including a plurality of NVM modules, in a system having a hard disk drive (HDD) and an operating system (O/S). In response to a user selection of a hybrid drive mode for the NVM, the plurality of NVM modules are ranked according to speed performance. Boot portions of the O/S are copied to a highly ranked NVM module, or a plurality of highly ranked NVM modules, and the HDD and the highly ranked NVM modules are assigned as a logical hybrid drive of the computer system. Ranking each of the plurality of NVM modules can include carrying out a speed performance test. This approach can provide hybrid disk performance using conventional hardware, or enhance performance of an existing hybrid drive, while taking into account relative performance of available NVM modules. | 02-21-2013 |
20130054870 | NETWORK-CAPABLE RAID CONTROLLER FOR A SEMICONDUCTOR STORAGE DEVICE - Embodiments of the present invention provide a network-capable RAID controller for a storage device of a serial attached small computer system interface/serial advanced technology attachment (PCI-Express) type that supports a low-speed data processing speed for a host. Specifically, embodiments of this invention provide a network-capable RAID controller coupled to one or more (i.e., a set of) semiconductor storage devices (SSDs). Among other components, the network-capable RAID controller comprises an input/output (I/O) controller coupled to a network interface. The network interface allows the network-capable RAID controller to communicate with an external network. | 02-28-2013 |
20130054871 | CONTROLLER WITH EXTENDED STATUS REGISTER AND METHOD OF USE THEREWITH - The embodiments described herein provide a controller with an extended status register and a method of use therewith. In one embodiment, a controller is provided with a first interface through which to communicate with a host and a second interface through which to communicate with a plurality of flash memory devices. The controller also comprises a status register, an extended status register, and a processor. The processor is operative to store, in the extended status register, status information of a plurality of events in time across the plurality of flash memory devices. The extended status register stores event status information, whereas the ONFI status register stores command status information. In response to a request from the host, the processor sends the status information of the plurality of events to the host for analysis. | 02-28-2013 |
20130054872 | DATA STORAGE APPARATUS WITH A HDD AND A REMOVABLE SOLID STATE DEVICE - A data storage apparatus includes a non-volatile hard disk drive platter, a coupling interface for removably receiving a non-volatile solid state device operable as a cache. The data storage apparatus also includes a communication line functionally connected to the hard disk drive platter and the coupling interface and a storage controller are connected to the communication line to control operations of the hard disk drive platter and the solid state device, in which the storage controller is to determine whether the solid state device is coupled to the coupling interface and to modify operations of the hard disk drive platter based upon whether the solid state device is coupled to the coupling interface. | 02-28-2013 |
20130054873 | STORAGE SYSTEM CACHE USING FLASH MEMORY WITH DIRECT BLOCK ACCESS - Embodiments of the invention enable a storage cache, comprising flash memory devices, to have direct block access to the flash such that the physical block addresses are presented to the storage system's cache layer, which thereby controls the storage cache data stream. An aspect of the invention includes a caching storage system. The caching storage system comprises a plurality of flash memory units organized in an array configuration. Each of the plurality of flash memory units includes at least one flash memory device and a flash unit controller. Each flash unit controller provides the caching storage system with direct physical block access to its corresponding at least one flash memory device. The caching storage system further comprises a storage cache controller. The storage cache controller selects physical block address locations (within a flash memory device) to be erased where data are to be written, issues erase commands to a flash unit controller corresponding to the selected physical block address locations, and issues page write operations to a set of erase blocks. | 02-28-2013 |
20130054874 | UPDATING COMPUTER READABLE INSTRUCTIONS ON DEVICES IN A DATA STORAGE FABRIC - Updating computer readable instructions on devices in a data storage fabric is disclosed. A zone manager virtual PHY is established and an active device is granted control over the devices in the data storage fabric. The devices include in-band communication with the zone manager virtual PHY. The zone manager virtual PHY flashes an image of the computer readable instructions over in-band communication to the devices through in-band communication with the active device. | 02-28-2013 |
20130054875 | High Priority Command Queue for Peripheral Component - In an embodiment, a peripheral component may include a low priority command queue configured to store a set of commands to perform a transfer on a peripheral interface and a high priority command queue configured to store a second set of commands to perform a transfer on the interface. The commands in the low priority queue may include indications which identify points at which the set of commands can be interrupted to perform the second set of commands. A control circuit may be coupled to the low priority command queue and may interrupt the processing of the commands from the low priority queue responsive to the indications, and may process commands from the high priority command queue. | 02-28-2013 |
20130054876 | APPARATUSES AND METHODS OF OPERATING FOR MEMORY ENDURANCE - Methods of operating an apparatus such as a computing system and/or memory device for memory endurance are provided. One example method can include receiving m digits of data having a first quantity of digits represented by a first data state that is more detrimental to memory cell wear than a second data state. The m digits of data are encoded into n digits of data having a second quantity of digits represented by the first data state. The value n is greater than the value m. The second quantity is less than or equal to the first quantity. The n digits of data are stored in an apparatus having memory cells. | 02-28-2013 |
20130054877 | DATA WRITING METHOD, MEMORY CONTROLLER AND MEMORY STORAGE APPARATUS - A data writing method and a memory controller and a memory storage apparatus using the same are provided. The method includes selecting physical units as a global random area and building a global random searching table for recording update information corresponding to updated logical pages that data stored in the global random area belongs to. The method also includes receiving updated data belonging to a logical page of a logical unit, assigning an index number for the logical unit, writing the updated data into the global random area, and using the index number to record update information corresponding the logical page in the global random searching table. Accordingly, a global random searching table having smaller size can be used for recording update information corresponding to updated logical pages that data stored in the global random area belongs to. | 02-28-2013 |
20130054878 | SOLID STATE DRIVE AND WEAR-LEVELING CONTROL METHOD THEREOF - A flash memory includes a first block with a first erase count and a second block with a second erase count. A first data corresponding to a first history index number is stored in the first block. A second data corresponding to a second history index number is stored in the second block. A controlling unit is connected with the flash memory, and includes a history index number generator for generating a plurality of history index numbers, which at least comprise the first history index number and the second history index number. According to the first erase count, the first history index number, the second erase count and the second history index number, the controlling unit determines whether a data swapping operation for exchanging the first data and the second data has to be performed or not. | 02-28-2013 |
20130054879 | Data Storage device based on SPI and its controlling method - A data storage device based on SPI includes an SPI circuit, a NAND flash memory for storing data, a NAND flash interface connected between the SPI interface and the NAND flash memory for controlling data transmission therebetween, an instruction controlling circuit connected between the SPI circuit and the NAND flash memory interface for converting an instruction received by the SPI circuit into an instruction recognizable to the NAND flash memory and a data converting circuit connected between the SPI circuit and the NAND flash memory interface for accomplishing conversion between serial data and parallel data. A data storage controlling method based on SPI is also disclosed. Thus a relatively small capacity and a relatively high price of a NOR flash memory based on SPI are avoided and costs are saved. | 02-28-2013 |
20130054880 | SYSTEMS AND METHODS FOR REDUCING A NUMBER OF CLOSE OPERATIONS IN A FLASH MEMORY - The disclosed subject matter includes a memory system with a flash memory and a flash memory controller. The flash memory has a plurality of blocks, where each block is configured to store data. The flash memory controller is configured to maintain a queue having a plurality of slots, where each of the plurality of slots is configured to maintain an identifier of an open block in the flash memory. The controller is also configured to store data to a target block in the flash memory. Furthermore, the controller is configured to remove an identifier of one of the open blocks from the queue and to add an identifier of the target block to the queue. | 02-28-2013 |
20130054881 | ELECTRONIC SYSTEM WITH STORAGE MANAGEMENT MECHANISM AND METHOD OF OPERATION THEREOF - A method of operation of an electronic system includes: forming a superblock by organizing an erase block according to a wear attribute; detecting a trigger count of the wear attribute of the superblock; updating a metadata table with the trigger count; and triggering a recycling event of the superblock based on the metadata table. | 02-28-2013 |
20130054882 | HYBRID HDD STORAGE SYSTEM AND CONTROL METHOD - Disclosed is a storage system which includes a hard disk drive and a nonvolatile memory used as a cache device for the HDD. A connected host is used to manage a data shift between the HDD and nonvolatile memory using a virtual system memory formed by extending a system memory in the host. | 02-28-2013 |
20130060989 | APPARATUS, SYSTEM, AND METHOD FOR REFERENCING DATA BLOCK USAGE INFORMATION BY WAY OF AN INTERFACE - An apparatus, system, and method are disclosed for data management. The method includes referencing data block usage information provided by way of an interface operable to communicate with a storage controller managing non-volatile storage media. The method also includes identifying to the storage controller one or more blocks for deallocation by the data block usage information. | 03-07-2013 |
20130060990 | DATA MOVING METHOD FOR FLASH MEMORY MODULE, AND MEMORY CONTROLLER AND MEMORY STORAGE APPARATUS USING THE SAME - A method of moving a first portion of data and a second portion of data, which belong to one page data and respectively stored in a second physical page and a third physical page, into a first physical page in a flash memory module is provided. The method includes transmitting a read command for reading page data stored in the second physical page; reading the first portion of data from a buffer area of the rewritable non-volatile memory module into a buffer memory; transmitting a read command for reading page data stored in the third physical page; transmitting the first portion of data from the buffer memory to the buffer area; and transmitting a write command for writing data stored in the buffer area into the first physical page. Accordingly, the method can effectively move one page data dispersedly stored in different physical pages into one physical page. | 03-07-2013 |
20130060991 | SOLID STATE DRIVE AND GARBAGE COLLECTION CONTROL METHOD THEREOF - A garbage collection control method for a solid state drive is provided. The garbage collection control method includes the following steps. Firstly, a total number of releasable spaces in a plurality of data-containing blocks of a flash memory is calculated and defined as A. A total number of spaces in a plurality of blank blocks of the flash memory is calculated and defined as B. If the ratio B/A is smaller than a first threshold value, a garbage collection is performed. During the garbage collection is performed, if the ratio B/A is larger than a second threshold value, the garbage collection is ended. The first threshold value is smaller than the second threshold value. | 03-07-2013 |
20130060992 | DATA COMPRESSION METHOD - A data compression method includes; generating compressed data from raw data having a normal size, defining a super page for a memory having a super size greater than the normal size, selecting a compressed data set from among the compressed data having a compression ratio less than a reference compression ratio ranging between 0.5 and 1.0, and storing the compressed data set in the memory using the super page. | 03-07-2013 |
20130060993 | STORAGE DEVICE AND STREAM FILTERING METHOD THEREOF - A storage device may include a main storage part including one or more memories; and a controller configured to control an overall operation of the main storage part. The controller includes a filter manager configured to store data format information and a filtering condition provided from a host; one or more stream filters configured to search and project data stored in the one or more memories in parallel in response to a control of the filter manager to produce searched and projected data; and a merge filter configured to merge the searched and projected data of the one or more stream filters in response to the control of the filter manager. | 03-07-2013 |
20130060994 | NON-VOLATILE MEMORY MANAGEMENT SYSTEM WITH TIME MEASURE MECHANISM AND METHOD OF OPERATION THEREOF - A method of operation of a non-volatile memory management system includes: selecting a specific time period by a unit controller; establishing a first time pool having super blocks written during the specific time period; and promoting to a second time pool, the super blocks from the first time pool, at the lapse of the specific time period. | 03-07-2013 |
20130060995 | MEMORY DEVICE, HOST DEVICE, MEMORY SYSTEM, MEMORY DEVICE CONTROL METHOD, HOST DEVICE CONTROL METHOD AND MEMORY SYSTEM CONTROL METHOD - A memory card | 03-07-2013 |
20130067136 | Administering Thermal Distribution Among Memory Modules Of A Computing System - A computing system includes a number of memory modules and temperature sensors. Each temperature sensor measures a temperature of a memory module. In such a computing system a garbage collector during garbage collection, determines whether a temperature measurement of a temperature sensor indicates that a memory module is overheated and, if a temperature measurement of a temperature sensor indicates a memory module is overheated, the garbage collector reallocates one or more active memory regions on the overheated memory module to a non-overheated memory module. Reallocating the active memory regions includes copying contents of the active memory regions from the overheated memory module to the non-overheated memory module. | 03-14-2013 |
20130067137 | SYSTEMS AND METHODS FOR USING RESERVED SOLID STATE NONVOLATILE MEMORY STORAGE CAPACITY FOR SYSTEM REDUCED POWER STATE - Systems and methods that may be implemented to utilize the same portion of solid state nonvolatile memory for both managing system running data during a system working state and to store previous working state data written from system volatile memory during a low power state when the system volatile memory is depowered. The previous working state information may include data and instructions that may be employed to restore the previous working state of the information handling system prior to entering the low power state and terminating power to the system volatile memory. | 03-14-2013 |
20130067138 | NON-VOLATILE MEMORY-BASED MASS STORAGE DEVICES AND METHODS FOR WRITING DATA THERETO - A non-volatile solid state memory-based mass storage device having at least one non-volatile memory component and methods of operating the storage device. In one aspect of the invention, the one or more memory components define a memory space partitioned into user memory and over-provisioning pools based on a P/E cycle count stored in a block information record. The storage device transfers the P/E cycle count of erased blocks to a host and the host stores the P/E cycle count in a content addressable memory. During a host write to the storage device, the host issues a low P/E cycle count number as a primary address to the content addressable memory, which returns available block addresses of blocks within the over-provisioning pool as a first dimension in a multidimensional address space. Changed files are preferably updated in append mode and the previous version can be maintained for version control. | 03-14-2013 |
20130067139 | STORAGE SYSTEM COMPRISING FLASH MEMORY, AND STORAGE CONTROL METHOD - A storage system comprises a plurality of flash packages comprising a plurality of flash chips, and a storage controller for receiving a first write request from a higher-level apparatus and sending a second write request of write data based on data conforming to this first write request to a write-destination flash package, and demonstrates a capacity virtualization function for causing a storage capacity to appear larger than an actual storage capacity for the higher-level apparatus, and for configuring a storage space using page units. The storage system generates a second VOL (logical volume) based on a first VOL, manages a plurality of VOLs comprising the first VOL and one or more second VOLs generated based on the first VOL as a VOL group, and allocates the same page to areas of the same address of the plurality of VOLs configuring the VOL group. | 03-14-2013 |
20130067140 | DATA MODIFICATION BASED ON MATCHING BIT PATTERNS - A data storage device includes a memory and a controller. The controller is configured to identify groups of bits that match any bit pattern in a first set of bit patterns. Each of the groups of bits includes a first bit of first data, a second bit of second data, and a third bit of third data to be stored at the memory. The controller is configured, in response to determining that a count of the identified groups exceeds a threshold, to change multiple bits of the first data. Changing the multiple bits of the first data reduces a number of the groups of bits that match any bit pattern in the first set of bit patterns. | 03-14-2013 |
20130067141 | DATA WRITING METHOD, AND MEMORY CONTROLLER AND MEMORY STORAGE APPARATUS USING THE SAME - A data writing method for a rewritable non-volatile memory module is provided. The rewritable non-volatile memory module has a plurality of lower physical pages and a plurality of upper physical pages respectively corresponding to the lower physical pages. The method includes determining whether a physical page is one of the upper physical pages before writing first data into the physical page; determining whether a backup area stores second data written into one of the lower physical pages corresponding to the physical page if the physical page is the upper physical page; reading the second data from the lower physical page corresponding to the physical page and backing up the second data into the backup area before writing the first data into the physical page when the backup area does not store the second data. Accordingly, the method may effectively prevent data loss due to a program failure. | 03-14-2013 |
20130067142 | FLASH MEMORY STORAGE DEVICE AND METHOD OF JUDGING PROBLEM STORAGE REGIONS THEREOF - A method of judging problem storage regions adapted for a flash memory storage device includes steps of: sending a writing order to a flash memory chip for writing a written data to an appointed storage paging; when the flash memory chip beginning writing the written data to the appointed storage paging, getting the first time; when the flash memory chip finishing writing the written data to the appointed storage paging, getting the second time; calculating a writing time according to the first time and the second time; if the writing time not coincident with a standard value, then labeling the appointed storage paging as a problem storage region and copying the written data to a backup paging; updating a Mapping Table. | 03-14-2013 |
20130067143 | MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME - According to one embodiment, a memory device includes a nonvolatile memory, a command storage module in which a command is stored, and a controller which receives the command from a host device, stores the command in the command storage module, executes the command stored in the command storage module, and after having completed the execution of the command, transmits, to the host device, a first signal reporting the completion of the execution of the command. | 03-14-2013 |
20130067144 | CONTROLLER FOR STORAGE APPARATUS AND CONTROLLING METHOD FOR STORAGE APPARATUS - According to one embodiment, a controller for a storage apparatus is disclosed having interfaces connectable to a host system, a first storage apparatus and a second storage apparatus. A data in the first storage apparatus and a data in the second storage apparatus are duplicates. A status table stores the operating state regarding the first storage apparatus and the second storage apparatus, wherein the operating state indicates among writing, reading, or standing by. A monitor monitors the interfaces and set up the operating state into the status table. A buffer memory buffers the data for writing in the first storage apparatus and the second storage apparatus. A command response unit receives the data for writing and write-in request from a host system, and directs the writing of the data to the first storage apparatus and the second storage apparatus while making the buffer memory buffer the received data. | 03-14-2013 |
20130067145 | MEMORY DEVICE, MEMORY SYSTEM, AND METHOD OF STORING DATA USING THE SAME - Provided is a memory device configured to store data having a first characteristic and a second characteristic in a memory region optimized to store data having the first characteristic and the second characteristic. The memory device includes a plurality of memory regions and a region determination unit configured to receive data, select a memory region appropriate for storing the received data, and store the data in the selected memory region. Correspondingly, performance degradation of the memory device may be prevented. | 03-14-2013 |
20130067146 | MEMORY DEVICE, CONTROL METHOD FOR THE MEMORY DEVICE, AND CONTROLLER - During normal power operation, an erased free block is prepared in nonvolatile memory so that at least one erased free block is continuously available as a standby block. If a power failure occurs, volatile data and its address conversion information are written into the standby block in the nonvolatile memory. | 03-14-2013 |
20130067147 | STORAGE DEVICE, CONTROLLER, AND READ COMMAND EXECUTING METHOD - A storage device of the embodiment includes memory, a control section, a table holding section for managing a table for holding an identifier, a logical address, and a data length based on a read command, an issuing section for issuing the logical address and the data length for each identifier to the control section, a buffer for holding data received from the memory along with the identifier, and an identifier queue for receiving the identifier of a number proportional to a data length when the data of the logical address of the same identifier is received in the buffer. The storage device of the embodiment includes a transfer section for transferring the data corresponding to the identifier received in the buffer to outside when the identifier is held as incomplete readout in the table in order from the identifier at a head of the identifier queue. | 03-14-2013 |
20130067148 | INFORMATION PROCESSING APPARATUS AND INFORMATION PROCESSING METHOD - An information processing apparatus includes an assignment unit and a determination unit. The assignment unit evaluates physical properties of each of a plurality of semiconductor memories constituting one storage device as a whole and assigns a usage attribute corresponding to an evaluation result to at least a part of the plurality of semiconductor memories. The determination unit determines a semiconductor memory having an optimal usage attribute as a write destination of data with respect to a write command of the data. | 03-14-2013 |
20130067149 | NON-VOLATILE CACHE - A method for managing a storage device including determining whether the storage device includes a non-volatile cache, scanning for a clear cache instruction received from a computing machine, and clearing the non-volatile cache on the storage device in response to authenticating the clear cache instruction. | 03-14-2013 |
20130067150 | DATA PROCESSOR WITH FLASH MEMORY, AND METHOD FOR ACCESSING FLASH MEMORY - A data processor includes a flash memory, a random access memory (RAM), and a controller that creates free space information of the flash memory, creates record data according to each of a read latest data of the flash memory, and stores the free space information and the record data into the RAM. | 03-14-2013 |
20130067151 | METHOD FOR EFFICIENT STORAGE OF METADATA IN FLASH MEMORY - A method includes writing a first portion of received user data to a first page of a block of a memory according to a writing schedule and writing a subsequent portion of the received user data to another page of the block according to the writing schedule. The method includes storing first metadata corresponding to writing the first portion in the memory. The method further includes associating the first metadata with the subsequent portion. | 03-14-2013 |
20130067152 | STORAGE SYSTEM - The temporary area capacity required to be secured with respect to the whole permanent area is calculated in accordance with the capacity and access frequency of a host computer data permanent area of a disk device contained in the storage system and a disk device of an external storage device that is managed by a storage virtualization function of this storage system. The nonvolatile memory is defined as the temporary area and is used to temporarily store host computer data when a data I/O from the host computer is processed. The required capacity of the temporary area is re-calculated in accordance with an event such as a configuration change in the external storage system. | 03-14-2013 |
20130067153 | HARDWARE BASED WEAR LEVELING MECHANISM - A memory system is provided. The system includes a controller that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the controller to regulate read and write access to the one or more FLASH devices. Wear leveling components along with read and write processing components are provided to facilitate efficient operations of the FLASH memory devices. | 03-14-2013 |
20130067154 | ELECTRONIC FLASH MEMORY EXTERNAL STORAGE METHOD AND DEVICE - An electronic flash memory external storage method and device for data processing system includes firmware which directly controls the access of electronic storage media and implements standard interface functions, adopts particular reading and writing formats of the external storage media, receives power via USB, externally stores data by flash memory and access control circuit with the cooperation of the firmware and the driver with the operating system, and has write-protection so that the data can be safely transferred. The method according to present invention is highly efficient and all parts involved are assembled as a monolithic piece so that it has large-capacity with small size and high speed. The device operates in static state and is driven by software. It is plug-and-play and adapted to data processing system. | 03-14-2013 |
20130073783 | HYBRID DATA STORAGE MANAGEMENT TAKING INTO ACCOUNT INPUT/OUTPUT (I/O) PRIORITY - A method uses a record of I/O priorities in a determination of a storage medium of a hybrid storage system in which to store a file. The method maintains the record of I/O priorities by assigning an I/O temperature value to each request for access to the file based upon an I/O priority level of the process making the request. The method marks the file as hot if the file temperature value is greater than a threshold value. The method stores files marked as hot in a lower latency storage medium of the hybrid storage medium. | 03-21-2013 |
20130073784 | METHOD AND SYSTEM FOR RANDOM WRITE UNALIGNMENT HANDLING - A method and system are disclosed for handling host write commands associated with both data aligned with physical page boundaries of parallel write increments in non-volatile storage areas in a non-volatile storage device and data unaligned with the physical page boundaries. The method may include a controller of a storage device identifying the aligned and unaligned portions of received data, temporarily storing the aligned and unaligned portions in different queues, and then writing portions from the unaligned data queue or the aligned data queue in parallel to the non-volatile memory areas when one of the queues has been filled with a threshold amount of data or when the controller detects a timeout condition. The system may include a storage device with a controller configured to perform the method noted above, where the non-volatile memory areas may be separate banks and the queues are random access memory. | 03-21-2013 |
20130073785 | RETENTION MANAGEMENT FOR PHASE CHANGE MEMORY LIFETIME IMPROVEMENT THROUGH APPLICATION AND HARDWARE PROFILE MATCHING - Methods and systems for managing memory and stress to memory systems. A method for managing memory includes receiving from a software application memory retention requirements for application data. The memory retention requirements include storage duration length and/or criticality of data retention. The method also includes storing the application data in one of a plurality of memory regions in non-volatile memory based on the memory retention requirements and memory retention characteristics of the memory regions. Each memory region may have different memory retention characteristics. | 03-21-2013 |
20130073786 | APPARATUS, SYSTEM, AND METHOD FOR IMPROVING READ ENDURANCE FOR A NON-VOLATILE MEMORY - Described are an apparatus, system, and method for improving read endurance for a non-volatile memory (NVM). The method comprises: determining a read count corresponding to a block of NVM; identifying whether the block of NVM is a partially programmed block (PPB); comparing the read count with a first threshold when it is identified that the block is a PPB; and when identified otherwise, comparing the read count with a second threshold, wherein the first threshold is smaller than the second threshold. The method further comprises: identifying a block that is a PPB; determining a first word line corresponding to un-programmed page of the PPB; and sending the first word line to the NVM, wherein the NVM to apply: a first read voltage level to word lines corresponding to the un-programmed pages of the PPB, and a second read voltage level to word lines corresponding to programmed pages of the PPB. | 03-21-2013 |
20130073787 | FASTER TREE FLATTENING FOR A SYSTEM HAVING NON-VOLATILE MEMORY - Systems and methods are disclosed for efficient buffering for a system having non-volatile memory (“NVM”). A tree can be stored in volatile memory that includes a logical-to-physical mapping between a logical space and physical addresses of the NVM. When the amount of memory available for the tree is below a pre-determined threshold, a system can attempt to reduce the number of data fragments in the NVM, and consequently flatten a portion of the tree. The NVM interface may select an optimal set of entries of the tree to combine. Any suitable approach can be used such as, for example, moving one or more sliding windows across the tree, expanding a sliding window when a condition has been satisfied, using a priority queue while scanning the tree, and/or maintaining a priority queue while the tree is being updated. | 03-21-2013 |
20130073788 | WEAVE SEQUENCE COUNTER FOR NON-VOLATILE MEMORY SYSTEMS - Systems and methods are disclosed for providing a weave sequence counter (“WSC”) for non-volatile memory (“NVM”) systems. The WSC can identify the sequence in which each page of the NVM is programmed. The “weave” aspect can refer to the fact that multiple blocks can be open for programming at once, thus allowing the pages of these blocks to be programmed in a “woven” manner. Systems and methods are also disclosed for providing a host weave sequence counter (“HWSC”). Each time new data is initially programmed to the NVM, this data can be associated with a particular HWSC. The HWSC associated with the data may not change, even when the data is moved to a new page (e.g., for wear leveling purposes and the like). The WSC and HWSC may aid in, for example, performing rollback, building logical-to-physical mappings, determining static-versus-dynamic page statuses, and performing maintenance operations (e.g., wear leveling). | 03-21-2013 |
20130073789 | SYSTEMS AND METHODS FOR CONFIGURING NON-VOLATILE MEMORY - Systems and methods are disclosed for configuring a non-volatile memory (“NVM”). In some embodiments, each block of the NVM can include a block table-of-contents (“TOC”), which can be encoded (e.g., run-length encoded) and dynamically-sized. Thus, as user data is being programmed to a block, the size of a block TOC can be concurrently recalculated and increased only if necessary. In some embodiments, the NVM interface can use a weave sequence stored in the context information and at least one weave sequence associated with each page of a block to determine whether to replay across the pages of the block after system boot-up. | 03-21-2013 |
20130073790 | MAGNETIC RANDOM ACCESS MEMORY WITH BURST ACCESS - A memory device which includes a magnetic memory unit for storing a burst of data during burst write operations, each burst of data includes, sequential data units with each data unit being received at a clock cycle, and written during a burst write operation, wherein the burst write operation is performed during multiple clock cycles. Further, the memory device includes a mask register coupled to the magnetic memory unit that generates a write mask during the burst write operation to inhibit or enable write of the data units of the burst of data, the memory device allowing a next burst write or read command to begin before the completion of the burst write operation and while receiving data units of the next burst of data to be written or providing read data. | 03-21-2013 |
20130073791 | MAGNETIC RANDOM ACCESS MEMORY WITH DYNAMIC RANDOM ACCESS MEMORY (DRAM)-LIKE INTERFACE - A memory device includes a magnetic memory unit for storing a burst of data during burst write operations, each burst of data includes, sequential data units with each data unit being received at a clock cycle, and written during a burst write operation, wherein the burst write operation is performed during multiple clock cycles. Further, the memory device includes a mask register coupled to the magnetic memory unit that generates a write mask during the burst write operation to inhibit or enable data units of write data, furthermore the memory device allowing burst write operation to begin while receiving data units of the next burst of data to be written or providing read data. | 03-21-2013 |
20130073792 | ELECTRONIC APPARATUS USING NAND FLASH AND MEMORY MANAGEMENT METHOD THEREOF - An electronic apparatus using NAND flash memory and a memory management method thereof are provided. The electronic apparatus uses the NAND flash memory to record data in the system memory. In the present method, when a standby instruction is received, a fast flash standby (FFS) procedure is initiated, and a state of the NAND flash memory is checked to determine whether the NAND flash memory is suitable for recording the data in the system memory. If the state is determined as suitable for recording the data, the data in the system memory is copied to the NAND flash and the operating system of the electronic apparatus is controlled to enter a hibernate mode. On the contrary, if the state is determined as not suitable for recording the data, the operating system of the electronic apparatus is controlled to enter a standby mode. | 03-21-2013 |
20130073793 | MEMORY DEVICE - According to one embodiment, a memory device includes a nonvolatile memory which stores data in units of a write unit includes cells, and a controller which controls the memory and partitions memory space of the memory. In response to a request to write write-data to the memory from a host, the controller requests the host to transmit a segment of the write-data with a specified size. The write-data segment has a size of an integral multiple of a size determined to allow for a set of the write-data segment and corresponding additional data to be the largest while smaller than the write unit. Before completion of processing a first command which requests access to a first partition, the controller accepts a second command which requests access to a second partition. | 03-21-2013 |
20130073794 | MEMORY SYSTEM AND CONTROL METHOD THEREOF - According to one embodiment, a memory system includes a storage unit including a buffer and a nonvolatile first memory, and a first controller which includes a processor and a volatile second memory, and in which the processor controls the storage unit based on data stored in the second memory, and issues a first command when switching from a normal state to a standby state. The memory system also includes a second controller which issues a second command for reading data from the first memory to the buffer, based on the first command, and issues a third command for reading the data from the buffer and storing the data in the second memory, when the first controller switches from the standby state to the normal state. | 03-21-2013 |
20130073795 | MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME - According to one embodiment, a memory device includes a nonvolatile memory in which data write or data read is executed in units of a plurality of cells, and a controller configured to control the memory and to manage a memory space of the memory by dividing the memory space into a plurality of partitions. | 03-21-2013 |
20130073796 | MEMORY CONTROLLER - According to one embodiment, a memory controller includes a first interface, a second interface, and a control module. The first interface transmits and receives a signal to and from a host. The second interface transmits and receives a signal to and from a nonvolatile semiconductor memory. The control module reserves a spare area in the semiconductor memory in response to a first command received by the first interface and writes update data into the spare area when updating data in the semiconductor memory. Size of the spare area is available according to the first command. | 03-21-2013 |
20130073797 | MEMORY DEVICE - According to one embodiment, a memory device includes a nonvolatile memory and a command storage module in which a command is stored. The memory device further comprises a memory module in which a type of a background process and an order of priority of the background process are set, in which information of a necessary background process is set, and in which permission or refusal of the background process is set by a host device. | 03-21-2013 |
20130073798 | FLASH MEMORY DEVICE AND DATA MANAGEMENT METHOD - Disclosed is a data management method for a flash storage device. The method includes collecting cold data stored in the flash memory device with reference to a cold list table, compressing the collected cold data, and then storing the compressed cold data in the flash memory. | 03-21-2013 |
20130073799 | Electronic Control Unit for Vehicle and Method of Writing Data - An electronic control unit for a vehicle including a nonvolatile memory capable of erasing and writing data electrically and two buffers to acquire, by communication, divided data obtained by dividing a program by predetermined size. Then, in parallel with using the two buffers alternately to receive divided data, the electronic control unit for a vehicle uses one buffer that is not used to receive divided data to write the received divided data into the nonvolatile memory. | 03-21-2013 |
20130073800 | Multipage Preparation Commands For Non-Volatile Memory Systems - Multipage preparation commands for non-volatile memory systems are disclosed. The multipage preparation commands supply data that can be used to prepare a non-volatile memory device for forthcoming multipage program operations. A host controller can use the commands ahead of a multipage program operation to optimize usage of a multipage program command. The non-volatile memory device can use the commands to configure the non-volatile memory in preparation for a subsequent operation, such as changing a command order or using the most optimized command set for the subsequent operation. | 03-21-2013 |
20130073801 | TECHNIQUES TO STORE CONFIGURATION INFORMATION IN AN OPTION READ-ONLY MEMORY - Method and apparatus to store configuration information in an option read-only memory are described. | 03-21-2013 |
20130080682 | RECLAIMING SPACE OCCUPIED BY AN EXPIRED VARIABLE RECORD IN A NON-VOLATILE RECORD STORAGE - In a method for reclaiming space occupied by an expired variable record in a non-volatile record storage, a reclaim state data that includes a state of a reclaim operation is maintained. In addition, the state of the reclaim operation is marked to indicate a progress of the reclaim operation at a plurality of stages of the reclaim operation. The reclaim operation is implemented by sliding, one section at a time, the data in a first direction along the plurality of sections and by sliding, one section at a time, the variable records, excluding the expired variable record, in a second direction along the plurality of sections, to thereby remove the expired variable record. | 03-28-2013 |
20130080683 | MEMORY SYSTEM PROVIDED WITH NAND FLASH MEMORY AND METHOD OF CONTROLLING THE SAME - According to one embodiment, a memory system includes first, and second districts, and control section. Each of the first and second districts includes a memory cell array. The control section receives a write command to simultaneously write first data to the first, and second districts, and addresses, and simultaneously writes the first data to the first and second districts. | 03-28-2013 |
20130080684 | ADAPTER HAVING HIGH SPEED STORAGE DEVICE - An adapter, providing a selective connection between a host and mass storage device, includes a high-speed storage device, a host interface and a device interface. The high-speed storage device is provided on a front surface of a printed circuit board (PCB), and includes multiple nonvolatile memory devices and a controller configured to control operations of the nonvolatile memory devices. The host interface is on a back surface of the PCB, and is configured to interface between the high-speed storage device and the host. The device interface is on the back surface of the PCB, and is configured to interface between the high-speed storage device and the mass storage device. | 03-28-2013 |
20130080685 | STORAGE DEVICES AND METHODS OF DRIVING STORAGE DEVICES - A storage device includes a data storage having first and second storage areas corresponding to different physical addresses. First data are stored in the first storage area. The storage device further includes a first memory that stores a reference count associated with the first data, and a controller that rearranges the first data from the first storage area to the second storage area in response to a change in the reference count of the first data. | 03-28-2013 |
20130080686 | DATA MANAGEMENT METHOD FOR NONVOLATILE MEMORY - A method of managing data in a system comprising a nonvolatile memory comprises storing a root object of application data, and at least one sub object referenced by the root object in the nonvolatile memory, and mapping virtual addresses of the root object and sub object to physical addresses of the nonvolatile memory respectively, in a page unit. The root object stored in the nonvolatile memory comprises a pointer that references the sub object stored in the nonvolatile memory. | 03-28-2013 |
20130080687 | SOLID STATE DISK EMPLOYING FLASH AND MAGNETIC RANDOM ACCESS MEMORY (MRAM) - A central processing unit (CPU) subsystem is disclosed to include a MRAM used among other things for storing tables used for flash block management. In one embodiment all flash management tables are in MRAM and in an alternate embodiment tables are maintained in DRAM and are near periodically saved in flash and the parts of the tables that are updated since last save are additionally maintained in MRAM. | 03-28-2013 |
20130080688 | DATA STORAGE DEVICE AND METHOD OF WRITING DATA IN THE SAME - A method is provided for writing data in a storage device, including a nonvolatile memory. The method includes receiving a pre-write command including a logical address and size information of write data, performing a pre-operation for optimization of a write operation based on the pre-write command, and writing the write data in the nonvolatile memory after the pre-operation is completed. | 03-28-2013 |
20130080689 | DATA STORAGE DEVICE AND RELATED DATA MANAGEMENT METHOD - A storage device performs data management for a nonvolatile memory device by detecting an allocation order of a first memory block, assigning page data of the first memory block to a second memory block or a third memory block having different erase counts based on the allocation order. | 03-28-2013 |
20130080690 | METHOD TO EMULATE EEPROM USING FLASH MEMORY - Methods of using FLASH memory to emulate EEROM are disclosed. The present method uses two pages of FLASH memory, where each page is one or more separately erasable blocks. One page is referred to as the current page, while the other is the next page. Tokens, which are data structures containing a data element, are written in successive locations in the current page. When the current page is nearly completely filled, the write operation starts writing the new tokens to the next page. In some embodiments, to equalize the execution time of the write routine, the write routine also copies one token from the current page to the next page after a new token is written to the next page. Once all tokens have been copied to the next page, the current page can be erased. At this point, the next page becomes the current page. | 03-28-2013 |
20130080691 | FLASH MEMORY DEVICE WITH PHYSICAL CELL VALUE DETERIORATION ACCOMMODATION AND METHODS USEFUL IN CONJUNCTION THEREWITH - A method for converting a measured physical level of a cell into a logical value, in an array of memory cells storing physical levels which diminish over time, the method may include: determining extent of deterioration of the physical levels and determining thresholds accordingly for at least an individual cell in the array; and reading the individual cell including reading a physical level in said cell and converting said physical level into a logical value using at least some of said thresholds, wherein said determining extent of deterioration comprises storing predefined physical levels rather than data-determined physical levels in each of a plurality of cells and determining extent of deterioration by computing deterioration of said predefined physical levels. | 03-28-2013 |
20130080692 | CONTENT-AWARE DIGITAL MEDIA STORAGE DEVICE AND METHODS OF USING THE SAME - A content-aware digital media storage device includes a host device interface for exchanging digital information with a host device, a memory array for storing digital information received from the host device via the host interface, a peripheral module configured to communicate the digital information stored in the memory array to a receiver located remote from the digital media storage device, and a controller communicatively coupled to the host device interface, the memory array and the peripheral module and configured to interpret directory information associated with the digital information stored in the memory array so as to selectively access said digital information and communicate such accessed digital information to the peripheral module for transmission to the remote receiver. Digital images stored in the memory array may be transmitted to a remote host via a wireless network access point with which the peripheral module of the storage device is associated. | 03-28-2013 |
20130086301 | Direct Memory Address for Solid-State Drives - A storage device is provided for direct memory access. A controller of the storage device performs a mapping of a window of memory addresses to a logical block addressing (LBA) range of the storage device. Responsive to receiving from a host a write request specifying a write address within the window of memory addresses, the controller initializes a first memory butler in the storage device and associates the first memory buffer with a first address range within the window of memory addresses such that the write address of the request is within the first address range. The controller writes to the first memory buffer based on the write address. Responsive to the buffer being full, the controller persists contents of the first memory buffer to the storage device using logical block addressing based on the mapping. | 04-04-2013 |
20130086302 | Enabling Throttling on Average Write Throughput for Solid State Storage Devices - A mechanism is provided for enabling throttling on average write throughput instead of peak write throughput for solid-state storage devices. The mechanism assures an average write throughput within a range but allows excursions of high throughput with periods of low throughput offsetting against those of heavy usage. The mechanism periodically determines average throughput and determines whether average throughput exceeds a high throughput threshold for a certain amount of time without being offset by periods of low throughput. | 04-04-2013 |
20130086303 | APPARATUS, SYSTEM, AND METHOD FOR A PERSISTENT OBJECT STORE - An apparatus, system, and method are disclosed for persistently storing data objects. An object store index module maintains an object store. The object store associates each data object of a plurality of data objects with a unique key value. A storage module persists object store data defining the object store to a logical block address of the solid-state storage device in response to an update event. The logical block address is a member of a restricted set of logical block addresses. The logical block address is mapped to a location of the object store data on the solid-state storage device. A read module provides a requested data object from the plurality of data objects to a requesting client in response to receiving a read request for the requested data object from the requesting client. The read request comprises the key value associated with the requested data object. | 04-04-2013 |
20130086304 | STORAGE SYSTEM COMPRISING NONVOLATILE SEMICONDUCTOR STORAGE MEDIA - Logical-physical translation information comprises information denoting the corresponding relationships between multiple logical pages and multiple logical chunks forming a logical address space of a nonvolatile semiconductor storage medium, and information denoting the corresponding relationships between the multiple logical chunks and multiple physical storage areas. Each logical page is a logical storage area conforming to a logical address range. Each logical chunk is allocated to two or more logical pages of multiple logical pages. Two or more physical storage areas of multiple physical storage areas are allocated to each logical chunk. A controller adjusts the number of physical storage areas to be allocated to each logical chunk. | 04-04-2013 |
20130086305 | NONVOLATILE SEMICONDUCTOR STORAGE SYSTEM - A nonvolatile semiconductor storage system has multiple nonvolatile semiconductor storage media, a control circuit having a media interface group (one or more interface devices) coupled to the multiple nonvolatile semiconductor storage media, and multiple switches. The media interface group and the multiple switches are coupled via data buses, and each switch and each of two or more nonvolatile chips are coupled via a data bus. The switch is configured so as to switch a coupling between a data bus coupled to the media interface group and a data bus coupled to any of multiple nonvolatile chips that are coupled to this switch. The control circuit partitions write-target data into multiple data elements, switches a coupling by controlling the multiple switches, and distributively sends the multiple data elements to multiple nonvolatile chips. | 04-04-2013 |
20130086306 | INFORMATION PROCESSOR AND MEMORY MANAGEMENT METHOD - According to one embodiment, an information processor includes: a controller, a volatile storage module, a non-volatile storage module, and a reader. The volatile storage module is configured to be allocated with a storage area which can be accessed by the controller. The non-volatile storage module is configured to save data stored in the storage area of the volatile storage module at transition to a power-off state. The reader is configured to read, if a state just prior to the transition to the power-off state is to be recovered, the data stored in the non-volatile storage module by each page, and to load the read data to the storage area in the volatile storage module. The page is configured by a plurality of memory cells. | 04-04-2013 |
20130086307 | INFORMATION PROCESSING APPARATUS, HYBRID STORAGE APPARATUS, AND CACHE METHOD - According to one embodiment, an information processing apparatus includes a determination module and a cache module. The determination module is configured to determine whether an access request from a host to the hard disk drive is a request for accessing a preset number of or more consecutive sectors in a hard disk drive. The cache module is configured to use a storage apparatus as a cache for the hard disk drive, and the cache module is configured not to use the storage apparatus as the cache when it is determined that the access request is the request for accessing the preset number of or more consecutive sectors. | 04-04-2013 |
20130086308 | STORAGE DEVICE AND METHOD OF ACCESSING COPY DESTINATION DATA - A storage device copies copy source data stored in a copy source volume to a copy destination volume and manages copied data in units of generations. The storage device includes a first storing unit, a second storing unit, and a processor. The first storing unit stores information representing presence/no-presence of a copy in association with a logical address of the copy destination volume in units of generations. The second storing unit stores a physical address of the copy destination volume in units of generations. The processor determines, when receiving an access request for a copy destination volume, presence/non-presence of a copy of a logical address for which the access request is made by using information in the first storing unit, and to access a physical address of the copy destination volume acquired from the second storing unit for a generation designated by a result of the determination. | 04-04-2013 |
20130086309 | FLASH-DRAM HYBRID MEMORY MODULE - A memory module that is couplable to a memory controller hub (MCH) of a host system includes a non-volatile memory subsystem, a data manager coupled to the non-volatile memory subsystem, a volatile memory subsystem coupled to the data manager and operable to exchange data with the non-volatile memory subsystem by way of the data manager, and a controller operable to receive read/write commands from the MCH and to direct transfer of data between any two or more of the MCH, the volatile memory subsystem, and the non-volatile memory subsystem based on the commands. | 04-04-2013 |
20130086310 | NON-TRANSITORY STORAGE MEDIUM ENCODED WITH COMPUTER READABLE PROGRAM, INFORMATION PROCESSING SYSTEM, INFORMATION PROCESSING APPARATUS, AND INFORMATION PROCESSING METHOD - An exemplary embodiment provides a non-transitory storage medium encoded with a computer readable program executable by the computer, for writing data in a semiconductor storage device capable of storing a plurality of bits in one memory cell. The program causes the computer to perform an allocation step of allocating a first area for storing first data in a storage area of a semiconductor storage device and a writing step of writing the first data only in an area of use, with a prescribed size from a boundary of the first area being defined as a protection area and a remaining area being defined as the area of use in response to a request for writing the first data. | 04-04-2013 |
20130086311 | METHOD OF DIRECT CONNECTING AHCI OR NVMe BASED SSD SYSTEM TO COMPUTER SYSTEM MEMORY BUS - A SSD system directly connected to the system memory bus includes at least one system memory bus interface unit, one storage controller with associated data buffer/cache, one data interconnect unit, one nonvolatile memory (NVM) module, and flexible association between storage commands and the NVM module. A logical device interface, the Advanced Host Controller Interface (AHCI) or NVM Express (NVMe), is used for the SSD system programming. The SSD system appears to the computer system physically as a dual-inline-memory module (DIMM) attached to the system memory controller, and logically as an AHCI device or an NVMe device. The SSD system may sit in a DIMM socket and scaling with the number of DIMM sockets available to the SSD applications. The invention moves the SSD system from I/O domain to the system memory domain. | 04-04-2013 |
20130086312 | Semiconductor Device - An object of the present invention is to realize a highly reliable long-life information processor capable of high-speed operation and easy to handle. The processor includes a semiconductor device comprising a nonvolatile memory device including a plurality of overwritable memory cells, and a control circuit device for controlling access to the nonvolatile memory device. The control circuit device sets assignments of second addresses to the nonvolatile memory device independently of first addresses externally supplied, such that the physical disposition of part of the memory cells used for writing of first data to be written externally supplied is one of the first to (N+1)th of every (N+1) memory cells (N: a natural number) at least in one direction. | 04-04-2013 |
20130086313 | METHODS TO SECURELY BIND AN ENCRYPTION KEY TO A STORAGE DEVICE - Embodiments of methods to securely bind a disk cache encryption key to a cache device are generally described herein. Other embodiments may be described and claimed. | 04-04-2013 |
20130086314 | STORAGE SYSTEM, STORAGE DEVICE, AND CONTROL METHOD THEREOF - A storage system including a storage device which includes media for storing data from a host computer, a medium controller for controlling the media, a plurality of channel controllers for connecting to the host computer through a channel and a cache memory for temporarily storing data from the host computer, wherein the media have a restriction on a number of writing times. The storage device includes a bus for directly transferring data from the medium controller to the channel controller. | 04-04-2013 |
20130091319 | CROSS-BOUNDARY HYBRID AND DYNAMIC STORAGE AND MEMORY CONTEXT-AWARE CACHE SYSTEM - Embodiments of the present invention provide an adaptive cache system and an adaptive cache system for a hybrid storage system. Specifically, in a typical embodiment, an input/out (I/O) traffic analysis component is provided for monitoring data traffic and providing a traffic analysis based thereon. An adaptive cache algorithm component is coupled to the I/O traffic analysis component for applying a set of algorithms to determine a storage schema for handling the data traffic. Further, an adaptive cache policy component is coupled to the adaptive cache algorithm component. | 04-11-2013 |
20130091320 | STORAGE SYSTEM AND STORAGE METHOD - A storage system comprises a storage comprising a nonvolatile storage medium, and a storage control apparatus for inputting/outputting data to/from the storage. The storage control apparatus comprises a memory for storing management information, which is information used in inputting/outputting data to/from the storage, and a control part for controlling access to the storage. The control part stores the management information, which is stored in the memory, in the storage as a base image, and when the management information is updated subsequent to the base image being stored in the storage, creates a journal comprising information related to this update, and stores the journal in the storage as a journal group which is configured from multiple journals. | 04-11-2013 |
20130091321 | METHOD AND APPARATUS FOR UTILIZING NAND FLASH IN A MEMORY SYSTEM HIERARCHY - In one embodiment, a method includes obtaining a request for data, determining if the data is present in a physical memory, and obtaining the data from a non-volatile random access memory if it is determined that the data is not present in the physical memory. The request is obtained by an overall system that includes the physical memory and the non-volatile random access memory, and the overall system is configured to push information from the physical memory to the non-volatile random access memory. | 04-11-2013 |
20130091322 | Electronic System and Memory Managing Method Thereof - A memory managing method for an electronic system is provided. The electronic system includes an auxiliary memory, and is capable of communicating with a flash memory including a plurality of blocks. Each of the blocks has a logical/physical address mapping relationship. The address mapping relationships are stored in a storage region in the flash memory. The memory managing method first determines whether the address mapping relationships stored in the storage region are correct. The address mapping relationships are copied from the storage region to the auxiliary memory when a determination result is affirmative. | 04-11-2013 |
20130091323 | IN-VEHICLE APPARATUS - An in-vehicle apparatus includes: a flash memory; a memory controller for executing an initialization process; a backup power source; a power source; a controller; and a power source controller. According to incompletion of initialization, the controller executes standby/boot process. According to completion of initialization, the controller executes the boot process. According to reception of data backup instruction, the controller stores data in the memory. The power source controller switches to a trigger standby mode. According to trigger, the power source controller inputs the energization instruction to the power source. According to termination of trigger, the power source controller inputs the data backup instruction to the controller. According to completion of backup, the power source controller halts to input the energization instruction, and switches to the trigger standby mode. According to incompletion of backup, the power source controller resets the switch and the power source. | 04-11-2013 |
20130097361 | MEMORY DEVICE - A memory device includes a control part and a storage part. The control part includes a first interface, a second interface, and a storage controller. The first interface is connected to an electronic device through a first bus. The second interface is connected to the storage controller through a second bus. The storage part includes a third interface and a storage unit. The storage unit is connected to the third interface through a third bus. The control part and the storage part are connected through a connection of the second interface and the third interface. | 04-18-2013 |
20130097362 | DATA WRITING METHOD, AND MEMORY CONTROLLER AND MEMORY STORAGE APPARATUS USING THE SAME - A data writing method, a memory controller using the method, and a memory storage apparatus using the method are provided. The method includes selecting a physical block as a reserved physical block for a plurality of updated physical blocks. The method also includes, when a host system is about to write updated data into a logical page belonging to a logical block and a physical page, which corresponds to the logical page, of a substitute physical block, which corresponds to an updated physical block mapped to the logical block, has stored data, independently assigning the reserved physical block to the updated physical block mapped to the logical block and writing the updated data into the reserved physical block. Accordingly, the method can complete data writing without performing a data merge operation, thereby shortening the time for performing a write command. | 04-18-2013 |
20130097363 | MEMORY CONTROL DEVICE - A memory control device for controlling a primary controller and a secondary controller to access a flash memory is provided. A bus switch is coupled to the primary controller, the secondary controller and the flash memory via a first, second and third serial peripheral interface (SPI) buses, respectively. A selecting unit selectively couples the third SPI bus to one of the first and second buses. When the bus switch receives an access request from the primary controller via the first SPI bus, the selecting unit couples the third SPI bus to the first SPI bus, so as to transmit a chip select signal, a clock signal and a master output slave input (MOSI) signal from the primary controller to the flash memory for accessing the flash memory. The first access request is provided by the first chip select signal. | 04-18-2013 |
20130097364 | NONVOLATILE MEMORY DEVICE AND RELATED METHOD OF OPERATION - A method of operating a nonvolatile memory device comprises defining a bit ordering for a plurality of n-bit (n>2) multi-level cells such that bit-reading numbers associated with different pages of the n-bit multi-level cells are substantially equalized, wherein the bit ordering assigns at least one bit “0” to an erased state of the n-bit multi-level cells, and programming n-bit data into each of the n-bit multi-level cells according to the bit ordering. | 04-18-2013 |
20130097365 | REDUCING A NUMBER OF CLOSE OPERATIONS ON OPEN BLOCKS IN A FLASH MEMORY - The disclosed subject matter includes a memory system with a flash memory and a flash memory controller. The flash memory controller is configured to divide the flash memory into virtual segments, each segment including blocks of flash memory cells. The controller is also configured to receive a write request to a location designated by a memory identifier and to map the memory identifier to a segment. When the segment matches an open segment and an open block can store the data, the controller is configured to retrieve the open segment and the open block from a collection tracking open blocks and to write the data to the open block. When the segment is different from the open segment, the controller is configured to close the open block, to write the data to a block in the segment, and to update the collection with the block in the segment. | 04-18-2013 |
20130097366 | STORAGE DEVICE AND USER DEVICE USING THE SAME - Provided are a storage device and a user device used by connecting to the user device. The storage device may include a nonvolatile memory and a control unit configured to control the nonvolatile memory. When write data is received from the host, the control unit outputs a first response signal including information indicating whether the write data is successfully received. When the write data is stored in the nonvolatile memory, the control unit outputs a second response signal including on whether the write data is successfully stored in the nonvolatile memory. Since the storage device does not require a program backup memory, it may be implemented in a small area. | 04-18-2013 |
20130097367 | APPARATUS, SYSTEM, AND METHOD FOR SOLID-STATE STORAGE AS CACHE FOR HIGH-CAPACITY, NON-VOLATILE STORAGE - An apparatus, system, and method are disclosed for solid-state storage as cache for high-capacity, non-volatile storage. The apparatus, system, and method are provided with a plurality of modules including a cache front-end module and a cache back-end module. The cache front-end module manages data transfers associated with a storage request. The data transfers between a requesting device and solid-state storage function as cache for one or more HCNV storage devices, and the data transfers may include one or more of data, metadata, and metadata indexes. The solid-state storage may include an array of non-volatile, solid-state data storage elements. The cache back-end module manages data transfers between the solid-state storage and the one or more HCNV storage devices. | 04-18-2013 |
20130097368 | AD HOC Flash Memory Reference Cells - A method for managing a flash memory that includes a plurality of primary cells and a plurality of spare cells includes interrogating the flash memory to determine which spare cells have been used to replace respective primary cells and using at least a portion of a remainder of the spare cells as reference cells. | 04-18-2013 |
20130097369 | APPARATUS, SYSTEM, AND METHOD FOR AUTO-COMMIT MEMORY MANAGEMENT - An apparatus, system, and method are disclosed for auto-commit memory management. The method includes receiving an auto-commit request from a client, such as a barrier request or a checkpoint request. The auto-commit request is associated with an auto-commit buffer of a non-volatile recording device. The method includes issuing a serializing instruction that flushes data from a processor complex to the auto-commit buffer. The method includes determining completion of the serializing instruction flushing the data to the auto-commit buffer. | 04-18-2013 |
20130097370 | FABRICATING AND OPERATING A MEMORY ARRAY HAVING A MULTI-LEVEL CELL REGION AND A SINGLE-LEVEL CELL REGION - Techniques are disclosed herein for applying different process steps to single-level cell (SLC) blocks in a memory array than to multi-level cell (MLC) blocks such that the SLC blocks will have high endurance and the MLC blocks will have high reliability. In some aspects, different doping is used in the MLC blocks than the SLC blocks. In some aspects, different isolation is used in the MLC blocks than the SLC blocks. Techniques are disclosed that apply different read parameters depending on how many times a block has been programmed/erased. Therefore, blocks that have been cycled many times are read using different parameters than blocks that have been cycled fewer times. | 04-18-2013 |
20130103886 | DUAL-FIRMWARE FOR NEXT GENERATION EMULATION - Disclosed is a host bus adapter (HBA) that to receives an input/output (I/O) command from an operating system I/O driver. Firmware stored on the host bus adapter includes primary firmware and secondary firmware to process the I/O command. The HBA is to respond to the I/O command under the control of one of the primary firmware or secondary firmware. The selected one of said primary firmware and secondary firmware may be used to certify a hardware driver for either the current generation (primary firmware) or a future generation (secondary firmware). | 04-25-2013 |
20130103887 | COMPUTING SYSTEM WITH NON-DISRUPTIVE FAST MEMORY RESTORE MECHANISM AND METHOD OF OPERATION THEREOF - A method for operating a computing system includes: monitoring a central interface for a power event; accessing a high-speed memory for pre-shutdown data; accessing a non-volatile memory during the power event for the pre-shutdown data previously stored on the high-speed memory; selecting a multiplexer for allowing external access to the high-speed memory; and formatting the pre-shutdown data in the non-volatile memory for access through a non-disruptive interface. | 04-25-2013 |
20130103888 | MEMORY ARRAY INCLUDING MULTI-STATE MEMORY DEVICES - A data storage system including a memory array including a plurality of memory devices programmable in greater than two states. A memory control module may control operations of the memory array, and an encoder module may encode input data for storing to the memory array. The memory array may be an m×n memory array, and the memory control module may control operations of storing data to and retrieving data from the memory array. | 04-25-2013 |
20130103889 | PAGE-BUFFER MANAGEMENT OF NON-VOLATILE MEMORY-BASED MASS STORAGE DEVICES - Mass storage devices and methods that use at least one non-volatile solid-state memory device, for example, one or more NAND flash memory devices, that defines a memory space for permanent storage of data. The mass storage device is adapted to be operatively connected to a host computer system having an operating system and a file system. The memory device includes memory cells organized in pages that are organized into memory blocks for storing data, and a page buffer partitioned into segments corresponding to a cluster size of the operating system or the file system of the host computer system. The size of a segment of the page buffer is larger than the size of any page of the memory device. The page buffer enables logically reordering multiple clusters of data fetched into the segments from pages of memory device and write-combining segments containing valid clusters. | 04-25-2013 |
20130103890 | CALIBRATING MEMORY - Apparatuses and methods of calibrating a memory interface are described. Calibrating a memory interface can include loading and outputting units of a first data pattern into and from at least a portion of a register to generate a first read capture window. Units of a second data pattern can be loaded into and output from at least the portion of the register to generate a second read capture window. One of the first read capture window and the second read capture window can be selected and a data capture point for the memory interface can be calibrated according to the selected read capture window. | 04-25-2013 |
20130103891 | ENDURANCE ENHANCEMENT CODING OF COMPRESSIBLE DATA IN FLASH MEMORIES - Methods described in the present disclosure may be based on a direct transformation of original data to “shaped” data. The disclosed methods may be performed “on-the-fly” and the disclosed methods may utilize an inherent redundancy in compressible data in order to achieve endurance enhancement and error reduction. In a particular example, a method comprises generating a first portion of output data by applying a mapping of input bit sequences to output bit sequences to a first portion of input data, updating the mapping of the input bit sequences to the output bit sequences based on the first portion of the input data to generate an updated mapping, reading a second portion of the input data, and generating a second portion of the output data by applying the updated mapping of the input bit sequences to the output bit sequences to the second portion of the input data. | 04-25-2013 |
20130103892 | COMBINED MEMORY BLOCK AND DATA PROCESSING SYSTEM HAVING THE SAME - A combined memory block includes a first memory unit configured to store data and an additional memory unit that forms a stacked structure with the memory unit, wherein the memory unit and the storage unit together form multi-level cells having variable resistance in storing data. | 04-25-2013 |
20130103893 | SYSTEM COMPRISING STORAGE DEVICE AND RELATED METHODS OF OPERATION - A memory system comprises a storage device and a host. The host classifies pages stored in the storage device into a plurality of data groups according to properties of the pages, and transmits setup information regarding the classified data groups to the storage device. | 04-25-2013 |
20130103894 | PROGRAMMING A MEMORY DEVICE TO INCREASE DATA RELIABILITY - Methods for programming a memory array, memory devices, and memory systems are disclosed. In one such method, the target reliability of the data to be programmed is determined The relative reliability of different groups of memory cells of the memory array is determined. The data is programmed into the group of memory cells of the array having a relative reliability corresponding to the target reliability. | 04-25-2013 |
20130103895 | FLASH MEMORY STORAGE SYSTEM - A flash memory storage system has a plurality of flash memory devices comprising a plurality of flash memories, and a controller having an I/O processing control unit for accessing a flash memory device specified by a designated access destination in an I/O request received from an external device from among the plurality of flash memory devices. A parity group can be configured of flash memory devices having identical internal configuration. | 04-25-2013 |
20130111103 | HIGH-SPEED SYNCHRONOUS WRITES TO PERSISTENT STORAGE | 05-02-2013 |
20130111104 | ASYNCHRONOUS DATA SHIFT AND BACKUP BETWEEN ASYMMETRIC DATA SOURCES | 05-02-2013 |
20130111105 | NON-VOLATILE DATA STRUCTURE MANAGER AND METHODS OF MANAGING NON-VOLATILE DATA STRUCTURES | 05-02-2013 |
20130111106 | PROMOTION OF PARTIAL DATA SEGMENTS IN FLASH CACHE | 05-02-2013 |
20130111107 | TIER IDENTIFICATION (TID) FOR TIERED MEMORY CHARACTERISTICS | 05-02-2013 |
20130111108 | SOLID STATE DRIVE AND METHOD FOR CONTROLLING CACHE MEMORY THEREOF | 05-02-2013 |
20130111109 | CAPACITOR SAVE ENERGY VERIFICATION | 05-02-2013 |
20130111110 | CAPACITOR SAVE ENERGY VERIFICATION | 05-02-2013 |
20130111111 | CAPACITOR SAVE ENERGY VERIFICATION | 05-02-2013 |
20130111112 | METHOD FOR ADJUSTING PERFORMANCE OF A STORAGE DEVICE AND A SEMICONDUCTOR STORAGE DEVICE THEREFOR | 05-02-2013 |
20130111113 | NAND Flash Memory Controller Exporting a NAND Interface | 05-02-2013 |
20130111114 | DISTRIBUTED STORAGE SYSTEM, APPARATUS, AND METHOD FOR MANAGING DISTRIBUTED STORAGE IN CONSIDERATION OF REQUEST PATTERN | 05-02-2013 |
20130111115 | MANAGING WRITE OPERATIONS IN A COMPUTERIZED MEMORY | 05-02-2013 |
20130111116 | STORAGE DEVICE AND COMPUTER USING THE SAME | 05-02-2013 |
20130111117 | STORAGE ARRAY, STORAGE SYSTEM, AND DATA ACCESS METHOD | 05-02-2013 |
20130111118 | SYSTEM AND METHOD FOR STORING DATA USING A FLEXIBLE DATA FORMAT | 05-02-2013 |
20130117496 | METHOD AND SYSTEM FOR MANAGING FLASH WRITE - A method for managing flash memory operations in a flash memory, comprising; assigning a state code to said flash memory operations; updating a state code flag with the assigned state code upon completion of each of said flash memory operations; wherein the assignment of said state codes is selected in a way that each of said updating a state code flag is performed by changing of one bit of the state code flag from one to zero. | 05-09-2013 |
20130117497 | BUFFER MANAGEMENT STRATEGIES FOR FLASH-BASED STORAGE SYSTEMS - Techniques are generally described related to a flash-based buffer management strategy. One example method for managing a buffer for a computer system may include monitoring, by a buffer management module, a plurality of operations being executed on the computer system and utilizing a plurality of buffer pages of the buffer. The example method may also include, upon a determination that the buffer is full, identifying a specific buffer page from the plurality of buffer pages for eviction, wherein the specific buffer page is selected based on a page state of the specific buffer page and a page hotness prediction for the specific buffer page. The example method may further include evicting the specific buffer page from the buffer. | 05-09-2013 |
20130117498 | SIMULATED NVRAM - Embodiments of the invention relate to leveraging disk controller cache memory to simulate non-volatile random access memory. At least one logical block address in cache memory of the disk controller is designated and set aside as permanently dirty. Read operations may be supported with data in the cache memory; including data retained in any block address designated as permanently dirty. Write operations may also be supported by storing the write data in the logical block address designated as permanently dirty. | 05-09-2013 |
20130117499 | REVERSIBLE WRITE-PROTECTION FOR NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - A serial memory device having a non-volatile memory array including a plurality of memory blocks, one or more said plurality of blocks being capable of being placed in a locked or an unlocked state upon receiving designated lock or unlock signal sequences is provided. The unlock signal sequences comprises at least two sequential signal sequences: a first unlock sequence, which has 1 to 7 signal bits, is applied to one of address input pins or a logic low enabled write-protection input pin and a second unlock sequence follows the first unlock signal sequence and is applied to a serial data access pin. The memory device further comprising a control logic circuit block coupled to a write-protection circuit block to provide means to identify the designated lock and unlock signal sequences and to set a protection state in a security area. | 05-09-2013 |
20130117500 | MEMORY SYSTEM AND MEMORY MANAGING METHOD THEREOF - A memory managing method is provided for a memory system, including a nonvolatile memory device and a memory controller controlling the nonvolatile memory device. The memory managing method includes determining whether a program-erase number of a memory block in the nonvolatile memory device reaches a first reference value; managing a life of the memory block according to a first memory managing method when the program-erase number of the memory block is determined to be less than the first reference value; and managing the life of the memory block according to a second memory managing method different from the first memory managing method when the program-erase number of the memory block is determined to be greater than the first reference value. | 05-09-2013 |
20130117501 | GARBAGE COLLECTION METHOD FOR NONVOLATILE MEMORY DEVICE - A nonvolatile memory device includes a memory area having free segments and first to fourth regions having used segments. The garbage collection method includes selecting a target segment from the used segments, moving a valid data block from the selected target segment to the used segments, and erasing data of all data blocks in the selected target segment and making the selected target segment into a free segment. When the number of free segments is greater than a predefined value, the target segment is selected by a first method and valid data blocks in the target segment are moved by a second method. When the number of free segments is less than the predefined value, the target segment is selected by a third method and valid data blocks in the target segment are moved by a fourth method. | 05-09-2013 |
20130117502 | METHOD FOR MANAGING SYSTEM FIRMWARE IN NAS SERVER - A method for managing system firmware in a network attached storage (NAS) server comprises: synchronizing system firmware stored one or more of two or more hard disks (HDDs) and system firmware stored in a nonvolatile memory with each other; and confirming whether or not at least one valid HDD in which the system firmware is stored exists, when an HDD is replaced; and copying the system firmware stored in the nonvolatile memory into the replaced HDD, when it is confirmed that the valid HDD does not exist. In the method, when a watch dog timer is reset, the system firmware stored in the nonvolatile memory is synchronized, based on the system firmware stored in the HDD, by confirming whether or not the system firmware of the HDD and the system firmware of the nonvolatile memory are synchronized with each other. | 05-09-2013 |
20130117503 | SERVICING NON-BLOCK STORAGE REQUESTS - An apparatus, system, and method are disclosed for servicing storage requests for a non-volatile memory device. An interface module is configured to receive a storage request for a data set of a non-volatile memory device from a client. The data set is different from a block of the non-volatile memory device, and may have a length different from a block size of the non-volatile memory device. A block load module is configured to load data of at least the block size of the non-volatile memory device. A fulfillment module is configured to service the storage request using at least a portion of the loaded data. | 05-09-2013 |
20130124778 | METHOD OF STORING HOST DATA AND META DATA IN A NAND MEMORY, A MEMORY CONTROLLER AND A MEMORY SYSTEM - A host device connected to memory devices, with each memory device having NAND memory chips and an associated controller. Each NAND memory chip can store a page of data in a single write operation, and can read a page of data from NAND memory in a single read operation, with the page being the smallest unit of storage and having a plurality of bits. The controller of each memory chip partitions each page of the associated NAND memory chip into first, second and third locations. The first location is for storage of host data. The second location is for storage of controller meta data. The third location is for storage of meta data of the host device associated with the host data. The host data, meta data of the controller, and meta data of the host device are written into or read from a page in a single operation. | 05-16-2013 |
20130124779 | SYSTEM AND METHOD FOR DATA INVERSION IN A STORAGE RESOURCE - A method may comprise receiving a page of data to be stored on a storage resource. The method may also comprise determining, for each particular inversion mode of a plurality of inversion modes, the number of bits of the page of data to be inverted to store a representation of the page of data in accordance with the particular inversion mode. The method may additionally comprise determining a selected inversion mode from the plurality of inversion modes for the page of data, the selected inversion mode comprising the inversion mode for which the least number of physical bit transitions are required to store the representation of the page of data in accordance with the selected inversion mode. The method may further comprise storing the representation of the page of data in a data memory in accordance with the inversion mode. | 05-16-2013 |
20130124780 | APPARATUS TO MANAGE EFFICIENT DATA MIGRATION BETWEEN TIERS - A data storage system having a slow tier and a fast tier maintains hot data on the fast tier by migrating data from the slow tier to reserve space on the fast tier as data becomes hot over time. The system maintains a reserve space table and performs a mass migration of data from the fast tier to the slow tier. Data migration is frequently unidirectional with data migrating from the slow to the fast tier, reducing overhead during normal operation. | 05-16-2013 |
20130124781 | DATA SCRAMBLING BASED ON TRANSITION CHARACTERISTIC OF THE DATA - A method of storing data includes receiving data to be written to a memory device. The method includes selecting a scrambling operation from at least a first scrambling operation and a second scrambling operation. The scrambling operation is selected based on a transition characteristic associated with the data. The method includes scrambling the data according to the selected scrambling operation and storing the scrambled data in the memory device. Additionally, the method may include descrambling the scrambled data to produce descrambled data. | 05-16-2013 |
20130124782 | SOLID STATE DRIVE AND METHOD FOR CONSTRUCTING LOGICAL-TO-PHYSICAL TABLE THEREOF - A solid state drive and a method for constructing a logical-to-physical table of the solid state drive are provided. Once the solid state drive is powered on again, the logical-to-physical table and the bitmap table are directly read from the flash memory. Then, the blocks whose history numbers are higher than the reference history number are searched from the flash memory. According to the history numbers in an ascending order, the physical-to-logical data in the blocks are sequentially reconstructed into the logical-to-physical table and the bitmap table of the mapping unit. Consequently, the logical-to-physical table and the bitmap table can be quickly reconstructed. | 05-16-2013 |
20130124783 | METHOD OF OPERATING NONVOLATILE MEMORY DEVICES STORING RANDOMIZED DATA GENERATED BY COPYBACK OPERATION - In an operating method for a nonvolatile memory device, first random data is sensed from a source area of the memory cell array, the first random data having been generated using first random sequence data. While sensing the first random data, third random sequence data is loaded to a page buffer circuit, the third random sequence data being generated from the first random sequence data and second random sequence data. A logical operation is performed on the sensed first random data and the third random sequence data in the page buffer circuit to generate second random data, and the second random data is programmed to a target area in the memory cell array different from the source area. | 05-16-2013 |
20130124784 | MEMORY SYSTEM COMPRISING NONVOLATILE MEMORY DEVICE AND RELATED METHOD OF OPERATION - A method of programming a nonvolatile memory device comprises receiving write data, detecting an address of a multi-level cell area associated with the write data, randomizing the write data using the address and programming the randomized data in a single-level cell area. | 05-16-2013 |
20130124785 | DATA DELETING METHOD AND APPARATUS - A data deleting method and apparatus is provided in embodiments of this application. The method comprises: when a file system detects a delete request for a target file, examining a security property of the target file, wherein the security property of a file comprises secret classified property; if the security property of the target file is secret classified property, executing an overwrite operation on the target file and then executing a delete operation to delete the target file; wherein the overwrite operation comprises sending a write command to a SSD, the write command being a predefined write command which is expanded by adding an immediate scrubbing flag, to cause the SSD to invoke a backstage garbage collection program according to the predefined write command to immediately delete data on garbage blocks corresponding to logical block addresses of the target file. | 05-16-2013 |
20130124786 | MEMORY MODULE AND MEMORY CONTROLLER FOR CONTROLLING A MEMORY MODULE - The memory module having a plurality of memory chips and a plurality of connections for connecting the memory module to a processor. At least part of the connections is configurable to be grouped into N sets of address and control connections for N separatively controllable groups of memory chips of the plurality of memory chips (N≧2). | 05-16-2013 |
20130124787 | NAND FLASH-BASED STORAGE DEVICE AND METHODS OF USING - A solid state drive having at least one NAND flash memory component organized in blocks, pages and cells. Each cell is adapted to store at least two bits. Each block of the memory component is adapted to be dynamically configured to store at least one bit per cell using a first mode of operation and dynamically configured to store at least two bits per cell using a second mode of operation while the mass storage device is operating, wherein the first mode of operation entails programming fewer bits of a cell in fewer passes as compared to the second mode of operation. | 05-16-2013 |
20130124788 | MULTI-LEVEL DATA PROTECTION FOR FLASH MEMORY SYSTEM - The disclosed embodiments are directed to methods and apparatuses for providing efficient and enhanced protection of data stored in a FLASH memory system. The methods and apparatuses involve a system controller for a plurality of FLASH memory devices in the FLASH memory system that is capable of protecting data using two layers of data protection, including inter-card card stripes and intra-card page stripes. | 05-16-2013 |
20130124789 | PARTIAL ALLOCATE PAGING MECHANISM - A memory system is provided. The system includes a controller that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the controller to regulate read and write access to the one or more FLASH devices. Wear leveling components along with read and write processing components are provided to facilitate efficient operations of the FLASH memory devices. | 05-16-2013 |
20130124790 | MEMORY MODULE, CACHE SYSTEM AND ADDRESS CONVERSION METHOD - A memory system including a non-volatile memory, a cache memory, a control circuit, and a data processing device is configured. The high speed can be achieved by transferring data in the non-volatile memory to the cache memory to retain the same therein. When the data in the non-volatile memory is transferred to the cache memory, error correction is performed so as to improve the reliability. Since the cache memory and the non-volatile memory can be accessed from the data processing device independently, improvement in usability can be achieved. The memory system including the plurality of chips is configured as a memory system module where respective chips are arranged in a stacked manner and wired by a ball grid array (BGA) and wire bonding between chips. | 05-16-2013 |
20130124791 | APPARATUS, SYSTEM, AND METHOD FOR STORAGE SPACE RECOVERY IN SOLID-STATE STORAGE - An apparatus, system, and method are disclosed for storage space recovery in solid-state storage. A sequential storage module sequentially writes data packets in a storage division. The storage division includes a portion of a solid-state storage. The data packets are derived from an object. The data packets are sequentially stored by order of processing. A storage division selection module selects a storage division for recovery. A data recovery module reads valid data packets from the storage division selected for recovery, queues the valid data packets with other data packets to be written sequentially, and updates an index with a new physical address of the valid data. The index includes a mapping of physical addresses of data packets to object identifiers. A storage division recovery module marks the storage division selected for recovery as available for sequentially writing data packets in response to completing copying valid data from the storage division. | 05-16-2013 |
20130124792 | ERASE-SUSPEND SYSTEM AND METHOD - A method for suspending an erase operation performed on a group of memory cells in a flash memory circuit is disclosed. One example method includes initiating an erase operation on one or more memory cells, the erase operation including a plurality of erase pulses, checking for receipt of a memory command after a predetermined number of erase pulses, suspending, after the predetermined number of erase pulses, the erase operation if the memory command was received, and performing a memory operation associated with the memory command. | 05-16-2013 |
20130124793 | Method For Utilizing A Memory Interface To Control Partitioning Of A Memory Module - Apparatuses and methods for implementing partitioning in memory cards and modules where conventional memory cards or modules have only a single partition. A representative memory card/module in accordance with the invention includes a memory device(s), and a memory interface which includes a data bus, a command line and a clock line. The memory card/module further includes a memory controller coupled to the memory device(s) and to the memory interface. The memory card/module includes means for controlling the partitioning of the memory device(s), and the memory controller is configured to operate the memory device(s) in accordance with the partition information. | 05-16-2013 |
20130124794 | LOGICAL TO PHYSICAL ADDRESS MAPPING IN STORAGE SYSTEMS COMPRISING SOLID STATE MEMORY DEVICES - The present idea provides a high read and write performance from/to a solid state memory device. The main memory of the controller is not blocked by a complete address mapping table covering the entire memory device. Instead such table is stored in the memory device itself, and only selected portions of address mapping information are buffered in the main memory in a read cache and a write cache. A separation of the read cache from the write cache enables an address mapping entry being evictable from the read cache without the need to update the related flash memory page storing such entry in the flash memory device. By this design, the read cache may advantageously be stored on a DRAM even without power down protection, while the write cache may preferably be implemented in nonvolatile or other fail-safe memory. This leads to a reduction of the overall provisioning of nonvolatile or fail-safe memory and to an improved scalability and performance. | 05-16-2013 |
20130132638 | DISK DRIVE DATA CACHING USING A MULTI-TIERED MEMORY - A disk drive is disclosed that utilizes multi-tiered solid state memory for caching data received from a host. Data can be stored in a memory tier that can provide the required performance at a low cost. For example, multi-level cell (MLC) memory can be used to store data that is frequently read but infrequently written. As another example, single-level cell (SLC) memory can be used to store data that is frequently written. Improved performance, reduced costs, and improved power consumption can thereby be attained. | 05-23-2013 |
20130132639 | NON-VOLATILE MEMORY PACKAGING SYSTEM WITH CACHING AND METHOD OF OPERATION THEREOF - A method of operation of a non-volatile memory packaging system includes: addressing an integrated circuit package having a system interface; accessing a module controller, in the integrated circuit package, through system interface; accessing a random access memory, in the integrated circuit package, by the module controller for storing data from the system interface; writing to a non-volatile memory, in the integrated circuit package by the module controller, with the data from the random access memory; and monitoring an address look-up register, by the module controller, for reading the data from the non-volatile memory or the random access memory through the system interface. | 05-23-2013 |
20130132640 | DATA WRITING METHOD, AND MEMORY CONTROLLER AND MEMORY STORAGE APPARATUS USING THE SAME - A data writing method for a rewritable non-volatile memory module, and a memory controller and a memory storage apparatus using the same are provided. The method includes partitioning physical blocks of the rewritable non-volatile memory module into a data area and a spare area and configuring logical blocks. The method also includes selecting physical blocks from the spare area as spare physical blocks corresponding to a logical block and using only lower physical pages of the spare physical blocks to store updated data that is to be written into the logical block. The method further includes moving valid data of all logical pages of the logical block into a physical block of the data area, wherein each lower physical page and an upper physical page corresponding thereto in the physical block are programmed together. Accordingly, the method can effectively improve the speed and reliability of writing data. | 05-23-2013 |
20130132641 | STORAGE SYSTEM AND CONTROL METHOD OF STORAGE SYSTEM - A storage system is provided with a plurality of nonvolatile semiconductor storage devices (hereafter referred to as semiconductor storage devices) and a storage controller that is coupled to the plurality of semiconductor storage devices and that provides an LU (logical unit) to an upper level apparatus. Each of the semiconductor storage devices is provided with a nonvolatile semiconductor storage medium (hereafter referred to as a semiconductor medium) and a medium controller that is a controller that is coupled to the semiconductor medium. In the case in which the medium controller receives a write command and a data unit from a storage controller, the medium controller writes the data unit to a physical storage region of a write destination of the semiconductor medium in accordance with the write command and updates the real write data amount information that is used for specifying a real write data amount that is a total amount of a data unit that is written to the semiconductor medium based on an amount of a data unit that has been actually written. The medium controller notifies the storage controller of the real write data amount information on a regular basis or on an irregular basis. The storage controller calculates a real write data amount of the LU based on the real write data amount information from each of the semiconductor storage devices. | 05-23-2013 |
20130132642 | SOLID STATE DRIVE - A solid state drive includes a flash memory, a cache memory, and a controlling unit. The solid state drive is in communication with a host. The flash memory includes a plurality of blocks, wherein each of the blocks has a plurality of pages. The cache memory includes a plurality of cache units. The cache units are allocated into a plurality of groups according to operating statuses of respective cache units. The controlling unit is in communication with the host, the flash memory and the cache memory. Under control of the controlling unit, a write data from the host is temporarily stored in the cache memory so as to be written into the flash memory, or a read data from the flash memory is temporarily stored in the cache memory so as to be provided to the host. | 05-23-2013 |
20130132643 | Method and Apparatus for Scalable Low Latency Solid State Drive Interface - A solid state drive (SSD) apparatus including a plurality of solid state drives, a channel-interleaved interface operably coupled to the solid state drives, and a Peripheral Component Interconnect Express (PCIe) bridge operably coupled to the channel-interleaved interface. | 05-23-2013 |
20130132644 | METHOD OF PROGRAMMING A NONVOLATILE MEMORY DEVICE - A method of programming a nonvolatile memory device including a page buffer is provided. The method includes loading first page data and second page data into the page buffer; performing, by the page buffer, a first selective dump operation on the first page data and the second page data to generate first interleaved page data; performing, by the page buffer, a second selective dump operation on the first page data and the second page data to generate second interleaved page data; and programming the first interleaved page data and the second interleaved page data into a multi-level cell block. | 05-23-2013 |
20130132645 | SYSTEM AND METHOD FOR INCREASING CAPACITY, PERFORMANCE, AND FLEXIBILITY OF FLASH STORAGE - In one embodiment, an interface circuit is configured to couple to one or more flash memory devices and is further configured to couple to a host system. The interface circuit is configured to present at least one virtual flash memory device to the host system, wherein the interface circuit is configured to implement the virtual flash memory device using the one or more flash memory devices to which the interface circuit is coupled. | 05-23-2013 |
20130132646 | HIGH THROUGHPUT FLASH MEMORY SYSTEM - There is disclosed a memory system and method. The memory system may include a plurality of memory planes including two or more data memory areas, and a memory controller adapted to controlling reading, writing, and erasing of the plurality of memory planes. When any one of the data memory areas is occupied with one of a write operation and an erase operation, the controller may reconstruct data stored in the one occupied data memory area by reading parity information and data stored in the plurality of memory areas other than the one occupied data memory area. | 05-23-2013 |
20130132647 | OPTIMIZED GARBAGE COLLECTION ALGORITHM TO IMPROVE SOLID STATE DRIVE RELIABILITY - A method for managing memory operations in a storage device having a plurality of data blocks, the method including steps for determining a number of invalid pages, in each of the plurality of data blocks, determining a number of page reads for each of the plurality of data blocks and determining a dwell time for each of the plurality of data blocks. In certain aspects, the method further comprises steps for selecting a data block, from among the plurality of data blocks, for memory reclamation based on the number of invalid pages, the number of page reads, and the dwell time of the selected data block. A flash storage system and computer-readable media are also provided. | 05-23-2013 |
20130132648 | PORTABLE STORAGE DEVICE AND THE METHOD OF DYNAMICALLY ADJUSTING THE OPERATING MODES THEREOF - A portable storage device includes a flash memory component, a flash memory interface coupled with the flash memory component, a host access interface coupled with the flash memory interface, and a control unit coupled between the flash memory interface and the host access interface to fetch a communication protocol of the host via the host access interface and adjust operation modes of the flash memory interface. If the transmission bandwidth of the host is no smaller than a set transmission bandwidth of the flash memory interface, the control unit controls the flash memory interface to work at a first operation mode. If the transmission bandwidth is smaller than the set transmission bandwidth, the control unit controls the flash memory interface to work at a second operation mode. The transmission bandwidth of the first operation mode is bigger than that of the second operation mode. | 05-23-2013 |
20130132649 | Flash Memory Controller and Method for Generating a Driving Current for Flash Memories - The invention provides a flash memory controller. In one embodiment, the flash memory controller is coupled to a plurality of flash memories, and comprises a driving current generator and a processor. The driving current generator generates a driving current to drive the flash memories. The processor calculates the total number of flash memories, determines a driving current value according to the total number of flash memories, and directs the driving current generator to generate the driving current with a level greater than or equal to the driving current value. The driving current value is determined by the processor to be increased with an increase of the total number of flash memories. | 05-23-2013 |
20130132650 | STORAGE DEVICE BASED ON A FLASH MEMORY AND USER DEVICE INCLUDING THE SAME - Disclosed is a storage device which includes a flash memory storing data; and a controller controlling the flash memory and performing an invalidation operation in response to a trim command of a host, wherein the controller configures a trim sector bitmap using trim information provided from the host at the invalidation operation and manage the trim sector bitmap by a region unit. | 05-23-2013 |
20130132651 | ELECTRONIC SYSTEM AND MEMORY MANAGING METHOD THEREOF - A method for managing a flash memory including a plurality of blocks is provided. Each block includes a plurality of sets of a first page and a second page configured in pair. In response to a request for writing target data into a target block, at least one cache block is selected from the blocks. The target data is then written into the first pages in the at least one cache block. When a write-back condition is established, the target data is written from the cache block back to the target block. | 05-23-2013 |
20130132652 | MANAGING NON-VOLATILE MEDIA - An apparatus, system, and method are disclosed to manage non-volatile media. A media characteristic module is configured to determine media characteristics for non-volatile media. A configuration parameter module is configured to determine different configuration parameters for different storage cell abodes and/or for different groups of pages of the non-volatile media based on the determined media characteristics. A cell configuration module is configured to use the different configuration parameters for the different storage cell abodes and/or the different groups of pages of the non-volatile media. | 05-23-2013 |
20130132653 | DATA PARTITIONING SCHEME FOR NON-VOLATILE MEMORIES - Systems and methods are disclosed for partitioning data for storage in a non-volatile memory (“NVM”), such as flash memory. In some embodiments, a priority may be assigned to data being stored, and the data may be logically partitioned based on the priority. For example, a file system may identify a logical address within a first predetermined range for higher priority data and within a second predetermined range for lower priority data, such using a union file system. Using the logical address, a NVM driver can determine the priority of data being stored and can process (e.g., encode) the data based on the priority. The NVM driver can store an identifier in the NVM along with the data, and the identifier can indicate the processing techniques used on the associated data. | 05-23-2013 |
20130132654 | METHOD FOR CONTROLLING ACCESS OPERATIONS OF A FLASH MEMORY, AND ASSOCIATED FLASH MEMORY DEVICE AND FLASH MEMORY CONTROLLER - A method for controlling access operations of a flash memory includes: receiving first source data from a host; generating a plurality of first scrambled signals according to a plurality of pseudo random sequences and the first source data; obtaining a plurality of transmission powers of the first scrambled signals; and selecting a target scrambled signal from the first scrambled signals according to the transmission powers for storing to the flash memory. An associated flash memory device and an associated flash memory controller are also provided. | 05-23-2013 |
20130132655 | REDUCING WRITE AMPLIFICATION IN A CACHE WITH FLASH MEMORY USED AS A WRITE CACHE - Embodiments of the invention are directed to reducing write amplification in a cache with flash memory used as a write cache. An embodiment of the invention includes partitioning at least one flash memory device in the cache into a plurality of logical partitions. Each of the plurality of logical partitions is a logical subdivision of one of the at least one flash memory device and comprises a plurality of memory pages. Data are buffered in a buffer. The data includes data to be cached, and data to be destaged from the cache to a storage subsystem. Data to be cached are written from the buffer to the at least one flash memory device. A processor coupled to the buffer is provided with access to the data written to the at least one flash memory device from the buffer, and a location of the data written to the at least one flash memory device within the plurality of logical partitions. The data written to the at least one flash memory device are destaged from the buffer to the storage subsystem. | 05-23-2013 |
20130132656 | STORAGE SUBSYSTEM AND ITS DATA PROCESSING METHOD - The amount of data to be stored in a semiconductor nonvolatile memory can be reduced and overhead associated with data processing can be reduced. When a microprocessor receives a write request from a host computer and data D | 05-23-2013 |
20130132657 | RETRIEVEING DATA FROM DATA STORAGE SYSTEMS - A method is used in retrieving data from data storage systems. A nonvolatile memory module connected to a data storage system is detected. The data storage system uses information stored in the nonvolatile memory module to initiate an action. Based on the information, the action is performed. The action includes retrieving data from the data storage system to the nonvolatile memory module. | 05-23-2013 |
20130138866 | METHODS, SYSTEMS, AND COMPUTER READABLE MEDIA FOR PROVIDING BASIC INPUT/OUTPUT SYSTEM (BIOS) DATA AND NON-BIOS DATA ON THE SAME NON-VOLATILE MEMORY - Methods, systems, and computer readable media for providing BIOS data and non-BIOS data on the same non-volatile memory. According to one aspect, a system for providing BIOS data and non-BIOS data on the same non-volatile memory includes a controller for controlling access by a host to a non-volatile memory for storing data, the data including BIOS data and non-BIOS data. The controller includes a first bus interface for communicating data to and from the host via a first bus of a first bus protocol, a second bus interface for communicating data to and from the host via a second bus of a second bus protocol, and a third interface for communicating data to and from the non-volatile memory. The first bus comprises a bus that is operable after power-on reset and before BIOS is accessed. | 05-30-2013 |
20130138867 | Storing Multi-Stream Non-Linear Access Patterns in a Flash Based File-System - Accesses to logical pages of memory are monitored. Each logical page corresponds to a logical memory address and the accesses defining an access pattern. The logical memory addresses are logged in ordered pairs of consecutive logical pages in the access pattern. Upon receipt of a request to write data to a given logical page, a given ordered pair of consecutive logical pages containing the logical memory address of the given logical page as a first logical memory address in the ordered pair of logical memory addresses associated with that consecutive pair is obtained. A first physical memory address mapping to the first logical memory address is identified, and a second logical memory address from that identified consecutive pair. A second physical memory address mapping to the second logical memory address is identified, and the data and the second physical memory address are written to the first physical memory address. | 05-30-2013 |
20130138868 | SYSTEMS AND METHODS FOR IMPROVED COMMUNICATIONS IN A NONVOLATILE MEMORY SYSTEM - Systems and methods are provided for improved communications in a nonvolatile memory (“NVM”) system. The system can toggle between multiple communications channels to provide point-to-point communications between a host device and NVM dies included in the system. The host device can toggle between multiple communications channels that extend to one or more memory controllers of the system, and the memory controllers can toggle between multiple communications channels that extend to the NVM dies. Power islands may be incorporated into the system to electrically isolate system components associated with inactive communications channels. | 05-30-2013 |
20130138869 | NONVOLATILE MEMORY AND MEMORY DEVICE INCLUDING THE SAME - A nonvolatile memory has a first memory block including a plurality of sub memory blocks stacked in a direction perpendicular to a substrate, and a second memory block including a plurality of sub memory blocks stacked in a direction perpendicular to the substrate, the second memory block being parallel to the first memory block. Management data unchanged after it is programmed once is stored in at least one sub memory block of the first memory block and main data is stored in sub memory blocks of the second memory block. Meta data may be stored in a sub memory block of the first memory block of in any memory block that does not contain the management data. | 05-30-2013 |
20130138870 | MEMORY SYSTEM, DATA STORAGE DEVICE, MEMORY CARD, AND SSD INCLUDING WEAR LEVEL CONTROL LOGIC - Disclosed is a memory system which includes a nonvolatile memory having a user area and a buffer area; and wear level control logic managing a mode change operation in which memory blocks of the user area are partially changed into the buffer area, based on wear level information of the nonvolatile memory. | 05-30-2013 |
20130138871 | Flash Memory Device and Data Access Method for Same - The invention provides a flash memory device. In one embodiment, the flash memory device is coupled to a host, and comprises a flash memory, a controller, and a random access memory. The flash memory comprises a plurality of blocks for data storage. The random access memory stores a read count table for recording read counts of the blocks. When the read counts of a plurality of original blocks are greater than a threshold according to the read count table, the controller obtains a plurality of spare blocks from the flash memory as mirror blocks respectively corresponding to the original blocks, and copies a portion of a plurality of data pages of the original blocks to the mirror blocks whenever the original blocks are read until all of the data pages of the original blocks have been copied to the mirror blocks. | 05-30-2013 |
20130138872 | APPARATUS WITH A MEMORY CONTROLLER CONFIGURED TO CONTROL ACCESS TO RANDOMLY ACCESSIBLE NON-VOLATILE MEMORY - An apparatus includes a printed circuit board with a plurality of printed circuit board traces, a memory controller mounted on the printed circuit board coupled to one or more of the plurality of printed circuit board traces, a plurality of non-volatile type of memory integrated circuits coupled to the printed circuit board, and a plurality of support integrated circuits coupled between the memory controller and the plurality of non-volatile type of memory integrated circuits. | 05-30-2013 |
20130138873 | MEMORY SYSTEMS - Memory systems having a volatile memory, a non-volatile memory arranged in blocks, and a controller coupled to the volatile memory and to the non-volatile memory. The controller is configured to maintain, in the volatile memory, a list of addresses of erased blocks of the non-volatile memory. The list of addresses of erased blocks of the non-volatile memory is limited to a maximum number of list entries. The controller is further configured to transfer the list of addresses of erased blocks of the non-volatile memory from the volatile memory to the non-volatile memory in response to the list containing its maximum number of list entries and/or in response to an operation that would increase the number of list entries to a number equal to or greater than the maximum number of list entries. | 05-30-2013 |
20130138874 | SYSTEMS WITH PROGRAMMABLE HETEROGENEOUS MEMORY CONTROLLERS FOR MAIN MEMORY - A translating memory module is disclosed including a printed circuit board, at least one memory integrated circuit coupled to the printed board, and at least one support chip coupled to the printed circuit board and coupled between the edge connector and the at least one memory integrated circuit. The at least one support chip includes a bi-directional translator to translate between a first memory communication protocol for the at least one memory integrated circuit and a second memory communication protocol for a memory channel differing from the first memory communication protocol. The second memory communication protocol to communicate data, address, and control signals over the memory channel bus to read and write data into the memory of the translating memory module. | 05-30-2013 |
20130138875 | STORING/READING SEVERAL DATA STREAMS INTO/FROM AN ARRAY OF MEMORIES - High speed mass storage devices using NAND flash memories (MDY.X) are suitable for recording and playing back a video data stream under real-time conditions, wherein the data are handled page-wise in the flash memories and are written in parallel to multiple memory buses (MBy). However, for operating with multiple independent data streams a significant buffer size is required. According to the invention, data from different data streams are collected in corresponding different buffers (FIFO | 05-30-2013 |
20130145075 | DYNAMICALLY MANAGING MEMORY LIFESPAN IN HYBRID STORAGE CONFIGURATIONS - A system, and computer program product for managing the lifespan of a memory using a hybrid storage configuration are provided in the illustrative embodiments. A throttling rate is set to a first value for processing memory operations in the memory device. The first value is set using a health data of the memory device for determining the first value. A determination is made whether a memory operation can be performed on the memory device within the first value of the throttling rate, the first value of the throttling rate allowing a first number of memory operations using the memory device per time period. In response to the determining being negative, the memory operation is performed using a secondary storage device. | 06-06-2013 |
20130145076 | SYSTEM AND METHOD FOR MEMORY STORAGE - A memory storage system includes multiple flash memory storage devices, multiple transmission interfaces and a central control device. The central control device has a cache and respectively coupled to the flash memory storage devices through the transmission interfaces. The central control device is for maintaining a block map table (BMT) to record a mapping relationship between multiple logical blocks and the physical blocks of the flash memory storage devices and the BMT is temporarily stored in the cache. In addition, the central control device uses the communication commands to access the physical blocks of the flash memory storage devices, in which the communication commands are transmitted to multiple controllers in the flash memory storage devices through the transmission interfaces and the controllers access the physical blocks according to communication commands. In this way, the system can effectively manage multiple flash memory storage devices. | 06-06-2013 |
20130145077 | DYNAMICALLY MANAGING MEMORY LIFESPAN IN HYBRID STORAGE CONFIGURATIONS - A method for managing the lifespan of a memory using a hybrid storage configuration is provided in the illustrative embodiments. A throttling rate is set to a first value for processing memory operations in the memory device. The first value is set using a health data of the memory device for determining the first value. A determination is made whether a memory operation can be performed on the memory device within the first value of the throttling rate, the first value of the throttling rate allowing a first number of memory operations using the memory device per time period. In response to the determining being negative, the memory operation is performed using a secondary storage device. | 06-06-2013 |
20130145078 | METHOD FOR CONTROLLING MEMORY ARRAY OF FLASH MEMORY, AND FLASH MEMORY USING THE SAME - A control method for a Flash memory array and a Flash memory is disclosed. The Flash memory array includes a plurality of blocks which are classified into groups and each group includes at least one block. The control method includes the steps of: recognizing an attribute of data transferred from a host, obtaining a storage group selected from the groups based on the attribute of the data, and storing the data into the blocks of the storage group and thereby the blocks of a same group store data of a same attribute; and performing a valid data collection, restricted to the blocks belonging to a same group, to release blocks of space. | 06-06-2013 |
20130145079 | MEMORY SYSTEM AND RELATED WEAR-LEVELING METHOD - A method is provided for performing wear-leveling in a memory system comprising a nonvolatile memory device and a memory controller configured to control the nonvolatile memory device. The method comprises setting a wear-level grade for each of a plurality of memory blocks based on a plurality of wear parameters, and determining an order in which to perform program and/or erase (P/E) operations on the memory blocks based on their respective wear-level grades. | 06-06-2013 |
20130145080 | Processing IC with Embedded Non Volatile Memory - There is disclosed an Integrated Circuit, IC, for use into a mobile device such as a cellular phone. The IC comprises a main processing unit ( | 06-06-2013 |
20130145081 | SEMICONDUCTOR DEVICE WITH NON-VOLATILE MEMORY AND RANDOM ACCESS MEMORY - A semiconductor device including a large capacity non-volatile memory and at least one random access memory, said the access time of said device being matched to the access time of each random access memory. The semiconductor memory device is comprised of: a non-volatile memory FLASH having a first reading time; a random access memory DRAM having a second reading time which is more than 100 times shorter than the first reading time; a circuit that includes a control circuit connected to both the FLASH and the DRAM and enabled to control accesses to those FLASH and DRAM; and a plurality of I/O terminals connected to the circuit. As a result, FLASH data is transferred to the DRAM before the DRAM is accessed, thereby matching the access time between the FLASH and the DRAM. Data is written back from the DRAM to the FLASH as needed, thereby keeping data matched between the FLASH and the DRAM and storing the data. | 06-06-2013 |
20130145082 | MEMORY ACCESS CONTROL APPARATUS AND MEMORY ACCESS CONTROL METHOD - A memory is readable by page and erasable by block including a plurality of pages. After a read request to the memory is issued, a memory controller specifies all blocks which can be accessed based on an address specified by a read command, as candidate blocks, and specifies an inspection target page out of pages included in the candidate blocks on the basis of a predetermined rule. The memory controller inspects whether or not there is an error in the inspection target page. | 06-06-2013 |
20130145083 | Semiconductor Memory Device - According to one embodiment, a semiconductor memory device includes a memory which comprises an area accessible from outside and a confidential information area storing confidential information and a set flag. A controller reads the flag from the memory when instructed to erase data in the confidential information area, determines whether the flag is set, erases data in the confidential information area when the flag is clear, and abandons process requested by the data erase instruction when the flag is set. An authenticator uses data in the confidential information area to execute operation for authentication. | 06-06-2013 |
20130145084 | Electronic Apparatus - An electronic apparatus provided with a serial communication circuit achieving a baud rate adjustment with high precision is provided. For example, a bit width of each of a plurality of bits in received serial data is measured by a clock counter, and an average value of the bit width is calculated detecting its maximum value and minimum value. Moreover, for example, a maximum tolerance and a minimum tolerance are calculated as a value substantially 1.5 times the average value and a value substantially 0.5 times the average value, and determination is made as to whether or not the maximum value and the minimum value are within a range between the maximum tolerance and the minimum tolerance. If they are within the range, the corresponding average value is set in a baud rate setting register. | 06-06-2013 |
20130145085 | Virtual Memory Device (VMD) Application/Driver with Dual-Level Interception for Data-Type Splitting, Meta-Page Grouping, and Diversion of Temp Files to Ramdisks for Enhanced Flash Endurance - A Virtual-Memory Device (VMD) driver and application execute on a host to increase endurance of flash memory attached to a Super Enhanced Endurance Device (SEED) or Solid-State Drive (SSD). Host accesses to flash are intercepted by the VMD driver using upper and lower-level filter drivers and categorized as data types of paging files, temporary files, meta-data, and user data files, using address ranges and file extensions read from meta-data tables. Paging files and temporary files are optionally written to flash. Full-page and partial-page data are grouped into multi-page meta-pages by data type before storage by the SSD. ramdisks and caches for storing each data type in the host DRAM are managed and flushed to the SSD by the VMD driver. Write dates are stored for pages or blocks for management functions. A spare/swap area in DRAM reduces flash wear. Reference voltages are adjusted when error correction fails. | 06-06-2013 |
20130145086 | PROCESSOR-BUS-CONNECTED FLASH STORAGE MODULE - A method for accessing a virtual memory of a processor using a processor-bus-connected flash storage module (PFSM) as a first paging device and a hard disk drive (HDD) as a second paging device, the method including: allocating a first address partition and a second address partition of a virtual memory for a software application of a processor to the first paging device and the second paging device, respectively, identifying a virtual memory page in the first paging device responsive to a page fault of the virtual memory triggered by the software application, sending a page access request to the PFSM for accessing the virtual memory page responsive to the page fault, and receiving the virtual memory page from the PFSM based on a command of the processor bus issued by the PFSM in conjunction with performing a flash memory access in the flash memory using a flash page address. | 06-06-2013 |
20130145087 | MEMORY SYSTEM AND BLOCK MERGE METHOD - In one embodiment, the invention provides a memory system including a flash memory device including a plurality of memory blocks implementing a plurality of data blocks, a plurality of log blocks, and a plurality of free blocks. The memory system further includes a flash translation layer maintaining the number of the free blocks to be at least equal to a reference number by converting selected memory blocks among the data and log blocks into free blocks via at least one merge operation during a background period. Additionally, the flash translation layer converts selected ones of the free blocks into data and log blocks, respectively. | 06-06-2013 |
20130145088 | HIGH-SPEED MEMORY SYSTEM - The disclosed embodiments relate to a Flash-based memory module having high-speed serial communication. The Flash-based memory module comprises, among other things, a plurality of I/O modules, each configured to communicate with an external device over one or more external communication links, a plurality of Flash-based memory cards, each comprising a plurality of Flash memory devices, and a plurality of crossbar switching elements, each being connected to a respective one of the Flash-based memory cards and configured to allow each one of the I/O modules to communicate with the respective one of the Flash-based memory cards. Each I/O module is connected to each crossbar switching element by a high-speed serial communication link, and each crossbar switching element is connected to the respective one of the Flash-based memory cards by a plurality of parallel communication links. | 06-06-2013 |
20130145089 | CACHE MEMORY MANAGEMENT IN A FLASH CACHE ARCHITECTURE - Provided is a method for managing cache memory to cache data units in at least one storage device. A cache controller is coupled to at least two flash bricks, each comprising a flash memory. Metadata indicates a mapping of the data units to the flash bricks caching the data units, wherein the metadata is used to determine the flash bricks on which the cache controller caches received data units. The metadata is updated to indicate the flash brick having the flash memory on which data units are cached. | 06-06-2013 |
20130145090 | SEMICONDUCTOR STORAGE DEVICE AND METHOD OF CONTROLLING THE SAME - A semiconductor storage device includes a first nonvolatile memory to store user data of a file, a second nonvolatile memory to store management data of the file, the second nonvolatile memory being different in type from the first nonvolatile memory, and a controller to control read/write of data with respect to the first and second nonvolatile memories. | 06-06-2013 |
20130151751 | HIGH SPEED SERIAL PERIPHERAL INTERFACE MEMORY SUBSYSTEM - A memory subsystem is disclosed. The memory subsystem includes a serial peripheral interface (SPI) double data rate (DDR) volatile memory component, a serial peripheral interface (SPI) double data rate (DDR) non-volatile memory component coupled to the serial peripheral interface (SPI) double data rate (DDR) volatile memory component and a serial peripheral interface (SPI) double data rate (DDR) interface. The serial peripheral interface (SPI) double data rate (DDR) interface accesses the serial peripheral interface (SPI) double data rate (DDR) volatile memory component and the serial peripheral interface (SPI) double data rate (DDR) non-volatile memory component where data is accessed on leading and falling edges of a clock signal. | 06-13-2013 |
20130151752 | BIT-LEVEL MEMORY CONTROLLER AND A METHOD THEREOF - The present invention is directed to a bit-level memory controller and method adaptable to managing defect bits of a non-volatile memory. A bad column management (BCM) unit retrieves a bit-level mapping table, in which defect bits are respectively marked, based on which the BCM unit constructs a bit-level script (BLS) that contains a plurality of entries denoting defect-bit groups respectively. An internal buffer is configured to store data managed by the BCM unit according to the BLS. | 06-13-2013 |
20130151753 | SYSTEMS AND METHODS OF UPDATING READ VOLTAGES IN A MEMORY - A method includes receiving hard bit data and soft bit data corresponding to a portion of a memory, where each storage element of the memory stores multiple bits per storage element. The hard bit data and the soft bit data is received in connection with reading a single bit of the multiple bits from each storage element in the portion of the memory based on one or more first read voltages. One or more second read voltages based on the hard bit data and the soft bit data are generated in response to a read voltage update operation. The memory reads data from the portion of the memory using the one or more second read voltages. | 06-13-2013 |
20130151754 | LBA BITMAP USAGE - Systems and methods are disclosed for logical block address (“LBA) bitmap usage for a system having non-volatile memory (“NVM”). A bitmap can be stored in volatile memory of the system, where the bitmap can store the mapping statuses of one or more logical addresses. By using the bitmap, the system can determine the mapping status of a LBA without having to access the NVM. In addition, the system can update the mapping status of a LBA with minimal NVM accesses. By reducing the number of NVM accesses, the system can avoid triggering a garbage collection process, which can improve overall system performance. | 06-13-2013 |
20130151755 | Non-Volatile Storage Systems with Go To Sleep Adaption - A non-volatile memory system goes into a low-power standby sleep mode to reduce power consumption if a host command is not received within delay period. The duration of this delay period is adjustable. In one set of embodiments, host commands can specify the delay value, the operation types to which it applies, and whether the value is power the current power session or to be used to reset a default value as well. In other aspects, the parameters related to the delay value are kept in a host resettable parameter file. In other embodiments, the memory system monitors the time between host commands and adjusts this delay automatically. | 06-13-2013 |
20130151756 | Data de-duplication and solid state memory device - Example methods and apparatus concern identifying placement and/or erasure data for a flash memory based solid state device that supports de-duplication. One example apparatus include a processor, a memory, a set of logics and an interface to connect the processor, the memory, and the set of logics. The apparatus may include an SSD placement logic configured to determine placement data for a de-duplication data set. The placement data may be based on forensic data acquired for the de-duplication data set. The apparatus may also include a write logic configured to write at least a portion of the de-duplication data set to an SSD as controlled by the placement data. The forensic data may identify, for example, the order in which sub-blocks are accessed, reference counts, access frequency, access groups, and other access information. | 06-13-2013 |
20130151757 | INDEPENDENT WRITE AND READ CONTROL IN SERIALLY-CONNECTED DEVICES - A memory device, comprising a first control input port, a second control input port, a third control input port, a data input port, a data output port, an internal memory and control circuitry. The control circuitry is responsive to a control signal on the first control input port to capture command and address information via the data input port. When the command is a read command, the control circuitry is further responsive to a read control signal on the second control input port to transfer data associated with the address information from the internal memory onto the data output port. When the command is a write command, the control circuitry is responsive to a write control signal on the third control input port to write data captured via the data input port into the internal memory at a location associated with the address information. | 06-13-2013 |
20130151758 | NONVOLATILE MEMORY DEVICE - A nonvolatile memory device includes: N (N is an integer equal to or greater than 2) number of nonvolatile memory cells disposed in a flag area of a page, N number of flag page buffers configured to input and output flag data to and from the nonvolatile memory cells of the flag area, and a data input/output control unit configured to select R number of flag page buffers so that the flag data is inputted and outputted from the R selected flag page buffers and no flag data is inputted and outputted through unselected N−R number of flag page buffers, wherein no one flag page buffer of the R selected flag page buffers is immediately adjacent to another one of the R selected flag page buffers. | 06-13-2013 |
20130151759 | STORAGE DEVICE AND OPERATING METHOD ELIMINATING DUPLICATE DATA STORAGE - A storage device includes storage media and a controller. The controller includes a de-duplication table that manages hash information for data stored in the storage media, and compares hash information for received write-requested data with hash information managed by the de-duplication table to determine whether the write-requested data is duplicate data. | 06-13-2013 |
20130151760 | NONVOLATILE MEMORY DEVICE AND OPERATING METHOD THEREOF - Disclosed is a memory system which includes a nonvolatile memory device configured to store data information; and a memory controller configured to control the nonvolatile memory device. The memory controller provides the nonvolatile memory device with a program command sequence including program speed information according to an urgency level of an internally requested program operation. | 06-13-2013 |
20130151761 | DATA STORAGE DEVICE STORING PARTITIONED FILE BETWEEN DIFFERENT STORAGE MEDIUMS AND DATA MANAGEMENT METHOD - A data management method for a data storage device includes receiving a write request; partitioning the file into first and second portions; encrypting the first portion, and storing the encrypted first portion in a first storage medium and the second portion in a second storage medium. | 06-13-2013 |
20130151762 | STORAGE DEVICE - The present invention aims to improve the performance of accessing flash memory used as a storage medium in a storage device. In the storage device in accordance with the present invention, a storage controller, before accessing the flash memory, queries a flash controller as to whether the flash memory is accessible. | 06-13-2013 |
20130151763 | STORAGE SYSTEM HAVING A PLURALITY OF FLASH PACKAGES - A storage system | 06-13-2013 |
20130151764 | SYSTEMS AND METHODS FOR STORING DATA IN A MULTI-LEVEL CELL SOLID STATE STORAGE DEVICE - This disclosure is related to systems and methods for storing data in multi-level cell solid state storage devices, such as Flash memory devices. In one example, a multi-level cell memory array has programmable pages, a first page having a first programming time, and a second page having a second programming time that is different than the first programming time. In one embodiment, the first programming time is faster than the to second programming time. Further, a controller coupled to the multi-level cell memory array may be configured to select the first page to store the data when a priority level of a write operation indicates a first priority level and select the second page to store the data when the priority level indicates a second priority level. | 06-13-2013 |
20130151765 | CLUSTER BASED NON-VOLATILE MEMORY TRANSLATION LAYER - Methods of operating non-volatile memory devices including dividing the non-volatile memory device into a plurality of sequentially addressed clusters, wherein each cluster contains a plurality of sequentially addressed logical blocks, and where at least one cluster of the plurality of sequentially addressed clusters addresses a different number of sequentially addressed logical blocks than another one of the clusters of the plurality of sequentially addressed clusters. | 06-13-2013 |
20130159599 | Systems and Methods for Managing Data in a Device for Hibernation States - The present application is directed to systems and methods for managing data in a device for hibernation states. In one implementation, the device includes an interface and a processor. The interface is coupled with a first memory and a second memory. The processor is in communication with the first and second memories via the interface. The processor is configured to read first data from the first memory, generate image data of the data stored in the first memory based on the first data, and write to the second memory prior to the device entering an initial hibernation state the image data of the data stored in the first memory. The processor is further configured to, after the device awakes from the initial hibernation state, read the image data from the second memory, reconstruct the first data based on the image data, and write the first data to the first memory. | 06-20-2013 |
20130159600 | Systems and Methods for Performing Variable Flash Wear Leveling - Systems and methods for performing wear leveling are disclosed. In one implementation, a controller partitions a memory block into at least a first partition and a second partition. The controller utilizes the first partition of the memory block for storage of data blocks until the first partition reaches a first end of life condition. After the first partition reaches the first end of life condition, the controller utilizes the first partition for storage of data blocks associated with a compression ratio that is less than a compression threshold until the first portion reaches a second end of life condition. The controller additionally utilizes the second partition for the storage of data blocks until the second partition reaches the first end of life condition. | 06-20-2013 |
20130159601 | Controller and Method for Virtual LUN Assignment for Improved Memory Bank Mapping - A controller communicates with a plurality of multi-chip memory packages. Each multi-chip memory package comprises a plurality of memory dies, each having a respective plurality of memory blocks, some of which are good and some of which are bad. The controller determines a number of good blocks in each memory die. Based on the determined number of good blocks in each memory die, the controller selects a memory die from each of the multi-chip memory packages to access in parallel, wherein the selected memory dies are not necessarily all in the same relative position in each multi-chip package. The controller then creates a metablock from a set of good blocks from each of the selected memory dies, wherein a maximum number of metablocks that can be created across the selected memory dies is determined by a lowest number of good blocks in the selected memory dies. | 06-20-2013 |
20130159602 | UNIFIED MEMORY ARCHITECTURE - Various embodiments of the present invention relate to a Unified Memory Architecture. The Unified Memory Architecture may use MRAM, phase change memory, and/or any other storage having similar features. | 06-20-2013 |
20130159603 | Apparatus, System, And Method For Backing Data Of A Non-Volatile Storage Device Using A Backing Store - Methods, storage controllers, and systems for backing data of a non-volatile storage device using a backing store are described. One method includes satisfying storage operations using a non-volatile storage device, determining an age for data stored on the non-volatile storage device, and copying data of the non-volatile storage device having an age that satisfies a data retention time threshold to a dedicated backing store. One storage controller includes an operations module that satisfies storage operations using a non-volatile storage device, an age module that determines an age for data stored on the non-volatile storage device, and a backup module that copies data of the non-volatile storage device having an age that satisfies a data retention time threshold to a dedicated backing store. | 06-20-2013 |
20130159604 | MEMORY STORAGE DEVICE AND MEMORY CONTROLLER AND DATA WRITING METHOD THEREOF - A memory storage device is provided. The memory storage device includes a connector, a rewriteable non-volatile memory module, a second temporary memory and a memory controller having a first temporary memory. The memory controller receives a write command and the write data, and temporarily stores the write data into the first temporary memory. The memory controller also copies the write data into the second temporary memory from the first temporary memory and, based on the write command, writes the write data into the rewriteable non-volatile memory module. Additionally, the memory controller determines whether a program fail occurs when executing the write command. If the program fail occurs, the memory controller reads the write data from the second temporary memory and re-execute the write command. Therefore, a write speed of the memory storage device can be effectively improved. | 06-20-2013 |
20130159605 | DATA MERGING METHOD FOR NON-VOLATILE MEMORY MODULE, AND MEMORY CONTROLLER AND MEMORY STORAGE DEVICE USING THE SAME - A data merging method for merging valid data of one logical block in a rewritable non-volatile memory module is provided. The method includes assigning a plurality of log physical blocks for the logical block. The method also includes performing a data arrangement operation and a data move operation with a partial synchronization manner to copy the valid data of the logical block into the lower physical pages of the log physical blocks from a first data physical block and at least one spare physical block while programming the valid data of the logical block into a second data physical block from the lower physical pages of the log physical blocks in units of each physical page group. The method further includes remapping the logical block to the second physical block. Accordingly, the method can effectively shorten the time of merging valid data and improving the reliability of data writing. | 06-20-2013 |
20130159606 | SYSTEM AND METHOD FOR CONTROLLING SAS EXPANDER TO ELECTRONICALLY CONNECT TO A RAID CARD - In a method for controlling a SAS expander to electronically connect to a RAID card in an electronic device, a plurality of different types for RAID cards, and configuration parameters of the SAS expander corresponding to each type of the RAID cards are preset. Information of the RAID card is read if the SAS expander is electronically connected the RAID card. The method further determines whether the RAID card matches the SAS expander. If the RAID card does not match the SAS expander, the configuration parameters of the SAS expander corresponding to the RAID card is read, and the read configuration parameters and the read information of the RAID card are written into a firmware file in the storage system. The method further stores the firmware file into a flash memory of the SAS expander. | 06-20-2013 |
20130159607 | MEMORY SYSTEM AND A PROGRAMMING METHOD THEREOF - A method of programming a storage device includes determining, at a controller of the storage device, that a first program mode of a plurality of program modes is to be entered in response to first information, wherein the first information includes a parameter associated with temperature, power consumption or input/output workload, and changing, using the controller, a program ratio of a first programming and a second programming of the storage device in the first program mode. | 06-20-2013 |
20130159608 | BRIDGE CHIPSET AND DATA STORAGE SYSTEM - A data storage system includes: a data storage medium configured to store data; a main controller configured to control an operation of the data storage medium; and a bridge chipset configured to convert a signal provided from the main controller according to a control information provided from an external source to the data storage medium and the main controller and to provide the converted signal to the data storage medium. | 06-20-2013 |
20130159609 | PROCESSING UNIT RECLAIMING REQUESTS IN A SOLID STATE MEMORY DEVICE - An apparatus and method for processing unit reclaiming requests in a solid state memory device. The present invention provides a method of managing a memory which includes a set of units. The method includes selecting a unit from the set of units having plurality of subunits. The method further includes determining a number of valid subunits m to be relocated from the units selected for a batch operation where m is at least 2. The selecting is carried out by a unit reclaiming process. | 06-20-2013 |
20130159610 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE RELATED METHOD OF OPERATION - A non-volatile semiconductor memory device includes a flash memory including plural blocks of memory cells, and a controller. The controller is configured to program a block of memory cells of the flash memory, to determine a first time period elapsed in which a given percentage of memory cells of the block of memory cells are programmed, and to compare the first time period with a reference second time period. The flash memory and controller are further configured, based on a comparison result between the first time period and the reference time period, to change an operational parameter associated with the block of memory cells, the changed operational parameter being in effect during at a next operational access of the block of memory cells. | 06-20-2013 |
20130159611 | SYSTEMS AND METHODS FOR PROVIDING LOAD ISOLATION IN A SOLID-STATE DEVICE - Systems for automatically calibrating a storage memory controller are disclosed. In some embodiments, the systems may be realized as a solid state device system with an electro-static discharge (ESD) protection capability. The system can include a memory controller electrically coupled to a channel, where the memory controller is configured to select at least one of a plurality of flash memory devices. The system can also include at least one isolation device including an ESD protection circuit, configured to electrically couple the channel to the at least one of the plurality of flash memory devices and to decouple the channel from the remaining of the plurality of flash memory devices. | 06-20-2013 |
20130159612 | Programmable Drive Strength in Memory Signaling - Embodiments of the invention relate to programmable data register circuits and programmable clock generation circuits For example, some embodiments include a buffer circuit for receiving input data and sending output data signals along a series of signal lines with a signal strength, and a signal modulator configured to determine the signal strength based on a control input. Some embodiments include a clock generation circuit for receiving clock reference and sending output clock signals along a series of signal lines with a signal character, and a signal modulator configured to determine the signal character based on a control input. | 06-20-2013 |
20130159613 | METHODS, APPARATUSES, AND COMPUTER PROGRAM PRODUCTS FOR ENHANCING MEMORY ERASE FUNCTIONALITY - A method, apparatus, and computer program product are provided for enhancing memory erase functionality. An apparatus may include a block-based mass memory and a controller configured to receive an erase command from a host device comprising an indication of a location of a block in the mass memory storing memory allocation data. The controller may be further configured to access the memory allocation data based at least in part upon the indicated location. The controller may additionally be configured to determine, based at least in part upon the memory allocation data, blocks within the mass memory that have been freed by the host device. The controller may also be configured to erase the freed blocks. Corresponding methods and computer program products are also provided. | 06-20-2013 |
20130166817 | DATA TRANSFER SYSTEMS WITH POWER MANAGEMENT - A controller for transferring data between a host and a storage medium includes a data transfer unit and a control unit. The data transfer unit transfers data according to control commands from the host if the data transfer unit is enabled. The control unit coupled to the data transfer unit receives a status signal indicating whether the storage medium is coupled to a socket of the controller. The control unit provides interruption signals to the host. Power and a clock signal for the control unit are disabled if the status signal indicates that the storage medium is decoupled from the controller. | 06-27-2013 |
20130166818 | MEMORY LOGICAL DEFRAGMENTATION DURING GARBAGE COLLECTION - A method and system defragments data during garbage collection. Garbage collection may be more efficient when the valid data that is aggregated together is related or logically linked. In particular, data from the same file or that is statistically correlated may be combined in the same blocks during garbage collection. | 06-27-2013 |
20130166819 | SYSTEMS AND METHODS OF LOADING DATA FROM A NON-VOLATILE MEMORY TO A VOLATILE MEMORY - A method may be performed in a data storage device that includes a controller, a non-volatile memory, and a volatile memory. The method includes loading a first portion of stored data from the non-volatile memory to the volatile memory according to one or more load priority indicators accessible to the controller. The method further includes, in response to completion of the loading of the first portion of the stored data to the volatile memory and prior to completion of loading a second portion of the stored data to the volatile memory, sending a signal to indicate to a host device operatively coupled to the data storage device that the volatile memory is ready for use by the host device. | 06-27-2013 |
20130166820 | METHODS AND APPRATUSES FOR ATOMIC STORAGE OPERATIONS - A method and apparatus for storing data packets in two different logical erase blocks pursuant to an atomic storage request is disclosed. Each data packet stored in response to the atomic storage request comprises persistent metadata indicating that the data packet pertains to an atomic storage request. In addition, a method and apparatus for restart recovery is disclosed. A data packet preceding an append point is identified as satisfying a failed atomic write criteria, indicating that the data packet pertains to a failed atomic storage request. One or more data packets associated with the failed atomic storage request are identified and excluded from an index of a non-volatile storage media. | 06-27-2013 |
20130166821 | LOW LATENCY AND PERSISTENT DATA STORAGE - Persistent data storage with low latency is provided by a method that includes receiving a low latency store command that includes write data. The write data is written to a first memory device that is implemented by a nonvolatile solid-state memory technology characterized by a first access speed. It is acknowledged that the write data has been successfully written to the first memory device. The write data is written to a second memory device that is implemented by a volatile memory technology. At least a portion of the data in the first memory device is written to a third memory device when a predetermined amount of data has been accumulated in the first memory device. The third memory device is implemented by a nonvolatile solid-state memory technology characterized by a second access speed that is slower than the first access speed. | 06-27-2013 |
20130166822 | SOLID-STATE STORAGE MANAGEMENT - Solid-state storage management for a system that includes a main board and a solid-state storage board separate from the main board is provided. The sold-state storage board includes a solid-state memory device and solid-state storage devices. The system is configured to perform a method that includes a correspondence being established, by a software module located on the main board, between a first logical address and a first physical address on the solid-state storage devices. The correspondence between the first logical address and the first physical address is stored in a location on the solid-state memory device. The method also includes translating the first logical address into the first physical address. The translating is performed by an address translator module located on the solid-state storage board and is based on the previously established correspondence between the first logical address and the first physical address. | 06-27-2013 |
20130166823 | NON-VOLATILE MEMORY DEVICE - A non-volatile memory device includes a plurality of bit lines; a plurality of page buffers corresponding to the bit lines, respectively, and configured to each store a write data; and a control circuit configured to control at least one page buffer of the plurality of page buffers to store the write data of a first logic level and control other ones of the plurality of page buffers to store the write data of a second logic level, wherein the control circuit is further configured to select the at least one page buffer based on an address inputted to the control circuit. Since write data of diverse patterns may be generated within a non-volatile memory device by using a portion of the bits of the address, a test operation of the non-volatile memory device may be performed within a short time. | 06-27-2013 |
20130166824 | BLOCK MANAGEMENT FOR NONVOLATILE MEMORY DEVICE - A method of managing memory blocks in a nonvolatile memory device comprises identifying a full memory block among a plurality of memory blocks in the nonvolatile memory device, determining whether a block life of the full memory block exceeds a threshold value, and upon determining that the block life of the full memory block exceeds the threshold value, selecting the full memory block as a target block for garbage collection. | 06-27-2013 |
20130166825 | Method Of Controlling Non-Volatile Memory, Non-Volatile Memory Controller Therefor, And Memory System Including The Same - A method of controlling a non-volatile memory device having multiple planes including receiving write requests from a host, the write requests each including a logical address, a write command, and a data set; storing the data sets at an address of a buffer; storing the buffer address in a mapping table that maps addresses of the buffer to the multiple planes; sequentially transmitting the data sets stored at respective buffer addresses to page buffers, respectively, of the planes corresponding to the buffer addresses according to the mapping table; and programming in parallel at least two data sets stored in respective page buffers to memory cells of the non-volatile memory device. | 06-27-2013 |
20130166826 | SOLID-STATE DEVICE MANAGEMENT - An embodiment is a method for establishing a correspondence between a first logical address and a first physical address on solid-state storage devices located on a solid-state storage board. The solid-state storage devices include a plurality of physical memory locations identified by physical addresses, and the establishing is by a software module located on a main board that is separate from the solid-state storage board. The correspondence between the first logical address and the first physical address is stored in in a location on a solid-state memory device that is accessible by an address translator module located on the solid-state storage board. The solid-state memory device is located on the solid-state storage board. The first logical address is translated to the first physical address by the address translator module based on the previously established correspondence between the first logical address and the first physical address. | 06-27-2013 |
20130166827 | WEAR-LEVEL OF CELLS/PAGES/SUB-PAGES/BLOCKS OF A MEMORY - The invention is directed to a method for wear-leveling cells or pages or sub-pages or blocks of a memory such as a flash memory, the method comprising:—receiving (S | 06-27-2013 |
20130166828 | DATA UPDATE APPARATUS AND METHOD FOR FLASH MEMORY FILE SYSTEM - Disclosed herein are a data update apparatus and method. The apparatus includes an update identification unit, a data storage unit, a block allocation unit, and a data update unit. The update identification unit determines whether the input/output request signal corresponds to an update signal. The data storage unit stores mapping information about the blocks of an arbitrary file in a metadata area. The block allocation unit stores addresses of one or more free blocks, which are selected from among blocks included in the data storage unit and in which data has not been stored. The data update unit acquires the addresses of the free blocks, writes the update data to the free blocks, and updates existing block addresses, which belong to information included in mapping information of the data storage unit and to which the update data has been mapped, with the addresses of the free blocks. | 06-27-2013 |
20130166829 | Fast Block Device and Methodology - A device, method and system is directed to fast data storage on a block storage device. New data is written to an empty write block. A location of the new data is tracked. Meta data associated with the new data is written. A lookup table may be updated based in part on the meta data. The new data may be read based the lookup table configured to map a logical address to a physical address. | 06-27-2013 |
20130166830 | BLOCK MANAGEMENT METHOD FOR FLASH MEMORY AND CONTROLLER AND STORAGE SYSETM USING THE SAME - A block management method for managing a mapping relationship between a plurality of logical blocks and a plurality of physical blocks of a flash memory is provided. The block management method includes: grouping the logical blocks into a plurality of logical zones; recording the mapping relationship between each logical block in each logical zone and all the data physical blocks among the physical blocks in a corresponding logical zone table in unit of the logical zones; and recording all the no-data physical blocks among the physical blocks with a single no-data physical block table. Thereby, the logical blocks can be mapped to all the physical blocks so that frequent access to specific physical blocks can be avoided when a user writes data into a specific logical zone frequently, and accordingly the lifespan of the flash memory can be prolonged. | 06-27-2013 |
20130166831 | Apparatus, System, and Method for Storing Metadata - Apparatuses, systems, and methods are disclosed for storing metadata. A mapping module is configured to maintain a mapping structure for logical addresses of a non-volatile device. A metadata module is configured to store membership metadata for the logical addresses with logical-to-physical mappings for the logical addresses in the mapping structure. | 06-27-2013 |
20130166832 | METHODS AND ELECTRONIC DEVICES FOR ADJUSTING THE OPERATING FREQUENCY OF A MEMORY - Methods and electronic devices for adjusting an operating frequency of a memory are disclosed. The method includes: transmitting to the memory a first command that instructs the memory to hold the data information in the memory; transmitting to the memory controller a second command that adjusts the first frequency of the memory controller to a second frequency; and transmitting to the memory a third command that instructs the memory to exchange the data information according to the second frequency of the memory controller. According to the disclosure, it is possible to dynamically adjust the frequency of the memory during operation, avoiding the need of the user to turn off and then turn on the electronic device to adjust the frequency of the memory. | 06-27-2013 |
20130173842 | Adaptive Logical Group Sorting to Prevent Drive Fragmentation - A method and system are disclosed for controlling the storage of data in a storage device to reduce fragmentation. The method may include a controller of a storage device receiving data for storage in non-volatile memory and determining if a threshold amount of data has been received. When the threshold amount of data is received, the non-volatile memory is scanned for sequentially numbered logical groups of data previously written in noncontiguous locations in the non-volatile memory. When a threshold amount of such sequentially numbered logical groups is found, the controller re-writes the sequentially numbered logical groups of data contiguously into a new block. The system may include a storage device with a controller configured to perform the method noted above, where the thresholds for scanning the memory for fragmented data and removing fragmentation by re-writing the fragmented data into new blocks may be fixed or variable. | 07-04-2013 |
20130173843 | WRITE BANDWIDTH MANAGEMENT FOR FLASH DEVICES - Embodiments of the present invention provide a flash memory device write-access management amongst different virtual machines (VMs) in a virtualized computing environment. In one embodiment, a virtualized computing data processing system can include a host computer with at least one processor and memory and different VMs executing in the host computer. The system also can include a flash memory device coupled to the host computer and accessible by the VMs. Finally, a flash memory controller can manage access to the flash memory device. The controller can include program code enabled to compute a contemporaneous bandwidth of requests for write operations for the flash memory device, to allocate a corresponding number of tokens to the VMs, to accept write requests to the flash memory device from the VMs only when accompanied by a token and to repeat the computing, allocating and accepting after a lapse of a pre-determined time period. | 07-04-2013 |
20130173844 | SLC-MLC Wear Balancing - A method and system for SLC-MLC Wear Balancing in a flash memory device is disclosed. The flash memory device includes a single level cell (SLC) portion and a multi-level cell (MLC) portion. The age of the SLC portion and the MLC portion may differ, leading potentially to one portion wearing out before the other. In order to avoid this, a controller is configured to receive an age indicator from one or both of the SLC portion and the MLC portion, determine, based on the age indicator, whether to modify operation of the SLC portion and/or the MLC portion, and in response to determining to modifying operation, modify the operation of the at least one of the SLC portion or the MLC portion. The modification of the operation may thus balance wear between the SLC and MLC portions, thereby potentially extending the life of the flash memory device. | 07-04-2013 |
20130173845 | Command Aware Partial Page Programming - A method and system for partial page programming in a storage device is disclosed. An amount of data for partial page programming is determined. The amount may include host data (such as host data in a host command sent from a host device) and/or binary cache index data. The write step, used for partial page programming, is dynamically set based on the determined amount of data for partial page programming. In this way, the write step for partial page programming is dynamic rather than fixed. Further, dynamically setting the write step may reduce the number of programming steps for storing the host data in the host command and may reduce padding when partial page programming, thereby leaving less invalid data inside a block. | 07-04-2013 |
20130173846 | Controller and Method for Memory Aliasing for Different Flash Memory Types - A controller and method for memory aliasing for different flash memory types are presented. In one embodiment, a controller is presented having one or more interfaces through which to communicate with a plurality of memory dies, wherein at least one of the memory dies is of a different memory type than the other memory dies. The controller also has an interface through which to communicate with a host, wherein the interface only supports commands for a single memory types. The controller further contains a processor that is configured to receive a logical address and a command from the host, determine which memory die is associated with the logical address, and translate the command received from the host to a form suitable for the memory type of the memory die associated with the logical address. | 07-04-2013 |
20130173847 | Metablock Size Reduction Using on Chip Page Swapping Between Planes - Methods and systems are disclosed herein for storing data in a memory device. Data for multiple pages is written in parallel using plane interleaving. For example, in a four plane write, a first set of four pages are written in the following sequence: 0, 1, 2, 3. A second set of four pages, after plane interleaving, are written in the following sequent: 7, 4, 5, 6. After writing the data, the pages of written data are read, page swapped if necessary, and then written into another portion of memory (such as MLC). | 07-04-2013 |
20130173848 | Controller and Method for Using a Transaction Flag for Page Protection - A controller is presented having one or more interfaces through which to communicate with a plurality of memory dies with multi-level memory cells and an interface through which to communicate with a host. The controller also contains a processor that is configured to receive a command from the host to program data in a plurality of lower pages and a plurality of upper pages of the multi-level memory cells. The controller detects an indication from the host that indicates which previously-programmed lower pages from a previous program command are at risk of being corrupted by the programming of the upper pages from the received program command. Prior to programming the upper pages, the controller backs up the previously-programmed lower pages from the previous program command that are at risk of being corrupted but not the lower pages of data programmed by the received program command. | 07-04-2013 |
20130173849 | WRITE BANDWIDTH MANAGEMENT FOR FLASHDEVICES - Embodiments of the present invention provide a flash memory device write-access management amongst different virtual machines (VMs) in a virtualized computing environment. In one embodiment, a virtualized computing data processing system can include a host computer with at least one processor and memory and different VMs executing in the host computer. The system also can include a flash memory device coupled to the host computer and accessible by the VMs. Finally, a flash memory controller can manage access to the flash memory device. The controller can include program code enabled to compute a contemporaneous bandwidth of requests for write operations for the flash memory device, to allocate a corresponding number of tokens to the VMs, to accept write requests to the flash memory device from the VMs only when accompanied by a token and to repeat the computing, allocating and accepting after a lapse of a pre-determined time period. | 07-04-2013 |
20130173850 | METHOD FOR MANAGING ADDRESS MAPPING INFORMATION AND STORAGE DEVICE APPLYING THE SAME - Methods and devices for managing address mapping information are disclosed. In one example, a method for managing address mapping information may include writing address mapping recovery information on a user data area of a storage medium in an initially set size unit, the address mapping recovery information being generated in response to a write operation, storing the address mapping recovery information without being written on the storage medium in a non-volatile memory device when an abnormal power off occurs in a storage device, and updating the address mapping information related to the storage device based on the address mapping recovery information stored in the non-volatile memory device and the storage medium when power is applied to the storage device. | 07-04-2013 |
20130173851 | NON-VOLATILE STORAGE DEVICE, ACCESS CONTROL PROGRAM, AND STORAGE CONTROL METHOD - An access control program is executed by a specific electronic device first connected to the non-volatile storage device to associate with the specific electronic device to be given full access to the storage, executed by the specific electronic device to set the specific electronic device associated with the non-volatile storage device to a first mode permitting full access to the storage, executed by an arbitrary electronic device connected to the non-volatile storage device to judge whether the arbitrary electronic device is the specific electronic device associated with the non-volatile storage device by performing certification; and executed by the arbitrary electronic device connected to the non-volatile storage device to perform mode setting. | 07-04-2013 |
20130173852 | MEMORY SYSTEM - According to the embodiments, a memory system includes a plurality of memory chips, I/O signal lines, CE signal lines, and a control unit. The plurality of memory chips is divided to a plurality of first groups. The first plurality of memory chips for each first group is divided to a plurality of second groups. Each of the I/O signal lines is commonly connected to the memory chips for each first group. Each of the CE lines is commonly connected to the memory chips for each second group. The control unit specifies one of the second groups using the CE signal line, and transmits a reset command to one of the I/O signal lines which is connected to the specified second group, at activation. Each of the memory chips belonging to the specified second group executes reset processing at respective timings after receiving the reset command. | 07-04-2013 |
20130173853 | MEMORY-EFFICIENT CACHING METHODS AND SYSTEMS - Caching systems and methods for managing a cache are disclosed. One method includes determining whether a cache eviction condition is satisfied. In response to determining that the cache eviction condition is satisfied, at least one Bloom filter registering keys denoting objects in the cache is referenced to identify a particular object in the cache to evict. Further, the identified object is evicted from the cache. In accordance with an alternative scheme, a bit array is employed to store recency information in a memory element that is configured to store metadata for data objects stored in a separate cache memory element. This separate cache memory element stores keys denoting the data objects in the cache and further includes bit offset information for each of the keys denoting different slots in the bit array to enable access to the recency information. | 07-04-2013 |
20130173854 | METHOD FOR MANAGING DATA IN STORAGE DEVICE AND MEMORY SYSTEM EMPLOYING SUCH A METHOD - A method for managing data in a storage device includes: receiving a logical page from a host and calculating an actual time stamp of the logical page; finding a block of the storage device in which the logical page is stored and detecting a time stamp of the block and a page offset of the logical page stored in the block; calculating an approximate time stamp of the logical page stored in the block using the time stamp of the block and the page offset; and determining that the logical page is in a first state if the difference between the actual time stamp and the approximate time stamp is smaller than a threshold value, and determining that the logical page is in a second state different from the first state if the difference between the actual time stamp and the approximate time stamp is larger than the threshold value. | 07-04-2013 |
20130173855 | METHOD OF OPERATING STORAGE DEVICE INCLUDING VOLATILE MEMORY AND NONVOLATILE MEMORY - For a storage device including a volatile memory and a nonvolatile memory, an operating method includes partitioning the volatile memory into volatile memory blocks in response to a first control command, and then performing a data read operation, a data write operation, or a data migration operation by using at least one of the volatile memory blocks. | 07-04-2013 |
20130173856 | DATA STORAGE DEVICE, MEMORY SYSTEM, AND COMPUTING SYSTEM USING NONVOLATILE MEMORY DEVICE - Provided is a data storage device including two or more data storage areas including may have two or more (heterogeneous) types of nonvolatile memory cells. At least one of the data storage areas includes a plurality of memory blocks that are sequentially selected, and metadata are stored in the currently selected memory block. The memory blocks can be sequentially used and metadata can be stored in a uniformly-distributed manner throughout the data storage device. Therefore, separate merging and wear-leveling operations are unnecessary. Thus, it is possible to improve the lifetime and writing performance of a data storage device having two or more heterogeneous nonvolatile memories. | 07-04-2013 |
20130173857 | FLASH MEMORY DEVICE WITH MULTI-LEVEL CELLS AND METHOD OF WRITING DATA THEREIN - In one aspect, a method of writing data in a flash memory system is provided. The flash memory system forms an address mapping pattern according to a log block mapping scheme. The method includes determining a writing pattern of data to be written in a log block, and allocating one of SLC and MLC blocks to the log block in accordance with the writing pattern of the data. | 07-04-2013 |
20130179623 | Buffer Managing Method and Buffer Controller thereof - By assigning a slave unit and at least one master unit in a buffer controller, clocks of the at least one master unit can be unified with a clock of the slave unit. A buffer status array is assigned for the slave unit in a buffer, and either a range status array or a queue status array is assigned for the master unit in the buffer for performing operations of the buffer controller in an accessing-by-block manner or in an accessing-by-spaced-interval manner. The master unit cooperated with the slave unit is determined from the at least one master unit by using a starvation-preventing algorithm. | 07-11-2013 |
20130179624 | SYSTEMS AND METHODS FOR TRACKING AND MANAGING NON-VOLATILE MEMORY WEAR - Systems and methods are disclosed that may be implemented to manage operation and tracking memory wear of flash devices, such as relatively large mixed use embedded NAND flash devices or other non-volatile memory (NVM) devices employed in information handling systems such as servers. The disclosed systems and methods may advantageously be implemented to perform tasks such as tracking and/or predicting actual wear for NVM devices, and optionally controlling write operations to a NVM device. The disclosed systems and methods may also be optionally implemented to generate wear alerts based on tracked or predicted wear of such NVM devices. | 07-11-2013 |
20130179625 | Security System Storage of Persistent Data - A security system including devices generating persistent data, a local control system (LCS) including a microprocessor and non-volatile memory and receiving persistent data from the devices, and a server remote from the LCS. The remote server is in communication with the LCS microprocessor which periodically transmits logical portions of persistent data (each including a timestamp) to the remote server where it is saved. The microprocessor also periodically saves the persistent data portions in LCS non-volatile memory less frequently than the persistent data portions are periodically saved in the remote data storage, and saves the timestamp in the local data storage for each persistent data portion saved only at the remote server. When rebooting the LCS, the microprocessor retrieves from the remote data storage only the persistent data portions having timestamps subsequent to the timestamp saved in the local data control system non-volatile memory. | 07-11-2013 |
20130179626 | DATA PROCESSING METHOD, MEMORY CONTROLLER AND MEMORY STORAGE APPARATUS - A data processing method for a memory storage apparatus having physical blocks is provided. The method includes: grouping the physical blocks into a data area, a spare area and a system area; configuring a plurality of logical addresses which would be formatted into a file allocation table area having cluster entry fields, a root directory area having directory entry fields and a file area having clusters; storing a communication file from the K | 07-11-2013 |
20130179627 | METHOD FOR MANAGING BUFFER MEMORY, MEMORY CONTROLLOR, AND MEMORY STORAGE DEVICE - A method for managing a buffer memory in a memory storage device is provided, wherein the memory storage device has a rewritable non-volatile memory module. The method includes transmitting temporary data from the buffer memory to a buffer area of the rewritable non-volatile memory module by using a pre-programmed command set, wherein the temporary data is not programmed into a storage area of the rewritable non-volatile memory module. The method also includes releasing a storage space storing the temporary data in the buffer memory and reloading the temporary data from the buffer area into the storage space of the buffer memory. Thereby, the method can temporarily increase available storage space of the buffer memory to meet the demand of additional operations. | 07-11-2013 |
20130179628 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes a memory and a controller. The controller controls the memory, communicates with a host device via a first signal line and a second signal line, and receives data items to be written in the memory from the host device on the first and second signal lines in a first period. The same group number is assigned to two data items which flow in parallel on the first and second signal lines. The controller transmits to the host device a response packet including an indication of a group number assigned to an unsuccessfully received one of the data items. | 07-11-2013 |
20130179629 | METHOD OF CONTROLLING MEMORY SYSTEM IN THE EVENT OF SUDDEN POWER OFF - A method of controlling a memory system that comprises a first flash memory device and a memory controller, the method comprising counting a first timeout when a sudden power off occurs, resetting the first flash memory device when the first timeout expires, and dumping data to the first flash memory device. | 07-11-2013 |
20130179630 | MEMORY SYSTEM - According to one embodiment, a memory system includes a nonvolatile semiconductor memory include a first area, and a second area smaller than the first area; and a controller configured to control data stored in the nonvolatile semiconductor memory, wherein the nonvolatile semiconductor memory is configured to store a first data accessible by a host command and to a second data inaccessible by the host command, and when receiving the host command, the controller writes the second data of the first area within the second area and initializes a first address information related the first data. | 07-11-2013 |
20130179631 | SOLID-STATE DISK (SSD) MANAGEMENT - SSD wear-level data ( | 07-11-2013 |
20130185476 | DEMOTING TRACKS FROM A FIRST CACHE TO A SECOND CACHE BY USING AN OCCUPANCY OF VALID TRACKS IN STRIDES IN THE SECOND CACHE TO CONSOLIDATE STRIDES IN THE SECOND CACHE - Information is maintained on strides configured in a second cache and occupancy counts for the strides indicating an extent to which the strides are populated with valid tracks and invalid tracks. A determination is made of tracks to demote from a first cache. A first stride is formed including the determined tracks to demote. The tracks from the first stride are to a second stride in the second cache having an occupancy count indicating the stride is empty. A determination is made of a target stride in the second cache based on the occupancy counts of the strides in the second cache. A determination is made of at least two source strides in the second cache having valid tracks based on the occupancy counts of the strides in the second cache. The target stride is populated with the valid tracks from the source strides. | 07-18-2013 |
20130185477 | VARIABLE LATENCY MEMORY DELAY IMPLEMENTATION - A method includes receiving, from a processor, a first read request mapped including a first read request address to a first memory location of a register array and a second read request including a second read request address to a second memory location of a register array. The method includes assigning a first simulated time delay to the first read request and assigning a second simulated time delay to the second read request. The method includes, in response to a first elapsed time being equal to the first simulated time delay, outputting a first read request response including first data. The first elapsed time commences upon receipt of the first read request. The method includes, in response to a second elapsed time being equal to the second simulated time delay, outputting a second read request response including second data. The second elapsed time commences upon receipt of the second read request. | 07-18-2013 |
20130185478 | POPULATING A FIRST STRIDE OF TRACKS FROM A FIRST CACHE TO WRITE TO A SECOND STRIDE IN A SECOND CACHE - Provided are a computer program product, system, and method for managing data in a cache system comprising a first cache, a second cache, and a storage system. A determination is made of tracks stored in the storage system to demote from the first cache. A first stride is formed including the determined tracks to demote. A determination is made of a second stride in the second cache in which to include the tracks in the first stride. The tracks from the first stride are added to the second stride in the second cache. A determination is made of tracks in strides in the second cache to demote from the second cache. The determined tracks to demote from the second cache are demoted. | 07-18-2013 |
20130185479 | DATA PROTECTING METHOD, MEMORY CONTROLLER AND MEMORY STORAGE APPARATUS - A data protecting method for protecting a sub-directory and at least one pre-stored file in a rewritable non-volatile memory module is provided. The method includes receiving a write command from a host system and determining whether a write address indicated by the write command is an address storing a file description block of the sub-directory. The method also includes, when the write address is the address storing a file description block of the sub-directory, determining whether a portion of data streams corresponding to the write command is the same as a corresponding content recorded in the file description block of the sub-directory. The method further includes, when the portion of data streams corresponding to the write command is not the same as the corresponding content recorded in the file description block of the sub-directory, transmitting a write failure signal to the host system. | 07-18-2013 |
20130185480 | STORAGE BALLOONING - One embodiment of the present invention provides a system for managing storage space in a mobile device. During operation, the system detects a decrease in available disk space in a host file system, wherein an image file for a guest system is stored in the host file system. In response to the detected decrease, the system increases a size of a balloon file in a storage of a guest system. The system then receives an indication of a TRIM or discard communication and intercepts the TRIM or discard communication. Next, the system determines that at least one block is free based on the intercepted TRIM or discard communication. Subsequently, the system frees a physical block corresponding to the at least one block in a storage of the host system and reduces a size of the image file for the guest system in accordance with the intercepted TRIM or discard communication. | 07-18-2013 |
20130185481 | SWITCHING DRIVERS BETWEEN PROCESSORS - Systems, methods, and computer software for operating a device can be used to operate the device in multiple modes. The device can be operated in a first operating mode adapted for processing data, in which a first processor executes a driver for a nonvolatile memory and a second processor performs processing of data stored in files on the nonvolatile memory. An instruction can be received to switch the device to a second operating mode adapted for reading and/or writing files from or to the nonvolatile memory. The driver for the nonvolatile memory can be switched from the first processor to the second processor in response to the instruction, and the driver for the nonvolatile memory can be executed on the second processor after performing the switch. A communications driver can be executed on the first processor in response to the instruction to switch the device to the second operating mode. | 07-18-2013 |
20130185482 | MEMORY SYSTEM USING A STORAGE HAVING FIRMWARE WITH A PLURALITY OF FEATURES - A memory system includes a host including a configuration controller to receive an input command and to output a configuration command corresponding to the input command, and a storage to be driven by firmware including a plurality of features, the storage including an adaptation controller to receive the configuration command from the configuration controller and to determine whether to enable each of the features. | 07-18-2013 |
20130185483 | DATA STORAGE SYSTEM, MEMORY CONTROLLER, NONVOLATILE MEMORY DEVICE, AND METHOD OF OPERATING THE SAME - A nonvolatile memory device includes: first through m-th word lines arranged sequentially and first through m-th pages connected respectively to the first through m-th word lines; a redundant array of inexpensive disks (RAID) controller generating first RAID parity data from first through (m−1)-th data; and an access controller connected to the RAID controller and capable of accessing the nonvolatile memory device, wherein the access controller programs the first through (m−1)-th data to the first through (m−1)-th pages and programs the first RAID parity data to the m-th page. | 07-18-2013 |
20130185484 | FILE PROGRAMMING METHOD AND ASSOCIATED DEVICE FOR NAND FLASH - A file programming method for a flash memory is provided. The method includes steps of: obtaining a section description file and corresponding allocation information and user data while generating burning files, wherein the section description file includes section description information of at least one section and the allocation information includes the number that the burning file is to be generated; determining a file type corresponding to a section file according to the section description information; and generating the burning files utilizing the user data according to section description information, the number that the burning file is to be generated corresponding to the section description information, and the file types corresponding to the section files. | 07-18-2013 |
20130185485 | Non-Volatile Memory Devices Using A Mapping Manager - Provided are storage devices that may include a non-volatile memory. The storage devices may also include a controller configured to perform a read operation on a physical page of the non-volatile memory in response to a read request on a logical page of the non-volatile memory from a host. The controller may include a mapping manager configured to manage a plurality of logical blocks by a logical unit. The mapping manager may include a unit map table including a correlation between the logical unit and a physical unit corresponding to the logical unit. Additionally, the mapping manager may be configured to change a mapping method according to whether the unit map table includes a physical unit corresponding to a logical unit including a logical page requested by the host. Related user devices and electronic devices are also provided. | 07-18-2013 |
20130185486 | STORAGE DEVICE, STORAGE SYSTEM, AND INPUT/OUTPUT CONTROL METHOD PERFORMED IN STORAGE DEVICE - A storage device includes a storage unit including a plurality of regions in which data is stored, the storage unit configured to input and output the data through channels and ways corresponding to the plurality of regions; an interface unit including a multi-entry queue, the multi-entry queue including a plurality of entries in which received commands are entered, the interface unit being configured to transmit data to be written in and read from the storage unit in response to the commands entered in the plurality of entries of the multi-entry queue; and a firmware unit configured to allocate the plurality of entries of the multi-entry queue corresponding to the commands received by the interface unit. | 07-18-2013 |
20130185487 | MEMORY SYSTEM AND MOBILE DEVICE INCLUDING HOST AND FLASH MEMORY-BASED STORAGE DEVICE - A memory system is provided which includes a storage device including a flash memory; and a host configured to request a storage device state and user pattern information via a user interface, to analyze the user pattern information, to set up a parameter of the storage device such that the storage device operates an optimization operation, according to the analyzing result, and to provide a command for the optimization operation to the storage device. | 07-18-2013 |
20130185488 | SYSTEMS AND METHODS FOR COOPERATIVE CACHE MANAGEMENT - A cache module leverages storage metadata to cache data of a backing store on a non-volatile storage device. The cache module maintains access metadata pertaining to access characteristics of logical identifiers in the logical address space, including access characteristics of un-cached logical identifiers (e.g., logical identifiers associated with data that is not stored on the non-volatile storage device). The access metadata may be separate and/or distinct from the storage metadata. The cache module determines whether to admit data into the cache and/or evict data from the cache using the access metadata. A storage module may provide eviction candidates to the cache module. The cache module may select candidates for eviction. The storage module may leverage the eviction candidates to improve the performance of storage recovery and/or grooming operations. | 07-18-2013 |
20130185489 | DEMOTING TRACKS FROM A FIRST CACHE TO A SECOND CACHE BY USING A STRIDE NUMBER ORDERING OF STRIDES IN THE SECOND CACHE TO CONSOLIDATE STRIDES IN THE SECOND CACHE - Information on strides configured in the second cache includes information indicating a number of valid tracks in the strides, wherein a stride has at least one of valid tracks and free tracks not including valid data. A determination is made of tracks to demote from the first cache. A first stride is formed including the determined tracks to demote. The tracks from the first stride are added to a second stride in the second cache that has no valid tracks. A target stride in the second cache is selected based on a stride most recently used to consolidate strides from at least two strides into one stride. Data from the valid tracks is copied from at least two source strides in the second cache to the target stride. | 07-18-2013 |
20130185490 | SEMICONDUCTOR MEMORY SYSTEM HAVING A SNAPSHOT FUNCTION - In a semiconductor memory computer equipped with a flash memory, use of backed-up data is enabled. The semiconductor memory computer includes an address conversion table for detecting physical addresses of at least two pages storing data by designating a logical address from one of logical addresses to be designated by a reading request. The semiconductor memory computer includes a page status register for detecting one page status allocated to each page, and page statuses to be detected include the at least following four statuses: (1) a latest data storage status, (2) a not latest data storage status, (3) an invalid data storage status, and (4) an unwritten status. By using the address conversion table and the page status register, at least two data s (latest data and past data) can be read for one designated logical address from a host computer. | 07-18-2013 |
20130191579 | APPARATUS AND METHOD FOR ENHANCING FLASH ENDURANCE BY ENCODING DATA - Input bits are stored in memory cells by mapping the input bits into a larger number of transformed bits using a shaping encoding that has a downward asymptotic bias with respect to a mapping of bit patterns to cell states and programming some of the cells according to that mapping of bit patterns to cell states. The programmed cells are erased before being programmed to store any other bits. The invention sacrifices memory capacity to increase endurance. | 07-25-2013 |
20130191580 | Controller, System, and Method for Mapping Logical Sector Addresses to Physical Addresses - A controller of a flash memory device exchanges data pages with the memory device via a host-type NAND interface and exchanges data sectors with a host via a flash-type NAND interface. The data sectors are different in size than the data pages. A data storage system includes the controller and the memory device. Another data storage system includes a memory whose physical pages have a common size and circuitry for exporting a flash-type NAND interface for exchanging data sectors, that differ in size from the physical pages, with a host. A data processing system includes the data storage system and the host. | 07-25-2013 |
20130191581 | MULTI-LAYER INPUT/OUTPUT PAD RING FOR SOLID STATE DEVICE CONTROLLER - Some embodiments of the disclosed subject matter include an integrated circuit. The integrated circuit includes a solid state device controller configured to control a plurality of flash memory devices, a first set of input output IO pads, coupled to the solid state device controller, arranged as a first pad ring around a perimeter of the integrated circuit, and a second set of IO pads arranged adjacent to at least one side of the first pad ring, wherein one of the second set of IO pads includes a power source node configured to receive a power supply voltage for the solid state device controller, a ground node, and a bond pad configured to receive an external signal. | 07-25-2013 |
20130191582 | Cache System Using Solid State Drive - A cache system for a storage device includes (i) one or more solid state drives (SSDs), (ii) one or more random access memories (RAMs), and (iii) a cache control device. The cache control device caches at least some of first data that is to be written to the storage device, and caches at least some of second data that is retrieved from the storage device. When caching first data or second data in one of the one or more RAMs, the cache control device writes to the one RAM non-sequentially with respect to a memory space of the one RAM. When caching first data or second data in one of the one or more SSDs, the cache control device writes to the one SSD sequentially with respect to a memory space of the one SSD. | 07-25-2013 |
20130191583 | CARD AND HOST APPARATUS - A host apparatus, into which a card having a nonvolatile semiconductor memory is inserted, issues a check command to the card. The check command instructs to send information on whether the card supports a termination process in which the card shifts into a state ready for a stop of power supply from the host apparatus. | 07-25-2013 |
20130198434 | Apparatus and Method to Provide Cache Move With Non-Volatile Mass Memory System - A method includes, in one non-limiting embodiment, receiving a command originating from an initiator at a controller associated with a non-volatile mass memory coupled with a host device, the command being a command to write data that is currently resident in a memory of the host device to the non-volatile mass memory; moving the data that is currently resident in the memory of the host device from an original location to a portion of the memory allocated for use at least by the non-volatile mass memory; and acknowledging to the initiator that the command to write the data to the non-volatile mass memory has been executed. An apparatus configured to perform the method is also described. | 08-01-2013 |
20130198435 | MEMORY PAGE EVICTION PRIORITY IN MOBILE COMPUTING DEVICES - Eviction priority technologies provide for the prioritized eviction of memory pages from a first memory, such as a DRAM, in a mobile computing device that have been copied from a second memory, such as flash memory. Eviction priority is based on eviction costs for the memory pages. The eviction cost for a page is based on page-in costs, page-out costs, the priority of a process associated with the page, page access probability and combinations thereof. Page-in costs include read costs, fixup costs and decompression costs, and page-out costs include write-back costs and compression costs. Page lists allow for the sorting of pages by page type (e.g., read only, read/write) and can be used to keep track of eviction costs. Pages are evicted from the first memory in order of increasing eviction cost. | 08-01-2013 |
20130198436 | IMPLEMENTING ENHANCED DATA PARTIAL-ERASE FOR MULTI-LEVEL CELL (MLC) MEMORY USING THRESHOLD VOLTAGE-DRIFT OR RESISTANCE DRIFT TOLERANT MOVING BASELINE MEMORY DATA ENCODING - A method and apparatus are provided for implementing enhanced data partial erase for multi-level cell (MLC) memory using threshold-voltage-drift or resistance-drift tolerant moving baseline memory data encoding. A data partial erase for data written to the MLC memory using threshold-voltage-drift or resistance-drift tolerant moving baseline memory data encoding is performed, and a data re-write after the partial erase to the MLC memory is performed using threshold-voltage-drift or resistance-drift tolerant moving baseline memory data encoding. A data partial erase cycle includes a duration and voltage level based upon a degradation of the MLC memory cells. | 08-01-2013 |
20130198437 | MEMORY MANAGEMENT DEVICE AND MEMORY MANAGEMENT METHOD - In an embodiment, a device includes a first unit, a second unit, and a third unit. The first unit generates a write address representing a write position to sequentially store sequential data from a processor to a nonvolatile main memory. The second unit generates order information representing a degree of newness of write. The third unit writes sequentially writes the sequential data at the write address with the order information. | 08-01-2013 |
20130198438 | DATA STORAGE APPARATUS AND METHOD FOR COMPACTION PROCESSING - According to one embodiment, a data storage apparatus includes a flash memory and a controller. The controller includes a compaction processor. The compaction processor performs the compaction processing on the flash memory, to dynamically set a range of compaction processing targets based on a number of available blocks and an amount of valid data in each of the blocks, and to search the range of compaction processing targets for blocks each with a relatively small amount of valid data as the target blocks for the compaction processing. | 08-01-2013 |
20130198439 | NON-VOLATILE STORAGE - The non-volatile storage SSD has non-volatile NVM, RAM capable of being accessed at a higher speed than this NVM, and a control unit for controlling accesses to the NVM and to the RAM. The control unit stores in the NVM an address translation table (LPT) that translates a logical address given to access this NVM to a physical address after dividing it into multiple tables, and stores in the RAM the multiple address translation tables-sub on RAM (LPT-SRs) that have been divided into multiple tables. | 08-01-2013 |
20130198440 | NONVOLATILE MEMORY DEVICE, MEMORY SYSTEM HAVING THE SAME AND BLOCK MANAGING METHOD, AND PROGRAM AND ERASE METHODS THEREOF - In one embodiment, the method includes overwriting a memory cell storing m-bit data to store n-bit data, where n is less than or equal to m. The memory cell has one of a first plurality of program states when storing the m-bit data, and the memory cell has one of a second plurality of program states when storing the n-bit data. The second plurality of program states include at least one program state not in the first plurality of program states. | 08-01-2013 |
20130198441 | SEMICONDUCTOR DEVICE WITH COPYRIGHT PROTECTION FUNCTION - A semiconductor device includes a serial communication interface connector, a non-volatile semiconductor memory, a memory controller, and a memory reader/writer. The serial communication interface connector is capable of being connected to a serial communication interface terminal of electronic equipment. The memory controller includes a memory interface connected to the non-volatile semiconductor memory and a copyright protection function and controls the non-volatile semiconductor memory. The memory reader/writer includes a controller interface connected to the memory controller and a serial communication interface connected to the serial communication interface connector. | 08-01-2013 |
20130198442 | HUMAN INTERFACE MODULE FOR MOTOR DRIVE - A power electronics device with an improved human interface module (HIM) is provided. More specifically, a motor drive is provided that includes a HIM with a portable memory device that stores the programming configuration of the motor drive. The improved HIM with portable memory enables improved techniques for quickly and efficiently updating the programming configuration of one or several motor drives. | 08-01-2013 |
20130198443 | SYSTEMS AND METHODS FOR PROGRAMMING A PLURALITY OF MOTOR DRIVES - The embodiments describe a control system and a method for programming a plurality of motor drives. One embodiment provides a control system including a workstation configured to acquire a configuration file, in which the configuration file is indicative of a programming configuration of a motor drive. The control system further includes a plurality of motor drives communicatively coupled to the workstation. The workstation is configured to transfer the configuration file to each of the plurality of motor drives, and each of the plurality of motor drives is configured to update the programming configuration associated with the motor drive based on the configuration file. | 08-01-2013 |
20130198444 | Enabling Throttling on Average Write Throughput for Solid State Storage Devices - A mechanism is provided for enabling throttling on average write throughput instead of peak write throughput for solid-state storage devices. The mechanism assures an average write throughput within a range but allows excursions of high throughput with periods of low throughput offsetting against those of heavy usage. The mechanism periodically determines average throughput and determines whether average throughput exceeds a high throughput threshold for a certain amount of time without being offset by periods of low throughput. | 08-01-2013 |
20130205065 | METHODS AND STRUCTURE FOR AN IMPROVED SOLID-STATE DRIVE FOR USE IN CACHING APPLICATIONS - Methods and structure for an improved solid-state drive (SSD) for use in caching applications. An improved SSD comprises both volatile and non-volatile memory. The volatile memory provides improved performance as compared to present SSDs for use in caching application. The improved SSD senses impending failure of external power applied to the SSD and, while adequate power remains, copies cached data from the volatile memory to the non-volatile memory to retain the data through the power loss. In some embodiments, a local power source may be present to assure sufficient time for the SSD to save cached data in the non-volatile memory. Since the volatile memory (e.g., DRAM) is used for the primary caching function and the non-volatile memory is rarely used, performance, reliability and cost goals are achieved for write cache applications. | 08-08-2013 |
20130205066 | ENHANCED WRITE ABORT MANAGEMENT IN FLASH MEMORY - A memory system or flash card may include safe zone blocks where data is written in case of an error condition, such as a write abort. The system may utilize predetermined risk zones when selecting the data that is written to the safe zone blocks. For example, data written to a lower page may be one example of data that is a predetermined risk. Upon receiving a write command, the data that is written to a lower page may be written to a safe zone either in parallel or after the write operation. | 08-08-2013 |
20130205067 | Storage Device Aware of I/O Transactions and Stored Data - A storage device that is aware of I/O transactions and stored data is provided. In one embodiment, a storage device identifies a type of data stored in each logical partition of the storage device. When the storage device receives a request from the host device to access a logical partition of the memory, the storage device handles the request based on the identified type of data stored in the logical partition. Other embodiments are disclosed, and each of the embodiments can be used alone or together in combination. | 08-08-2013 |
20130205068 | Storage Device and Method for Utilizing Unused Storage Space - A storage device and method for utilizing unused storage space are provided. In one embodiment, a storage device identifies unused storage space in the memory. The storage device then performs risk analysis on the identified unused storage space. Based on the risk analysis, the storage device uses the identified unused storage space for an internal storage device operation. Other embodiments are disclosed, and each of the embodiments can be used alone or together in combination. | 08-08-2013 |
20130205069 | System for Out of Band Management of Rack-Mounted Field Replaceable Units - A system for the management of rack-mounted field replaceable units (FRUs) that affords the enhanced availability and serviceability of FRUs provided by blade-based systems but in a manner that accommodates different types of FRUs (e.g., in relation to form factors, functionality, and the like) installed within a rack or cabinet. | 08-08-2013 |
20130205070 | STORAGE APPARATUS PROVIDED WITH A PLURALITY OF NONVOLATILE SEMICONDUCTOR STORAGE MEDIA AND STORAGE CONTROL METHOD - A storage apparatus is provided with a plurality of nonvolatile semiconductor storage media and a storage controller that is a controller that is coupled to the plurality of semiconductor storage media. The storage controller identifies a first semiconductor storage unit that is at least one semiconductor storage media and a second semiconductor storage unit that is at least one semiconductor storage media and that is provided with a remaining length of life shorter than that of the first semiconductor storage unit based on the remaining life length information that has been acquired. The storage controller moreover identifies a first logical storage region for the first semiconductor storage unit and a second logical storage region that is provided with a write load higher than that of the first logical storage region for the second semiconductor storage unit based on the statistics information that indicates the statistics that is related to a write for every logical storage region. The storage controller reads data from the first logical storage region and the second logical storage region, and writes data that has been read from the first logical storage region to the second logical storage region and/or writes data that has been read from the second logical storage region to the first logical storage region. | 08-08-2013 |
20130205071 | COMPRESSED CACHE STORAGE ACCELERATION - In described embodiments, compressed cache storage acceleration employs compression and caching together in a combination to provide a performance gain. A layered file system includes a filter layer for the file system that selectively identifies and compresses data with the knowledge of the file structure before being stored in local cache memory or on a storage medium. Selection of compressed and uncompressed data for relatively immediate access is determined by monitoring access patterns and generating an access profile. The compressed and uncompressed data is locally stored and accessed in the cache, which might be Flash memory, to provide the performance gain. | 08-08-2013 |
20130205072 | ASYNCHRONOUS BAD BLOCK MANAGEMENT IN NAND FLASH MEMORY - Methods for receiving data from a file system and storing it in a flash storage medium, wherein a bad block management process comprises queuing, at a bad block manager, one or more write requests, and receiving data associated with each of the one or more write requests and storing the received data in the bad block manager buffer; and performing cache management of data in the bad block manager buffer and subsequently returning a success status to the file system; and executing the one or more queued write requests in a separate task, wherein the executing comprises programming the received data to the flash storage medium during the bad block management process. Corresponding devices are also provided. | 08-08-2013 |
20130205073 | MEMORY DEVICE, MEMORY SYSTEM, AND PROGRAMMING METHOD THEREOF - A memory device, a memory system, and a programming method thereof. The memory system includes a memory controller configured to set first type offset information corresponding to a first type of data and set second type offset information corresponding to a second type of data; and a memory device configured to receive the first type offset information to program the first type of data in a first type of page that is read at a first speed and receive the second type offset information to program the second type of data in a second type of page that is read at a second speed, the first speed being different from the second speed. | 08-08-2013 |
20130205074 | DATA I/O CONTROLLER AND SYSTEM INCLUDING THE SAME - A controller controls data input/output for a semiconductor memory device. The controller includes a first buffer configured to perform data transmission between an interface and the semiconductor memory device, a first control unit configured to control the semiconductor memory device according to an external request, and a second control unit configured to control the first buffer and the first control unit to simultaneously process a plurality of external requests according to a pipeline scheme. | 08-08-2013 |
20130205075 | NONVOLATILE MEMORY DEVICE AND MEMORY CARD INCLUDING THE SAME - There is provided a nonvolatile memory device including a memory cell array including nonvolatile memory cells, a battery not supplied with external power and configured to store a charged voltage, a sensing unit configured to sense a degradation state of the nonvolatile memory cells of the memory cell array, and a trigger circuit configured to transmit a refresh trigger signal based on the sensing result, wherein the nonvolatile memory cells of the memory cell array are refreshed using the charged voltage provided by the battery in response to the trigger signal transmitted from the trigger circuit. | 08-08-2013 |
20130205076 | APPARATUS, METHODS AND ARCHITECTURE TO INCREASE WRITE PERFORMANCE AND ENDURANCE OF NON-VOLATILE SOLID STATE MEMORY COMPONENTS - A solid-state mass storage device for use with host computer systems, and methods of increasing the endurance of non-volatile memory components thereof that define a first non-volatile memory space. The mass storage device further has a second non-volatile memory space containing at least one non-volatile memory component having a higher write endurance than the memory components of the first non-volatile memory space. The second non-volatile memory space functions as a low-pass filter for host writes to the first non-volatile memory space to minimize read accesses to the first non-volatile memory space. Contents of the second non-volatile memory space are managed using a change counter. | 08-08-2013 |
20130205077 | PROMOTION OF PARTIAL DATA SEGMENTS IN FLASH CACHE - For efficient track destage in secondary storage in a more effective manner, for temporal bits employed with sequential bits for controlling the timing for destaging the track in a primary storage, the temporal bits and sequential bits are transferred from the primary storage to the secondary storage. The temporal bits are allowed to age on the secondary storage. | 08-08-2013 |
20130205078 | Extending Cache for an External Storage System into Individual Servers - Mechanisms are provided for extending cache for an external storage system into individual servers. Certain servers may have cards with cache in the form of dynamic random access memory (DRAM) and non-volatile storage, such as flash memory or solid-state drives (SSDs), which may be viewed as actual extensions of the external storage system. In this way, the storage system is distributed across the storage area network (SAN) into various servers. Several new semantics are used in communication between the cards and the storage system to keep the read caches coherent. | 08-08-2013 |
20130205079 | SYSTEMS AND METHODS FOR THE IDENTIFICATION AND/OR DISTRIBUITION OF MUSIC AND OTHER FORMS OF USEFUL INFORMATION - The present invention relates generally to the field of telecommunications systems and methods. More specifically, the present invention is directed to systems and methods for identifying and/or distributing music and other types of useful information for users in a very simple and convenient manner. A variety of systems and methods are disclosed which provide users with quick and convenient access to various forms of information, such as, for example, audio information including music and news items as well as coupons and other information. The systems and methods allow users to store data representative of a time of transmission and preferably a source of transmission so that data of interest may be identified for ordering an/or downloading. | 08-08-2013 |
20130212315 | STATE RESPONSIVEOPERATIONS RELATING TO FLASH MEMORY CELLS - A non-transitory computer readable medium, a flash controller and a method for state responsive encoding and programming; the method may include encoding an information entity by applying a state responsive encoding process to provide at least one codeword; wherein the state responsive encoding process is responsive to a state of flash memory cells; and programming the at least one codeword to at least one group of flash memory cells by applying a state responsive programming process that is responsive to the state, the state being either an estimated state or an actual state. | 08-15-2013 |
20130212316 | CONFIGURABLE FLASH INTERFACE - A flash memory controller, a non-transitory computer readable medium and a method for performing operations with a flash memory device, the method may include receiving, by a flash memory controller, a request to perform a requested operation with the flash memory device; selecting multiple selected instructions to be executed by a programmable module of the flash memory controller, based upon (a) an interface specification supported by the flash memory device and (b) the requested operation; wherein the programmable module comprising multiple operation phase circuits; and executing the multiple selected instructions by the programmable module, wherein the executing of the multiple selected instructions comprises executing a plurality of selected instructions by multiple operation phase circuits; wherein different operation phase circuits are arranged to execute different operation phases of the requested operation. | 08-15-2013 |
20130212317 | Storage and Host Devices for Overlapping Storage Areas for a Hibernation File and Cached Data - Storage and host devices are provided for overlapping storage areas for a hibernation file and cached data. In one embodiment, a storage device is provided that receives a command from a host device to evict cached data in a first address range of the memory. The storage device then receives a command from the host device to store a hibernation file in a second address range of the memory, wherein the second address range does not exist in the memory. The storage device maps the second address range to the first address range and stores the hibernation file in the first address range. In another embodiment, a host device is provided that sends a command to a first storage device to evict cached data in a first address range of the first storage device's memory. The host device then sends a command to the first storage device to store a hibernation file in the first address range. | 08-15-2013 |
20130212318 | ARCHITECTURE FOR ADDRESS MAPPING OF MANAGED NON-VOLATILE MEMORY - The disclosed architecture uses address mapping to map a block address on a host interface to an internal block address of a non-volatile memory (NVM) device. The block address is mapped to an internal chip select for selecting a Concurrently Addressable Unit (CAU) identified by the block address. The disclosed architecture supports generic NVM commands for read, write, erase and get status operations. The architecture also supports an extended command set for supporting read and write operations that leverage a multiple CAU architecture. | 08-15-2013 |
20130212319 | MEMORY SYSTEM AND METHOD OF CONTROLLING MEMORY SYSTEM - According to one embodiment, a controller reads out the non-volatile address management information required to execute one of the read commands into an address information cache and retrieves data from the nonvolatile memory according to the volatile address management information stored in the address information cache. In addition, the controller among the read commands stored in the command queue, preferentially executes the read command whose logical addresses are all found in the volatile address management information. | 08-15-2013 |
20130212320 | NON-VOLATILE MEMORY CONTROLLER PROCESSING NEW REQUEST BEFORE COMPLETING CURRENT OPERATION, SYSTEM INCLUDING SAME, AND METHOD - A non-volatile memory controller, system and method capable of processing a next request as an interrupt before completing a current operation are disclosed. The non-volatile memory system includes a first memory storing meta data loaded from a flash memory; a second memory storing the meta data copied from the first memory; and a flash memory controller copying the meta data from the first memory to the second memory, changing the meta data in the second memory, and then re-copying the changed meta data from the second memory to the first memory during a first-type operation that requires changes in the meta data. | 08-15-2013 |
20130212321 | Apparatus, System, and Method for Auto-Commit Memory Management - Apparatuses, systems, methods, and computer program products are disclosed. A method includes receiving a request to copy data from a first location to a second location. The data may be associated with an identifier known to a client that initiated the request. One of the locations may include an auto-commit buffer of a non-volatile device. An auto-commit buffer may be configured to commit stored data from the auto-commit buffer to a non-volatile medium of a non-volatile device in response to a restart event. A method includes copying the data from the first location to the second location. A method includes preserving the identifier known to the client and an association between the identifier and a location of the data at the second location such that client can retrieve the data based on the identifier known to the client. | 08-15-2013 |
20130212322 | TECHNIQUES FOR REDUCING MEMORY WRITE OPERATIONS USING COALESCING MEMORY BUFFERS AND DIFFERENCE INFORMATION - Techniques are described for reducing write operations in memory. In use, write operations to be performed on data stored in memory are identified. A difference is then determined between results of the write operations and the data stored in the memory. Difference information is stored in coalescing memory buffers. To this end, the write operations may be reduced, utilizing the difference information. | 08-15-2013 |
20130212323 | INFORMATION PROCESSING DEVICE, EXTERNAL STORAGE DEVICE, HOST DEVICE, RELAY DEVICE, CONTROL PROGRAM, AND CONTROL METHOD OF INFORMATION PROCESSING DEVICE - According to the embodiments, an external storage device switches to an interface controller for supporting only a read operation of nonvolatile memory when a shift condition for shifting to a read only mode is met. A host device switches to an interface driver for supporting only the read operation of the nonvolatile memory when determining to recognize as read only memory based on information acquired from the external storage device. | 08-15-2013 |
20130212324 | INFORMATION PROCESSING DEVICE, EXTERNAL STORAGE DEVICE, HOST DEVICE, RELAY DEVICE, CONTROL PROGRAM, AND CONTROL METHOD OF INFORMATION PROCESSING DEVICE - According to the embodiments, an external storage device switches to an interface controller for supporting only a read operation of nonvolatile memory when a shift condition for shifting to a read only mode is met. A host device switches to an interface driver for supporting only the read operation of the nonvolatile memory when determining to recognize as read only memory based on information acquired from the external storage device. | 08-15-2013 |
20130212325 | INFORMATION PROCESSING DEVICE, EXTERNAL STORAGE DEVICE, HOST DEVICE, RELAY DEVICE, CONTROL PROGRAM, AND CONTROL METHOD OF INFORMATION PROCESSING DEVICE - According to the embodiments, an external storage device switches to an interface controller for supporting only a read operation of nonvolatile memory when a shift condition for shifting to a read only mode is met. A host device switches to an interface driver for supporting only the read operation of the nonvolatile memory when determining to recognize as read only memory based on information acquired from the external storage device. | 08-15-2013 |
20130212326 | MEMORY SYSTEM - A controller includes an identification information management table that manages identification information indicating, for each of addresses in second-management unit, whether one or more data in first management unit belonging to the addresses is stored in the second or the third storing area. When the controller executes a process of flushing data from the first storing area to the second storing area or the third storing area, the controller updates the identification information in the identification information management table. The controller executes a process of reading data from the second storing area or the third storing area by referring to the identification information. As a result, the speed of searches conducted in the management table is increased. | 08-15-2013 |
20130212327 | COMPOSITE SOLID STATE DRIVE IDENTIFICATION AND OPTIMIZATION TECHNOLOGIES - Technologies for an operating system identifying SSD and CSSD devices based on a corresponding descriptor, and for optimizing operating system functionalities with respect to the SSD/CSSD device. Optimizations include disabling non-SSD/CSSD functionalities, such as HDD defragmentation, and by enabling SSD/CSSD specific functionalities, such as write optimization storage functionalities. | 08-15-2013 |
20130219105 | METHOD, DEVICE AND SYSTEM FOR CACHING FOR NON-VOLATILE MEMORY DEVICE - Example embodiments described herein may relate to memory devices, and may relate more particularly to caching for non-volatile memory devices. | 08-22-2013 |
20130219106 | TRIM TOKEN JOURNALING - Systems and methods are disclosed for trim token journaling. A device can monitor the order in which trim commands and write commands are applied to an indirection system stored in a volatile memory of the device. In some embodiments, the device can directly write to a page of an NVM with a trim token that indicates that a LBA range stored in the page has been trimmed. In other embodiments, a device can add pending trim commands to a trim buffer stored in the volatile memory. Then, when the trim buffer reaches a pre-determined threshold or a particular trigger is detected, trim tokens associated with all of the trim commands stored in the trim buffer can be written to the NVM. Using these approaches, the same sequence of events that was applied to the indirection system during run-time can be applied during device boot-up. | 08-22-2013 |
20130219107 | WRITE ABORT RECOVERY THROUGH INTERMEDIATE STATE SHIFTING - A memory system or flash card may include a multi-level cell block with multiple states. Before the upper page is written, an intermediate state may be shifted to prevent or minimize overlapping of the states from the corresponding lower page. A write abort during the writing of the upper page will not result in a loss of data from the corresponding lower page. | 08-22-2013 |
20130219108 | Method, Memory Controller and System for Reading Data Stored in Flash Memory - An exemplary method for reading data stored in a flash memory. The method includes: controlling the flash memory to perform a read operation upon a first page of the flash memory; obtaining a first codeword of the first page; obtaining a first set of log-likelihood ratio (LLR) mapping values of the first codeword according to a first LLR mapping rule; performing an error correction operation according to the first set of LLR mapping values; obtaining a second set of LLR values of the first codeword according to a second LLR mapping rule, if the error correction operation performed according to the first set of LLR mapping values indicates an uncorrectable result; and performing the error correction operation according to the second set of LLR mapping values. | 08-22-2013 |
20130219109 | MEMORY SYSTEM AND PROGRAM METHOD THEREOF - A memory system includes a nonvolatile memory device having a first data area storing M-bit data using a buffer program operation and a second data area storing N-bit data (N being an integer larger than M) using a main program operation and a memory controller configured to control the nonvolatile memory device. When a main program operation using data stored at the first and second data areas is required, the memory controller calculates values indicating a performance of the required main program operation to be executed according to a plurality of main program manners, selects one of the plurality of main program manners based on the calculated values, and controls the nonvolatile memory device to perform the required main program operation according to the selected main program manner. | 08-22-2013 |
20130219110 | ELECTRONIC APPARATUSES - Electronic apparatus, comprising: non-volatile memory configured to be written to or read from in memory portions which are erased a sector at a time, each said sector comprising a plurality of said portions, and the memory having at least three said sectors each of which is adapted to be erased independently of the others; and control means operable to control erasing of the sectors, wherein: the control means is configured to store in a plurality of the sectors other than a target said sector erasure information concerning an erasure procedure, the erasure procedure involving erasing the target sector, so that such information in the sectors may be inspected to establish a suitable recovery procedure following an interruption event. | 08-22-2013 |
20130219111 | SYSTEM AND METHOD FOR READ-WHILE-WRITE WITH NAND MEMORY DEVICE - System, method, and program to perform simultaneous read and write operations in a NAND-type memory device, including: assigning a first partition in a NAND-type memory device, wherein the first partition is configured to perform read operations on high priority read content; assigning a second partition in the NAND-type memory device, wherein the second partition is configured to perform read operations and write operations, wherein the read operations are performed on non-high priority read content; and controlling the first partition and second partition to operate in a simultaneous manner. | 08-22-2013 |
20130219112 | MANAGING MEMORY SYSTEMS CONTAINING COMPONENTS WITH ASYMMETRIC CHARACTERISTICS - A memory controller (MC) is associated with a remapping table to enable access to content in a memory system that includes asymmetric memory. The MC receives a request for a memory read or an Input/Output (I/O) write from a central processing unit (CPU) for a physical address specified by the system's memory management unit (MMU). The CPU uses the MMU to manage memory operations for the CPU, by translating the virtual addresses associated with CPU instructions into physical addresses representing system memory or I/O locations. The MC for asymmetric memories is configured to process the MMU-specified physical addresses as an additional type of virtual addresses, creating a layer of abstraction between the physical address specified by the MMU and the physical memory address with which that address is associated by the MC. The MC shields the CPU from the computational complexities required to implement a memory system with asymmetric components. | 08-22-2013 |
20130219113 | MEMORY SYSTEM CONTROLLER - The present disclosure includes methods and devices for a memory system controller. In one or more embodiments, a memory system controller includes a host interface communicatively coupled to a system controller. The system controller has a number of memory interfaces, and is configured for controlling a plurality of intelligent storage nodes communicatively coupled to the number of memory interfaces. The system controller includes logic configured to map between physical and logical memory addresses, and logic configured to manage wear level across the plurality of intelligent storage nodes. | 08-22-2013 |
20130219114 | COMBINED MOBILE DEVICE AND SOLID STATE DISK WITH A SHARED MEMORY ARCHITECTURE - A mobile device includes a system-on-chip (SOC) that includes a mobile device control module, a solid state disk (SSD) control module, and a random access memory (RAM) control module. The mobile device control module executes application programs for the mobile device. The solid-state disk (SSD) control module controls SSD operations. The RAM control module communicates with the mobile device control module and the SSD control module and stores both SSD-related data and mobile device-related data in a single RAM. | 08-22-2013 |
20130227194 | ACTIVE NON-VOLATILE MEMORY POST-PROCESSING - A computing node includes an active Non-Volatile Random Access Memory (NVRAM) component which includes memory and a sub-processor component. The memory is to store data chunks received from a processor core, the data chunks comprising metadata indicating a type of post-processing to be performed on data within the data chunks. The sub-processor component is to perform post-processing of said data chunks based on said metadata. | 08-29-2013 |
20130227195 | METHOD AND APPARATUS UTILIZING NON-UNIFORM HASH FUNCTIONS FOR PLACING RECORDS IN NON-UNIFORM ACCESS MEMORY - Method and apparatus for storing records in non-uniform access memory. In various embodiments, the placement of records is localized in one or more regions of the memory. This can be accomplished utilizing different ordered lists of hash functions to preferentially map records to different regions of the memory to achieve one or more performance characteristics or to account for differences in the underlying memory technologies. For example, one ordered list of hash functions may localize the data for more rapid access. Another list of hash functions may localize the data that is expected to have a relatively short lifetime. Localizing such data may significantly improve the erasure performance and/or memory lifetime, e.g., by concentrating the obsolete data elements in one location. Thus, the two or more lists of ordered hash functions may improve one or more of access latency, memory lifetime, and/or operation rate. | 08-29-2013 |
20130227196 | CIRCUIT AND METHOD FOR INITIALIZING A COMPUTER SYSTEM - A circuit for use in a computing system including and a bus interface unit and an autoload controller. The autoload controller has an input to receive an initialization signal. In response to receiving the initialization signal, autoload controller searches for a signature using the bus interface unit and, in response to finding the signature at a signature address, loads a plurality of base addresses corresponding to a plurality of controllers from memory locations having a predetermined relationship to the address, and provides the plurality of base addresses to a control output thereof. | 08-29-2013 |
20130227197 | MULTIPLE PRE-DRIVER LOGIC FOR IO HIGH SPEED INTERFACES - A memory system or flash card may include a controller interface for communicating with a host. The interface utilizes multiple pre-driver logic blocks that are tolerant to different voltages. For example, one block may use gate oxide devices tolerant to IO low voltage that speed up the delay path during low voltage operation, while a second block may use gate oxide devices tolerant to IO higher voltage for backwards compatibility with devices that operate at a high IO voltage. This allows the interface to take advantage of the IO low voltage device speed for multi-purpose IO use, while still being used for both low voltage and higher voltage protocols. | 08-29-2013 |
20130227198 | FLASH MEMORY DEVICE AND ELECTRONIC DEVICE EMPLOYING THEREOF - A flash memory device and an electronic device employing thereof are provided for efficiently processing data that is larger than a page size of a data block and for processing data that is smaller than the page size of the data block. The flash memory device preferably includes a plurality of flash arrays therein and the plurality of flash arrays is divided into partitions depending on at least two or more page sizes, thereby advantageously improving the performance of random write. | 08-29-2013 |
20130227199 | FLASH MEMORY STORAGE SYSTEM AND ACCESS METHOD - The present disclosure relates, according to some embodiments, to a data writing method in a storage system. The method comprises receiving data by the storage media controller, reading a non-volatile memory operation mode in the memory unit by a central control unit, in which the mode corresponds to a data reliability lower than the data reliability requirement of the storage system, reading a data reliability reduction condition in the memory unit by the central control unit, determining whether a system information related to the data meets the condition by the central control unit, and controlling the media control unit to write the data into the non-volatile memory according to the mode by the central control unit when the system information meets the condition. | 08-29-2013 |
20130227200 | DETERMINING BIAS INFORMATION FOR OFFSETTING OPERATING VARIATIONS IN MEMORY CELLS BASED ON WORDLINE ADDRESS - Disclosed is an apparatus and method for providing memory cell bias information for use in memory operations. One or more memory die are selected from a group of memory die, and one or more memory blocks selected from the selected one or more memory die. A group of cells are programmed within the selected memory blocks, and one or more distributions of cell program levels associated with a group of wordlines are determined. A bias value for each wordline is then generated based on comparing one or more program levels in a distribution of program levels associated with the respective wordline with predetermined programming levels. The bias values are stored lookup table that is configured to be accessible at runtime by a memory controller for retrieval of the bias value during a program or read operation. | 08-29-2013 |
20130227201 | Apparatus, System, and Method for Accessing Auto-Commit Memory - Apparatuses, systems, methods, and computer program products are disclosed for providing access to auto-commit memory. An auto-commit memory module is configured to cause an auto-commit memory to commit stored data to a non-volatile memory medium in response to a failure condition. A mapping module is configured to determine whether to associate a range of data with the auto-commit memory. A bypass module is configured to service a request for the range of data directly from the auto-commit memory in response to the auto-commit mapping module determining to associate the range of data with the auto-commit memory. | 08-29-2013 |
20130227202 | IMPLEMENTING RAID IN SOLID STATE MEMORY - The present disclosure includes systems and techniques relating to implementing fault tolerant data storage in solid state memory. In some implementations, a method includes receiving a request for data stored in a solid state memory, and identifying a logical block grouping for logical data blocks of the requested data, the logical data blocks corresponding to the solid state memory, and the logical block grouping comprising at least one physical data storage block from two or more solid state physical memory devices. The method also includes reading the stored data and a code stored in the identified logical block grouping, and comparing the code to the stored data to assess the requested data. | 08-29-2013 |
20130227203 | DYNAMIC SLC/MLC BLOCKS ALLOCATIONS FOR NON-VOLATILE MEMORY - Apparatus and methods are disclosed, such as those that provide dynamic block allocations in NAND flash memory between single-level cells (SLC) and multi-level cells (MLC) based on characteristics. In one embodiment, a memory controller dynamically switches between programming and/or reprogramming blocks between SLC mode and MLC mode based on the amount of memory available for use. When memory usage is low, SLC mode is used. When memory usage is high, MLC mode is used. Dynamic block allocation allows a memory controller to obtain the performance and reliability benefits of SLC mode while retaining the space saving benefits of MLC mode. | 08-29-2013 |
20130227204 | Mask-Programmed Read-Only Memory with Reserved Space - The present invention discloses a mask-ROM with reserved space (mask-ROM | 08-29-2013 |
20130227205 | Data Transfer in Memory Card System - A memory card system includes a host that issues a read command and a memory card that upon receiving the read command sends read data to the host in synchronism with a read clock signal generated within the memory card. In addition, the memory card sends the read clock signal to the host, and the host receives the read data in synchronism with the read clock signal, for increasing the allowable setup time period at the host. | 08-29-2013 |
20130227206 | METADATA STORAGE ASSOCIATED WITH WEAR-LEVEL OPERATION REQUESTS - A method includes responding to a wear-level operation request by copying data from a first portion of a first memory array to a second portion of the first memory array, and copying metadata associated with the data from a third portion of a second memory array to a fourth portion of the second memory array. The first memory array includes a NAND or NAND-based memory array, and the second memory array includes non-volatile memory including at least one of the group consisting of: phase-change memory, EEPROM, and NOR flash memory. | 08-29-2013 |
20130227207 | ADVANCED MANAGEMENT OF A NON-VOLATILE MEMORY - A method of managing a non-volatile memory device, the method comprising: receiving data sectors; writing each data sector into a data block that is allocated to a memory space subset that is associated with the data sector; wherein the data block belongs to a buffer of the non-volatile memory device; maintaining a management data structure that comprises location metadata about a location of each data sector in the buffer; and merging, if a criterion is fulfilled and before the buffer becomes full, data sectors stored at different data blocks and belong to a same set of logical memory blocks into a sequential portion of the non-volatile memory device, wherein the sequential portion differs from the buffer. | 08-29-2013 |
20130227208 | MEMORY SYSTEM - A memory system includes a management-information restoring unit. The management-information restoring unit determines whether a short break has occurred referring to a pre-log or a post-log in a NAND memory. The management-information restoring unit determines that a short break has occurred when the pre-log or the post-log is present in the NAND memory. In that case, the management-information restoring unit determines timing of occurrence of the short break, and, after selecting a pre-log or a post-log used for restoration, performs restoration of the management information reflecting these logs on a snapshot. Thereafter, the management-information restoring unit applies recovery processing to all write-once blocks in the NAND memory, takes the snapshot again, and opens the snapshot and the logs in the past. | 08-29-2013 |
20130232290 | REDUCING WRITE AMPLIFICATION IN A FLASH MEMORY - An apparatus having a memory circuit and a manager is disclosed. The memory circuit generally has (i) one or more Flash memories and (ii) a memory space that spans a plurality of memory addresses. The manager may be configured to (i) receive data items in a random order from one or more applications, (ii) write the data items in an active one of a plurality of regions in a memory circuit and (iii) mark the memory addresses in the active region that store the data items as used. Each data item generally has a respective host address. The applications may be executed in one or more computers. The memory addresses in the active region may be accessed in a sequential order while writing the data items to minimize a write amplification. The random order is generally preserved between the data items while writing in the active region. | 09-05-2013 |
20130232291 | Transfer Command with Specified Sense Threshold Vector Component - Various embodiments of the present disclosure are generally directed to the accessing of data in a memory, such as but not limited to a flash memory array. In accordance with some embodiments, a transfer command is received to transfer selected data between a control module and a memory module. The transfer command specifies a target address in the memory module and a sense threshold vector associated with the selected data. The sense threshold vector in the received transfer command is used to sense a programmed state of at least one solid-state memory cell at the target address responsive to the received transfer command. The transfer command may be a read or write command. | 09-05-2013 |
20130232292 | IMPLEMENTING LARGE BLOCK RANDOM WRITE HOT SPARE SSD FOR SMR RAID - A method and a storage system are provided for implementing a sustained large block random write performance mechanism for shingled magnetic recording (SMR) drives in a redundant array of inexpensive disks (RAID). A Solid State Drive (SSD) is provided with the SMR drives in the RAID. The SSD is used in a hot spare mode, which is activated when a large block random-write event is identified for a SMR drive in the RAID. In the hot spare mode, the SSD temporarily receives new incoming writes for the identified SMR drive. Then the identified SMR drive is updated from the SSD to restore the state of the identified SMR drive, and operations continue with normal writing only using the SMR drives in the RAID. | 09-05-2013 |
20130232293 | HIGH PERFORMANCE STORAGE TECHNOLOGY WITH OFF THE SHELF STORAGE COMPONENTS - Using integrated circuits, such as field programmable gate arrays, it is possible to transfer data to common off the shelf storage devices at high speeds which would normally be associated with special purpose hardware created for a particular application. Such high speed storage can include prefetching data to be stored from a memory element into a cache, and translating the commands which will be used in accomplishing the transfer into a standard format, such as peripheral component interconnect express. | 09-05-2013 |
20130232294 | ADAPTIVE CACHE PROMOTIONS IN A TWO LEVEL CACHING SYSTEM - Provided are a computer program product, system, and method for managing data in a first cache and a second cache. A reference count is maintained in the second cache for the page when the page is stored in the second cache. It is determined that the page is to be promoted from the second cache to the first cache. In response to determining that the reference count is greater than zero, the page is added to a Least Recently Used (LRU) end of an LRU list in the first cache. In response to determining that the reference count is less than or equal to zero, the page is added to a Most Recently Used (LRU) end of the LRU list in the first cache. | 09-05-2013 |
20130232295 | ADAPTIVE CACHE PROMOTIONS IN A TWO LEVEL CACHING SYSTEM - Provided are a computer program product, system, and method for managing data in a first cache and a second cache. A reference count is maintained in the second cache for the page when the page is stored in the second cache. It is determined that the page is to be promoted from the second cache to the first cache. In response to determining that the reference count is greater than zero, the page is added to a Least Recently Used (LRU) end of an LRU list in the first cache. In response to determining that the reference count is less than or equal to zero, the page is added to a Most Recently Used (LRU) end of the LRU list in the first cache. | 09-05-2013 |
20130232296 | MEMORY SYSTEM AND CONTROL METHOD OF MEMORY SYSTEM - A memory system in embodiments includes a nonvolatile semiconductor memory that stores user data, a forward lookup address translation table and a reverse lookup address translation table, and a controller. The controller is configured to determine that the user data stored in the nonvolatile semiconductor memory is valid or invalid based on these two tables. The controller may perform data organizing of selecting data determined valid and rewriting the data in a new block. The controller may perform write processing and rewriting processing to the new block alternately at a predetermined ratio. The controller may determine whether a predetermined condition is satisfied on a basis of addresses included in write requests and write data in the MLC mode when the condition is satisfied and write data in the SLC mode when the condition is not satisfied. | 09-05-2013 |
20130232297 | Storage System Comprising Flash Memory Modules Subject to Two Wear - Leveling Process - A storage system using flash memories includes a storage controller and plural flash memory modules as storage media. Each flash memory module includes at least one flash memory chip and a memory controller for leveling erase counts of blocks belonging to the flash memory chip. The storage controller combines the plural flash memory modules into a first logical group, translates a first address used for accessing the flash memory modules belonging to the first logical group to a second address used for handling the first address in the storage controller, and combines the plural first logical groups into a second logical group. | 09-05-2013 |
20130232298 | MODULAR MASS STORAGE SYSTEM AND METHOD THEREFOR - A modular mass storage system and method that enables cableless mounting of ATA and/or similar high speed interface-based mass storage devices in a computer system. The system includes a printed circuit board, a system expansion slot interface on the printed circuit board and comprising power and data pins, a host bus controller on the printed circuit board and electrically connected to the system expansion slot interface, docking connectors connected with the host bus controller to receive power and exchange data therewith and adapted to electrically couple with industry-standard non-volatile memory devices without cabling therebetween, and features on the printed circuit board for securing the memory devices thereto once coupled to the docking connectors. | 09-05-2013 |
20130238831 | METHOD FOR IMPLEMENTING SECURITY OF NON-VOLATILE MEMORY - An integrated circuit includes a non-volatile memory module that can censor access to various memory regions based upon a censorship criteria. Information used to implement the censorship criteria is stored at a non-volatile memory location. A one-time programmable non-volatile memory location stores a value representing permanent censorship key. If the permanent censorship key is in an erased state, one or more resources are allowed to modify the non-volatile memory location and disable censorship. If the permanent censorship key has one or more programmed bits, no resource is allowed to modify the non-volatile memory location and disable censorship. | 09-12-2013 |
20130238832 | DEDUPLICATING HYBRID STORAGE AGGREGATE - Methods and apparatuses for performing deduplication in a hybrid storage aggregate are provided. In one example, a method includes operating a hybrid storage aggregate that includes a plurality of tiers of different types of physical storage media. The method includes identifying a first storage block and a second storage block of the hybrid storage aggregate that contain identical data and identifying caching statuses of the first storage block and the second storage block. The method also includes deduplicating the first storage block and the second storage block based on the caching statuses of the first storage block and the second storage block. | 09-12-2013 |
20130238833 | HEURISTICS FOR PROGRAMMING DATA IN A NON-VOLATILE MEMORY - Systems and methods are disclosed for heuristics associated with programming data in a non-volatile memory (“NVM”). One or more applications can generate information that notifies a system of the amounts of recoverable and unrecoverable new data that will be programmed to an NVM. Based on this information, the system can calculate the amount of new data that needs to be placed in a bulk mode instead of a SLC mode. By utilizing multi-modal modes of an NVM effectively, the system can improve overall performance and reduce the probability of unnecessary garbage collection. | 09-12-2013 |
20130238834 | DYNAMIC STORAGE PARAMETER TRACKING - A method or system comprising iteratively updating a value of an operating parameter of a storage region of a storage device based on dynamic characterization of the storage region during operation of the storage device and using the updated value of the operating parameter during access to the storage region. | 09-12-2013 |
20130238835 | BURNING SYSTEM AND METHOD - A burning system includes an indentifying module, a dividing module, a calculating module, an index module, and a burning module. The identifying module identifies bad blocks of the flash memory. The dividing module reads all blocks of the flash memory in sequence, and when one or more continuous blocks being read are bad blocks, groups the bad blocks and the previously read good block as a storage sector. The calculating module calculates a bad block ratio of each storage sector. The index module assigns a priority level to each storage sector according to the bad block ratio of the storage sector, and associates each priority level of the storage sectors with a start address. The burning module accesses the storage sectors in an order of the priority levels of the storage sectors, and begins writing programs into the storage sectors from the associated start addresses. | 09-12-2013 |
20130238836 | SEMICONDUCTOR STORAGE DEVICE HAVING NONVOLATILE SEMICONDUCTOR MEMORY - A semiconductor storage device has a nonvolatile semiconductor memory comprised from multiple storage areas, and a controller, which is coupled to the nonvolatile semiconductor memory. The controller (A) identifies a storage area state, which is the state of a storage area, (B) decides, based on the storage area state identified in the (A), a read parameter, which is a parameter for use when reading data from a storage area with respect to a storage area of this storage area state, and (C) uses the read parameter decided in the (B) with respect to a read-target storage area and reads data from this read-target storage area. | 09-12-2013 |
20130238837 | STORAGE DEVICE WHICH CAN PERFORM STABLE COMMUNICATION BETWEEN HOST AND STORAGE DEVICE, AND METHOD OF CONTROLLING THE SAME - According to one embodiment, a storage device includes a nonvolatile memory, an interface, a register, and a controller. The nonvolatile memory stores communication speed information. The interface communicates with a host. The register is included in the interface. The controller controls the nonvolatile memory and the interface. The controller reads the speed information from the nonvolatile memory and sets the speed information in the register when the device is started, and the interface communicates with the host based on the speed information set in the register. | 09-12-2013 |
20130238838 | CONTROLLER, STORAGE DEVICE, AND COMPUTER PROGRAM PRODUCT - According to an embodiment, a controller is connected to an external storage device and controls access to a semiconductor storage device including blocks each including memory cell groups each having memory cells. The block includes pages associated with each memory cell group. A writing process for each memory cell group includes writing stages. The controller includes a determining unit configured to determine data to be transferred to the page required in the writing process for a first memory cell group before the writing stage first starts when the writing stage is performed; a reading unit configured to read the determined data from the semiconductor storage device and to store the read data in the external storage device before the writing stage starts; and a writing unit configured to perform the writing process using the data stored in the external storage device when the writing stage is performed. | 09-12-2013 |
20130238839 | Systems and Methods for Temporarily Retiring Memory Portions - A flash memory apparatus that may include a plurality of memory portions, and a controller operative to reserve for data retention purposes, for at least a first duration of time, only certain memory portions; allocate data, during said first duration of time, only to said certain memory portions, thereby to define a retired memory portion for said first duration of time; determine to copy data from a certain memory portion to a retired memory portion based upon a relationship between effective cycle counts of the certain memory portion and the retired memory portion, an effective cycle count of any memory portion is responsive to a number of erase-write cycles and to an effective duration of time the memory portion had available to recover from erase-write cycles; and copy the data from the certain memory portion to the retired memory portion. | 09-12-2013 |
20130238840 | MEMORY ARRAY WITH FLASH AND RANDOM ACCESS MEMORY AND METHOD THEREFOR - Memory array, system and method for storing data. The memory array has a flash memory array, a random access memory array coupled to the flash memory and configured to receive the data, a memory management module and a data bus. The memory management module is coupled to the random access memory array and to the flash memory array, the memory management module being configured to transfer at least a portion of the data stored in the random access memory array to the flash memory array. The data bus is coupled to the flash memory array and configured to output at least a portion of the data originally stored in the random access memory array from the flash memory array. | 09-12-2013 |
20130238841 | DATA PROCESSING DEVICE AND METHOD FOR PREVENTING DATA LOSS THEREOF - A data access memory includes a nonvolatile memory module configured to store meta data and a volatile memory module configured to store normal data. The volatile memory module includes a latency controller delaying input of an address signal and the normal data for a constant delay time to share with the nonvolatile memory module a first transmission line for communicating with a processor. | 09-12-2013 |
20130238842 | FLASH STORAGE DEVICE WITH ENHANCED DATA CORRECTION - Provided herein is a flash storage device with enhanced data correction, comprising a controller and at least one flash memory comprising a main area and a spare area. The main area comprises a plurality of sectors. The controller selects from the plurality of sectors at least one sector as an auxiliary sector and leaves the other sectors as data sectors for storing data. The spare area is capable of extending the storage capacity with the assistance from the auxiliary sector. The extended spare area is divided into a plurality of spare spaces according to the number of the data sectors, each of the spare spaces corresponding to one of the data sectors to store error correction codes (ECCs) for data verification. Thereby, the spare area is extended by sacrificing parts of the space of the main area so as to store lengthened error correction codes and enhance data correction. | 09-12-2013 |
20130238843 | METHOD AND APPARATUS FOR PERFORMING MULTI-BLOCK ACCESS OPERATION IN NONVOLATILE MEMORY DEVICE - A nonvolatile memory device comprises a first mat, a second mat, a third mat, a first address decoder, a second address decoder, and a third address decoder. The first mat comprises first memory blocks, the second mat comprises second memory blocks, and the third mat comprises third memory blocks. The first address decoder selects one of the first memory blocks according to a first even address, the second address decoder selects one of the second memory blocks according to a second even address or a first odd address, and the third address decoder selects one of the third memory blocks according to a second odd address. | 09-12-2013 |
20130238844 | METHOD AND SYSTEM FOR ACCESSING A STORAGE SYSTEM WITH MULTIPLE FILE SYSTEMS - In order to write data to a storage system accessible with a first and second file system, a manager receives a data write request associated with a file. The manager determines if a function supported by the second file system is needed to complete the write request. If so, the file is opened and extended with the first file system. The file is then opened and written to by the second file system. The file is truncated by the first file system, and closed by both file systems. If the second file system function is not needed, the file is opened, written, and closed by the first file system. In order to read data from a storage system using a function supported by the second file system, the second file system's cached storage system index is updated, then the file is opened, read, and closed by the second file system. | 09-12-2013 |
20130238845 | SYSTEM AND METHOD FOR ALLOCATING CAPACITY - For a storage apparatus where flash memory disks and hard disks coexist, high-density mounting of flash memory modules is achieved. The storage apparatus includes flash memories and a storage controller. A second storage apparatus including magnetic disks is connected to the storage apparatus. The storage controller can form a storage area using a flash memory or a magnetic disk to create a logical volume. When an input/output request is issued from a host computer, if a storage area is formed with a flash memory, the storage controller directly accesses the flash memory to handle the request. When the storage apparatus defines a storage area formed with a flash memory, the storage apparatus defines the storage area by adding up the capacity of a storage area to be provided for the host computer and a substitute area capacity determined in consideration of restrictions on the number deletions of the flash memory. | 09-12-2013 |
20130238846 | SERIAL INTERFACE NAND - Embodiments are provided for operating a memory device by issuing certain instructions to the memory device that specify a cache and/or memory array address where an operation is to occur. One such method may include loading data into a specified address of a cache of the memory device, in which the specified address of the cache of the memory device may be specified by a first program sequence received at an interface of the memory device from a host external to the memory device. The method may also include writing the data from the specified address of the cache of the memory device to a specified address of a memory array of the memory device, in which the specified address of the memory array of the memory device may be specified by a second program sequence received at the interface from the host. | 09-12-2013 |
20130246687 | DATA WRITING METHOD, MEMORY CONTROLLER AND MEMORY STORAGE APPARATUS - A data writing method for writing data into a physical block of a rewritable non-volatile memory module is provided. The method includes setting danger distance respectively corresponding to each of the physical pages of the physical block, and setting a secure writing flag in an enable state in response to a secure write command. The method also includes determining whether the secure writing flag is set in the enable state when receiving a write command and updated data thereof; if no, writing the updated data into a predetermined physical page of the physical block; if yes, writing the updated data into a secure physical page of the physical block and re-setting the secure writing flag in a disable state, and the distance between the secure physical page and the predetermined physical page is equal to the danger distance corresponding to the predetermined physical page. | 09-19-2013 |
20130246688 | SEMICONDUCTOR MEMORY DEVICE AND COMPUTER PROGRAM PRODUCT - According an embodiment, a semiconductor memory device includes a semiconductor memory chip to store plural pieces of data that are written and read in units of a page and are erased in units of a block including plural pages; a discarding unit to discard, after the data is written in the semiconductor memory chip with a logic address being designated, at least a portion of valid data among the plural pieces of data; a compaction unit to write the valid data excluding the discarded data in a second block among the valid data stored in a first block and erase the first block; and a controller to output, in response to a request for reading the discarded data, a response indicating that the data is unable to be read. When all the valid data included in a block are discarded, the discarding unit erases the block. | 09-19-2013 |
20130246689 | MEMORY SYSTEM, DATA MANAGEMENT METHOD, AND COMPUTER - According to one embodiment, a memory system includes a non-volatile memory, a volatile memory, a controller, and a compression/decompression processor. When data transmission is performed through the volatile memory between a host apparatus and the non-volatile memory, the controller updates management information stored in the volatile memory. In addition, the compression/decompression processor compresses the management information in the case where a first condition is satisfied, and decompresses the compressed management information in the case where a second condition is satisfied. The controller stores the compressed management information in the non-volatile memory. | 09-19-2013 |
20130246690 | INFORMATION PROCESSING SYSTEM AND DATA-STORAGE CONTROL METHOD - In an information processing system, a processor requests a first transfer control circuit to transfer data to a first memory. In response to the request from the processor, the first transfer control circuit sends the data to a second transfer control circuit. The second transfer control circuit stores in a second memory the data received from the first transfer control circuit, and also stores the data in the first memory through the first transfer control circuit. | 09-19-2013 |
20130246691 | ADAPTIVE PRESTAGING IN A STORAGE CONTROLLER - In one aspect of the present description, at least one of the value of a prestage trigger and the value of the prestage amount, may be modified as a function of the drive speed of the storage drive from which the units of read data are prestaged into a cache memory. Thus, cache prestaging operations in accordance with another aspect of the present description may take into account storage devices of varying speeds and bandwidths for purposes of modifying a prestage trigger and the prestage amount. Other features and aspects may be realized, depending upon the particular application. | 09-19-2013 |
20130246692 | COLLECTABLE DISPLAY DEVICE - Provided is a collectable display device, including at least one display panel having at least one user accessible opening for housing and displaying at least one collectable object. The display panel is configured to be connected or connectable to at least one auxiliary panel having visual markings relating to at least one collectable. The collectable display device also includes an electronic solid-state flash memory data storage device that is non-detachably secured to the auxiliary panel, and the solid-state flash memory device is having sufficient storage capacity to record and store at least one digital picture image associated with at least one appearance characteristic of at least one collectable object. In operation, the solid-state flash memory device is readable by an electronic device physically and electronically connected to the solid-state flash memory device. In some embodiments, the collectable object is a coin, a stamp, or a sports card, or the like. | 09-19-2013 |
20130246693 | FLASH-AWARE STORAGE OPTIMIZED FOR MOBILE AND EMBEDDED DBMS ON NAND FLASH MEMORY - Reliable storage for database management systems (DBMS) running on memory devices such as NAND type flash memory utilizes minimum I/O overhead and provides maximum data durability. A virtual page map is utilized between the flash memory and a page access component to record changes to the DBMS pages and prevent overwriting or data loss. There is no need for journaling and logging, and performance is increased by reducing the write and erase counts on the flash memory. The logical page numbers of the DBMS are mapped to physical page numbers in the page map, such that the virtual page map allocates an available page from the physical pages when changes to a page occur, and the updated information is stored in the allocated page. The allocated page number is mapped to the logical page number of the original page, thus maintaining a modified page representation while preventing physical in-place updates. | 09-19-2013 |
20130246694 | Multilevel Memory Bus System For Solid-State Mass Storage - The present invention relates to a multilevel memory bus system for transferring information between at least one DMA controller and at least one solid-state semiconductor memory device, such as NAND flash memory devices or the like. This multilevel memory bus system includes at least one DMA controller coupled to an intermediate bus; a flash memory bus; and a flash buffer circuit between the intermediate bus and the flash memory bus. This multilevel memory bus system may be disposed to support: an n-bit wide bus width, such as nibble-wide or byte-wide bus widths; a selectable data sampling rate, such as a single or double sampling rate, on the intermediate bus; a configurable bus data rate, such as a single, double, quad, or octal data sampling rate; CRC protection; an exclusive busy mechanism; dedicated busy lines; or any combination of these. | 09-19-2013 |
20130246695 | INTEGRATED CIRCUIT DEVICE, SIGNAL PROCESSING SYSTEM AND METHOD FOR PREFETCHING LINES OF DATA THEREFOR - An integrated circuit device comprising at least one prefetching module for prefetching lines of data from at least one memory element. The prefetching module is configured to determine a position of a requested block of data within a respective line of data of the at least one memory element, determine a number of subsequent lines of data to prefetch, based at least partly on the determined position of the requested block of data within the respective line of data of the at least one memory element, and cause the prefetching of n successive lines of data from the at least one memory element. | 09-19-2013 |
20130254457 | METHODS AND STRUCTURE FOR RAPID OFFLOADING OF CACHED DATA IN A VOLATILE CACHE MEMORY OF A STORAGE CONTROLLER TO A NONVOLATILE MEMORY - Methods and structure for rapid offloading of cached data in a volatile cache memory of a storage controller to a nonvolatile memory. Features and aspects hereof provide an enhanced storage controller having a volatile cache memory and multiple communication channels each coupled with a corresponding nonvolatile memory device. Responsive to detecting an impending loss of power, control logic of the controller copies data from the volatile cache memory to the multiple nonvolatile memories using the multiple communication channels operating substantially in parallel. Using multiple parallel channels and nonvolatile memory substantially temporally overlapping their operations assures that the cached data can be saved to nonvolatile memory before the controller is inoperable due to power loss. A simple “file system” and error detection and correction codes on the nonvolatile memory help assure that the saved data is valid for return to the volatile memory when power is restored to the controller. | 09-26-2013 |
20130254458 | SINGLE-LEVEL CELL AND MULTI-LEVEL CELL HYBRID SOLID STATE DRIVE - A solid state drive (SSD) having a first memory portion comprising SLC flash memory and a second memory portion comprising MLC flash memory. The first memory portion may store read/write data, and the second memory portion may store read-only or read-mostly data. In some instances, the second memory portion may store historical data. The present disclosure also relates to a method of data progression in a hybrid solid state drive having both single-level cell (SLC) flash memory and multi-level cell (MLC) flash memory. The method may include monitoring write operations to the SLC memory, determining whether the frequency of write operations to a particular portion of the SLC memory is below a determined threshold, and moving the data stored in the particular portion of the SLC memory to the MLC memory. | 09-26-2013 |
20130254459 | BLOCK STORAGE VIRTUALIZATION ON COMMODITY SECURE DIGITAL CARDS - One embodiment of the present invention provides a system that facilitates storing an image file of a virtual machine on a potentially unprotected flash storage exhibiting sub-optimal non-sequential write performance on a mobile phone. During operation, the system stores in the flash storage data in a log-structured format and in a protected storage meta-data associated with the data stored in the flash storage. The system also checks integrity of the data stored in the flash storage using the meta-data in the protected storage. | 09-26-2013 |
20130254460 | USING DIFFERENT SECURE ERASE ALGORITHMS TO ERASE CHUNKS FROM A FILE ASSOCIATED WITH DIFFERENT SECURITY LEVELS - Provided are a computer program product, system, and method for using different secure erase algorithms to erase chunks from a file associated with different security levels. A request is received to secure erase a file having a plurality of chunks stored in at least one storage device. A determination is made of a first secure erase algorithm to apply to a first chunk in the file in response to the request and of a second secure erase algorithm to apply to a second chunk in the file in response to the request. The first secure erase algorithm is applied to erase the first chunk and the second secure erase algorithm is applied to erase the second chunk. The first and second secure erase algorithms use different processes to erase the chunks to which they are applied. | 09-26-2013 |
20130254461 | MEMORY CONTROLLER AND MEMORY STORAGE DEVICE AND DATA WRITING METHOD - A data writing method for a memory storage device having physical unit unions is provided, wherein each of the physical unit unions includes upper physical units and lower physical units. The method includes partitioning the physical unit unions into a storage area including a data area and a spare area; configuring logical units for mapping to the physical unit unions of the data area; and receiving update data from a host system. The method also includes: selecting several physical unit unions from the spare area as buffer physical unit unions; writing the update data only to a part of each of the buffer physical unit unions; and moving the update data from buffer physical unit unions to the storage area by using a copy procedure. Therefore, the time of performing a write command can be shorten and the lifespan of the memory storage device can be prolonged effectively. | 09-26-2013 |
20130254462 | METHOD AND APPARATUS TO REDUCE FLASH MEMORY DEVICE PROGRAMMING TIME OVER A C.A.N. BUS - Data frames, such as Controller Access Network frames, that are to be programmed into a FLASH memory device, are sent from a programming station to a target device via a relatively high-speed bus and stored temporarily at the target device in numbered frame buffers. Each frame carries a payload. Before a frame is sent, an identifier is assigned to it, or an identifier is appended to the frame. The identifier identifies a particular buffer in the target device where the frame is to be stored in the target device until the target device is able to process the frame and write its payload into a FLASH memory device. | 09-26-2013 |
20130254463 | MEMORY SYSTEM - According to an embodiment, a memory system includes a nonvolatile memory that stores system data into a first address, a first data verifying unit, an address selecting unit, a first data operating unit, a second data verifying unit and a second data operating unit. | 09-26-2013 |
20130254464 | MEMORY SYSTEM - According to one embodiment, the memory system includes a nonvolatile semiconductor memory, a data buffer, a volatile memory for storing a management table uniquely associates the user data with an address of the physical storage region of nonvolatile semiconductor memory, a controller that carries out a force quit process for writing the user data stored in a data buffer, the management table stored in volatile memory into the nonvolatile semiconductor memory, and a storage battery. The controller starts the force quit process prior to the power supply of the internal power supply regulator is switched from an external power supply to the storage battery. | 09-26-2013 |
20130254465 | SOLID STATE MEMORY FORMATTING - The present disclosure includes methods and devices for solid state drive formatting. One device embodiment includes control circuitry coupled to a number of memory arrays, wherein each memory array has multiple physical blocks of memory cells. The memory arrays are formatted by the control circuitry that is configured to write system data to the number of memory arrays, where the system data ends at a physical block boundary; and write user data to the number of memory arrays, where the user data starts at a physical block boundary. | 09-26-2013 |
20130254466 | RANK-MODULATION REWRITING CODES FOR FLASH MEMORIES - Rank modulation has been recently proposed as a scheme for storing information in flash memories. Three improved aspects are disclosed. In one aspect the minimum push-up scheme, for storing data in flash memories is provided. It aims at minimizing the cost of changing the state of the memory. In another aspect, multi-cells, used for storing data in flash memories is provided. Each transistor is replaced with a multi-cell of mm transistors connected in parallel. In yet another aspect, multi-permutations, are provided. The paradigm of representing information with permutations is generalized to the case where the number of cells in each level is a constant greater than one. In yet another aspect, rank-modulation rewriting schemes which take advantage of polar codes, are provided for use with flash memory. | 09-26-2013 |
20130254467 | SYSTEM AND METHOD FOR SCANNING FLASH MEMORIES - A system and method for providing memory device readiness to a memory controller is disclosed. One example system includes a channel controller operably connected to a memory controller and a group of flash memory devices. The channel controller may receive, from the memory controller a request for a status of one or more memory devices in the group of flash memory devices. The channel controller may determine the status of the one or more memory devices, the status being determined while the memory controller is permitted to execute one or more other commands related to one or more other memory devices in a different group of memory devices. On determining that the one or more memory devices are in a ready status, the channel controller may provide the ready status to the memory controller. | 09-26-2013 |
20130254468 | STORAGE CONTROL DEVICE, STORAGE CONTROL METHOD AND PROGRAM - A storage control device of an outboard motor writing operation history information of the outboard motor to a nonvolatile memory by using an electric power generated by driving of an internal combustion engine, the storage control device includes a stop instruction detecting unit detecting a stop instruction of the driving of the internal combustion engine by a boat operator, a writing unit writing the operation history information to the nonvolatile memory in accordance with the stop instruction detected by the stop instruction detecting unit, a write judgment unit judging whether or not the operation history information is written to the nonvolatile memory by the writing unit, and a stop processing unit stopping the driving of the internal combustion engine after it is judged that the operation history information is written to the nonvolatile memory by the write judgment unit. | 09-26-2013 |
20130254469 | AUTOMOTIVE ELECTRONIC CONTROL UNIT AND DATA REWRITING METHOD FOR AUTOMOTIVE ELECTRONIC CONTROL UNIT - An automotive electronic control unit receives rewrite data wirelessly transmitted in units of a predetermined size from an external device and rewrites data stored in a nonvolatile memory based on the rewrite data. At this time, the rewrite data is communicated by switching between broadcast communication and unicast communication, or between multicast communication and unicast communication. | 09-26-2013 |
20130254470 | EFFICIENT DATA STORAGE IN MULTI-PLANE MEMORY DEVICES - A method for data storage includes initially storing a sequence of data pages in a memory that includes multiple memory arrays, such that successive data pages in the sequence are stored in alternation in a first number of the memory arrays. The initially-stored data pages are rearranged in the memory so as to store the successive data pages in the sequence in a second number of the memory arrays, which is less than the first number. The rearranged data pages are read from the second number of the memory arrays. | 09-26-2013 |
20130254471 | DEVICE AND MEMORY SYSTEM FOR MEMORY MANAGEMENT USING ACCESS FREQUENCY INFORMATION - An integrated memory management device according to an example of the invention comprises an acquiring unit acquiring a read destination logical address from a processor, an address conversion unit converting the read destination logical address into a read destination physical address of a non-volatile main memory, an access unit reading, from the non-volatile main memory, data that corresponds to the read destination physical address and has a size that is equal to a block size or an integer multiple of the page size of the non-volatile main memory, and transmission unit transferring the read data to a cache memory of the processor having a cache size that depends on the block size or the integer multiple of the page size of the non-volatile main memory. | 09-26-2013 |
20130262741 | SYSTEM AND METHOD FOR SUPPORTING MULTIPLE AUTHENTICATION SYSTEMS - A system for supporting multiple authentication systems. The system includes a computing device, a host memory for storing a plurality of software stacks, a flash memory configured to be programmed with one of the plurality of software stacks, and at least one processor. The at least one processor is programmed to identify a model of the device, select a software stack from the plurality of software stacks based on a device model of the computing device, and program the selected software stack into the flash memory. The device may be an electrical appliance. | 10-03-2013 |
20130262742 | METHOD AND APPARATUS FOR MANAGING BUFFER CACHE TO PERFORM PAGE REPLACEMENT BY USING REFERENCE TIME INFORMATION REGARDING TIME AT WHICH PAGE IS REFERRED TO - A method and apparatus manages a buffer cache. An extended buffer is used to perform a page replacement algorithm using reference time information regarding a time at which a page is referred. Pages replaced through the page replacement algorithm, when re-referred to, may be retrieved from the extended buffer, instead of a hard disk. As a result, write/read operations with respect to the disk are made efficient and the page input/output speed is increased. | 10-03-2013 |
20130262743 | ENCODING PROGRAM BITS TO DECOUPLE ADJACENT WORDLINES IN A MEMORY DEVICE - Subject matter disclosed herein relates to memory operations regarding encoding program bits to be programmed into a memory array. | 10-03-2013 |
20130262744 | NAND Flash Memory Interface - A NAND flash memory chip has a configurable interface that can communicate with a NAND flash memory controller using either parallel communication or serial communication. Serial communication requires fewer channels. Control information from the NAND flash memory controller uses a small number of channels. Double Data Rate (DDR) communication provides serial communication with adequate data transfer speed. | 10-03-2013 |
20130262745 | Memory System with Command Queue Reordering - A non-volatile memory system includes a memory controller that receives commands from a host and identifies commands that can be executed in parallel. The order in which commands are received is recorded so that responses may be provided to the host in the same order in which the commands were received. | 10-03-2013 |
20130262746 | ENHANCING THE LIFETIME AND PERFORMANCE OF FLASH-BASED STORAGE - A storage management system decouples application write requests from write requests to a flash-based storage device. By placing a layer of software intelligence between application requests to write data and the storage device, the system can make more effective decisions about when and where to write data that reduce wear and increase performance of the storage device. An application has a set of performance characteristics and writes data with a frequency that is appropriate for the application, but not necessarily efficient for the hardware. By analyzing how data is being used by an application, the system can strategically place data in the storage device or even avoid using the storage device altogether for some operations to minimize wear. One technique for doing this is to create an in-memory cache that acts as a buffer between the application requests and the storage hardware. | 10-03-2013 |
20130262747 | DATA WRITING METHOD, AND MEMORY CONTROLLER AND MEMORY STORAGE DEVICE USING THE SAME - A data writing method for a rewritable non-volatile memory module containing physical blocks is provided. The method includes: configuring virtual block address to map to at least a part of the logical blocks; receiving a write command which instructs to write file data to the first virtual block addresses, and the first virtual block addresses are mapped to first logical blocks of the at least the part of the logical blocks. The method further includes: writing the file data into the physical blocks mapped to a plurality of second logical blocks; determining whether a program failure is occurred during the writing period; and if the program failure is not occurred, the first virtual block addresses are remapped to the second logical block. Accordingly, the method can ensure the update completeness of the file data. | 10-03-2013 |
20130262748 | DATA PROTECTING METHOD, MEMORY CONTROLLER AND MEMORY STORAGE DEVICE USING THE SAME - A data protecting method for a rewritable non-volatile memory module having physical blocks is provided, a plurality of logical block addresses is mapped to a part of the physical blocks. The method includes, configuring a plurality of virtual block addresses to map to the logical block addresses, grouping at least one virtual block address into a virtual block address area, and allocating the virtual block address area to an application. The method also includes, receiving an access command which is configured to instruct accessing a first virtual block address from the application. The method also includes: determining whether the first virtual block address belongs to the virtual block address area, if not, sending an error message to the application. Accordingly, the method can effectively prevent an application from accessing the data which can not be accessed by the application program. | 10-03-2013 |
20130262749 | STORAGE SYSTEM WITH FLASH MEMORY, AND STORAGE CONTROL METHOD - A storage system has: one or more flash memory chips, each of which has a storage region configured by a plurality of blocks; and a device controller that controls access to data corresponding to the storage regions of the flash memory chips. The device controller manages for each of the blocks the number of determination readings for determining read disturb on the basis of a read request with respect to data of each block from a higher-level device, and, when there is a block for which the number of determination readings becomes equal to or larger than a threshold represented as a standard indicating a predetermined state related to read disturb, transmits, to the higher-level device, notification information that includes information indicating that read disturb of the block enters the predetermined state. | 10-03-2013 |
20130262750 | STORAGE SYSTEM AND STORAGE SYSTEM CONTROL METHOD - The device controller (a) executes a data I/O process with respect to a physical storage area in accordance with an I/O command, and (b) sends to the storage controller an I/O command-related response comprising status information subsequent to being changed in accordance with the I/O process. The storage controller (A) receives the response from the target physical storage device, and (B) based on the status information included in the response received in (A), makes a determination as to whether or not to execute internal processing, and in a case where the result of the determination is to execute internal processing, sends to the target physical storage device an internal processing execution command instructing the execution of internal processing. The device controller in the target physical storage device (c), upon receiving the internal processing execution command, executes internal processing in accordance with the internal processing execution command. | 10-03-2013 |
20130262751 | NONVOLATILE MEMORY DEVICE, MEMORY SYSTEM, AND PROGRAM METHOD THREOF - Disclosed is a method for programming a nonvolatile memory device, the nonvolatile memory device including cell strings formed in a direction perpendicular to a substrate, and which selects memory cells by a string selection line unit. The programming method includes detecting wear leveling information of a selected memory block, determining a selection sequence of string selection lines of the selected memory block according to the wear leveling information, and writing data at the selected memory block according to the determined selection sequence. | 10-03-2013 |
20130262752 | EFFICIENT USE OF HYBRID MEDIA IN CACHE ARCHITECTURES - A multi-tiered cache manager and methods for managing multi-tiered cache are described. Multi-tiered cache manager causes cached data to be initially stored in the RAM elements and selects portions of the cached data stored in the RAM elements to be moved to the flash elements. Each flash element is organized as a plurality of write blocks having a block size and wherein a predefined maximum number of writes is permitted to each write block. The portions of the cached data may be selected based on a maximum write rate calculated from the maximum number of writes allowed for the flash device and a specified lifetime of the cache system. | 10-03-2013 |
20130262753 | Multiprocessor Storage Controller - A storage controller has multiple processors, divided into groups, each of which handles a different stage of a pipelined process of performing host reads and writes. In some embodiments, the storage controller operates with a flash memory module, and includes a first processor group, a second processor group and a third processor group, each having one or more processors for handling a different stage of a pipelined execution of host storage commands. With respect to a first host command, a first processor of the first processor group, a first processor of the second processor group, and a first processor of the third processor group comprise a first pipeline, and with respect to a second host command, a second processor of the first processor group, a second processor of the second processor group, and a second processor of the third processor group comprise a second pipeline. | 10-03-2013 |
20130262754 | SEMICONDUCTOR INTEGRATED CIRCUIT ADAPTED TO OUTPUT PASS/FAIL RESULTS OF INTERNAL OPERATIONS - In a semiconductor integrated circuit, an internal circuit is capable of executing a first operation and a second operation concurrently, and an output circuit outputs to the outside of the semiconductor integrated circuit information indicating whether or not the first operation is being executed and information indicating whether or not the second operation is executable. | 10-03-2013 |
20130262755 | DATA ACCESSING METHOD FOR FLASH MEMORY STORAGE DEVICE HAVING DATA PERTURBATION MODULE, AND STORAGE SYSTEM AND CONTROLLER USING THE SAME - A data accessing method, and a storage system and a controller using the same are provided. The data accessing method is suitable for a flash memory storage system having a data perturbation module. The data accessing method includes receiving a read command from a host and obtaining a logical block to be read and a page to be read from the read command. The data accessing method also includes determining whether a physical block in a data area corresponding to the logical block to be read is a new block and transmitting a predetermined data to the host when the physical block corresponding to the logical block to be read is a new block. Thereby, the host is prevented from reading garbled code from the flash memory storage system having the data perturbation module. | 10-03-2013 |
20130268717 | EMULATED ELECTRICALLY ERASABLE MEMORY HAVING SECTOR MANAGEMENT - A semiconductor memory device comprises a volatile memory and a non-volatile memory including a plurality of sectors. Each of the plurality of sectors configured to store a sector status indicator and a plurality of data records. A control module is coupled to the non-volatile memory and the volatile memory. The control module manages the sectors by scanning the sectors to identify the records with invalid data; changing the status indicator of a particular sector when all of the records in the particular sector are invalid, and discontinuing scanning the particular sector while all of the records in the particular sector are invalid. | 10-10-2013 |
20130268718 | IMPLEMENTING REMAPPING COMMAND WITH INDIRECTION UPDATE FOR INDIRECTED STORAGE - A method, apparatus, and a storage system are provided for implementing enhanced indirection update for indirected storage devices. A novel remapping command generated by a host is used to store indirection data. The remapping command enables remapping of a set of Logical Block Addresses (LBAs) to a different set of LBAs. The remapping command includes a source LBA, length and a destination LBA. | 10-10-2013 |
20130268719 | REMAPPING AND COMPACTING IN A MEMORY DEVICE - Methods for remapping and/or compacting data in memory devices, memory devices, and systems are disclosed. One such method of remapping and/or compacting data includes reducing a first quantity of write operations that are received from a host to a second quantity of write operations for programming to a page of a memory device that are within the specifications of partial page write operations for the memory device. The second quantity of write operations can also remap data that were originally intended to be programmed to memory address ranges that conflict with a memory map of the memory device. | 10-10-2013 |
20130268720 | MEMORY SYSTEM AND WIRELESS COMMUNICATION METHOD BY MEMORY SYSTEM - A memory system includes a nonvolatile memory area including a first area in which write-in and read-out actions on data are performed and a second area in which such actions are prohibited, first and second interfaces, and a controller configured to connect to a second host using a first wireless communication configuration when the controller determines a second wireless communication configuration to connect to the second host device is not retained in the first area, the controller controlling the first interface in so that the first host device writes data into the memory area on a basis of a command provided from the second host device. When the controller changes the first wireless communication configuration, the controller connects to the second host device using the second wireless communication configuration, and the first interface notifies an error to the first host device not to write data into the memory area. | 10-10-2013 |
20130268721 | NON-VOLATILE MEMORY DEVICE HAVING PARALLEL QUEUES WITH RESPECT TO CONCURRENTLY ADDRESSABLE UNITS, SYSTEM INCLUDING THE SAME, AND METHOD OF OPERATING THE SAME - A non-volatile memory device having respective parallel queues is disclosed. The non-volatile memory device includes a plurality of concurrently addressable units. The non-volatile memory device has respective queues for the concurrently addressable units, and transfers a second command to respective queues for the remaining concurrently addressable units while a first command is executed in a part of the concurrently addressable units, and executes a second command in the remaining concurrently addressable units. Accordingly, non-volatile memory device may concurrently access the concurrently addressable units in parallel, and may have high speed. | 10-10-2013 |
20130268722 | NON-VOLATILE MEMORY DEVICE USING DIVISION ADDRESSING AND ELECTRONIC DEVICE INCLUDING SAME - A non-volatile memory device uses division addressing scheme and N address input terminals. A address decoder of the non-volatile memory device simultaneously activates a row select signal and a column select signal by synchronizing a first N-bit address signal and a second N-bit address signal sequentially input after the first N-bit address signal. | 10-10-2013 |
20130268723 | FLASH MEMORIES USING MINIMUM PUSH UP, MULTI-CELL AND MULTI-PERMUTATION SCHEMES FOR DATA STORAGE - Rank modulation has been recently proposed as a scheme for storing information in flash memories. Three improved aspects are disclosed. In one aspect the minimum push-up scheme, for storing data in flash memories is provided. It aims at minimizing the cost of changing the state of the memory. In another aspect, multi-cells, used for storing data in flash memories is provided. Each transistor is replaced with a multi-cell of mm transistors connected in parallel. In yet another aspect, multi-permutations, are provided. The paradigm of representing information with permutations is generalized to the case where the number of cells in each level is a constant greater than one. | 10-10-2013 |
20130268724 | SSD WITH RAID CONTROLLER AND PROGRAMMING METHOD - A solid state drive (SSD) includes non-volatile memory devices and a RAID controller. Each of the non-volatile memory devices includes a memory cell array having a plurality of physical pages. The RAID controller performs a parity operation on 1st through (N−1)th physical page data to generate Nth physical page data, determines a physical page group including 1st through Nth physical pages that are selected from the 1st through Nth non-volatile memory devices, respectively, such that at least two of the 1st through Nth physical pages have different bit error rates from each other, and stores the 1st through Nth physical page data in the 1st through Nth physical pages, respectively. | 10-10-2013 |
20130268725 | NONVOLATILE MEMORY WEAR MANAGEMENT - Embodiments of the present disclosure describe methods, apparatus, and system configurations for providing targeted wear management in nonvolatile memory. | 10-10-2013 |
20130268726 | Dual Mode Write Non-Volatile Memory System - Host writes may be handled differently from background writes to non-volatile memory systems. As a result of using different write algorithms for host writes and backgrounds writes, maximum system lifetime and the maximum system performance may be improved in some embodiments. | 10-10-2013 |
20130275651 | SYSTEM AND METHOD OF ADJUSTING A PROGRAMMING STEP SIZE FOR A BLOCK OF A MEMORY - A method includes decreasing a programming step size from a first value to a second value for a block of a memory device. The programming step size is decreased at least partially based on determining that an error count corresponding to the block satisfies a threshold. | 10-17-2013 |
20130275652 | METHODS AND STRUCTURE FOR TRANSFERRING ADDITIONAL PARAMETERS THROUGH A COMMUNICATION INTERFACE WITH LIMITED PARAMETER PASSING FEATURES - Methods and structure for transferring additional parameters through a communication interface with limited parameter passing features. Features and aspects hereof provide for generating and transmitting multiple related commands from an initiator device to a target device where one or more initial commands provide additional parameters. The additional parameters are utilized in processing the last of the multiple commands to actually perform a desired data transfer. The initial commands and the data transfer command may all be associated by encoding of a common tag or sub-tag value in each command. The initial commands may be read/write commands having a zero data transfer length. The associated data transfer command may be a read/write command having a non-zero data transfer length. The initial commands each provide one or more additional parameters for processing the data transfer command in addition to the standard parameters that may be encoded in the data transfer command. | 10-17-2013 |
20130275653 | MULTI-TIER STORAGE USING MULTIPLE FILE SETS - Storage locations in a first tier of a multi-tier storage system are allocated to a first set of data structures (e.g., inodes) in a first file set. A file that is stored in the first tier is associated with a first data structure of the first set. In response to determining that data in the file should be moved to a second tier of the multi-tier storage system, the file is associated with a second data structure in a second file set. The second data structure is allocated a storage location in the second tier. Consequently, two data structures are associated with the file. The data is copied from the first tier to the storage location in the second tier, and can be subsequently accessed using the second data structure. | 10-17-2013 |
20130275654 | MEMORY STORAGE APPARATUS, AND MEMORY CONTROLLER AND POWER CONTROL METHOD - A memory storage apparatus having a rewritable non-volatile memory module, a first circuit, a memory controller and a power management circuit is provided. The first circuit outputs a state signal and keeps the state signal in a first state when the first circuit is enabled, and then the first circuit keeps the state signal in a second state after a predetermined condition is satisfied. When the memory controller receives a first signal, the power management circuit stops supplying an output voltage to the rewritable non-volatile memory module and the memory controller. Additionally, when the memory controller is enabled, the memory controller determines whether the state signal is in the first state. If true, the memory controller performs a first procedure; and if not, the memory controller performs a second procedure. | 10-17-2013 |
20130275655 | MEMORY MANAGEMENT METHOD AND MEMORY CONTROLLER AND MEMORY STORAGE DEVICE USING THE SAME - A memory management method for a rewritable non-volatile memory module including physical unit unions is provided. The physical unit unions are at least partitioned into a data area and a second area. Logical unit union addresses are managed by a file system and would be allocated and mapped to the physical unit unions of the data area. The method includes executing a procedure if a programming error occurs when programming a third physical unit union of the second area. The procedure includes obtaining a second physical unit union mapped to a second logical unit union address from the data area and mapping the second logical unit union address to the third physical unit union. Accordingly, the lifespan of the rewritable non-volatile memory module would be prolonged by the method. | 10-17-2013 |
20130275656 | APPARATUS, SYSTEM, AND METHOD FOR KEY-VALUE POOL IDENTIFIER ENCODING - Apparatuses, systems, and methods are disclosed for a key-value store. A method includes encoding a key of a key-value pair into a logical address of a sparse logical address space for a non-volatile medium. A method includes mapping a logical address to a physical location in the non-volatile medium. A method includes storing a value of a key-value pair at a physical location. | 10-17-2013 |
20130275657 | DATA STORAGE DEVICE AND OPERATING METHOD THEREOF - An operating method of a data storage device including a plurality of nonvolatile memory devices includes the steps of: mapping physical addresses of the nonvolatile memory devices into logical addresses; reflecting environmental factors to remap a physical address into a logical address requested to be accessed; and performing an interleaving operation for the nonvolatile memory devices using the remapped physical address. | 10-17-2013 |
20130275658 | FLASH MEMORY DEVICE AND METHOD OF PROGRAMMING THE SAME - A method is provided for programming a flash memory device including memory cells formed in a direction perpendicular to a substrate, a first sub word line connected to first memory cells and selectable by a first selection line, and a second sub word line connected to second memory cells and selectable by a second selection line, the first and second memory cells being formed at the same level and being supplied with a program voltage at the same time. The method includes performing LSB program operations on the first and second sub word lines by enabling the first and second selection lines, respectively; performing CSB program operations on the first and second sub word lines by enabling the first and second selection lines, respectively; and performing MSB program operations on the first and second sub word lines by enabling the first and second selection lines, respectively. | 10-17-2013 |
20130275659 | ELECTRONIC DEVICES - A storage device ( | 10-17-2013 |
20130275660 | MANAGING TRIM OPERATIONS IN A FLASH MEMORY SYSTEM - A method and system for managing a flash memory system facilitates the use of TRIM or similar operations so as to release physical memory space of logical block addresses that are declared to be deleted by a user file management system. A series of data structures accounts for the levels of indirection used to manage the correspondence between a user logical block address and the physical location of the data in the memory system and to respond to user read and write requests by efficiently determining the current status of the user logical block address in the frame of reference of the memory system and substantially decoupling the TRIM management from the garbage collection and wear leveling operations. | 10-17-2013 |
20130275661 | PLATFORM STORAGE HIERARCHY WITH NON-VOLATILE RANDOM ACCESS MEMORY WITH CONFIGURABLE PARTITIONS - A non-volatile random access memory (NVRAM) is used in a computer system to perform multiple roles in a platform storage hierarchy. The NVRAM is byte-addressable by the processor and can be configured into one or more partitions, with each partition implementing a different tier of the platform storage hierarchy. The NVRAM can be used as mass storage that can be accessed without a storage driver. | 10-17-2013 |
20130282954 | SOLID-STATE DRIVE MANAGEMENT AND CONTROL - Various techniques of solid-state drive (“SSD”) management systems, components, modules, routines, and processes are described in this application. In one embodiment, a management engine for controlling a solid-state drive includes an input interface configured to receive a target operation profile from an input source. The management engine also includes a process component g configured to receive the target operation profile from the input interface, retrieve an operating policy from a database based on the target operation profile, and determine operating parameters for the SSD based on the retrieved operating policy. The management engine further includes a device interface coupled to the process component, the device interface being configured to transmit the determined operating parameters to the SSD for controlling operation of the SSD. | 10-24-2013 |
20130282955 | SYSTEM AND METHOD FOR LIMITING FRAGMENTATION - A method and system are disclosed for controlling the storage of data in a storage device to reduce fragmentation. The method may include a controller of a storage device receiving data for storage in non-volatile memory, proactively preventing fragmentation by only writing an amount of sequentially addressed logical groups of data into a main storage area of the storage device, such as multi-level cell (MLC) flash memory, and reactively defragmenting data previously written into the MLC memory when a trigger event is reached. The system may include a storage device with a controller configured to perform the method noted above, where the thresholds for minimum sequential writes into MLC, and for scanning the memory for fragmented data and removing fragmentation by re-writing the fragmented data already in MLC into new MLC blocks, may be fixed or variable. | 10-24-2013 |
20130282956 | Automobile MP3 System - An automobile MP3 system for an automobile is provided. The automobile MP3 system comprises a data storage device mounted within the automobile, the data storage device having memory for holding content and content downloading capability. The data storage device stores music and other content. | 10-24-2013 |
20130282957 | Managing Operational State Data In Memory Module - The specification and drawings present a new apparatus and method for managing/configuring by the memory module controller storing operational state data for operating the memory module controller into an extended random access memory comprised in a memory module and in a host system memory of a host device during various operational modes/conditions of the memory module and the host system memory. Essentially, the memory module controller operated as a master for the data transfers as described herein. The operational state data typically comprises state information, a logical to physical (L2P) mapping table and register settings. | 10-24-2013 |
20130282958 | Obsolete Block Management for Data Retention in Nonvolatile Memory - In a nonvolatile memory array, blocks that contain only obsolete data are modified by adding charge to their cells, increasing the charge level from the programmed charge levels that represented obsolete data to elevated charge levels. The increase in overall charge in such blocks lessens the tendency of such blocks to impact data retention in neighboring blocks. | 10-24-2013 |
20130282959 | SYSTEM OPERATION METHOD AND MEMORY CONTROLLER AND MEMORY STORAGE DEVICE USING THE SAME - A system operation method for controlling a rewritable non-volatile memory module is provided. The rewritable non-volatile memory module includes a plurality of physical blocks. The system operation method includes following steps. A first signal is received from a host system through a host interface. Whether a system setting of the host interface is to be modified is determined. If the system setting is to be modified, a system parameter is read from the physical blocks, and the system setting is modified according to the system parameter. A second signal is transmitted to the host system to establish a connection recognition between the rewritable non-volatile memory module and the host system. Thereby, the settings of transmission between the host system and the rewritable non-volatile memory module are made more flexible. | 10-24-2013 |
20130282960 | INTELLIGENT SCHEDULING OF BACKGROUND OPERATIONS IN MEMORY - A memory system or flash card may include an algorithm for identifying a pattern in a sustained or continuous write operation. In one example, a video recording device may be a host that continuously writes data to a memory card in an identifiable pattern. The pattern identification algorithm may be stored in the firmware of the memory card and used to schedule background operations during the predicted idle times in which the host is not writing data to the memory card. | 10-24-2013 |
20130282961 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROL THEREOF - A semiconductor memory device includes a nonvolatile semiconductor memory in which writing is carried out at a page unit and erasing is carried out at a block unit larger than the page unit, and a controller for transferring data between a host device and the nonvolatile semiconductor memory. The controller includes a log-management section that is configured to: (i) record a page unit of log data in a buffer area each time a monitored event (e.g., error) occurs, the buffer area being partitioned into a plurality of pages and the page unit of log data is recorded in a designated page of the buffer area, and (ii) prior to recording the page unit of log data in the designated page, copy part of the designated page to another page of the buffer area. | 10-24-2013 |
20130282962 | STORAGE CONTROL SYSTEM WITH FLASH CONFIGURATION AND METHOD OF OPERATION THEREOF - A storage control system and method of operation thereof includes: a memory circuit for accessing a configuration category; a configuration module, coupled to the memory circuit, for configuring the memory circuit with the configuration category; and an operation module, coupled to the configuration module, for controlling a performance characteristic of a memory device based on the configuration category. | 10-24-2013 |
20130282963 | NON-VOLATILE FLASH-RAM MEMORY WITH MAGNETIC MEMORY - A flash-RAM memory includes non-volatile random access memory (RAM) formed on a monolithic die and non-volatile page-mode memory formed on top of the non-volatile RAM, the non-volatile page-mode memory and the non-volatile RAM reside on the monolithic die. The non-volatile RAM is formed of stacks of magnetic memory cells arranged in three-dimensional form for higher density and lower costs. | 10-24-2013 |
20130282964 | FLASH MEMORY CACHE INCLUDING FOR USE WITH PERSISTENT KEY-VALUE STORE - Described is using flash memory, RAM-based data structures and mechanisms to provide a flash store for caching data items (e.g., key-value pairs) in flash pages. A RAM-based index maps data items to flash pages, and a RAM-based write buffer maintains data items to be written to the flash store, e.g., when a full page can be written. A recycle mechanism makes used pages in the flash store available by destaging a data item to a hard disk or reinserting it into the write buffer, based on its access pattern. The flash store may be used in a data deduplication system, in which the data items comprise chunk-identifier, metadata pairs, in which each chunk-identifier corresponds to a hash of a chunk of data that indicates. The RAM and flash are accessed with the chunk-identifier (e.g., as a key) to determine whether a chunk is a new chunk or a duplicate. | 10-24-2013 |
20130282965 | FLASH MEMORY CACHE INCLUDING FOR USE WITH PERSISTENT KEY-VALUE STORE - Described is using flash memory, RAM-based data structures and mechanisms to provide a flash store for caching data items (e.g., key-value pairs) in flash pages. A RAM-based index maps data items to flash pages, and a RAM-based write buffer maintains data items to be written to the flash store, e.g., when a full page can be written. A recycle mechanism makes used pages in the flash store available by destaging a data item to a hard disk or reinserting it into the write buffer, based on its access pattern. The flash store may be used in a data deduplication system, in which the data items comprise chunk-identifier, metadata pairs, in which each chunk-identifier corresponds to a hash of a chunk of data that indicates. The RAM and flash are accessed with the chunk-identifier (e.g., as a key) to determine whether a chunk is a new chunk or a duplicate. | 10-24-2013 |
20130282966 | Communicating to Update a Memory - Embedded devices typically have an operating system, one or more file-systems, as well as a bootloader and other data components resident in flash memory. During software development and testing, there is frequently a need to selectively update a combination of such images. The described technique organizes the images in the flash memory such that one can speed up the update process by eliminating relocation of existing images. A command-driven update mechanism provides a flexible process—eg, one can upload the images back to a host, one can update the update code itself, etc. A start handshake is used that enables auto-detection of the embedded serial port that is used for the update. | 10-24-2013 |
20130282967 | STATISTICAL WEAR LEVELING FOR NON-VOLATILE SYSTEM MEMORY - Statistical wear leveling is described that may be particularly useful for non-volatile system memory. In one embodiment, the invention includes a wear level move state machine to select an active block based on a wear criteria, to move the contents of the selected active block to a block from a free block list, and to move the selected active block to an unused block list, a free block list expansion state machine to take a block from a target free block list, to move the contents of the block to a block from the unused block list, and to move the block taken from the target block list to a free block list, and a target free block generation state machine to select blocks from the unused block list and to move the selected blocks to the target free block list. | 10-24-2013 |
20130282968 | INITIAL OPERATION OF A PORTABLE DATA CARRIER - In a portable data carrier having a non-volatile memory, a memory controller and a memory interface, an effected initial operation of the data carrier is checked through a request to a security unit of the data carrier via a security interface connected to the security unit. For this purpose, the data carrier comprises a memory portion comprising the memory interface and a body portion comprising the security interface, which are interconnected such that the memory portion can be folded out of the body portion, so that simultaneously the memory interface is laid open for a connection to an end device and the electrical connection between the security unit and the security interface is disconnected irreversibly. | 10-24-2013 |
20130290598 | Reducing Power Consumption by Migration of Data within a Tiered Storage System - Mechanisms identify one or more first storage devices in a first tier of the tiered storage system that may be placed in a minimal power consumption state and identify one or more data segments stored on the one or more first storage devices that are most likely to be accessed during a period of time in which the one or more first storage devices are in the minimal power consumption state. The mechanisms migrate the one or more data segments to one or more second storage devices in one of the first tier or a second tier of the storage system and place the one or more first storage devices in the minimal power consumption state. Access requests to the one or more data segments are serviced by the one or more second storage devices while the one or more first storage devices are in the minimal power consumption state. | 10-31-2013 |
20130290599 | LEVERAGING A HYBRID INFRASTRUCTURE FOR DYNAMIC MEMORY ALLOCATION AND PERSISTENT FILE STORAGE - Dynamic allocation of memory in a hybrid system is provided. In particular, a method and system is provided to leverage a hybrid infrastructure for dynamic memory allocation and persistent file storage. The method includes dynamically allocating a file or its part or to cache a file or its part between different storage technologies and respective memory technologies in a hybrid infrastructure. | 10-31-2013 |
20130290600 | DATA STORAGE BASED UPON TEMPERATURE CONSIDERATIONS - A method includes, in a nonvolatile memory device that includes a plurality of dies, detecting that a first temperature associated with a first die is equal to or exceeds a temperature threshold. A metablock is defined to include a first plurality of storage blocks that includes a first storage block of the first die. Each storage block of the metablock resides in a distinct die of the plurality of dies. The method also includes, in response to detecting that the first temperature is equal to or exceeds the temperature threshold, redefining the metablock to exclude from the redefined metablock any storage block associated with the first die. | 10-31-2013 |
20130290601 | LINUX I/O SCHEDULER FOR SOLID-STATE DRIVES - An I/O scheduler and a method for scheduling I/O requests to a solid-state drive (SSD) is disclosed. The I/O scheduler in accordance with the present disclosure bundles the write requests in such a form that the write requests in each bundle goes into one SSD block. Bundling the write requests in accordance with the present disclosure reduces write amplification and increases system performance. The I/O scheduler in accordance with the present disclosure also helps increasing the life of the SSDs. | 10-31-2013 |
20130290602 | DATA STORAGE DEVICE - A data storage device includes a memory, a controller, a first module, a first interface, and a second interface. The first interface and the second interface are coupled to the controller. The controller is used to access data in the memory, the first module is used to perform a first predetermined function. The second interface is inaccessible to the first module. The first interface may gain access to at least one additional module in the data storage device to perform at least one additional predetermined function which the second interface may not gain access to and may not perform. | 10-31-2013 |
20130290603 | EMULATED ELECTRICALLY ERASABLE MEMORY PARALLEL RECORD MANAGEMENT - A method of transferring data from a non-volatile memory (NVM) having a plurality of blocks of an emulated electrically erasable (EEE) memory to a random access memory (RAM) of the EEE includes accessing a plurality of records, a record from each block. A determination is made if any of the data signals of the first data signals are valid and thereby considered valid data signals. If there is only one or none that are valid, the valid data, if any is loaded into RAM and the process continues with subsequent simultaneous accesses. If more than one is valid, then the processes is halted until the RAM is loaded with the valid data, then the method continues with subsequent simultaneous accesses of records. | 10-31-2013 |
20130290604 | PROGRAM-DISTURB DECOUPLING FOR ADJACENT WORDLINES OF A MEMORY DEVICE - Subject matter disclosed herein relates to memory operations regarding programming bits into a memory array. | 10-31-2013 |
20130290605 | CONVERGED MEMORY AND STORAGE SYSTEM - Embodiments of the present invention provide an approach for Dynamic Random Access Memory (DRAM) and flash converged memory and storage. Specifically, in a typical embodiment, at least one substrate will be provided on which a DRAM unit and flash memory unit are positioned. A set (e.g., one or more of input/outputs (I/Os)) may be provided for the units. Such a set of I/Os may communicate storage and/or memory access requests to a set (e.g., one or more) of controllers, which control the DRAM and flash memory units. The set of controllers may comprise a single integrated controller or multiple controllers having separate and distinct functions (e.g., a memory controller, a storage controller, a DRAM controller, a flash controller, etc.). | 10-31-2013 |
20130290606 | POWER MANAGEMENT FOR A SYSTEM HAVING NON-VOLATILE MEMORY - Systems and methods are disclosed for power management of a system having non-volatile memory (“NVM”). One or more controllers of the system can optimally turn modules on or off and/or intelligently adjust the operating speeds of modules and interfaces of the system based on the type of incoming commands and the current conditions of the system. This can result in optimal system performance and reduced system power consumption. | 10-31-2013 |
20130290607 | STORING CACHE METADATA SEPARATELY FROM INTEGRATED CIRCUIT CONTAINING CACHE CONTROLLER - A technique includes using a cache controller of an integrated circuit to control a cache including cached data content and associated cache metadata. The technique includes storing the metadata and the cached data content off of the integrated circuit and organizing the storage of the metadata relative to the cached data content such that a bus operation initiated by the cache controller to target the cached data content also targets the associated metadata. | 10-31-2013 |
20130290608 | System and Method to Keep Parity Consistent in an Array of Solid State Drives when Data Blocks are De-Allocated - A method comprises sending a first command to a solid state drive (SSD), the first command indicating that the SSD can de-allocate a first plurality of logical block addresses (LBAs), and calculating first parity data for a redundant array of independent disks (RAID) array that includes the SSD in response to receiving a first reply from the SSD indicating that the first LBAs were de-allocated by the SSD. The first parity data is calculated based upon the first LBAs including all logical zeros. | 10-31-2013 |
20130290609 | MEMORY FORMATTING METHOD, MEMORY CONTROLLER, AND MEMORY STORAGE APPARATUS - A memory formatting method adapted to a memory storage apparatus is provided. The memory formatting method includes configuring a plurality of logical block addresses to be mapped to a portion of a plurality of physical blocks, generating a first file system data and a second file system data according to the size of the logical block addresses, and storing the first file system data into a first physical block, and the first physical block is mapped to a first logical block address among the logical block addresses. The memory formatting method also includes selecting a second physical block among the physical blocks, storing the second file system data into the second physical block, determining whether a format command is received, and when the format command is received, re-mapping the first logical block address to the second physical block. | 10-31-2013 |
20130290610 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a memory unit configured in page units, an error correction code (ECC) module for generating error correcting codes, a page information addition module for generating page information, and a controller for controlling the reading and writing of data to the memory unit. The controller is configured to associate error correction code information and page information with each frame unit of data written to the memory unit and to store the associated information with each frame unit. The controller is configured to output data to an external host in sizes less than one page unit, such as one frame unit. | 10-31-2013 |
20130290611 | POWER MANAGEMENT IN A FLASH MEMORY - The peak power requirements for operations performed on a FLASH memory circuit vary substantially, with reading, writing and erasing requiring increasing levels of power. When the memory is operated to improve performance using erase hiding, the performance of write or erase operations where the time periods for such operations can overlap results in increased peak power requirements. Controlling the time periods during which modules of a RAID group are permitted to perform erase operations, with respect to other modules in other RAID groups may smooth out the requirements. In addition, such scheduling may lead to improved efficiency in using shared data buses. | 10-31-2013 |
20130290612 | SOFT INFORMATION MODULE - A system and method for generating reliability information (aka “soft information”) from a flash memory device is disclosed. A plurality of memory cells are read by a data storage controller at a first read level to obtain a plurality of program values. On an error indicator being received in connection with reading the plurality of memory cells, the plurality of memory cells are read one or more times at one or more different read levels to categorize the plurality of memory cells into two or more cell program regions. A confidence value is then assigned to each memory cell based on a corresponding cell program region for the memory cell, the confidence value being representative of a likelihood that the memory cell is programmed to a corresponding program value read at the first read level. | 10-31-2013 |
20130290613 | STORAGE SYSTEM AND STORAGE APPARATUS - A storage system comprises a first controller and a plurality of storage devices. The plurality of storage devices configure RAID, each of which includes one or more non-volatile memory chips providing storage space where data from a host computer is stored, and a second controller coupled to the non-volatile memory chips. In case where the first controller receives an update request to update first data to second data from the host computer, the second controller in a first storage device of the storage devices is configured to store the second data in an area different from an area where the first data has been stored, in the storage space of the first storage device; generate information that relates the first data and the second data; and generate an intermediate parity based on the first and the second data. | 10-31-2013 |
20130290614 | FLASH MEMORY CONTROLLER - A method includes, in at least one aspect, asserting a control signal to one or more devices, determining an initial wait time after asserting the control signal, issuing a first command based on the initial wait time, determining a first interval time associated with the first command and a second command, and issuing the second command based on the first interval time. | 10-31-2013 |
20130290615 | COMPRESSION AND DECOMPRESSION OF DATA AT HIGH SPEED IN SOLID STATE STORAGE - Compression and decompression of data at high speed in solid state storage is described, including accessing a compressed data comprising a plurality of blocks of the compressed data, decompressing each of the plurality of blocks in a first stage of decompression to produce a plurality of partially decompressed blocks, and reconstructing an original data from the partially decompressed blocks in a second stage of decompression. | 10-31-2013 |
20130290616 | CONTROL APPARATUS OF NON-VOLATILE MEMORY AND IMAGE FORMING APPARATUS - An apparatus has an external memory control apparatus for controlling rewriting of a memory. The external memory control apparatus allows the memory to store the number of formed monochromatic images and changes a rewriting frequency of the memory according to the number of formed monochromatic images. | 10-31-2013 |
20130290617 | METHOD AND SYSTEM FOR CONTROLLING LOSS OF RELIABILITY OF NON-VOLATILE MEMORY - A method for controlling a loss of reliability of a non-volatile memory (NVM) included in an integrated circuit card (ICC) may include determining whether the NVM is reliable at the operating system (OS) side of the ICC, and generating an event associated with the reliability of the NVM at the OS side for an application of the ICC, if the NVM is determined to be unreliable. | 10-31-2013 |
20130290618 | HIGHER-LEVEL REDUNDANCY INFORMATION COMPUTATION - Higher-level redundancy information computation enables a Solid-State Disk (SSD) controller to provide higher-level redundancy capabilities to maintain reliable operation in a context of failures of non-volatile (e.g. flash) memory elements during operation of an SSD. A first portion of higher-level redundancy information is computed using parity coding via an XOR of all pages in a portion of data to be protected by the higher-level redundancy information. A second portion of the higher-level redundancy information is computed using a weighted-sum technique, each page in the portion being assigned a unique non-zero “index” as a weight when computing the weighted-sum. Arithmetic is performed over a finite field (such as a Galois Field). The portions of the higher-level redundancy information are computable in any order, such as an order based on order of read operation completion of non-volatile memory elements. | 10-31-2013 |
20130297851 | PERIPHERAL DEVICE AND DATA ACCESS CONTROL METHOD THEREOF - A peripheral device includes a first memory, a second memory, a first access controller, a second access controller and a main controller. When accessing data, first data is written to the first memory from the main controller while second data is read from the second memory to the main controller. Then the first data is written from the first memory to the second memory after writing the first data to the first memory and reading the second data from the second memory are completed. | 11-07-2013 |
20130297852 | SYSTEMS AND METHODS FOR PROVIDING EARLY HINTING TO NONVOLATILE MEMORY CHARGE PUMPS - Systems and methods for providing early hinting to nonvolatile memory charge pumps are disclosed. Charge pumps associated with one or more nonvolatile memory dies can be proactively activated based on a determination that a command queue of access requests contains at least a threshold number of consecutive access requests of the same type. Based on analysis of the command queue, the memory controller can transmit an early hint command to a nonvolatile memory die to proactively activate its charge pump to provide a voltage suitable for executing the consecutive access requests of the same type. | 11-07-2013 |
20130297853 | SELECTIVE WRITE-ONCE-MEMORY ENCODING IN A FLASH BASED DISK CACHE MEMORY - In a method for storing data in a flash memory array, the flash memory array includes a plurality of physical pages. The method includes receiving a request to perform a data access operation through a communication bus. The request includes data and a logical page address. The method further includes allocating one or more physical pages of the flash memory array to perform the data access operation. The method further includes, based on a historical usage data of the flash memory array, selectively encoding the data contained in the logical page into the one or more physical pages. | 11-07-2013 |
20130297854 | ENSURING WRITE OPERATION CONSISTENCY USING RAID STORAGE DEVICES - Solid-state storage devices (SSD) are combined with larger capacity magnetic disk-based RAID arrays for storing write data to ensure data consistency across multiple RAID disks. Write operations are stored in a sequential write buffer in at least one SSD to guarantee their storage and then copied from the sequential write buffer to the destination address in RAID array. The sequential write buffer stores write data in locations corresponding to the order of receipt of write operations. Write data from the sequential write buffer is transferred to the RAID array in the same order and a checkpoint index is frequently updated to indicate the completion of some transfers. During system initialization, a copy of the sequential write buffer and its associated checkpoint index are retrieved and used as a starting location for transferring write data from the sequential write buffer to the magnetic disk storage devices in the RAID array. | 11-07-2013 |
20130297855 | ENSURING WRITE OPERATION CONSISTENCY USING MULTIPLE STORAGE DEVICES - Relatively small capacity solid-state storage devices (SSD) are combined with larger capacity magnetic disk storage devices for storing storage block write data to ensure data consistency. Write operations are stored in a sequential write buffer in an SSD to guarantee the storage of write data and then copied from the sequential write buffer to the destination address in a magnetic disk storage device. The sequential write buffer store write data in locations corresponding to the order of receipt of write operations. Write data from the sequential write buffer is transferred to the magnetic disk storage device in the same order and a checkpoint index is frequently updated to indicate the completion of some transfers. During system initialization, the most recent value of the checkpoint index is retrieved and used as a starting location for transferring write data from the sequential write buffer to the magnetic disk storage device. | 11-07-2013 |
20130297856 | STORAGE SYSTEM AND CONTROL METHOD THEREFOR - A storage system comprises multiple memory packages and a storage controller. The multiple memory packages respectively comprise multiple nonvolatile semiconductor memory devices for storing data, and a memory controller for controlling the reading/writing of data from/to these multiple semiconductor memory devices, and the storage controller receives an I/O command issued from a host computer, creates, on the basis of the received I/O command, a first level command for controlling the multiple memory packages, and sends this first level command to the multiple memory packages. The memory controllers of the multiple memory packages create a second level command for the multiple nonvolatile semiconductor memory devices inside its own memory package, and estimate the power to be consumed in its own memory package. In a case where the estimated power consumption exceeds a preconfigured permissible power, suspends the execution of the received second level command. | 11-07-2013 |
20130297857 | PARALLEL COMPUTATION WITH MULTIPLE STORAGE DEVICES - A method and system are disclosed for allowing access to processing resources of one or more idle memory devices to an active memory device is disclosed, where the idle and active memory devices are associated with a common host. The resources shared may be processing power, for example in the form of using a processor of an idle memory to handle some of the logical-to-physical mapping associated with a host command, or may be other resources such as RAM sharing so that a first memory has expanded RAM capacity. The method may include exchanging tokens with resource sharing abilities, operation codes and associated data relevant to the requested resources. | 11-07-2013 |
20130297858 | SYSTEMS AND METHODS FOR PROVIDING CHANNEL BUFFER IN A SOLID-STATE DEVICE - Systems and methods for providing a buffer between a memory controller and memory devices in high performance solid state devices. Some embodiments include a solid state device system. The solid state device system can include a memory controller electrically coupled to a channel, where the memory controller is configured to select one of a plurality of flash memory devices and, in response to the selection, provide a control signal. The solid state device system can also include a buffer having a first tri-state logic gate coupled to the channel, where the buffer is configured to receive the control signal from the memory controller and, in response, to couple the channel to the selected one of the plurality of flash memory devices via the first tri-state logic gate and to decouple the remainder of the plurality of flash memory devices from the channel. | 11-07-2013 |
20130297859 | CONTROL DEVICE, STORAGE DEVICE, AND STORAGE CONTROL METHOD - A control device includes: a management information generation unit configured to generate or update logical-physical block address management information with respect to either data to be written to a non-volatile memory or data which has been already written in the non-volatile memory, the logical-physical block address management information indicating association between a logical block address and a physical block address on the non-volatile memory; and an access control unit configured to, during write of the data to the non-volatile memory, control write of the data as well as the logical-physical block address management information to a physical write unit of the non-volatile memory. | 11-07-2013 |
20130297860 | MEMORY SYSTEM HAVING A PLURALITY OF TYPES OF MEMORY CHIPS AND A MEMORY CONTROLLER FOR CONTROLLING THE MEMORY CHIPS - A memory controller converts controller output signals output from a controller into memory input signals according to the operation specifications of memory chips to operate, and outputs the resultant to the memory chips through a common bus. The memory controller also receives memory output signals output from the memory chips through the common bus, and converts the received signals into controller input signals receivable to the controller. This allows the single memory controller to access the plurality of types of memory chips. As a result, the memory controller can be reduced in chip size, lowering the cost of the memory system. | 11-07-2013 |
20130297861 | MEMORY SYSTEM HAVING A PLURALITY OF TYPES OF MEMORY CHIPS AND A MEMORY CONTROLLER FOR CONTROLLING THE MEMORY CHIPS - A memory controller converts controller output signals output from a controller into memory input signals according to the operation specifications of memory chips to operate, and outputs the resultant to the memory chips through a common bus. The memory controller also receives memory output signals output from the memory chips through the common bus, and converts the received signals into controller input signals receivable to the controller. This allows the single memory controller to access the plurality of types of memory chips. As a result, the memory controller can be reduced in chip size, lowering the cost of the memory system. | 11-07-2013 |
20130297862 | MEMORY SYSTEM HAVING A PLURALITY OF TYPES OF MEMORY CHIPS AND A MEMORY CONTROLLER FOR CONTROLLING THE MEMORY CHIPS - A memory controller converts controller output signals output from a controller into memory input signals according to the operation specifications of memory chips to operate, and outputs the resultant to the memory chips through a common bus. The memory controller also receives memory output signals output from the memory chips through the common bus, and converts the received signals into controller input signals receivable to the controller. This allows the single memory controller to access. the plurality of types of memory chips. As a result, the memory controller can be reduced in chip size, lowering the cost of the memory system. | 11-07-2013 |
20130297863 | MEMORY DEVICE RESPONDING TO DEVICE COMMANDS FOR OPERATIONAL CONTROLS - A memory device responding to device commands for operational controls. An embodiment of memory device includes one or more memory elements, a system element including a memory controller, and a physical interface including command input pins to receive commands for the memory device. The commands include commands for operational controls for the memory device, including one or both of a first command for a reset control to reset the memory device and a second command for a clock enable (CKE) control to halt internal clock distribution for the memory device. | 11-07-2013 |
20130304964 | DATA PROCESSING METHOD, AND MEMORY CONTROLLER AND MEMORY STORAGE DEVICE USING THE SAME - A data processing method for a re-writable non-volatile memory module is provided. The method includes receiving a write data stream associating to a logical access address of a logical programming unit; selecting a physical programming unit; and determining whether the write data stream associates with a kind of pattern. The method includes, if the write data stream associates with the kind of pattern, setting identification information corresponding to the logical access address as an identification value corresponding to the pattern, and storing the identification information corresponding to the logical access address into a predetermined area, wherein the write data stream is not programmed into the selected physical programming unit. The method further includes mapping the logical programming unit to the physical programming unit. Accordingly, the method can effectively shorten the time for writing data into the re-writable non-volatile memory module. | 11-14-2013 |
20130304965 | STORAGE UNIT MANAGEMENT METHOD, MEMORY CONTROLLER AND MEMORY STORAGE DEVICE USING THE SAME - A storage unit management method for managing a plurality of physical units in a rewritable non-volatile memory module is provided, wherein the physical units are at least grouped into a data area and a spare area. The method includes configuring a plurality of logical units for mapping to the physical units belonging to the data area, and determining whether the rewritable non-volatile memory module contains cold data. The method further includes performing a first wear-leveling procedure on the physical units if it is determined that the rewritable non-volatile memory module does not contain any cold data, and performing a second wear-leveling procedure on the physical units if it is determined that the rewritable non-volatile memory module contains the cold data. | 11-14-2013 |
20130304966 | NON-VOLATILE MEMORY DEVICE AND METHOD FOR PROGRAMMING THE SAME - A non-volatile memory device and a method for programming the same are disclosed. The non-volatile memory device includes first and second memory blocks, each of which includes a plurality of memory cells including a plurality of pages in which data is written; a data write unit, upon receiving a write signal and an address allocation signal, configured to write first data in a first page of the first memory block, and write second data in a first page of the second memory block; and a copy-back unit, upon receiving a chip idle signal and a copy-back control signal, configured to write the first data written in the first memory block into a second page of the second memory block. | 11-14-2013 |
20130304967 | INFORMATION MEMORY SYSTEM IN WHICH DATA RECEIVED SERIALLY IS DIVIDED INTO PIECES OF DATA AND MEMORY ABNORMALITY PROCESSING METHOD FOR AN INFORMATION MEMORY SYSTEM - An information memory system in which data received is divided into pieces of data, which are stored in memories in parallel, includes controller configured to storing a number of the divided pieces of data and monitoring a read request and a buffer full notice, in a case where the number of read requests does not reach the number of valid memory units and the buffer full notice continues in all buffers except for one buffer which does not output the read request, performing a read control corresponding to the buffers which output the buffer full notice, and performing control of the integration of a piece of data reconstructed, after being read from the memory unit corresponding to the buffer which does not output the read request and the pieces of data read from the memory units corresponding to the buffers which output the buffer full notice. | 11-14-2013 |
20130304968 | DEMOTING TRACKS FROM A FIRST CACHE TO A SECOND CACHE BY USING AN OCCUPANCY OF VALID TRACKS IN STRIDES IN THE SECOND CACHE TO CONSOLIDATE STRIDES IN THE SECOND CACHE - Information is maintained on strides configured in a second cache and occupancy counts for the strides indicating an extent to which the strides are populated with valid tracks and invalid tracks. A determination is made of tracks to demote from a first cache. A first stride is formed including the determined tracks to demote. The tracks from the first stride are to a second stride in the second cache having an occupancy count indicating the stride is empty. A determination is made of a target stride in the second cache based on the occupancy counts of the strides in the second cache. A determination is made of at least two source strides in the second cache having valid tracks based on the occupancy counts of the strides in the second cache. The target stride is populated with the valid tracks from the source strides. | 11-14-2013 |
20130304969 | PERFORMANCE IMPROVEMENT OF A CAPACITY OPTIMIZED STORAGE SYSTEM INCLUDING A DETERMINER - A system for storing data comprises a performance storage unit and a performance segment storage unit. The system further comprises a determiner. The determiner determines whether a requested data is stored in the performance storage unit. The determiner determines whether the requested data is stored in the performance segment storage unit in the event that the requested data is not stored in the performance storage unit. | 11-14-2013 |
20130304970 | SYSTEMS AND METHODS FOR PROVIDING HIGH PERFORMANCE REDUNDANT ARRAY OF INDEPENDENT DISKS IN A SOLID-STATE DEVICE - The present disclosure relates to systems and methods for providing high performance Redundant Array of Independent Disks (RAID) in a solid-state device. The present disclosure includes a solid state device. The solid state device can include a buffer having a plurality of bit cells, configured to maintain a plurality of bits of information. The solid state device can also include a memory controller configured to logically partition the plurality of bit cells into a plurality of logical blocks, each configured to maintain a data block. The solid state device can additionally include a RAID engine coupled to the buffer, where the buffer is configured to provide data blocks to the RAID engine, and in response, the RAID engine is configured to compute first parity bits from the data blocks and directly provide the first parity bits to one of a plurality of flash memory devices. | 11-14-2013 |
20130304971 | CONTROL DEVICE, STORAGE DEVICE, AND DATA WRITING METHOD - A control device includes a control unit that performs a writing control of supplied host data, according to a data writing request from a host apparatus, with respect to a non-volatile memory where multi-value storage with 2 bits or more is performed in one memory cell, having a lower level page and an upper level page for at least the multi-value storage as a physical page in which a physical address is set, and where data writing is performed using each physical page in an order of physical addresses, and that causes the data writing to be performed until the physical page immediately before the lower level page, such that the data writing according to a next data writing request is started from the lower level page. | 11-14-2013 |
20130304972 | CONTROL DEVICE, STORAGE DEVICE, AND STORAGE CONTROL METHOD - A control device includes a control unit that performs control of writing of data with respect to a first non-volatile memory, in which a size of a physical block that is a deletion unit is larger than a size of a physical page that is a minimum writing unit, and generates logical and physical address management information that indicates a correspondence relation between a physical page address and a logical address in a writing target physical block, in which data is written through the control of writing, so as to perform control so that the logical and physical address management information is stored in a second non-volatile memory every time data is written in the first non-volatile memory. | 11-14-2013 |
20130304973 | CONTROL DEVICE, STORAGE DEVICE, AND STORAGE CONTROL METHOD - A control device includes a control unit that performs control of writing of data with respect to a memory unit, in which a size of a physical block that is a deletion unit is larger than a size of a physical page that is a minimum writing unit, and generates logical and physical address management information that indicates a correspondence relation between a physical page address and a logical address in a writing target physical block, in which data is written through the control of writing, so as to perform control so that the logical and physical address management information is written in the writing target physical block. | 11-14-2013 |
20130304974 | SYSTEM AND METHOD FOR STORING DATA USING A FLEXIBLE DATA FORMAT - A flash storage device includes a flash storage for storing data and a controller for receiving a command in connection with user data and selecting a sector size associated with storing the user data. The controller allocates the user data among data sectors having the sector size and writes the data sectors to the flash storage. In some embodiments, the controller generates system data and stores the system data in the data sectors or a system sector, or both. | 11-14-2013 |
20130304975 | APPARATUSES FOR MANAGING AND ACCESSING FLASH MEMORY MODULE - A method for maintaining address mapping for a flash memory module is disclosed including: recording a first set of addresses corresponding to a first set of sequential logical addresses in a first section of a first addressing block; recording a second set of addresses corresponding to a second set of sequential logical addresses in a second section of the first addressing block; recording a third set of addresses corresponding to a third set of sequential logical addresses in a first section of a second addressing block; and recording a fourth set of addresses corresponding to a fourth set of sequential logical addresses in a second section of the second addressing block; wherein the second set of logical addresses is successive to the first set of logical addresses, and the third set of logical addresses is successive to the second set of logical addresses. | 11-14-2013 |
20130304976 | TECHNIQUES FOR PROVIDING DATA REDUNDANCY AFTER REDUCING MEMORY WRITES - A storage subsystem receives writes from a computer via a storage subsystem interface. The storage subsystem reduces a number of the writes. A single drive of the storage subsystem has primary and redundant storage devices with storage device interfaces. A disk controller of the single drive implements a data redundancy scheme by storing data associated with the reduced number of writes in the primary storage devices and by storing computed redundancy information in the redundant storage devices. The disk controller is operable without a loss of data in the presence of at least a single failure of any of the storage devices. Optionally the storage devices are flash memory devices. Optionally the disk controller is operable without a loss of data in the presence of at least two failures of any of the storage devices when a number of the redundant storage devices is at least two. | 11-14-2013 |
20130304977 | METHOD FOR PERFORMING MEMORY ACCESS MANAGEMENT, AND ASSOCIATED MEMORY DEVICE AND CONTROLLER THEREOF - A method for performing memory access management includes: with regard to a same Flash cell of a Flash memory, receiving a first digital value outputted by the Flash memory, requesting the Flash memory to output at least one second digital value, wherein the first digital value and the at least one second digital value are utilized for determining information of a same bit stored in the Flash cell, and a number of various possible states of the Flash cell correspond to a possible number of bit(s) stored in the Flash cell; based upon the second digital value, generating/obtaining soft information of the Flash cell, for use of performing soft decoding; and controlling the Flash memory to perform sensing operations by respectively utilizing a plurality of sensing voltages that are not all the same, in order to generate the first digital value and the second digital value. | 11-14-2013 |
20130304978 | HIGH-PERFORMANCE STORAGE STRUCTURES AND SYSTEMS FEATURING MULTIPLE NON-VOLATILE MEMORIES - A memory storage system that includes at least a storage controller, a first non-volatile, solid-state memory and a second non-volatile, solid-state memory. The storage controller has an interface to receive commands from a host system. The first non-volatile, solid-state memory device is coupled with the storage controller to at least store data received from the host system. The second non-volatile, solid-state memory is coupled with the storage controller to store context information corresponding to the data stored in the first non-volatile, solid-state memory device. | 11-14-2013 |
20130304979 | ACCESS CONTROL FOR NON-VOLATILE RANDOM ACCESS MEMORY ACROSS PLATFORM AGENTS - A controller is used in a computer system to control access to an NVRAM. The computer system includes a processor coupled to a non-volatile random access memory (NVRAM). The NVRAM is byte-rewritable and byte-erasable. The NVRAM stores data to be used by a set of agents including in-band agents and an out-of-band agent. The in-band agents run on a processor having one or more cores, and the out-of-band agent that runs on a non-host processing element. When the controller receives an access request from the out-of-band agent, the controller determines, based on attributes associated with the out-of-band agent, whether a region in the NVRAM is shareable by the out-of-band agent and at least one of the in-band agents. | 11-14-2013 |
20130304980 | AUTONOMOUS INITIALIZATION OF NON-VOLATILE RANDOM ACCESS MEMORY IN A COMPUTER SYSTEM - A non-volatile random access memory (NVRAM) is used in a computer system to store information that allows the NVRAM to autonomously initialize itself at power-on. The computer system includes a processor, an NVRAM controller coupled to the processor, and an NVRAM that comprises the NVRAM controller. The NVRAM is byte-rewritable and byte-erasable by the processor. The NVRAM stores a memory interface table containing information for the NVRAM controller to autonomously initialize the NVRAM upon power-on of the computer system without interacting with the processor and firmware outside of the NVRAM. The information is provided by the NVRAM controller to the processor to allow the processor to access the NVRAM. | 11-14-2013 |
20130311698 | DATA STORAGE DEVICE AND METHOD FOR FLASH BLOCK MANAGEMENT - The invention provides a data storage device. In one embodiment, the data storage device comprises a flash memory and a controller. The flash memory comprises a spare block pool and a data block pool, wherein the spare block pool comprises a plurality of spare blocks, and the data block pool comprises a plurality of data blocks. The controller determines a minimum erase count from the erase counts of the spare blocks and the data blocks, adds a first difference to the minimum erase count to obtain a jail threshold, compares the erase counts of the spare blocks with the jail threshold to obtain a plurality of jail blocks with the erase counts greater than the jail threshold, and confines the jail blocks to a jail pool. | 11-21-2013 |
20130311699 | OPERATIONS USING DIRECT MEMORY ACCESS - A system includes a serial interface, a peripheral device coupled to the serial interface, non-volatile memory, and a DMA controller including multiple linked channels. The various channels can be configured in different modes to facilitate the DMA controller performing various operations, such as data transfer, with respect to the non-volatile memory or the peripheral device. | 11-21-2013 |
20130311700 | Extending Lifetime For Non-volatile Memory Apparatus - A non-volatile memory apparatus includes non-volatile memory having a user block and a reserved block, a first connector for connecting to a host device, at least one second connector for connecting to a storage medium, and a first controller connected to the non-volatile memory, the first connector and the at least one second connector. Memory blocks of the storage medium are used as extra reserved blocks for the non-volatile memory apparatus. The first controller controls and remaps the user blocks and reserved blocks of the non-volatile memory, and the memory blocks of the storage medium. | 11-21-2013 |
20130311701 | DATA STORAGE DEVICE AND METHOD FOR FLASH BLOCK MANAGEMENT - The invention provides a data storage device. In one embodiment, the data storage device is coupled to a host, and comprises a flash memory and a controller. The flash memory comprises a spare block pool and a data block pool, wherein the spare block pool comprises a plurality of spare blocks, and the data block pool comprises a plurality of data blocks. The controller receives target data from the host, writes the target data to a current data block, and determines whether the current data block is full. When the current data block is full, the controller updates at least one table according to the information of the current data block. | 11-21-2013 |
20130311702 | DATA STORAGE DEVICE AND METHOD FOR FLASH BLOCK MANAGEMENT - A data storage device is coupled to a host and includes a flash memory and a controller. The flash memory comprises a spare block pool and a data block pool, wherein the spare block pool comprises a plurality of spare blocks, and the data block pool comprises a plurality of data blocks, wherein a spare block count indicates a total number of the spare blocks. The controller receives target data from the host, writes the target data to a current data block, determines whether a current programming page is the first page of the current data block, determines whether the spare block count is less than a spare block count threshold when the current programming page is the first page, and sets data move information for a data merge process when the spare block count is less than the spare block count threshold. | 11-21-2013 |
20130311703 | DATA STORAGE DEVICE AND METHOD FOR FLASH BLOCK MANAGEMENT - A data storage includes a flash memory and a controller. The flash memory comprises a spare block pool and a data block pool, wherein the spare block pool comprises a plurality of spare blocks, and the data block pool comprises a plurality of data blocks, wherein the spare blocks with erase counts higher than a hot threshold are determined as hot spare blocks, and a hot spare block count indicates a total number of the hot spare blocks. The controller receives target data from the host, writes the target data to a current data block, determines whether a current programming page is the first page of the current data block, determines whether the hot spare block count is greater than zero when the current programming page is the first page, and sets data move information for a wear-leveling process when the hot spare block count is greater than zero. | 11-21-2013 |
20130311704 | DATA STORAGE DEVICE AND METHOD FOR FLASH BLOCK MANAGEMENT - The invention provides a data storage device. In one embodiment, the data storage device is coupled to a host, and comprises a flash memory and a controller. The flash memory comprises a spare block pool and a data block pool, wherein the spare block pool comprises a plurality of spare blocks, and the data block pool comprises a plurality of data blocks. The controller receives target data from the host, writes the target data to a current programming data block, determines whether a current programming page is a first page of the current programming data block, determines whether data move information is set when the current page is not the first page, and when the data move information is set, perform a data move process according to the data move information within a limited time period. | 11-21-2013 |
20130311705 | DATA STORAGE DEVICE AND METHOD FOR FLASH BLOCK MANAGEMENT - The invention provides a data storage device. In one embodiment, the data storage device is coupled to a host, and comprises a plurality of flash memory areas and a controller. Each of the flash memory areas comprises a spare block pool and a data block pool, wherein the spare block pool comprises a plurality of spare blocks, and the data block pool comprises a plurality of data blocks. The controller receives target data from the host, selects a target memory area to which the target data is to be written from the flash memory areas, sets a physical address range parameter according to the target memory area, sets a spare block pool parameter according to the target memory area, and writes the target data to a current data block of the target memory area. | 11-21-2013 |
20130311706 | STORAGE SYSTEM AND METHOD OF CONTROLLING DATA TRANSFER IN STORAGE SYSTEM - An embodiment of the present invention is a storage system including a plurality of non-volatile storage devices for storing user data, and a controller for controlling data transfer between the plurality of non-volatile storage devices and a host. The controller includes a processor core circuit, a processor cache, and a primary storage device including a cache area for temporarily storing user data. The processor core circuit ascertains contents of a command received from the host. The processor core circuit ascertains a retention storage device of data to be transferred in the storage system in operations responsive to the command. The processor core circuit determines whether to transfer the data via the processor cache in the storage system, based on a type of the command and the ascertained retention storage device. | 11-21-2013 |
20130311707 | STORAGE CONTROL APPARATUS AND STORAGE CONTROL METHOD - A storage control apparatus comprises a storage unit, an association unit, and an execution unit. The storage unit stores association information showing multiple physical chunks which are configured in a physical address space of a nonvolatile semiconductor memory, multiple logical storage areas which are configured in a logical address space of the nonvolatile semiconductor memory, multiple logical chunks which are respectively associated with the multiple physical chunks, and an association between a logical storage area and a logical chunk. The association unit changes the association by changing the association information in accordance with a state of the nonvolatile semiconductor memory, and identifies based on the association information a physical storage area corresponding to a logical storage area specified in an input/output request from a computer. The execution unit executes the input/output request with respect to the identified physical storage area. | 11-21-2013 |
20130311708 | FILE PROTECTING METHOD AND SYSTEM, AND MEMORY CONTROLLER AND MEMORY STORAGE APPARATUS THEREOF - A file protecting method and system and a memory controller and a memory storage apparatus using the same are provided. The file protecting method includes performing a file protection enabling procedure for a file to generate an entry value backup according to at least one entry value corresponding to at least one cluster storing the file, which is recorded in a file allocation document, store the entry value backup in a secure storage area and change the entry value corresponding to the cluster storing the file in the file allocation document, wherein the file cannot be read according to the changed entry value. Accordingly, the file stored in the memory storage apparatus the can be effectively protected from being accessed by an un-authorized person. | 11-21-2013 |
20130311709 | METHODS AND APPARATUS FOR REALLOCATING ADDRESSABLE SPACES WITHIN MEMORY DEVICES - Integrated circuit systems include a non-volatile memory device (e.g, flash EEPROM device) and a memory processing circuit. The memory processing circuit is electrically coupled to the non-volatile memory device. The memory processing circuit is configured to reallocate addressable space within the non-volatile memory device. This reallocation is performed by increasing a number of physical addresses within the non-volatile memory device that are reserved as redundant memory addresses, in response to a capacity adjust command received by the memory processing circuit. | 11-21-2013 |
20130311710 | NONVOLATILE MEMORY DEVICE AND PROGRAM METHOD THEREOF - Disclosed is a nonvolatile memory device which includes a nonvolatile memory including a plurality of LSB and MSB pages at a plurality of wordlines; and a controller controlling the nonvolatile memory. The controller controls the nonvolatile memory such that an LSB program operation on a first wordline (first LSB page) of the plurality of wordlines is programmed and then an LSB program operation on a second wordline of the plurality of wordlines (second LSB page) is programmed. When the LSB program operation on the second wordline (second LSB page) is performed, the nonvolatile memory stores information about LSB data programmed at the first wordline (first LSB page) at a spare area of the second wordline (second LSB page). | 11-21-2013 |
20130311711 | NONVOLATILE MEMORY DEVICE AND PROGRAM METHOD THEREOF - Disclosed is a nonvolatile memory device which includes a nonvolatile memory having multi-level cell (MLC) storage; and a controller configured to control the nonvolatile memory, wherein if a logical address of write-requested data coincides with a logical address of data stored in the nonvolatile memory, the controller controls the nonvolatile memory to program the write-requested data prior to programming of a page sharing the same word line as a page including the data stored in the nonvolatile memory. | 11-21-2013 |
20130311712 | CONTROL APPARATUS, STORAGE DEVICE, AND STORAGE CONTROL METHOD - A control apparatus includes a control unit configured to perform control in such a manner that in a case where data is to be written into a physical area, which is the unit in which an erasing operation is performed, subjected to processing in a first non-volatile memory in response to a write request and in a case where the end of the data does not match a boundary between physical regions, which are the smallest units in which a writing operation is performed, in the first non-volatile memory, first data having a size smaller than the smallest units is stored in a predetermined temporary storage area, and thereafter in a case where second data specified by the same logical address as the first data is requested to be written, the first data and the second data are combined and written into the physical area subjected to processing. | 11-21-2013 |
20130311713 | SYSTEM AND APPARATUS FOR FLASH MEMORY DATA MANAGEMENT - The system and apparatus for managing flash memory data includes a host transmitting data, wherein when the data transmitted from the host have a first time transmission trait and the address for the data indicates a temporary address, temporary data are retrieved from the temporary address to an external buffer. A writing command is then executed and the temporary data having a destination address are written to a flash memory buffer. When the flash memory buffer is not full, the buffer data are written into a temporary block of the flash memory. The writing of buffer data into the temporary block includes using an address changing command, or executing a writing command to rewrite the external buffer data to the flash memory buffer so that the data are written into the temporary block. | 11-21-2013 |
20130311714 | APPARATUSES AND METHODS OF OPERATING FOR MEMORY ENDURANCE - Methods of operating an apparatus such as a computing system and/or memory device for memory endurance are provided. One example method can include receiving m digits of data having a first quantity of digits represented by a first data state that is more detrimental to memory cell wear than a second data state. The m digits of data are encoded into n digits of data having a second quantity of digits represented by the first data state. The value n is greater than the value m. The second quantity is less than or equal to the first quantity. The n digits of data are stored in an apparatus having memory cells. | 11-21-2013 |
20130311715 | METHOD FOR MODIFYING DATA MORE THAN ONCE IN A MULTI-LEVEL CELL MEMORY LOCATION WITHIN A MEMORY ARRAY - A method and apparatus for marking a block of multi-level memory cells for performance of a block management function by programming at least one bit in a lower page of the memory cell block such that a first logic state is stored in the at least one bit in the lower page; programming at least one bit in an upper page of the memory cell block such that the first logic state is stored in the at least one bit in the upper page; reprogramming the at least one bit in the upper page such that the at least one bit transitions from the first logic state to a second logic state; identifying the first logic state in the at least one bit of a lower page and the transition of at least one corresponding bit in the upper page from the first logic state to the second logic state; and in response, marking the corresponding memory cell block for performance of a block management function. | 11-21-2013 |
20130311716 | MEMORY CONTROLLER - A microcomputer retains a group definition table associating the sector sections created by dividing all sectors into multiple sections under a given condition with different memory regions on a flash memory, respectively. A memory control section makes reference to the group definition table to identify a memory region corresponding to a specified sector, and searches the identified memory region range for a physical address corresponding to the specified sector. Furthermore, the memory control section moves a specified sector within the identified memory region range for rewriting data corresponding to the specified sector. | 11-21-2013 |
20130318283 | SPECIALIZING I/0 ACCESS PATTERNS FOR FLASH STORAGE - Systems and methods for efficiently using solid-state devices are provided. Some embodiments provide for a data processing system that uses a non-volatile solid-state device as a circular log, with the goal of aligning data access patterns to the underlying, hidden device implementation, in order to maximize performance. In addition, metadata can be interspersed with data in order to align data access patterns to the underlying device implementation. Multiple input/output (I/O) buffers can also be used to pipeline insertions of metadata and data into a linear log. The observed queuing behavior of the multiple I/O buffers can be used to determine when the utilization of the storage device is approaching saturation (e.g., in order to predict excessively-long response times). Then, the I/O load on the storage device may be shed when utilization approaches saturation. As a result, the overall response time of the system is improved. | 11-28-2013 |
20130318284 | Data Storage Device and Flash Memory Control Method - A data storage device and a flash memory control method. The disclosed data storage device includes a random access memory, a flash memory and a controller. The flash memory provides a data space for data storage and an in-system-program (ISP) space stored with ISP codes. One of the ISP codes is a permanent-ISP code. The permanent-ISP code contains a look-up table showing how the ISP codes stored in the flash memory map to the random access memory. By the controller, the permanent-ISP code obtained from the flash memory is loaded into the random access memory. Based on the look-up table contained in the permanent-ISP code and loaded in the random access memory with the permanent-ISP code, subsequently requested ISP codes are obtained from the ISP codes of the flash memory and are loaded into the random access memory. | 11-28-2013 |
20130318285 | FLASH MEMORY CONTROLLER - An apparatus and method of managing the operation of a plurality of FLASH chips provides for a physical layer (PHY) interface to a FLASH memory circuit having a plurality of FLASH chips having a common interface bus. The apparatus has a PHY for controlling the voltages on the interface pins in accordance with a microprogrammable state machine. A data transfer in progress over the bus may be interrupted to perform another command to another chip on the shared bus and the data transfer may be resumed after completion of the another command. | 11-28-2013 |
20130318286 | MEASURE OF HEALTH FOR WRITING TO LOCATIONS IN FLASH - A number of pulses to modify information stored in a given location in a plurality of locations is obtained for each of the plurality of locations in flash memory. A location having the largest number of pulses is selecting from the plurality of locations. The selected location is written to. | 11-28-2013 |
20130318287 | BRIDGING DEVICE HAVING A FREQUENCY CONFIGURABLE CLOCK DOMAIN - A composite memory device including discrete memory devices and a bridge device for controlling the discrete memory devices. A configurable clock controller receives a system clock and generates a memory clock having a frequency that is a predetermined ratio of the system clock. The system clock frequency is dynamically variable between a maximum and a minimum value, and the ratio of the memory clock frequency relative to the system clock frequency is set by loading a frequency register with a Frequency Divide Ratio (FDR) code any time during operation of the composite memory device. In response to the FDR code, the configurable clock controller changes the memory clock frequency. | 11-28-2013 |
20130318288 | METHOD AND SYSTEM FOR DATA DE-DUPLICATION - An apparatus may comprise a non-volatile random access memory to store data and a processor coupled to the non-volatile random access memory. The apparatus may further include a data de-duplication module operable on the processor to read a signature of incoming data, compare the signature to first data in the non-volatile random access memory, and flag the incoming data for discard when the signature indicates a match to the first data. Other embodiments are disclosed and claimed. | 11-28-2013 |
20130318289 | SELECTIVE ENABLEMENT OF OPERATING MODES OR FEATURES VIA HOST TRANSFER RATE DETECTION - Selective enablement of operating modes or features of a storage system via host transfer rate detection enables, in some situations, enhanced performance. For example, a Solid-State Disk (SSD) having a serial interface compatible with a particular serial interface standard selectively enables coalescing of status information for return to a host based on detecting a particular host transfer rate capability. Some hosts are not fully compliant with the particular standard, being unable to properly process the coalesced status information. The selective enablement disables status coalescing for a non-compliant host and enables status coalescing for at least some compliant hosts, without the SSD having prior knowledge of coupling to a noncompliant/compliant host. The SSD conservatively determines the host is non-compliant/compliant based on a negotiated speed of the serial interface, and selectively disables/enables status coalescing in response to the negotiated speed. | 11-28-2013 |
20130326113 | USAGE OF A FLAG BIT TO SUPPRESS DATA TRANSFER IN A MASS STORAGE SYSTEM HAVING NON-VOLATILE MEMORY - Systems and methods are disclosed for usage of a flag bit to suppress data transfer in a mass storage system having non-volatile memory (“NVM”). In some embodiments, a host of the system can issue queue-able trim commands by dispatching non-data transfer write commands to the NVM. In some embodiments, the host can track the read behavior of a particular application over a period of time. As a result, the host can maintain heuristics of logical sectors that are most frequently read together. The host can then notify the NVM to pre-fetch data that the application will most likely request at some point in the future. These notifications can take the form of non-data transfer read commands. Each non-data transfer read commands can include a flag bit that is set to indicate that no data transfer is desired. | 12-05-2013 |
20130326114 | WRITE MITIGATION THROUGH FAST REJECT PROCESSING - Apparatus and method for data management in a memory, such as but not limited to a flash memory array. In accordance with some embodiments, a first hash value associated with a first set of data stored in a memory is compared to a second hash value associated with a second set of data pending storage to the memory. The second set of data is stored in the memory responsive to a mismatch between the first and second hash values. | 12-05-2013 |
20130326115 | BACKGROUND DEDUPLICATION OF DATA SETS IN A MEMORY - Apparatus and method for data management in a memory, such as but not limited to a flash memory array. In accordance with some embodiments, a plurality of data sets in a memory are identified as having a common data content and different physical addresses in the memory. A selected one of the data sets is marked as valid data and the remaining data sets are marked as stale data responsive to evaluation of at least one variable parameter associated with the physical addresses at which the data sets are respectively stored. | 12-05-2013 |
20130326116 | ALLOCATING MEMORY USAGE BASED ON QUALITY METRICS - A tiered memory system includes a memory controller for a primary memory and a secondary memory, where the secondary memory is used as a cache for the primary memory. The memory controller is configured to cause redundant data that is stored in the primary memory of the memory system to be stored in first memory locations of the secondary memory. The controller causes data that is not stored in the primary memory to be stored in second memory locations of the secondary memory. The second memory locations have at least one of lower bit error rate and higher access speed than the first memory locations. | 12-05-2013 |
20130326117 | APPARATUS, SYSTEM, AND METHOD FOR GROUPING DATA STORED ON AN ARRAY OF SOLID-STATE STORAGE ELEMENTS - Methods, storage controllers, and systems for grouping data stored on an array of solid-state storage elements are described. One method includes sequentially writing user data to an append point at a head of a log stored in an array of solid-state storage elements. The user data is stored in a plurality of logical erase blocks of the array. The method further includes selecting partially invalidated logical erase blocks of the array based on a characteristic for the partially invalidated logical erase blocks and arranging valid portions of the selected partially invalidated logical erase blocks into groups based on the characteristic. The method further includes writing the groups of valid portions to the log. | 12-05-2013 |
20130326118 | Data Storage Device and Flash Memory Control Method - A data storage device and a Flash memory control method. A data storage device comprises a Flash memory and a controller. The controller controls the Flash memory in accordance with firmware. When the firmware is available for at least a predetermined time period without being requested by a host, the controller, driven according to the firmware, performs a garbage-collection operation on the Flash memory without a request from the host. | 12-05-2013 |
20130326119 | STORAGE DEVICE HAVING NONVOLATILE MEMORY DEVICE AND WRITE METHOD - Disclosed is a method of writing data in a storage device including a nonvolatile memory device. The method includes receiving write data with a write request, detecting a number of free blocks, if the detected number of free blocks is less than a threshold value, allocating a log block only in accordance with a sub-block unit, but if the detected number of free blocks is not less than the threshold value, allocating the log block in accordance with one of the sub-block unit and a physical block unit, wherein the sub-block unit is smaller than the physical block unit. | 12-05-2013 |
20130326120 | DATA STORAGE DEVICE AND OPERATING METHOD FOR FLASH MEMORY - A data storage device and operating method for a FLASH memory are disclosed. The data storage device includes a FLASH memory and a controller. The FLASH memory includes a first block and a second block. The first and second blocks each includes a plurality of pages. The controller executes a firmware to determine whether a data segment from a host is a complete page segment. When the data segment is a complete page segment, the controller stores the data segment into the first block. When the data segment is an incomplete page segment, the controller stores the data into segment the second block. | 12-05-2013 |
20130326121 | DATA-STORAGE DEVICE AND FLASH MEMORY CONTROL METHOD - FLASH memory is allocated to provide a data-storage device and management tables. The management tables may record logical-to-physical address mapping information in a hierarchical structure consisting of at least two levels. Further, in addition to the logical-to-physical address mapping information, the management tables may further provide a valid page count table and an invalid block record. The logical-to-physical address mapping information is updated after an update of the valid page count table is completed. The invalid block record is maintained based on the valid page count table. | 12-05-2013 |
20130326122 | DISTRIBUTED MEMORY ACCESS IN A NETWORK - A method of distributed memory access in a network, the network including a plurality of distributed compute elements, at least one control element and a plurality of distributed memory elements, wherein a data element is striped into data segments, the data segments being imported on at least a number of the distributed memory elements by multiple paths in the network, includes receiving, by a requesting element, credentials including an access permission for accessing the number of distributed memory elements and location information from the control element, the location information indicating physical locations of the data segments on the number of distributed memory elements; and launching, by the requesting element, a plurality of data transfers of the data segments over the multiple paths in the network to and/or from the physical locations. | 12-05-2013 |
20130326123 | MEMORY MANAGEMENT DEVICE AND METHOD, AND PROGRAM - There is provided a memory management device including a non-volatile memory that performs writing and reading of data on a per-page basis, and performs erasing on a per-block basis, and a control unit that manages a data process in the non-volatile memory by performing logical-physical translation on a per-translation unit (TU) basis, and performs a fold process. The control unit sets data of a physical TU corresponding to unnecessary logical TU information to be excluded from a copy target in the fold process based on the unnecessary logical TU information, the unnecessary logical TU information being notified of by a file system and representing a logical TU corresponding to a physical TU in which unnecessary data is physically written. | 12-05-2013 |
20130326124 | POWER MANAGEMENT ARCHITECTURE BASED ON MICRO/PROCESSOR ARCHITECTURE WITH EMBEDDED AND EXTERNAL NVM - A control unit for power supply circuits of points of load (POL) of an electronic system includes a means for autonomous customization by the customer-user of the original control program residing in the ROM of the device, as well as configuration of control parameters of the POL. Microprocessor architecture of the device includes a dedicated logic block and a rewritable non-volatile memory coupled to the data bus of the device or to an auxiliary bus thereof, thus providing a means for software extension of the power supply circuits. RAM is loaded at start-up with data of modified or added routines for implementing new commands and values of configuration and control data of the POL. The RAM may optionally be subjected to encryption/decryption for protection. During operation, program execution jumps from ROM address space to RAM address space and vice versa when certain values of a program counter are reached. | 12-05-2013 |
20130326125 | FLASH MEMORY APPARATUS AND DATA ACCESS METHOD FOR FLASH MEMORY WITH REDUCED DATA ACCESS TIME - A data access method for flash memory includes: receiving a first data from a host terminal by utilizing a flash memory controller; transmitting and writing the first data into a single-level cell of the flash memory form the flash memory controller; and when the flash memory controller receives a second data from the host terminal, utilizing the flash memory controller to execute a copy back program to merge at least a portion of the first data stored in the single-level cell into a multi-level cell. | 12-05-2013 |
20130326126 | ELECTRONIC CONTROL UNIT - An electronic control unit (ECU) has a memory area in a non-volatile memory that stores a control program in a rewritable manner for controlling a predetermined control object. The ECU also has an operation unit for performing a process according to the control program stored in the memory and for performing a rewrite process to rewrite contents of the control program stored in the memory area when a predetermined rewrite condition is met. The memory area has a plurality of sub-memory areas that are exclusively defined in a non-overlapping manner. From among the plurality of sub-memory areas a read sub-memory area, from which the control program is read by the operation unit to perform the process according to the control program, is different and separate from a rewrite sub-memory area, which stores program contents of the control program that is rewritten by the rewrite process. | 12-05-2013 |
20130326127 | Sub-block Accessible Nonvolatile Memory Cache - Subject matter disclosed herein relates to sub-block accessible cache memory. | 12-05-2013 |
20130326128 | Methods and Apparatus for Passing Information to a Host System to Suggest Logical Locations to Allocate to a File - Methods and apparatus for passing information to a host system to suggest logical locations to allocate to a file are disclosed. Generally, when a host system determines a need to allocate a logical location to a file, the host system sends a non-data command to a memory system. In response, the memory system sends information to the host system that includes one or more logical locations to allocate to the file. By suggesting one or more logical locations to allocate to a file, the memory system may reduce a number of data consolidation or garbage collection operations that will need to be performed in the future, thereby improving performance of the memory system. | 12-05-2013 |
20130326129 | STORAGE DEVICE INCLUDING FLASH MEMORY AND CAPABLE OF PREDICTING STORAGE DEVICE PERFORMANCE BASED ON PERFORMANCE PARAMETERS - A storage device includes a semiconductor memory storing data. A controller instructs to write data to the semiconductor memory in accordance with a request the controller receives. A register holds performance class information showing one performance class required to allow the storage device to demonstrate best performance which the storage device supports, of performance classes specified in accordance with performance. | 12-05-2013 |
20130326130 | Techniques for increasing a lifetime of blocks of memory - Techniques are described for increasing a lifetime of a plurality of blocks of memory by equalizing a variation between the blocks. In operation, blocks to be written are allocated from a set of blocks having a lifetime factor below a threshold. The threshold is reset as required to resupply the set of blocks available for allocation. | 12-05-2013 |
20130332644 | METHOD OF INITIALIZING A NON-VOLATILE MEMORY SYSTEM - A method of initializing a non-volatile memory system is disclosed. System data are written to a non-volatile memory based on a formula rule at a factory, and a number of copies of the system data are written to the non-volatile memory. The system data are searched in the non-volatile memory according to the formula rule and a selected data access mode. At least one operating parameter of the selected data access mode is reconfigured, followed by checking if the searched system data are successfully read. The system data are utilized to set the at least one operating parameter of the non-volatile memory system when the searched system data are successfully read from the non-volatile memory. | 12-12-2013 |
20130332645 | SYNCHRONOUS AND ANSYNCHRONOUS DISCARD SCANS BASED ON THE TYPE OF CACHE MEMORY - A computational device maintains a first type of cache and a second type of cache. The computational device receives a command from the host to release space. The computational device synchronously discards tracks from the first type of cache, and asynchronously discards tracks from the second type of cache. | 12-12-2013 |
20130332646 | PERFORMING ASYNCHRONOUS DISCARD SCANS WITH STAGING AND DESTAGING OPERATIONS - A controller receives a request to perform staging or destaging operations with respect to an area of a cache. A determination is made as to whether one or more discard scans are being performed or queued for the area of the cache. In response to determining that one or more discard scans are being performed or queued for the area of the cache, the controller avoids satisfying the request to perform the staging or the destaging operations with respect to the area of the cache. | 12-12-2013 |
20130332647 | METHOD AND APPARATUS FOR FAULT TOLERANT FOTA UPDATE WITH SINGLE BACKUP BLOCK WRITE - A method for recovering from an interruption during a Firmware Over-The-Air (FOTA) update is provided. The method includes identifying a missing block of a plurality of blocks to be updated in the first memory, the missing block corresponding to a block being updated when the interruption occurred, copying a backup block into a backup buffer, simulating an application of the FOTA update in a second memory, the simulation including, for each block of the plurality of blocks to be updated, performing a reversible operation on the contents of the backup buffer and an updated block, and updating the backup buffer with the operation result, replacing the missing block with the updated backup buffer, and resuming the FOTA update. | 12-12-2013 |
20130332648 | MAINTAINING VERSIONS OF DATA IN SOLID STATE MEMORY - Various embodiments are directed to maintaining versions of data within a solid state memory. At least one request to write at least one dataset to a logical page of a solid state memory is received from a file system. At least one physical page in a data block of the solid state memory associated with the logical page is identified. A processor stores the dataset in the at least one physical page. At least one data versioning tag is associated with the at least one dataset in a data structure associated with the logical page. The data versioning tag identifies the at least one dataset as a given version of the logical page. The at least one dataset is maintained as accessible from the at least one physical page irrespective of subsequent write operations to the logical page in response to associating the at least one data versioning tag. | 12-12-2013 |
20130332649 | FILE SYSTEM FOR MAINTAINING DATA VERSIONS IN SOLID STATE MEMORY - One or more embodiments are directed to managing data in a solid state memory supporting data versioning. A file system reserves a plurality of logical pages from a solid state memory. Each logical page in the plurality of logical pages is associated with a plurality of physical pages in the solid state memory. Each logical page in the plurality of logical pages is assigned to one group in a plurality of groups. A request is sent to a flash translation layer for an operation to be performed by the flash translation layer on a group in the plurality of groups. | 12-12-2013 |
20130332650 | FLASH TRANSLATION LAYER SYSTEM FOR MAINTAINING DATA VERSIONS IN SOLID STATE MEMORY - One or more embodiments are directed to managing data in a solid state memory supporting data versioning. At least one request to perform an operation on at least one logical page of a solid state memory is received from a file system. A data structure associated with the at least one logical page is identified. The data structure at least identifies one or more physical pages associated with the at least one logical page, and a version of the at least one logical page represented by a dataset stored in each of the one or more physical pages. The operation is performed on the at least one logical page based on the data structure that has been identified. | 12-12-2013 |
20130332651 | DISK SUBSYSTEM AND DATA RESTORATION METHOD - A disk subsystem and a data restoration method with which the rise time when the disk subsystem is restored can be shortened. | 12-12-2013 |
20130332652 | COMPUTER SYSTEM AND METHOD FOR CONTROLLING COMPUTER SYSTEM - The present invention provides a computer system comprising a server and a storage system having a compression function, wherein the server includes a control unit and a cache, and the storage system has a storage area provided by a plurality of storage devices. When a designated data of a received read request is stored in the cache, the control unit of the server returns the stored data as a response to the read request, and when the designated data is not stored in the cache, the control unit acquires the designated data compressed via the compression function and stored in the storage area in the compressed state from the storage system, decompresses the acquired compression data, and returns the same as a response to the read request. | 12-12-2013 |
20130332653 | MEMORY MANAGEMENT METHOD, AND MEMORY CONTROLLER AND MEMORY STORAGE DEVICE USING THE SAME - A memory management method adapted to a rewritable non-volatile memory module having a plurality of physical erase units is provided. The operation mode of each physical erase unit is set to include three modes. A first mode indicates all physical program units to be programmable, a second mode and a third mode indicate upper physical program units to be non-programmable, but the third mode is unswitchable to the first or the second mode. The physical erase units are grouped into a first area and a second area. Each physical erase unit in the first area switchably operates in the first or the second mode, and each physical erase unit in the second area operates in the third mode. If a condition is satisfied, a physical erase unit in the first area is grouped to the second area. Thereby, the lifespan of the rewritable non-volatile memory module is prolonged. | 12-12-2013 |
20130332654 | DATA VERSIONING IN SOLID STATE MEMORY - One or more embodiments are directed a solid state storage device for maintaining versions of data. The solid state storage device comprises a processor and a solid state memory communicatively coupled to the processor. A flash translation layer is configured to perform a method comprising creating at least one data structure associated with at least one logical page of the solid state memory. The logical page is associated with at least one physical page in a data block of the solid state memory. A first set of information associated with the logical page is stored in the data structure. A second set of information associated with the physical page is stored in the data structure. The second set of information comprises at least versioning information identifying which version of the logical page is represented by a dataset stored within the physical page. | 12-12-2013 |
20130332655 | MAINTAINING VERSIONS OF DATA IN SOLID STATE MEMORY - One or more embodiments are directed a solid state storage device for maintaining versions of data. The solid state storage device comprises a processor and a solid state memory communicatively coupled to the processor. A flash translation layer receives at least one request from a file system to write at least one dataset to a logical page of the solid state memory. At least one physical page in a data block of the solid state memory associated with the logical page is identified. At least one dataset in the physical page is stored. At least one data versioning tag is associated with the dataset in a data structure associated with the logical page. The data versioning tag identifies the dataset as a given version of the logical page. The dataset is maintained as accessible from the physical page irrespective of subsequent write operations to the logical page. | 12-12-2013 |
20130332656 | FILE SYSTEM FOR MAINTAINING DATA VERSIONS IN SOLID STATE MEMORY - One or more embodiments are directed to managing data in a solid state memory supporting data versioning. A file system residing at an information processing system reserves a plurality of logical pages from a solid state memory. Each logical page in the plurality of logical pages is associated with a plurality of physical pages in the solid state memory. Each logical page in the plurality of logical pages is assigned to one group in a plurality of groups. A request is sent to a flash translation layer for an operation to be performed by the flash translation layer on a group in the plurality of groups. | 12-12-2013 |
20130332657 | FLASH TRANSLATION LAYER SYSTEM FOR MAINTAINING DATA VERSIONS IN SOLID STATE MEMORY - One or more embodiments are directed to maintaining versions of data within a solid state memory. At least one request to perform an operation on at least one logical page of a solid state memory is received from a file system. A data structure associated with the at least one logical page is identified. The data structure at least identifies one or more physical pages associated with the at least one logical page, and a version of the at least one logical page represented by a dataset stored in each of the one or more physical page. The operation is performed on the at least one logical page based on the data structure that has been identified. | 12-12-2013 |
20130332658 | DATA STORAGE SYSTEM AND METHOD THEREOF - The present invention discloses a data storage system using a solid state disk to replace a non-volatile memory. The data storage system comprises a plurality of controllers, a first storage unit and a second storage unit. The plurality of controllers are electrically connected with each other, and are capable of storing data into said storage units and restoring data from said storage units. When a controller receives the data transmitted from a remote device, a data journal is generated and stored into the first storage unit. After a message of “successfully received” is sent back to the remote device, the data is transferred to the second storage unit. | 12-12-2013 |
20130332659 | SEMICONDUCTOR STORAGE DEVICE AND CONTROLLER - A semiconductor storage device includes memory cells, select transistors, memory strings, first and second blocks, word lines, and select gate lines. In the memory string, the current paths of plural memory cells are connected in series. When data are written in a first block, after a select gate line connected to the gate of a select transistor of one of the memory strings in the first block is selected, the data are sequentially written in the memory cells in the memory string connected to the selected select gate line. When data are written in the second block, after a word line connected to the control gates of memory cells of different memory strings in the second block is selected, the data are sequentially written in the memory cells of the different memory strings in the second block which have their control gates connected to the selected word line. | 12-12-2013 |
20130332660 | Hybrid Checkpointed Memory - Apparatuses, systems, methods, and computer program products are disclosed for hybrid checkpointed memory. A method includes referencing data of a range of virtual memory of a host. The referenced data is already stored by a non-volatile medium. A method includes writing, to a non-volatile medium, data of a range of virtual memory that is not stored by the non-volatile medium. A method includes providing access to data of a range of virtual memory from a non-volatile medium using a persistent identifier associated with referenced data and written data. | 12-12-2013 |
20130332661 | INFORMATION PROCESSING APPARATUS AND METHOD AND PROGRAM - There is provided an information processing apparatus including a rewrite frequency management section configured to manage a rewrite frequency of a page included in a nonvolatile primary storage apparatus having an upper limit in the rewrite frequency, and a data processing section configured, when an instruction for writing write data to a predetermined page is issued and a rewrite frequency of the predetermined page reaches a threshold value that is less than the upper limit of the rewrite frequency of the primary storage apparatus, to write the write data to another page different from the predetermined page, the other page storing no effective data and having a rewrite frequency that does not reach the threshold value. | 12-12-2013 |
20130332662 | INFORMATION PROCESSING APPARATUS AND METHOD AND PROGRAM - There is provided an information processing apparatus including a table saving unit configured to copy an address conversion table stored in a first storage area of a memory to a storage area other than the first storage area and save the copied address conversion table, a table recovery unit configured to recover the address conversion table of a saving time point by copying the saved address conversion table to the first storage area of the memory, and a rewrite control unit configured to, when there is a rewrite request for data of a virtual address associated with a physical address on the address conversion table after the address conversion table has been saved, change the physical address associated with the virtual address, and cause the rewritten data to be stored in a storage area corresponding to the changed physical address. | 12-12-2013 |
20130332663 | DATA STORAGE APPARATUS WITH A HDD AND A REMOVABLE SOLID STATE DEVICE - According to an example, a data storage apparatus may include a non-volatile primary storage medium, a coupling interface to removably receive a non-volatile solid state device, a communication line connected to the non-volatile primary storage medium and the coupling interface, and a storage controller connected to the communication line. The storage controller may determine a memory type of the non-volatile solid state device, cache a first type of data in the non-volatile solid state device in response to a determination that the non-volatile to solid state device is of a first memory type, and cache a second type of data in the non-volatile solid state device in response to a determination that the non-volatile solid state device is of a second memory type, in which the second type of data differs from the first type of data. | 12-12-2013 |
20130339573 | OPTIMIZING WRITE PERFORMANCE TO FLASH MEMORY - Embodiments relate to optimizing write performance of a flash device. Aspects include receiving a request to evict a plurality of pages from a main memory and determining a block size for the flash device. Aspects also include grouping the plurality of pages from the main memory into a move specification block, wherein a size of the move specification block is the block size and writing the move specification block to the flash device. The block size being determined based on one or more operational characteristics of the flash device. | 12-19-2013 |
20130339574 | VARIABILITY AWARE WEAR LEVELING - Techniques are presented that include determining, for data to be written to a nonvolatile memory, a location in the nonvolatile memory to which the data should be written based at least on one or more wear metrics corresponding to the location. The one or more wear metrics are based on measurements of the location. The measurements estimate physical wear of the location. The techniques further include writing the data to the determined location in the nonvolatile memory. The techniques may be performed by methods, apparatus (e.g., a memory controller), and computer program products. | 12-19-2013 |
20130339575 | DATA STORAGE DEVICE AND DATA TRIMMING METHOD - A data storage device is disclosed. In one embodiment, the data storage device comprises a flash memory and a controller. The flash memory comprises a plurality of blocks, wherein each block comprises a plurality of pages, and each page comprises a plurality of data trimming units which is a smallest unit for data modification. After a data trimming process has been performed on an address range of the flash memory, the controller determines a last page corresponding to an ending address of the address range, determines whether data values stored in the last page with addresses subsequent to the ending address are all equal to a specific data pattern, and sets the value of a trimming flag corresponding to the last page to be 1 when the data values stored in the last page with addresses subsequent to the ending address are all equal to the specific data pattern. | 12-19-2013 |
20130339576 | METHOD FOR CONSTRUCTING ADDRESS MAPPING TABLE OF SOLID STATE DRIVE - A method for constructing an address mapping table of a solid state drive is provided. The address mapping table is stored in a non-volatile memory of the solid state drive. The method includes the following steps. After the solid state drive is powered on, a command from a host is received. Then, a logical allocation address is calculated according to a logical block address corresponding to the command. Then, the calculated logical allocation address is defined as an initial address, and a specified number of logical allocation addresses starting from the initial address and corresponding physical allocation addresses are loaded into a cache memory, so that a first portion of the address mapping table is constructed into the cache memory. Afterwards, the solid state drive responds the command according to the first portion of the address mapping table. | 12-19-2013 |
20130339577 | METHOD FOR READING A MULTILEVEL CELL IN A NON-VOLATILE MEMORY DEVICE - A non-volatile memory device has a memory array comprising a plurality of memory cells. The array can operate in either a multilevel cell or single level cell mode and each cell has a lower page and an upper page of data. The memory device has a data latch for storing flag data and a cache latch coupled to the data latch. A read method comprises initiating a lower page read of a memory cell and reading, from the data latch, flag data that indicates whether a lower page read operation is necessary. | 12-19-2013 |
20130339578 | SERVER AND DRIVE CONTROL DEVICE - According to one embodiment, a drive control device includes a monitor, data memory and a controller. The monitor monitors an operating state of a solid-state drive and detects whether the solid-state drive is busy. The data memory is capable of holding temporarily a write target data which should be written to the solid-state drive or a read target data which was read from the solid-state drive and should be transmitted to a requestor. The controller which writes the write target data to the data memory when the controller receives a write request and the monitor detects that the solid-state drive is busy, and which writes the write target data held in the data memory to the solid-state drive after the solid-state drive becomes not busy. | 12-19-2013 |
20130339579 | NUMERIC REPRESENTATION TO IMPROVE LIFE OF SOLID STATE STORAGE DEVICES - Technologies and implementations for improving life of a solid state storage device are generally disclosed. | 12-19-2013 |
20130339580 | STRIPE-BASED NON-VOLATILE MULTILEVEL MEMORY OPERATION - Stripe-based non-volatile multilevel memory operation can include writing a number of lower stripes including programming a number of lower pages of information in each of the number of lower stripes. An upper stripe can be written including programming a number of upper pages of the information in the upper stripe. Each of the number of upper pages can correspond to a respective one of the number of lower pages. Each of the respective ones of the number of lower pages corresponding to the number of upper pages can be programmed in a different lower stripe of the number of lower stripes. | 12-19-2013 |
20130339581 | Flash Storage Controller Execute Loop - A storage controller is provided that contains multiple processors. In some embodiments, the storage controller is coupled to a flash memory module having multiple flash memory groups, each flash memory group corresponding to a distinct flash port in the storage controller, each flash port comprising an associated processor. Each processor handles a portion of one or more host commands, including reads and writes, allowing multiple parallel pipelines to handle one or more host commands simultaneously. | 12-19-2013 |
20130339582 | Flash Storage Controller Execute Loop - A storage controller is provided that contains multiple processors. In some embodiments, the storage controller is coupled to a flash memory module having multiple flash memory groups, each flash memory group corresponding to a distinct flash port in the storage controller, each flash port comprising an associated processor. Each processor handles a portion of one or more host commands, including reads and writes, allowing multiple parallel pipelines to handle one or more host commands simultaneously. | 12-19-2013 |
20130339583 | SYSTEMS AND METHODS FOR TRANSFERRING DATA OUT OF ORDER IN NEXT GENERATION SOLID STATE DRIVE CONTROLLERS - Systems and methods are provided for transferring data back and forth from a NAND based storage device by issuing instructions for reading an allocation unit. The instructions may be issued out of order with respect to a sequential order of the data. The allocation unit related information is stored in a linked list data structure. The stored linked list data structure may be accessed for processing the allocation unit related information out of order with respect to the sequential order of the data. | 12-19-2013 |
20130339584 | METHOD FOR ACCESSING FLASH MEMORY HAVING PAGES USED FOR DATA BACKUP AND ASSOCIATED MEMORY DEVICE - The present invention provides a method for accessing a flash memory, where a block of the flash memory includes pages whose quantity is (2 | 12-19-2013 |
20130339585 | Management of Non-Volatile Memory Systems Having Large Erase Blocks - A non-volatile memory system of a type having blocks of memory cells erased together and which are programmable from an erased state in units of a large number of pages per block. If the data of only a few pages of a block are to be updated, the updated pages are written into another block provided for this purpose. Updated pages from multiple blocks are programmed into this other block in an order that does not necessarily correspond with their original address offsets. The valid original and updated data are then combined at a later time, when doing so does not impact on the performance of the memory. If the data of a large number of pages of a block are to be updated, however, the updated pages are written into an unused erased block and the unchanged pages are also written to the same unused block. By handling the updating of a few pages differently, memory performance is improved when small updates are being made. The memory controller can dynamically create and operate these other blocks in response to usage by the host of the memory system. | 12-19-2013 |
20130339586 | METHODS FOR ADAPTIVELY PROGRAMMING FLASH MEMORY DEVICES AND FLASH MEMORY SYSTEMS INCORPORATING SAME - A method for programming data into a first plurality of rows within a second plurality of erase sectors of a flash memory device using a programming process having at least one selectable parameter, the method includes characterizing each of at least one row subsets, each row subset comprising at least one row from among said first plurality of rows, thereby to generate at least one row subset characteristic value; and programming data into at least a portion of at least one individual row belonging to at least one row subset, using a programming process having at least one selectable parameter, said at least one selectable parameter being set at least partly in accordance with the row subset characteristic value characterizing a row subset to which said individual row belongs; wherein at least two row subsets of an array of flash memory cells differ from each other by their row subset characteristic values. | 12-19-2013 |
20130339587 | STORAGE SYSTEM EMPLOYING MRAM AND ARRAY OF SOLID STATE DISKS WITH INTEGRATED SWITCH - A high-availability storage system includes a first storage system and a second storage system. The first storage system includes a first Central Processing Unit (CPU), a first physically-addressed solid state disk (SSD) and a first non-volatile memory module that is coupled to the first CPU. Similarly, the second storage system includes a second CPU and a second SSD. Upon failure of one of the first or second CPUs, or the storage system with the non-failing CPU continues to be operational and the storage system with the failed CPU is deemed inoperational and the first and second SSDs remain accessible. | 12-19-2013 |
20130339588 | System on Chip with Reconfigurable SRAM - A system on chip includes a random access memory, a read-only memory, and a processor. The processor is configured to, during a development phase of the system on chip, read program code from the random access memory and execute the program code. The program code is developed during the development phase until a completed version of the program code is reached. The processor is configured to, during an operational phase of the system on chip, (i) read the completed version from the read-only memory, (ii) execute the completed version, and (iii) cache data in the random access memory. The processor is configured to, during the operational phase and in response to an improvement to the completed version of the program code being developed, (i) read program code corresponding to the improvement from the random access memory, and (ii) read remaining portions of the completed version from the read-only memory. | 12-19-2013 |
20130339589 | ADAPTIVE CONFIGURATION OF NON-VOLATILE MEMORY - Examples are disclosed for adaptive configuration of non-volatile memory. The examples include a mode register configured to include default and updated values to indicate one or more configurations of the non-volatile memory. The examples may also include discoverable capabilities maintained in a configuration table that may indicate memory address lengths and/or operating power states. | 12-19-2013 |
20130339590 | SEMICONDUCTOR DEVICE WITH NONVOLATILE MEMORY PREVENTED FROM MALFUNCTIONING CAUSED BY MOMENTARY POWER INTERRUPTION - In an internal register, a value for controlling operation of a flash memory is stored. A power shutoff detection register holds a value which changes when power shutoff occurs, and data stored in a specific memory cell is written in the power shutoff detection register. An EX-OR circuit compares the data stored in the specific memory cell with the value of the power shutoff detection register to thereby detect power shutoff. When power shutoff is detected, the value of the internal register is re-set. Thus, when power shutoff occurs, the flash memory can be prevented from malfunctioning. | 12-19-2013 |
20130346668 | Virtual Memory Module - A memory controller of a mass memory device determining that a memory operation has been initiated which involves the mass memory device, and in response dynamically checks for available processing resources of a host device that is operatively coupled to the mass memory device and thereafter puts at least one of the available processing resources into use for performing the memory operation. In various non-limiting examples: the available processing resources may be a core engine of a multi-core CPU, a DPS or a graphics processor; central processing unit; a digital signal processor; and a graphics processor; and it may also be dynamically checked whether memory resources of the host are available and those can be similarly put into use (e.g., write data to a DRAM of the host, process data in the DRAM with the host DSP, then write the processed data to the mass memory device). | 12-26-2013 |
20130346669 | UPDATING HARDWARE LIBRARIES FOR USE BY APPLICATIONS ON A COMPUTER SYSTEM WITH AN FPGA COPROCESSOR - A computer system includes one or more field programmable gate arrays as a coprocessor that can be shared among processes and programmed using hardware libraries. Given a set of hardware libraries, an update process periodically updates the libraries and/or adds new libraries. One or more update servers can provide information about libraries available for download, either in response to a request or by notifying systems using such libraries. New available libraries can be presented to a user for selection and download. Requests for updated libraries can arise in several ways, such as through polling for updates, exceptions from applications attempting to use libraries, and upon compilation of application code. | 12-26-2013 |
20130346670 | METHOD FOR CONTROLLING DATA WRITE OPERATION OF A MASS STORAGE DEVICE - A method for controlling data write operation of a mass storage device is provided. The mass storage device has a controller and a memory unit. The method includes connecting the mass storage device to a host device, and receiving a voltage provided from the host device; sensing and monitoring whether the voltage is lower than a first predefined voltage; writing data to the mass storage device with a first frequency when the sensed voltage is higher than the first predefined voltage; and writing data to the mass storage device with a second frequency when the sensed voltage is lower than the first predefined voltage, wherein the second frequency is adjusted by decreasing the first frequency. | 12-26-2013 |
20130346671 | On-Chip Bad Block Management for NAND Flash Memory - Certain functions relating to creation and use of a look-up table for bad block mapping may be implemented “on chip” in the memory device itself, that is on the same die in an additional circuit, or even within the command and control logic of the memory device, so as to reduce the overhead. Moreover, the on-chip implementation of the look-up table may be tightly integrated with other functions of the command and control logic to enable powerful new commands for NAND flash memory, such as a continuous read command and variations thereof. | 12-26-2013 |
20130346672 | Multi-Tiered Cache with Storage Medium Awareness - The subject disclosure is directed towards a multi-tiered cache having cache tiers with different access properties. Objects are written to a selected a tier of the cache based upon object-related properties and/or cache-related properties. In one aspect, objects are stored in an active log among a plurality of logs. The active log is sealed upon reaching a target size, with a new active log opened. Garbage collecting is performed on a sealed log, such as the sealed log with the most garbage therein. | 12-26-2013 |
20130346673 | METHOD FOR IMPROVING FLASH MEMORY STORAGE DEVICE ACCESS - A method for improving flash memory storage device access is disclosed. The steps of the method comprises requesting to read/write data of logical address by a host; setting up an engine by a CPU; looking up physical address and updating at least one table stored in at least one flash memory by the engine; and reading/writing data from/to the at least one flash memory. Thereby, the engine is accessing the data from each table in parallel to significantly reduce the total operation time. | 12-26-2013 |
20130346674 | DATA WRITING METHOD, MEMORY CONTROLLER AND MEMORY STORAGE DEVICE - A data writing method for controlling a rewritable non-volatile memory module having a plurality of physical erase units is provided. The method includes: receiving a write command which instructs writing data to a first logical address, wherein the first logical address is mapped to a second physical erase unit; determining whether the second physical erase unit is in a sequential writing state which represents that the physical programming units over a predetermined ratio in the second physical erasing unit have been successively written sequentially within a predetermined time; if yes, writing the data into a third physical erasing unit in a first programming mode, wherein the first programming mode represents that a plurality of upper physical programming units are non-programmable. Accordingly, the data writing rate is increased. | 12-26-2013 |
20130346675 | DATA STORING METHOD, AND MEMORY CONTROLLER AND MEMORY STORAGE APPARATUS USING THE SAME - A data storing method for a rewritable non-volatile memory module is provided. The method includes dividing logical addresses into a plurality of logical zones, and respectively establishing a plurality of logical address mapping tables for the logical zones. The method also includes writing data of a logical address into a physical program unit; and recording a mapping record indicating the logical address is mapped to the physical program unit in a temp mapping table. The method further includes: if the temp mapping table is full, updating the mapping relations between the logical addresses and the physical program units in the logical address mapping tables based on mapping records recorded in the temp mapping table, and deleting the mapping records in the temp mapping table. | 12-26-2013 |
20130346676 | OPERATING METHOD OF DATA STORAGE DEVICE - Provided is an operating method of a data storage device including a plurality of nonvolatile memory devices. The operating method includes the steps of: dividing storage areas of the nonvolatile memory devices into a first memory area and a second memory area; determining wear levels of each of the first memory area and the second memory area; and varying a ratio of the first memory area and the second memory area according to the determined wear levels. | 12-26-2013 |
20130346677 | NON-VOLATILE MEMORY DEVICE - A non-volatile memory device comprises a first storage unit which stores mapping information between a plurality of first addresses and a plurality of second addresses, and data; a second storage unit having a storage capacity smaller than that of the first storage unit; and a decoder which receives a first read address that is one of the plurality of first addresses, and while the mapping information is provided from the first storage unit to the second storage unit in order to locate a second read address that is one of the plurality of second addresses and corresponds to the first read address, applies a read command for reading data corresponding to the second read address to the first storage unit. | 12-26-2013 |
20130346678 | MEMORY EXPANDING DEVICE - A memory expanding device includes an input and output part coupleable to an external optical interface, a controller coupled to the input and output part through a first internal optical interface, a main memory module coupled to the controller through a second internal optical interface, and a sub-memory module coupled to the controller through a first internal electrical interface. | 12-26-2013 |
20130346679 | SYSTEM OF GENERATING SCRAMBLE DATA AND METHOD OF GENERATING SCRAMBLE DATA - A system of generating scramble data includes a linear feedback shift register and a scramble engine. The linear feedback shift register is used for generating a plurality of first scramble values according to an initial value. The scramble engine is coupled to the linear feedback shift register for utilizing at least one bit of a first scramble value of the plurality of first scramble values to execute a first logic operation on other bits of the first scramble value to generate a second scramble value corresponding to the first scramble value. A bit number of the second scramble value is the same as a bit number of the first scramble value. | 12-26-2013 |
20140006687 | Data Cache Apparatus, Data Storage System and Method | 01-02-2014 |
20140006688 | Endurance and Retention Flash Controller with Programmable Binary-Levels-Per-Cell Bits Identifying Pages or Blocks as having Triple, Multi, or Single-Level Flash-Memory Cells | 01-02-2014 |
20140006689 | NON-VOLATILE MEMORY DEVICE, CONTROL METHOD FOR INFORMATION PROCESSING DEVICE, AND INFORMATION PROCESSING DEVICE | 01-02-2014 |
20140006690 | STORAGE DEVICE CAPABLE OF INCREASING ITS LIFE CYCLE AND OPERATING METHOD THEREOF | 01-02-2014 |
20140006691 | Memory Pre-Characterization | 01-02-2014 |
20140006692 | MEMORY PROTECTION | 01-02-2014 |
20140006693 | SEMICONDUCTOR DEVICE AND OPERATING METHOD THEREOF | 01-02-2014 |
20140006694 | DATA STORAGE DEVICE AND OPERATING METHOD THEREOF | 01-02-2014 |
20140006695 | INFORMATION PROCESSING APPARATUS | 01-02-2014 |
20140006696 | APPARATUS AND METHOD FOR PHASE CHANGE MEMORY DRIFT MANAGEMENT | 01-02-2014 |
20140013025 | HYBRID MEMORY WITH ASSOCIATIVE CACHE - A hybrid memory system includes a primary memory comprising a host memory space arranged as memory sectors corresponding to host logical block addresses (host LBAs). A secondary memory is implemented as a cache for the primary host memory. A hybrid controller is configured map the clusters of host LBAs to clusters of solid state drive (SSD) LBAs. The SSD LBAs correspond to a memory space of the cache. Mapping of the host LBA clusters to the SSD LBA clusters is fully associative such that any host LBA cluster can be mapped to any SSD LBA cluster. | 01-09-2014 |
20140013026 | MEMORY ACCESS REQUESTS IN HYBRID MEMORY SYSTEM - Incoming memory access requests are routed in a set of incoming queues, the incoming memory access requests comprise a range of host logical block addresses (LBAs) that correspond to a memory space of a primary memory. The host LBA range is mapped to clusters of secondary memory LBAs, the secondary memory LBAs corresponding to a memory space of a secondary memory. Each incoming memory access request queued in the set of incoming queues is transformed into one or more outgoing memory access requests that include a range of secondary memory LBAs or one or more clusters of secondary memory LBAs. The outgoing memory access requests are routed in a set of outgoing queues. The secondary memory is accessed using the outgoing memory access requests. | 01-09-2014 |
20140013027 | LAYERED ARCHITECTURE FOR HYBRID CONTROLLER - Approaches for implementing a controller for a hybrid memory that includes a main memory and a cache for the main memory are discussed. The controller comprises a hierarchy of abstraction layers, wherein each abstraction layer is configured to provide at least one component of a cache management structure. Each pair of abstraction layers utilizes processors communicating through an application programming interface (API). The controller is configured to receive incoming memory access requests from a host processor and to manage outgoing memory access requests routed to the cache using the plurality of abstraction layers. | 01-09-2014 |
20140013028 | HARDWARE FLASH MEMORY WEAR MONITORING - A system for monitoring wear in a flash memory device that is written by receiving program and erase commands from a microprocessor on a memory bus includes a non-volatile memory separate from the flash memory device that stores a number of completed erase cycles for each sector of the flash memory device; and a memory monitor circuit that monitors the memory bus for a completed erase cycle for an erased sector and updates the number of completed erase cycles in the non-volatile memory for the erased sector. | 01-09-2014 |
20140013029 | MEMORY STORAGE DEVICE AND REPAIRING METHOD THEREOF - A memory storage device and a repairing method thereof are provided. The memory storage device has a rewritable non-volatile memory module having multiple physical units. The physical units include at least one backup physical unit which is configured to be accessed only by a specific command set and stored with at least one customized data. The method includes receiving a specific read command from a host system for reading the backup physical unit and transmitting the customized data therein to the host system when the memory storage device is capable of receiving and processing commands from the host system, the specific read command belongs to the specific command set; and writing the customized data from the host system into a corresponding physical unit to restore the memory storage device to a factory setting when receiving the writing command from the host system for writing the customized data. | 01-09-2014 |
20140013030 | MEMORY STORAGE DEVICE, MEMORY CONTROLLER THEREOF, AND METHOD FOR WRITING DATA THEREOF - A method for writing data is provided, including: configuring multiple logical programming units for mapping to a portion of the physical programming units in the rewritable non-volatile memory module, and dividing each logical programming unit into multiple logical management units, wherein a size of each logical management unit is identical to a basic access unit of a host system. The method includes: receiving a first data from the host system, determining whether a logical start address of the first data is not aligned to a start address of each logical management unit within the first logical programming unit and/or determining whether a logical end address of the first data is not aligned to an end address of each logical management unit within the first logical programming unit. If the determination result is positive, filling the first data by using a second data which is larger than the basic access unit. | 01-09-2014 |
20140013031 | DATA STORAGE APPARATUS, MEMORY CONTROL METHOD, AND ELECTRONIC APPARATUS HAVING A DATA STORAGE APPARATUS - According to one embodiment, a data storage apparatus comprises a first controller, a second controller, a third controller, and a fourth controller. The first controller controls a flash memory, writing and reading data, in units of blocks, to and from the flash memory. The second controller detects any a write-interrupted block is interrupted by the first controller. The third controller sets the write-interrupted block detected by the second controller, as a block to be refreshed in another block. The fourth controller performs the process of refreshing. | 01-09-2014 |
20140013032 | METHOD AND APPARATUS FOR CONTROLLING WRITING DATA IN STORAGE UNIT BASED ON NAND FLASH MEMORY - A method and apparatus for controlling writing of data in a storage unit based on a NAND flash memory are provided. The method includes determining reference values for classifying dirty pages to be written in the storage unit into a plurality of groups; calculating, with respect to each of the dirty pages, a hotness indicating a possibility of a change of data; classifying the dirty pages into the groups corresponding to reference values most similar to the calculated hotness; determining whether sizes of the groups are greater than a size of a segment, where the segment is a unit for performing a write request in the storage unit; and requesting a write operation for each segment with respect to groups having a size at least equal to the size of the segment to the storage unit. | 01-09-2014 |
20140013033 | OPTIMIZED FLASH MEMORY WITHOUT DEDICATED PARITY AREA AND WITH REDUCED ARRAY SIZE - A method and system for optimizing flash memory without dedicated parity area and with reduced array size. The memory size of a multi level cell (MLC) flash is reduced and controller operation is simplified. Simplified operation includes the controller being able to program each host data page to an integer number of flash pages. A maximal available information bits per cell (IBPC) is maintained in a flash device while also maximizing the programming throughput of the flash. Features include the ability to dynamically select which number of cell states is used by flash memory cells. | 01-09-2014 |
20140013034 | NONVOLATILE RANDOM ACCESS MEMORY AND DATA MANAGEMENT METHOD - A data management method for a main memory including a memory controller and a nonvolatile RAM includes; designating code page data temporarily stored in a standby area of the nonvolatile RAM as set, copying the code page data from the standby area to an in-use area of the nonvolatile RAM, designating the code page data stored in the in-use area as reset, and thereafter, during rebooting of a user device incorporating the main memory, invalidating the reset code page data while retaining the set code page data in the nonvolatile RAM. | 01-09-2014 |
20140013035 | SOLID STATE STORAGE DEVICE CONTROLLER WITH EXPANSION MODE - Solid state storage device controllers, solid state storage devices, and methods for operation of solid state storage device controllers are disclosed. In one such solid state storage device, the controller can operate in either an expansion DRAM mode or a non-volatile memory mode. In the DRAM expansion mode, one or more of the memory communication channels normally used to communicate with non-volatile memory devices is used to communicate with an expansion DRAM device. | 01-09-2014 |
20140013036 | USER DEVICE HAVING NONVOLATILE RANDOM ACCESS MEMORY AND METHOD OF BOOTING THE SAME - Disclosed is a method of booting a user device including a nonvolatile random access memory (RAM) and a mode register. The method includes reading a Basic Input/Output System (BIOS) refresh setting during a booting operation, and setting the mode register to a refresh timing mode of the nonvolatile RAM according to the BIOS refresh setting. The refresh timing mode selectively includes a refresh inactivation mode for inactivating a refresh operation of the nonvolatile RAM or a refresh execution mode of multiple refresh execution modes having corresponding different refresh periods for activating the refresh operation of the nonvolatile RAM. | 01-09-2014 |
20140013037 | ELECTRONIC CONTROL APPARATUS AND DATA REWRITING SYSTEM - An electronic control apparatus includes: a plurality of processing devices that have a rewritable non-volatile memory and that execute a predetermined process in accordance with stored data that is stored in the non-volatile memory, wherein each of the processing devices extracts individual rewriting data included within a dedicated address range that is individually allocated in advance for each of the processing devices, out of rewriting data transmitted from an external rewriting apparatus, and rewrites the stored data that is stored in the non-volatile memory of each of the processing devices by using the individual rewriting data. | 01-09-2014 |
20140013038 | DATA STORAGE DEVICE AND OPERATING METHOD FOR FLASH MEMORY - A data storage device and an operating method for a FLASH memory are disclosed. The disclosed data storage device includes a FLASH memory and a controller. The FLASH memory provides a storage space which is stored with a first storage type system information and a second storage type system information. Data recognition for the first storage type system information is stricter than that of the second storage type information. The controller reads the storage space of the FLASH memory and performs an error checking and correction process on data read from the storage space, and, based on the storage type system information, among the first and second storage type information, which first passes the error checking and correction process, the controller operates the FLASH memory. | 01-09-2014 |
20140013039 | ADAPTIVE MEMORY SYSTEM FOR ENHANCING THE PERFORMANCE OF AN EXTERNAL COMPUTING DEVICE - An adaptive memory system is provided for improving the performance of an external computing device. The adaptive memory system includes a single controller, a first memory type (e.g., Static Random Access Memory or SRAM), a second memory type (e.g., Dynamic Random Access Memory or DRAM), a third memory type (e.g., Flash), an internal bus system, and an external bus interface. The single controller is configured to: (i) communicate with all three memory types using the internal bus system; (ii) communicate with the external computing device using the external bus interface; and (iii) allocate cache-data storage assignment to a storage space within the first memory type, and after the storage space within the first memory type is determined to be full, allocate cache-data storage assignment to a storage space within the second memory type. | 01-09-2014 |
20140013040 | INFORMATION PROCESSING APPARATUS EQUIPPED WITH OVERWRITE DELETION FUNCTION, METHOD OF CONTROLLING THE SAME, AND STORAGE MEDIUM - An information processing apparatus which is capable of effectively using an overwrite deletion function and a hibernation function. An image forming apparatus as the information processing apparatus that is equipped with an overwrite deletion function for overwriting data stored in a HDD, and a hibernation function for causing data stored in a RAM to be stored in the HDD. In a case where one of the overwrite deletion function and the hibernation function is enabled, a CPU disables the other function. | 01-09-2014 |
20140013041 | SIMULTANEOUS READ AND WRITE DATA TRANSFER - A controller for an arrangement of memory devices may issue a write command without waiting for the receipt of a previously issued read command. An addressed memory device may read data out onto the data bus according to a read command while, simultaneously, writing data according to a write command received subsequent to the read command. | 01-09-2014 |
20140013042 | METHOD FOR MASKING THE END-OF-LIFE TRANSITION OF AN ELECTRONIC DEVICE AND DEVICE COMPRISING A CORRESPONDING CONTROL MODULE - The invention relates to a method for masking the end-of-life transition of an electronic microprocessor device comprising a reprogrammable non-volatile memory containing an end-of-life state variable (FdVE). The value of the variable (FdVE) is loaded (A) into random access memory. Prior to the execution of any current command (COM), the value of the variable (FdVR) in random access memory is checked (B). The end-of-life transition is executed (C) in the event of an empty value. Otherwise, the initialization or the execution of the command (COM) is continued (D). Upon detection (E) of an intrusive attack, the end-of-life state variable (FdVR) is written (F) in the single random-access memory, and the end-of-life state variable (FdVE) is deleted (G) from the non-volatile memory in a delayed manner. The invention is suitable for all electronic devices, microprocessor cards or the like. | 01-09-2014 |
20140013043 | MEMORY SYSTEM - A memory system according to an embodiment of the present invention comprises: speed of processing for searching through management tables is increased by providing a forward lookup table for searching for, respectively in track and cluster units, from a logical address, a storage device position where data corresponding to the logical address and a reverse lookup table for searching for, from a position of the storage device, a logical address stored in the position and linking these tables. | 01-09-2014 |
20140019669 | METHOD FOR STATIC WEAR LEVELING IN NON-VIOLATE STORAGE DEVICE - A method for static wear leveling in non-violate storage device is disclosed. Use the method to balance all blocks' erasure counts to avoid most blocks having smaller erasure count and several blocks having larger erasure count to shorten the life time of the device. | 01-16-2014 |
20140019670 | DATA WRITING METHOD, MEMORY CONTROLLER, AND MEMORY STORAGE DEVICE - A data writing method for controlling a rewritable non-volatile memory module having physical erasing units is provided. The physical erasing units are grouped into a first buffer area and a second buffer area. A write command instructed to write a data to a first logical address is received. Whether the quantity of the data is smaller than a predetermined value is determined. If so, the data is written into the first buffer area or the second buffer area. If the data is written into the second buffer area, at least one second logical address mapped to at least one physical programing unit in the first buffer area is obtained, and valid data belonging to the second logical address is merged, wherein the number of the second logical address is smaller than a merging threshold. Thereby, the time for a host system to wait for a write success message is shortened. | 01-16-2014 |
20140019671 | Flash Memory Controllers and Error Detection Methods - A flash memory controller includes a read/write unit, a state machine, a processing unit, and an auxiliary unit. The read/write unit is connected to a flash memory and performs a writing command or a reading command. The state machine is configured to determine a state of the flash memory controller. The processing unit is connected to the read/write unit and the state machine and configured to control the read/write unit. The auxiliary unit is connected to a first data line and a second data line and the processing unit and configured to receive and store a string output from the processing unit. The auxiliary unit outputs the string through the first and second data lines when the flash memory controller completes a writing data transmission. | 01-16-2014 |
20140019672 | MEMORY SYSTEM AND CONTROL METHOD THEREOF - A memory system has a storage unit having two or more parallel read/write processing elements and non-volatile data recording areas for a logical block divided into a plurality of logical pages, and a control unit that generates log information for each unit of data written into the recording areas, determines for each logical page a log information recording area from a group of recording areas of the logical page, and controls the parallel operation elements to write the log information generated for a logical page into the log information recording area of the logical page and the data of the logical page into the other recording areas of the group of recording areas of the logical page. | 01-16-2014 |
20140019673 | DYNAMICALLY ALLOCATING NUMBER OF BITS PER CELL FOR MEMORY LOCATIONS OF A NON-VOLATILE MEMORY - Systems and methods are provided for dynamically allocating a number of bits per cell to memory locations of a non-volatile memory (“NVM”) device. In some embodiments, a host may determine whether to store data in the NVM device using SLC programming or MLC programming operations. The host may allocate an erased block as an SLC block or MLC block based on this determination regardless of whether the erased block was previously used as an SLC block, MLC block, or both. In some embodiments, to dynamically allocate a memory location as SLC or MLC, the host may provide an address vector to the NVM package, where the address vector may specify the memory location and the number of bits per cell to use for that memory location. | 01-16-2014 |
20140019674 | MEMORY SYSTEM INCLUDING NONVOLATILE AND VOLATILE MEMORY AND OPERATING METHOD THEREOF - A memory system having multiple memory layers includes a first memory layer comprising a volatile memory, a second memory layer comprising a first sub-memory and a second sub-memory. In response to a reference failure that occurred in the first memory layer, to which a read reference failed data and a write reference failed data are respectively loaded from a lower level memory layer. | 01-16-2014 |
20140019675 | NONVOLATLE MEMORY DEVICE AND MEMORY SYSTEM HAVING THE SAME, AND RELATED MEMORY MANAGEMENT, ERASE AND PROGRAMMING METHODS - An erase method of a nonvolatile memory device includes setting an erase mode, and performing one of a normal erase operation and a quick erase operation according to the set erase mode. The normal erase operation is performed to set a threshold voltage of a memory cell to an erase state which is lower than a first erase verification level. The quick erase operation is performed to set a threshold voltage of a memory cell to a pseudo erase state which is lower than a second erase verification level. The second erase verification level is higher than the first erase verification level. | 01-16-2014 |
20140019676 | REPURPOSING NAND READY/BUSY PIN AS COMPLETION INTERRUPT - A system and method of controlling a flash memory device such as a NAND memory device may involve receiving a command to execute an operation. A Ready/Busy contact of the memory device may be pulsed low in response to determining that execution of the operation has completed. | 01-16-2014 |
20140025863 | DATA STORAGE DEVICE, MEMORY CONTROL METHOD, AND ELECTRONIC DEVICE WITH DATA STORAGE DEVICE - According to one embodiment, a data storage device includes a first controller, a second controller, and a third controller. The first controller performs a control operation of writing data of a first data unit to a storage area in a flash memory and reading the data of the first data unit from the storage area. The second controller carries out migration processing of measuring a data amount of valid data stored in storage areas of a second data unit that is a data erase processing unit. | 01-23-2014 |
20140025864 | DATA STORAGE DEVICE AND OPERATING METHOD THEREOF - A data storage device with a FLASH memory and an operating method for the data storage device are disclosed. According to the disclosure, the space of the FLASH memory is allocated to include groups of data blocks, a plurality of shared cache blocks (SCBs) and a plurality of dedicated cache blocks (DCBs). Each SCB is shared by one group of data blocks, for the write data storage when any data block of the group of data blocks is exhausted. The DCBs are allocated for the hot data storage. Each DCB corresponds to one hot logical block. | 01-23-2014 |
20140025865 | SEMICONDUCTOR MEMORY DEVICE - According to an embodiment, a semiconductor memory device includes a controller and a second storage unit. The controller is configured to control a write process of writing data into a first storage unit in which data supplied from a host device are stored or a read process of reading the data stored in the first storage in response to a request from the host device. The second storage unit is temporarily used in the write process or the read process. The second storage unit includes a nonvolatile third storage unit having an area for storing a duplicate of the data to be written by the write process; and a nonvolatile fourth storage unit having a work area for the write process or the read process and having a higher read/write speed than the third storage unit. | 01-23-2014 |
20140025866 | NONVOLATILE MEMORY DEVICE AND OPERATING METHOD - A method of programming data in a nonvolatile memory via a first memory cell group and a second memory cell group in a page of memory cells includes; executing a first program operation that programs the first memory cell group with a first program voltage that is stepwise adjusted by a first increment over successive programming loop iterations, and thereafter executing a second program operation that programs the second memory cell with a second program voltage that is stepwise adjusted by a second increment over successive programming loop iterations, wherein the first program voltage is different from the second program voltage. | 01-23-2014 |
20140025867 | CONTROL APPARATUS AND METHOD FOR CONTROLLING A MEMORY HAVING A PLURALITY OF BANKS - A control apparatus which controls a memory having a plurality of banks, allocates the plurality of banks to a first region and a second region, wherein data transfer is performed by interleaving access in a plurality of banks in the first region, and data transfer is performed by non-interleaving access in at least one bank in the second region. The control apparatus sets a bank in the first region and a bank in the second region independently to a low-power state. | 01-23-2014 |
20140025868 | SYSTEM AND METHOD FOR MANAGING STORAGE DEVICE CACHING - Systems and methods are disclosed for caching data according to user-selected caching modes. In an embodiment, an apparatus may comprise a controller configured to pin data from a non-volatile storage medium to a data cache based on at least one user-selectable caching mode. In another embodiment, a device may comprise a processor configured to display a graphical user interface (GUI) at a display, and receive, from the GUI, an indication of a user selection of a data caching mode that determines which data to pin from a non-volatile memory of a data storage device to a data cache of the data storage device. The processor may be configured to then send an indication of the user selection of the data caching mode to the data storage device. | 01-23-2014 |
20140025869 | METHOD AND SYSTEM FOR IMPROVING A CONTROL OF A LIMIT ON WRITING CYCLES OF AN IC CARD - The present invention relates to a method and system for controlling a number of writing cycles supported by a cell or portion ( | 01-23-2014 |
20140025870 | COMPUTER REPROGRAMMING METHOD, DATA STORAGE MEDIUM AND MOTOR VEHICLE COMPUTER | 01-23-2014 |
20140025871 | PROCESSOR SYSTEM AND CONTROL METHOD THEREOF - A processor system according to the present invention includes a storage unit, a control information area that stores an access prohibit flag capable of switching from an allow side to a prohibit side, a main PEa that issues an access request to the storage unit and a request for rewriting a copy register, a security PE that evaluates whether or not the request for rewriting the copy register is valid, the copy register that stores, when the access prohibit flag is set to the allow side, a value corresponding to the allowance and, when the access prohibit flag is set to the prohibit side, a value corresponding to an evaluation result by the security PE, and an access control circuit that controls whether or not to allow access from the main PEa to the storage unit based on an output value from the copy register. | 01-23-2014 |
20140025872 | SYSTEMS AND METHODS FOR CONTEXTUAL STORAGE - A storage layer presents logical address space of a non-volatile storage device. The storage layer maintains logical interfaces to the non-volatile storage device, which may include arbitrary, any-to-any mappings between logical identifiers and storage resources. Data may be stored on the non-volatile storage device in a contextual format, which includes persistent metadata that defines the logical interface of the data. The storage layer may modify the logical interface of data that is stored in the contextual format. The modified logical interface may be inconsistent with the existing contextual format of the data on the non-volatile storage media. The storage layer may provide access to the data in the inconsistent contextual format through the modified logical interface. The contextual format of the data may be updated to be consistent with the modified logical interface in a write out-of-place storage operation. | 01-23-2014 |
20140025873 | SOLID-STATE DRIVE COMMAND GROUPING - An apparatus and other embodiments associated with solid-state drive command grouping are described. In one embodiment, an apparatus includes a hardware memory configured to store a plurality of commands that are to be executed on a solid-state drive. The apparatus also includes organization logic implemented with at least hardware and configured to arrange at least two commands of the plurality of commands into a command pack based, at least in part, on one or more attributes of the at least two commands. | 01-23-2014 |
20140025874 | NONVOLATILE MEMORY SYSTEM AND RELATED METHOD OF PRESERVING STORED DATA DURING POWER INTERRUPTION - A nonvolatile memory system comprises a temporary power supply that supplies power in the event of an unexpected power interruption. The temporary power supply provides power while metadata stored in one or more buffers is compressed and transferred to a nonvolatile memory device. | 01-23-2014 |
20140025875 | Method for Controlling Cache Mapping and Cache System - The present invention relates to a method for controlling cache mapping and a cache system. The method includes: changing, at a preset time interval, a target data block in a cache of an underlying storage medium, where at least one data block in the underlying storage medium is mapped to the target data block, one or more data blocks in the underlying storage medium are mapped only to one target data block in the cache, the cache of the underlying storage medium includes a flash memory medium, and the changed target data block in the cache includes the target data block currently having the maximum number of erasure times in the cache. By utilizing the technical solution, the service life of the flash memory medium can be optimized. | 01-23-2014 |
20140025876 | APPARATUS INCLUDING MEMORY CHANNEL CONTROL CIRCUIT AND RELATED METHODS FOR RELAYING COMMANDS TO LOGICAL UNITS - Memory system controllers can include a switch and non-volatile memory control circuitry coupled to the switch. The non-volatile memory control circuitry can include a channel control circuit coupled to logical units. The channel control circuitry can be configured to relay an erase command to a first one of the logical units and relay a particular command from the switch to a second one of the logical units while the erase command is being executed on the first one of the plurality of logical units. | 01-23-2014 |
20140025877 | AUTO-COMMIT MEMORY METADATA - Apparatuses, systems, methods, and computer program products are disclosed. A method includes tracking which portions of data stored in a volatile memory buffer are not yet stored in a non-volatile memory medium. A volatile memory buffer may be accessible using memory semantics. A volatile memory buffer may be associated with logic configured to ensure that the data stored in the volatile memory buffer is non-volatile. A method includes maintaining consistency of data between a volatile memory buffer and a non-volatile memory medium based on tracked portions of the data. A method includes copying at least portions of data not yet stored in a non-volatile memory medium to the non-volatile memory medium in response to a trigger. | 01-23-2014 |
20140032813 | METHOD OF ACCESSING A NON-VOLATILE MEMORY - A method of accessing a non-volatile memory is disclosed. Original bits of data are duplicated on a bit level to generate a plurality of duplicated bits corresponding to each original bit. At least one shielding bit is provided between the duplicated bits corresponding to different original bits. The duplicated bits and the at least one shielding bit are programmed to the non-volatile memory. The original bits are generated or determined according to the duplicated bits. | 01-30-2014 |
20140032814 | HYBRID STORAGE DEVICE HAVING DISK CONTROLLER WITH HIGH-SPEED SERIAL PORT TO NON-VOLATILE MEMORY BRIDGE - A hybrid storage device comprises at least one storage disk, a disk controller configured to control writing of data to and reading of data from the storage disk, a non-volatile electronic memory, and a bridge device coupled between the disk controller and the non-volatile electronic memory. The disk controller comprises a plurality of high-speed serial interfaces. In one embodiment, the high-speed serial interfaces include a first high-speed serial interface configured to interface the disk controller to a host device, and a second high-speed serial interface configured to interface the disk controller to the non-volatile memory via the bridge device. The non-volatile memory may comprise a flash memory, and the bridge device may comprise a flash controller. The disk controller may be implemented in the form of an SOC integrated circuit that is operative in a plurality of modes including a hybrid mode of operation and an enterprise mode of operation. | 01-30-2014 |
20140032815 | METHODS AND APPARATUSES FOR CALIBRATING DATA SAMPLING POINTS - Methods and apparatuses for calibrating data sampling points are disclosed herein. An example apparatus may include a memory that may be configured to receive a calibration command and an attribute. The memory may include a first register that is configured to store a tuning data pattern and a second register that is configured to receive and store the tuning data pattern stored in the first register. The second register may be further configured to store the tuning data pattern responsive, at least in part, to the memory receiving the calibration command. The memory may be configured to execute an operation on at least one of the tuning data pattern stored in the first register or the tuning data pattern stored in the second register based, at least in part, on the attribute. | 01-30-2014 |
20140032816 | SERIAL INTERFACE FLASH MEMORY APPARATUS AND WRITING METHOD FOR STATUS REGISTER THEREOF - A serial interface flash memory apparatus and a writing method for a status register thereof are disclosed. The writing method for the status register mentioned above includes: receiving a write command with an updated data for the status register; writing the updated data to a volatile latch and set an update flag according to whether or not a write-protected data in the status register is updated by the write command; and writing the data from the volatile latch to the status register according to the update flag when a power down process of the serial interface flash memory apparatus is processed. | 01-30-2014 |
20140032817 | VALID PAGE THRESHOLD BASED GARBAGE COLLECTION FOR SOLID STATE DRIVE - A method for garbage collection in a solid state drive (SSD) includes determining whether the SSD is idle by a garbage collection module of the SSD; based on determining that the SSD is idle, determining a victim block from a plurality of memory blocks of the SSD; determining a number of valid pages in the victim block; comparing the determined number of valid pages in the victim block to a valid page threshold; and based on the number of valid pages in the victim block being less than the valid page threshold, issuing a garbage collection request for the victim block. | 01-30-2014 |
20140032818 | PROVIDING A HYBRID MEMORY - A hybrid memory has a volatile memory and a non-volatile memory. The volatile memory is dynamically configurable to have a first portion that is part of a memory partition, and a second portion that provides a cache for the non-volatile memory. | 01-30-2014 |
20140032819 | COLLECTING INSTALLATION AND FIELD PERFORMANCE DATA FOR MEMORY DEVICES - An approach to determine a power-on-hour offset for a memory device that is newly-installed into a computer system is provided, which subtracts a current power-on-hour count of the memory device from a current power-on-hour value of a power supply that supplies operative power to the memory device within the computer system. In response to the computer system powering down, an accumulated power-on-hour for the memory device is determined by subtracting the power-on-hour offset of the memory from a current power-on-hour value of the computer system power supply. The determined power-on-hour offset and accumulated power-on-hour values are saved into one or more designated bytes of a free area of electrically erasable programmable read-only memory of the memory device that are available for data storage by a memory controller, and wherein data stored therein persists after operative power is lost to the memory device, the memory controller or the computer system. | 01-30-2014 |
20140032820 | DATA STORAGE APPARATUS, MEMORY CONTROL METHOD AND ELECTRONIC DEVICE WITH DATA STORAGE APPARATUS - According to one embodiment, a data storage apparatus comprises a first controller, a second controller, and a third controller. The first controller controls first write processing of writing data to a flash memory in accordance with a request from a host. The second controller controls second write processing of writing data to the flash memory, the second write processing is different from the first write processing. | 01-30-2014 |
20140032821 | NONVOLATILE MEMORY DEVICE AND METHOD OF OPERATING THE SAME - Provided are a nonvolatile memory device and a method for operating the nonvolatile memory device. The method for operating the nonvolatile memory device includes generating a first program voltage, applying the generated first program voltage to a first word line to which a first memory cell is connected for performing a first program operation on the first memory cell, determining whether a number of pulses of a pumping clock signal for generating the first program voltage is greater than or equal to a predetermined critical value n (where n is a natural number), and stopping the performing of the first program operation on the first memory cell when the number of pulses of the pumping clock signal is determined to be greater than or equal to the predetermined critical value n. | 01-30-2014 |
20140032822 | WRITING DATA TO SOLID STATE DRIVES - Technologies and implementations for writing data to a solid state drive are generally disclosed. | 01-30-2014 |
20140032823 | MEMORY BLOCK IDENTIFIED BY GROUP OF LOGICAL BLOCK ADDRESSES, STORAGE DEVICE WITH MOVABLE SECTORS, AND METHODS - In an embodiment, only one sector of a plurality of sectors in a physical block of a plurality of physical blocks has a sector status location configured to store information that indicates a move status of an other sector of the plurality sectors of the physical block of the plurality of physical blocks, where the only one sector of the plurality of sectors in the physical block of the plurality of physical blocks is configured to store a sector of data in addition to the information that indicates the move status. | 01-30-2014 |
20140032824 | Memory Controller, Memory System Including the Same, and Method for Operating the Same - A memory controller includes a first interface unit, a processor, a randomization unit, a state conversion unit, and a second interface unit. The first interface unit exchanges data with an external device, and the processor determines whether to randomize or state-convert the received data. The randomization unit randomizes data received through the first interface unit in response to the processor and generates randomization information in response to the randomization operation. The state conversion unit state-converts data received through the first interface unit in response to the processor and generates conversion information in response to the state conversion operation. The second interface unit receives the randomized data and the randomization information from the randomization unit, receives the state-converted data and the conversion information from the state conversion unit, and exchanges at least one of the randomized data, the randomization information, the state-converted data and the conversion information with a memory. | 01-30-2014 |
20140032825 | DEVICES AND METHODS FOR OPERATING A SOLID STATE DRIVE - The present disclosure includes methods and devices for operating a solid state drive. One method embodiment includes receiving an indication of a desired number of write input/output operations (IOPs) per unit time performed by the solid state drive. The method can also include managing the number of write IOPs performed by the solid state drive at least partially based on the desired number of write IOPs per unit time, a number of spare blocks in the solid state drive, and a desired operational life for the solid state drive. | 01-30-2014 |
20140040530 | MIXED GRANULARITY HIGHER-LEVEL REDUNDANCY FOR NON-VOLATILE MEMORY - Mixed-granularity higher-level redundancy for NVM provides improved higher-level redundancy operation with better error recovery and/or reduced redundancy information overhead. For example, pages of the NVM that are less reliable, such as relatively more prone to errors, are operated in higher-level redundancy modes having relatively more error protection, at a cost of relatively more redundancy information. Concurrently, blocks of the NVM that are more reliable are operated in higher-level redundancy modes having relatively less error protection, at a cost of relatively less redundancy information. Compared to techniques that operate the entirety of the NVM in the higher-level redundancy modes having relatively less error protection, techniques described herein provide better error recovery. Compared to techniques that operate the entirety of the NVM in the higher-level redundancy modes having relatively more error protection, the techniques described herein provide reduced redundancy information overhead. | 02-06-2014 |
20140040531 | SINGLE-READ BASED SOFT-DECISION DECODING OF NON-VOLATILE MEMORY - A Solid-State Disk (SSD) controller performs soft-decision decoding with a single read, thus improving performance, power, and/or reliability of a storage sub-system, such as an SSD. In a first aspect, the controller generates soft-decision metrics from channel parameters of a hard decode read, without additional reads and/or array accesses. In a second aspect, the controller performs soft decoding using the generated soft-decision metrics. In a third aspect, the controller generates soft-decision metrics and performs soft decoding with the generated soft-decision metrics when a hard decode read error occurs. | 02-06-2014 |
20140040532 | STACKED MEMORY DEVICE WITH HELPER PROCESSOR - A processing system comprises one or more processor devices and other system components coupled to a stacked memory device having a set of stacked memory layers and a set of one or more logic layers. The set of logic layers implements a helper processor that executes instructions to perform tasks in response to a task request from the processor devices or otherwise on behalf of the other processor devices. The set of logic layers also includes a memory interface coupled to memory cell circuitry implemented in the set of stacked memory layers and coupleable to the processor devices. The memory interface operates to perform memory accesses for the processor devices and for the helper processor. By virtue of the helper processor's tight integration with the stacked memory layers, the helper processor may perform certain memory-intensive operations more efficiently than could be performed by the external processor devices. | 02-06-2014 |
20140040533 | DATA MANAGEMENT METHOD, MEMORY CONTROLLER AND MEMORY STORAGE DEVICE - A data management method for a rewritable non-volatile memory module including a first memory unit and a second memory unit is provided. The method includes: grouping erasing units of the first memory unit into a data area and a spare area; and grouping the physical erasing units of the second memory unit into a data backup area and a command recording area; configuring multiple logical addresses to map to the physical erasing units associated with the data area; receiving a write command which instructs writing data; writing the data to a physical erasing unit associated with the spare area, and writing the data to a physical erasing unit associated with the data backup area; recording at least a portion of the write command in a physical erasing unit associated with the command recording area. Accordingly, data is backuped in the rewritable non-volatile memory module. | 02-06-2014 |
20140040534 | DATA STORING METHOD AND MEMORY CONTROLLER AND MEMORY STORAGE DEVICE USING THE SAME - A data storing method for a rewritable non-volatile memory module and a memory controller and a memory storage device using the same are provided. The data storing method includes moving or writing data into a physical erase unit of the rewritable non-volatile memory module and determining whether the physical erase unit contains a dancing bit. The data storing method further includes when the physical erase unit contains the dancing bit, restoring the rewritable non-volatile memory module to the state before the data is moved or moving the data from the physical erase unit to another physical erase unit. Thereby, the data storing method can effectively ensure the reliability of the data. | 02-06-2014 |
20140040535 | NONVOLATILE MEMORY DEVICE HAVING WEAR-LEVELING CONTROL AND METHOD OF OPERATING THE SAME - A method is provided for controlling a write operation in a nonvolatile memory device to provide wear leveling, where the nonvolatile memory device includes multiple memory blocks. The method includes reading write indication information with respect to at least a selected memory block of the multiple memory blocks; determining whether a write order of data to be stored in the selected memory block is an ascending order or a descending order, based on the write indication information of the selected memory block; and generating addresses of memory regions in the selected memory block in an ascending order when the write order of the data is determined to be an ascending order, and generating addresses of the memory regions in the selected memory block in a descending order when the write order is determined to be a descending order. | 02-06-2014 |
20140040536 | STORAGE MEDIUM USING NONVOLATILE SEMICONDUCTOR STORAGE DEVICE, DATA TERMINAL HAVING THE STORAGE MEDIUM MOUNTED THEREON, AND FILE ERASING METHOD USABLE FOR THE SAME - A storage medium using a nonvolatile semiconductor storage device for erasing data with certainty on a file-by-file basis and preventing an inadvertent file leak as much as possible is provided. A file erasing method includes (a) reading data other than data in a file which is a target of erase from an erase block having the file as the target of erase recorded therein; (b) writing the read data other than the data in the file which is the target of erase to another erase block; and (c) erasing all the data in the erase block in which the file as the target of erase is recorded. | 02-06-2014 |
20140040537 | STORAGE MEDIUM USING NONVOLATILE SEMICONDUCTOR STORAGE DEVICE, AND DATA TERMINAL INCLUDING THE SAME - A storage medium using a nonvolatile semiconductor storage device for preventing an inadvertent file leak as much as possible is provided. A storage medium using a nonvolatile semiconductor storage device includes a control unit for writing data to memory cells which store data corresponding to files stored on the storage medium, such that all the memory cells are put into the same electronic state, or for erasing data from the memory cells, after a lapse of a set time period. | 02-06-2014 |
20140040538 | METHOD OF WRITING DATA, MEMORY, AND SYSTEM FOR WRITING DATA IN MEMORY - A method of writing data in a memory comprising a NAND cell array is disclosed, wherein a data output device completes the writing process only by transmitting the data and a start address for writing the data to the memory. | 02-06-2014 |
20140040539 | METHOD FOR WEAR LEVELING IN A NONVOLATILE MEMORY - A method for writing and reading data memory cells, comprising: defining in a first memory zone erasable data pages and programmable data blocks; and, in response to write commands of data, writing data in erased blocks of the first memory zone, and writing, in a second memory zone, metadata structures associated with data pages and comprising, for each data page, a wear counter containing a value representative of the number of times that the page has been erased. | 02-06-2014 |
20140040540 | Metadata Management For Virtual Volumes - Methods, apparatus, and systems, including computer programs encoded on a computer storage medium, manage metadata for virtual volumes. In some implementations, a method includes: loading into memory at least a portion of metadata for a virtual volume (VV) that spans data extents of different persistent storage devices, wherein the metadata comprises virtual metadata block (VMB) descriptors and virtual metadata blocks (VMBs); mapping an address of the VV to a VMB number and an index of an extent pointer within a VMB identified by the VMB number, wherein the extent pointer indicates an extent within one of the different persistent storage devices; locating a VMB descriptor in the memory based on the VMB number; and locating the identified VMB in the memory or not in the memory based on the located VMB descriptor. | 02-06-2014 |
20140047159 | ENTERPRISE SERVER WITH FLASH STORAGE MODULES - A server system, such as an enterprise server, may include an array of memory devices. The memory devices may include non-volatile or flash memory and be referred to as flash storage modules (“FSM”). The server system includes a host computer or host server that communicates with the array of FSM. The host may include a media management layer or flash transformation layer that is implemented by drivers on the host for controlling the FSM. | 02-13-2014 |
20140047160 | DATA WRITING METHOD, AND MEMORY CONTROLLER AND MEMORY STORAGE APPARATUS USING THE SAME - A data writing method for writing data into a memory cell of a rewritable non-volatile memory module, and a memory controller and a memory storage apparatus using the same area provided. The method includes recording a wear degree of the memory cell and adjusting an initial write voltage and a write voltage pulse time corresponding to the memory cell based on the wear degree thereof. The method further includes programming the memory cell by applying the initial write voltage and the write voltage pulse time, thereby writing the data into the memory cell. Accordingly, data can be accurately stored into the rewritable non-volatile memory module by the method. | 02-13-2014 |
20140047161 | System Employing MRAM and Physically Addressed Solid State Disk - A computer system includes a Central Processing Unit (CPU) that has a physically-addressed solid state disk (SSD), addressable using physical addresses associated with user data and provided by a host. The user data is to be stored in or retrieved from the physically-addressed SSD in blocks. Further, a non-volatile memory module is coupled to the CPU and includes flash tables used to manage blocks in the physically addressed SSD. The flash tables have tables that are used to map logical to physical blocks for identifying the location of stored data in the physically addressed SSD. The flash tables are maintained in the non-volatile memory modules thereby avoiding reconstruction of the flash tables upon power interruption. | 02-13-2014 |
20140047162 | MEMORY SYSTEM CAPABLE OF PREVENTING DATA DESTRUCTION - According to one embodiment, a memory system includes a memory unit, a first controller, and a second controller. In the memory unit, first to fourth levels (first level02-13-2014 | |
20140047163 | NONVOLATILE MEMORY DEVICE AND PROGRAMMING METHOD - A non-volatile memory (NVM) includes a memory cell array of multi-level memory cells (MLC) arranged in physical pages. A programming method for the NVM includes; receiving first data and partitioning the first data according to a single bit page capacity of a physical page to generate partitioned first data, programming the partitioned first data as single-bit data to a plurality of physical pages, and receiving second data and programming the second data as multi-bit data to a selected physical page among the plurality of physical pages, wherein the second data is simultaneously programmed to the MLC of the selected physical page. | 02-13-2014 |
20140047164 | Physically Addressed Solid State Disk Employing Magnetic Random Access Memory (MRAM) - A computer system includes a central processing unit (CPU), a system memory coupled to the CPU and including flash tables, and a physically-addressable solid state disk (SSD) coupled to the CPU. The physically-addressable SSD includes a flash subsystem and a non-volatile memory and is addressable using physical addresses. The flash subsystem includes one or more copies of the flash tables and the non-volatile memory includes updates to the copy of the flash tables. The flash tables include tables used to map logical to physical blocks for identifying the location of stored data in the physically addressable SSD, wherein the updates to the copy of the flash tables and the one or more copies of the flash tables are used to reconstruct the flash tables upon power interruption. | 02-13-2014 |
20140047165 | Storage System Employing MRAM and Physically Addressed Solid State Disk - A storage system includes a Central Processing Unit (CPU) that has a physically-addressed solid state disk (SSD), addressable using physical addresses associated with user data and provided by a host. The user data is to be stored in or retrieved from the physically-addressed SSD in blocks. Further, a non-volatile memory module is coupled to the CPU and includes flash tables used to manage blocks in the physically addressed SSD. The flash tables have tables that are used to map logical to physical blocks for identifying the location of stored data in the physically addressed SSD. The flash tables are maintained in the non-volatile memory modules thereby avoiding reconstruction of the flash tables upon power interruption. | 02-13-2014 |
20140047166 | STORAGE SYSTEM EMPLOYING MRAM AND ARRAY OF SOLID STATE DISKS WITH INTEGRATED SWITCH - A storage system includes a central processing unit (CPU) subsystem including a CPU, a physically-addressed solid state disk (SSD) that is addressable using physical addresses associated with user data, provided by the CPU, to be stored in or retrieved from the physically-addressed SSD in blocks. Further, the storage system includes a non-volatile memory module, the non-volatile memory module having flash tables used to manage blocks in the physically addressed SSD, the flash tables include tables used to map logical to physical blocks for identifying the location of stored data in the physically addressed SSD. Additionally, the storage system includes a peripheral component interconnect express (PCIe) switch coupled to the CPU subsystem and a network interface controller coupled through a PCIe bus to the PCIe switch, wherein the flash tables are maintained in the non-volatile memory modules thereby avoiding reconstruction of the flash tables upon power interruption. | 02-13-2014 |
20140047167 | NONVOLATILE MEMORY DEVICE AND METHOD OF CONTROLLING SUSPENSION OF COMMAND EXECUTION OF THE SAME - A nonvolatile memory device includes a memory cell array, a row decoder, a page buffer, and control logic. The memory cell array includes memory cells connected to word lines and bit lines, the memory cell array being configured to store data. The row decoder is configured to selectively activate a string selection line, a ground selection line, and the word lines of the memory cell array. The page buffer is configured to temporarily store external data and to apply a predetermined voltage to the bit lines according to the stored data during a program operation, and to sense data stored in selected memory cells using the bit lines during a read operation or a verification operation. The control logic is configured to control the row decoder and the page buffer. During execution of commands, when a request to suspend the execution of the commands is retrieved, chip information is backed up to a storage space separate from the control logic. | 02-13-2014 |
20140047168 | DATA STORAGE SYSTEM AND METHOD OF OPERATING DATA STORAGE SYSTEM - A method of operating a data storage device includes providing a memory cell array that includes a first word line, a second word line and a buffer configured to store second data to be programmed into the second word line, reading the second data from the buffer, and programming first data into the first word line. A programming condition of the first data being is changed based on the second data read from the buffer. | 02-13-2014 |
20140047169 | METHOD FOR OPERATING A MEMORY CONTROLLER AND A SYSTEM HAVING THE MEMORY CONTROLLER - A method for operating a memory controller includes determining a number of free blocks to be created during an idle time by using a block consumption history, and controlling a non-volatile memory device to perform a garbage collection operation during the idle time to create the determined number of free blocks. | 02-13-2014 |
20140047170 | MAINTAINING ORDERING VIA A MULTI-LEVEL MAP OF A SOLID-STATE MEDIA - Described embodiments provide a media controller that processes requests including a logical address and address range. A map of the media controller determines physical addresses of a media associated with the logical address and address range of the request. The map is a multi-level map having a plurality of leaf-level map pages that are stored in the media, with a subset of the leaf-level map pages stored in a map cache. Based on the logical address and address range, it is determined whether a corresponding leaf-level map page is stored in the map cache. If the leaf-level map page is stored in the map cache, a cache index and control indicators of the map cache entry are returned in order to enforce ordering rules that selectively enable access to a corresponding leaf-level map page based on the control indicators and a determined request type. | 02-13-2014 |
20140047171 | SYSTEM AND METHOD OF CACHING INFORMATION - A system and method is provided wherein, in one aspect, a currently-requested item of information is stored in a cache based on whether it has been previously requested and, if so, the time of the previous request. If the item has not been previously requested, it may not be stored in the cache. If the subject item has been previously requested, it may or may not be cached based on a comparison of durations, namely (1) the duration of time between the current request and the previous request for the subject item and (2) for each other item in the cache, the duration of time between the current request and the previous request for the other item. If the duration associated with the subject item is less than the duration of another item in the cache, the subject item may be stored in the cache. | 02-13-2014 |
20140047172 | DATA STORAGE DEVICE - A data storage device may include a first memory board having multiple memory chips and a controller board that is arranged and configured to operably connect to the first memory board. The controller board may include an interface to a host and a controller that is arranged and configured to control command processing for multiple different types of memory chips, automatically recognize a type of the memory chips on the first memory board, receive commands from the host using the interface, and execute the commands using the memory chips. | 02-13-2014 |
20140052892 | METHODS AND APPARATUS FOR PROVIDING ACCELERATION OF VIRTUAL MACHINES IN VIRTUAL ENVIRONMENTS - A host server computer system that includes a hypervisor within a virtual space architecture running at least one virtualization, acceleration and management server and at least one virtual machine, at least one virtual disk that is read from and written to by the virtual machine, a cache agent residing in the virtual machine, wherein the cache agent intercepts read or write commands made by the virtual machine to the virtual disk, and a solid state drive. The solid state drive includes a non-volatile memory storage device, a cache device and a memory device driver providing a cache primitives application programming interface to the cache agent and a control interface to the virtualization, acceleration and management server. | 02-20-2014 |
20140052893 | FILE DELETION FOR NON-VOLATILE MEMORY - A device includes non-volatile memory and a controller. The controller receives a write request including data and a logical address associated with a file. The controller stores the data at a data storage segment having a physical address and associates the physical address with the logical address and a file identifier for the file. The controller receives a second write request including data and the logical address associated with the file. The controller stores the data at a second data storage segment having a second physical address and associates the second physical address with the logical address and the file identifier. When a file delete request for the file is received, the controller identifies the first physical address and the second physical address using the file identifier and erases the information stored at the first data storage segment and the second data storage segment based upon the file identification. | 02-20-2014 |
20140052894 | MEMORY CONTROLLER FOR MEMORY WITH MIXED CELL ARRAY AND METHOD OF CONTROLLING THE MEMORY - A memory controller, system including the memory controller and method of controlling the memory. The memory controller receives requests for memory and content sensitively allocates memory space in a mixed cell memory. The memory controller allocates sufficient space including performance memory storing a single bit per cell and dense memory storing more than one bit per cell. Some or all of the memory may be selectable by the memory controller as either Single Level per Cell (SLC) or Multiple Level per Cell (MLC). | 02-20-2014 |
20140052895 | MEMORY WITH MIXED CELL ARRAY AND SYSTEM INCLUDING THE MEMORY - A memory system, system including the memory system and method of reducing memory system power consumption. The memory system includes multiple memory units allocable to one of a number of processor units, e.g., processors or processor cores. A memory controller receives requests for memory from the processor units and allocates sufficient space from the memory to each requesting processor unit. Allocated memory can include some Single Level per Cell (SLC) memory units storing a single bit per cell and other memory units storing more than one bit per cell. Thus, two processor units may be assigned identical memory space, while half, or fewer, than the number of cells of one are assigned to the other. | 02-20-2014 |
20140052896 | SYSTEM AND METHOD FOR EMULATING AN EEPROM IN A NON-VOLATILE MEMORY DEVICE - The invention relates to an electronic memory system, and more specifically, to a system for emulating an electrically erasable programmable read only memory in a non-volatile memory device, and a method of emulating an electrically erasable programmable read only memory in a non-volatile memory device. According to an embodiment, a system for emulating an electrically erasable programmable read only memory is provided, the system including a Flash memory, wherein the Flash memory is configurable into a first region and a second region, wherein the first region is adapted to store a first class of data and the second region is adapted to store a second, different class of data. | 02-20-2014 |
20140052897 | DYNAMIC FORMATION OF GARBAGE COLLECTION UNITS IN A MEMORY - Method and apparatus for managing data in a memory, such as but not limited to a flash memory. In accordance with some embodiments, a memory is provided with a plurality of addressable data storage blocks which are arranged into a first set of garbage collection units (GCUs). The blocks are rearranged into a different, second set of GCUs responsive to parametric performance of the blocks. | 02-20-2014 |
20140052898 | METHOD FOR MAPPING MANAGEMENT - A method for mapping management is disclosed. The steps of the method comprises sending data from a host; programming a host data a non-volatile storage device; updating a mapping address to a Physical Entry to Logical (PE2L) mapping table stored in a SRAM; updating a Physical Entry (PE) status table; checking if the PE2L mapping table is full; if no, loop to the step of programming a non-violate storage device; if yes, remove invalid entries in the PE2L mapping table and update the PE status table, and then run next step; transferring part of the PE2L mapping table to a Logical to Physical (L2P) mapping table stored in the non-volatile storage device; and programming the L2P mapping table to the non-volatile storage device and looping to the step of removing invalid entries in the PE2L mapping table and updating the PE status table. | 02-20-2014 |
20140052899 | MEMORY ADDRESS TRANSLATION METHOD FOR FLASH STORAGE SYSTEM - A memory address translation method for flash storage system is disclosed. There are two level mapping tables to reduce overhead of mapping table management. In level-one mapping table, each entry contains two kinds of information, which one is the validation of this entry, called Valid Mark and the other is the location of level-two mapping. The level-one mapping table is always located on RAM, and never saved into flash memory. In level-two mapping table, each entry contains two kinds of information, which one is the validation of this entry and the other is the physical location of data in flash memory. The physical addresses of both data and level-two mapping table are dynamically determined. Level-two mapping table is loaded to RAM when it is needed to reference, and is saved into flash memory periodically if the content is updated. | 02-20-2014 |
20140052900 | MEMORY CONTROLLER FOR MEMORY WITH MIXED CELL ARRAY AND METHOD OF CONTROLLING THE MEMORY - A memory controller, system including the memory controller and method of controlling the memory. The memory controller receives requests for memory and content sensitively allocates memory space in a mixed cell memory. The memory controller allocates sufficient space including performance memory storing a single bit per cell and dense memory storing more than one bit per cell. Some or all of the memory may be selectable by the memory controller as either Single Level per Cell (SLC) or Multiple Level per Cell (MLC). | 02-20-2014 |
20140052901 | MEMORY WITH MIXED CELL ARRAY AND SYSTEM INCLUDING THE MEMORY - A memory system, system including the memory system and method of reducing memory system power consumption. The memory system includes multiple memory units allocable to one of a number of processor units, e.g., processors or processor cores. A memory controller receives requests for memory from the processor units and allocates sufficient space from the memory to each requesting processor unit. Allocated memory can include some Single Level per Cell (SLC) memory units storing a single bit per cell and other memory units storing more than one bit per cell. Thus, two processor units may be assigned identical memory space, while half, or fewer, than the number of cells of one are assigned to the other. | 02-20-2014 |
20140052902 | ELECTRONIC DEVICE AND METHOD OF GENERATING VIRTUAL UNIVERSAL SERIAL BUS FLASH DEVICE - An electronic device connected to several USB devices. The electronic device divides a memory of each USB device to a plurality of memory blocks. Corresponding memory blocks of each USB device are combined to sectors. All the sectors form a virtual USB flash device. When data need to be written to the USB flash drive, the data is divided to data blocks according to a size of each memory block. The data blocks of the data are stored into the memory blocks of each sector. When the data need to be read from the virtual USB flash device, the data blocks of the data are read from the memory blocks of corresponding sectors. The electronic device combines the data blocks to integrated data. | 02-20-2014 |
20140052903 | MEMORY SYSTEM AND BUS SWITCH - A memory system includes a nonvolatile memory having a plurality of nonvolatile memory chips incorporated therein, a control circuit that controls the nonvolatile memory, an MPU that controls the control circuit, and an interface circuit that communicates with a host, all of which are mounted on a board of the memory system, and the memory system further includes a bus switch that switches connection of a signal line between the control circuit and the nonvolatile memory chips. | 02-20-2014 |
20140052904 | SYSTEMS AND METHODS FOR RECOVERING ADDRESSING DATA - A memory includes first memory configured to store first data indicating relationships between logical addresses and respective physical addresses, wherein the physical addresses are arranged in a plurality of different groups, respective statuses of each of the plurality of different groups, and an activity log indicating when any of the respective statuses has changed. A second memory is configured to store second data in memory locations corresponding to the physical addresses and, in response to a respective status of one of the plurality of groups changing, store a portion of the first data corresponding to the one of the plurality of groups. A recovery module is configured to update, in response to the activity log indicating that the respective status of the one of the plurality of groups has changed, the first data with the portion of the first data corresponding to the one of the plurality of groups. | 02-20-2014 |
20140059270 | EFFICIENT ENFORCEMENT OF COMMAND EXECUTION ORDER IN SOLID STATE DRIVES - A method in a storage device includes receiving from a host storage commands for execution in a non-volatile memory of the storage device. At least a subset of the storage commands are to be executed in accordance with an order-of-arrival in which the storage commands in the subset are received. The received storage commands are executed in the non-volatile memory in accordance with internal scheduling criteria of the storage device, which permit deviations from the order-of-arrival, but such that execution of the storage commands in the subset reflects the order-of-arrival to the host. | 02-27-2014 |
20140059271 | FAST EXECUTION OF FLUSH COMMANDS USING ADAPTIVE COMPACTION RATIO - A method includes receiving one or more storage commands and at least one flush command in a storage device, which includes a non-volatile memory and a volatile buffer for buffering data received for storage in the non-volatile memory. The flush command instructs the storage device to commit the data buffered in the volatile buffer to the non-volatile memory. The storage commands are executed in accordance with a first storage rule. The flush command is executed in accordance with a second storage rule having smaller latency relative to the first storage rule. | 02-27-2014 |
20140059272 | DATA PROCESSING SYSTEM AND METHOD FOR STORAGE - A data processing system includes a first storage, a second storage, a processor and a controller. The first storage is a non-volatile storage, the second storage is a volatile storage. The first storage and the second storage are initialized when the data processing system is started up. The controller detects whether the first storage and the second storage have been initialized, and generates a signal to control the processor to write data from the first storage to the second storage. The controller further detects when the processor generates a request to read data from the first storage, and generates a reading instruction to control the processor to, instead, read the same data from the second storage that was copied from the first storage to the second storage. | 02-27-2014 |
20140059273 | HOST APPARATUS AND MEMORY DEVICE - According to one embodiment, a host apparatus is capable of accessing memory device. The host apparatus includes application software, a dedicated file system, and an interface circuit. The application software issues, to a file system, a request for access to the memory device. The dedicated file system manages a memory area of the memory device in accordance with a method appropriate to a flash memory in response to the access request. The dedicated file system manages logical address spaces by predetermined unit areas, and sequentially writes data into one of reserved unit areas. The application software issues the access request to the dedicated file system without recognizing a size of the unit area. | 02-27-2014 |
20140059274 | FLASH MEMORY CONTROLLER, FLASH MEMORY SYSTEM, AND FLASH MEMORY CONTROL METHOD - A flash memory controller configures, in a polling interval storage part, a polling interval, which is a time interval for outputting an acquisition signal for acquiring from a flash memory, information showing whether or not the execution of programing or erasing has ended after the execution of the programming or erasing has started with respect to the flash memory. The flash memory controller sends either a program command or an erase command to the flash memory, and thereafter, outputs the acquisition signal in accordance with the configured polling interval until information denoting that the execution of either the programming or the erasing has ended is received. | 02-27-2014 |
20140059275 | STORAGE DEVICES INCLUDING NON-VOLATILE MEMORY AND MEMORY CONTROLLER AND METHODS OF ALLOCATING WRITE MEMORY BLOCKS - Storage devices including a flash memory and a memory controller, and write memory block allocating methods of the storage devices are provided. A write memory block allocating method may include storing a pre-allocation table in a Random Access Memory (RAM) of a memory controller. The pre-allocation table may include allocation order information of a pre-allocated memory block included in a flash memory. The method may also include receiving a write request from a host, determining whether a write memory block for the write request can be allocated according to the pre-allocation table and allocating the pre-allocated memory block as the write memory block according to the pre-allocation table when the write memory block can be allocated according to the pre-allocation table. | 02-27-2014 |
20140059276 | HOST DEVICE AND SYSTEM INCLUDING THE SAME - A memory module includes a first storage module including a first module controller and a first memory unit. The first storage module is configured to receive first partial data from a host and write the first partial data to the first memory unit. A second storage module includes a second module controller and a second memory unit. The second storage module is configured to receive second partial data from the host and write the second partial data to the second memory unit. The first storage module and the second storage module are configured to connect to the host through a single host interface bus. | 02-27-2014 |
20140059277 | STORAGE FOR ADAPTIVELY DETERMINING A PROCESSING TECHNIQUE WITH RESPECT TO A HOST REQUEST BASED ON PARTITION DATA AND OPERATING METHOD FOR THE STORAGE DEVICE - Provided are: a storage device for adaptively determining a processing technique with respect to a host request based on partition data; and an operating method for the storage device. The storage device responds to receipt of a read or write request from a host by ascertaining a partition corresponding to the host request based on data about block addresses occupied by various partitions stored in the storage device. Also, the storage device adaptively determines a processing technique with respect to the host request based on predetermined attributes of the partition concerned. | 02-27-2014 |
20140059278 | STORAGE DEVICE FIRMWARE AND MANUFACTURING SOFTWARE - Storage device FirmWare (FW) and manufacturing software techniques include access to FW images and communication of a manufacturing software tool. The manufacturing software tool enables download of the FW images into an I/O device and controlling a manufacturing test of the I/O device that is a storage device providing a storage capability. Execution of the downloaded FW images enables an I/O controller of the I/O device to provide the storage capability via operation with one or more selected types of flash memory devices. The selected types are selected from a plurality of flash memory types that the I/O controller is capable of operating with by executing appropriate ones of the FW images. Optionally the manufacturing test includes testing the storage capability of the I/O device. The techniques further include an SSD manufacturing self-test capability. | 02-27-2014 |
20140059279 | SSD Lifetime Via Exploiting Content Locality - A solid state drive (SSD), which is used in computing systems, implements the systems and methods of a Delta Flash Transition Layer (ΔFTL) to store compressed data in the SSD instead of original new data. The systems and methods of ΔFTL reduce the write count via exploiting the content locality between the write data and its corresponding old version in the flash. Content locality implies the new version resembles the old to some extent, so that the difference (delta) between the versions may be compressed compactly. Instead of storing new data in its original form in the flash, ΔFTL stores the compressed deltas. | 02-27-2014 |
20140059280 | HOST DEVICE AND SYSTEM INCLUDING THE SAME - A memory module includes a first storage module including a first module controller and a first memory unit. The first storage module is configured to receive first partial data from a host and write the first partial data to the first memory unit. A second storage module includes a second module controller and a second memory unit. The second storage module is configured to receive second partial data from the host and write the second partial data to the second memory unit. The first storage module and the second storage module are configured to connect to the host through a single host interface bus. | 02-27-2014 |
20140059281 | MEMORY SYSTEM - According to the embodiments, a memory system includes a nonvolatile semiconductor memory and a writing-loop-count monitoring unit that monitors a loop count of an applied voltage to the nonvolatile semiconductor memory required for data writing of the nonvolatile semiconductor memory as a writing loop count. Moreover, the memory system includes a management table for managing the writing loop count in block unit that is a unit of data erasing and a life managing unit that determines a degraded state of the nonvolatile semiconductor memory based on the management table. | 02-27-2014 |
20140068142 | REDUNDANCY SCHEMES FOR NON-VOLATILE MEMORY BASED ON PHYSICAL MEMORY LAYOUT - A method includes, for a memory die including at least first and second memory planes, each including multiple physical memory blocks, holding a definition of a redundancy mapping between first memory blocks in the first memory plane and respective second memory blocks in the second memory plane, such that a physical separation on the die between each first physical memory block and a corresponding second physical memory block meets a predefined criterion. Data is stored in one or more first physical memory blocks in the first memory plane. Redundancy information is stored relating to the data in one or more second physical memory blocks in the second memory plane that are mapped by the redundancy mapping to the one or more first physical memory blocks. | 03-06-2014 |
20140068143 | APPARATUS FOR MEASURING REMAINING POWER OF BATTERY UNIT AND METHOD THEREOF - An apparatus for measuring a remaining power of a battery unit includes a first memory unit, a second memory unit, and a processor. The first memory unit stores a first program code. The second memory unit stores a second program code. The second memory unit is accessed at a second speed that is lower than a first speed at which the first memory unit is accessed. The processor is utilized for reading the first program code from the first memory unit to execute calculation for current of the battery unit during a normal operation mode and reading the second program code from the second memory unit to execute an exception during the normal operation mode if required. | 03-06-2014 |
20140068144 | HETEROGENEOUS DATA PATHS FOR SYSTEMS HAVING TIERED MEMORIES - A nonvolatile memory (“NVM”) buffer can be incorporated into an NVM system between a volatile memory buffer and an NVM to decrease the size of the volatile memory buffer and organize data for programming to the NVM. Heterogeneous data paths may be used for write and read operations such that the nonvolatile memory buffer is used only in certain situations. | 03-06-2014 |
20140068145 | SRAM HANDSHAKE - Various exemplary embodiments relate to an integrated circuit including: a RF interface; a wired interface connectable to a host; a volatile memory having a first block and a last block configured to store data transferred between the RF interface and the wired interface; and a memory controller configured to detect when the last block of the volatile memory has been written and to indicate that the volatile memory is ready to read. Various exemplary embodiments relate to a method performed by a tag including: determining that data is to be received on the first interface; blocking the second interface; writing data from the first interface to a volatile memory; detecting that the last block of the volatile memory has been written; unblocking the second interface; indicating that data is available for reading; blocking the first interface; and reading data from the volatile memory to the second interface. | 03-06-2014 |
20140068146 | MEMORY SYSTEM - According to one embodiment, a memory system according to one embodiment is equipped with several nonvolatile memory chips and a memory controller that controls the nonvolatile memory chips based on a firmware. The firmware is written in a nonvolatile memory chip positioned the farthest distance from the memory controller. | 03-06-2014 |
20140068147 | Flash Memory Devices and Controlling Methods Therefor - A flash memory controller is provided. The flash memory controller includes a read/write unit, a state machine, a processing unit, and a reserve unit. The read/write unit is coupled to a flash memory. The read/write unit is configured to perform a write command or a read command. The state machine is configured to determine a state of the flash memory controller. The processing unit is coupled to the read/write unit and the state machine. The processing unit is configured to control the read/write unit. The reserve unit is coupled to a first data line, a second data line, and the read/write unit. When the flash memory controller is operating abnormally, the reserve unit receives an external signal via the first data line and the second data line and controls the read/write unit according to the external signal. | 03-06-2014 |
20140068148 | LEVEL PLACEMENT IN SOLID-STATE MEMORY - Methods and apparatus are provided for determining level placement in q-level cells of solid-state memory, where q>2. Groups of the cells are programmed to respective levels of a predetermined plurality of programming levels, and each cell is then read at a series of time instants to obtain a sequence of read metric values for that cell. The sequences of read metric values for the group of cells programmed to each programming level are processed to derive statistical data as a function of time for that level. The statistical data for each programming level is processed to determine for that level at least one parameter of a model defining variation with time of the statistical data for programming levels. The parameters for the levels are extrapolated to define parameter variation as a function of level. A set of q programming levels which has a desired property over time is then calculated from said parameter variation and said model. | 03-06-2014 |
20140068149 | MEMORY SYSTEM - According to one embodiment, a memory system includes a nonvolatile semiconductor storage device, a first storage module, a second storage module, a controller, a random number generator, and a randomizing module. The first storage module stores a plurality of management data. The second storage module stores seed data. The controller issues a first command to designate one of the management data, and issues a second command to command writing in or reading from the storage device. The random number generator generates random number data, by shuffling the seed data, based on the management data that is designated by the first command. The randomizing module randomizes written data or read data, based on the random number data. | 03-06-2014 |
20140068150 | DATA STORAGE DEVICE AND OPERATING METHOD THEREOF - A data storage device includes: a first memory device. a second memory device configured to share a write control signal and a read control signal which are provided to the first memory device. and a controller configured to control the first and second memory devices, wherein the controller provides the write control signal and the read control signal to the first and second memory devices at the same time, the first memory device receives only the read control signal according to a first mask signal, and the second memory device receives only the write control signal according to a second mask signal. | 03-06-2014 |
20140068151 | METHOD OF READING AND INPUTTING DATA FOR TESTING SYSTEM AND TESTING SYSTEM THEREOF - A method of inputting data for a testing system is disclosed. The method includes coupling an information buffer to a device to be tested, transferring the device to be tested to a plurality of test stations in the testing system in turn, and obtaining the plurality of product identifications stored in the information buffer in each of the plurality of test stations. | 03-06-2014 |
20140068152 | METHOD AND SYSTEM FOR STORAGE ADDRESS RE-MAPPING FOR A MULTI-BANK MEMORY DEVICE - A method and system for storage address re-mapping in a multi-bank memory is disclosed. The method includes allocating logical addresses in blocks of clusters and re-mapping logical addresses into storage address space, where short runs of host data dispersed in logical address space are mapped in a contiguous manner into megablocks in storage address space. Independently in each bank, valid data is flushed within each respective bank from blocks having both valid and obsolete data to make new blocks available for receiving data in each bank of the multi-bank memory when an available number of new blocks falls below a desired threshold within a particular bank. | 03-06-2014 |
20140068153 | WEAR MANAGEMENT APPARATUS AND METHOD FOR STORAGE SYSTEM - A wear management apparatus and a wear management method of a storage system including storage nodes are provided. The wear management apparatus includes a monitor unit configured to collect status information about each of the storage nodes. The wear management apparatus further includes a wear management unit configured to establish a wear progress model with respect to the storage nodes based on the status information, and control a wear acceleration index of each of the storage nodes based on the wear progress model and a wear management policy. | 03-06-2014 |
20140068154 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes a first memory circuit and a first controller. The first memory circuit includes a register in which a read page size is stored, and a memory cell array. The first controller is configured to access the first memory circuit by the page size stored in the register, in one of an open page policy and closed page policy. | 03-06-2014 |
20140068155 | INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, AND PROGRAM - Provided is an information processing apparatus, including: a volatile memory; a nonvolatile memory including a rewritable area configured to store rewritable data, and a non-rewritable area configured to store non-rewritable data and a Snapshot Boot image, the Snapshot Boot image showing a home window corresponding to an execution status of the non-rewritable data; and a controller configured to load the rewritable data and the Snapshot Boot image into the volatile memory when booting, and to draw the home window based on difference information and the Snapshot Boot image, the difference information corresponding to difference data of the rewritable data before and after | 03-06-2014 |
20140068156 | DATA PROCESSING APPARATUS, METHOD FOR PROCESSING DATA, AND COMPUTER READABLE RECORDING MEDIUM RECORDED WITH PROGRAM TO PERFORM THE METHOD - A data processing apparatus includes a first storage device which stores compressed data therein, a second storage device which accesses and temporarily stores the compressed data stored in the first storage device, a data decompressor which generates decompressed data by decompressing the compressed data and outputs the decompressed data to the second storage device so that the decompressed data is temporarily stored in the second storage device, and a controller which accesses the decompressed data temporarily stored in the second storage device. The data decompressor directly scatters the decompressed data into a page cache based on addresses of the page cache. Accordingly, the operating speed of the program and the data processing apparatus can be improved. | 03-06-2014 |
20140068157 | SOLID-STATE DRIVE DEVICE - A solid state drive (SSD) device using a flash memory and including a non-volatile memory that differs in type from the flash memory. The SSD device receives data to be written to the flash memory; stores the received data in the non-volatile memory; stores the data stored in the non-volatile memory to the flash memory; and stores, in the non-volatile memory, flow data indicating a flow of tasks to be undertaken while storing the received data in the non-volatile memory and storing the data stored in the non-volatile memory to the flash memory. | 03-06-2014 |
20140068158 | FLASH STORAGE DEVICE AND CONTROL METHOD FOR FLASH MEMORY - A FLASH memory is used in data storage and is further stored with a logical-to-physical address mapping table and a write protection mapping table. The write protection mapping table shows the write protection statuses of the different logical addresses. In accordance with logical addresses issued via a dynamic capacity management command from a host, a controller of the data storage device modifies the logical-to-physical address mapping table to break the logical-to-physical mapping relationship of the issued logical addresses. Further, the controller asserts a flag, corresponding to the issued logical addresses, in the write protection mapping table, to a write protected mode. According to a change in the amount of write-protected flags of the write protection mapping table, the controller adjusts an end-of-life judgment value of the FLASH memory and thereby a lifespan of the FLASH memory is prolonged. | 03-06-2014 |
20140068159 | MEMORY CONTROLLER, ELECTRONIC DEVICE HAVING THE SAME AND METHOD FOR OPERATING THE SAME - A memory controller includes first and second interfaces, a microprocessor, a register and a plane control unit. The first interface is configured to receive a first command and plane logic information of a plurality of planes in a memory device from a host. The microprocessor is coupled to the first interface, and configured to decode the first command to provide a corresponding second command, and to map the plane logic information to be suited to a non-volatile memory device. The register is configured to queue the second command and the mapped plane logic information. The second interface is configured to provide the second command and the queued plane logic information to the memory device. The plane control unit is configured to control multiple planes corresponding to portions of the queued plane logic information to perform concurrently the second command in the non-volatile memory device. | 03-06-2014 |
20140068160 | MEMORY CONTROLLER, METHOD OF OPERATING MEMORY CONTROLLER, AND SYSTEM COMPRISING MEMORY CONTROLLER - A memory controller controls operation of a nonvolatile memory device comprising a memory area comprising a plurality of multi-level cells (MLCs). The memory controller receives an address of the memory area and data to be programmed to the memory area, analyzes access history information regarding the memory area based on the address, generates first mapping data corresponding to the data or second mapping data based on the data and previous mapping data that has been programmed to the MLCs according to a result of the analysis, and transmits a program command comprising one of the first mapping data and the second mapping data to the nonvolatile memory device. | 03-06-2014 |
20140068161 | MEMORY CONTROLLER, AND ELECTRONIC DEVICE HAVING THE SAME AND METHOD FOR OPERATING THE SAME - A memory controller includes a first interface and a microprocessor. The first interface is configured to receive a first command, a first address, an address state separation command, and a second address, the first address corresponding to the first command, and the address state separation command separating the first and second addresses from each other. The microprocessor is configured to decode the first command, map the first address to a non-volatile memory device, execute the first command relative to the first address mapped to the non-volatile memory device, and determine a relation between the first address and the second address. The microprocessor is further configured to selectively execute the second command relative to the second address mapped to the non-volatile memory device concurrently with the first command based on the relation between the first address and the second address. | 03-06-2014 |
20140068162 | DATA ACCESSING METHOD FOR FLASH MEMORY STORAGE DEVICE HAVING DATA PERTURBATION MODULE, AND STORAGE SYSTEM AND CONTROLLER USING THE SAME - A data accessing method, and a storage system and a controller using the same are provided. The data accessing method is suitable for a flash memory storage system having a data perturbation module. The data accessing method includes receiving a read command from a host and obtaining a logical block to be read and a page to be read from the read command. The data accessing method also includes determining whether a physical block in a data area corresponding to the logical block to be read is a new block and transmitting a predetermined data to the host when the physical block corresponding to the logical block to be read is a new block. Thereby, the host is prevented from reading garbled code from the flash memory storage system having the data perturbation module. | 03-06-2014 |
20140068163 | PERFORMING ASYNCHRONOUS DISCARD SCANS WITH STAGING AND DESTAGING OPERATIONS - A controller receives a request to perform staging or destaging operations with respect to an area of a cache. A determination is made as to whether one or more discard scans are being performed or queued for the area of the cache. In response to determining that one or more discard scans are being performed or queued for the area of the cache, the controller avoids satisfying the request to perform the staging or the destaging operations or a read hit with respect to the area of the cache. | 03-06-2014 |
20140075092 | SIMULATING EEPROM IN VIRTUAL DISTRIBUTED SWITCHES - A virtual EEPROM driver is simulated for a virtual switch. A write function may be written to a shared memory device and designated as a virtual EEPROM driver. The virtual EEPROM driver may be duplicated into a non-volatile memory providing availability during a boot process. | 03-13-2014 |
20140075093 | METHOD AND SYSTEM FOR IMPLICIT OR EXPLICIT ONLINE REPAIR OF MEMORY - Systems and methods related to a memory device are provided. The systems and methods include using at least one driver with predetermined reduced driving capability to drive at least one of the memory elements of the memory device in a reliable detection algorithm. The at least one driver has reduced driving capability compared to a driver used for standard read access. The reliable detection algorithm can include detecting failing memory elements on a respective reading current diverging from an expected or expectable reading current. | 03-13-2014 |
20140075094 | METHOD TO IMPLEMENT A BINARY FLAG IN FLASH MEMORY - A system and method for changing a state of a binary flag in a flash memory. The method defines a cell segment including a predetermined number of bits as the binary flag, where each bit is converted to a logical 1 when the memory is erased. The method also defines that an even number of logical 1 bits in the flash cell segment is an even parity and an odd number of logical 1 bits in the flash cell segment is an odd parity, and defines whether an even parity is an ON state of the binary flag or an odd parity is the ON state of the binary flag. The method changes the parity of the binary flag by writing one of the bits in the flash cell segment from a logical 1 to a logical 0 to change the state of the flag. | 03-13-2014 |
20140075095 | OPTIMIZED FRAGMENTED BLOCK COMPACTION WITH A BITMAP - A memory system may include an optimized data compaction algorithm. The compaction may include transferring only valid data from a source block to a destination block. A compaction bitmap that is maintained in random access memory (“RAM”) may be populated during the compaction process. The populated bitmap may be used to copy valid fragments to the destination block. | 03-13-2014 |
20140075096 | STORAGE DEVICE AND METHOD FOR CONTROLLING THE SAME - A storage device according to an embodiment includes: a host interface connected to a host; a memory including a first buffer that stores a logical address range designated by an invalidation instruction received from the host via the host interface and a second buffer that stores an internal logical address range which is an area combination with the logical address range; a nonvolatile memory; and a controller. The controller includes: an invalidation instruction processor that stores the logical address range designated by the invalidation instruction in the first buffer; an area combination executor that generates the internal logical address range by the area combination with the logical address range and stores the internal logical address range in the second buffer; and an invalidation executor that executes invalidation processing on the nonvolatile memory based on the internal logical address range. | 03-13-2014 |
20140075097 | SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR CONTROLLING NONVOLATILE SEMICONDUCTOR MEMORY - According to embodiments, a controller comprises a write control unit that performs writing in a nonvolatile semiconductor memory, and an area management unit that causes the write control unit to perform write processing until a spare area not storing valid data is not present in the nonvolatile semiconductor memory, and transmits an error to a host when the spare area is not present. | 03-13-2014 |
20140075098 | MEMORY SYSTEM AND CONTROL METHOD FOR THE SAME - A memory system includes a non-volatile memory, a compressor capable of compressing data, an encryptor which encrypts data, a decryptor which decrypts data, and a data flow controller. The data flow controller is configured to perform first and second processes. In the first process, the data flow controller causes the encryptor to encrypt user data received from a host in a non-compressed state, and causes the encrypted user data to be written into the non-volatile memory via the second area. In the second process, the data flow controller causes the encrypted user data to be read out from the non-volatile memory, causes the decryptor to decrypt the encrypted user data, causes the compressor to compress the decrypted user data, causes the encryptor to encrypt the compressed user data, and causes the encrypted and compressed user data to be written into the non-volatile memory. | 03-13-2014 |
20140075099 | CONTROL METHOD AND MEMORY SYSTEM OF NON-VOLATILE SEMICONDUCTOR MEMORY - A method and a device for controlling a non-volatile semiconductor memory device having a plurality of physical memory blocks are described. The control method includes forming a logical block including normal physical blocks and a defective physical block. Then read-only data (which can include system data and user data which is infrequently used) is targeted for a write to the defective physical block. Instead of actually writing the read-only data in the defective physical block, an error correction coding generated using the read-only data is stored in the normal physical blocks together with other data. When the read-only data is requested to be read, the read-only data is reproduced using the error correction coding. | 03-13-2014 |
20140075100 | MEMORY SYSTEM, COMPUTER SYSTEM, AND MEMORY MANAGEMENT METHOD - A memory system includes a non-volatile memory having a physical memory region and a controller for conducting data transmission between the non-volatile memory and a host. The controller includes a section management module and a wear leveling module. The section management module divides the physical memory region into multiple sections including a first section and one or more of second sections. The wear leveling module performs independent wear leveling for each of the second sections without performing wear leveling for the first section. The section management module performs expansion of the first section according to a physical memory region expansion request from the host. | 03-13-2014 |
20140075101 | METHODS FOR TWO-DIMENSIONAL MAIN MEMORY - In one embodiment of the invention, a memory module is disclosed including a printed circuit board with an edge connector; an address controller coupled to the printed circuit board; and a plurality of memory slices. Each of the plurality of memory slices of the memory module includes one or more memory integrated circuits coupled to the printed circuit board, and a slave memory controller coupled to the printed circuit board and the one or more memory integrated circuits. The slave memory controller receives memory access requests for the memory module from the address controller. The slave memory controller selectively activates one or more of the one or more memory integrated circuits in the respective memory slice in response to the address received from the address controller to read data from or write data into selected memory locations in the memory integrated circuits. | 03-13-2014 |
20140075102 | CONTROLLER OF A NONVOLATILE MEMORY DEVICE AND A COMMAND SCHEDULING METHOD THEREOF - A controller which includes a working memory on which a command scheduler is loaded; and a processor configured to load at least one mapping table from a mapping table array onto the working memory. The command scheduler reorders commands provided from a host based on logical block addresses, and the processor loads at least one other mapping table onto the working memory according to logical block addresses of the commands reordered by the command scheduler. | 03-13-2014 |
20140075103 | METHOD CAPABLE OF INCREASING PERFORMANCE OF A MEMORY AND RELATED MEMORY SYSTEM - The present invention discloses a method capable of increasing performance of a memory, where a memory system applied to the method includes a memory and a controller, and a reserved space of the memory is used for storing a logic address/physical block mapping table. The method includes the controller reserving a plurality of physical blocks of the memory as a writing buffer pool; and the controller executing width writing operation or depth writing operation on a plurality of data and the writing buffer pool according to the logic address/physical block mapping table when the plurality of data are written to the memory. The logic address/physical block mapping table includes corresponding relationships between the plurality of physical blocks and a plurality of logic addresses. | 03-13-2014 |
20140075104 | SIMULATING NON-VOLATILE MEMORY IN VIRTUAL DISTRIBUTED SWITCHES - A virtual non-volatile memory is simulated for a virtual switch. Operating instructions from the non-volatile memory of a physical switch may be translated into a flash type file. The flash type file may be stored on a virtual storage area in the virtual switch. Operating instructions in the virtual switch may access the flash type file in the virtual storage area without the need to access the non-volatile memory in the physical switch. | 03-13-2014 |
20140075105 | SCHEDULING OF I/O IN AN SSD ENVIRONMENT - A system and method for effectively scheduling read and write operations among a plurality of solid-state storage devices. A computer system comprises client computers and data storage arrays coupled to one another via a network. A data storage array utilizes solid-state drives and Flash memory cells for data storage. A storage controller within a data storage array comprises an I/O scheduler. The characteristics of corresponding storage devices are used to schedule I/O requests to the storage devices in order to maintain relatively consistent response times at predicted times. In order to reduce a likelihood of unscheduled behaviors of the storage devices, the storage controller is configured to schedule proactive operations on the storage devices that will reduce a number of occurrences of unscheduled behaviors. | 03-13-2014 |
20140082257 | SYSTEMS AND METHODS FOR CODE PROTECTION IN NON-VOLATILE MEMORY SYSTEMS - Methods and systems are disclosed for code protection in non-volatile memory (NVM) systems. Information stored within NVM memory sectors, such as boot code or other code blocks, is protected using lockout codes and lockout keys written in program-once memory areas within the NVM systems. Further, lockout codes can be combined into a merged lockout code that can be stored in a merged protection register. The merged protection register is used to control write access to protected memory sectors. Lockout code/key pairs are written to the program-once area when a memory sector is protected. The program-once area, which stores the lockout code/key pairs, is not readable by external users. Once protected, a memory sector can not be updated without the lockout code/key pair. | 03-20-2014 |
20140082258 | MULTI-SERVER AGGREGATED FLASH STORAGE APPLIANCE - A device for aggregating flash modules includes a switch to connect to a plurality of servers and a midplane to connect to a plurality of flash modules. The switch and midplane are connected such that the switch can route data traffic to any of the plurality of flash modules, and the plurality of servers can connect to the plurality of flash modules transparently, as if a flash module was directly installed into a server. | 03-20-2014 |
20140082259 | DATA STORING METHOD, MEMORY CONTROLLER AND MEMORY STORAGE APPARATUS - A data storing method for a memory storage apparatus having a flash memory module is provided. The method includes detecting the operating temperature of the memory storage device through a thermal sensor and determining whether the operating temperature of the memory storage device is larger than a predetermined temperature. The methods further includes using a first data storing mode to access the flash memory module if the operating temperature of the memory storage device is not larger than the predetermined temperature; and using a second data storing mode to access the flash memory module if the operating temperature of the memory storage apparatus is larger than the predetermined temperature, wherein the first data storing mode is different from the second data storing mode. Accordingly, the method can effectively ensure the accuracy of the data stored into the flash memory module. | 03-20-2014 |
20140082260 | FLASH MEMORY CONTROLLER HAVING DUAL MODE PIN-OUT - A memory controller of a data storage device, which communicates with a host, is configurable to have at least two different pinout assignments for interfacing with respective different types of memory devices. Each pinout assignment corresponds to a specific memory interface protocol. Each memory interface port of the memory controller includes port buffer circuitry configurable for different functional signal assignments, based on the selected memory interface protocol to be used. The interface circuitry configuration for each memory interface port is selectable by setting a predetermined port or registers of the memory controller. | 03-20-2014 |
20140082261 | SELF-JOURNALING AND HIERARCHICAL CONSISTENCY FOR NON-VOLATILE STORAGE - A non-volatile storage system having Non-Volatile Memory (NVM) provides self-journaling and hierarchical consistency, enabling low-latency recovery and force unit access handshake. Mappings between host addresses and addresses in the NVM are maintained via one or more map entries, enabling locating of host data written to the NVM. Objects stored in the NVM include sufficient information to recover the object solely within the object itself. The NVM is managed as one or more data streams, a map stream, and a checkpoint stream. Host data is written to the data streams, map entries are written to the map stream, and checkpoints of map entries and other data structures are written to the checkpoint stream. Time markers embedded in the streams enable determination, during recovery, that selected portions of the streams are inconsistent with each other and are to be discarded. | 03-20-2014 |
20140082262 | APPARATUS, METHOD AND SYSTEM THAT STORES BIOS IN NON-VOLATILE RANDOM ACCESS MEMORY - A non-volatile random access memory (NVRAM) is used in a computer system to perform multiple roles in the platform storage hierarchy. The NVRAM is byte-rewritable and byte-erasable by the processor. The NVRAM is coupled to the processor to be directly accessed by the processor without going through an I/O subsystem. The NVRAM stores a Basic Input and Output System (BIOS). During a Pre-Extensible Firmware Interface (PEI) phase of the boot process, the cache within the processor can be used in a write-back mode for execution of the BIOS. | 03-20-2014 |
20140082263 | MEMORY SYSTEM - According to one embodiment, a memory system includes a plurality of nonvolatile memories, an address converter, a plurality of channel controllers, and a controller. The plurality of nonvolatile memories is connected to respective channels. The address converter converts a logical address of a read request into a physical address of the nonvolatile memories. Each of the channel controllers is provided to each of the channels. Each of the channel controllers has a plurality of queues, each queues stores at least two read request. The controller selects a queue which stores no read request, and transfers the read request to the selected queue. | 03-20-2014 |
20140082264 | NAND FLASH STORAGE CHIP CHECKING METHOD AND DEVICE - A NAND flash storage chip correcting method is provided in the present invention. The method can correct one or two bits errors and find a number of bits errors according to the row and column XOR value and Hash value of each page written into the spare area, comparing the data stored in the data area and the computed Hash value of data area to correct one or two bits of errors, thus ensures the accuracy and integrity of the data stored in the NAND Flash chip and reduces the risk of crash of the file system. | 03-20-2014 |
20140082265 | DATA STORAGE DEVICE AND FLASH MEMORY CONTROL METHOD THEREOF - A mapping table H2F update technique for a FLASH memory is disclosed. In a disclosed data storage device, the controller updates a logical-to-physical address mapping table between a host and the FLASH memory in accordance with a group count of a buffer block of the FLASH memory. The group count reflects a logical address distribution of write data buffered in the buffer block and with non-updated logical-to-physical address mapping information. The higher the group count, the more dispersed the logical address distribution. In this manner, each update of the logical-to-physical address mapping table just takes a short time. | 03-20-2014 |
20140082266 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a plurality of memory strings each of which includes a series of memory cells that each store data having n bits (n≧3), word lines, each connected in common to memory cells of different memory strings, and a control circuit which controls a first write operation and a second write operation. The first write operation includes a first step where a middle threshold voltage distribution is formed in memory cells and a second step following the first step where threshold voltages of some of the memory cells are increased, and the second write operation includes a step where threshold voltage distributions which correspond to the data having n bits is formed in the memory cells, wherein a write verify operation is performed after the first step but not after the second step of the first write operation. | 03-20-2014 |
20140082267 | EMBEDDED MULTIMEDIA CARD (eMMC), HOST CONTROLLING eMMC, AND METHOD OPERATING eMMC SYSTEM - An embedded multimedia card (eMMC) includes a flash memory and an eMMC controller that controls operation of the flash memory. The eMMC controller includes a command register that receives from a host a command set defining a next operation specifying second data simultaneously with a transfer of first data specified by a current operation, a first memory that stores the first data, and a second memory that stores the second data. | 03-20-2014 |
20140082268 | HOST FOR CONTROLLING NON-VOLATILE MEMORY CARD, SYSTEM INCLUDING THE SAME, AND METHODS OPERATING THE HOST AND THE SYSTEM - A host for controlling a non-volatile memory card, a system including the same, and methods of operating the host and the system are provided. The method of operating the host connected with the non-volatile memory card through a clock bus, a command bus, and one or more data buses includes transmitting a first command to the non-volatile memory card through the command bus, transmitting first data corresponding to the first command to the non-volatile memory card through the one or more data buses or receiving the first data from the non-volatile memory card through the data buses, and transmitting a second command to the non-volatile memory card at least once through the command bus during or before transfer of the first data. | 03-20-2014 |
20140082269 | EMBEDDED MULTIMEDIA CARD (eMMC), HOST CONTROLLING SAME, AND METHOD OF OPERATING eMMC SYSTEM - A method of operating an eMMC system includes a host sending SEND_EXT_CSD command to obtain busy control clock information from an eMMC. The busy control clock information is then used to control provision of a host-provided clock to the eMMC while the eMMC is in a busy state. | 03-20-2014 |
20140082270 | METHODS, APPARATUSES, AND COMPUTER PROGRAM PRODUCTS FOR ENHANCING MEMORY ERASE FUNCTIONALITY - A method, apparatus, and computer program product are provided for enhancing memory erase functionality. An apparatus may include a block-based mass memory and a controller configured to receive an erase command from a host device comprising an indication of a location of a block in the mass memory storing memory allocation data. The controller may be further configured to access the memory allocation data based at least in part upon the indicated location. The controller may additionally be configured to determine, based at least in part upon the memory allocation data, blocks within the mass memory that have been freed by the host device. The controller may also be configured to erase the freed blocks. Corresponding methods and computer program products are also provided. | 03-20-2014 |
20140082271 | FLASH MEMORY ARCHITECTURE WITH SEPARATE STORAGE OF OVERHEAD AND USER DATA - A memory device has a plurality of dedicated data blocks for storing user data and a plurality of dedicated overhead blocks for storing overhead data. A dedicated overhead block of the plurality of dedicated overhead blocks has a plurality of overhead segments. The overhead segments have physical block address registers configured to store physical block addresses defining respective dedicated data blocks. | 03-20-2014 |
20140089560 | MEMORY DEVICES AND METHODS HAVING WRITE DATA PERMUTATION FOR CELL WEAR REDUCTION - A memory system can include a plurality of memory elements each comprising a memory layer having at least one layer programmable between at least two different impedance states; a data input configured to receive multi-bit write data values; and a permutation circuit coupled between the memory elements and the data input, and configured to repeatedly permute the multi-bit write data values prior to writing such data values into the memory elements. | 03-27-2014 |
20140089561 | Techniques Associated with Protecting System Critical Data Written to Non-Volatile Memory - Examples are disclosed for techniques associated with protecting system critical data written to non-volatile memory. In some examples, system critical data may be written to a non-volatile memory using a first data protection scheme. User data that includes non-system critical data may also be written to the non-volatile memory using a second data protection scheme. For these examples, both data protection schemes may have a same given data format size. Various examples are provided for use of the first data protection scheme that may provide enhanced protection for the system critical data compared to protection provided to user data using the second data protection scheme. Other examples are described and claimed. | 03-27-2014 |
20140089562 | EFFICIENT I/O PROCESSING IN STORAGE SYSTEM - Exemplary embodiments provide information processing system and data processing for efficient I/O processing in the storage system. In one aspect, a storage system comprises: a memory; and a controller being operable to execute a process for data stored in the memory so that an address of the data stored in the memory is changed between a first address managed in a virtual memory on a server and a second address managed by the controller, based on a command containing an address corresponding to the first address, the command being sent from the server to the storage system. In some embodiments, the memory includes a server data memory and a storage data memory. In specific embodiments, in response to the command from the server, the controller is operable to change a status of data stored in the memory from server data to storage data or from storage data to server data. | 03-27-2014 |
20140089563 | CONFIGURATION INFORMATION BACKUP IN MEMORY SYSTEMS - According to one configuration, a memory system includes a configuration manager and multiple memory devices. The configuration manager includes status detection logic, retrieval logic, and configuration management logic. The status detection logic receives notification of a failed attempt by a first memory device to be initialized with custom configuration settings stored in the first memory device. In response to the notification, the retrieval logic retrieves a backup copy of configuration settings information from a second memory device in the memory system. The configuration management logic utilizes the backup copy of the configuration settings information retrieved from the second memory device to initialize the first memory device. | 03-27-2014 |
20140089564 | METHOD OF DATA COLLECTION IN A NON-VOLATILE MEMORY - A method of data collection is performed in a non-volatile memory that has a number of blocks and each block has multiple pages. A timestamp is recorded associated with a data written to the non-volatile memory. Some of the written data are moved from a plurality of different pages respectively to a first block according to the timestamps associated with the plurality of written data stored in the plurality of different pages. | 03-27-2014 |
20140089565 | SOLID STATE DEVICE WRITE OPERATION MANAGEMENT SYSTEM - A solid state device (SSD) write operation management system including a file system that incorporates SSD status information into its operational logic is disclosed. By incorporating SSD status information, the system achieves various advantages over conventional systems, such as enhanced write performance and extended SSD lifespan. The system processes various criteria to select the optimal virtual device (“vdev”) for data allocation in response to a write request. The first criterion utilizes Program/Erase counts of physical blocks contained in the SSDs. Another criterion is the number of physical free blocks of a drive. If the average of the selected vdev's physical free blocks is higher than the OP threshold, then the system selects for data allocation the vdev with the greatest amount of logical free space. In the instance that the average is lower, the system schedules garbage collection for the vdev. | 03-27-2014 |
20140089566 | DATA STORING METHOD, AND MEMORY CONTROLLER AND MEMORY STORAGE APPARATUS USING THE SAME - A data storing method and a memory controller and a memory storage apparatus using the same are provided. The method includes logically grouping physical erase units into a data area and a spare area; selecting a physical erase unit form the spare area as a first data collecting unit; and selecting a physical erase unit from the spare area as a second data collecting unit. The method also includes writing data received from a host into the first data collecting unit. The method further includes performing a data arranging operation to move valid data in a third physical erase unit to the second data collecting unit and associating the third physical erase unit with the spare area. Accordingly, the method can effectively enhance the performance of the write operation. | 03-27-2014 |
20140089567 | HARDWARE INTEGRITY VERIFICATION - A flash memory management method and apparatus provides for the separation of the command and data paths so that communication paths may be used more efficiently, taking account of the characteristics of NAND FLASH circuits where the times to read, write and erase data differ substantially. A unique sequence identifier is assigned to a write command and associated data and association of the data and commands are validated prior to writing to the memory by comparing the unique sequence numbers of the data and command prior to executing the command. This comparison is performed after the data and command have traversed the communication paths. | 03-27-2014 |
20140089568 | EMBEDDED MULTIMEDIA CARD (EMMC), HOST FOR CONTROLLING THE EMMC, AND METHODS OF OPERATING THE EMMC AND THE HOST - A method of operating an eMMC system includes receiving a first command defining a first operation from the host, and storing the first command in a first command register among N command registers, and receiving a second command defining a second operation from the host, and storing the second command in a second command register among the N command registers, wherein the second command is received while the first operation is being performed. | 03-27-2014 |
20140089569 | WRITE CACHE SORTING - A method of managing a non-volatile memory system is described where data elements stored in a buffer are characterized by attributes and a write data tag is created for the data elements. A plurality of write data tag queues is maintained so that different data attributes may be applied as sorting criteria when the data elements are formed into pages for storage in the non-volatile memory. The memory system may be organized as a RAID system and a write data tag queue may be associated with a specific RAID group such that the data pages may be written from a buffer to the non-volatile memory in accordance with the results of sorting each write data queue. The data elements stored in the buffer may be received from a user, or be read from the non-volatile memory during the performance of system overhead operations. | 03-27-2014 |
20140089570 | SEMICONDUCTOR MEMORY - A memory block area in a semiconductor memory includes program segments. Each program segment includes a group of memory cells arranged at positions where word lines and bit lines intersect and connected to a common source line. The word lines are shared by the program segments. At program operation time source line switches are used for supplying first voltage to a source line in a program segment, of the program segments, including a memory cell to be programmed and supplying second voltage to a source line in a program segment, of the program segments, not including the memory cell to be programmed. | 03-27-2014 |
20140089571 | BIT INVERSION IN MEMORY DEVICES - Bit inversions occurring in memory systems and apparatus are provided. Data is acquired from a source destined for a target. As the data is acquired from the source, the set bits associated with data are tabulated. If the total number of set bits exceeds more than half of the total bits, then an inversion flag is set. When the data is transferred to the target, the bits are inverted during the transfer if the inversion flag is set. | 03-27-2014 |
20140095764 | MICROCONTROLLER WITH INTEGRATED INTERFACE ENABLING READING DATA RANDOMLY FROM SERIAL FLASH MEMORY - A microcontroller includes a microprocessor, a serial flash memory interface, and input/output (I/O) terminals for coupling the serial flash memory interface to external serial flash memory. The microprocessor is operable to generate instruction frames that trigger respective commands to read data from specified addresses in the external serial flash memory. The serial flash memory interface receives and processes the instruction frames, obtains the data contained in the specified addresses in the external serial flash memory regardless of whether the specified addresses are sequential or non-sequential, and provides the data for use by the microprocessor. | 04-03-2014 |
20140095765 | FLASH TRANSLATION LAYER (FTL) DATABASE JOURNALING SCHEMES - A method includes, in a storage device that includes a non-volatile memory and a volatile memory, maintaining at least one data structure that stores management information used for managing data storage in the non-volatile memory, such that at least a portion of the data structure is stored in the volatile memory. A sequence of journaling chunks is created during operation of the storage device, each journaling chunk including a respective slice of the data structure and one or more changes that occurred in the data structure since a previous journaling chunk in the sequence. The sequence of the journaling chunks is stored in the non-volatile memory. Upon recovering from an electrical power interruption in the storage device, the data structure is reconstructed using the stored journaling chunks. | 04-03-2014 |
20140095766 | PERSISTENT LOG OPERATIONS FOR NON-VOLATILE MEMORY - In an embodiment, a first delayed persistence operation to store information in a log contained in a non-volatile memory (NVM) may be performed. The information may include, for example, a current value of a variable contained in the NVM. A second delayed persistence operation to store information in the variable may be performed. A third delayed persistence operation to store information in the NVM that indicates the log is cleared may be performed. A flush operation may be performed, for example after the first, second, and third delayed persistence operations. The flush operation may commit information associated with at least one of the first, second, or third delayed persistence operations to the NVM. | 04-03-2014 |
20140095767 | STORAGE DEVICE TRIMMING - In an embodiment, a command that specifies a logical block to trim in a storage device is acquired. An entry in a logical-to-physical address (L2P) table that contains a physical address that corresponds to the logical block may be set to point to an invalid address. A trim token that specifies the logical block may be generated. The trim token may be stored in a non-volatile storage contained in the storage device. | 04-03-2014 |
20140095768 | ENCODING DATA FOR STORAGE IN A DATA STORAGE DEVICE - A data storage device includes a memory and a controller. A method performed in the data storage device includes performing a first transformation of a unit of data to generate a first transformed unit of data. Performing the first transformation includes sorting permutations of the unit of data. The method includes performing a move-to-front transformation of the first transformed unit of data to generate a second transformed unit of data. The method includes performing a weight-based encoding of the second transformed unit of data to generate an encoded unit of data. The encoded unit of data has a same number of bits as the unit of data. | 04-03-2014 |
20140095769 | FLASH MEMORY DUAL IN-LINE MEMORY MODULE MANAGEMENT - Systems and methods to manage memory on a dual in-line memory module (DIMM) are provided. A particular method may include receiving at a flash application-specific integrated circuit (ASIC) a request from a processor to access data stored in a flash memory of a DIMM. The data may be transferred from the flash memory to a switch of the DIMM. The data may be routed to a dynamic random-access memory (DRAM) of the DIMM. The data may be stored in the DRAM and may be provided from the DRAM to the processor. | 04-03-2014 |
20140095770 | Selective Protection of Lower Page Data During Upper Page Write - Lower page data that may be endangered by programming upper page data in the same memory cells is protected during upper programming using protective upper page programming schemes. High overall programming speeds are maintained by selectively using protective upper programming schemes only where endangered data is committed and may not be recoverable from another location. | 04-03-2014 |
20140095771 | HOST DEVICE, COMPUTING SYSTEM AND METHOD FOR FLUSHING A CACHE - A computing system includes a storage device, and a host device configured to flush a plurality of pages to the storage device. The host device includes a write-back (WB) cache configured to store the pages, and a file system module configured to flush pages having first characteristics to the storage device from among the pages stored in the WB cache, and then flush pages having second characteristics which are different from the first characteristics to the storage device from among the pages stored in the WB cache. | 04-03-2014 |
20140095772 | COMPUTING SYSTEM AND METHOD OF MANAGING DATA IN THE COMPUTING SYSTEM - A computing system a storage device and a file system. The storage device includes a storage area having flash memory. The file system is configured to divide the storage area into multiple zones, multiple sections and multiple blocks, and to write a log in each block. The file system includes a block allocation module. The block allocation module is configured to allocate a target block, in which a log is to be written, by a continuous block allocation method according to which a block having a continuous address with a most recently selected block is set as the target block. The block allocation module is further configured to find a free section from the multiple sections when it is not possible to allocate the target block by the continuous block allocation method, and to set a block in the found free section as the target block. | 04-03-2014 |
20140095773 | SOLID STATE MEMORY DEVICE LOGICAL AND PHYSICAL PARTITIONING - Embodiments relate to solid state memory device including a storage array having a plurality of physical storage devices and the storage array includes a plurality of partitions. The solid state memory device also includes a controller comprising a plurality of mapping tables, wherein each of the plurality of mapping tables corresponds to one of the plurality of partitions. Each of the plurality of mapping tables is configured to store a physical location and a logical location of data stored in its corresponding partition. | 04-03-2014 |
20140095774 | CODE PATCHING FOR NON-VOLATILE MEMORY - Example embodiments described herein may comprise a transfer of firmware execution within a non-volatile memory device to one or more replacement instructions at least in part in response to a match between a code fetch address and an address stored in a trap address register. | 04-03-2014 |
20140095775 | SYSTEMS AND METHODS FOR CACHE ENDURANCE - A cache and/or storage module may be configured to reduce write amplification in a cache storage. Cache layer write amplification (CLWA) may occur due to an over-permissive admission policy. The cache module may be configured to reduce CLWA by configuring admission policies to avoid unnecessary writes. Admission policies may be predicated on access and/or sequentiality metrics. Flash layer write amplification (FLWA) may arise due to the write-once properties of the storage medium. FLWA may be reduced by delegating cache eviction functionality to the underlying storage layer. The cache and storage layers may be configured to communicate coordination information, which may be leveraged to improve the performance of cache and/or storage operations. | 04-03-2014 |
20140095776 | STORAGE SYSTEM INCLUDING A PLURALITY OF FLASH MEMORY DEVICES - A storage system including a storage device which includes media for storing data from a host computer, a medium controller for controlling the media, a plurality of channel controllers for connecting to the host computer through a channel and a cache memory for temporarily storing data from the host computer, wherein the media have a restriction on a number of writing times. The storage device includes a bus for directly transferring data from the medium controller to the channel controller. | 04-03-2014 |
20140101368 | Binding microprocessor to memory chips to prevent re-use of microprocessor - A processor is provided that binds itself to a circuit such that the processor cannot be subsequently reused in other circuits. On a first startup of the processor, a memory segment of an external volatile memory device is read to obtain information prior to initialization of the memory segment. An original/initial identifier may be generated from the information read from the memory segment. The original/initial identifier may then be stored in a non-volatile storage of the processor. On subsequent startups of the processor, it verifies that the processor is still coupled to the same external volatile memory device by using the stored identifier. For instance, on a subsequent startup, the processor again reads the same memory segment of the external memory device and generates a new identifier. If the identifier matches the previously stored identifier, then the processor may continue its operations; otherwise the processor is disabled/halted. | 04-10-2014 |
20140101369 | METHODS, DEVICES AND SYSTEMS FOR PHYSICAL-TO-LOGICAL MAPPING IN SOLID STATE DRIVES - A data storage device comprises a plurality of non-volatile memory devices storing physical pages, each stored at a predetermined physical location. A controller may be coupled to the memory devices and configured to access data stored in a plurality of logical pages (L-Pages), each associated with an L-Page number that enables the controller to logically reference data stored in the physical pages. A volatile memory may comprise a logical-to-physical address translation map that enables the controller to determine a physical location, within the physical pages, of data stored in each L-Page. The controller may be configured to maintain, in the memory devices, journals defining physical-to-logical correspondences, each journal covering a predetermined range of physical pages and comprising a plurality of entries that associate one or more physical pages to each L-Page. The controller may read the journals upon startup and rebuild the address translation map from the read journals. | 04-10-2014 |
20140101370 | APPARATUS AND METHOD FOR LOW POWER LOW LATENCY HIGH CAPACITY STORAGE CLASS MEMORY - A method and a storage system are provided for implementing enhanced solid-state storage class memory (eSCM) including a direct attached dual in line memory (DIMM) card containing dynamic random access memory (DRAM), and at least one non-volatile memory, for example, Phase Change memory (PCM), Resistive RAM (ReRAM), Spin-Transfer-Torque RAM (STT-RAM), and NAND flash chips. An eSCM processor controls selectively allocating data among the DRAM, and the at least one non-volatile memory primarily based upon a data set size. | 04-10-2014 |
20140101371 | SYSTEMS AND METHODS FOR NONVOLATILE MEMORY PERFORMANCE THROTTLING - Systems and methods for nonvolatile memory (“NVM”) performance throttling are disclosed. Performance of an NVM system may be throttled to achieve particular data retention requirements. In particular, because higher storage temperatures tend to reduce the amount of time that data may be reliably stored in an NVM system, performance of the NVM system may be throttled to reduce system temperatures and increase data retention time. | 04-10-2014 |
20140101372 | MEMORY SYSTEM AND READ RECLAIM METHOD THEREOF - A memory system includes a nonvolatile memory device including a first memory area formed of memory blocks which store n-bit data per cell and a second memory area formed of memory blocks which store m-bit data per cell, where n and m are different integers, and a memory controller configured to control the nonvolatile memory device. The memory controller is configured to execute a read operation, and to execute a read reclaim operation in which valid data of a target memory block of the second memory area is transferred to one or more memory blocks of the first memory area, the target memory block selected during the read operation. The read reclaim operation is processed as complete when all the valid data of the target memory block is transferred to the one or more memory blocks of the first memory area. | 04-10-2014 |
20140101373 | METHOD OF MANAGING DATA STORAGE DEVICE AND DATA STORAGE DEVICE - A method of managing a data storage device including a memory controller and a memory device includes: calculating a first sequential and consecutive write cost (SCWC) according to a garbage collection (GC) write operation policy, a second SCWC according to a slack space recycling (SSR) write operation policy and a third SCWC according to an in-place updating (IPU) write operation policy respectively, in response to a write request in the memory controller; determining a write operation policy which has a minimum cost of the first through third SCWCs; and writing data in a selected segment in the memory device according to the determined write operation policy. | 04-10-2014 |
20140101374 | TRACKING A LIFETIME OF WRITE OPERATIONS TO A NON-VOLATILE MEMORY STORAGE - A method, device, and system are disclosed. In one embodiment method begins by incrementing a count of a total number of write operations to a non-volatile memory storage for each write operation to the non-volatile memory storage. The method then receives a request for the total count of lifetime write operations from a requestor. Finally, the method sends the total count of lifetime write operations to the requestor. | 04-10-2014 |
20140101375 | APPARATUS, SYSTEM, AND METHOD FOR ALLOCATING STORAGE - An apparatus, system, and method are disclosed for allocating non-volatile storage. The storage device may present a logical address, which may exceed a physical storage capacity of the device. The storage device may allocate logical capacity in the logical address space. An allocation request may be allowed when there is sufficient unassigned and/or unallocated logical capacity to satisfy the request. Data may be stored on the non-volatile storage device by requesting physical storage capacity. A physical storage request, such as a storage request or physical storage reservation, when there is sufficient available physical storage capacity to satisfy the request. The device may maintain an index to associate logical identifiers (LIDs) in the logical address space with storage locations on the storage device. This index may be used to make logical capacity allocations and/or to manage physical storage space. | 04-10-2014 |
20140101376 | APPARATUS, SYSTEM, AND METHOD FOR CONDITIONAL AND ATOMIC STORAGE OPERATIONS - An apparatus, system, and method are disclosed for implementing conditional storage operations. Storage clients access and allocate portions of an address space of a non-volatile storage device. A conditional storage request is provided, which causes data to be stored to the non-volatile storage device on the condition that the address space of the device can satisfy the entire request. If only a portion of the request can be satisfied, the conditional storage request may be deferred or fail. An atomic storage request is provided, which may comprise one or more storage operations. The atomic storage request succeeds if all of the one or more storage operations are complete successfully. If one or more of the storage operations fails, the atomic storage request is invalidated, which may comprise deallocating logical identifiers of the request and/or invalidating data on the non-volatile storage device pertaining to the request. | 04-10-2014 |
20140101377 | SOLID STATE MEMORY (SSM), COMPUTER SYSTEM INCLUDING AN SSM, AND METHOD OF OPERATING AN SSM - In one aspect, data is stored in a solid state memory which includes first and second memory layers. A first assessment is executed to determine whether received data is hot data or cold data. Received data which is assessed as hot data during the first assessment is stored in the first memory layer, and received data which is first assessed as cold data during the first assessment is stored in the second memory layer. Further, a second assessment is executed to determine whether the data stored in the first memory layer is hot data or cold data. Data which is then assessed as cold data during the second assessment is migrated from the first memory layer to the second memory layer. | 04-10-2014 |
20140101378 | Metadata Rebuild in a Flash Memory Controller Following a Loss of Power - A method of rebuilding metadata in a flash memory controller following a loss of power is provided. The method includes reading logical address information associated with an area of flash memory, and using time stamp information to determine if data stored in the flash memory area are valid. | 04-10-2014 |
20140101379 | Variable Over-Provisioning For Non-Volatile Storage - Dynamically varying Over-Provisioning (OP) enables improvements in lifetime, reliability, and/or performance of a Solid-State Disk (SSD) and/or a flash memory therein. A host coupled to the SSD writes newer data to the SSD. If the newer host data is less random than older host data, then entropy of host data on the SSD decreases. In response, an SSD controller of the SSD dynamically alters allocations of the flash memory, decreasing host allocation and increasing OP allocation. If the newer host data is more random, then the SSD controller dynamically increases the host allocation and decreases the OP allocation. The SSD controller dynamically allocates the OP allocation between host OP and system OP proportionally in accordance with a ratio of bandwidths of host and system data writes to the flash memory. | 04-10-2014 |
20140108702 | STORAGE SYSTEM WHICH INCLUDES NON-VOLATILE SEMICONDUCTOR STORAGE MEDIUM, AND STORAGE CONTROL METHOD OF STORAGE SYSTEM - A storage system is configured to perform the host write process including the following process (a1) and (a2),
| 04-17-2014 |
20140108703 | Scalable Data Structures for Control and Management of Non-Volatile Storage - Scalable control/management data structures enable optimizing performance and/or attempting to achieve a particular performance target of an SSD in accordance with host interfacing, number of NVM devices, NVM characteristics and size, and NVM aging and performance decline. Pre-scaled data structures are included in SSD controller firmware loadable at system initialization. Static data structure configurations enable load-once-operate-for-product-lifetime operation for consumer applications. Dynamic configurations provide sequences of data structures pre-scaled to optimize operation as NVM ages and performance declines. Pre-configured adjustments in data structure size included in consecutive configurations periodically replace earlier configurations at least one time during product lifetime, producing a periodic rescaling of data structure size to track changes in aging NVM. Optionally, sizes of some data structures are decreased as NVM usage increases, enabling an increase in translation layer mapping structure sizes, reducing accesses to translation tables in NVM, and reducing write amplification. | 04-17-2014 |
20140108704 | DATA DECOMPRESSION METHOD FOR A CONTROLLER EQUIPPED WITH LIMITED RAM - A method of operating a controller to decompress a compressed data file stored on a host computer, and store the resulting uncompressed data in a flash memory. The processor loads compressed data into random access memory (RAM) until a predetermined amount of compressed data is present in the RAM. The controller then decompresses compressed data retrieved from the RAM until a decompressed amount of decompressed data equals a block size corresponding to a minimum modulus size of the flash memory, where the minimum size block of data that can be written to the flash memory because of the design of the flash memory. The controller then transfers the block of decompressed data to the flash memory. These steps are repeated in a coordinated fashion until the entire compressed data file has been downloaded from the host computer, decompressed by the controller, and stored in the flash memory. | 04-17-2014 |
20140108705 | Use of High Endurance Non-Volatile Memory for Read Acceleration - A high endurance, short retention NAND memory is used as a read cache for a memory of a higher level of non-volatility, such as standard NAND flash memory or a hard drive. The combined memory system identifies frequently read logical addresses of the main non-volatile memory or specific read sequences and stores the corresponding data in cache NAND to accelerate host reads. This may also reduce host's DRAM requirements. In some arrangements, special commands or partitions can be used by operating system to identify these fast read areas. The main non-volatile memory will typically also maintain a back-up copy of data in the cache NAND. In some embodiments, the read cache can be implemented as a middle layer between the host and storage system, say as an SATA-SATA bridge dongle to boost read access for frequently read data or specific patterns, such as a boot sequence. | 04-17-2014 |
20140108706 | DATA STORAGE DEVICE, STORAGE MEDIA CONTROLLER AND STORAGE MEDIA CONTROL METHOD - A storage media control method, by which a data strobe signal is shifted by different phase shifts at different time intervals during a write-leveling operation to be received by a storage media and compared to a clock signal for returning a data signal. At the storage media side, during the write-leveling operation, a synchronous transmission between the received data strobe signal and the clock signal causes a transition event at the data signal. The number of transition-event occurrences is counted. When the count shows that just one transition event has occurred over a full round of phase shift tests of the data strobe signal, the phase shift corresponding to the transition event is used in the adjustment of the data strobe signal, which is received by the storage media as the data extraction reference of a write operation. | 04-17-2014 |
20140108707 | DATA STORAGE ARCHITECTURE AND SYSTEM FOR HIGH PERFORMANCE COMPUTING - Data storage systems and methods for storing data are described herein. The storage system may be integrated with or coupled with a compute cluster or super computer having multiple computing nodes. A plurality of nonvolatile memory units may be included with computing nodes, coupled with computing nodes or coupled with input/output nodes. The input/output nodes may be included with the compute cluster or super computer, or coupled thereto. The nonvolatile memory units store data items provided by the computing nodes, and the input/output nodes maintain where the data items are stored in the nonvolatile memory units via a hash table distributed among the input/output nodes. The use of a distributed hash table allows for quick access to data items stored in the nonvolatile memory units even as the computing nodes are writing large amounts of data to the storage system quickly in bursts. | 04-17-2014 |
20140108708 | RAID CONFIGURATION IN A FLASH MEMORY DATA STORAGE DEVICE - A method of storing data in a flash memory data storage device that includes a plurality of memory chips is disclosed. The method includes determining a number of memory chips in the data storage device, defining, via a host coupled to the data storage device, a first partition of the data storage device, where the first partition includes a first subset of the plurality of memory chips and defining a second partition of the data storage device via a host coupled to the data storage device, where the second partition includes a second subset of the plurality of memory chips. First data is written to the first partition while reading data from the second partition, and first data is written to the second partition while reading data from the first partition. | 04-17-2014 |
20140108709 | File Server Node with Non-Volatile Memory Processing Module Coupled to Cluster File Server Node - Apparatus includes a file server node having (i) a first interface operable to communicate with a network and receiving a network request via network, (ii) a non-volatile memory operable to temporarily store a request related to the network request received by the first interface, (iii) a second interface operable to be coupled to the storage device for storing the request, and (iv) a non-volatile memory processing module, coupled to the first interface, the non-volatile memory and the second interface, and operable to be coupled to another file server node, so that the request can be sent to the non-volatile memory, the second interface and the another file server node after the non-volatile memory processing module receives the file system request. | 04-17-2014 |
20140108710 | METHOD FOR ADJUSTING STORAGE SPACE OF PARTITION OF EMBEDDED MULTIMEDIA CARD AND TERMINAL - A method is provided for adjusting a storage space of a partition of an embedded multimedia card and a terminal. The method includes: determining a current external SD card mode of a terminal, where the external SD card mode includes an external SD card installed mode or an external SD card uninstalled mode; receiving instruction information, where the instruction information is used for instructing the terminal to switch from the external SD card uninstalled mode to the external SD card installed mode, or used for instructing the terminal to switch from the external SD card installed mode to the external SD card uninstalled mode; and adjusting a size of a storage space of a partition of an embedded multimedia card according to the instruction information. | 04-17-2014 |
20140108711 | PORTABLE SECURE DEVICE PROVIDING STORAGE SERVICE - A secure device includes a non volatile memory and a secure storage unit for a contactless reader. The storage unit manages logical sectors comprising a preset number of 16-byte data blocks and provides secured access to these data blocks. The unit is a software agent. The secure device comprises a microprocessor able to run the secure storage unit. The unit is adapted to ensure consistency of the data blocks and to ensure a preset number of writing into the data blocks without erasing operations. | 04-17-2014 |
20140108712 | PROGRAMMING MODE FOR MULTI-LAYER STORAGE FLASH MEMORY ARRAY AND SWITCHING CONTROL METHOD THEREOF - The present invention relates to a programming mode for improving the reliability of a multi-layer storage flash memory device in a semiconductor storage field. The present invention provides several programming modes for improving the reliability of a multi-layer storage flash memory device and switching control methods thereof, based on the technical conception of skipping some specific logic pages in the programming process to reduce the impact of the floating gate coupling effect on the operation of the flash memory. By skipping some logic pages, the present invention effectively reduces the floating gate coupling effect in the horizontal, diagonal and vertical directions of the multi-layer storage flash memory in the programming process. Therefore, the error rate is reduced, the service life of the device is prolonged, and the reliability of the whole system is enhanced. | 04-17-2014 |
20140108713 | STORAGE SYSTEM HAVING A PLURALITY OF FLASH PACKAGES - A storage system | 04-17-2014 |
20140108714 | APPARATUS AND METHOD FOR GENERATING DESCRIPTORS TO TRANSFER DATA TO AND FROM NON-VOLATILE SEMICONDUCTOR MEMORY OF A STORAGE DRIVE - A storage drive including first, second, third, fourth and fifth modules. The first module is configured to control transfer of blocks of data between a host device and the storage drive. The second module is configured to transfer the blocks of data to and from a non-volatile semiconductor memory in the storage drive. The third module is configured to generate a first descriptor, which describes a transfer of blocks of data between the second module and the non-volatile semiconductor memory. The fourth module is configured to, according to the first descriptor, generate second descriptors. Each of the second descriptors corresponds to a respective one of the blocks of data. The fifth module is configured to generate instruction signals based on the second descriptors. The second module is configured to, based on the instruction signals, transfer the blocks of data between the first module and the non-volatile semiconductor memory. | 04-17-2014 |
20140108715 | Flash Storage Controller Execute Loop - A storage controller is provided that contains multiple processors. In some embodiments, the storage controller is coupled to a flash memory module having multiple flash memory groups, each flash memory group corresponding to a distinct flash port in the storage controller, each flash port comprising an associated processor. Each processor handles a portion of one or more host commands, including reads and writes, allowing multiple parallel pipelines to handle one or more host commands simultaneously. | 04-17-2014 |
20140115229 | METHOD AND SYSTEM TO REDUCE SYSTEM BOOT LOADER DOWNLOAD TIME FOR SPI BASED FLASH MEMORIES - Method and system for providing increased frequency of flash memories compatible to Serial Peripheral Interface (SPI) bus protocol by delayed data capturing so that system boot loader down load time reduces for a given memory configuration. Methods and systems are provided for operating the memory at the device rated frequency. | 04-24-2014 |
20140115230 | Flash Memory with Data Retention Partition - A NAND flash memory chip includes a first partition that has smaller memory cells, with smaller charge storage elements, and a second partition that has larger memory cells, with larger charge storage elements, in the same memory array. Data is selected for storage in the first or second partition according to characteristics, or expected characteristics, of the data. | 04-24-2014 |
20140115231 | NAND MEMORY MANAGEMENT - Apparatus, systems, and methods manage NAND memory are described. In one embodiment, an apparatus comprises a memory controller logic to apply a binary parity check code to a binary string and convert the binary string to a ternary string. Other embodiments are also disclosed and claimed. | 04-24-2014 |
20140115232 | Metadata Journaling with Error Correction Redundancy - Method and apparatus for managing a memory, such as but not limited to a flash memory. In accordance with some embodiments, user data and associated metadata are stored in a memory. The metadata are arranged as a first sequence of snapshots of the metadata at different points in time during the operation of the memory, and a second sequence of intervening journals which reflect updates to the metadata from one snapshot to the next. Requested portions of the metadata are recovered from the memory using a selected snapshot in the first sequence and first and second journals in the second sequence. | 04-24-2014 |
20140115233 | Restoring Virtualized GCU State Information - Method and apparatus for managing a memory, such as but not limited to a flash memory. In accordance with some embodiments, initial state information is stored which identifies an actual state of a garbage collection unit (GCU) of a memory during a normal operational mode. During a restoration mode after a memory power cycle event, a virtualized state of the GCU is determined responsive to the initial state information and to data read from the GCU. The memory is transitioned from the restoration mode to the normal operational mode once the virtualized state for the GCU is determined. | 04-24-2014 |
20140115234 | MEMORY SYSTEM COMPRISING NONVOLATILE MEMORY DEVICE AND RELATED METHOD OF OPERATION - A method of programming a nonvolatile memory device comprises generating write data and metadata associated with the write data, generating a seed associated with the write data and scrambling the generated seed, randomizing the write data and the metadata using the scrambled seed, and programming the randomized write data, the randomized metadata, and the scrambled seed in the nonvolatile memory device. | 04-24-2014 |
20140115235 | CACHE CONTROL APPARATUS AND CACHE CONTROL METHOD - A cache control apparatus comprises a primary cache part, a secondary cache part for caching data destaged from the primary cache part, and a controller connected to the primary cache part and to the secondary cache part. The secondary cache part has a first storage part and a second storage part having a lifetime longer than that of the first storage part. The controller determines whether the data destaged from the primary cache part is to be stored in the first storage part or the second storage part in the secondary cache part, based on a use state indicating whether or not the data has been updated, and stores the data in the first storage part or the second storage part determined. | 04-24-2014 |
20140115236 | SERVER AND METHOD FOR MANAGING REDUNDANT ARRAY OF INDEPENDENT DISK CARDS - In a method for managing redundant array of independent disk (RAID) cards, physical layer (PHY) chips of the RAID card is detected by a serial port. Information of a malfunctioning PHY chip and a standby PHY chip is read and stored in a firmware of a flash erasable programmable read only memory (EPROM) of the RAID card. An address of the malfunctioning PHY chip is set as an address of the standby PHY chip, and a hard disk electronically connected to the malfunctioning PHY chip is connected to the standby PHY chip. A new serial attached small computer system interface (SAS) address is obtained by amending an original SAS address according to the number and address of the standby PHY chip, and a new firmware is created in the flash EPROM according to the new SAS address. | 04-24-2014 |
20140115237 | ENCODING PROGRAM DATA BASED ON DATA STORED IN MEMORY CELLS TO BE PROGRAMMED - A method of programming data in a nonvolatile memory device comprises receiving program data to be programmed in selected memory cells of the nonvolatile memory device, reading data from the selected memory cells, encoding the program data using at least one encoding scheme selected from among multiple encoding schemes according to a comparison of the program data and the read data, generating flag data including encoding information, and programming the encoded program data and the flag data in the selected memory cells. | 04-24-2014 |
20140115238 | STORAGE CONTROLLERS AND STORAGE CONTROL METHODS - According to various embodiments, a storage controller configured to control storage of data in a pre-determined area of a storage medium may be provided. The storage controller may include a memory configured to store a write pointer, a reclaim pointer, and a wrapped around pointer. The write pointer may indicate a location of the storage medium to write incoming data. The reclaim pointer may indicate a location of the storage medium to perform a space reclamation. The wrapped around pointer may indicate a location of the storage medium where writing is to continue if writing of data reaches an end of the pre-determined area. | 04-24-2014 |
20140115239 | METHOD OF MANAGING DATA IN NONVOLATILE MEMORY DEVICE - A method of managing data in a nonvolatile memory device. The method includes providing a nonvolatile memory device having a hot region and a cold region. The hot region includes first through n-th blocks. Input pages having metadata are received from a host. The input pages are sequentially written to the first through n-th blocks. Valid pages are identified from the input pages written to the first block after the n-th block is written. The valid pages are written to the cold region. | 04-24-2014 |
20140115240 | STORAGE DEVICES AND METHODS FOR CONTROLLING A STORAGE DEVICE - According to various embodiments, a storage device may be provided. The storage device may include: a first memory including a magnetic recording medium and configured to store user data; a second memory including a solid state drive recording medium and configured to store at least one of metadata or other frequently accessed data; and an interface configured to access the second memory using a pre-determined communication protocol. | 04-24-2014 |
20140115241 | BUFFER MANAGEMENT APPARATUS AND METHOD - A buffer management apparatus ( | 04-24-2014 |
20140115242 | SYSTEMS AND METHODS FOR HANDLING NON-VOLATILE MEMORY OPERATING AT A SUBSTANTIALLY FULL CAPACITY - This can relate to handling a non-volatile memory (“NVM”) operating at a substantially full memory. The non-volatile memory can report its physical capacity to an NVM driver. The NVM driver can scale-up the physical capacity a particular number of times to generate a “scaled physical capacity,” which is then reported to the file system. Because the scaled physical capacity is greater than the NVM's actual physical capacity, the file system allocates a logical space to the NVM that is substantially greater than the NVM's capacity. This can cause less crowding of the logical block addresses within the logical space, thus making it easier for the file system to operate and improving system performance. A commitment budget can also be reported to the file system that corresponds to the NVM's physical capacity, and which can define the amount of data the file system can commit for storage in the NVM. | 04-24-2014 |
20140122773 | PARTIAL PAGE MEMORY OPERATIONS - Apparatuses may include a memory block with strings of memory cells formed in a plurality of tiers. The apparatus may further comprise access lines and data lines shared by the strings, with the access lines coupled to the memory cells corresponding to a respective tier of the plurality of tiers. The memory cells corresponding to at least a portion of the respective tier may comprise a respective page of a plurality of pages. Subsets of the data lines may be mapped into a respective partial page of a plurality of partial pages of the respective page. Each partial page may be independently selectable from other partial pages. Additional apparatuses and methods are disclosed. | 05-01-2014 |
20140122774 | Method for Managing Data of Solid State Storage with Data Attributes - Different FTL implementations, including the use of different mapping schemes, log block utilization, merging, and garbage collection strategies, perform more optimally than others for different data operations with certain characteristics. The presently claimed invention provides a method to distinguish and categorize the different data operations according to their different characteristics, or data attributes; then deploy the most optimal mapping schemes, log block utilization, merging, and garbage collection strategies depending on the data attributes; wherein the data attributes include, but are not limited to, access frequency, access sequence, access size, request mode, and request write ratio. | 05-01-2014 |
20140122775 | MEMORY CONTROLLER FOR MEMORY DEVICE - A memory controller that generates interface signals for a memory device determines an interface signal frequency based on a timing mode of the memory device and a corresponding clock division ratio. Based on the timing mode, a look up table (LUT) is selected and then a timing parameter corresponding to the clock division ratio and the interface signal frequency is fetched from the LUT. An interface signal is generated based on the interface signal frequency and fetched timing parameter. | 05-01-2014 |
20140122776 | DYNAMIC TUNING OF INTERNAL PARAMETERS FOR SOLID-STATE DISK BASED ON WORKLOAD ACCESS PATTERNS - A system and method for tuning a solid state disk memory includes computing a metric representing a usage trend of a solid state disk memory. Whether one or more parameters need to be adjusted to provide a change in performance is determined. The parameter is adjusted in accordance with the metric to impact the performance of running workloads. These steps are repeated after an elapsed time interval. | 05-01-2014 |
20140122777 | FLASH MEMORY CONTROLLER HAVING MULTI MODE PIN-OUT - A memory controller of a data storage device which communicates with a host, has channel control modules each being configurable to have at three different pinout assignments for interfacing with two different types of memory devices operating with different memory interface protocols. One pinout assignment corresponds to a memory interface protocol where memory devices can be connected in parallel with each other. Two other pinout assignments correspond respectively to inbound and outbound signals of another memory interface protocol where memory devices are serially connected with each other. In this mode of operation, one channel control module is configured to provide the outbound signals while another channel control module is configured to receive the inbound signals. Each memory port of the channel control modules includes port buffer circuitry configurable for different functional signal assignments. The configuration of each channel control module is selectable by setting predetermined ports or registers. | 05-01-2014 |
20140122778 | RAPID NETWORK DATA STORAGE TIERING SYSTEM AND METHODS - Systems and methods are disclosed herein to a data storage tiering system comprising at least one storage array; at least one solid state storage unit; and a storage controller in communication with the at least one storage array and the at least one solid state storage unit and configured to combine the at least one storage array and the at least one solid state storage unit into one business tier data container using a virtualization layer and present the business tier data container on a storage area network as one storage array to a server, wherein the storage controller creates a business data tier by combining a partition of the solid state storage unit with the at least one storage array. | 05-01-2014 |
20140122779 | MAGNETIC RANDOM ACCESS MEMORY JOURNAL FOR MULTI-LEVEL CELL FLASH MEMORY - A flash memory system comprises a logic block interface operable to receive a write command from a host computer, the write command specifying data and a write destination address in a flash memory device, the flash memory device operable to store data at a complementary address corresponding to the specified write destination address. The system further comprises a journal communicatively coupled to the flash memory device and the logic block interface operable to temporarily store data from the complementary address of the flash memory device, and to provide the stored data in the journal to be restored to the flash memory device at the complementary address in the event of an error occurring while executing the write command. | 05-01-2014 |
20140122780 | MAGNETIC RANDOM ACCESS MEMORY JOURNAL - A flash memory system comprises a logic block interface operable to receive a write command to store data from a host computer, a flash memory device operable to store the data in response to the write command, and a non-volatile memory communicatively coupled to the flash memory device and the logic block interface operable to temporarily store the data, and to provide the stored data to be written to the flash memory device in the event of a disruption during execution of the write command. | 05-01-2014 |
20140122781 | HIERARCHICAL FLASH TRANSLATION LAYER - A flash memory system comprises a flash device operable to store data in a plurality of physical blocks assigned to a plurality of sections, a plurality of Flash Translation Tables stored in a memory comprising a Forward Translation Table that maps a Section to a plurality of physical blocks, and a Sector Translation Table for each Section, the Sector Translation Table operable to map to a Physical Page Number identifying a particular Page, a Page Offset identifying a particular location within the Page, and a Section Local Block Table comprising Block Physical Addresses indexed by a Section Local Block Table ID. | 05-01-2014 |
20140122782 | MEMORY SYSTEM - A memory system includes a first, second and third storing area included in a volatile semiconductor memory, and a controller that allocates the storage area of the nonvolatile semiconductor memory to the second storing area and the third storing area in a logical block unit associated with one or more blocks. First and second management units respectively manage the second and third storing areas. The second management unit has a size larger than that of the first management unit. When flushing data from the first to the second or third storing areas, the controller collects, from at least one of the first, second and third storing areas, data other than the data to be flushed and controls the flushing of the data such that a total of the data is a natural number times as large as the block unit as much as possible. | 05-01-2014 |
20140122783 | SOLID STATE MEMORY (SSM), COMPUTER SYSTEM INCLUDING AN SSM, AND METHOD OF OPERATING AN SSM - In one aspect, data is stored in a solid state memory which includes first and second memory layers. A first assessment is executed to determine whether received data is hot data or cold data. Received data which is assessed as hot data during the first assessment is stored in the first memory layer, and received data which is first assessed as cold data during the first assessment is stored in the second memory layer. Further, a second assessment is executed to determine whether the data stored in the first memory layer is hot data or cold data. Data which is then assessed as cold data during the second assessment is migrated from the first memory layer to the second memory layer. | 05-01-2014 |
20140122784 | SOLID-STATE DISK, AND USER SYSTEM COMPRISING SAME - The inventive concept relates to a user system including a solid state disk. The user system may include a main memory for storing data processed by a central processing unit; and a solid state disk for storing the selected data among data stored in the main memory. The main memory and the solid state disk form a single memory hierarchy. Thus, the user system of the inventive concept can rapidly process data. | 05-01-2014 |
20140122785 | DATA WRITING METHOD AND SYSTEM - A data writing method for writing data to a flash memory includes writing an initial value to the data storage area, determining whether or not the writing of the initial value is performed normally based on a write flag, writing data to the data storage area when the writing is performed normally, and erasing a block including the data storage area when the writing is not performed normally. An initial value is written to the data storage area before writing data, so that whether or not an error correction code storage area contains the initial value may be confirmed. An erase operation of the block is performed only when the error correction code storage area does not contain the initial value, so that the number of times of erasure of the block may be reduced and the life of the product may be increased. | 05-01-2014 |
20140122786 | FLASH MEMORY CONTROLLER - In some implementations, an apparatus includes a first programmable hardware timer that specifies an initial wait time before issuing two or more commands to a storage device, and a second programmable hardware timer that specifies an interval time between at least two commands of the two or more commands. | 05-01-2014 |
20140122787 | ADAPTIVE OVER-PROVISIONING IN MEMORY SYSTEMS - A method for data storage includes, in a memory that includes multiple memory blocks, specifying at a first time a first over-provisioning overhead, and storing data in the memory while retaining in the memory blocks memory areas, which do not hold valid data and whose aggregated size is at least commensurate with the specified first over-provisioning overhead. Portions of the data from one or more previously-programmed memory blocks containing one or more of the retained memory areas are compacted. At a second time subsequent to the first time, a second over-provisioning overhead, different from the first over-provisioning overhead, is specified, and data storage and data portion compaction is continued while complying with the second over-provisioning overhead. | 05-01-2014 |
20140122788 | REFRESH ALGORITHM FOR MEMORIES - A method and apparatus for refreshing data in a flash memory device is disclosed. A counter is maintained for each memory block. When a memory block is erased, the counter for that erase block is set to a predetermined value while the remaining counters for other erase blocks are changed. When a memory block counter reaches a predetermined threshold value, the associated memory block is refreshed. | 05-01-2014 |
20140129757 | SYSTEM AND METHOD FOR DYNAMIC MEMORY POWER MANAGEMENT - Various embodiments of methods and systems for hardware (“HW”) based dynamic memory management in a portable computing device (“PCD”) are disclosed. One exemplary method includes generating a lookup table (“LUT”) to track each memory page located across multiple portions of a volatile memory. The records in the LUT are updated to keep track of data locations. When the PCD enters a sleep state to conserve energy, the LUT may be queried to determine which specific memory pages in a first portion of volatile memory (e.g., an upper bank) contain data content and which pages in a second portion of volatile memory (e.g., a lower bank) are available for receipt of content. Based on the query, the location of the data in the memory pages of the upper bank is known and can be quickly migrated to memory pages in the lower bank which are identified for receipt of the data. | 05-08-2014 |
20140129758 | WEAR LEVELING IN FLASH MEMORY DEVICES WITH TRIM COMMANDS - Systems and methods are provided to implement a memory device that includes a memory array having a plurality of sectors, a non-volatile memory that stores sector state information, and a memory controller that performs wear leveling according to the sector state information. The sector state information can specify respective states for respective sectors of the plurality of sectors of the memory array. The memory controller, based on the states of respective sectors, determines whether or not to swap contents of the sectors during wear leveling, thereby reducing write amplification effects. | 05-08-2014 |
20140129759 | LOW POWER WRITE JOURNALING STORAGE SYSTEM - A low power write journaling storage system may be part of an information handling system that includes a system processor and a system memory that is coupled to the system processor. The low power write journaling storage system is coupled to the system processor and includes a non-volatile solid state memory system. A first processing element in the low power write journaling storage system is operable, while the storage system is in a storage system first mode, to journal write commands in the non-volatile solid state memory system. A second processing element in the low power write journaling storage system is operable, while the storage system is in a storage system second mode that may cause the low power write journaling storage system to consume more power than when in the storage system first mode, to execute the write commands journaled in the non-volatile solid state memory system. | 05-08-2014 |
20140129760 | NON-VOLATILE MEMORY SYSTEM AND HOST CONFIGURED TO COMMUNICATE WITH THE SAME - A nonvolatile memory system includes a memory controller for copying a mapping data group including logical-physical address mapping information regarding user data from a nonvolatile memory to a mapping information storage unit, and transmit size information regarding the mapping data group to a host. The host may receive size information regarding the mapping data group from the nonvolatile memory system, and determine the order of commands to be transmitted to the nonvolatile memory based on the size information regarding the mapping data group. | 05-08-2014 |
20140129761 | NON-VOLATILE MEMORY DEVICE AND HOST DEVICE CONFIGURED TO COMMUNICATION WITH THE SAME - A non-volatile memory device and a non-volatile memory host device are configured to communicate with the non-volatile memory device. The speed at which the non-volatile memory device responds to a request for accessing user data from the host device may be increased. The non-volatile memory device may transmit logical-physical address mapping information regarding user data to the host device and may receive a request and logical-physical address mapping information from the host device. The host device may receive and store the logical-physical address mapping information from the non-volatile memory device and may transmit the request for accessing the user data and stored mapping information to the non-volatile memory device. | 05-08-2014 |
20140129762 | SKEWING EXPECTED WEAROUT TIMES OF MEMORY DEVICES - Aspects of the present invention include a system, method, and computer program product for skewing expected wearout times of memory devices in an array are provided according to some embodiments of the present invention. In general, the method includes determining or receiving an amount of spare space to provide in an array of memory devices, allocating the spare space non-uniformly to the memory devices in the array, and skewing expected wearout times of the memory devices by controlling writing of data to the array according to the allocation of the spare space. | 05-08-2014 |
20140129763 | DATA WRITING METHOD, MEMORY CONTROLLER, AND MEMORY STORAGE APPARATUS - A method for writing updated data into a flash memory module having a plurality of physical pages is provided, wherein each physical page is the smallest writing unit of the flash memory module. The method includes partitioning a physical page into storage segments and configuring a state mark for each storage segment, wherein the state marks indicate the validity of data stored in the storage segments. The method also includes writing the updated data into at least one of the storage segments and changing the state mark corresponding to the storage segment containing the updated data, wherein the state mark corresponding to the storage segment containing the updated data indicates a valid state, and the state marks corresponding to the other storage segments of the physical page not containing the updated data indicate an invalid state. Thereby, the time for writing data into a physical page is effectively shortened. | 05-08-2014 |
20140129764 | ALLOCATION STRUCTURE FOR FLASH MEMORY DEVICE - An allocation structure is used for a flash memory device. The flash memory device includes a first memory module and a second memory module. The first memory module and the second memory module respectively have a plurality of groups, and each of the groups of the first memory module has a plurality of physical blocks of the first memory module and each of the groups of the second memory module has a plurality of physical blocks of the second memory module. The allocation structure includes a first zone. The first zone is used to store a first allocation unit, and is formed by a first group of the groups of the first memory module and a first part of a second group of the groups of the second memory module. | 05-08-2014 |
20140136753 | METHODS, DATA STORAGE DEVICES AND SYSTEMS FOR FRAGMENTED FIRMWARE TABLE REBUILD IN A SOLID STATE DRIVE - A data storage device comprises a plurality of non-volatile memory devices configured to store a plurality of physical pages; a controller coupled to the plurality of memory devices that is configured to program data to and read data from the plurality of memory devices. A volatile memory may be coupled to the controller and may be configured to store a firmware table comprising a plurality of firmware table entries. The controller may be configured to maintain a plurality of firmware journals in the non-volatile memory devices. Each of the firmware journals may be associated with a firmware table entry and may comprise firmware table entry information. The controller may be configured to read the plurality of firmware journals upon startup and rebuild the firmware table using the firmware table entry information in each of the read plurality of firmware journals. | 05-15-2014 |
20140136754 | INTELLIGENT MONITORING FOR COMPUTATION IN MEMORY - A memory device can include a non-volatile memory array and control logic integrated with and distributed over the non-volatile memory array. The control logic can be operable to selectively distribute functionality across the non-volatile memory array. | 05-15-2014 |
20140136755 | FLEXIBLE PROCESSORS AND FLEXIBLE MEMORY - An apparatus includes but is not limited to a non-volatile memory array and a processor integrated with the apparatus. The processor is operable to operate in combination with the non-volatile memory array to accumulate information associated with a product. In addition to the foregoing, other aspects are described in the claims, drawings, and text forming a part of the present disclosure. | 05-15-2014 |
20140136756 | NAND Flash Based Content Addressable Memory - A NAND Flash based content addressable memory (CAM) is used for a key-value addressed storage drive. The device can use a standard transport protocol such as PCI-E, SAS, SATA, eMMC, SCSI, and so on. A host writes a key-value pair to the drive, where the drive writes the keys along bit lines of a CAM NAND portion of the drive and stores the value in the drive. The drive then maintains a table linking the keys to location of the value. In a read process, the host provides a key to drive, which then broadcasts down the word lines of blocks storing the keys. Based on any matching bit lines, the tables can then be used to retrieve and supply the corresponding data to the host. | 05-15-2014 |
20140136757 | NAND Flash Based Content Addressable Memory - A NAND Flash based content addressable memory (CAM) is used for a key-value addressed storage drive. The device can use a standard transport protocol such as PCI-E, SAS, SATA, eMMC, SCSI, and so on. A host writes a key-value pair to the drive, where the drive writes the keys along bit lines of a CAM NAND portion of the drive and stores the value in the drive. The drive then maintains a table linking the keys to location of the value. In a read process, the host provides a key to drive, which then broadcasts down the word lines of blocks storing the keys. Based on any matching bit lines, the tables can then be used to retrieve and supply the corresponding data to the host. | 05-15-2014 |
20140136758 | Key Value Addressed Storage Drive Using NAND Flash Based Content Addressable Memory - A NAND Flash based content addressable memory (CAM) is used for a key-value addressed storage drive. The device can use a standard transport protocol such as PCI-E, SAS, SATA, eMMC, SCSI, and so on. A host writes a key-value pair to the drive, where the drive writes the keys along bit lines of a CAM NAND portion of the drive and stores the value in the drive. The drive then maintains a table linking the keys to location of the value. In a read process, the host provides a key to drive, which then broadcasts down the word lines of blocks storing the keys. Based on any matching bit lines, the tables can then be used to retrieve and supply the corresponding data to the host. | 05-15-2014 |
20140136759 | DE-DUPLICATION TECHNIQUES USING NAND FLASH BASED CONTENT ADDRESSABLE MEMORY - A NAND Flash based content addressable memory (CAM) is used for a key-value addressed storage drive. The device can use a standard transport protocol such as PCI-E, SAS, SATA, eMMC, SCSI, and so on. A host writes a key-value pair to the drive, where the drive writes the keys along bit lines of a CAM NAND portion of the drive and stores the value in the drive. The drive then maintains a table linking the keys to location of the value. In a read process, the host provides a key to drive, which then broadcasts down the word lines of blocks storing the keys. Based on any matching bit lines, the tables can then be used to retrieve and supply the corresponding data to the host. This arrangement can be applied to de-duplication: for data sets stored in a primary data storage section, corresponding data keys can be generated and store in search NAND. A received key, rather from external to the system or internally generated, can then be compared against the search NAND. The system can be applied to both in-line and off-line de-duplication. | 05-15-2014 |
20140136760 | DE-DUPLICATION SYSTEM USING NAND FLASH BASED CONTENT ADDRESSABLE MEMORY - A NAND Flash based content addressable memory (CAM) is used for a key-value addressed storage drive. The device can use a standard transport protocol such as PCI-E, SAS, SATA, eMMC, SCSI, and so on. A host writes a key-value pair to the drive, where the drive writes the keys along bit lines of a CAM NAND portion of the drive and stores the value in the drive. The drive then maintains a table linking the keys to location of the value. In a read process, the host provides a key to drive, which then broadcasts down the word lines of blocks storing the keys. Based on any matching bit lines, the tables can then be used to retrieve and supply the corresponding data to the host. This arrangement can be applied to de-duplication: for data sets stored in a primary data storage section, corresponding data keys can be generated and store in search NAND. A received key, rather from external to the system or internally generated, can then be compared against the search NAND. The system can be applied to both in-line and off-line de-duplication. | 05-15-2014 |
20140136761 | ARCHITECTURES FOR DATA ANALYTICS USING COMPUTATIONAL NAND MEMORY - A data analytic system allows for analytic operations be moved from a server on to a solid state drive (SSD) type analytic system, where a CAM NAND structure can be used in the analytic operations. The server can run a software using database language can issue command to the analytic system. On the data analytic system (that can interface with common, existing database language), the software commands are translated into firmware language and broken down into multiple small tasks. The small tasks are executed on the SSD flash controllers or on NAND flash according to the task specifications. The mid-product from the NAND flash or the SSD controllers can be merged within each SSD blade and also further merged on the top server level. | 05-15-2014 |
20140136762 | DATA SEARCH USING BLOOM FILTERS AND NAND BASED CONTENT ADDRESSABLE MEMORY - A NAND Flash based content addressable memory (CAM) is used for a key-value addressed storage drive. A host writes a key-value pair to the drive, where the drive writes the keys along bit lines of a CAM NAND portion of the drive and stores the value in the drive. The drive then maintains a table linking the keys to location of the value. In a read process, the host provides a key to drive, which then broadcasts down the word lines of blocks storing the keys. Based on any matching bit lines, the tables can then be used to retrieve and supply the corresponding data to the host. This arrangement can be applied to data search operations using bloom filters stored along bit lines of search matrix, where the search matrix can extend across large numbers of arrays. In the example of an internet search, the bloom filters are formed from key words associated with a website are stored along bit lines of the matrix and corresponding URLs are stored in primary storage. In response to search word based query, any matching URLs are returned. | 05-15-2014 |
20140136763 | CAM NAND with OR Function and Full Chip Search Capability - Various techniques for extending the capabilities of CAM NAND type memories are discussed. Multi-block or even full chip search operations can be performed. In addition to the inherent AND property of NAND strings, the memory array has an inherent OR property between NAND string from different blocks along the same bit line that can be exploited through multi-block CAM-type operations. To reduce data-dependent word line to word line effects, in multiple data dependent sensing operations, the sensing can be broken up into sub-operations that avoid data dependent values on adjacent word lines. To improve data protection, subsequent to writing a memory block with indices, the word lines are read back and compared bit-by-bit with their intended values and the results are accumulated to determine whether any of indices include error. A bloom filter can also be used as an initial check during data search operations in order to provide increased data protection. | 05-15-2014 |
20140136764 | USE OF BLOOM FILTER AND IMPROVED PROGRAM ALGORITHM FOR INCREASED DATA PROTECTION IN CAM NAND MEMORY - Various techniques for extending the capabilities of CAM NAND type memories are discussed. Multi-block or even full chip search operations can be performed. In addition to the inherent AND property of NAND strings, the memory array has an inherent OR property between NAND string from different blocks along the same bit line that can be exploited through multi-block CAM-type operations. To reduce data-dependent word line to word line effects, in multiple data dependent sensing operations, the sensing can be broken up into sub-operations that avoid data dependent values on adjacent word lines. To improve data protection, subsequent to writing a memory block with indices, the word lines are read back and compared bit-by-bit with their intended values and the results are accumulated to determine whether any of indices include error. A bloom filter can also be used as an initial check during data search operations in order to provide increased data protection. | 05-15-2014 |
20140136765 | MEMORY SYSTEM COMPRISING NONVOLATILE MEMORY DEVICE AND RELATED READ METHOD - A method of operating a nonvolatile memory device configured to erase a memory block in sub-block units comprises detecting state information of unselected sub-blocks associated with a selected sub-block comprising selected memory cells, adjusting a read bias of the selected memory cells based on the state information, and reading data from the selected memory cells according to the adjusted read bias. The state information indicates a number of the unselected sub-blocks having a programmed state or an erased state. | 05-15-2014 |
20140136766 | CACHE DEVICE FOR HARD DISK DRIVES AND METHODS OF OPERATION - A solid-state mass storage device adapted to be used as a cache for an hard disk drive that utilizes a more efficient logical data management method relative to conventional systems. The storage device includes a circuit board, a memory controller, at least one non-volatile memory device, and at least two data interfaces. The storage device is coupled to a host computer system and configured to operate as a cache for at least one hard disk drive. The storage device is interposed between the host computer system and the at least one hard disk drive. Both the storage device and the at least one hard disk drive are coupled to the host computer system through a single connection and configured to operate in a daisy chain configuration. | 05-15-2014 |
20140136767 | MEMORY SYSTEM HAVING MEMORY CONTROLLER WITH CACHE MEMORY AND NVRAM AND METHOD OF OPERATING SAME - In a memory system including a flash memory and a memory controller having a cache memory and a nonvolatile random access memory (NVRAM), a method of operating the memory system includes; receiving a write request specifying a write operation directed to a page of a designated active write block in the flash memory, storing a page mapping table for the active write block in the cache memory, generating update information for the page mapping table stored in the cache memory as a result of executing the write operation, and storing the update information in the NVRAM, and storing an updated version of the page mapping table in the flash memory after execution of the write operation is complete. | 05-15-2014 |
20140136768 | APPARATUS, METHOD AND SYSTEM FOR USING SHADOW DRIVES FOR ALTERNATIVE DRIVE COMMANDS - A storage processor is configured to identify a first disk drive and a second shadow drive associated with the first disk drive to an initiator. The storage processor receives storage commands from an initiator. When the storage commands access the first disk drive, the storage processor issues a first storage operation to the first disk drive. When the storage commands access the second shadow drive, the storage processor issues different storage operations to the first disk drive that are not supported by the initiator. | 05-15-2014 |
20140136769 | SOLID-STATE STORAGE MANAGEMENT - Solid-state storage management for a system, the management including establishing, externally to a solid-state storage board, a correspondence between a first logical address and a first physical address on solid-state storage devices located on the solid-state storage board. The solid-state storage devices include a plurality of physical memory locations identified by physical addresses. The correspondence between the first logical address and the first physical address is accepted by the solid-state storage board. The correspondence between the first logical address and the first physical address is stored in a location on a solid-state memory device that is accessible by an address translator module, the address translator module and the solid-state memory device located on the solid-state storage board. The first logical address is translated to the first physical address by the address translator module based on the previously established correspondence between the first logical address and the first physical address. | 05-15-2014 |
20140136770 | LOW LATENCY AND PERSISTENT DATA STORAGE - Persistent data storage with low latency is provided by a computer program product that includes computer program code configured for receiving a low latency store command that includes write data. The write data is written to a first memory device that is implemented by a nonvolatile solid-state memory technology characterized by a first access speed. It is acknowledged that the write data has been successfully written to the first memory device. The write data is written to a second memory device that is implemented by a volatile memory technology. At least a portion of the data in the first memory device is written to a third memory device when a predetermined amount of data has been accumulated in the first memory device. The third memory device is implemented by a nonvolatile solid-state memory technology characterized by a second access speed that is slower than the first access speed. | 05-15-2014 |
20140136771 | Initiating Memory Wear Leveling - Systems and processes may use a host and an external host. The host may be a portable device that includes a memory, a memory controller, and a communication interface for communication with the external host. The portable device may receive a command signal from the external host and initiate a predetermined amount of wear leveling in response to the command signal. | 05-15-2014 |
20140136772 | MEMORY SYSTEM - According to one embodiment, a memory system includes a nonvolatile semiconductor memory include a first area, and a second area smaller than the first area; and a controller configured to control data stored in the nonvolatile semiconductor memory, wherein the nonvolatile semiconductor memory is configured to store a first data accessible by a host command and to a second data inaccessible by the host command, and when receiving the host command, the controller writes the second data of the first area within the second area and initializes a first address information related the first data. | 05-15-2014 |
20140143473 | DATA REFRESH IN NON-VOLATILE MEMORY - A method of reducing read errors in a non-volatile memory device that result from bit-line or word-line disturb conditions generated by erase operations includes selecting a subset of a memory array for refresh after each erase operation. A pointer to the refresh target section is updated as part of the method to direct the refresh operation to the appropriate subset of the memory array. Refresh may be performed subsequent to an erase operation or concurrently therewith. By distributing the time consumed by refresh operations over many erase operations so the relative refresh time for any one erase becomes small. | 05-22-2014 |
20140143474 | FLEXIBLE WEAR MANAGEMENT FOR NON-VOLATILE MEMORY - Systems and methods of memory cell wear management that can achieve a more uniform distribution of write cycles across a memory cell address space. The systems and methods allow physical addresses of memory cells subjected to a high number of write cycles to be swapped with physical addresses of memory cells subjected to a lower number of write cycles. The physical address of a group of memory cells is a “hot address” if the write cycle count for that memory cell group exceeds a specified threshold. If the write cycle count for a group of memory cells does not exceed the specified threshold, then the physical address of that memory cell group is a “cold address”. The systems and methods allow the specified threshold of write cycle counts to be dynamically incremented to assure that cold addresses are available for swapping with hot addresses in the memory cell address space. | 05-22-2014 |
20140143475 | Fast Secure Erasure Schemes for Non-Volatile Memory - A method includes, in a memory with multiple analog memory cells, storing one or more data pages in respective groups of the memory cells using a first programming configuration having a first storage speed. Upon receiving a request to securely erase a data page from the memory, one or more of the memory cells in a group that stores the data page are re-programmed using a second programming configuration having a second storage speed that is faster than the first storage speed. | 05-22-2014 |
20140143476 | USAGE OF CACHE AND WRITE TRANSACTION INFORMATION IN A STORAGE DEVICE - A method and system are disclosed for tracking write transactions in a manner to prevent corruption of file system during interruptions such as power failures between write commands. The method includes the storage device tracking transaction identifiers for write commands and delaying the update of a main memory logical-to-physical map until all of the write commands for a particular transaction have been received based on the transaction ID information. The system includes a storage device having a flash memory with a main logical-to-physical mapping data structure and a controller configured to track individual write commands of a write transaction and store data from those commands without updating the main logical-to-physical mapping data structure until all of the data for the write transaction has been received. | 05-22-2014 |
20140143477 | COMPUTER SYSTEM AND DATA RECOVERY METHOD THEREOF - A computer system and a data recovery method are provided. The computer system includes an embedded controller (EC). The data recovery method includes following steps. When the computer system stores data into the EC through a basic input/output system (BIOS), the data is backed up into a non-volatile random access memory (NVRAM) by the BIOS. The EC enters a power-off mode. The data is obtained from the NVRAM and is stored back to the EC after the EC leaves the power-off mode. Accordingly, the EC recovers from the power-off mode. | 05-22-2014 |
20140143478 | SEMICONDUCTOR MEMORY DEVICE AND COMPUTER SYSTEM INCLUDING THE SAME - A semiconductor memory device includes a first memory block of a first type of memory; and a second memory block of a second type of memory having a different type from the first type. A first address region of the first memory block and a second address region of the second memory block are included in the same address domain. Each of the first and second memory blocks is accessed by an address signal including an address of the address domain, and the second memory block is a nonvolatile memory. | 05-22-2014 |
20140143479 | TEMPORARY MIRRORING, LOGICAL SEGREGATION, AND REDUNDANT PROGRAMMING OR ADDRESSING FOR SOLID STATE DRIVE OPERATION - The present disclosure includes methods and devices for operating a solid state drive. One method embodiment includes mirroring programming operations such that data associated with a programming operation is programmed to two or more locations in memory of the solid state drive. The method also includes ceasing to mirror programming operations upon an occurrence of a particular event. | 05-22-2014 |
20140143480 | MANAGEMENT OF MEMORY ARRAY WITH MAGNETIC RANDOM ACCESS MEMORY (MRAM) - An embodiment of the invention includes a mass storage device with a storage media that includes magnetic random access memory (MRAM) devices with a NAND flash interface and NAND flash memory devices that are coupled to the MRAM devices. The storage media is partitioned into a hybrid reserved area made of a combination of MRAM array NAND array and hybrid user area made of a combination of MRAM array and NAND array and further includes a controller with a host interface and flash interface coupled to the MRAM and NAND flash memory devices through a flash interface. | 05-22-2014 |
20140143481 | MANAGEMENT OF MEMORY ARRAY WITH MAGNETIC RANDOM ACCESS MEMORY (MRAM) - An embodiment of the invention includes a mass storage device with a storage media that includes magnetic random access memory (MRAM) devices with a NAND flash interface and NAND flash memory devices that are coupled to the MRAM devices. The storage media is partitioned into a hybrid reserved area made of a combination of MRAM array NAND array and hybrid user area made of a combination of MRAM array and NAND array and further includes a controller with a host interface and flash interface coupled to the MRAM and NAND flash memory devices through a flash interface. | 05-22-2014 |
20140143482 | MEMORY MANAGEMENT SCHEMES FOR NON-VOLATILE MEMORY DEVICES - A method includes storing data in a non-volatile memory that includes multiple memory blocks. At least first and second regions are defined in the non-volatile memory. A definition is made of a first over-provisioning ratio between a first logical address space and a first physical memory space of the first region, and a second over-provisioning ratio, different from the first over-provisioning ratio, between a second logical address space and a second physical memory space of the second region. Portions of the data are compacted, individually within each of the first and second regions and independently of the other region, by copying the portions from one or more source memory blocks to one or more destination memory blocks using the first and second over-provisioning ratios, respectively. | 05-22-2014 |
20140143483 | MEMORY MANAGEMENT SCHEMES FOR NON-VOLATILE MEMORY DEVICES - A method includes storing data in a non-volatile memory that includes multiple memory blocks. At least first and second regions are defined in the non-volatile memory. A definition is made of a first over-provisioning ratio between a first logical address space and a first physical memory space of the first region, and a second over-provisioning ratio, different from the first over-provisioning ratio, between a second logical address space and a second physical memory space of the second region. Portions of the data are compacted, individually within each of the first and second regions and independently of the other region, by copying the portions from one or more source memory blocks to one or more destination memory blocks using the first and second over-provisioning ratios, respectively. | 05-22-2014 |
20140143484 | STAGGERED PROGRAMMING FOR RESISTIVE MEMORIES - Subject matter disclosed herein relates to a memory device and method of programming same. | 05-22-2014 |
20140149637 | METHOD AND SYSTEM FOR PERFORMING DATA TRANSFER WITH A FLASH STORAGE MEDIUM - This invention discloses a method for data transfer between a host memory and a flash memory module through direct memory access (DMA), and a related data-transfer subsystem. In one embodiment, the subsystem comprises a DMA controller, a flash-memory controller, a data buffer for buffering data transferred between the DMA controller and the flash-memory controller, and a status-register group for storing a current status of the data buffer. The DMA controller and the flash-memory controller are configured such that both of them are allowed to update the current status and to detect a change of the current status during the data transfer, so that a substantial part of the data transfer's process is executed through direct interaction between the DMA controller and the flash-memory controller without involving a central processing unit. The subsystem may further comprise a command storing unit for storing command packages for execution by the flash-memory controller. | 05-29-2014 |
20140149638 | SYSTEM AND METHOD FOR PROVIDING A FLASH MEMORY CACHE INPUT/OUTPUT THROTTLING MECHANISM BASED UPON TEMPERATURE PARAMETERS FOR PROMOTING IMPROVED FLASH LIFE - Aspects of the disclosure pertain to a system and method for providing a flash memory cache input/output throttling mechanism based upon temperature parameters for promoting improved flash life. The mechanism restricts flash memory cache caching of inputs/outputs associated with Least Recently Used data and Most Recently Used data when a temperature of the flash memory is at or above a threshold temperature. | 05-29-2014 |
20140149639 | CODING TECHNIQUES FOR REDUCING WRITE CYCLES FOR MEMORY - Structures and methods for encoding data to reduce write cycles in a semiconductor memory device are disclosed herein. In one embodiment, a method of writing data to a semiconductor memory device can include: (i) determining a number of significant bits for data to be written in the semiconductor memory device; (ii) determining a tag associated with the data to be written in the semiconductor memory device, where the tag is determined based on the determined number of significant bits; (iii) encoding the data when the tag has a first state, where the tag is configured to indicate data encoding that comprises using N bits of the encoded data to store M bits of the data, where M and N are both positive integers and N is greater than M; and (iv) writing the encoded data and the tag in the semiconductor memory device. | 05-29-2014 |
20140149640 | Adaptive Power Control of Memory Map Storage Devices - An apparatus includes a storage resource to store data. The data can be accessible by a host computer system. The apparatus includes a set of dynamically powered volatile memory devices that are configured to store mapping information. The mapping information maps logical addresses of received access requests to corresponding physical addresses of the storage resource to which the access requests pertain. In accordance with received mode setting information, the controller logic adaptively controls power settings of the volatile memory devices storing the mapping information. If an abundance of power such as 120 VAC power is available, more of volatile memory devices can be powered to store a greater portion of the mapping information. If only battery power is available, fewer than all of the volatile memory devices can be powered to store a smaller portion of the mapping information. | 05-29-2014 |
20140149641 | Optimized Configurable NAND Parameters - Configurable parameters may be used to access NAND flash memory according to schemes that optimize such parameters according to predicted characteristics of memory cells, for example, as a function of certain memory cell device geometry, which may be predicted based on the location of a particular device within a memory array. | 05-29-2014 |
20140149642 | DATA ERASABLE METHOD OF MEMORY IN SMART CARD AND SMART CARD THEREOF - The invention relates to a data erasable method of memory in smart cards and smart cards thereof, which includes: when a CPU in the smart card determines a data erasable operation will be proceed in the specified memory of the smart card, cache the data to be written in a random memory cache of the specified memory; after sending a data erasable signal to the specified memory, control itself to enter a standby sleep mode. The data erasable signal is used to indicate the specified memory to process the data erasable operation by obtaining the data to be written from the random memory cache. Using the provided solution, the current of the machine card interface can be reduced when a data erasable is proceed in the specified memory of the smart card, thus abnormal conditions due to the high current of the machine card interface are avoided, and the power consumption is reduced at the same time, the standby time of the device which the smart card is in is improved. | 05-29-2014 |
20140149643 | PATCH MECHANISM IN EMBEDDED CONTROLLER FOR MEMORY ACCESS - Various exemplary embodiments relate to a patch module connected between a data bus and a ROM memory controller. The patch module may include: at least one patch address register configured to store a ROM address; a patch data register corresponding to each patch address register, each patch data register configured for storing an instruction; an address comparator configured to compare an address received on the data bus with an address stored in each patch address register and output a first signal identifying a matching patch address register and a second signal indicating whether there is a matching address; and a first multiplexer configured to select the patch data register corresponding to the matching patch address register and output the contents of the patch data register to the data bus. | 05-29-2014 |
20140149644 | ELECTRONIC APPARATUS, METHOD OF UPDATING FIRMWARE, AND COMPUTER-READABLE RECORDING MEDIUM - An electronic apparatus includes a function unit which stores firmware, a communication interface unit which receives new firmware to be updated, a controller which converts an operation mode of the electronic apparatus to a power-saving mode, and an update unit which updates firmware of the function unit using the new firmware received in a process of restoring an operation mode of the electronic apparatus from a power-saving mode to a general mode. | 05-29-2014 |
20140149645 | INFORMATION PROCESSING APPARATUS, METHOD OF CONTROLLING THE SAME, AND STORAGE MEDIUM - An information processing apparatus capable of reading/writing a storage device capable of performing dynamic wear leveling, a method of controlling the apparatus, and a storage medium. The apparatus confirms a logically free region of the storage device, and performs writing of dummy data to the logically free region and logical deletion of a region to which the dummy data is written. | 05-29-2014 |
20140149646 | MEMORY SYSTEMS INCLUDING FLASH MEMORIES, FIRST BUFFER MEMORIES, SECOND BUFFER MEMORIES AND MEMORY CONTROLLERS AND METHODS FOR OPERATING THE SAME - One example embodiment of the inventive concepts is directed to provide an operating method of a memory system including a flash memory, a first buffer memory, a second buffer memory and a memory controller. The operating method includes reading data stored at the flash memory and generating an address corresponding to a region of the first buffer memory at which the read data is to be stored. The operating method further includes determining whether the second buffer memory is at an erase state and if the determining indicates that the second buffer memory is at an erase state, storing the read data at the second buffer memory and the generated address of the first buffer memory at an internal register. | 05-29-2014 |
20140149647 | METHOD AND ELECTRONIC APPARATUS FOR IMPLEMENTING MULTI-OPERATING SYSTEM - A method for implementing multi-operating system, applied to an electronic apparatus in which a Solid State Disk, SSD, is provided, the SSD including a plurality of partitions each of which corresponding to a unique logical snapshot table, and a plurality of operating systems being installed in different partitions respectively, wherein the method includes: determining a logical snapshot table corresponding to an operating system to be loaded currently as a first logical snapshot table during a Power On Self Test process of a basic input/output system; and determining a position of a partition in the SSD which corresponds to a reading/writing operation based on the first logical snapshot table if the reading/writing operation is performed on the SSD in a manner of Logical Block Addressing. | 05-29-2014 |
20140149648 | MEMORY SYSTEM WITH USER CONFIGURABLE DENSITY/PERFORMANCE OPTION - The memory system has one or more memory dies coupled to a processor or other system controller. Each die has a separate memory array organized into multiple memory blocks. The different memory blocks of each die can be assigned a different memory density by the end user, depending on the desired memory performance and/or memory density. The user configurable density/performance option can be adjusted with special read/write operations or a configuration register having a memory density configuration bit for each memory block. | 05-29-2014 |
20140149649 | MEASURE OF HEALTH FOR WRITING TO LOCATIONS IN FLASH - For each of a plurality of locations in flash memory, a number of pulses required to change a value stored in that location is obtained. From the plurality of locations, a location to write to is selected using the obtained number of pulses. The selected location is written to. | 05-29-2014 |
20140156909 | Systems and Methods for Dynamic Optimization of Flash Cache in Storage Devices - In various embodiments, a storage device includes a magnetic media, a cache memory, and a drive controller. In embodiments, the drive controller is configured to establish a portion of the cache memory as an archival zone having a cache policy to maximize write hits. The drive controller is further configured to pre-erase the archival zone, direct writes from a host to the archival zone, and flush writes from the archival zone to the magnetic media. In embodiments, the drive controller is configured to establish a portion of the cache memory as a retrieval zone having a cache policy to maximize read hits. The drive controller is further configured to pre-fetch data from the magnetic media to the retrieval zone, transfer data from the retrieval zone to a host upon request by the host, and transfer read ahead data to the retrieval zone to replace data transferred to the host. | 06-05-2014 |
20140156910 | Automated Space Management for Server Flash Cache - Techniques for automatically allocating space in a flash storage-based cache are provided. In one embodiment, a computer system collects I/O trace logs for a plurality of virtual machines or a plurality of virtual disks and determines cache utility models for the plurality of virtual machines or the plurality of virtual disks based on the I/O trace logs. The cache utility model for each virtual machine or each virtual disk defines an expected utility of allocating space in the flash storage-based cache to the virtual machine or the virtual disk over a range of different cache allocation sizes. The computer system then calculates target cache allocation sizes for the plurality of virtual machines or the plurality of virtual disks based on the cache utility models and allocates space in the flash storage-based cache based on the target cache allocation sizes. | 06-05-2014 |
20140156911 | HOST READ COMMAND RETURN REORDERING BASED ON TIME ESTIMATION OF FLASH READ COMMAND COMPLETION - Managing data returns to a host in response to read commands, an operation monitor of a solid-state drive (SSD) manages counters used to hold metrics that characterize the estimated time to complete a read operation on a corresponding flash die. A timer generates a periodic event which decrements the counters over time. The value stored in each counter is generated for flash operations submitted to the corresponding die and is, generally, based on the operational history and the physical location of the operation. Whenever a read command is scheduled for submission to a particular die, the time estimate for that particular read operation is retrieved and, based on this information, the optimum order in which to return data to the host is determined. This order is used to schedule and program data transfers to the host so that a minimum number of read commands get blocked by other read commands. | 06-05-2014 |
20140156912 | MEMORY MANAGEMENT METHOD, AND MEMORY CONTROLLER AND MEMORY STORAGE APPARATUS USING THE SAME - A memory management method and a memory controller and a memory storage apparatus using the same are provided. The method includes applying different detection biases to read data stored in physical pages of a rewritable non-volatile memory module and calculating the number of error bits according the read data. The method further includes estimating a value of a wearing degree of each physical page according to the calculated number of error bits and operating the rewritable non-volatile memory module according to the value of the wearing degree of each physical page. Accordingly, the method can effectively identify the wearing degree of the rewritable non-volatile memory module and operate the rewritable non-volatile memory module by applying a corresponding management mechanism, so as to prevent data errors. | 06-05-2014 |
20140156913 | DATA PROCESSING METHOD, MEMORY CONTROLLER AND MEMORY STORAGE APPARATUS - A data processing method, a memory controller and a memory storage apparatus are provided. The method includes receiving a write command from a host system. A write data stream corresponding to the write command includes multiple sub-data streams, and each of the sub-data streams is attached with a data index mark by an application installed in the host system. The application determines the data index mark attached to each sub-data stream in accordance with a first rule including a predetermined function, an initial parameter selecting manner and a parameter increasing manner, in which the first rule is pre-agreed by the application with the memory storage apparatus. The method also includes reordering the sub-data streams according to the first rule and the data index mark of each sub-data stream. The method further includes transmitting the reordered sub-data streams to a smartcard chip in the memory storage apparatus. | 06-05-2014 |
20140156914 | BLIND AND DECISION DIRECTED MULTI-LEVEL CHANNEL ESTIMATION - Data which is read back from a multi-level storage device is received. For each bin in a set of bins, a portion of reads which fall into that particular bin and which are to be maintained is received. The set of bins is adjusted so that the read-back data, after assignment using the adjusted set of bins, matches the received portions of reads which are to be maintained. | 06-05-2014 |
20140156915 | PARTITIONING A FLASH MEMORY DATA STORAGE DEVICE - A method of partitioning a data storage device that has a plurality of memory chips includes determining a number memory chips in the data storage device, defining, via a host coupled to the data storage device, a first partition of the data storage device, where the first partition includes a first subset of the plurality of memory chips, defining a second partition of the data storage device via the host where the second partition includes a second subset of the plurality of memory chips, such that the first subset does not include any memory chips of the second subset and wherein the second subset does not include any memory chips of the first subset. | 06-05-2014 |
20140156916 | CONTROL ARRANGEMENTS AND METHODS FOR ACCESSING BLOCK ORIENTED NONVOLATILE MEMORY - A read/write arrangement is described for use in accessing at least one nonvolatile memory device in read/write operations with the memory device being made up of a plurality of memory cells which memory cells are organized as a set of pages that are physically and sequentially addressable with each page having a page length such that a page boundary is defined between successive ones of the pages in the set. The read/write arrangement includes a control arrangement that is configured to store and access a group of data blocks that is associated with a given write operation in a successive series of pages of the memory such that at least an initial page in the series is filled and each block includes a block length that is different than the page length. | 06-05-2014 |
20140156917 | Storage Devices, Flash Memories, and Methods of Operating Storage Devices - A storage device is provided including a flash memory, and a controller programming first bit data and second bit data into the flash memory and not backing up the first bit data when programming the first bit data and the second bit data in the same transaction and backing up the first bit data when programming the first bit data and the second bit data in different transactions, wherein the first bit data is less significant bit data than the second bit data, and each of the transactions is determined using a sync signal transmitted from a host. | 06-05-2014 |
20140156918 | STORAGE DEVICES INCLUDING MEMORY DEVICE AND METHODS OF OPERATING THE SAME - Storage devices including a memory device and methods of operating the storage devices are provided. The storage devices may include a controller which is configured to program first bit data and second bit data paired with the first bit data into a memory device. The first bit data may be less significant bit data than the second bit data. The controller may be configured to selectively perform or skip backup of the first bit data when programming the second bit data. | 06-05-2014 |
20140156919 | Isolation Switching For Backup Memory - Certain embodiments described herein include a memory system having a volatile memory subsystem, a non-volatile memory subsystem, a controller coupled to the non-volatile memory subsystem, and a circuit coupled to the volatile memory subsystem, to the controller, and to a host system. In a first mode of operation, the circuit is operable to selectively isolate the controller from the volatile memory subsystem, and to selectively couple the volatile memory subsystem to the host system to allow data to be communicated between the volatile memory subsystem and the host system. In a second mode of operation, the circuit is operable to selectively couple the controller to the volatile memory subsystem to allow data to be communicated between the volatile memory subsystem and the nonvolatile memory subsystem using the controller, and the circuit is operable to selectively isolate the volatile memory subsystem from the host system. | 06-05-2014 |
20140156920 | Isolation Switching For Backup Of Registered Memory - Certain embodiments described herein include a memory system having a register coupled to a host system and operable to receive address and control signals from the host system, a volatile memory subsystem, a non-volatile memory subsystem, a controller coupled to the non-volatile memory subsystem, and a circuit coupled to the register, the volatile memory subsystem, and the controller. In a first mode of operation, the circuit is operable to selectively isolate the controller from the volatile memory subsystem, and to selectively couple the volatile memory subsystem to the register to allow data to be communicated between the volatile memory subsystem and the host system. In a second mode of operation, the circuit is operable to selectively couple the controller to the volatile memory subsystem to allow data to be communicated between the volatile memory subsystem and the non-volatile memory subsystem using the controller, and is operable to selectively isolate the volatile memory subsystem from the register. | 06-05-2014 |
20140156921 | METHODS FOR WRITING DATA TO NON-VOLATILE MEMORY-BASED MASS STORAGE DEVICES - Methods of operating a non-volatile solid state memory-based mass storage device having at least one non-volatile memory component. In one aspect of the invention, the one or more memory components define a memory space partitioned into user memory and over-provisioning pools based on a P/E cycle count stored in a block information record. The storage device transfers the P/E cycle count of erased blocks to a host and the host stores the P/E cycle count in a content addressable memory. During a host write to the storage device, the host issues a low P/E cycle count number as a primary address to the content addressable memory, which returns available block addresses of blocks within the over-provisioning pool as a first dimension in a multidimensional address space. Changed files are preferably updated in append mode and the previous version can be maintained for version control. | 06-05-2014 |
20140156922 | NON-VOLATILE MEMORY DEVICE ADAPTED TO IDENTIFY ITSELF AS A BOOT MEMORY - Non-volatile memory devices and methods of their operation are provided. One such non-volatile memory device has an interface and a control circuit. The non-volatile memory device is adapted to identify itself as a boot memory in response to receiving an interrogation request on the interface. | 06-05-2014 |
20140164675 | LOW-OVERHEAD STORAGE OF A HIBERNATION FILE IN A HYBRID DISK DRIVE - A hybrid drive and associated methods provide low-overhead storage of a hibernation file in the hybrid hard disk drive. During operation, the hybrid drive allocates a portion of solid-state memory in the drive that is large enough to accommodate a hibernation file associated with a host device of the hybrid drive. In addition to the erased memory blocks that are normally present during operation of the hybrid drive, the portion of solid-state memory allocated for accommodating the hibernation file may include over-provisioned memory blocks, blocks used to store a previous hibernation file that has been trimmed, and/or non-dirty blocks. | 06-12-2014 |
20140164676 | USING A VIRTUAL TO PHYSICAL MAP FOR DIRECT USER SPACE COMMUNICATION WITH A DATA STORAGE DEVICE - A data storage device includes multiple flash memory devices, where each of the flash memory devices are arranged into multiple blocks having multiple pages for storing data. The data storage device includes a memory controller that is operationally coupled with the flash memory devices. The memory controller is configured to receive a virtual to physical memory address translation map from a host device, where a physical memory address includes a physical address for memory on the host device. The memory controller is configured to store the virtual to physical memory address translation map in a memory module on the memory controller, receive commands directly from an application running on the host device, where the commands include virtual memory addresses that refer to the memory on the host device and translate the virtual memory addresses to physical memory addresses using the virtual to physical memory address translation map. | 06-12-2014 |
20140164677 | USING A LOGICAL TO PHYSICAL MAP FOR DIRECT USER SPACE COMMUNICATION WITH A DATA STORAGE DEVICE - A data storage device includes multiple flash memory devices, where each of the flash memory devices is arranged into multiple blocks having multiple pages for storing data. The data storage device includes a memory controller operationally coupled with the flash memory devices. The memory controller is configured to receive a logical to physical address translation map from a host device, where a physical address includes a physical address for one of the flash memory devices. The memory controller is configured to store the logical to physical address translation map in a memory module on the memory controller, receive read commands directly from an application running on the host device, where the read commands include logical memory addresses that refer to the logical locations on the flash memory devices, and translate the logical addresses to physical memory addresses using the logical to physical address translation map. | 06-12-2014 |
20140164678 | INTELLIGENT DETECTION DEVICE OF SOLID STATE HARD DISK COMBINING A PLURALITY OF NAND FLASH MEMORY CARDS AND DETECTING METHOD FOR THE SAME - An intelligent detection device of solid state hard disks combining a plurality of NAND flash memory card, and detecting method for the same. Wherein, a central processing unit (CPU) controls a control unit, and is connected electrically to a plurality of flash card insertion slots, for a plurality of NAND flash memory card to be inserted in. Said control unit reads parameters of said flashcards, and transmits said parameters back to said CPU, for it to determine status of each said NAND flash memory card, and display status of each said NAND flash memory card on at least a status display unit. Said intelligent detection device is capable of integrating storage space of a plurality of NAND flash memory card into a larger storage space, and detecting status of each said NAND flash memory card, to inform users to backup data in time. | 06-12-2014 |
20140164679 | Dynamic Block Linking with Individually Configured Plane Parameters - A multi-plane non-volatile memory die includes circuits that receive and apply different parameters to different planes while accessing planes in parallel so that different erase blocks are accessed using individualized parameters. Programming parameters, and read parameters can be modified on a block-by-block basis with modification based on the number of write-erase cycles or other factors. | 06-12-2014 |
20140164680 | METHOD FOR SWITCHING OPERATION MODE, MEMORY CONTROLLER AND MEMORY STORAGE APPARATUS - An operation mode switching method for a memory storage apparatus, a memory controller and a memory storage apparatus using the method are provided. The operation mode switching method includes receiving at least one access command from a host system and determining whether the access command conforms to a predetermined pattern. If the access command conforms to the predetermined pattern, an operation mode of the memory storage apparatus is switched from a first mode to a second mode. The access command includes a first write command including a write string, and the memory storage apparatus executes an operation corresponding to the write string. Accordingly, the method switches the operation mode of the storage memory apparatus by determining the pattern of the access command, so as to simplify the procedure of switching the operation mode and effectively decrease the probability of switching the operation mode incorrectly. | 06-12-2014 |
20140164681 | Systems and Methods for Intelligent Flash Management - Systems and method for performing intelligent flash management are disclosed. A controller may determine if a write pattern exists between a set of writes associated with a first data chunk and a set of writes associated with a second data chunk based on whether a number of writes for first data chunk is equal to a number of writes for second data chunk; a degree to which a sequence of logical block address for the first data chunk matches the sequence of logical block addresses for the second data chunk; and a degree to which a size of each write for the first data chunk matches a size of each write for the second data chunk. The controller may then perform storage management operations based on whether or not a write pattern exists. | 06-12-2014 |
20140164682 | NONVOLATILE MEMORY APPARATUS, OPERATING METHOD THEREOF, AND DATA PROCESSING SYSTEM HAVING THE SAME - Provided is a nonvolatile memory apparatus which writes data into a memory cell according to a program and verify (PNV) operation, wherein the nonvolatile memory apparatus performs the PNV operation for first data during a first time, and performs a plurality of PNV operations for second data during the first time. | 06-12-2014 |
20140164683 | NONVOLATILE MEMORY APPARATUS, OPERATING METHOD THEREOF, AND DATA PROCESSING SYSTEM HAVING THE SAME - A nonvolatile memory apparatus includes: a memory cell array; a write driver/sense amplifier (WD/SA) configured to program data into the memory cell array or read data from the memory cell array; and an I/O controller configured to receive the read data from the memory cell array from the WD/SA, decide a coding mode based on comparison data between write data and the read data, encode the write data according to the coding mode, and provide the encoded data to the WD/SA. | 06-12-2014 |
20140164684 | Storage array controller - A storage array controller provides a method and system for autonomously issuing trim commands to one or more solid-state storage devices in a storage array. The storage array controller is separate from any operating system running on a host system and separate from any controller in the solid-state storage device(s). The trim commands allow the solid-state storage device to operate more efficiently. | 06-12-2014 |
20140164685 | NON-VOLATILE MEMORY DEVICE AND OPERATING METHOD THEREOEF - An operating method is for operating a memory controller which controls a non-volatile memory device. The non-volatile memory device includes a plurality of memory cells arranged in a direction perpendicular to a substrate. The operating method includes erasing the plurality of memory cells, reading memory cells connected with a first word line using a first word line voltage to search string address information corresponding to memory cells being at an off state, and programming memory cells corresponding to the string address information to a particular program state based on the string address information to store mapping information. | 06-12-2014 |
20140164686 | MOBILE DEVICE AND METHOD OF MANAGING DATA USING SWAP THEREOF - A mobile device includes a storage configured to store data, a buffer memory configured to include a swap victim buffer area and a normal data area, and an application processor configured to select page data to be swapped from the normal data area and to perform a swapping operation on the selected page data. The swapping operation performs an instant swapping operation or a lazy swapping operation according to a data type of the selected page data. | 06-12-2014 |
20140164687 | MEMORY CONTROLLER AND DATA MANAGEMENT METHOD THEREOF - The present invention provides a flash memory controller for mapping the logical addresses to the physical addresses of memory including a plurality of blocks, each having a plurality of pages, wherein the memory controller includes a processor. The processor includes hot page decision unit and an address translation unit. The hot page decision unit classifies pages in each block into hot pages and cold pages based on a predetermined criterion. When there is a plurality of the classified hot pages, the address translation unit respectively arranges the classified hot pages in different target blocks. | 06-12-2014 |
20140173173 | METHOD, DEVICE, AND SYSTEM INCLUDING CONFIGURABLE BIT-PER-CELL CAPABILITY - A method includes providing a partition command to a device that includes a memory array including a plurality of memory cells. In response to the providing of the partition command, the memory cells of the memory array are partitioned to select a portion of the memory array. In response to the providing of the partition command, one of bit numbers that are to be stored in one memory cell is selected, so that each of the memory cells included in the selected portion stores data with the selected one of the bit numbers. | 06-19-2014 |
20140173174 | LOWER PAGE READ FOR MULTI-LEVEL CELL MEMORY - An electronic memory or controller may use a first type of read command, addressed to a first page of memory of an electronic memory that includes information to indicate that a second page of memory of the electronic memory has not been programmed and a second type of read command, addressed to the first page of memory, that includes information to indicate that the second page of memory has been programmed. The first page of memory may include a lower page of a multi-level cell (MLC), and the second page of memory may include an upper page of the same MLC. The second page of memory is enabled during a period of time that the first type of read command is used. | 06-19-2014 |
20140173175 | NAND COMMAND AGGREGATION - An embodiment is a method and apparatus to provide an optimization of commands in a flash device. Commands sent by at least a top-level processor to a flash device are buffered in a buffer. The buffered commands are analyzed for an optimizing condition. The commands are aggregated if the optimizing condition is met. The aggregated commands are sent to the flash device. | 06-19-2014 |
20140173176 | HEAP-BASED MECHANISM FOR EFFICIENT GARBAGE COLLECTION BLOCK SELECTION - N page counters are associated with N blocks in the flash subsystem. Each of the N page counters indicates a count of invalid pages in each corresponding block in the N blocks. A max heap structure is formed over the N page counters. At least one of the N page counters is updated each time the count changes. The max heap structure is updated each time the at least one of the N page counters is updated. | 06-19-2014 |
20140173177 | Write Performance In Solid State Storage by Recognizing Copy Source to Target Operations and Only Storing Updates Instead of Entire Block - A mechanism is provided in a data processing system for accessing a solid state drive. Responsive to receiving request to write an update to a block of data in the solid state drive with an update option set, the mechanism reads the block of data from the solid state drive. The mechanism determines a difference between the update and the block of data. The mechanism compresses the difference to form an update record. The mechanism stores the update record and modifies metadata of the block of data to reference the update record. | 06-19-2014 |
20140173178 | Joint Logical and Physical Address Remapping in Non-volatile Memory - A method includes, for data items that are to be stored in a non-volatile memory in accordance with respective logical addresses, associating the logical addresses with respective physical storage locations in the non-volatile memory, and storing the data items in the respective associated physical storage locations. A remapping command, which specifies a group of source logical addresses that are associated with respective source physical storage locations, is received. In response to the remapping command, destination physical storage locations and destination logical addresses are selected jointly for replacing the source physical storage locations and the source logical addresses, respectively, so as to meet a joint performance criterion with respect to the logical addresses and the physical storage locations. The data items are copied from the source physical storage locations to the respective destination physical storage locations, and the destination physical storage locations are re-associated with the respective destination logical addresses. | 06-19-2014 |
20140173179 | VIRTUAL BOUNDARY CODES IN A DATA IMAGE OF A READ-WRITE MEMORY DEVICE - Methods, systems and devices are provided for configuring a read-write memory device with a data image. The method includes determining a data image distribution based on a virtual block size of a series of virtual blocks designated for the read-write memory device. The data image is divided into one or more data image portions, wherein a virtual boundary code is appended to at least one of the data image portions. The data image portions are stored in respective virtual blocks of the series of virtual blocks, skipping over any bad block within the read-write memory device, even between the virtual blocks. | 06-19-2014 |
20140173180 | TRACKING READ ACCESSES TO REGIONS OF NON-VOLATILE MEMORY - A data storage device includes a memory and a controller and may perform a method that includes updating, in the controller, a value of a particular counter of a set of counters in response to a read access to a particular region of the non-volatile memory that is tracked by the particular counter. Read accesses to a first region of the non-volatile memory are tracked by a first counter of the set of counters and read accesses to a second region of the non-volatile memory are tracked by a second counter of the set of counters. The method includes, in response to the value of the particular counter indicating that a count of read accesses to the particular region equals or exceeds a first threshold, initiating a remedial action to the particular region of the non-volatile memory. | 06-19-2014 |
20140173181 | RAPID VIRTUAL MACHINE SUSPEND AND RESUME - A method of enabling “fast” suspend and “rapid” resume of virtual machines (VMs) employs a cache that is able to perform input/output operations at a faster rate than a storage device provisioned for the VMs. The cache may be local to a computer system that is hosting the VMs or may be shared cache commonly accessible to VMs hosted by different computer systems. The method includes the steps of saving the state of the VM to a checkpoint file stored in the cache and locking the checkpoint file so that data blocks of the checkpoint file are maintained in the cache and are not evicted, and resuming execution of the VM by reading into memory the data blocks of the checkpoint file stored in the cache. | 06-19-2014 |
20140173182 | NONVOLATILE SEMICONDUCTOR MEMORY - According to one embodiment, a memory includes a temporary storage area which temporary stores data in a read/write operation to an array. The temporary storage area comprises a clamp FET connected between a first data bus and a second data bus, a first precharge FET connected between the first data bus and first potential, a second precharge FET connected between the second data bus and the first potential, a first storage area connected to the first data bus, and a second storage area connected to the second data bus. The control circuit is configured to generate a precharge state in which the first data bus is precharged to the first potential and the second data bus is precharged to a second potential lower than the first potential, when the data is transferred from the second storage area to the first storage area. | 06-19-2014 |
20140173183 | DATA STORAGE DEVICE AND METHOD OF OPERATING THE SAME - An operating method of a data storage device including nonvolatile memory devices includes making a victim block list for victim blocks for which a merge operation is to be performed and copying valid pages of the victim bocks to a merge block. The method also includes determining whether there is a victim block which has an erase-held valid page selectively erasing the victim blocks included in the victim block list, according to which victim blocks have an erase-held page, and updating the victim block list according to which victim blocks are erased. | 06-19-2014 |
20140173184 | DATA STORAGE DEVICE AND OPERATING METHOD THEREOF - A method of operating a data storage device includes setting program verify voltages for verifying whether memory cells of a nonvolatile memory device are programmed to desired program states; transmitting the set program verify voltages to the nonvolatile memory device; generating data patterns respectively corresponding to program states based on the program verify voltages; transmitting a data pattern corresponding to the program verify voltages to the nonvolatile memory device; and programming the memory cells with the transmitted data pattern. | 06-19-2014 |
20140173185 | Write Performance in Fault-Tolerant Clustered Storage Systems - Embodiments of the invention relate to supporting transaction data committed to a stable storage. Committed data in the cluster is stored in the persistent cache layer and replicated and stored in the cache layer of one or more secondary nodes. One copy is designated as a master copy and all other copies are designated as replica, with an exclusive write lock assigned to the master and a shared write lock extended to the replica. An acknowledgement of receiving the data is communicated following confirmation that the data has been replicated to each node designated to receive the replica. Managers and a director are provided to support management of the master copy and the replicas within the file system, including invalidation of replicas, fault tolerance associated with failure of a node holding a master copy, recovery from a failed node, recovered of the file system from a power failure, and transferring master and replica copies within the file system. | 06-19-2014 |
20140173186 | Journaling RAID System - A method of providing data storage is disclosed that includes writing a plurality of data non-sequentially to at least one first storage drive, the at least one first storage drive having a random first input/output operations per second (IOPS) speed, and writing the plurality of data and an associated plurality of journal metadata sequentially to at least one second storage drive, the at least one second storage drive having a second random IOPS speed that is slower than the first random IOPS speed. | 06-19-2014 |
20140173187 | VIRTUAL BOUNDARY CODES IN A DATA IMAGE OF A READ-WRITE MEMORY DEVICE - Methods, systems and devices are provided for revising a data image of a read-write memory device. The method includes accessing an initial data image from an initial virtual block corresponding to an actual block of a series of actual blocks of the read-write memory device. The initial data image includes an initial boot loader. Also, a backup data image is stored in a remote virtual block spaced away and following in the series of actual blocks from the initial virtual block. The backup data image includes a backup boot loader. Additionally, the initial data image is erased from the initial virtual block and a replacement data image is stored in the initial virtual block. The initial virtual block may include more than one virtual block spaced away and proceeding in the series of actual blocks from the remote virtual block. | 06-19-2014 |
20140173188 | INFORMATION PROCESSING DEVICE - An information processing device includes: an SSD storage controlling unit for storing a physical address of a storage region of data stored in an SSD (Solid State Drive) and a number of updates of the storage region, as SSD update information into the SSD; a backup storage controlling unit for storing copy data of the data stored in the SSD, and copy update information obtained by copying the SSD update information, in association with each other into a backup storage part; an acquiring unit for acquiring the copy update information corresponding to data associated with the SSD update information acquired from the SSD, from the backup storage part; and a deciding unit for deciding the data to be stored into the backup storage part based on the acquired SSD update information and the acquired copy update information. | 06-19-2014 |
20140173189 | COMPUTING SYSTEM USING NONVOLATILE MEMORY AS MAIN MEMORY AND METHOD FOR MANAGING THE SAME - A method of managing data of a computing system is provided, where the computing system uses a nonvolatile memory as a main memory. The method includes loading a process into the nonvolatile memory in response to a first run request, freezing the process loaded into the nonvolatile memory in response to an exit request of the process, and activating the process frozen in the nonvolatile memory in response to a second run request of the process. Freezing the process releases control of the process without deleting the process loaded into the nonvolatile memory. | 06-19-2014 |
20140173190 | TECHNIQUES TO PERFORM POWER FAIL-SAFE CACHING WITHOUT ATOMIC METADATA - A method and system to allow power fail-safe write-back or write-through caching of data in a persistent storage device into one or more cache lines of a caching device. No metadata associated with any of the cache lines is written atomically into the caching device when the data in the storage device is cached. As such, specialized cache hardware to allow atomic writing of metadata during the caching of data is not required. | 06-19-2014 |
20140173191 | SEMICONDUCTOR MEMORY SYSTEM HAVING A SNAPSHOT FUNCTION - In a semiconductor memory computer equipped with a flash memory, use of backed-up data is enabled. The semiconductor memory computer includes an address conversion table for detecting physical addresses of at least two pages storing data by designating a logical address from one of logical addresses to be designated by a reading request. The semiconductor memory computer includes a page status register for detecting one page status allocated to each page, and page statuses to be detected include the at least following four statuses: (1) a latest data storage status, (2) a not latest data storage status, (3) an invalid data storage status, and (4) an unwritten status. By using the address conversion table and the page status register, at least two data s (latest data and past data) can be read for one designated logical address from a host computer. | 06-19-2014 |
20140181363 | ADAPTING BEHAVIOR OF SOLID-STATE DRIVE USING REAL USAGE MODEL - An embodiment is a technique to adapt behavior of a solid-state drive (SSD) to extend lifespan of the SSD. Real environmental information is received from an environmental processor. The real environmental information corresponds to an environment of the SSD. A behavior model is selected based on a real environmental model and an internal data usage model. If a new behavior model is selected, the environmental processor is informed about the new behavior model. The environmental processor sends control commands to a power management module to apply new power policy to the SSD. Information on the new behavior model is made available for query. If current behavior model is selected, the current behavior model is maintained. | 06-26-2014 |
20140181364 | Systems And Methods For Support Of Non-Volatile Memory On A DDR Memory Channel - Systems and methods are provided for supporting use of non-volatile memory (NVM) on a double data rate (DDR) memory channel for an information handling system so that non-volatile memory devices (e.g., such as Phase Change Memory “PCM” devices) may be employed for main memory usage. In one possible implementation, information handling system memory reads may be managed directly in hardware as memory semantics via use code, while memory writes may be separately handled, e.g., via an operating system (OS)/driver. In another possible implementation, both DRAM-based and NVM-based memory systems may be populated for an information handling system. | 06-26-2014 |
20140181365 | Techniques to Configure a Solid State Drive to Operate in a Storage Mode or a Memory Mode - Examples are disclosed for configuring a solid state drive (SSD) to operate in a storage mode or a memory mode. In some examples, one or more configuration commands may be received at a controller for an SSD having one or more non-volatile memory arrays. The SSD may be configured to operate in at least one of a storage mode, a memory mode or a combination of the storage mode or the memory mode based on the one or more configuration commands. Other examples are described and claimed. | 06-26-2014 |
20140181366 | METHOD FOR DISPERSING AND COLLATING I/O'S FROM VIRTUAL MACHINES FOR PARALLELIZATION OF I/O ACCESS AND REDUNDANCY OF STORING VIRTUAL MACHINE DATA - Methods and systems to disperse and collate I/O from virtual machines (VMs) among a plurality of near line controllers for parallelization of I/O's (parallel reads and parallel writes) and for providing redundancy for stored VM data is disclosed. | 06-26-2014 |
20140181367 | IN-PLACE CHANGE BETWEEN TRANSIENT AND PERSISTENT STATE FOR DATA STRUCTURES ON NON-VOLATILE MEMORY - Methods and apparatus related to in-place change between transient and persistent state for data structures on non-volatile memory are described. In one embodiment, controller logic causes a change in a state of a first portion of one or more non-volatile memory devices between a persistent state and a transient state and without moving data stored in the first portion of the one or more non-volatile memory devices. Other embodiments are also disclosed and claimed. | 06-26-2014 |
20140181368 | EQUALIZING WEAR ON STORAGE DEVICES WITH WRITE COUNTERS - Data stored in file blocks and storage blocks of a storage device may be tracked by the file system. The file system may track a number of writes performed to each file block and storage block. The file system may also track a state of each storage block. The file system may use information, such as the write count and the block state, to determine locations for updated data to be stored on the storage device. Placement of data by the file system allows the file system to manage wear on storage devices, such as solid state storage devices. | 06-26-2014 |
20140181369 | DYNAMIC OVERPROVISIONING FOR DATA STORAGE SYSTEMS - Disclosed embodiments are directed to systems and methods for dynamic overprovisioning for data storage systems. In one embodiment, a data storage system can reserve a portion of memory, such as non-volatile solid-state memory, for overprovisioning. Depending on various overprovisioning factors, recovered storage space due to compressing user data can be allocated for storing user data and/or overprovisioning. Utilizing the disclosed dynamic overprovisioning systems and methods can result is more efficient utilization of cache memory, reduction of write amplification, increase in a cache hit rate, and the like. Improved data storage system performance and increased endurance and longevity can thereby be attained. | 06-26-2014 |
20140181370 | METHOD TO APPLY FINE GRAIN WEAR LEVELING AND GARBAGE COLLECTION - An apparatus includes a non-volatile memory and a controller. The controller is coupled to the non-volatile memory and configured to (i) measure a rate of free space consumption in the non-volatile memory, (ii) measure a rate of free space production in the non-volatile memory, and (iii) adjust a rate of a recycling process in response to the measured rate of free space consumption and the measured rate of free space production. | 06-26-2014 |
20140181371 | METHOD AND SYSTEM FOR REDUCING MAPPING TABLE SIZE IN A STORAGE DEVICE - A method and system are disclosed for handling logical-to-physical mapping and reducing mapping table size. The method includes the storage device storing in fast access memory, such as DRAM, only the physical location of a primary cluster in each cluster group, and then writing location information for remaining clusters in a cluster group into the header of the data for the primary cluster of the cluster group in non-volatile memory. The system includes a storage device having volatile memory, non-volatile memory and a controller in communication with the volatile and non-volatile memory that is configured to carry out the method noted above. | 06-26-2014 |
20140181372 | DATA READING METHOD, MEMORY CONTROLLER, AND MEMORY STORAGE DEVICE - A data reading method, a memory controller, and a memory storage device are provided. The data reading method is adapted to a rewritable non-volatile memory module having a plurality of physical erasing units. The data reading method includes following steps. A plurality of logical addresses is configured to be mapped to a part of the physical erasing units. A plurality of read commands is received from a host system. The read commands instruct to read a plurality of first logical addresses among aforementioned logical addresses. The read commands are executed, and whether the first logical addresses are successive is determined. If the first logical addresses are successive, data belonging to a logical range is pre-read from the physical erasing units into a buffer memory. Thereby, the data reading speed is increased. | 06-26-2014 |
20140181373 | Persistent Storage Device with NVRAM for Staging Writes - A persistent storage device includes both persistent storage, which includes a set of persistent storage blocks, and NVRAM, and in particular a set of NVRAM blocks. The persistent storage device also typically includes a storage controller. The persistent storage device, in addition to responding to commands to write data directly to and to read data directly from persistent storage blocks is also configured to write data to specified NVRAM blocks (e.g., specified by a host NVRAM write command) and to transfer data from a specified NVRAM block to a specified persistent storage block. As a result, multiple writes to a particular persistent storage block can be replaced with multiple writes to an NVRAM block and a subsequent single write to the particular persistent storage block. This reduces the number of writes to persistent storage and also reduces the number of corresponding block erase operations. | 06-26-2014 |
20140181374 | Speculative Copying of Data from Main Buffer Cache to Solid-State Secondary Cache of a Storage Server - A network storage server includes a main buffer cache to buffer writes requested by clients before committing them to primary persistent storage. The server further uses a secondary cache, implemented as low-cost, solid-state memory, such as flash memory, to store data evicted from the main buffer cache or data read from the primary persistent storage. To prevent bursts of writes to the secondary cache, data is copied from the main buffer cache to the secondary cache speculatively, before there is a need to evict data from the main buffer cache. Data can be copied to the secondary cache as soon as the data is marked as clean in the main buffer cache. Data can be written to secondary cache at a substantially constant rate, which can be at or close to the maximum write rate of the secondary cache. | 06-26-2014 |
20140181375 | MEMORY CONTROLLER - According to one embodiment, a memory controller includes a first interface, a second interface, a cache unit, a translation unit, an access unit and a lock unit. The first interface receives a lock request and an access request which includes a logical address. The second interface is connectable to a non-volatile memory. The cache unit comprises a plurality of cache line and caches correspondence information between the logical address and a physical address of the non-volatile memory. The translation unit translates the logical address included in the access request into the physical address with reference to the cache unit. The access unit performs access in accordance with the access request to a position indicated by the translated physical address. The lock unit sets the cache line lock state in accordance with the lock request. The lock state is the state where the cache line being prohibited to be refilled. | 06-26-2014 |
20140181376 | MEMORY CONTROLLER AND MEMORY SYSTEM - According to an embodiment, a retention time of each block group is managed and a degree of wear of each block is managed. A free block allocated to each block group is determined based on the retention time of each block group and the degree of wear of each block. | 06-26-2014 |
20140181377 | CONCURRENT CONTENT MANAGEMENT AND WEAR OPTIMIZATION FOR A NON-VOLATILE SOLID-STATE CACHE - Described is a technique for managing the content of a nonvolatile solid-state memory data cache to improve cache performance while at the same time, and in a complementary manner, providing for automatic wear leveling. A modified circular first-in first-out (FIFO) log/algorithm is generally used to determine cache content replacement. The algorithm is used as the default mechanism for determining cache content to be replaced when the cache is full but is subject to modification in some instances. In particular, data are categorized according to different data classes prior to being written to the cache, based on usage. Once cached, data belonging to certain classes are treated differently than the circular FIFO replacement algorithm would dictate. Further, data belonging to each class are localized to designated regions within the cache. | 06-26-2014 |
20140181378 | CONTROL DEVICE, CONTROL METHOD, AND PROGRAM - There is provided a control device including, a reading and writing control unit configured to control writing and reading of data on and from a non-volatile memory that has a plurality of blocks each set to be a unit for performing erasure of data. The non-volatile memory stores order information indicating an order of the blocks in which data is to be written. The reading and writing control unit selects a writing target block that is a target block for writing of data according to the order indicated by the order information, and writes data in the selected writing target block. | 06-26-2014 |
20140181379 | File Reading Method, Storage Device And Electronic Device - A file reading method, storage device and electronic device are described. The file reading method is applied to an electronic device that includes a nonvolatile storage device as an internal storage device. The method includes determining a specific file in the electronic device as a hotspot file according to a predetermined condition; copying the determined hotspot file to the non-volatile storage device; and directly addressing the non-volatile storage device and reading the hotspot file from the nonvolatile storage device when receiving a request for reading the hotspot file. | 06-26-2014 |
20140181380 | MEMORY WEAR CONTROL - The disclosure is related to systems and methods of controlling wear of a memory. In a particular embodiment, a system is disclosed that comprises a memory and a performance governor circuit coupled to the memory. The performance governor circuit is adapted to control a wear of the memory as a function of time. | 06-26-2014 |
20140181381 | Pre-Fetching Data into a Memory - Systems and methods for pre-fetching of data in a memory are provided. By pre-fetching stored data from a slower memory into a faster memory, the amount of time required for data retrieval and/or processing may be reduced. First, data is received and pre-scanned to generate a sample fingerprint. Fingerprints stored in a faster memory that are similar to the sample fingerprint are identified. Data stored in the slower memory associated with the identified stored fingerprints is copied into the faster memory. The copied data may be compared to the received data. Various embodiments may be included in a network memory architecture to allow for faster data matching and instruction generation in a central appliance. | 06-26-2014 |
20140181382 | User Selectable Balance Between Density and Reliability - A method for enabling users to select a configuration balance for a memory device is described. The method includes receiving an indication of a memory configuration for a mass memory including two or more of memory cells. One or more memory cells of the mass memory are selected based at least in part on 1) the indication, 2) a current configuration for each of the one or more memory cells and 3) a program-erase count for each of the one or more memory cells. The method also includes determining a new configuration for each of the selected one or more memory cells. For each of the selected one or more memory cells, the configuration of the memory cell is changed from the current configuration to the determined new configuration. Apparatus and computer readable media are also disclosed. | 06-26-2014 |
20140181383 | RELIABILITY SCHEME USING HYBRID SSD/HDD REPLICATION WITH LOG STRUCTURED MANAGEMENT - In one embodiment, a method of managing data includes managing a first copy of data in a solid state memory using a controller of the solid state memory, and managing a second copy of the data in a hard disk drive memory using the controller. In another embodiment, a system for storing data includes a solid state memory, at least one hard disk drive memory, and a controller for controlling storage of data in both the solid state memory and the hard disk drive memory. Other methods, systems, and computer program products are also described according to various embodiments. | 06-26-2014 |
20140189197 | SHARING SERIAL PERIPHERAL INTERFACE FLASH MEMORY IN A MULTI-NODE SERVER SYSTEM ON CHIP PLATFORM ENVIRONMENT - Methods and apparatus related to sharing Serial Peripheral Interface (SPI) flash memory in a multi-node server SoC (System on Chip) platform environment are described. In one embodiment, multi-port non-volatile memory is shared by a plurality of System on Chip (SoC) devices. Each of the plurality of SoC devices comprises controller logic to control access to the multi-port non-volatile memory and/or to translate a host referenced address of a memory access request to a linear address space and a physical address space of the multi-port non-volatile memory. Other embodiments are also disclosed and claimed. | 07-03-2014 |
20140189198 | MEMORY ALLOCATION FOR FAST PLATFORM HIBERNATION AND RESUMPTION OF COMPUTING SYSTEMS - Memory allocation for fast platform hibernation and resumption of computing systems. An embodiment of an apparatus includes logic at least partially implemented in hardware, the logic to: dynamically allocate at least a first portion of a nonvolatile memory; in response to a command to enter the apparatus into a standby state, the logic to store at least a portion of a context data from a volatile memory to the dynamically allocated first portion of the nonvolatile memory; and in response to a resumption of operation of the apparatus, the logic to copy at least the portion of the context data from the first portion of the nonvolatile memory to the volatile memory, and to reclaim the first portion of the nonvolatile memory for dynamic allocation. | 07-03-2014 |
20140189199 | FALSE POWER FAILURE ALERT IMPACT MITIGATION - Apparatus and computer program products implement embodiments of the present invention that include copying, by a storage system having a volatile memory configured as a write cache, write cache data from the volatile memory to a solid state device, upon receiving a signal indicating a loss of power to the storage system. Subsequent to copying the write cache data, the solid state device is configured as the write cache. | 07-03-2014 |
20140189200 | Flash Memory Using Virtual Physical Addresses - A system and method for using virtual physical addresses in a non-volatile memory device are disclosed. The physical layout of the non-volatile memory device may have physical die that are not a power-of-2 in number. In order to advantageously use the power-of-2 die number, which enables using a power-of-2 die interleave, a virtual physical addressing scheme is used. In particular, the virtual physical addressing scheme includes virtual die and virtual blocks, wherein the virtual die are a power-of-2 in number. Further, a conversion between the virtual physical addressing scheme and the actual physical addressing scheme is provided. In this way, for certain operations of the memory device, the virtual addressing scheme is used. For other operations, such as reading from, writing to or erasing, the actual physical addressing scheme is used. | 07-03-2014 |
20140189201 | Flash Memory Interface Using Split Bus Configuration - A system having a split bus flash memory and a method for operating the split bus flash memory is disclosed. The system may include a controller, a non-volatile memory (including first and second non-volatile memory chips) and the system bus. The controller is configured to communicate via an N-bit bus. The first and second non-volatile memory chips are configured to communicate via an M-bit bus, with M07-03-2014 | |
20140189202 | STORAGE APPARATUS AND STORAGE APPARATUS CONTROL METHOD - The access performance of a drive having a non-volatile memory is improved. | 07-03-2014 |
20140189203 | STORAGE APPARATUS AND STORAGE CONTROL METHOD - A cache memory (CM) in which data, which is accessed with respect to a storage device, is temporarily stored is coupled to a controller for accessing the storage device in accordance with an access command from a higher-level apparatus. The CM comprises a nonvolatile semi-conductor memory (NVM), and provides a logical space to the controller. The controller is configured to partition the logical space into multiple segments and to manage these segments, and to access the CM by specifying a logical address of the logical space. The CM receives the logical address-specified access, and accesses a physical area allocated to a logical area, which belongs to the specified logical address. A first management unit, which is a unit of a segment, is larger than a second management unit, which is a unit of an access performed with respect to the NVM. The capacity of the logical space is larger than the storage capacity of the NVM. | 07-03-2014 |
20140189204 | INFORMATION PROCESSING APPARATUS AND CACHE CONTROL METHOD - An information processing apparatus comprises a plurality types of cache memories having different characteristics, decides on a type of cache memory to be used as a data cache destination based on the access characteristics of cache-target data, and caches the data in the cache memory of the decided type. | 07-03-2014 |
20140189205 | METHOD AND SYSTEM FOR MANAGING PROGRAM CYCLES IN A MULTI-LAYER MEMORY - A system and method for managing program cycles in a multi-layer memory is disclosed. The method includes a controller receiving a request to program data from a host and, in advance of programming data associated with the request, determining a program cycle for programming the data associated with the request and an amount of data already programmed in the plurality of memory layers necessary to be programmed in maintenance operations to provide free memory capacity for a subsequent request to program data from the host. The controller programs the data associated with the request, and the amount of data already programmed to be programmed in maintenance operations, in predetermined programming units according to the determined program cycle. | 07-03-2014 |
20140189206 | METHOD AND SYSTEM FOR MANAGING BLOCK RECLAIM OPERATIONS IN A MULTI-LAYER MEMORY - A multi-later memory and method for operation is disclosed. The memory includes at least one flash memory die having multiple layers and a controller configured to execute block reclaim operations in a layer of the flash memory die until a net gain of at least one additional free block has been made in the layer. The method may include relocating data from reclaim blocks to relocation blocks within the same layer, or within a same partition in the same layer until a net gain of one free block has been achieved and an integer number of relocation blocks has been filled with relocated data. The method may also include moving data from reclaim blocks in a first layer into destination blocks in a second layer until a net gain of at least one free block has been achieved in the first layer. | 07-03-2014 |
20140189207 | METHOD AND SYSTEM FOR MANAGING BACKGROUND OPERATIONS IN A MULTI-LAYER MEMORY - A multi-layer memory and method for performing background maintenance operations are disclosed. The memory includes a plurality of flash memory die having multiple layers, where each layer is made up of flash memory cells having a greater bit per cell storage capacity than then prior layer and each layer may have a plurality of partitions for different data types. A controller managing the flash memory die is configured to identify an idle die and determine if a layer in the die satisfies a background maintenance criterion. Upon identifying a layer satisfying the background maintenance criterion, the valid data from reclaim blocks in the layer is relocated into a relocation block in the same layer until the relocation block is filled and the background maintenance cycle ends. | 07-03-2014 |
20140189208 | METHOD AND SYSTEM FOR PROGRAM SCHEDULING IN A MULTI-LAYER MEMORY - A multi-layer memory and method for operation is disclosed. The memory includes an interface, at least one flash memory die having a plurality of layers and a controller. The controller is configured to select an appropriate one of a predetermined number of program cycles for programming a fixed amount of host data, and for carrying out maintenance operations in one or more of the layers sufficient to permit a next host data write operation. The controller calculates an interleave ratio of maintenance operations to host data programming operations in each of the layers used in the determined programming cycle so that creation of free space is interspersed with host data writes in a steady manner during execution of the determined programming cycle. | 07-03-2014 |
20140189209 | MULTI-LAYER MEMORY SYSTEM HAVING MULTIPLE PARTITIONS IN A LAYER - A multi-layer memory and method for operation is disclosed. The memory includes multiple layers, where each layer includes flash memory cells having a greater bit per cell capacity than then prior layer and each layer may include a plurality of partitions having blocks exclusively associated with a particular data type. The method may include the steps of directing host data directly into a particular partition of a particular layer of the multi-layer memory upon receipt depending on a type of the data. The method may also include copying data within the same partition in a respective layer in a data relocation operation to generate more free blocks of memory so that data preferably stays within each layer and in the same partition, as well as transferring data from one layer to the next higher bit per cell layer within a same partition when layer transfer criteria are met. | 07-03-2014 |
20140189210 | MEMORY SYSTEM HAVING AN UNEQUAL NUMBER OF MEMORY DIE - A flash memory system having unequal number of memory die and method for operation is disclosed. The memory includes a plurality of flash memory die distributed unevenly among different control lines, such that there are an unequal number of die between control lines. A total physical storage capacity of the plurality of flash memory die is greater than a total logical capacity such that the memory system is over provisioned with physical storage capacity. A logical address splitter directs data received from a host system and associated with host logical block addresses such that each control line only receives data associated with predetermined host logical block address ranges and directs the data such that a ratio of physical capacity to logical capacity is equal among each of the control lines, regardless of the different number of die, and associated different physical capacity per control line. | 07-03-2014 |
20140189211 | Remapping Blocks in a Storage Device - In the present disclosure, a persistent storage device includes both persistent storage, which includes a set of persistent storage blocks, and a storage controller. The persistent storage device stores and retrieves data in response to commands received from an external host device. The persistent storage device stores a logical block address to physical address mapping. The persistent storage device also, in response to a remapping command, stores an updated logical block address to physical block address mapping. | 07-03-2014 |
20140189212 | PRESENTATION OF DIRECT ACCESSED STORAGE UNDER A LOGICAL DRIVE MODEL - In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for presentation of direct accessed storage under a logical drive model; for implementing a distributed architecture for cooperative NVM Data protection; data mirroring for consistent SSD latency; for boosting a controller's performance and RAS with DIF support via concurrent RAID processing; for implementing arbitration and resource schemes of a doorbell mechanism, including doorbell arbitration for fairness and prevention of attack congestion; and for implementing multiple interrupt generation using a messaging unit and NTB in a controller through use of an interrupt coalescing scheme. | 07-03-2014 |
20140189213 | ADDRESS GENERATING CIRCUIT AND ADDRESS GENERATING METHOD - An address generating circuit according to an embodiment includes a register that maintains a partition address set by a CPU, a comparator that determines whether a designated address designated by the CPU designates the interleaved area or the non-interleaved area, a selection signal generating unit that generates the selection signal based on a least significant bit of the designated address in a case of the interleaved area and generates the selection signal based on a high-order bit other than the least significant bit of the designated address in a case of the non-interleaved area, and a physical address generating unit that generates the physical address acquired by excluding the least significant bit from the designated address in a case of the interleaved area and generates the physical address acquired by excluding the high-order bit from the designated address in a case of the non-interleaved area. | 07-03-2014 |
20140189214 | FALSE POWER FAILURE ALERT IMPACT MITIGATION - Methods, apparatus and computer program products implement embodiments of the present invention that include copying, by a storage system having a volatile memory configured as a write cache, write cache data from the volatile memory to a solid state device, upon receiving a signal indicating a loss of power to the storage system. Subsequent to copying the write cache data, the solid state device is configured as the write cache. | 07-03-2014 |
20140189215 | MEMORY MODULES AND MEMORY SYSTEMS - A memory module includes a plurality of memory devices and a buffer chip. The buffer chip manages the memory devices. The buffer chip includes a refresh control circuit that groups a plurality of memory cell rows of the memory devices into a plurality of groups according to a data retention time of tire memory cell rows. The buffer chip selectively refreshes each of the plurality of groups in each of a plurality of refresh time regions that are periodically repeated and applies respective refresh periods to the plurality of groups, respectively. | 07-03-2014 |
20140189216 | APPARATUS, SYSTEM, AND METHOD FOR CONDITIONAL AND ATOMIC STORAGE OPERATIONS - An apparatus, system, and method are disclosed for implementing conditional storage operations. Storage clients access and allocate portions of an address space of a non-volatile storage device. A conditional storage request is provided, which causes data to be stored to the non-volatile storage device on the condition that the address space of the device can satisfy the entire request. If only a portion of the request can be satisfied, the conditional storage request may be deferred or fail. An atomic storage request is provided, which may comprise one or more storage operations. The atomic storage request succeeds if all of the one or more storage operations are complete successfully. If one or more of the storage operations fails, the atomic storage request is invalidated, which may comprise deallocating logical identifiers of the request and/or invalidating data on the non-volatile storage device pertaining to the request. | 07-03-2014 |
20140189217 | SEMICONDUCTOR STORAGE DEVICE - According to an embodiment, a semiconductor storage device includes a first storage unit, a read control unit, a second storage unit, and a write control unit. The first storage unit is configured to store data supplied from a host device. The read control unit is configured to perform control of reading the data in accordance with a read request. The second storage unit is configured to store a logical address used for reading the data from the first storage unit by the read control unit. The write control unit is configured to perform control of adding the stored logical address to the data and write the resulting data into the first storage unit in a case where a size of the data requested to be written into the first storage unit by the host device is smaller than a threshold. | 07-03-2014 |
20140189218 | METHOD OF PROGRAMMING DATA INTO NONVOLATILE MEMORY AND METHOD OF READING DATA FROM NONVOLATILE MEMORY - Disclosed is a method of programming data into a nonvolatile memory that includes a plurality of memory cells connected with a word line, each memory cell storing first to mth bits of a plurality of bits, the plurality of bits forming first to mth pages. The method includes generating first to mth metadata based on first to mth page data received; rearranging the first to mth metadata to generate first to mth rearranged metadata; and programming the first to mth rearranged metadata and the first to mth page data into the first to mth pages, respectively. | 07-03-2014 |
20140189219 | SOLID STATE STORAGE ELEMENT AND METHOD - A method and system for storing and retrieving data using flash memory devices. One example system includes an apparatus within a flash memory configuration. The flash memory configuration includes a plurality of memory cells, where each memory cell has a charge storage capacity for use in implementing digital storage. The apparatus includes a processing arrangement configured to access each of the memory cells in a write operation and a read operation. The apparatus also includes an instruction set for instructing the processor to impose target charge levels for defining a plurality of data values for each of the memory cells. The target charge levels are programmably movable with respect to the charge storage capacity. | 07-03-2014 |
20140189220 | EXECUTE-IN-PLACE MODE CONFIGURATION FOR SERIAL NON-VOLATILE MEMORY - Example embodiments for configuring a serial non-volatile memory device for an execute-in-place mode may comprise a non-volatile configuration register to store an execute-in-place mode value that may be read at least in part in response to power being applied to the memory device. | 07-03-2014 |
20140189221 | SEMICONDUCTOR STORAGE DEVICE AND METHOD OF CONTROLLING THE SAME - A semiconductor storage device includes a first nonvolatile memory to store user data of a file, a second nonvolatile memory to store management data of the file, the second nonvolatile memory being different in type from the first nonvolatile memory, and a controller to control read/write of data with respect to the first and second nonvolatile memories. | 07-03-2014 |
20140189222 | METHOD FOR PERFORMING DATA SHAPING, AND ASSOCIATED MEMORY DEVICE AND CONTROLLER THEREOF - A method for performing data shaping is applied to a controller of a Flash memory, where the Flash memory includes a plurality of blocks. The method includes: performing a program optimization operation according to original data and a plurality of shaping codes, in order to generate trace back information corresponding to a Trellis diagram and utilize the trace back information as side information; and dynamically selecting at least one shaping code from the shaping codes according to the side information to perform data shaping on the original data. | 07-03-2014 |
20140189223 | IC CARD, PORTABLE ELECTRONIC DEVICE, AND METHOD OF CONTROLLING IC CARD - According to one embodiment, an IC card which executes a process in accordance with a command transmitted from an external device, includes, a first storage module configured to pre-store an application including a plurality of structures, a reception module configured to receive a command transmitted from the external device, and a second storage module configured to identify, when a write command for writing the application stored by the first storage module has been received by the reception module, a structure missing in the application stored by the first storage module, and storing the identified structure. | 07-03-2014 |
20140195718 | CONTROL LOGIC DESIGN TO SUPPORT USB CACHE OFFLOAD - A redundant array of independent drives controller and board controlled cache off-loading during a power failure is described. Methods associated with the use of the redundant array of independent drives controller and board for controlled cache off-loading during a power failure are also described. | 07-10-2014 |
20140195719 | INSTANTANEOUS SAVE/RESTORE OF VIRTUAL MACHINES WITH PERSISTENT MEMORY - A computer implemented method creates a snapshot of a logical volume of a computer. The computer stores a system state of the computer in persistent memory. The computer flushes a cash of the computer. The computer identifies a preceding snapshot. Responsive to identifying the preceding snapshot, the computer hardens changes occurring after the preceding snapshot. The computer then switches from a first indirection table to a second indirection table. | 07-10-2014 |
20140195720 | High-Performance Indexing For Data-Intensive Systems - Aspects of the present invention provide high-performance indexing for data-intensive systems in which “slicing” is used to organize indexing data on an SSD such that related entries are located together. Slicing enables combining multiple reads into a single “slice read” of related items, offering high read performance. Small in-memory indexes, such as hash tables, bloom filters or LSH tables, may be used as buffers for insert operations to resolve slow random writes on the SSD. When full, these buffers are written to the SSD. The internal architecture of the SSD may also be leveraged to achieve higher performance via parallelism. Such parallelism may occur at the channel-level, the package-level, the die-level and/or the plane-level. Consequently, memory and compute resources are freed for use by higher layer applications, and better performance may be achieved. | 07-10-2014 |
20140195721 | INSTANTANEOUS SAVE/RESTORE OF VIRTUAL MACHINES WITH PERSISTENT MEMORY - A computer implemented method creates a snapshot of a logical volume of a computer. The computer stores a system state of the computer in persistent memory. The computer flushes a cash of the computer. The computer identifies a preceding snapshot. Responsive to identifying the preceding snapshot, the computer hardens changes occurring after the preceding snapshot. The computer then switches from a first indirection table to a second indirection table. | 07-10-2014 |
20140195722 | STORAGE SYSTEM WHICH REALIZES ASYNCHRONOUS REMOTE COPY USING CACHE MEMORY COMPOSED OF FLASH MEMORY, AND CONTROL METHOD THEREOF - The first storage apparatus provides a primary logical volume, and the second storage apparatus has a secondary logical volume. When the first storage apparatus receives a write command to the primary logical volume, a package processor in a flash package allocates first physical area in the flash memory chip to first cache logical area for write data and stores the write data to the allocated first physical area. And when the package processor receives journal data creation command form the processor, allocates the first physical area to second journal area for journal data without storing journal data corresponding to the write data. | 07-10-2014 |
20140195723 | NON-VOLATILE CONFIGURATION FOR SERIAL NON-VOLATILE MEMORY - Example embodiments for configuring a serial non-volatile memory device may comprise a non-volatile configuration register to store a configuration value received from the processor, the configuration value to specify one or more attributes of a memory access operation. The configuration value may be read at least in part in response to power being applied to the memory device. | 07-10-2014 |
20140195724 | APPARATUS AND METHOD OF CONVERTING ADDRESS AND DATA OF MEMORY IN A TERMINAL - An apparatus and method of converting an address and data of a memory in a terminal. The apparatus includes a random key generator configured to generate a new random key, each time the terminal is powered on, an address mapper configured to convert an address of a memory area for data writing or reading using the random key and transmit the converted address to a data converter, and the data converter configured to convert data to be written to the memory using the converted address and convert data to read from the memory using the converted address to original data. | 07-10-2014 |
20140195725 | METHOD AND SYSTEM FOR DATA STORAGE - A system and method of storing data in a semiconductor-type non-volatile memory is described, where a physical storage address of data is made available to a user application such as a file system and where characteristics of the memory system that may be allocated on a physical or a logical basis to a user are separately characterizable as to performance, size, redundancy, or the like. A read request to the memory system may be serviced by accessing the physical address included in the read request rather than using a logical-to-physical address lookup in the memory system. Garbage collection operations may be performed on a virtual-physical-block basis to preserve the relationship between the physical address known to the user and the actual physical location of the data. | 07-10-2014 |
20140195726 | CONTROLLER, DATA STORAGE DEVICE AND DATA STORAGE SYSTEM HAVING THE CONTROLLER, AND DATA PROCESSING METHOD - A controller, a data storage device and a data storage system including the controller, and a data processing method are provided. The controller may process a plurality of instructions in parallel by including a plurality of address translation central processing units (CPUs) in a multi-channel parallel array structure, thereby improving the performance of a semiconductor memory system. | 07-10-2014 |
20140195727 | APPARATUS AND METHOD FOR GENERATING DESCRIPTORS TO REACCESS A NON-VOLATILE SEMICONDUCTOR MEMORY OF A STORAGE DRIVE DUE TO AN ERROR - A storage drive including a first module and a second module. The first module is configured to, based on an instruction signal of a first descriptor, transfer a block of data to or from a non-volatile semiconductor memory in the storage drive. The second module is configured to: monitor a status of the transfer of the block of data; determine whether an error exists with respect to the transfer of the block of data; and independent of communication with a host device, initiate generation of a second descriptor if the error exists. The second module is configured to, according to the second descriptor, perform a reaccess event including reaccessing the non-volatile semiconductor memory to again transfer the block of data to or from the non-volatile semiconductor memory. | 07-10-2014 |
20140201423 | SYSTEMS AND METHODS OF CONFIGURING A MODE OF OPERATION IN A SOLID-STATE MEMORY - Disclosed herein is an architecture that pairs a controller with a NVM (non-volatile memory) storage system. The NVM storage system includes a bridge device that communicates with the controller. In one embodiment, the bridge device allows for certain data locations (blocks, pages or units at any other granularity) in the flash dies to be (1) placed into a reserved mode where data access is prevented (2) assigned into an SLC (Single-Level Cell) mode or an MLC (Multi-Level Cell) mode in response to controller command, (3) made available for data access after the assignment of mode. This flexibility enables the controller to increase SLC mode or MLC mode data locations based on run-time conditions. In one embodiment, the assignment of the reserved data locations is performed in a way to ensure that warranty conditions imposed by the memory vendors are observed. | 07-17-2014 |
20140201424 | DATA MANAGEMENT FOR A DATA STORAGE DEVICE - Managing data stored in at least one data storage device (DSD) of a computer system where the at least one DSD includes at least one disk for storing data. A Linear Tape File System (LTFS) write or read command is generated including an LTFS block address. The LTFS block address is translated to a device address for the at least one DSD and data on a disk of the at least one DSD is written or read at the device address. | 07-17-2014 |
20140201425 | ORCHESTRATING MANAGEMENT OPERATIONS AMONG A PLURALITY OF INTELLIGENT STORAGE ELEMENTS - An apparatus and associated methodology contemplating a data storage system having a group of processor-controlled intelligent storage elements (ISEs). Each ISE in the group individually includes storage resources and a network interface. The storage resources of all the ISEs in the group collectively define a field of storage (FoS). A portion of the FoS is addressable by a remote device or by another ISE via the respective ISE's network interface. An ISE FoS structure (ISEFoS) is individually stored in nonvolatile memory within each of the ISEs in the group. Each ISEFoS contains parametric data pertaining to every ISE in the group. Orchestration logic executed by one of the ISEs of the group (a recipient ISE), in response to the recipient ISE receiving a storage management operation request via the network interface, queries the recipient ISE's ISEFoS in order to optimally determine which ISE in the group to use in executing the storage management operation request. | 07-17-2014 |
20140201426 | Page Allocation for Flash Memories - Technologies are described herein for allocating pages in a flash memory. Some example technologies may receive multiple data elements and a write request to write the multiple data elements to the flash memory. Example technologies may identify a correlation between a subset of the data elements based on correlation criteria. Example technologies may allocate neighboring pages of the flash memory for storing the subset of the data elements. Example technologies may write the subset of the data elements into the allocated pages. | 07-17-2014 |
20140201427 | STORAGE CONTROL APPARATUS, DATA STORAGE APPARATUS AND METHOD FOR STORAGE CONTROL - According to one embodiment, a storage control apparatus includes a first buffer controller and a second buffer controller. The first buffer controller is configured to store data of a first unit in each of data buffer regions, and the data of the first unit is transmitted from a host and written in a nonvolatile memory, or read from the nonvolatile memory and transmitted to the host. The second buffer controller is configured to independently transmit data of a second unit from the data buffer region corresponding to a bank prepared for transmission when data is written in the nonvolatile memory, and to independently transmit data of the second unit from a bank to be read to the data buffer region corresponding to the bank to be read when data is transmitted to the host. | 07-17-2014 |
20140201428 | CONSISTENT, DISK-BACKED ARRAYS - Disk-backed array techniques can, in some implementations, help ensure that the arrays contain consistent data. An alert can be provided if it is determined that the data in the array is, or may be, corrupted. | 07-17-2014 |
20140201429 | SSD-BLOCK ALIGNED WRITES - An SSD, comprising a mapping module and a controller, mapping module is capable of mapping a plurality of SSD-block aligned groups, each comprises a specific sequence of LBAs, to SSD blocks. The controller is capable of determining whether a LBA referenced in an incoming write request is a first LBA in a respective group, and if so, the controller is capable of: opening an ongoing SSD-block aligned write session; assigning a SSD block to the session; and recording in the session's data an indication of which LBA is associated with the write data that was saved to the SSD. In case the LBA referenced in the incoming write request is not the first LBA in the respective group, but is a successor of a latest-saved LBA of the group, storing the write data in sequence with a latest used segment of the SSD-block that was assigned to the group. | 07-17-2014 |
20140201430 | SNAPSHOTTING OF A PERFORMANCE STORAGE SYSTEM IN A SYSTEM FOR PERFORMANCE IMPROVEMENT OF A CAPACITY OPTIMIZED STORAGE SYSTEM - A system for storing data comprises a performance storage system for storing one or more data items. A data item of the one or more data items comprises a data file or a data block. The system further comprises a segment storage system for storing a snapshot of a stored data item of the one or more data items in the performance storage system. The taking of the snapshot of the stored data item enables recall of the stored data item as stored at a time of the snapshot. At least one newly stored segment is stored as a reference to a previously stored segment. | 07-17-2014 |
20140201431 | DISTRIBUTED PROCEDURE EXECUTION AND FILE SYSTEMS ON A MEMORY INTERFACE - Nonvolatile memory (e.g., flash memory, solid-state disk) is included on memory modules that are on a DRAM memory channel. Nonvolatile memory residing on a DRAM memory channel may be integrated into the existing file system structures of operating systems. The nonvolatile memory residing on a DRAM memory channel may be presented as part or all of a distributed file system. Requests and/or remote procedure call (RPC) requests, or information associated with requests and/or RPCs, may be routed to the memory modules over the DRAM memory channel in order to service compute and/or distributed file system commands. | 07-17-2014 |
20140201432 | PERSISTENT BLOCK STORAGE ATTACHED TO MEMORY BUS - A method of configuring a computer memory system includes receiving a request from customized software driver or a BIOS extension software or a customized legacy BIOS or a customized UEFI PMM extension software or a customized UEFI BIOS, scanning memory module sockets in response to the request, recognizing memory modules in the memory module sockets, the memory modules being made of, at least in part, persistent memory modules (PMMs), configuring the PMMs to be invisible to the OS, and storing the mapping information to a designated protected persistent memory area, and presenting the PMMs as a persistent block storage to the OS. | 07-17-2014 |
20140201433 | SELECTIVE ACTIVATION OF PROGRAMMING SCHEMES IN ANALOG MEMORY CELL ARRAYS - A method for data storage includes defining a first programming scheme that programs a group of analog memory cells while reducing interference caused by at least one memory cell that neighbors the group, and a second programming scheme that programs the group of the analog memory cells and does not reduce all of the interference reduced by the first programming scheme. One of the first and second programming schemes is selected based on a criterion defined with respect to the analog memory cells. Data is stored in the group of the analog memory cells using the selected programming scheme. | 07-17-2014 |
20140207996 | HYBRID HARD DISK DRIVE HAVING A FLASH STORAGE PROCESSOR - An apparatus is described that is configured to control operations in a hybrid hard disk drive. In an implementation, the apparatus includes a hybrid flash storage processor connected to the host interface that is configured to communicatively couple a flash storage component and to a hard disk integrated circuit chip. The integrated circuit chip includes a read/write channel device configured to communicatively couple to a hard disk drive assembly and a hard disk drive controller operatively coupled to the read/write channel device. The hard disk drive controller is configured to operate the read/write channel device to store and to retrieve data on the hard disk drive assembly. The flash storage processor is configured to furnish a command to the integrated circuit chip when the command represents an instruction for accessing the hard disk drive assembly and is configured to access the flash storage component when the command represents an instruction for accessing the flash storage component. | 07-24-2014 |
20140207997 | PREGROOMER FOR STORAGE ARRAY - Techniques are disclosed relating to arranging data on storage media. In one embodiment, a computer system is configured to access a storage array that includes a plurality of storage blocks. The computer system executes a first set of processes and a second set of processes, where the first set of processes operates on selected ones of the plurality of storage blocks to increase a likelihood that the selected storage blocks are operated on by the second set of processes. In some embodiments, the second set of processes determines whether to operate on a storage block based on an amount of invalid data within the storage block. In such an embodiment, the first set of processes increases a likelihood that the storage block is operated on by increasing the amount of invalid data within the storage block. | 07-24-2014 |
20140207998 | SYSTEM AND METHOD OF WEAR LEVELING FOR A NON-VOLATILE MEMORY - In an architecture of wear leveling for a non-volatile memory composed of plural storage units, a translation layer is configured to translate a logical address provided by a host to a physical address of the non-volatile memory. A cold-block table is configured to assign a cold block or blocks in at least one storage unit, the cold block in a given storage unit having an erase count being less than erase counts of non-cold blocks in the given storage unit. The logical addresses and the associated physical addresses of the cold blocks are recorded in the cold-block table, thereby building a cold-block pool composed of the cold blocks. | 07-24-2014 |
20140207999 | PERFORMING STAGING OR DESTAGING BASED ON THE NUMBER OF WAITING DISCARD SCANS - A controller receives a request to perform staging or destaging operations with respect to an area of a cache. A determination is made as to whether more than a threshold number of discard scans are waiting to be performed. The controller avoids satisfying the request to perform the staging or the destaging operations or a read hit with respect to the area of the cache, in response to determining that more than the threshold number of discard scans are waiting to be performed. | 07-24-2014 |
20140208000 | Techniques for Surfacing Host-Side Flash Storage Capacity to Virtual Machines - Techniques for surfacing host-side flash storage capacity to a plurality of VMs running on a host system are provided. In one embodiment, the host system creates, for each VM in the plurality of VMs, a flash storage space allocation in a flash storage device that is locally attached to the host system. The host system then causes the flash storage space allocation to be readable and writable by the VM as a virtual flash memory device. | 07-24-2014 |
20140208001 | Techniques for Achieving Crash Consistency when Performing Write-Behind Caching Using a Flash Storage-Based Cache - Techniques for achieving crash consistency when performing write-behind caching using a flash storage-based cache are provided. In one embodiment, a computer system receives from a virtual machine a write request that includes data to be written to a virtual disk and caches the data in a flash storage-based cache. The computer system further logs a transaction entry for the write request in the flash storage-based cache, where the transaction entry includes information usable for flushing the data from the flash storage-based cache to a storage device storing the virtual disk. The computer system then communicates an acknowledgment to the VM indicating that the write request has been successfully processed. | 07-24-2014 |
20140208002 | MULTILEVEL CELL NONVOLATILE MEMORY SYSTEM - A multilevel cell (MLC) nonvolatile memory system including a plurality of memory cells each cell storing first bit data and second bit data, and a controller programming the plurality of memory cells on a page-by-page basis, the controller programming original data to an original block and programming copy data that is the same as the original data to a mirroring block, wherein first bit page data and second bit page data of the original data are programmed to memory cells connected to the same word line, but the first bit page data and second bit page data of the copy data are programmed to memory cells connected to different word lines. | 07-24-2014 |
20140208003 | VARIABLE-SIZE FLASH TRANSLATION LAYER - A method for using a variable-size flash transition layer is disclosed. Step (A) receives a read request to read data corresponding to a logical block address from a nonvolatile memory. Step (B) reads a particular entry of a map to obtain (i) a physical address of a particular page of the nonvolatile memory, (ii) an offset in the particular page to compressed data previously stored and (iii) a length of the compressed data. The particular entry is associated with the logical block address. Step (C) converts the offset and the length to (i) an address of a given read unit in the particular page and (ii) a number of the read units to be read. Step (D) reads from the particular page at most the number of the read units starting from the given read unit. An offset and length granularity are finer than one read unit. | 07-24-2014 |
20140208004 | TRANSLATION LAYER PARTITIONED BETWEEN HOST AND CONTROLLER - A method for using a partitioned flash transition layer is disclosed. Step (A) receives, at an apparatus from a host, a write command having first write data. Step (B) generates second write data by compressing the first write data in the apparatus. The second write data generally has a variable size. Step (C) stores the second write data at a physical location in a nonvolatile memory. The physical location is a next unwritten location. Step (D) returns, from the apparatus to the host in response to the write command, an indication of the physical location. | 07-24-2014 |
20140208005 | System, Method and Computer-Readable Medium for Providing Selective Protection and Endurance Improvements in Flash-Based Cache - A cache controller includes a cache memory distributed across multiple solid-state storage units in which cache line fill operations are applied sequentially in a defined manner and write operations are protected by a RAID-5 (striping plus parity) scheme upon a stripe reaching capacity. The cache store is responsive to data from a storage controller managing a primary data store. The cache store arranges the data differently based on the origin or type of data received at the cache interface. Line fill operations are placed in the cache memory without generating and storing corresponding parity information. When a sufficient number of write operations fill strips that constitute a full stripe are present in cache store, a corresponding parity strip is generated and stored in a strip location designated for storage of the parity information. | 07-24-2014 |
20140208006 | APPARATUS AND METHOD FOR EXTENDING MEMORY IN TERMINAL - An apparatus and a method capable of selectively extending a memory in a terminal are provided. The apparatus includes a socket unit into which an external memory having a built-in Random Access Memory (RAM) is inserted, and a controller that performs a control operation for moving data stored in a RAM of the terminal to the RAM of the external memory and for securing available space of the RAM of the terminal, when the external memory having the built-in RAM is inserted into the socket unit. | 07-24-2014 |
20140208007 | MANAGEMENT OF AND REGION SELECTION FOR WRITES TO NON-VOLATILE MEMORY - Management of and region selection for writes to non-volatile memory of an SSD improves performance, reliability, unit cost, and/or development cost of an SSD. A controller receives and determines characteristics of writes (e.g. by analyzing the write data, the write data source, and/or by receiving a hint) and selects a region based on the determined characteristics and properties of regions of non-volatile memory. For example, a controller receives writes determined to be read-only data and selects regions of non-volatile memory containing cells that are likely to have write failures. By placing read-only data in write failure prone regions, the likelihood of an error is reduced, thus improving reliability. As another example, a controller receives writes hinted to be uncompressible and selects regions of non-volatile memory containing uncompressible data. | 07-24-2014 |
20140208008 | ELECTRONIC CONTROL UNIT FOR VEHICLE AND DATA COMMUNICATION METHOD - An electronic control unit for a vehicle includes a nonvolatile memory that is capable of erasing and writing data electrically, and capable of receiving a program to be written into the nonvolatile memory in units of a predetermined size by means of communication using a communication buffer. The electronic control unit for the vehicle uses communication buffers, the number of which is greater than the number of communication buffers used in an in-vehicle communication environment, to receive the program. | 07-24-2014 |
20140208009 | STORAGE SYSTEM - A storage system in an embodiment of this invention comprises a non-volatile storage area for storing write data from a host, a cache area capable of temporarily storing the write data before storing the write data in the non-volatile storage area, and a controller that determines whether to store the write data in the cache area or to store the write data in the non-volatile storage area without storing the write data in the cache area, and stores the write data in the determined area. | 07-24-2014 |
20140208010 | SUB-LUN INPUT/OUTPUT PROFILING FOR SSD DEVICES - A read/write ratio for each of a plurality of data segments classified in a hot category as hot data segments is determined. Each of the plurality of hot data segments is ordered by the read/write ratio in a descending order. Each of a plurality of available SSD devices is ordered by a remaining life expectancy in an ascending order. Those of the plurality of hot data segments are matched with those of the plurality of hot data segments with those of the plurality of available SSD devices such that a hot data segment having a higher read/write ratio is provided to an SSD device having a smaller remaining life expectancy than another hot data segment having a lower read/write ratio. | 07-24-2014 |
20140208011 | SUB-LUN INPUT/OUTPUT PROFILING FOR SSD DEVICES - A read/write ratio for each of a plurality of data segments classified in a hot category as hot data segments is determined. Each of the plurality of hot data segments is ordered by the read/write ratio in a descending order. Each of a plurality of available SSD devices is ordered by a remaining life expectancy in an ascending order. Those of the plurality of hot data segments are matched with those of the plurality of hot data segments with those of the plurality of available SSD devices such that a hot data segment having a higher read/write ratio is provided to an SSD device having a smaller remaining life expectancy than another hot data segment having a lower read/write ratio. | 07-24-2014 |
20140208012 | VIRTUAL DISK REPLICATION USING LOG FILES - Techniques involving replication of virtual machines at a target site are described. One representative technique includes an apparatus including a virtual machine configured to provide storage access requests targeting a virtual disk. A storage request processing module is coupled to the virtual machine to receive the storage access requests and update the virtual disk as directed by the storage access requests. A replication management module is coupled to the virtual machine to receive the storage access requests in parallel with the storage request processing module, and to store information associated with the storage access requests in a log file(s). The log file may be transferred to a destination as a recovery replica of at least a portion of the virtual disk. | 07-24-2014 |
20140208013 | MEMORY SYSTEM - A memory system includes a volatile first storing unit, a nonvolatile second storing unit, and a controller. The controller performs data transfer, stores management information including a storage position of the data stored in the second storing unit into the first storing unit, and performs data management while updating the management information. The second storing unit has a management information storage area for storing management information storage information including management information in a latest state and a storage position of the management information. The storage position information is read by the controller during a startup operation of the memory system and includes a second pointer indicating a storage position of management information in a latest state in the management information storage area and a first pointer indicating a storage position of the second pointer. The first pointer is stored in a fixed area in the second storing unit and the second pointer is stored in an area excluding the fixed area in the second storing unit. | 07-24-2014 |
20140208014 | OPERATING A MEMORY - For enabling an efficient storage of received compressed data, an additional lossless compression is applied to the compressed data to obtain binary digits. The lossless compression is configured to result, on an average, in a higher percentage of binary digits having a first value than binary digits having a second value. The obtained binary digits are caused to be stored in a memory, wherein the storage of binary digits of the first value require less energy than or an equal amount of energy as the storage of binary digits of the second value. | 07-24-2014 |
20140215122 | NON-VOLATILE MEMORY PROGRAMMING DATA PRESERVATION - A system and methods for programming a set of data onto non-volatile memory elements, maintaining copies of the data pages to be programmed, as well as surrounding data pages, internally or externally to the memory circuit, verifying programming correctness after programming, and upon discovering programming error, recovering the safe copies of the corrupted data to be reprogrammed in alternative non-volatile memory elements. Additionally, a system and methods for programming one or more sets of data across multiple die of a non-volatile memory system, combining data pages across the multiple die by means such as the XOR operation prior to programming the one or more sets of data, employing various methods to determine the correctness of programming, and upon identifying data corruption, recovering safe copies of data pages by means such as XOR operation to reprogram the pages in an alternate location on the non-volatile memory system. | 07-31-2014 |
20140215123 | Controller-Opaque Communication with Non-Volatile Memory Devices - The disclosure is directed to a system and method for controlling a non-volatile memory (NVM) device with controller-opaque commands issued by a host. A device controller is configured to receive a command script from a host. The device controller executes one or more commands of the command script including sending one or more operations of the command script to a NVM device in communication with the device controller. The device controller is enabled to provide at least a portion of the one or more operations from the command script to be executed by the NVM device without any embedded knowledge by the device controller of the actions of and/or consequences of the operations, thereby allowing the host to access NVM commands that are not necessarily supported by the device controller. | 07-31-2014 |
20140215124 | SYSTEM AND METHOD FOR ADAPTIVE BIT RATE PROGRAMMING OF A MEMORY DEVICE - The disclosure relates to an electronic memory system, and more specifically, to a system for adaptive bit rate programming of a memory device, and a method for adaptive bit rate programming of a memory device. According to an embodiment, a system for adaptive bit rate programming of a memory device including a plurality of memory cells is provided, wherein the memory cells are configured to be electrically programmable by application of a current supplied by a current source, the system including selection devices for selecting memory cells for programming based on availability of current from the current source. | 07-31-2014 |
20140215125 | LOGICAL BLOCK ADDRESS REMAPPING - A method and system is disclosed that remaps logical block addresses (LBAs) for defragmentation that is managed at the storage device level. The remapping may include sequentially remapping LBAs where individual files are remapped so that each file is referenced by sequential LBAs. The remapping of LBAs may be performed without changes to the physical location of data. | 07-31-2014 |
20140215126 | Data Randomization in 3-D Memory - In a nonvolatile memory array, such as a three-dimensional array of charge-storage memory cells, data is randomized so that data of different strings along the same bit line are randomized using different keys and portions of data along neighboring word lines are randomized using different keys. Keys may be rotated so that data of a particular word line is randomized according to different keys in different strings. | 07-31-2014 |
20140215127 | APPARATUS, SYSTEM, AND METHOD FOR ADAPTIVE INTENT LOGGING - A system and method is provided for implementing adaptive intent logging in a file system of a computing device. The file system receives an I/O request from one more applications executing on the computing device. The file system includes one or more intent logging modules that adaptively and/or selectively write detail data included in an I/O request directly to storage pool device or an intent log that based on logging rules and/or the detail data associated with the request. The intent logging modules minimizes processing delays when an application issues multiple synchronous requests, such as small write request. | 07-31-2014 |
20140215128 | ADAPTIVE INITIAL PROGRAM VOLTAGE FOR NON-VOLATILE MEMORY - When programming a set of non-volatile storage elements using a multi-stage programming process, a series of programming pulses are used for each stage. The magnitude of the initial program pulse for the current stage being performed is dynamically set as a function of the number of program pulses used for the same stage of the multi-stage programming process when programming non-volatile storage elements connected to on one or more previously programmed word lines. | 07-31-2014 |
20140215129 | COOPERATIVE FLASH MEMORY CONTROL - This disclosure provides for host-controller cooperation in managing NAND flash memory. The controller maintains information for each erase unit which tracks memory usage. This information assists the host in making decisions about specific operations, for example, initiating garbage collection, space reclamation, wear leveling or other operations. For example, metadata can be provided to the host identifying whether each page of an erase unit has been released, and the host can specifically then command each of consolidation and erase using direct addressing. By redefining host-controller responsibilities in this manner, much of the overhead association with FTL functions can be substantially removed from the memory controller, with the host directly specifying physical addresses. This reduces performance unpredictability and overhead, thereby facilitating integration of solid state drives (SSDs) with other forms of storage. The disclosed techniques are especially useful for direct-attached and/or network-attached storage. | 07-31-2014 |
20140215130 | CLOCK SWITCHING METHOD, MEMORY CONTROLLER AND MEMORY STORAGE APPARATUS - A clock switching method for a memory storage apparatus is provided. The method includes: setting a value of the clock as a first operation frequency when an operation mode is switched to an initial state; determining whether a first continuous accessing time of accessing continuously a rewritable non-volatile memory module is larger than a first setting value during a period in which the operation mode is at the initial state; re-setting the value of the clock as a second operation frequency, which is smaller than the first operation frequency, to switch the operation mode to a power saving state if the first continuously access time is larger than the first setting value; and re-setting the value of the clock as the first operation frequency to switch the operation mode to a general state during a period in which the operation mode is at the power saving state. | 07-31-2014 |
20140215131 | CONTROLLING METHOD, MEMORY CONTROLLER, AND DATA TRANSMISSION SYSTEM - A controlling method of a rewritable non-volatile memory module, and a memory controller and a data transmission system using the same are provided. The controlling method includes following steps. A command is received from a host system. Whether the command is a configuration command is determined according to a command code of the command. A plurality of action information in the configuration command and an execution sequence corresponding to the action information are analyzed. The action information is executed according to the execution sequence. Each action information is configured to request the rewritable non-volatile memory module to execute a predetermined action. Thereby, the functionality of a memory storage device can be dynamically extended. | 07-31-2014 |
20140215132 | DATA WRITING METHOD, MEMORY CONTROLLER AND MEMORY STORAGE DEVICE - A data writing method, a memory controller, and a memory storage device are provided. The method is applied to control a rewritable non-volatile memory module that includes two memory units. The method includes: configuring a plurality of logical addresses and mapping the logical addresses to at least parts of physical erasing units in the two memory units; receiving a writing command from a host system to instruct to write data into one of the logical addresses; writing the data into a physical erasing unit in the two memory units; determining one of the memory units where the physical erasing unit belongs to; if the physical erasing unit belongs to one of the memory units, erasing another physical erasing unit in the other memory unit while writing the data into the physical erasing unit. Accordingly, a speed of writing data into the memory storage device by the host system is accelerated. | 07-31-2014 |
20140215133 | MEMORY SYSTEM AND RELATED BLOCK MANAGEMENT METHOD - A memory system manages memory blocks of a nonvolatile memory device by determining at least one memory block property of a selected memory block among the multiple memory blocks in the nonvolatile memory device, storing memory block property information indicating the at least one memory block property, arranging a free memory block list based on the stored memory block property information, and designating a free memory block from the arranged free memory block list as an active memory block, wherein the designation of the free memory block as an active memory block is based on an ordering of the free memory block list. | 07-31-2014 |
20140215134 | MAINBOARD AND METHOD OF BACKING UP OF BASEBOARD MANAGEMENT CONTROLLER - A mainboard includes a selecting module, a calculating module, and a backup module. The selecting module selects a highest backup sequence group. The calculating module checks whether current backup time arrives, and calculates memory space of partitions belonging to the highest backup sequence group when the current backup time arrives. The backup module checks whether residual space in a first flash is enough according to the calculated memory space, and backs up the partitions belonging to the highest backup sequence group originally in a second flash to the first flash if the residual space in the first flash is enough. A method of the mainboard backing up of a baseboard management controller is also provided, which provides backing up for the baseboard management controller. | 07-31-2014 |
20140215135 | MEMORY DEVICE, MEMORY SYSTEM, AND CONTROL METHOD PERFORMED BY THE MEMORY SYSTEM - Provided are a memory device, a memory system, and a control method performed by the memory system. The control method includes operations of generating, by a first function block of the memory system, a main request comprising a first sub-request for a first operation that is requested by an external source and a second sub-request for a second operation that is dependent upon a processing result of the first operation; processing, by a second function block of the memory system, the first sub-request or the second sub-request; and when a processing result of the first sub-request performed by the second function block is a fail, transmitting, by a third function block of the memory system, abortion information to the first function block in response to the main request, regardless of processing the second sub-request. | 07-31-2014 |
20140215136 | METHODS AND APPARATUS FOR STORING DATA TO A SOLID STATE STORAGE DEVICE BASED ON DATA CLASSIFICATION - Systems and methods for storing data to a non-volatile storage device are provided. A request to store data to the storage device at a given address corresponding to one of a plurality of regions of the storage device is received. A region classification map associated with the storage device associates a classification with each of the plurality of regions. A determination is made based on the region classification map as to which classification is associated with the one of the plurality of regions corresponding to the given address. The data is stored at the given address in response to determining that the one of the plurality of regions is associated with a first classification. The data is stored to an alternate location in response to determining that the one of the plurality of regions is associated with a second classification. | 07-31-2014 |
20140215137 | METHODS FOR IMPLEMENTATION OF AN ARCHIVING SYSTEM WHICH USES REMOVABLE DISK STORAGE SYSTEM - According to the disclosure, embodiments of archival storage system are disclosed. The archival storage system includes two or more removable disk drives that provide random access and are readily expandable. One or more application servers can store archival data to the one or more removable disk drives. Further, the archival storage system provides intelligent archiving by adapting storage requirements to the type of data being archived by the application servers. Methods for storing archival data are also provided that store archival information in removable disk drives. | 07-31-2014 |
20140215138 | MEMORY BUFFER WITH ONE OR MORE AUXILIARY INTERFACES - The present memory system includes a memory buffer having an interface arranged to buffer data and/or command bytes being written to or read from the RAM chips residing on a DIMM by a host controller. The memory buffer further includes at least one additional interface arranged to buffer data and/or command bytes between the host controller or RAM chips and one or more external devices coupled to the at least one additional interface. For example, the memory buffer may include a SATA interface and be arranged to convey data between the host controller or RAM chips and FLASH memory devices coupled to the SATA interface. The additional interfaces may include, for example, a SATA interface, an Ethernet interface, an optical interface, and/or a radio interface. | 07-31-2014 |
20140215139 | MEMORY DEVICES HAVING SPECIAL MODE ACCESS - Memory devices are provided that include special operating modes accessible upon receipt of a particular message from a host. One device includes a memory array, a special mode enable register, and a controller. When the controller receives a register write command to write first data into the special mode enable register and the memory device does so, the memory device operates in a first mode. When the controller receives a register write command to write second data into the special mode enable register and the memory device does so, the memory device operates in a second mode. | 07-31-2014 |
20140223071 | METHOD AND SYSTEM FOR REDUCING WRITE LATENCY IN A DATA STORAGE SYSTEM BY USING A COMMAND-PUSH MODEL - A data storage system is provided that implements a command-push model that reduces latencies. The host system has access to a nonvolatile memory (NVM) device of the memory controller to allow the host system to push commands into a command queue located in the NVM device. The host system completes each IO without the need for intervention from the memory controller, thereby obviating the need for synchronization, or handshaking, between the host system and the memory controller. For write commands, the memory controller does not need to issue a completion interrupt to the host system upon completion of the command because the host system considers the write command completed at the time that the write command is pushed into the queue of the memory controller. The combination of all of these features results in a large reduction in overall latency. | 08-07-2014 |
20140223072 | Tiered Caching Using Single Level Cell and Multi-Level Cell Flash Technology - A data storage system includes two tiers of caching memory. Cached data is organized into cache windows, and the cache windows are organized into a plurality of priority queues. Cache windows are moved between priority queues on the basis of a threshold data access frequency; only when both a cache window is flagged for promotion and a cache window is flagged for demotion will a swap occur. | 08-07-2014 |
20140223073 | MANAGEMENT OF RANDOM CACHE READ OPERATIONS - A method and system are disclosed that monitor and control random cache read operations. Random cache read operation may occur until the expiration of a timer. Upon expiration of the timer, the current random cache read sequence is terminated and new received read commands will not use this sequence. A flash controller may either use a page read operation or initiate a new random cache read sequence. | 08-07-2014 |
20140223074 | NON-VOLATILE MEMORY MONITORING - The invention provides a technique for managing write operations issued to a non-volatile memory included in a wireless device. A monitor software application executes on the wireless device and is configured to determine that a number of write operations issued to the non-volatile memory is greater than or equal to a write operation threshold associated with the non-volatile memory. In response, at least one application is isolated as the application responsible for issuing excessive write operations. The isolation can be carried out locally on the wireless device, or the isolation can be carried out remotely at a server by sending information about the write operations to the server. The monitor then limits additional write operations from being issued to the non-volatile memory so as to protect the non-volatile memory from becoming corrupted or inoperable. | 08-07-2014 |
20140223075 | PHYSICAL-TO-LOGICAL ADDRESS MAP TO SPEED UP A RECYCLE OPERATION IN A SOLID STATE DRIVE - A method for increasing performance of a recycle operation in a solid state drive, comprising the steps of (A) creating an empty physical-to-logical address map in a memory having a plurality of entry locations, (B) filling one of the plurality of entry locations with a physical page address associated with each data write operation to a block, where the block has a plurality of pages, (C) writing the physical-to-logical address map to a last of the plurality of pages during a write to a second to last page of the block and (D) initiating a recycle operation of the block by reading the address map to determine whether the pages contain valid data. | 08-07-2014 |
20140223076 | CONTROLLING METHOD, CONNECTOR, AND MEMORY STORAGE DEVICE - A controlling method, a connector, and a memory storage device are provided. The controlling method includes following steps. A connection between the memory storage device and a host system is established. A first command is received from the host system and stored into a command queue. The command queue includes at least one second command after the first command is stored into the command queue. Whether a command number of the second commands is greater than a threshold is determined. The threshold is greater than 1. If the command number is greater than the threshold, a using right of the connection is obtained and a second command is executed by the memory storage device. If the command number is not greater than the threshold, a command from the host system is waited for. The using right of the connection belongs to the host system. Thereby, the system efficiency is improved. | 08-07-2014 |
20140223077 | MEMORY SYSTEM - According to one embodiment, a memory system includes a nonvolatile memory, a command managing unit, a command issuing unit, a data control unit and a command monitoring unit. The command issuing unit issues a command received by the command managing unit to the nonvolatile memory. The data control unit controls a reading or writing of data to the nonvolatile memory. The command monitoring unit monitors the command managing unit and outputs a receipt signal to the data control unit when the command managing unit receives the command. The data control unit interrupts the reading or writing when receiving the receipt signal, issues the command from the command issuing unit to the nonvolatile memory, and resumes the reading or writing after issuing the command. | 08-07-2014 |
20140223078 | VIRTUAL OTP PRE-PROGRAMMING - Aspects of virtual one-time programmable (OTP) memory pre-programming are described. A device may include a logical sink destination, an OTP memory map, a virtual memory map, and a comparator. The OTP memory map may store one or more OTP logical values, and the virtual memory map may store one or more default virtual logical values. Generally, the virtual memory map may be predefined for various representative OTP scenarios including test and customer-specific values. Certain portions or outputs of the logical values stored in the OTP memory map and the virtual memory map may be compared by the comparator, and the logical result of the comparison may be output to the logical sink destination. In certain aspects, the portions or outputs of OTP and virtual memory maps that are compared may be determined based on various factors such as strap option settings, temperatures, voltages, or register values of the device. | 08-07-2014 |
20140223079 | NON-VOLATILE MEMORY APPARATUS AND OPERATING METHOD THEREOF - A non-volatile memory (NVM) apparatus and an operation method thereof are provided. A mapping table in a main memory is divided into a plurality of sub-mapping tables according to logical address groups. When an access command of a host is processed by the NVM apparatus, at least one corresponding sub-mapping table is selected from the sub-mapping tables according to a logical address of the access command. If the at least one corresponding sub-mapping table is required to be rebuilt, then the at least one corresponding sub-mapping table is rebuilt, and the logical address of the access command is converter for accessing the NVM apparatus according to the at least one corresponding sub-mapping table which has been rebuilt. | 08-07-2014 |
20140223080 | NON-VOLATILE MEMORY DEVICE, ELECTRONIC CONTROL SYSTEM, AND METHOD OF OPERATING THE NON-VOLATILE MEMORY DEVICE - Provided are a non-volatile memory device, an electronic control system, and a method of operating the non-volatile memory device. A non-volatile memory device according to an embodiment of the present invention includes a first NAND cell array including a first group of pages, and a second NAND cell array including a second group of pages. A plurality of X-decoders are at least one-to-one connected to the first and second NAND cell arrays. A control logic controls the plurality of X-decoders to simultaneously sense data of a first page corresponding to a start address from among the first group of pages, and data of a second page subsequent to the first page from among the second group of pages. | 08-07-2014 |
20140223081 | POINT IN TIME COPY OPERATIONS FROM SOURCE VOLUMES TO SPACE EFFICIENT TARGET VOLUMES IN TWO STAGES VIA A NON-VOLATILE STORAGE - A request is received to perform a point in time copy operation from a source volume to a space efficient target volume. A controller copies data stored in a group of data storage units, from the source volume to a non-volatile storage, to preserve the point in time copy operation. A background process asynchronously copies the data from the non-volatile storage to the space efficient target volume to commit a physical point in time copy of the data from the source volume to the target volume. | 08-07-2014 |
20140223082 | METHOD OF MANAGING THE ENDURANCE OF NON-VOLATILE MEMORIES - The invention relates to a method for managing the endurance of a data storage system provided with a set of sectors endowed with a guaranteed native endurance capacity (G), comprising the steps consisting in:—partitioning said data storage system into a plurality of work sectors, and into a plurality of replacement sectors able to form an endurance reservoir, certain of the work sectors being intended to be replaced by replacement sectors when said work sectors are expended after a certain number of programming and/or erasure cycles;—defining an address management area making it possible to retrieve the location of the replacement sectors assigned to expended work sectors;—determining, sector by sector, whether a current work sector is physically expended, and executing a step of replacing this work sector by a replacement sector, only when said current work sector is declared physically expended. This method of managing endurance is in particular characterized in that in order to measure the expenditure of a sector, automatic reading of the quality of erasure of the memory points of the sector with respect to a severized reading criterion (margin Vref.) is carried out, that is to say one which is more severe than a normal criterion (Normal Vref.). | 08-07-2014 |
20140223083 | ZONE-BASED DEFRAGMENTATION METHODS AND USER DEVICES USING THE SAME - A defragmentation method of a user device which includes a host and a nonvolatile storage device includes: determining whether fragments of a first file stored at the nonvolatile storage device are in a same logical address zone; and executing defragmentation on the fragments of the first file if the fragments of the first file are in different logical address zones by moving the fragments of the first file to a logical address space corresponding to at least one of the different logical address zones. | 08-07-2014 |
20140223084 | MEMORY SYSTEM AND RELATED METHOD OF OPERATION - A method of operating a memory system comprises determining whether a write request from a host is a random write request, and as a consequence of determining that the write request is a random write request, programming a lower page of a selected word line of a nonvolatile memory device with restorable data of the nonvolatile memory device, and programming an upper page of the selected word line with write data corresponding to the write request after programming the lower page. | 08-07-2014 |
20140223085 | Memory Systems and Operating Methods of Memory Controllers - A memory system is provided which includes a nonvolatile memory; and a controller configured to control the nonvolatile memory, wherein the controller comprises a voltage detector configured to detect a level of a power supply voltage; and wherein when a level of the power supply voltage is lower than a first threshold value, the controller issues a reset command to the nonvolatile memory and then performs a reset operation. | 08-07-2014 |
20140223086 | RAPID READING FROM MEMORY DEVICES - The invention generally relates to rapid reading of data from multi-level cell (MLC) memory devices. Information is stored in a way that allows all of the bit-space to be used but that also allows single-read-per-cell retrieval. Data is triaged into high priority data and low priority data. The high priority data is then stored in an MLC memory device with one bit per cell. This data can them be read from the MLC cells by one comparison operation on each cell, accomplishing all of the required read operations in parallel in the time it takes to perform a single comparison. Low priority data is stored in the remaining bit-space of the cells, to take full advantage of all of the available bit-space of the cells. | 08-07-2014 |
20140223087 | MULTI-PARTITIONING OF MEMORIES - Various embodiments comprise apparatuses and methods including a method of reconfiguring partitions in a memory device as directed by a host. The method includes managing commands through a first interface controller to mapped portions of a first memory not having an attribute enhanced set, and mapping portions of a second memory having the attribute enhanced set through a second interface controller. Additional apparatuses and methods are described. | 08-07-2014 |
20140223088 | INFORMATION PROCESSING DEVICE, EXTERNAL STORAGE DEVICE, HOST DEVICE, RELAY DEVICE, CONTROL PROGRAM, AND CONTROL METHOD OF INFORMATION PROCESSING DEVICE - According to the embodiments, an external storage device switches to an interface controller for supporting only a read operation of nonvolatile memory when a shift condition for shifting to a read only mode is met. A host device switches to an interface driver for supporting only the read operation of the nonvolatile memory when determining to recognize as read only memory based on information acquired from the external storage device. | 08-07-2014 |
20140223089 | METHOD AND DEVICE FOR STORING DATA IN A FLASH MEMORY USING ADDRESS MAPPING FOR SUPPORTING VARIOUS BLOCK SIZES - The present invention relates to a method and device for storing data in a flash memory using address mapping for supporting various block sizes. A storage device determines the size of a block that a host system uses on the basis of the size of data that the host system requests and uses the determined block size as a mapping unit. Additionally, the storage device divides a logical address space into at least one area, and maps an address using the minimum units of different mappings in each divided area. | 08-07-2014 |
20140237162 | NON-VOLATILE MEMORY CHANNEL CONTROL USING A GENERAL PURPOSE PROGRAMMABLE PROCESSOR IN COMBINATION WITH A LOW LEVEL PROGRAMMABLE SEQUENCER - A system includes a control processor, a non-volatile memory device interface, and a micro-sequencer. The control processor may be configured to receive commands and send responses via a command interface. The non-volatile memory device interface may be configured to couple the system to one or more non-volatile memory devices. The micro-sequencer is generally coupled to (i) the control processor and (ii) the non-volatile memory device interface. The micro-sequencer includes a control store readable by the micro-sequencer and writable by the control processor. In response to receiving a particular one of the commands, the control processor is enabled to cause the micro-sequencer to begin executing at a location in the control store according to the particular command and the micro-sequencer is enabled to perform at least a portion of the particular command according to a protocol of the one or more non-volatile memory devices coupled to the non-volatile memory device interface. | 08-21-2014 |
20140237163 | REDUCING WRITES TO SOLID STATE DRIVE CACHE MEMORIES OF STORAGE CONTROLLERS - Methods and structure are provided for reducing the number of writes to a cache of a storage controller. One exemplary embodiment includes a storage controller that has a non-volatile flash cache memory, a primary memory that is distinct from the cache memory, and a memory manager. The memory manager is able to receive data for storage in the cache memory, to generate a hash key from the received data, and to compare the hash key to hash values for entries in the cache memory. The memory manager can write the received data to the cache memory if the hash key does not match one of the hash values. Also, the memory manager can modify the primary memory instead of writing to the cache if the hash key matches a hash value, in order to reduce the amount of data written to the cache memory. | 08-21-2014 |
20140237164 | HYBRID DRIVE THAT IMPLEMENTS A DEFERRED TRIM LIST - A hybrid drive controller maintains a deferred trim list that holds a subset of logical addresses of writes performed on magnetic disks. For example, if a write command is issued to an LBA space that overlaps a portion stored in flash memory and the write is to be performed on the magnetic disks, the trimming of the overlapping portion in the flash memory will be deferred. Instead of trimming, the logical addresses associated with the overlapping portion will be added to the deferred trim list and trimming of the logical addresses in the deferred trim list will be carried out at a later time, asynchronous to the write that caused them to be added to the list. | 08-21-2014 |
20140237165 | MEMORY CONTROLLER, METHOD OF OPERATING THE SAME AND MEMORY SYSTEM INCLUDING THE SAME - A memory controller controlling a nonvolatile memory device having a plurality of memory blocks as a data storage space includes an error detection and correction circuit and a reclaim control unit. The error detection and correction circuit receives data from a memory block and calculates a comparison result by comparing a bit error rate of the received data and a predetermined value. The reclaim control unit determines whether or not to perform a read reclaim operation depending on the comparison result and a read voltage used to read the data. The read reclaim operation copies the data to a memory block different from a memory block having stored the data. | 08-21-2014 |
20140237166 | HIGHER-LEVEL REDUNDANCY INFORMATION COMPUTATION - Higher-level redundancy information computation enables a Solid-State Disk (SSD) controller to provide higher-level redundancy capabilities to maintain reliable operation in a context of failures of non-volatile (e.g. flash) memory elements during operation of an SSD. A first portion of higher-level redundancy information is computed using parity coding via an XOR of all pages in a portion of data to be protected by the higher-level redundancy information. A second portion of the higher-level redundancy information is computed using a weighted-sum technique, each page in the portion being assigned a unique non-zero “index” as a weight when computing the weighted-sum. Arithmetic is performed over a finite field (such as a Galois Field). The portions of the higher-level redundancy information are computable in any order, such as an order based on order of read operation completion of non-volatile memory elements. | 08-21-2014 |
20140237167 | Apparatus and Methods for Peak Power Management in Memory Systems - Disclosed are apparatus and techniques for managing power in a memory system having a controller and nonvolatile memory array. In one embodiment, prior to execution of each command with respect to the memory array, a request for execution of such command is received with respect to the memory array. In response to receipt of each request for each command, execution of such command is allowed or withheld with respect to the memory array based on whether such command, together with execution of other commands, is estimated to exceed a predetermined power usage specification for the memory system. | 08-21-2014 |
20140237168 | Mass Storage Controller Volatile Memory Containing Metadata Related to Flash Memory Storage - A storage controller is provided that contains multiple processors. In some embodiments, the storage controller is coupled to a flash memory module having multiple flash memory groups, each flash memory group corresponding to a distinct flash port in the storage controller, each flash port comprising an associated processor. Each processor handles a portion of one or more host commands, including reads and writes, allowing multiple parallel pipelines to handle one or more host commands simultaneously. | 08-21-2014 |
20140237169 | HOT MEMORY BLOCK TABLE IN A SOLID STATE STORAGE DEVICE - Solid state storage devices and methods for populating a hot memory block look-up table (HBLT) are disclosed. In one such method, an indication to an accessed page table or memory map of a non-volatile memory block is stored in the HBLT. If the page table or memory map is already present in the HBLT, the priority location of the page table or memory map is increased to the next priority location. If the page table or memory map is not already stored in the HBLT, the page table or memory map is stored in the HBLT at some priority location, such as the mid-point, and the priority location is incremented with each subsequent access to that page table or memory map. | 08-21-2014 |
20140237170 | STORAGE DEVICE, AND READ COMMAND EXECUTING METHOD - A storage device of the embodiment includes memory, a control section, a table holding section for managing a table for holding an identifier, a logical address, and a data length based on a read command, an issuing section for issuing the logical address and the data length for each identifier to the control section, a buffer for holding data received from the memory along with the identifier, and an identifier queue for receiving the identifier of a number proportional to a data length when the data of the logical address of the same identifier is received in the buffer. The storage device of the embodiment includes a transfer section for transferring the data corresponding to the identifier received in the buffer to outside when the identifier is held as incomplete readout in the table in order from the identifier at a head of the identifier queue. | 08-21-2014 |
20140237171 | SOLID-STATE DISK WITH WIRELESS FUNCTIONALITY - A system including an interface module to interface a solid-state disk controller to a computing device. A memory control module exchanges data with the computing device via the interface module and caches the data in a solid-state memory controlled by the solid-state disk controller. A network interface module communicates with the computing device via the interface module and interfaces the computing device to a wireless network. A crossbar module has a master bus (Mbus) interface bridged to an advanced high-performance bus (AHB). A memory communicates with one or more of the network interface module and the crossbar module via one or more of the Mbus interface and the AHB. In response to data being cached from the computing device to the solid-sate memory or data cached in the solid-state memory being output to the computing device, the network interface module buffers data received from the wireless network in the memory. | 08-21-2014 |
20140237172 | IMPARTING DURABILITY TO A TRANSACTIONAL MEMORY SYSTEM - A transactional memory system uses a volatile memory as primary storage for transactions. Data is selectively stored in a non-volatile memory to impart durability to the transactional memory system to allow the transactional memory system to be restored to a consistent state in the event of data loss to the volatile memory. | 08-21-2014 |
20140244895 | Robust Sector ID Scheme for Tracking Dead Sectors to Automate Search and Copydown - A brownout tolerant EEPROM emulator ( | 08-28-2014 |
20140244896 | Data Update Management in a Cloud Computing Environment - Method and apparatus for managing data in a cloud computing environment. In accordance with some embodiments, data updates are received to a multi-tier memory structure across a cloud network and stored as working data in an upper rewritable non-volatile memory tier of the memory structure. The working data are periodically logged to a lower non-volatile memory tier in the memory structure while a current version of the working data remain in the upper memory tier. The upper and lower memory tiers each are formed of rewritable memory cells having different constructions and storage attributes. | 08-28-2014 |
20140244897 | Metadata Update Management In a Multi-Tiered Memory - Method and apparatus for managing data in a memory. In accordance with some embodiments, metadata updates are stored in a first tier of a a multi-tier non-volatile memory structure responsive to access operations associated with data objects in the memory structure. The stored metadata updates are logged in a second, lower tier of the memory structure. The stored metadata updates are further migrated to a different location within the first tier responsive to an accumulated count of said access operations. | 08-28-2014 |
20140244898 | I/O Hint Framework for Server Flash Cache - An I/O hint framework is provided. In one embodiment, a computer system can receive an I/O command originating from a virtual machine (VM), where the I/O command identifies a data block of a virtual disk. The computer system can further extract hint metadata from the I/O command, where the hint metadata includes one or more characteristics of the data block that are relevant for determining how to cache the data block in a flash storage-based cache. The computer system can then make the hint metadata available to a caching module configured to manage the flash storage-based cache. | 08-28-2014 |
20140244899 | STORAGE CONTROL SYSTEM WITH DATA MANAGEMENT MECHANISM AND METHOD OF OPERATION THEREOF - A method of operation of a storage control system includes: calculating a throttle threshold; identifying a detection point based on the throttle threshold; and calculating a number of write/erase cycles based on the detection point and the throttle threshold for writing a memory device. | 08-28-2014 |
20140244900 | NON-VOLATILE MEMORY BASED SYSTEM RAM - A memory module includes an input/output (I/O) interface adapted to fit into a system random access memory (RAM) socket. The module also includes at least one controller coupled to the I/O interface, the controller comprising a plurality of registers, and a plurality of non-volatile memory devices coupled to the controller. In the module, when data is received at the I/O interface, the received data is stored using at least one of the plurality of registers and the controller performs one of a plurality of non-volatile memory operations on at least a portion of the plurality of non-volatile memory devices based on the received data. | 08-28-2014 |
20140244901 | METADATA MANAGEMENT FOR A FLASH DRIVE - An apparatus having one or more memories and a controller is disclosed. The memories are divided into a plurality of regions. Each regions is divided into a plurality of blocks. The blocks correspond to a plurality of memory addresses respectively. The controller is configured to (i) receive data from a host, (ii) generate metadata that maps a plurality of host addresses of the data to the memory addresses of the memories and (iii) write sequentially into a given one of the regions both (a) a portion of the data and (b) a corresponding portion of the metadata. | 08-28-2014 |
20140244902 | FAST READ IN WRITE-BACK CACHED MEMORY - An apparatus having a cache and a circuit is disclosed. The cache includes a plurality of cache lines. The cache is configured to (i) store a plurality of data items in the cache lines and (ii) generate a map that indicates a dirty state or a clean state of each of the cache lines. The cache also has a write-back policy to a memory. The circuit is configured to (i) check a location in the map corresponding to a read address of a read request and (ii) obtain read data directly from the memory by bypassing the cache in response to the location having the clean state. | 08-28-2014 |
20140244903 | CONTROLLER, SEMICONDUCTOR STORAGE DEVICE AND METHOD OF CONTROLLING DATA WRITING - According to one embodiment, a memory controller includes a mode selection part that selects one of a MLC-mode and a SLC-mode, after a write command is decoded by a command decode part, and a write part that executes a data writing to a storage memory by using one of the MLC-mode and the SLC-mode selected by the mode selection part. The mode selection part is configured to check whether a first data wrote from a host to a buffer memory is a time-continuous data that is wrote continuously during a predetermined period, execute the data writing of a second data from the buffer memory to the storage memory in the MLC-mode, when the first data is the time-continuous data, and execute the data writing of the second data from the buffer memory to the storage memory in the SLC-mode, when the first data is not the time-continuous data. | 08-28-2014 |
20140244904 | MEMORY DEVICE AND COMPUTER SYSTEM - A memory device according to an embodiment includes a non-volatile storage device from which data is read and to which data is written, an interface that is connected to the host device by a multiple upstream lanes and/or a multiple downstream lanes and performs data communication in both directions with the host device, and a memory controller. The memory controller changes a connection state of each lane on the basis of lane settings which are determined on the basis of at least one of an amount of data transmitted and the sequentiality of data when the data is transmitted between the memory device and the host device. | 08-28-2014 |
20140244905 | Linear Programming Based Decoding for Memory Devices - Technologies are generally described herein for linear programming based decoding for memory devices. In some examples, a cell threshold voltage level of a memory cell is detected. An interference voltage level of an interference cell that interferes with the memory cell can be determined. The cell threshold voltage level can be decoded in accordance with a set of beliefs to determine the value of the memory cell. The set of beliefs can include a minimization of an objective function of a linear program representing inter-cell interference between the memory cell and the interference cell. | 08-28-2014 |
20140244906 | MEMORY, AND METHOD OF READING DATA FROM THE MEMORY - Disclosed is a method of reading data from a memory including a NAND cell array for performing communications via a serial peripheral interface (SPI) bus. The method includes sequentially receiving inputs of a block address, a word-line address, and a bit-line address of the NAND cell array; and starting to output data written in the NAND cell array immediately after the bit-line address is completely input. In this case, the sequential receiving of the inputs is performed via one input terminal. | 08-28-2014 |
20140244907 | MEMORY DEVICE - According to an embodiment of the invention, a memory device includes an interface unit, a determining unit, a second command generating unit, and a processor. The interface unit receives a first command from the outside of the memory device. The determining unit determines whether the first command received by the interface unit is an access command that is a write command or a read command. When the determining unit determines that the first command is the access command, the second command generating unit extracts access destination information, which is address information or size information of an access destination, from the first command and generates a second command which includes the extracted access destination information and has a size less than that of the first command. The processor executes the second command. | 08-28-2014 |
20140244908 | INTEGRATED CIRCUIT FOR COMPUTING TARGET ENTRY ADDRESS OF BUFFER DESCRIPTOR BASED ON DATA BLOCK OFFSET, METHOD OF OPERATING SAME, AND SYSTEM INCLUDING SAME - A method of operating an integrated circuit is provided. The method includes receiving a data block offset from a second storage device, obtaining a target entry address using the data block offset, and reading an entry among a plurality of entries comprised in a buffer descriptor stored in a first storage device based on the target entry address. The method also includes reading data from a data buffer among a plurality of data buffers included in the first storage device using a physical address included in the entry and transmitting the data to the second storage device. | 08-28-2014 |
20140244909 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes: string units including a plurality of memory cells stacked above a semiconductor substrate; and a control circuit configured to perform an erase operation per a block, the block including the string units, the control circuit being configured to perform an erase verify operation per string unit. | 08-28-2014 |
20140244910 | ELECTRONIC APPARATUS IMPLEMENTED WITH MICROPROCESSOR WITH REWRITABLE MICRO PROGRAM AND METHOD TO REWRITE MICRO PROGRAM - An intelligent optical transceiver able to revise a micro program by the host system is disclosed. The optical transceiver includes a MDIO interface, a CPU, and a non-volatile memory. The host system may communicate with the CPU through an external MDIO bus, the MDIO interface, and an internal bus; while the CPU communicated with the non-volatile memory through another bus. The new micro program sent from the host system is temporarily stored in the non-volatile memory through the MDIO interface and the CPU, and finally set in the flash ROM in the CPU. | 08-28-2014 |
20140244911 | METHOD FOR PROGRAMMING A FLASH MEMORY - A method of programming a flash memory is described. The method includes partitioning a flash memory into a first group having a first level of write-protection, a second group having a second level of write-protection, and a third group having a third level of write-protection. The write-protection of the second and third groups is disabled using an installation adapter. The third group is programmed using a Software Installation Device. | 08-28-2014 |
20140244912 | Retired Page Utilization (RPU) for Improved Write Capacity of Solid State Drives - A method for writing data to a memory module, the method may include determining to write a representation of a data unit to a retired group of memory cells; searching for a selected retired group of memory cells that can store a representation of the data unit without being erased; and writing the representation of the data unit to the selected retired group of memory cells. | 08-28-2014 |
20140244913 | MEMORY SYSTEMS - Memory systems having a volatile memory, a non-volatile memory arranged in blocks, and a controller coupled to the volatile memory and to the non-volatile memory. The controller is configured to maintain, in the volatile memory, a list of addresses of erased blocks of the non-volatile memory. The list of addresses of erased blocks of the non-volatile memory is limited to a maximum number of list entries. The controller is further configured to transfer the list of addresses of erased blocks of the non-volatile memory from the volatile memory to the non-volatile memory in response to the list containing its maximum number of list entries and/or in response to an operation that would increase the number of list entries to a number equal to or greater than the maximum number of list entries. | 08-28-2014 |
20140244914 | MITIGATE FLASH WRITE LATENCY AND BANDWIDTH LIMITATION - A method of operating a memory system is provided. The method includes a controller that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the controller to regulate read and write access to the one or more FLASH devices. Wear leveling components along with read and write processing components are provided to facilitate efficient operations of the FLASH memory devices. | 08-28-2014 |
20140244915 | PINNING CONTENT IN NONVOLATILE MEMORY - Systems and methods relating to pinning selected data to sectors in non-volatile memory. A graphical user interface allows a user to specify certain data (e.g., directories or files) to be pinned. A list of pinned sectors can be stored so that a driver or controller that operates on a sector basis and not a file or directory basis can identify data to be pinned. | 08-28-2014 |
20140244916 | VIRTUAL MEMORY MANAGEMENT APPARATUS - A virtual memory management apparatus of an embodiment is embedded in a computing machine | 08-28-2014 |
20140244917 | METHODS AND SYSTEMS FOR REDUCING CHURN IN FLASH-BASED CACHE - A storage device includes a flash memory-based cache for a hard disk-based storage device and a controller that is configured to limit the rate of cache updates through a variety of mechanisms, including determinations that the data is not likely to be read back from the storage device within a time period that justifies its storage in the cache, compressing data prior to its storage in the cache, precluding storage of sequentially-accessed data in the cache and/or throttling storage of data to the cache within predetermined write periods and/or according to user instruction. | 08-28-2014 |
20140244918 | METHODS AND SYSTEMS FOR REDUCING CHURN IN FLASH-BASED CACHE - A storage device includes a flash memory-based cache for a hard disk-based storage device and a controller that is configured to limit the rate of cache updates through a variety of mechanisms, including determinations that the data is not likely to be read back from the storage device within a time period that justifies its storage in the cache, compressing data prior to its storage in the cache, precluding storage of sequentially-accessed data in the cache, and/or throttling storage of data to the cache within predetermined write periods and/or according to user instruction. | 08-28-2014 |
20140244919 | METHOD OF ERASING INFORMATION STORED IN A NONVOLATILE REWRITABLE MEMORY, STORAGE MEDIUM AND MOTOR VEHICLE COMPUTER - Method of erasing information stored in a nonvolatile rewritable memory of a computer, wherein a master module sends erasing requests to a slave module of the computer, the memory including at least two interleaved sectors. The method includes preliminary steps of determining a virtual memory addressing space associated with the memory, in which each sector extends over a specific range of consecutive virtual memory addresses, and establishing a first correspondence function for determining, from a range of virtual memory addresses, the sector or sectors whose contents must be erased, and for each erasing request received by the slave module indicating a range of virtual memory addresses, a step of determining the sector or sectors whose contents must be erased by the slave module. The memory includes a plurality of segments, each segment breaking down into a plurality of sectors and at least two segments including interleaved physical memory addresses. | 08-28-2014 |
20140250256 | APPARATUS AND SYSTEM FOR OBJECT-BASED STORAGE SOLID-STATE DRIVE - An object-based storage system comprising a host system capable of executing applications for and with an object-based storage device (OSD). Exemplary configurations include a call interface, a physical layer interface, an object-based storage solid-state device (OSD-SSD), and are further characterized by the presence of a storage processor capable of processing object-based storage device algorithms interleaved with processing of physical storage device management. Embodiments include a storage controller capable of executing recognition, classification and tagging of application files, especially including image, music, and other media. Also disclosed are methods for initializing and configuring an OSD-SSD device. | 09-04-2014 |
20140250257 | COMPRESSION-ENABLED BLENDING OF DATA IN NON-VOLATILE MEMORY - Described herein are embodiments of an apparatus configured for compression-enabled blending of data, a system including the apparatus configured for compression-enabled blending of data, and a method for compression-enabled blending of data. An apparatus configured for compression-enabled blending of data may include non-volatile memory configured to operate in a single-level cell mode and a multi-level cell mode, a compression module configured to compress data to generate compressed data, and a memory controller configured to write, in response to a reduction ratio of the compressed data being less than a threshold compression ratio, a first portion of the compressed data to the non-volatile memory in the single-level cell mode, and a second portion of the compressed data to the non-volatile memory in the multi-level cell mode. Other embodiments may be described and/or claimed. | 09-04-2014 |
20140250258 | DATA STORAGE DEVICE AND FLASH MEMORY CONTROL METHOD - A data storage device with a FLASH memory accessed via multiple channels and a FLASH memory control method. The control method includes the following steps: dividing a plurality of blocks of the FLASH memory into groups to be accessed via different channels; allocating at least one set of cache spaces in a random access memory for temporary write data storage for the different channels; separating write data issued from a host to correspond to the plurality of channels; and, when data arrangement for every channel has been completed in one set of cache spaces, writing the data that has been arranged in the set of cache spaces to the FLASH memory via the plurality of channels corresponding to the different cache spaces of the set of cache spaces. | 09-04-2014 |
20140250259 | DATA STORAGE DEVICE AND FLASH MEMORY CONTROL METHOD - A data storage device and a FLASH memory control method with a cache space. The FLASH memory control method includes the following steps: using a plurality of channels to access a FLASH memory, wherein the FLASH memory has a plurality of blocks each with a plurality of pages, and the blocks are grouped to be accessed by the different channels; allocating a random access memory to provide a cache space, the cache space having a plurality of cache areas caching write data for the different channels, respectively; distributing the data issued from a host to correspond to the different channels; and reusing a latest-updated cache area of the cache space to cache write data when a logical address requested to be written with data is identical to a logical address that the latest-updated cache area corresponds to. | 09-04-2014 |
20140250260 | ASYNCHRONOUS FIFO BUFFER FOR MEMORY ACCESS - An asynchronous FIFO buffer that provides data in response to requests to read a memory array is disclosed. The asynchronous FIFO buffer provides the data output within a latency tolerance. The asynchronous FIFO has a read clock input and a write clock input. The read clock input receives a read enable signal that defines how data should be clocked out. The write clock input receives a write clock that is asynchronous from the read enable signal. The asynchronous FIFO inputs data from the memory array in accordance with the write clock signal. The asynchronous FIFO outputs data in accordance with the read enable signal. Control logic may pre-fetch data from the memory array into the asynchronous FIFO prior to the read enable signal first being received. | 09-04-2014 |
20140250261 | LOGICAL UNIT OPERATION - The present disclosure includes methods and devices for logical unit operation. One device embodiment includes a number of logical units, wherein each of the number of logical units has a unique address. The device includes control circuitry coupled to the number of logical units and configured optionally to control more than one of the number of logical units with one of a number of commands and one address. | 09-04-2014 |
20140250262 | SYSTEM AND METHOD FOR POLLING THE STATUS OF MEMORY DEVICES - A memory controller and methods thereof suitable for operating a system utilizing multiple memory bus channels and/or multiple banks of memory devices on each channel wherein the memory devices is polled only when necessary. The memory controller includes means for determining a status of each individual memory device of the plurality of memory devices, a channel controller for each memory bus channel, and at least one status register on which is stored a plurality of bits. The channel controller maintains a derived status of each individual memory device based on the current and previous status data. Each individual bit of the plurality of bits of the status register corresponds to an individual memory device of the plurality of memory devices and indicates the derived status of the individual memory device which are used to determine whether to check for a queued command destined for the individual memory device. | 09-04-2014 |
20140250263 | TECHNIQUES FOR REDUCING MEMORY WRITE OPERATIONS USING COALESCING MEMORY BUFFERS AND DIFFERENCE INFORMATION - A system, method, and computer program product are provided for reducing write operations in memory. In use, write operations to be performed on data stored in memory are identified. A difference is then determined between results of the write operations and the data stored in the memory. Difference information associated with the difference is stored in the memory. To this end, the write operations may be reduced, utilizing the difference information. | 09-04-2014 |
20140250264 | MEMORY SYSTEM - A memory system according to an embodiment of the present invention comprises: speed of processing for searching through management tables is increased by providing a forward lookup table for searching for, respectively in track and cluster units, from a logical address, a storage device position where data corresponding to the logical address and a reverse lookup table for searching for, from a position of the storage device, a logical address stored in the position and linking these tables. | 09-04-2014 |
20140250265 | DATA MODIFICATION BASED ON MATCHING BIT PATTERNS - A data storage device includes a memory and a controller. The controller is configured to identify groups of bits that match any bit pattern in a first set of bit patterns. Each of the groups of bits includes a first bit of first data, a second bit of second data, and a third bit of third data to be stored at the memory. The controller is configured, based on determining that a count of the identified groups exceeds a threshold, to change multiple bits of the first data. Changing the multiple bits of the first data reduces a number of the groups of bits that match any bit pattern in the first set of bit patterns. | 09-04-2014 |
20140250266 | Data Randomization in 3-D Memory - In a nonvolatile memory array, such as a three-dimensional array of charge-storage memory cells, data is randomized so that data of different strings along the same bit line are randomized using different keys and portions of data along neighboring word lines are randomized using different keys. Keys may be rotated so that data of a particular word line is randomized according to different keys in different strings. | 09-04-2014 |
20140258588 | METHODS, DEVICES AND SYSTEMS FOR TWO STAGE POWER-ON MAP REBUILD WITH FREE SPACE ACCOUNTING IN A SOLID STATE DRIVE - A data storage device comprises a non-volatile memory comprising a plurality of blocks, each configured to store a plurality of physical pages at predetermined physical locations. A controller programs and reads data stored in a plurality of logical pages. A volatile memory comprises a logical-to-physical address translation map configured to enabling determination of the physical location, within one or more physical pages, of the data stored in each logical page. A plurality of journals may be stored, each comprising a plurality of entries associating one or more physical pages to each logical page. At startup, the controller may read at least some of the plurality of journals in an order and rebuild the map; indicate a readiness to service data access commands after the map is rebuilt; rebuild a table from the map and, based thereon, select block(s) for garbage collection after having indicated the readiness to process the commands. | 09-11-2014 |
20140258589 | RANDOM NUMBER GENERATION - A system for random number generation may include non-volatile memory, and a random number stored on the non-volatile memory. The system may also include a key linked to the random number. The system may further include a computer-apparatus designed to use the random number based upon the key. | 09-11-2014 |
20140258590 | Enhanced Dynamic Read Process with Single-Level Cell Segmentation - A dynamic read case designation is determined for each of multiple wordline regions, respectively, of each of a number of single-level cell logic groups within a computer memory. The dynamic read case designation for any given one of the multiple wordline regions specifies a wordline read voltage to be used in reading memory cells of each wordline within the given one of the multiple wordline regions. The number of single-level cell logic groups are folded into a multi-level cell block. The folding includes reading the memory cells of each wordline of each of the multiple wordline regions of each of the number of single-level cell logic groups using a wordline read voltage corresponding to the dynamic read case designation, as determined for the wordline region within which the read memory cells reside. | 09-11-2014 |
20140258591 | DATA STORAGE AND RETRIEVAL IN A HYBRID DRIVE - A data storage device includes a magnetic storage device and a non-volatile solid-state memory device. The addressable space of the non-volatile solid-state storage device is partitioned into a plurality of equal sized segments and the addressable space of a command to read or write data to the data storage device is partitioned into a number of equal sized sets of contiguous addresses, such that each set of contiguous addresses has the same size as a segment of the addressable space of the non-volatile solid-state storage device. Storage can be allocated in the non-volatile solid-state device for selected sets of the contiguous addresses by mapping each selected set to a specific segment of the addressable space of the non-volatile solid-state device. | 09-11-2014 |
20140258592 | WRITE PROTECTION DATA STRUCTURE - A data storage device includes a write protection data structure that includes a first set of entries corresponding to a first set of ranges of memory addresses. A first indication stored in an entry, in the first set of entries, corresponds to an absence of write-protected data between a lowest address of the range of addresses corresponding to the entry and a highest address of a memory. A second indication stored in the entry corresponds to write-protected data within the range of addresses. The data storage device also includes a write protection map that includes a second set of entries corresponding to a second set of ranges of the memory addresses. The device is configured to locate, in the write protection data structure, an entry corresponding to a range of memory addresses. | 09-11-2014 |
20140258593 | APPROXIMATE MULTI-LEVEL CELL MEMORY OPERATIONS - The present technology relaxes the precision (or full data-correctness-guarantees) requirements in memory operations, such as writing or reading, of MLC memories so that an application may write and read a digital data value as an approximate value. Types of MLCs include Flash MLC and MLC Phase Change Memory (PCM) as well as other resistive technologies. Many software applications may not need the accuracy or precision typically used to store and read data values. For example, an application may render an image on a relatively low resolution display and may not need an accurate data value for each pixel. By relaxing the precision or correctness requirements is a memory operation, MLC memories may have increased performance, lifetime, density, and/or energy efficiency. | 09-11-2014 |
20140258594 | RANDOM NUMBER GENERATION - A system for random number generation may include non-volatile memory, and a random number stored on the non-volatile memory. The system may also include a key linked to the random number. The system may further include a computer-apparatus designed to use the random number based upon the key. | 09-11-2014 |
20140258595 | SYSTEM, METHOD AND COMPUTER-READABLE MEDIUM FOR DYNAMIC CACHE SHARING IN A FLASH-BASED CACHING SOLUTION SUPPORTING VIRTUAL MACHINES - A cache controller implemented in O/S kernel, driver and application levels within a guest virtual machine dynamically allocates a cache store to virtual machines for improved responsiveness to changing demands of virtual machines. A single cache device or a group of cache devices are provisioned as multiple logical devices and exposed to a resource allocator. A core caching algorithm executes in the guest virtual machine. As new virtual machines are added under the management of the virtual machine monitor, existing virtual machines are prompted to relinquish a portion of the cache store allocated for use by the respective existing machines. The relinquished cache is allocated to the new machine. Similarly, if a virtual machine is shutdown or migrated to a new host system, the cache capacity allocated to the virtual machine is redistributed among the remaining virtual machines being managed by the virtual machine monitor. | 09-11-2014 |
20140258596 | MEMORY CONTROLLER AND MEMORY SYSTEM - A memory controller having a plurality of channels according to an embodiment of the present invention includes: a valid page information management unit that manages, for each of the channel, identification information of a valid page; a write buffer that stores data to be written to the memory; a garbage collection control unit that executes a garbage collection process; and a channel controller capable of executing multi-plane read. The garbage collection control unit controls multi-plane read of the channel controller based on the identification information to level a total number of valid pages read from each of the channel. | 09-11-2014 |
20140258597 | MEMORY CONTROLLER AND MEMORY SYSTEM INCLUDING THE SAME - An operating method is for a memory device which controls a nonvolatile memory. The operating method includes managing a program depth bit map indicating an upper page program state of each of a plurality of word lines of the nonvolatile memory in response to an external write request, and outputting one of a plurality of different read commands to the nonvolatile memory based on information of the program depth bit map corresponding to a word line to be accessed in response to an external read request. | 09-11-2014 |
20140258598 | SCALABLE STORAGE DEVICES - Techniques using scalable storage devices represent a plurality of host-accessible storage devices as a single logical interface, conceptually aggregating storage implemented by the devices. A primary agent of the devices accepts storage requests from the host using a host-interface protocol, processing the requests internally and/or forwarding the requests as sub-requests to secondary agents of the storage devices using a peer-to-peer protocol. The secondary agents accept and process the sub-requests, and report sub-status information for each of the sub-requests to the primary agent and/or the host. The primary agent optionally accumulates the sub-statuses into an overall status for providing to the host. Peer-to-peer communication between the agents is optionally used to communicate redundancy information during host accesses and/or failure recoveries. Various failure recovery techniques reallocate storage, reassign agents, recover data via redundancy information, or any combination thereof. | 09-11-2014 |
20140258599 | WRITE PROTECTION DATA STRUCTURE - A data storage device includes a write protection data structure that includes a first set of entries corresponding to a first set of ranges of memory addresses. A first indication stored in an entry, in the first set of entries, corresponds to an absence of write-protected data between a lowest address of the range of addresses corresponding to the entry and a highest address of a memory. A second indication stored in the entry corresponds to write-protected data within the range of addresses. The data storage device also includes a write protection map that includes a second set of entries corresponding to a second set of ranges of the memory addresses. The device is configured to locate, in the write protection data structure, an entry corresponding to a range of memory addresses. | 09-11-2014 |
20140258600 | PRE-LOADING DATA - A device includes a non-volatile memory configured to store software to facilitate normal functions of the device, a first processing section including a data processor configured to execute the software when the device is in a normal mode, and load the software into a working memory in response to a trigger, and a second processing section coupled to a clock for maintaining a time, the second processing section configured to handle background processes when the device is in a low-power mode and initiate the trigger in response to the time of the clock preceding a user-set time by a preset advance interval, the pre-set advance interval taking into account a length of time to load the software into the working memory, wherein the working memory includes a volatile memory configured to store the software, and wherein in the low-power mode, the volatile memory receives insufficient power to store the software. | 09-11-2014 |
20140258601 | Memory Controller Supporting Nonvolatile Physical Memory - A memory system includes nonvolatile physical memory, such as flash memory, that exhibits a wear mechanism asymmetrically associated with write operations. A relatively small cache of volatile memory reduces the number of writes, and wear-leveling memory access methods distribute writes evenly over the nonvolatile memory. | 09-11-2014 |
20140258602 | SEMICONDUCTOR STORAGE DEVICE WITH VOLATILE AND NONVOLATILE MEMORIES TO ALLOCATE BLOCKS TO A MEMORY AND RELEASE ALLOCATED BLOCKS - A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second and third memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data outputted from the first memory area by a first management unit in the second memory area, and a third processing for storing data outputted from the first memory area by a second management unit in the third memory area. | 09-11-2014 |
20140281122 | MULTI-LEVEL TABLE DELTAS - A memory system or flash card may include an algorithm or process for managing the handling of large tables in memory. A delta may be used for each table to accumulate updates. There may be a plurality of deltas for a multi-level delta structure. In one example, the first level delta is stored in random access memory (RAM), while the other level deltas are stored in the flash memory. Multiple-level deltas may improve the number of flash writes and reduce the number and amount of each flush to the actual table in flash. The use of multi-level deltas may improve performance by more efficiently writing to the table in flash. | 09-18-2014 |
20140281123 | SYSTEM AND METHOD FOR HANDLING I/O WRITE REQUESTS - System and methods for managing I/O write requests of host systems to physical storage. A storage subsystem includes a plurality of storage devices where each storage device is configured to provide data storage. At least a pair of redundant controllers is connected to the plurality of storage devices for executing the I/O write requests from the host systems. A received I/O write request is initially saved in a controller memory of one of the controllers and mirrored in controller memory of the other controller. In one embodiment, the I/O write request is transferred to a flash memory device for subsequent transfer to the storage devices. Once transferred to the flash memory device, the I/O write request may be flushed from the controller memories. The I/O write request may then be transferred to the storage devices from the flash memory device as a background operation. | 09-18-2014 |
20140281124 | SYSTEM AND METHOD FOR CACHING A STORAGE MEDIUM - A standalone storage cache is responsive to a host independent of drivers or caching logic on the host. The standalone storage cache (standalone cache) interfaces between the host and corresponding storage device, and appears to each as the same I/O interface. I/O requests are sent by the host, and received/acknowledges by the standalone cache as if it were the native storage device. Similarly, the native storage device receives the I/O requests and fetches or stores the corresponding data. Caching logic in the standalone cache determines occupancy in the cache, and identifies when a request can be fulfilled by the cache rather than incurring an I/O to the storage device. No driver or other control need be resident on the host, due to independence of the standalone cache. Since the caching logic is inherent in the standalone cache, existing hosts may benefit from caching without host modification or storage volume upgrade. | 09-18-2014 |
20140281125 | SYSTEMS AND METHODS FOR IN-PLACE REORGANIZATION OF DEVICE STORAGE - A method for in-place reorganization of contents stored in a non-volatile storage of a device and organized according to an original organization scheme having at least one original storage unit and on original organization logic associated therewith, to a target organization scheme having at least one target storage unit and a target organization logic associated therewith, includes: obtaining instructions to reorganize the contents in the non-volatile storage from the original organization scheme to a defined target organization scheme; generating, on the device, based on the instructions and the applying of the target organization logic to a virtual storage, a sequence of update commands for generating in the non-volatile storage the at least one target storage unit organized according to the target organization scheme; and executing the update commands on the non-volatile storage. | 09-18-2014 |
20140281126 | OVERPROVISION CAPACITY IN A DATA STORAGE DEVICE - A data storage module includes a non-volatile memory and a controller. A method performed in the data storage module includes receiving an overprovision capacity instruction from a host device. The method further includes updating a file system table of the non-volatile memory to indicate, by designating logical addresses in the file system table as being in use, that the logical addresses are used without reducing an amount of free physical space in the non-volatile memory. | 09-18-2014 |
20140281127 | Storage Module and Method for Regulating Garbage Collection Operations Based on Write Activity of a Host - A storage module and method for regulating garbage collection operations based on write activity of a host are disclosed. In one embodiment, a storage module determines whether the host is operating in a burst mode by determining whether write activity of the host over a time period exceeds a threshold. The write activity can comprise one or both of (i) an amount of data received from the host to be written in the storage module and (ii) a number of write commands received from the host. If the host is operating in the burst mode, the storage module limits an amount of garbage collection operations during the burst mode. When the host is no longer operating in the burst mode, the storage module increases an amount of garbage collection operations. | 09-18-2014 |
20140281128 | DECODING DATA STORED IN SOLID-STATE MEMORY - Embodiments of decoding data stored in solid-state memory arrays are disclosed. In one embodiment, multiple read operations are performed while taking inter-cell interference (ICI) into account. Soft-decision information, such as log-likelihood ratios (LLRs), is determined by using known data and its corresponding multi-read output. Soft-decision information is provided to a detector. Reliability is improved and performance is increased. | 09-18-2014 |
20140281129 | DATA TAG SHARING FROM HOST TO STORAGE SYSTEMS - A system and method for data tag sharing is disclosed. A host system may provide a storage system with information that identifies a set of logical addresses as pointing to data that is cold, which may mean that the data has not been written to within a threshold time period, such as a year. The storage system may process the data stored at physical locations corresponding to the set of logical addresses as cold data based on receipt of the information from the host system. | 09-18-2014 |
20140281130 | ACCESSING NON-VOLATILE MEMORY THROUGH A VOLATILE SHADOW MEMORY - An apparatus is provided that includes a non-volatile (device storage) memory configured to store data in a plurality of locations. The apparatus also includes a device interface coupled to the non-volatile memory and including a volatile (device storage) shadow memory configured to store an image of the plurality of locations of the non-volatile memory in a corresponding plurality of locations of the volatile shadow memory. The device interface is configured to receive a command across a network bus from a bus controller, and in response thereto, the device interface is configured to write data from the network bus to a location in the non-volatile memory. This write includes the device interface being configured to write the data to the corresponding location in the volatile shadow memory, and thereafter write the data from the corresponding location in the volatile shadow memory to the location in the non-volatile memory. | 09-18-2014 |
20140281131 | SYSTEMS AND METHODS FOR PERSISTENT CACHE LOGGING - A cache log module stores an ordered log of cache storage operations sequentially within the physical address space of a non-volatile storage device. The log may be divided into segments, each comprising a set of log entries. Data admitted into the cache may be associated with respective log segments. Cache data may be associated with the log segment that corresponds to the cache storage operation in which the cache data was written into the cache. The backing store of the data may be synchronized to a particular log segment by identifying the cache data pertaining to the segment (using the associations), and writing the identified data to the backing store. Data lost from the cache may be recovered from the log by, inter alia, committing entries in the log after the last synchronization time of the backing store. | 09-18-2014 |
20140281132 | METHOD AND SYSTEM FOR RAM CACHE COALESCING - A system and method for coalescing data fragments in a volatile memory such as RAM cache is disclosed. The method may include storing multiple data fragments in volatile memory and initiating a single write operation to flash memory only when a predetermined number of data fragments have been received and aggregated into a single flash write command. The method may also include generating a binary cache index delta that aggregates in a single entry all of the binary cache index information for the aggregated data fragments. A memory system having a non-volatile memory, a volatile memory sized to at least store a number of data fragments equal to a physical page managed in a binary cache of the non-volatile memory, and a controller is disclosed. The controller may be configured to execute the method of coalescing data fragments into a single flash write operation described above. | 09-18-2014 |
20140281133 | MANAGING THE WRITE PERFORMANCE OF AN ASYMMETRIC MEMORY SYSTEM - Some implementations include a method of managing a hosted non-volatile random-access memory (NVRAM) based storage subsystem that includes NVRAM devices. The method includes: receiving, at a device driver on the host computing device, write requests each requesting to write a respective unit of data to the NVRAM-based storage subsystem; categorizing the write requests into subgroups of write requests, where write requests within respective subgroups are mutually exclusive; ascertaining a load condition of each of several of the NVRAM devices of the NVRAM-based storage subsystem; identifying a target location on at least one NVRAM device to service a particular subgroup of write requests according to the ascertained load conditions of the NVRAM devices of the NVRAM-based storage subsystem; and servicing the particular subgroup of write requests by writing the corresponding units of data to the identified target location on the at least one NVRAM device of the NVRAM-based storage subsystem. | 09-18-2014 |
20140281134 | SYSTEM AND METHOD OF PROCESSING OF DUPLICATE DATA AT A DATA STORAGE DEVICE - A data storage device includes a memory and a controller. A method may be performed at the data storage device. The method includes receiving a request to write data, generating a signature of the data, and searching a signature table to determine if the generated signature is in the signature table. The signature table includes at least one signature table entry that includes a signature of stored data and a physical address of the stored data. | 09-18-2014 |
20140281135 | Dynamic Address Grouping For Parallel Programming In Non-Volatile Memory - A non-volatile memory system evaluates user data before writing in order to potentially group addresses for writing within a cycle. The system can determine which sense amplifier addresses of a column address will be programmed in a column address cycle. The number of bits that will be programmed is compared with an allowable number of parallel bits. The system generates groups of sense amplifier addresses based on the comparison. The system generates groups that include a total number of bits to be programmed that is within the allowable number of parallel bits. Each group is programmed in one sense amplifier address cycle. Multiple sense amplifier addresses can be grouped for programming while still remaining within an allowable number of parallel programming bits. The system performs a read before write operation and generates bitmap data for the grouping information corresponding sense amplifier addresses. | 09-18-2014 |
20140281136 | SYSTEMS AND METHODS FOR WRITING TO HIGH-CAPACITY MEMORY - Systems and methods for writing to high-capacity memory are disclosed. In high-capacity memory systems in which the capacity of the characteristic portion of the memory (e.g., a page of NAND flash memory) exceeds the capacity of a buffer used to write to the memory, underutilization issues are prevalent. Data organized in the buffer can be combined with additional data to improve utilization of the characteristic portion. According to various embodiments, the additional data can include duplicate copies of the data, whitened data, or any other suitable type of data. | 09-18-2014 |
20140281137 | METHOD AND DEVICE IMPLEMENTING EXECUTE-ONLY MEMORY PROTECTION - Access requests to access data operands from memory space designated as a type of execute-only memory are allowed to precede in response to determining that the operand access request was generated using a particular type of addressing mode. | 09-18-2014 |
20140281138 | SYNCHRONOUS MIRRORING IN NON-VOLATILE MEMORY SYSTEMS - First data is received for storing in a first asymmetric memory device. A first writing phase is identified as a current writing phase. A first segment included in the first asymmetric memory device is identified as next segment available for writing data. The first data is written to the first segment. Information associated with the first segment is stored, along with information indicating that the first segment is written in the first writing phase. Second data is received for storing in the asymmetric memory. A second segment included in the first asymmetric memory device is identified as the next segment available for writing data. The second data is written to the second segment. Information associated with the second segment and the second memory block is stored along with information indicating that the second segment is written in the second writing phase. | 09-18-2014 |
20140281139 | DUAL-INTERFACE FLASH DRIVE - Various embodiments relate to apparatuses and methods of dual-interface flash drives which prevent both interfaces of the dual-interface flash drive from being able to be simultaneously connected to interface ports of devices. This eliminates the risk of damage to or malfunction of the dual-interface flash drive as a result of both interfaces being simultaneously connected. As one example, a dual-interface flash drive can include a housing with a standard USB connector on one end and a micro USB connector on the opposite end. A flash memory is embedded within the housing, and a protective shield is attached to the housing. The flash memory is protected from simultaneous access by both the standard USB connector and the micro USB connector by the protective shield physically preventing both connectors from being able to be simultaneously connected to a port of a device | 09-18-2014 |
20140281140 | NETWORK STORAGE SYSTEM USING FLASH STORAGE - A system can comprise an I/O circuitry, a processor, reconfigurable circuitry, an array of flash storage devices, and a serial interconnect network that is coupled to transfer data between the I/O circuitry, the processor, the reconfigurable circuitry and the flash storage devices. The processor can be configured to designate an interconnect address space for use in communication over the interconnect network among the I/O circuitry, the processor, the reconfigurable circuitry and the flash storage devices. The reconfigurable circuitry can be configured to translate data addresses during transfers of data between the I/O circuitry and the array of flash storage devices. A method to access an array of flash storage devices that are coupled to I/O circuitry over a serial interconnect network can comprise using reconfigurable circuitry to capture data during transfers of data over the serial interconnect network. | 09-18-2014 |
20140281141 | Binning of Blocks for Dynamic Linking - A multi-plane non-volatile memory die includes circuits that receive and apply different parameters to different planes while accessing planes in parallel so that different erase blocks are accessed using individualized parameters. Programming parameters, and read parameters can be modified on a block-by-block basis with modification based on the number of write-erase cycles or other factors. | 09-18-2014 |
20140281142 | Storage System Employing MRAM and Redundant Array of Solid State Disk - A storage system includes one or more RAID groups, a RAID group comprising a number of physically addressed solid state disks (paSSD). Stripes are formed across a RAID group, data to be written is saved in a non-volatile buffer until enough data for a full strip is received (without any restriction about logical address of data), full stripes are sent and written to paSSDs comprising the RAID group, accordingly the partial stripe read-modify-write is avoided. | 09-18-2014 |
20140281143 | REDUCING FLASH MEMORY WRITE AMPLIFICATION AND LATENCY - Data is distributed to solid-state disks (SSDs) using the RAID-0 technique. Based on a utilization of a first region of a first one of the SSDs, the first region is selected for garbage collection. Valid data from the first region is copied to an active region of the first one of the SSDs as part of a process of garbage collection. While the process of garbage collection is being performed, data is distributed to a subset of the SSDs using the RAID-0 technique where the subset of the SSDs does not include the first one of the plurality of nonvolatile solid-state memories selected for garbage collection. | 09-18-2014 |
20140281144 | MEMORY SYSTEM - According to one embodiment, a memory system includes a nonvolatile memory including first blocks configured to store an address indicating a data storage position, and second blocks configured to store the data, a first table configured to store a first address including first information and second information, the second information indicating a data storage position in the first block, and a second table configured to convert the first information into third information, the first information having a first data size by which one entry of the second table can be identified, the third information having a second data size which is larger than the first data size and by which one of the first blocks and the second blocks can be identified. | 09-18-2014 |
20140281145 | ATOMIC WRITE COMMAND SUPPORT IN A SOLID STATE DRIVE - A method of performing an atomic write command in a data storage device comprising a volatile memory and a plurality of non-volatile memory devices configured to store a plurality of physical pages. The method may comprise storing data in a plurality of logical pages (L-Pages), each associated with a logical address. A logical-to-physical address translation map may be maintained in the volatile memory, and may be configured to enable determination of a physical location, within one or more of the physical pages, of the data referenced by each logical address. The data specified by a received atomic write command may be stored one or more L-Pages. Updates to the entry or entries in the translation map associated with the L-Page(s) storing the data specified by the atomic write command may be deferred until all L-Pages storing data specified by the atomic write command have been written in a power-safe manner. | 09-18-2014 |
20140281146 | COMPRESSION AND FORMATTING OF DATA FOR DATA STORAGE SYSTEMS - Embodiments of compression and formatting of data for data storage systems are disclosed. In some embodiments, a data storage system can compress fixed sized data before storing it on a media and format obtained variable sized compressed data for storing on the media that typically has fixed size storage granularity. One or more modules compress the incoming host data and create an output stream of fixed sized storage units that contain compressed data. The storage units are stored on the media. Capacity, reliability, and performance are thereby increased. | 09-18-2014 |
20140281147 | MEMORY SYSTEM - According to one embodiment, a memory system includes a first interface unit configured to operate in parallel nonvolatile memories, and a second interface unit configured to receive data requested by a host from the first interface unit and transfer the data to the host independently of an order of commands sent from the host. The second interface unit includes a first storage unit configured to store commands sent from the host, a second storage unit configured to store items of first information sent from the first interface unit, and a control unit configured to perform data transfer concerning the command stored in the first storage unit in an order in which the items of first information are stored in the second storage unit. | 09-18-2014 |
20140281148 | MEMORY SYSTEM - According to one embodiment, a memory system comprises a nonvolatile memory, a first volatile memory which stores management information to manage the nonvolatile memory, a controller which controls operations of the nonvolatile memory and the first volatile memory, and a power supply circuit which makes power supplied to part of the first volatile memory zero in accordance with a data capacity of the management information in response to a request from the controller. | 09-18-2014 |
20140281149 | APPARATUSES AND METHODS FOR ADAPTIVE CONTROL OF MEMORY - Apparatuses and methods for adaptive control of memory are disclosed. One example apparatus includes a processing unit configured to run an operating system, and a memory coupled to the processing unit. The memory configured to communicate with the processing unit via a memory bus. The example apparatus may further include an adaptive memory controller configured to receive monitored statistical data from the memory and from the processing unit. The adaptive memory controller is configured to manage the memory based on the monitored statistical data. | 09-18-2014 |
20140281150 | DIFFERENCE L2P METHOD - A method for maintaining a data set includes storing a base copy of the data set in a first non-volatile memory having a first writing speed, storing changes to the data set in a first change data set in a second non-volatile memory having a second writing speed, and generating a current copy of the data set by reading the base copy and the changes. If a threshold number of entries in the first change data set is reached, then part or all of the first change data set is moved into a second change data set in the first non-volatile memory, where the generating step includes reading the second change data set. If a threshold number of entries in the second change data set is reached, then the current copy is generated by reading the base copy and the changes in the first and the second non-volatile memory. | 09-18-2014 |
20140281151 | Green NAND Device (GND) Driver with DRAM Data Persistence For Enhanced Flash Endurance and Performance - A Green NAND Device (GND) driver application queries AC line and battery status and then stores an image of processor states and caches and a resume routine to DRAM when power failure occurs. A DRAM image is then stored to flash memory for a persistent mode when battery power is available. The image in DRAM may be a partial image that includes entries, flushed caches, processor contexts, ramdisks, write caches, and a resume context. Endurance of flash memory is increased by a Super Enhanced Endurance Device (SEED) SSD. In a power down mode, the GND driver limits DRAM use and only caches in DRAM data that can be deleted on power down. Host accesses to flash are intercepted by the GND driver and categorized by data type. Paging files and temporary files cached in DRAM are optionally written to flash. | 09-18-2014 |
20140281152 | Managing the Write Performance of an Asymmetric Memory System - Some implementations include a method of managing a hosted non-volatile random-access memory (NVRAM) based storage subsystem that includes NVRAM devices. The method includes: receiving, at a device driver on the host computing device, write requests each requesting to write a respective unit of data to the NVRAM-based storage subsystem; categorizing the write requests into subgroups of write requests, where write requests within respective subgroups are mutually exclusive; ascertaining a load condition of each of several of the NVRAM devices of the NVRAM-based storage subsystem; identifying a target location on at least one NVRAM device to service a particular subgroup of write requests according to the ascertained load conditions of the NVRAM devices of the NVRAM-based storage subsystem; and servicing the particular subgroup of write requests by writing the corresponding units of data to the identified target location on the at least one NVRAM device of the NVRAM-based storage subsystem. | 09-18-2014 |
20140281153 | FLASH-BASED STORAGE SYSTEM INCLUDING RECONFIGURABLE CIRCUITRY - Apparatus and method for accelerating processing operations of flash based storage systems are disclosed herein. In some embodiments, an IC component disposed between I/O circuitry and flash storage devices is configured to optimize fulfillment of data read and write requests originating from a network or device external to the flash based storage system using cache memory before involving the flash storage devices. | 09-18-2014 |
20140281154 | MEMORY SYSTEM - According to one embodiment, there is provided a memory system that is connected to a host apparatus. The memory system includes a transmitting port and a controller. The transmitting port transmits a transmission signal to the host apparatus. The controller includes a first output interface that is connected to the transmitting port and a second output interface that is connected to the transmitting port. The memory system is configured such that a drivability of an output from the first output interface is larger than a drivability of an output from the second output interface in a first mode. | 09-18-2014 |
20140281155 | STORAGE DEVICE ASSISTED DATA DE-DUPLICATION - Systems and methods presented herein provide for de-duplication of data. In one embodiment, an input/output module is operable to generate an input/output operation to write data. A storage device is communicatively coupled to the input/output module and operable to write the data of the input/output operation at a logical address of the storage device, and to generate a signature based on the data. The input/output module is further operable to process the signature to determine whether the data exists at another logical address. | 09-18-2014 |
20140281156 | MANAGING WAIT STATES FOR MEMORY ACCESS - A latch signal is received from a non-volatile memory device that is indicative of a current access time for the non-volatile memory device. The access time represents an amount of time required for the non-volatile memory device to make data available responsive to a request for data. A bus system clock signal is received. The latch signal is evaluated and a wait state for the non-volatile memory device is adjusted based on the evaluation. The wait state represents a number of cycles of the bus system clock used by a central processing unit for an access of the non-volatile memory device. A bus system data ready signal that is triggered based on the adjusted wait state is produced. The bus system data ready signal, when triggered, indicates that data is available responsive to the request. | 09-18-2014 |
20140281157 | MEMORY SYSTEM, MEMORY CONTROLLER AND METHOD - According to one embodiment, a memory system includes a plurality of non-volatile memory chips and a memory controller. The memory controller controls a read operation of the memory chips, and manages correspondence relation information between a logical address included in a read command and a physical address of the memory chip. The memory controller causes at least two memory chips to store the same correspondence relation information. Further, in the read operation, the memory controller reads the correspondence relation information from at least one memory chip among the plurality of memory chips storing the same correspondence relation information. | 09-18-2014 |
20140281158 | FILE DIFFERENTIATION BASED ON DATA BLOCK IDENTIFICATION - A memory system or flash card may include an algorithm for identifying and accounting for the rewrite frequency of data to be written to the card. The file system partition or file type of data may be used for monitoring rewrite frequency and predicting future rewrites. A learning algorithm that monitors rewrites may be implemented in firmware for accurate and dynamic identification of file types/partitions with the most likely rewrites. The identification of rewrites may be used to sort the data into groups (e.g. hot data=likely rewritten, and cold data=not likely to be rewritten). The hot data may stay in single level cell (SLC) update blocks longer, while the cold data can be moved to MLC blocks sooner. | 09-18-2014 |
20140281159 | MEMORY CONTROLLER - According to one embodiment, a memory controller includes an address conversion table, an address conversion circuit which executes a conversion of a first logical address for accessing to a primary storage device and a conversion of a second logical address for accessing to a secondary storage device, and a control circuit which is configured to access a nonvolatile memory as the primary storage device by receiving the first logical address, and access the nonvolatile memory as the secondary storage device by receiving the second logical address. | 09-18-2014 |
20140281160 | NON-VOLATILE SEMICONDUCTOR STORAGE APPARATUS - According to one embodiment, apparatus includes non-volatile memory chips, and a first controller which executes processing for reading first valid data stored in a first storage region of a first non-volatile memory chip in the non-volatile memory chips, processing for storing the first valid data in a buffer memory, processing for writing the first valid data stored in the buffer memory in a second storage region of the first non-volatile memory chip, and processing for erasing data stored in the first storage region. Each of the non-volatile memory chips comprises erase blocks. Each erase block includes write blocks. Each of the first storage region and the second storage region includes at least one erase block. | 09-18-2014 |
20140281161 | MEMORY SYSTEMS AND METHODS INCLUDING TRAINING, DATA ORGANIZING, AND/OR SHADOWING - Described embodiments include memory systems that may shadow certain data stored in a first memory device (e.g. NAND flash device) onto a second memory device (e.g. DRAM device). Memory systems may train and/or re-organize stored data to facilitate the selection of data to be shadowed. Initial responses to memory commands may be serviced from the first memory device, which may have a lower latency than the second memory device. The remaining data may be serviced from the second memory device. A controller may begin to access the remaining data while the initial response is being provided from the first memory device, which may reduce the apparent latency associated with the second memory device. | 09-18-2014 |
20140281162 | ADAPTIVE REFERENCE TUNING FOR ENDURANCE ENHANCEMENT OF NON-VOLATILE MEMORIES - A wear leveling technique is employed in a memory device so that the cycling history of a memory block is represented by the cycling history of a representative memory cell or a small number of representative memory cells. A control logic block tracks the cycling history of the one or more representative memory cells. A table tabulating the predicted shift in an optimal value for a reference variable for a sensing circuit as a function of cycling history is provided within the memory device. Prior to sensing a memory cell, the control logic block checks the total number of cycling in the one or more representative memory cells and adjusts the value for the reference variable in the sensing circuit, thereby providing an optimal value for the reference variable in the sensing circuit for each sensing cycle of the memory device. | 09-18-2014 |
20140281163 | MEMORY SYSTEM - According to one embodiment, a memory system includes a plurality of nonvolatile semiconductor memories configured to hold data, or a conversion table for converting a logical address of the data into a physical address of the data, a table memory configured to hold the conversion table, an interface configured to exchange data and a table with the plurality of nonvolatile semiconductor memories based on a command issue request. | 09-18-2014 |
20140281164 | MEMORY SYSTEM AND MEMORY CONTROLLER - According to one embodiment, a memory system includes a plurality of nonvolatile semiconductor memories including a plurality of memory cell transistors for holding data, and holding position information indicating a position of a defective memory cell transistor incapable of normally holding data and a position of a substitute portion for the defective memory cell transistor. | 09-18-2014 |
20140281165 | Integrated Circuit with a Patching Function - An integrated circuit with a patching function comprises a one-time programmable memory (OTP), a random access memory (RAM), and a control unit. The control unit copies data stored on the OTP into the RAM to obtain a copied image mirroring said data. It checks for presence of one or more patch instructions in the OTP, and, if a patch instruction is found in the OTP, modifies a portion of the copied image based on the patch instruction, to obtain a patched image stored in the RAM. The integrated circuit further comprises a processing unit configured to access the patched image in the RAM. The patch can be provided wirelessly. | 09-18-2014 |
20140281166 | METHOD OF OPERATING A MEMORY SYSTEM, THE MEMORY SYSTEM, AND A MEMORY CONTROLLER - In one embodiment, the method includes buffering, under control of a memory controller, received data and an associated program entity in a buffer. The program entity includes first address information and second address information, the first address information indicates an address of the buffer storing the received data, and the second address information indicates an address in the memory to store the received data. The method further includes storing, at the memory controller, management information. The management information includes program information, and the program information includes a pointer to the program entity in the buffer. The method also includes transferring the received data from the buffer to the memory based on the management information and the program entity. | 09-18-2014 |
20140281167 | COMPRESSOR RESOURCES FOR HIGH DENSITY STORAGE UNITS - In various embodiments, a high-density solid-state storage unit includes a plurality of flash cards. Each flash card has a flash controller that incorporates one or more resources for facilitating compression and decompression operations. In one aspect, data reduction and data reconstruction operations can be performed in-line as data is stored to and retrieved from flash memory. In another aspect, data reduction and data reconstruction operations can be performed as a service. Any one of the plurality of flash cards can be used to provide data reduction or data reconstruction services on demand for any type of data, including system data, libraries, and firmware code. | 09-18-2014 |
20140281168 | STORAGE SYSTEM AND METHOD OF CONTROL FOR STORAGE SYSTEM - The storage system includes a plurality of storage devices and a storage controller. The storage controller stores a data request quantity indicating the data quantity of write data written to the target area in a specific period, and estimates, based on the quantity of request data and relationship information received from storage devices, the estimated data quantity written to the nonvolatile semiconductor memory chips based on the write data written to the target area in the specific period. The storage controller selects a second logical storage area with an estimated data quantity less than an estimated data quantity for the first logical storage area and assigned to a storage device different from a storage device assigned to the first logical storage area, and migrates the first data stored in the first logical storage area to the second logical storage area. | 09-18-2014 |
20140281169 | FLASH-BASED STORAGE SYSTEM INCLUDING RECONFIGURABLE CIRCUITRY - Apparatus and method for accelerating processing operations of flash based storage systems are disclosed herein. In some embodiments, an IC component disposed between I/O circuitry and flash storage devices is configured to optimize fulfillment of data read and write requests originating from a network or device external to the flash based storage system using cache memory before involving the flash storage devices. | 09-18-2014 |
20140281170 | NONVOLATILE STORAGE DEVICE AND OPERATING SYSTEM (OS) IMAGE PROGRAM METHOD THEREOF - A nonvolatile storage device in accordance with the inventive concepts includes a nonvolatile memory device comprising a first memory area, a second memory area, and a memory controller. The memory controller includes a first register configured to store reliable mode information, and a second register configured to store operating system (OS) image information. The memory controller is configured to receive a command from a host based on the reliable mode information; determine whether the command is a write request for an OS image and whether OS image information accompanying the command matches the OS image information stored in the second register; write the OS image to the first memory area if the OS image information accompanying the command matches the OS image information stored in the second register, and block data migration of the OS image from the first memory area to the second memory area. | 09-18-2014 |
20140281171 | Lock-Free Communication Storage Request Reordering - Lock-free communication storage request reordering enables reduced latency and/or increased bandwidth in some usage scenarios, such as a multi-threaded driver context operating with a device, such as a storage device (e.g. a Solid-State Disk (SSD)) enabled to respond to a multiplicity of outstanding requests. | 09-18-2014 |
20140281172 | NONVOLATILE MEMORY DEVICE, ELECTRONIC DEVICE AND COMPUTING SYSTEM INCLUDING THE SAME - A nonvolatile memory device includes a memory onto which a flash translation layer is loaded, a controller, and first and second memory areas. The controller is configured to execute the flash translation layer. The nonvolatile memory is configured to receive write requested data and corresponding category information. The flash translation layer is configured to map a logical address of the write requested data to a physical address, based on the category information, such that the write requested data is selectively stored in one of the first and second memory areas. The category information is based on a storage characteristic of the write requested data. | 09-18-2014 |
20140281173 | NONVOLATILE MEMORY SYSTEM, SYSTEM INCLUDING THE SAME, AND METHOD OF ADAPTIVELY ADJUSTING USER STORAGE REGION IN THE SAME - A method is for adaptively adjusting a user storage region in an entire storage region of a nonvolatile memory system. The method includes a host transmitting a user region information request command to the nonvolatile memory system, the nonvolatile memory system transmitting user region information to the host, the host changing the user region information, the host transmitting a user region information setting command to the nonvolatile memory system, and the nonvolatile memory system controlling a size of the user storage region in response to the user region information setting command. | 09-18-2014 |
20140281174 | NON-VOLATILE MULTI-LEVEL CELL MEMORY SYSTEM AND METHOD OF PERFORMING ADAPTIVE DATA BACK-UP IN THE SYSTEM - In one example embodiment of the inventive concepts, an adaptive data backup method performed in a memory system including a non-volatile multi-level cell memory device includes receiving a write command from a host and determining a backup data size which is a size of data to be backed up among data requested to be written in the write command. The adaptive data backup method further includes selecting a backup type among at least two different backup types, based on the backup data size and backing up the data according to the selected backup type. | 09-18-2014 |
20140281175 | Program Method, Data Recovery Method, and Flash Memory Using the Same - A program method for a multi-level cell (MLC) flash memory is provided. The memory array includes a plurality of pages and a plurality of paired pages, which correspond to the respective pages. The program method includes the following steps. Firstly, a program address command is obtained. Next, whether the program address command corresponding to any one of the paired pages is determined. When the program address command corresponds to a first paired page, which corresponds to a first page among the pages, among the paired pages, data stored in the first page to a non-volatile memory are copied. After that, the first paired page is programmed. | 09-18-2014 |
20140281176 | ACCESSING METADATA WITH AN EXTERNAL HOST - Systems and processes may be used to retrieve metadata from a nonvolatile memory of a portable device and transmit the retrieved metadata to an external host. Metadata may be analyzed using the external host and/or at least a portion of the metadata may be modified based on the analysis. Modified metadata may be transmitted from the external host to a memory controller of the host. | 09-18-2014 |
20140281177 | HYBRID MEMORY MANAGEMENT - Methods and apparatus for managing data storage in hybrid memory devices utilizing single level and multi-level memory cells. Logical addresses can be distributed between single level and multilevel memory cells based on a frequency of write operations performed. Initial storage of data corresponding to a logical address in memory can be determined by various methods including initially writing all data to single level memory or initially writing all data to multilevel memory. Other methods permit a host to direct logical address writes to single level or multilevel memory cells based on anticipated usage. | 09-18-2014 |
20140281178 | METHOD FOR ASSIGNING ADDRESSES TO MEMORY DEVICES - A memory system having a memory controller and several separate memory devices connected to the controller by a system bus. The memory devices each included an array of memory cells, addressing circuitry used to address the cells and an address storage circuit which stores a local address unique to each of the memory devices. The local addresses are sequentially assigned to the memory devices by selecting a first one of the devices and forwarding an address assign command to the selected device. A command decoder, having detected the address assign command, will permit a local address placed on the bus by the controller to be loaded into the selected memory device. This sequence will continue until all of the memory devices have been assigned local addresses at which time the memory devices can be accessed to perform memory read, program, erase and other operations. | 09-18-2014 |
20140281179 | STOCHASTIC BLOCK ALLOCATION FOR IMPROVED WEAR LEVELING - Systems and methods are disclosed for stochastic block allocation for improved wear leveling for a system having non-volatile memory (“NVM”). The system can probabilistically allocate a block or super block for wear leveling based on statistics associated with the block or super block. In some embodiments, the system can select a set of blocks or super blocks based on a pre-determined threshold of a number of cycles (e.g., erase cycles and/or write cycles). The block or super block can then be selected from the set of super blocks. In other embodiments, the system can use a fully stochastic approach by selecting a block or super block based on a biased random variable. The biased random variable may be generated based in part on the number of cycles associated with each block or super block of the NVM. | 09-18-2014 |
20140289447 | APPARATUS, SYSTEM, AND METHOD FOR STORAGE SPACE RECOVERY - An apparatus, system, and method are disclosed for storage space recovery. A storage division selection module selects a first storage division for recovery. The first storage division comprises a portion of solid-state storage in a solid-state storage device. A data recovery module reads valid data from the first storage division in response to selecting the first storage division for recovery. The data recovery module stores the valid data in a second storage division of the solid-state storage device. The data recovery module passes the valid data through at least a portion of a write data pipeline for the solid-state storage device without passing the valid data to a host device and/or without routing the valid data outside of a solid-state storage controller for the solid-state storage device. | 09-25-2014 |
20140289448 | ADVANCED MEMORY INTERFACES AND METHODS - Controllers, interfaces, memory devices, methods and systems are disclosed, including a controller configured to interface with a separate memory device and perform an iterative write operation to program a selected memory cell of the memory device to a target state, wherein each iteration of the write operation is configured to successively change a physical state of the selected memory cell. Other controllers, interfaces, memory device, methods and systems are also described, such as those where either a controller or a memory device can throttle a data communication operation, and/or those that utilize customized programming pulses. | 09-25-2014 |
20140289449 | STORAGE APPARATUS, STORAGE CONTROLLER AND METHOD FOR RELOCATING DATA IN SOLID STATE DRIVE - According to one embodiment, a storage controller comprises an access statistic collection unit, a selection unit and a rewrite unit. The access statistic collection unit collects write frequencies of a plurality of small logical address areas having a predetermined size which configure a logical area of a logical unit defined using a solid state drive. The selection unit selects a set of first small logical address areas having low write frequencies from the logical unit. The rewrite unit collectively rewrites data of the set of the first small logical address areas to the solid state drive, and collectively rewrites data of a set of remaining second small logical address areas to the solid state drive. | 09-25-2014 |
20140289450 | Dynamic Log Likelihood Ratio Quantization for Solid State Drive Controllers - A method for system for dynamic channel Log Likelihood Ratio (LLR) quantization for a Solid State Drive (SSD) controller is a targeted approach to scaling which results in a scaled, quantized set of LLRs whose relative magnitude remains undisturbed from an original magnitude. The method reads a set of voltages from each channel of the SSD. The set of reads is configured in location and number for performance. Once a set is returned, the method determines an LLR for each of the voltages read resulting in a raw set of LLRs. Targeted scaling results in a scaled set of LLRs between an upper limit and a lower limit determined for reading by a decoder. Once scaled, the LLRs are rounded and quantized for use by the decoder to produce an Error Correction Code (ECC). | 09-25-2014 |
20140289451 | METHOD OF RECORDING MAPPING INFORMATION, AND MEMORY CONTROLLER AND MEMORY STORAGE APPARATUS USING THE SAME - A method of recording mapping information for a rewritable non-volatile memory module is provided. The method includes configuring a plurality of logical addresses, establishing at least one logical address mapping table, and storing the at least one logical address mapping table into the rewritable non-volatile memory module. The method also includes receiving data to be stored into a plurality of continuous logical addresses from a host system, writing the data into a plurality of physical programming units, updating mapping relations between the continuous logical addresses and the physical programming units in a corresponding logical address mapping table loaded to a buffer memory, storing a continuous mapping table in the buffer memory, and recording a continuous mapping record corresponding to the continuous logical addresses in the continuous mapping table. | 09-25-2014 |
20140289452 | ELECTRONIC EQUIPMENT INCLUDING STORAGE DEVICE - According to one embodiment, a storage device includes a nonvolatile memory, controller and interface. The nonvolatile memory stores data. The controller controls the operation of the nonvolatile memory. The interface includes first and second input/output units that transmit and receive a signal with respect to a host device. The first and second input/output units are set on the first hierarchy having the same communication function. The interface issues a connection request to the first input/output unit and when the connection request to the first input/output unit is rejected, the interface issues the connection request to the second input/output unit. | 09-25-2014 |
20140289453 | MEMORY SYSTEM AND CONSTRUCTING METHOD OF VIRTUAL BLOCK - According to one embodiment, a virtual block is constructed according to configuration conditions that, when a plurality of physical blocks included in the virtual block are selected, the sum of the number of physical block pairs and the number of single blocks allocated from the same memory chip to one virtual block is less than or equal to a first value. | 09-25-2014 |
20140289454 | STORAGE DEVICE AND CONTROLLER - A storage device includes a memory having one or more storage regions each of which is assigned a physical address, and a controller having a writing control circuit configured to write data that is divided into a plurality of data units into logical storage positions, at least one of which is associated with two storage regions of the memory, and a conversion unit configured to perform a conversion process on a logical address of the logical storage position that is associated with two storage regions of the memory to generate physical addresses corresponding to the two storage regions of the memory. | 09-25-2014 |
20140289455 | Memory Patching Circuit - A patching circuit for patching a memory | 09-25-2014 |
20140289456 | DISK LOGGING METHOD APPLICABLE TO STORAGE MEDIUM AND ELECTRNOIC DEVICE, STORAGE MEDIUM USING THE SAME AND ELECTRONIC DEVICE USING THE SAME - The present disclosure proposes a disk logging method configured for an electronic device comprising a temporary non-volatile storage medium to log data from a volatile memory to said first storage medium, and the method includes the elements of aggregating data from applications of the electronic device in a queue, transferring the aggregated data to a per device queue targeted toward a native queue of the storage medium, writing the data stored in the native queue of the storage medium into a disk platter of the storage medium, and transmitting an interrupt in response to the completion of the writing of the data to the disk platter, wherein the first batch size is dynamically adjusted such that the step of writing the data to the platter takes more time than the step of transferring the data from the per device queue to the native queue of the storage medium. | 09-25-2014 |
20140289457 | METHOD AND DEVICE TO REDUCE LEAKAGE AND DYNAMIC ENERGY CONSUMPTION IN HIGH-SPEED MEMORIES - A microcomputer comprising a microprocessor unit and a first memory unit is disclosed. In one aspect, the microprocessor unit comprises at least one functional unit and at least one register. Further, the at least one register is a wide register comprising a plurality of second memory units which are capable to each contain one word, the wide register being adapted so that the second memory units are simultaneously accessible by the first memory unit, and at least part of the second memory units are separately accessible by the at least one functional unit. Further, the first memory unit is an embedded non-volatile memory unit. | 09-25-2014 |
20140289458 | SYSTEM AND METHOD FOR MICRO-TIERING IN NON-VOLATILE MEMORY - In a storage device such as a solid state disk (SSD), a central controller communicates with a plurality of multi-chip memory packages. Each multi-chip memory package comprises a plurality of memory dies and a local processor, wherein the plurality of memory dies includes different memory tiers. The central controller may handle management of the virtual address space while the local processor in each MCP manages the storage of data within memory tiers in the memory dies of its respective MCP. | 09-25-2014 |
20140289459 | STORAGE SYSTEM - The temporary area capacity required to be secured with respect to the whole permanent area is calculated in accordance with the capacity and access frequency of a host computer data permanent area of a disk device contained in the storage system and a disk device of an external storage device that is managed by a storage virtualization function of this storage system. The nonvolatile memory is defined as the temporary area and is used to temporarily store host computer data when a data I/O from the host computer is processed. The required capacity of the temporary area is re-calculated in accordance with an event such as a configuration change in the external storage system. | 09-25-2014 |
20140297921 | Method of Partitioning Physical Block and Memory System Thereof - A method of partitioning a physical block in a memory includes: determining a sub-block size according to a data length of a sequential write and a block size; partitioning the physical block into sub-blocks, each having a size equal to the sub-block size; and mapping logical blocks to the sub-blocks. | 10-02-2014 |
20140297922 | METHOD AND APPARATUS FOR MANAGING SERIAL PERIPHERAL INTERFACE (SPI) FLASH - A system for communicating with a flash device includes: a controller configured for communicating with the flash device, the controller including logic for classifying a command to the flash device as one of safe and unsafe and communicating each safe command. Methods and a computer program product and a computing system are disclosed. | 10-02-2014 |
20140297923 | Populating Localized Fast Bulk Storage in a Multi-Node Computer System - A high performance computing (HPC) system includes computing blades having a first region that includes processors for performing a computation, and a second region that includes non-volatile memory for use in performing the computation and another computing processor for performing data movement and storage. Because data movement and storage are offloaded to the secondary processor, the processors for performing the computation are not interrupted to perform these tasks. A method for use in the HPC system receives instructions in the computing processors and first data in the memory. The method includes receiving second data into the memory while continuing to execute the instructions in the computing processors, without interruption. A computer program product implementing the method is also disclosed. | 10-02-2014 |
20140297924 | NONVOLATILE MEMORY ERASURE TECHNIQUES - Embodiments of the present disclosure describe methods, apparatus, and system configurations for conditional pre-programming of nonvolatile memory before erasure. In one instance, the method includes receiving a request to erase information in a portion of the nonvolatile memory device, in which the portion includes a plurality of storage units, determining whether one or more storage units of the plurality of storage units included in the portion of the non-volatile memory device are programmed, pre-programming the portion of the non-volatile memory device if the one or more storage units are determined to be programmed, and erasing the pre-programmed portion of the non-volatile memory device. A number of determined programmed storage units may not exceed a predetermined value. Other embodiments may be described and/or claimed. | 10-02-2014 |
20140297925 | STORAGE DEVICE WITH SELF-CONTAINED INFORMATION STORAGE SPACE - A storage device with self-contained information storage space includes at least a type-I non-volatile memory and a type-II non-volatile memory which form a data storage region and an information storage region, respectively. The type-II non-volatile memory has higher endurance than the type-I non-volatile memory. The type-I and type-II non-volatile memory are connected to a controller through a parallel interface and a series interface, respectively. The storage device uses the high-storage-density type-I non-volatile memory to meet high-capacity storage space requirement and uses the high-endurance type-II non-volatile memory to store important information and therefore ensure system stability, thereby solving problems facing existing storage devices—information stored in high-storage-density memory gets damaged easily because of an increase in programming/erase (P/E) cycles thereof. | 10-02-2014 |
20140297926 | INFORMATION PROCESSING DEVICE AND METHOD FOR CONTROLLING REPLACEMENT OF SEMICONDUCTOR STORAGE DEVICE - A processor or hard-wired logic circuit of an information processing device is configured to collect a life-expectancy index value of a first semiconductor storage device of primary semiconductor storage devices. The life-expectancy index value relates to a remaining number of times written data is able to be erased. The processor or hard-wired logic circuit is configured to collect read/write information regarding read/write access including read access of reading data from the first semiconductor storage device and write access of writing data to the first semiconductor storage device. The processor or hard-wired logic circuit is configured to determine, based on the collected read/write information, a criterion threshold used as a criterion for replacement of the first semiconductor storage device, and replace the first semiconductor storage device with a second semiconductor storage device of secondary semiconductor storage devices if the life-expectancy index value is less than the criterion threshold. | 10-02-2014 |
20140297927 | INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, AND RECORDING MEDIUM - An information processing apparatus includes a main storage device, in which the main storage device includes a non-volatile storage unit and a volatile storage unit, and a page is moved between the non-volatile storage unit and the volatile storage unit at a predetermined timing based on a priority that is assigned to the page. | 10-02-2014 |
20140297928 | Electronic Circuit for and Method of Executing an Application Program Stored in a One-Time-Programmable (OTP) Memory in a System on Chip (SoC) - A method and apparatus for executing an application program stored in an one-time-programmable, OTP, memory in a system on chip (SoC) is described. The SoC has RAM, a CPU and an OTP controller. The OTP memory stores an application program. The method includes, by the processor unit at power-up, instructing the OTP controller to copy the application program from the OTP memory to RAM, executing the application program from RAM, and setting the system on chip (SoC) in sleep mode. By the OTP controller after a wake-up, copying the application program from the OTP memory to the RAM and after the copying, waking up the CPU and transferring control back to the CPU. By the CPU after being woken up by the OTP controller, executing the application program from RAM. | 10-02-2014 |
20140297929 | NON-VOLATILE MEMORY INTERFACE - Apparatuses, systems, methods, and computer program products are disclosed for a memory controller. An apparatus includes a volatile memory medium located on a memory module. An apparatus includes a non-volatile memory medium located on a memory module. A memory controller is located on a memory module. A memory controller may be configured to provide access to at least a non-volatile memory medium over a direct wire interface with a processor. | 10-02-2014 |
20140297930 | MEMORY SYSTEM - According to the embodiments, a memory system includes a nonvolatile semiconductor memory and a writing-loop-count monitoring unit that monitors a loop count of an applied voltage to the nonvolatile semiconductor memory required for data writing of the nonvolatile semiconductor memory as a writing loop count. Moreover, the memory system includes a management table for managing the writing loop count in block unit that is a unit of data erasing and a life managing unit that determines a degraded state of the nonvolatile semiconductor memory based on the management table. | 10-02-2014 |
20140297931 | METHOD FOR WEAR LEVELING IN A NONVOLATILE MEMORY - A method for writing and reading data memory cells, comprising: defining in a first memory zone erasable data pages and programmable data blocks; and, in response to write commands of data, writing data in erased blocks of the first memory zone, and writing, in a second memory zone, metadata structures associated with data pages and comprising, for each data page, a wear counter containing a value representative of the number of times that the page has been erased. | 10-02-2014 |
20140297932 | MEMORY SYSTEM IN WHICH EXTENSION FUNCTION CAN EASILY BE SET - According to one embodiment, a non-transitory medium, a controller, a memory, an extension function section, and an extension register. The controller controls the non-transitory medium. The memory which is serving as a work area is connected to the controller. The extension function section is controlled by the controller. The extension register which is provided on the memory is provided with a certain block length capable of defining an extension function of the extension function section. The controller processes a first command to write header data of a command to operate the extension function section to the extension function section through the extension register, and a second command to read header data of a response from the extension function section through the extension register. | 10-02-2014 |
20140297933 | NUMERIC REPRESENTATION TO IMPROVE LIFE OF SOLID STATE STORAGE DEVICES - Technologies and implementations for improving life of a solid state storage device are generally disclosed. | 10-02-2014 |
20140297934 | METHOD AND APPARATUS FOR OPTIMIZING THE PERFORMANCE OF A STORAGE SYSTEM - Methods and apparatuses for optimizing the performance of a storage system comprise a FLASH storage system, a hard drive storage system, and a storage controller. The storage controller is adapted to receive READ and WRITE requests from an external host, and is coupled to the FLASH storage system and the hard drive storage system. The storage controller receives a WRITE request from an external host containing data and an address, forwards the received WRITE request to the FLASH storage system and associates the address provided in the WRITE request with a selected alternative address, and provides an alternative WRITE request, including the selected alternative address and the data received in the WRITE request, to the hard drive storage system, wherein the alternative address is selected to promote sequential WRITE operations within the hard drive storage system. | 10-02-2014 |
20140297935 | MOUNT-TIME RECONCILIATION OF DATA AVAILABILITY - Systems and methods are disclosed for mount-time reconciliation of data availability. During system boot-up, a non-volatile memory (“NVM”) driver can be enumerated, and an NVM driver mapping can be obtained. The NVM driver mapping can include the actual availability of LBAs in the NVM. A file system can then be mounted, and a file system allocation state can be generated. The file system allocation state can indicate the file system's view of the availability of LBAs. Subsequently, data availability reconciliation can be performed. That is, the file system allocation state and the NVM driver mapping can be overlaid and compared with one another in order to expose any discrepancies. | 10-02-2014 |
20140297936 | NON-VOLATILE MEMORY STORAGE APPARATUS, MEMORY CONTROLLER AND DATA STORING METHOD - A non-volatile memory storage apparatus having a connector, an energy storage circuit, a power regulator and supply circuit, a non-volatile memory module, a memory controller and a buffer memory is provided. The power regulator and supply circuit is configured for transforming an output voltage from the energy storage circuit into a first voltage used for the non-volatile memory module and a second voltage used for the memory controller and the buffer memory. The memory controller is configured for writing data stored temporarily in the buffer memory into the non-volatile memory module with a special writing mode when receiving a detecting signal indicating that an input voltage is continuously smaller than a predetermined voltage for a predetermined period or receiving a detecting signal indicating that an inactive status of the connector or receiving a suspend mode signal, a warm reset signal or a hot reset signal from a host system. | 10-02-2014 |
20140297937 | SEGMENTED CACHES - Embodiments herein relate to segmenting and pinning a first non-volatile memory to store cache information. In an embodiment, the first non-volatile memory is divided into a plurality of segments. Then, a first type of software of a plurality of types of software is pinned to a first segment of the plurality of segments. The first pinned segment stores the cache information associated with the first type of software. | 10-02-2014 |
20140304451 | COMPUTER SYSTEM AND MANAGEMENT SYSTEM - A storage system, which comprises multiple memory cells and a storage controller, wherein the storage controller manages cell mode information, which either directly or indirectly denotes the number of bits to be stored in multiple memory cells. The cell mode information can be changed in accordance with a request from a management system. | 10-09-2014 |
20140304452 | METHOD FOR INCREASING STORAGE MEDIA PERFORMANCE - A storage access system provides consistent memory access times for storage media with inconsistent access latency and reduces bottlenecks caused by the variable time delays during memory write operations. Data is written iteratively into multiple different media devices to prevent write operations from blocking all other memory access operations. The multiple copies of the same data then allow subsequent read operations to avoid the media devices currently servicing the write operations. Write operations can be aggregated together to improve the overall write performance to a storage media. A performance index determines how many media devices store the same data. The number of possible concurrent reads varies according to the number of media devices storing the data. Therefore, the performance index provides different selectable Quality of Service (QoS) for data in the storage media. | 10-09-2014 |
20140304453 | Effective Caching for Demand-based Flash Translation Layers in Large-Scale Flash Memory Storage Systems - This invention discloses methods for implementing a flash translation layer in a computer subsystem comprising a flash memory and a random access memory (RAM). According to one disclosed method, the flash memory comprises data blocks for storing real data and translation blocks for storing address-mapping information. The RAM includes a cache space allocation table and a translation page mapping table. The cache space allocation table may be partitioned into a first cache space and a second cache space. Upon receiving an address-translating request, the cache space allocation table is searched to identify if an address-mapping data structure that matches the request is present. If not, the translation blocks are searched for the matched address-mapping data structure, where the physical page addresses for accessing the translation blocks are provided by the translation page mapping table. The matched address-translating data structure is also used to update the cache space allocation table. | 10-09-2014 |
20140304454 | DATA HARDENING IN A STORAGE SYSTEM - A storage system, and a method of data hardening in the storage system, including: a de-glitch module configured for a detection of a power failure event; a write page module, coupled to the de-glitch module, the write page module configured for an execution of a cache write command based on the power failure event to send a cache page from a cache memory to a storage channel controller, wherein the cache memory is a volatile memory; and a signal empty module, coupled to the write page module, the signal empty module configured for a generation of a sleep signal to shut down a host bus adapter, wherein the host bus adapter interfaces with the storage channel controller to write the cache page back to the cache memory upon a power up of the host bus adapter and the storage channel controller. | 10-09-2014 |
20140304455 | DATA MANAGEMENT IN A STORAGE SYSTEM - A storage system, and a method of data management in the storage system, with non-volatile memory device characteristics determined during an inspection of non-volatile memory devices before a runtime operation of a storage device in the storage system including: a controller in the storage system: a drive-level control unit configured for an update of operational capabilities based on the non-volatile memory device characteristics during the runtime operation of the storage device and for a group of the non-volatile memory devices based on the operational capabilities; and a memory control unit, coupled to the drive-level control unit, the memory control unit configured to receive the operational capabilities for control of the non-volatile memory devices. | 10-09-2014 |
20140304456 | MEMORY APPARATUS AND METHODS THEREOF FOR PREVENTING READ ERRORS ON WEAK PAGES IN A NON-VOLATILE MEMORY SYSTEM - A memory apparatus and methods are provided for preventing read errors on weak pages in a non-volatile memory system. In one example, a method includes identifying a weak page in a non-volatile memory device along a word line, wherein the weak page is partially written with at least some data; buffering data associated with the weak page to a weak page buffer that is coupled in communication with the non-volatile memory device; determining that an amount of data in the weak page buffer has reached a predetermined data level; and writing the data from the weak page buffer into the weak page along the word line in the non-volatile memory device. | 10-09-2014 |
20140304457 | NONVOLATILE STORAGE DEVICE AND METHOD OF STORING DATA THEREOF - A data storing method of a nonvolatile storage device that includes a plurality of nonvolatile memory devices electrically connected to a plurality of channels is provided. The data storing method includes allocating part of write data provided from a host to the nonvolatile memory devices to each channel; determining whether at least one channel among the channels is present that is connected to a nonvolatile memory device in a last page offset state; and when the at least one channel is determined to be present, scheduling erase commands on the plurality of channels, scheduling write commands on the plurality of channels with respect to the allocated write data, and executing the erase commands and the write commands on the plurality of channels. | 10-09-2014 |
20140304458 | MEMORY CONTROLLER AND ACCESSING SYSTEM UTILIZING THE SAME - A memory controller including a first transmittal module, a clock pin, a second transmittal module, a first control module and a second control module is disclosed. The first transmittal module includes a specific pin. The clock pin receives a clock signal. The first transmittal module and the clock pin constitute an embedded multimedia card (eMMC) interface. The second transmittal module and the clock pin constitute a universal flash storage (UFS) interface. The first control module communicates with an external host via the first transmittal module according to the clock signal when a level of the specific pin is at a first level. The second control module communicates with the external host via the second transmittal module according to the clock signal when the level of the specific pin is at a second level. The first level exceeds the second level. | 10-09-2014 |
20140304459 | MULTI LEVEL CELL MEMORY SYSTEM - A multi level cell memory system may include a nonvolatile memory device including a memory cell array configured to store first bit page data and second bit page data, and a page buffer configured to store data to be programmed in the memory cell array; and a memory controller configured to input first bit page data and second bit page data into the page buffer, wherein the memory controller is configured such that the memory controller inputs the first bit page data into the page buffer to temporarily store the first bit page data in a first bit page program operation, and inputs the second bit page data into the page buffer together with the temporarily stored first bit page data in a second bit page program operation. | 10-09-2014 |
20140304460 | Multiprocessor System with Independent Direct Access to Bulk Solid State Memory Resources - A system includes a collection of central processing units, where each central processing unit is connected to at least one other central processing unit and a root path into at least 10 Tera Bytes of solid state memory resources. Each central processing unit directly accesses solid state memory resources without swapping solid state memory contents into main memory. | 10-09-2014 |
20140304461 | STORAGE SUBSYSTEM - The storage system includes a plurality of flash memory devices, each of the flash memory devices including a flash memory controller and flash memory chips, which are configured as a RAID group and a storage controller, coupled to the plurality of flash memory devices, configured to receive data from a computer and send the data to a first flash memory device of the plurality of flash memory devices. The flash memory controller of the flash memory device is configured to receive the data from the storage controller and execute a parity operation using the data. | 10-09-2014 |
20140310445 | STORAGE CONTROL SYSTEM WITH POWER-OFF TIME ESTIMATION MECHANISM AND METHOD OF OPERATION THEREOF - A storage control system, and a method of operation thereof, including: a power-down module for powering off a memory sub-system; a decay estimation module, coupled to the power-down module, for estimating a power-off decay rate upon the memory sub-system powered up, the power-off decay rate is for indicating how much data in the memory sub-system has decayed while the memory sub-system has been powered down; and a recycle module, coupled to the decay estimation module, for recycling an erase block for data retention based on the power-off decay rate. | 10-16-2014 |
20140310446 | CIRCUIT FOR GENERATING A START SEQUENCE AND METHOD FOR GENERATING A START SEQUENCE - The invention relates to a circuit and to a method for generating a start sequence. The circuit comprises at least one partially programmable memory (nonvol) for storing an encoded start sequence (Ni) and a control unit (CTRL), which is equipped to read the encoded start sequence (Ni) and decode it into a decoded start sequence (dNi) and to generate a target register address (n) depending on the decoded start sequence (dNi). An addressable memory (vol) is provided, to which the decoded start sequence (dNi) can be written by means of the control unit (CTRL) at the target register address (n). | 10-16-2014 |
20140310447 | HALF BLOCK MANAGEMENT FOR FLASH STORAGE DEVICES - A method for managing block erase operations is provided for an array of memory cells including erasable blocks of memory cells in the array. The method comprises maintaining status data for a plurality of sub-blocks of the erasable blocks of the array. The status data indicate whether the sub-blocks are currently accessible and whether the sub-blocks are invalid. The method comprises, in response to a request to erase a selected sub-block of a particular erasable block, issuing an erase command to erase the particular block if the other sub-blocks of the particular erasable block are invalid, else updating the status data to indicate that the selected sub-block is invalid. | 10-16-2014 |
20140310448 | METHOD OF OPERATING MEMORY CONTROLLER AND DATA STORAGE DEVICE INCLUDING MEMORY CONTROLLER - In one embodiment, the method includes determining, at the memory controller, a status of a selected page of memory based on a program/erase cycle count for a block of the memory. The block of the memory includes the selected page. The program/erase cycle count indicates a number of times the block has been erased. The status is selected from a plurality of status states. The status states include a normal state, a weak state and a bad state. | 10-16-2014 |
20140310449 | Virtualization of Storage Devices - Systems and techniques relating to storage technologies include, according to an aspect, a data processing apparatus including: a processor; a controller coupled with the processor; a solid state drive coupled with the controller; and a mass storage drive coupled with the controller; wherein at least a portion of the solid state drive and the mass storage drive are virtualized as a single physical storage drive; wherein multiple applications stored in the virtualized single physical storage drive are configured to run on the processor; wherein one or more applications in a hot application group are stored in the solid state drive, and one or more applications in a cold application group are stored in the mass storage drive; and wherein each of the multiple applications is actively monitored and placed in either the hot application group or the cold application group. | 10-16-2014 |
20140310450 | External Memory Controller Node - A memory controller to provide memory access services in an adaptive computing engine is provided. The controller comprises: a network interface configured to receive a memory request from a programmable network; and a memory interface configured to access a memory to fulfill the memory request from the programmable network, wherein the memory interface receives and provides data for the memory request to the network interface, the network interface configured to send data to and receive data from the programmable network. | 10-16-2014 |
20140317334 | STORAGE OF GATE TRAINING PARAMETERS FOR DEVICES UTILIZING RANDOM ACCESS MEMORY - Methods and structure are provided for maintaining gate training parameters for Random Access Memory. The system comprises a memory controller and a management unit. The management unit is able to initialize the system after the system returns from an unpowered state by accessing a non-volatile memory to retrieve timing intervals for electrical impulses sent between the memory controller and a Random Access Memory. The timing intervals previously enabled communication between the memory controller and the Random Access Memory. The management unit is further able to initialize the system after the system returns from an unpowered state by calibrating the memory controller to enable communication with the Random Access Memory based on the retrieved timing intervals. | 10-23-2014 |
20140317335 | DATA STORAGE DEVICE, STORAGE CONTROLLER, AND DATA STORAGE CONTROL METHOD - According to one embodiment, a data storage device includes a first storage medium, a second nonvolatile storage medium, and a controller. The controller allows write data requested to be written from a host device to be recorded into the first storage medium which is a cache memory of the second storage medium according to a first recording method and allows read data that is read from the second storage medium to be recorded into the first storage medium according to a second recording method that provides lower reliability but larger memory capacity than the first recording method. | 10-23-2014 |
20140317336 | LOCAL DIRECT STORAGE CLASS MEMORY ACCESS - A queued, byte addressed system and method for accessing flash memory and other non-volatile storage class memory, and potentially other types of non-volatile memory (NVM) storage systems. In a host device, e.g., a standalone or networked computer, having attached NVM device storage integrated into a switching fabric wherein the NVM device appears as an industry standard OFED™ RDMA verbs provider. The verbs provider enables communicating with a ‘local storage peer’ using the existing OpenFabrics RDMA host functionality. User applications issue RDMA Read/Write directives to the ‘local peer (seen as a persistent storage) in NVM enabling NVM memory access at byte granularity. The queued, byte addressed system and method provides for Zero copy NVM access. The methods enables operations that establish application private Queue Pairs to provide asynchronous NVM memory access operations at byte level granularity. | 10-23-2014 |
20140317337 | METADATA MANAGEMENT AND SUPPORT FOR PHASE CHANGE MEMORY WITH SWITCH (PCMS) - Methods and apparatus related to management and/or support of metadata for PCMS (Phase Change Memory with Switch) devices are described. In one embodiment, a PCMS controller allows access to a PCMS device based on metadata. The metadata may be used to provide efficiency, endurance, error correction, etc. as discussed in the disclosure. Other embodiments are also disclosed and claimed. | 10-23-2014 |
20140317338 | MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME, AND OPERATION METHOD OF MEMORY DEVICE - A memory device includes a memory cell array having a plurality of memory cells, a storage unit suitable for storing a fail address corresponding to a fail memory cell in the memory cell array, an available storage capacity determination unit suitable for generating available capacity information indicating an available storage capacity in the storage unit, and an output circuit suitable for outputting the available capacity information. | 10-23-2014 |
20140317339 | DATA ACCESS SYSTEM, DATA ACCESSING DEVICE, AND DATA ACCESSING CONTROLLER - A data access system, device and controller are provided. The data access system includes a plurality of storage units and first controllers, a second controller, and a host. The first controller is utilized to parallel access the storage units, and each first controller includes a plurality of first storage unit controllers, a buffer and a multiplexer. The first storage unit controllers are coupled one-to-one with the storage units. The multiplexer is coupled to the first storage unit controllers and the buffer. The second controller is coupled to the first controllers. The second controller includes a plurality of second storage unit controllers which are coupled one-to-one with the first controllers. The host is coupled to the second controller, and accesses the storage units through the second controller and the first controllers. | 10-23-2014 |
20140317340 | STORAGE SYSTEM AND STORAGE CONTROL METHOD - A storage system includes: a storage device including a recording medium that stores data and a device controller that executes addition processing involving a change of state of the data with respect to the data; and a storage controller that controls input and output of data for the storage device. The storage controller transmits, to the storage device, determination information that can be utilized by the device controller for determining whether or not to execute the addition processing along with input-output processing relating to input-output target data. The device controller controls execution of the addition processing with respect to the input-output target data based on the determination information transmitted from the storage controller. | 10-23-2014 |
20140317341 | SYSTEM AND APPARATUS FOR FLASH MEMORY DATA MANAGEMENT - The system and apparatus for managing flash memory data includes a host transmitting data, wherein when the data transmitted from the host have a first time transmission trait and the address for the data indicates a temporary address, temporary data are retrieved from the temporary address to an external buffer. A writing command is then executed and the temporary data having a destination address are written to a flash memory buffer. When the flash memory buffer is not full, the buffer data are written into a temporary block of the flash memory. The writing of buffer data into the temporary block includes using an address changing command, or executing a writing command to rewrite the external buffer data to the flash memory buffer so that the data are written into the temporary block. | 10-23-2014 |
20140325116 | SELECTIVELY PERSISTING APPLICATION PROGRAM DATA FROM SYSTEM MEMORY TO NON-VOLATILE DATA STORAGE - Application program data stored in system memory may be selectively persisted. An indication may be provided to an application program that an application data object or a range of application data stored in system memory may be treated as persistent. Data backup may be enabled for the application data object or range of application data in the event of a system failure, copying the application data object or range of application data from system memory to non-volatile data storage. Upon recovery from a system failure, further data backup for the application data object or the range of application data may be disabled. In some embodiments, at least some of the application data object or range of application data may be recovered for the application program to access. Data backup for the application data object or the range of application data may also be re-enabled. | 10-30-2014 |
20140325117 | FLASH TRANSLATION LAYER WITH LOWER WRITE AMPLIFICATION - A method of associating a logical block address with a physical location in a non-volatile memory includes (A) in response to a write request comprising a respective logical block address in a logical block address space and respective data to be written to the non-volatile memory, determining a physical location in the non-volatile memory to store the respective data of the write request, (B) adding an entry to a journal, such that the added entry trails any entries already in the journal and the added entry has a respective logical block address field set to the respective logical block address of the write request and a respective physical location field set to the determined physical location, and (C) updating one of a plurality of second-level map pages in a two-level map according to the respective logical block address of the write request with the determined physical location. | 10-30-2014 |
20140325118 | DATA WRITING METHOD, MEMORY CONTROLLER AND MEMORY STORAGE APPARATUS - A data writing method for writing data into a physical erasing unit and a memory controller and a memory storage apparatus using the data writing method are provided. The method includes dividing the data into a plurality of information frames in a unit of one physical programming unit. The method also includes writing the information frames in sequence into at least one physical programming unit constituted by memory cells disposed on at least one first word line and programming the storage state of memory cells disposed on at least one second word line following the first word line to an auxiliary pattern. Accordingly, the method effectively prevents data stored in the physical erasing unit, which is not full of data, from being lost due to a high temperature. | 10-30-2014 |
20140325119 | WRITING METHOD, MEMORY CONTROLLER AND MEMORY STORAGE DEVICE - A writing method, a memory controller and a memory storage device are provided. The writing method includes steps of: configuring logical addresses to map to part of physical programming units in a storage area, wherein at least one of the physical programming units stores a valid data; transmitting a first write command for writing data having a first data length to at least one of the physical programming units; receiving a status signal; and selecting a spare physical erasing unit and copying the valid data having a second data length to the spare physical erasing unit, after transmitting the first write command and before receiving the status signal, wherein the first data length is not greater than the second data length. Therefore, it prevents a host system from waiting too long when writing data. | 10-30-2014 |
20140325120 | RESISTIVE MEMORY DEVICE AND OPERATION METHOD THEREOF - A resistive memory device includes a memory cell array including a unit memory cell coupled between a word line and a bit line, wherein the unit memory cell includes a data storage material and a non-silicon-substrate-based type bidirectional access device coupled in series, a path setting circuit coupled between the bit line and the word line, suitable for providing a program pulse toward the bit line or the word line based on a path control signal, a forward write command, and a reverse write command, and a control unit suitable for providing a write path control signal, a forward program command, and a reverse program command based on an external command signal. | 10-30-2014 |
20140325121 | STORAGE SYSTEM - A storage system monitors the first access frequency of occurrence which is the access frequency of occurrence from a host device during a first period, and the second access frequency of occurrence which is the access frequency of occurrence from a host device during a second period shorter than the first period. Along with performing data relocation among the tiers (levels) in the first period cycle based on the first access frequency of occurrence, the storage system performs a decision whether or not to perform a second relocation based on the first access frequency of occurrence and the second access frequency of occurrence, synchronously with access from a host device. Here the threshold value utilized in a decision on whether or not to perform the first relocation is different from the threshold value utilized in a decision on whether or not to perform the second relocation. | 10-30-2014 |
20140325122 | NONVOLATILE MEMORY SYSTEM INCLUDING NONVOLATILE MEMORY DEVICE, MEMORY CONTROLLER AND OPERATING METHOD THEREOF - An operating method of a memory controller that controls a nonvolatile memory device is provided. A command is received from an external device. Whether the nonvolatile memory device is in a temperature control mode is determined. When the nonvolatile memory device is in the temperature control mode, the received command is delayed for a predetermined time until the received command is outputted to the nonvolatile memory device. When the nonvolatile memory device is in the temperature control mode, the nonvolatile memory device is in an idle state. | 10-30-2014 |
20140325123 | INFORMATION PROCESSING APPARATUS, CONTROL CIRCUIT, AND CONTROL METHOD - An information processing apparatus includes a cyclic frequency counter that updates a count value when a process that determines whether data stored in each of multiple storage areas included in NAND devices is targeted for a move has been executed on all pieces of data stored in the NAND devices. Furthermore, the information processing apparatus includes a table storing unit that stores therein, when data is stored in one of the NAND devices, the count value of the cyclic frequency counter associated with the data. Furthermore, the information processing apparatus includes a cyclic reference control unit that compares, for each data stored in the NAND devices, a value stored in the table storing unit with the count value of the cyclic frequency counter and then determines whether each piece of data is targeted for a move. | 10-30-2014 |
20140325124 | MEMORY SYSTEM AND METHOD FOR OPERATING A MEMORY SYSTEM - A memory system for storing data in a plurality N of memory chips. The memory system includes a number K of sets of memory chips, wherein each set of the K sets includes a number M of the memory chips, with N=K·M; and one signal processing unit having a number L of signal processing engines for signal processing data of the N memory chips and having a data link interface for interfacing each of the K sets. | 10-30-2014 |
20140325125 | ATOMIC WRITE METHODS - A method of transmitting atomic write data from a host to a data storage device in a data system includes; communicating a header identifying a plurality of data chunks associated with an atomic write operation from the host to the data storage device and storing the header in a buffering area designated in the data storage device, then successively communicating the plurality of data chunks from the host to the data storage device and successively storing the each one of the plurality of data chunks in the buffering area, and then storing write data including at least the plurality of data chunks in a first area of storage media in the data storage device. | 10-30-2014 |
20140325126 | DATA STORAGE DEVICE PERFORMING ATOMIC WRITE AND RELATED METHOD OF OPERATION - A method of operating a data storage device comprises allocating a plurality of data blocks among received data to a plurality of intellectual property (IP) cores, performing an atomic write independently for of the IP cores, wherein the atomic write for each of the IP cores writes corresponding allocated data blocks to a corresponding memory region of the data storage device, and generating an independent identifier indicating completion of the atomic write for each of the IP cores. | 10-30-2014 |
20140325127 | STORAGE SYSTEM COMPRISING FLASH MEMORY MODULES SUBJECT TO TWO WEAR-LEVELING PROCESSES - A storage system using flash memories includes a storage controller and plural flash memory modules as storage media. Each flash memory module includes at least one flash memory chip and a memory controller for leveling erase counts of blocks belonging to the flash memory chip. The storage controller combines the plural flash memory modules into a first logical group, translates a first address used for accessing the flash memory modules belonging to the first logical group to a second address used for handling the first address in the storage controller, and combines the plural first logical groups into a second logical group. | 10-30-2014 |
20140325128 | Mirror Copies of Solid State Drives Using Portions of Hard Disk Drives - Mechanisms for storing data to a storage system comprising a set of one or more solid state storage devices and a set of non-solid state storage devices are provided. A request to write data to the storage system is received and the data is written to the set of one or more solid state storage devices in response to receiving the request. Moreover, a mirror copy of the data is written to the set of non-solid state storage devices in response to receiving the request. Thus, the non-solid state storage devices serve as a mirror backup copy of the data stored to the solid state storage devices. | 10-30-2014 |
20140325129 | METHOD AND APPARATUS FOR ACTIVE RANGE MAPPING FOR A NONVOLATILE MEMORY DEVICE - Methods and systems are provided that may include a nonvolatile memory to implement a virtual random access memory space. | 10-30-2014 |
20140325130 | STATUS INFORMATION SAVING AMONG MULTIPLE COMPUTERS - Provided are techniques for status information saving among multiple computers. In one embodiment, a selected computer is operated using a plurality of input/output devices over switched input/output signal paths passing through a KVM (keyboard video mouse) switch positioned between the selected computer and the plurality of input/output devices. Status data is carried over signal paths passing through the KVM switch wherein the status data represents status information for a plurality of computers connected to the KVM switch. The status data passing through the KVM switch is stored in a memory coupled to the KVM switch. Other embodiments are described and claimed. Other embodiments are contemplated, depending upon the particular application. | 10-30-2014 |
20140325131 | Controller and Method for Performing Background Operations - The embodiments described herein provide a controller and method for performing a background commands or operations. In one embodiment, a controller is provided with interfaces through which to communicate with a host and a plurality of flash memory devices. The controller contains a processor operative to perform a foreground command received from the host, wherein the processor performs the foreground command to completion without interruption. The processor is also operative to perform a background commands or operations stored in the controller's memory, wherein the processor performs the background command until completed or preempted by a foreground command. If the background command is preempted, the processor can resume performing the background command at a later time until completed. | 10-30-2014 |
20140325132 | METHOD AND APPARATUS FOR TRANSFERRING DATA BETWEEN A HOST AND BOTH A SOLID-STATE MEMORY AND A MAGNETIC STORAGE DEVICE - A hybrid circuit includes a system-in-a-package (SIP) and an integrated circuit. The SIP includes a solid-state memory, and a first control module. The first control module controls access to the solid-state memory based on a first control signal. The integrated circuit includes an embedded multi-media card (eMMC) module, a second control module, and a management module. The eMMC module is in communication with the SIP according to an eMMC standard. The first eMMC module transfers the first control signal to the first control module to access the solid-state memory. The second control module controls access to a magnetic storage device based on a second control signal. The management module generates the control signals to transfer first data between a host and the SIP via the eMMC module and transfer the first data or second data between the host and the magnetic storage device via the second control module. | 10-30-2014 |
20140325133 | AMOUNT OF MEMORY FOR EXECUTION OF AN APPLICATION - Examples disclose determining an amount of memory for execution of an application, associated with a user preference, based on an inspection of data associated with the application. Further the example discloses transmitting a request to a non-volatile memory to allocate a segment corresponding to the amount of memory for execution of the application. Additionally, the example also discloses receiving a response of the amount of memory available for the segment and reserving a portion of the segment for the execution of the application. | 10-30-2014 |
20140325134 | PREARRANGING DATA TO COMMIT TO NON-VOLATILE MEMORY - An apparatus includes a hybrid memory module, and the hybrid memory module includes volatile memory and non-volatile memory. Data is prearranged in the volatile memory. The data is committed to the non-volatile memory, as prearranged, in a single write operation when a size of the prearranged data reaches a threshold. | 10-30-2014 |
20140331001 | Command Barrier for a Solid State Drive Controller - Methods and systems may perform one or more operations for solid state device administrative command execution including, but not limited to: receiving, in at least one administrative command queue, at least one administrative command affecting at least one submission queue; halting enqueuing of one or more submission commands in the at least one submission queue in response to the receiving the at least one administrative command affecting the at least one submission queue; adding at least one barrier command to at least one submission queue affected by the at least one administrative command; processing one or more commands in the at least one submission queue until the at least one barrier command in the at least one submission queue is processed; and processing the at least one administrative command affecting the at least one submission queue in response to the processing of the at least one barrier command. | 11-06-2014 |
20140331002 | Systems and Methods for Internal Initialization of a Nonvolatile Memory - Methods and systems are provided that may include a memory device having a physical nonvolatile memory, a memory space, and a controller. At least a portion of a physical nonvolatile memory may permit a direct read operation of the physical nonvolatile memory and prohibit a direct write operation of the physical nonvolatile memory. A memory space may comprise at least open one write overlay window available after a reset operation. Such a memory space may be adapted to permit at least one read overlay window to be opened that is logically separate from at least one open write overlay window. A controller may be included to open at least one read overlay window. | 11-06-2014 |
20140331003 | FAULT-TOLERANT NON-VOLATILE INTEGRATED CIRCUIT MEMORY - Apparatus and methods are disclosed, such as those that store data in a plurality of non-volatile integrated circuit memory devices, such as NAND flash, with convolutional encoding. A relatively high code rate for the convolutional code consumes relatively little extra memory space. In one embodiment, the convolutional code is spread over portions of a plurality of memory devices, rather than being concentrated within a page of a particular memory device. In one embodiment, a code rate of m/n is used, and the convolutional code is stored across n memory devices. | 11-06-2014 |
20140331004 | Write Spike Performance Enhancement In Hybrid Storage Systems - In an embodiment, a hybrid storage array one uses two or more storage device tiers provided by solid state drives (SSDs) and hard disk drives (HDDs). Random writes are collected and written to a write cache extension, such as a portion of the SSD storage tier. The write cache extension absorbs such accesses that would otherwise be written to HDD storage directly. Data structures are created in a cache memory local to an array controller representing the location on the write cache extension to which the writes were committed and a location in the storage system where they were originally intended to go. The write cache extension can be enabled all of the time, or only when the array controller write cache experiences certain operating conditions, such as when its utilization exceeds a predetermined amount. The approach improves the overall performance of the hybrid array. | 11-06-2014 |
20140331005 | MEMORY SYSTEM AND BUS SWITCH - A memory system includes a nonvolatile memory having a plurality of nonvolatile memory chips incorporated therein, a control circuit that controls the nonvolatile memory, an MPU that controls the control circuit, and an interface circuit that communicates with a host, all of which are mounted on a board of the memory system, and the memory system further includes a bus switch that switches connection of a signal line between the control circuit and the nonvolatile memory chips. | 11-06-2014 |
20140337560 | System and Method for High Performance and Low Cost Flash Translation Layer - Aspects include systems and methods for increasing performance of a flash translation layer (FTL) of a flash memory device. A copy of FTL tables stored on a flash memory device may be copied to a memory of a host device. The copy of the FTL tables may be directly accessed by the flash memory device to translate between logical addresses provided by the host device for read/write operations from/to a flash memory of the flash memory device, and the respective physical addresses of the flash memory. The flash memory device is granted direct memory access to a portion of the memory of the host device where the copy of the FTL tables is stored. The flash memory device bus masters communication busses connecting the flash memory device to the memory of the host device. | 11-13-2014 |
20140337561 | Flash memory cache for data storage device - A storage device made up of multiple storage media is configured such that a flash memory serves as a cache for data stored on a backend storage device having one or more magnetic storage media. The storage device includes a controller configured to maintain a direct mapping from respective backend block addresses of the backend storage device to respective physical addresses of the flash memory. Such mapping is used to translate a backend block address of the backend storage device at which a first block is stored into a physical address of the flash memory at which the first block is cached. | 11-13-2014 |
20140337562 | JOURNAL MANAGEMENT - Apparatuses, systems, methods, and computer program products are disclosed for managing a journal. A method may include reordering storage commands based on different storage volumes associated with the storage commands. A method may include reordering storage commands based on different snapshots associated with the storage commands. A method may include adjusting a frequency of writing data from a write buffer based on a rate of write requests. A method may include adjusting a ratio of storage capacity for storing mirrored write data to storage capacity for storing non-mirrored read data. | 11-13-2014 |
20140337563 | METHOD AND APPARATUS FOR CONFIGURING WRITE PERFORMANCE FOR ELECTRICALLY WRITABLE MEMORY DEVICES - Methods and systems are provided that may include a nonvolatile memory to store information, where the nonvolatile memory is associated with a configuration register to indicate a write speed setting for at least one write operation to the nonvolatile memory. A circuit may supply current to achieve an indicated write speed setting for the at least one write operation to the nonvolatile memory. | 11-13-2014 |
20140337564 | APPARATUSES AND METHODS OF OPERATING FOR MEMORY ENDURANCE - Methods of operating an apparatus such as a computing system and/or memory device for memory endurance are provided. One example method can include receiving m digits of data having a first quantity of digits represented by a first data state that is more detrimental to memory cell wear than a second data state. The m digits of data are encoded into n digits of data having a second quantity of digits represented by the first data state. The value n is greater than the value m. The second quantity is less than or equal to the first quantity. The n digits of data are stored in an apparatus having memory cells. | 11-13-2014 |
20140337565 | STORAGE SUBSYSTEM INCLUDING LOGIC FOR COPY-OUT AND WRITE - A storage server receives a write request from a client system including new data and a location to store the new data. The storage server transmits a copy instruction to a storage subsystem to relocate old data at the location and transmits a write instruction to the storage subsystem to overwrite the old data with the new data. The storage subsystem includes fast stable storage in which the copy instruction and the write instruction are stored. After receiving each instruction, the storage subsystem sends an acknowledgement to the storage server. When both instructions have been acknowledged, the storage server sends an acknowledgement to the client system. The storage subsystem performs the instructions asynchronously from the client system's write request. | 11-13-2014 |
20140337566 | SOLID STATE MEMORY (SSM), COMPUTER SYSTEM INCLUDING AN SSM, AND METHOD OF OPERATING AN SSM - In one aspect, data is stored in a solid state memory which includes first and second memory layers. A first assessment is executed to determine whether received data is hot data or cold data. Received data which is assessed as hot data during the first assessment is stored in the first memory layer, and received data which is first assessed as cold data during the first assessment is stored in the second memory layer. Further, a second assessment is executed to determine whether the data stored in the first memory layer is hot data or cold data. Data which is then assessed as cold data during the second assessment is migrated from the first memory layer to the second memory layer. | 11-13-2014 |
20140337567 | STORAGE DEVICE INCLUDING FLASH MEMORY AND CAPABLE OF PREDICTING STORAGE DEVICE PERFORMANCE BASED ON PERFORMANCE PARAMETERS - A storage device includes a semiconductor memory storing data. A controller instructs to write data to the semiconductor memory in accordance with a request the controller receives. A register holds performance class information showing one performance class required to allow the storage device to demonstrate best performance which the storage device supports, of performance classes specified in accordance with performance. | 11-13-2014 |
20140344503 | METHODS AND APPARATUS FOR ATOMIC WRITE PROCESSING - Example implementations described herein are directed to implementation of the atomic write feature in the storage system setting. Example implementations may utilize flash memory to facilitate or to form atomic write commands to improve flash memory performance and endurance. Several protocols involving the cache unit of the storage system may include managing a status of the storage system so that data corresponding to an atomic write command are stored in a cache unit, with old data maintained in the storage system until the write data corresponding to an atomic write command is properly received. | 11-20-2014 |
20140344504 | HYPERVISOR-BASED FLASH CACHE SPACE MANAGEMENT IN A MULTI-VM ENVIRONMENT - Techniques for managing space in a flash storage-based cache are provided. In one embodiment, a computer system can calculate “ratio of effective cache space” (rECS) values for a plurality of VMs, where each VM has a cache allocation comprising a subset of a global pool of cache blocks in the flash storage-based cache, and where the rECS value for the VM indicates a proportion of the subset that has been populated with cached data and re-accessed by the VM within a current time window. The computer system can further determine a new cache allocation size for at least one VM in the plurality of VMs based on the rECS values. The computer system can then adjust the number of cache blocks in the at least one VM's cache allocation based on the new cache allocation size. | 11-20-2014 |
20140344505 | SEMICONDUCTOR DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor device includes a memory block including memory cells coupled to bit lines, read/write circuits each including cache latch suitable for temporarily storing data to be stored in the memory cells, wherein the read/write circuits are divided into a plurality of groups and perform a program operation to store the data in the memory cells coupled to the bit lines, and an initialization control unit suitable for initializing the cache latches of the read/write circuits of a group corresponding to the address before the data is input to the cache latches, when a program command and an address are input. | 11-20-2014 |
20140344506 | ELECTRONIC DEVICE WITH WRITING PROTECTION AND RELATED METHOD - An electronic device comprises a buffer, a processing module, and a storage. When the electronic device generates a writing instruction, the processing module executes a protection and writes data of the buffer into the storage. Based on the protection, the processing module fails to execute interrupt instructions while writing data into the storage. | 11-20-2014 |
20140344507 | SYSTEMS AND METHODS FOR STORAGE METADATA MANAGEMENT - A storage layer may be configured to over-provision logical storage resources to objects. The storage layer may provision the resources in response to, inter alia, a request to open and/or create a zero-length file. The storage layer may be further configured to store data of the objects in a contextual format configured to associate the data with respective logical identifiers. The storage layer may determine an actual, storage size of the object based on the associations stored on the stored associations. Storage clients may rely on the storage layer to determine the size of the object and, as such, may defer and/or eliminate updates to persistent metadata. | 11-20-2014 |
20140344508 | MANAGING MEMORY AND STORAGE SPACE FOR A DATA OPERATION - Processing a plurality of data units to generate result information, includes: performing a data operation for each data unit of a first subset of data units from the plurality of data units, and storing information associated with a result of the data operation in a first set of one or more data structures stored in working memory space of a memory device; after an overflow condition on the working memory space is satisfied, storing information in overflow storage space of a storage device; and repeating an overflow processing procedure multiple times during the processing of the plurality of data units, the overflow processing procedure including: updating a new set of one or more data structures stored in the working memory space using at least some information stored in the overflow storage space. | 11-20-2014 |
20140344509 | HARD DISK CACHING WITH AUTOMATED DISCOVERY OF CACHEABLE FILES - In some embodiments a permanent cache list of files not to be removed from a cache is determined in response to a user selection of an application to be added to the cache. The determination is made by adding a file to the cache list if the file is a static dependency of the application, or if a file has a high probability of being used in the future by the application. Other embodiments are described and claimed. | 11-20-2014 |
20140344510 | STORAGE SYSTEM - In an exemplary storage system, a processor assigns an unused process to a read request designating an area of a logical volume. The processor determines whether the data designated by the read request is in a cache memory, based on a first identifier for identifying the area designated by the read request. When the designated data is not in the cache memory and a part of physical volumes providing the logical volume is a first kind of physical volume, the processor stores the first identifier associated with an identifier for identifying an area allocated in the cache memory. When the designated data is not in the cache memory and a part of the physical volumes is a second kind of physical volume, the processor stores a second identifier for identifying the process assigned to the read request associated with an identifier for identifying an area allocated in the cache memory. | 11-20-2014 |
20140351485 | Differential File System for Computer Memory - An approach is described to overcome the rapid consumption of available flash space when frequently modifying files stored on the flash space. This “differential” sector approach determines the correlation between the new content and the old content, and saves only the “delta” part of the old and the new content to the sectorized memory device. A predetermined threshold can be used to determine whether to use the “differential” sector approach or the fixed sector approach, based on the amount of data change in a given memory access request. | 11-27-2014 |
20140351486 | VARIABLE REDUNDANCY IN A SOLID STATE DRIVE - An apparatus comprising a memory and a controller. The memory may be configured to process a plurality of read/write operations. The memory comprises a plurality of memory modules each having a size less than a total size of the memory. The controller is configured to provide a first redundancy scheme when user data occupies less than a preconfigured limit and a second redundancy scheme that protects less than all of the user data when the user data occupies greater than the preconfigured limit. | 11-27-2014 |
20140351487 | NONVOLATILE MEMORY AND RELATED REPROGRAMMING METHOD - A method of reprogramming a nonvolatile memory device, comprising setting up bit lines of selected memory cells according to logic values of first and second latches of a page buffer connected to the bit lines, supplying a program pulse to the selected memory cells, performing a program verify operation on the selected memory cells using the first and second latches, and performing a predictive program operation on the selected memory cells according to a result of the program verify operation. In the predictive program operation, bit lines of the selected memory cells are setup according to a logic value of a third latch of the page buffer that corresponds to each of the selected memory cells. | 11-27-2014 |
20140351488 | METHOD AND ELECTRONIC DEVICE FOR PROCESSING INFORMATION - The present disclosure provides a method and electronic device for processing information. The method is applied in a solid state storage apparatus which is connected to an electronic device. The solid state storage apparatus supports N logical-address-to-physical-address mapping tables different from each other simultaneously, wherein N is an integer greater than or equal to 1. The method comprises: receiving identity information for a user from the electronic device; determining a first logical-address-to-physical-address mapping table corresponding to the user based on the identity information; and assigning the first logical-address-to-physical-address mapping table to the user. | 11-27-2014 |
20140351489 | MECHANISM FOR WRITING INTO AN EEPROM ON AN I2C BUS - A method for writing data into an EEPROM connected to an I2C bus, wherein the data to be written is transmitted in frames having a size corresponding to the size of a physical half-page of the memory. The programming of a data page in the memory is performed while another page is being received. | 11-27-2014 |
20140351490 | METHOD FOR UPDATING INVERTED INDEX OF FLASH SSD - Disclosed is a method for updating an inverted index of a flash solid state disk (SSD). The method including: storing postings of a term that is present in only an in-memory inverted index in a block of an output buffer and reading postings of a last block of each posting list to be updated from an on-disk inverted index to be stored in each block of an input buffer, by scanning the on-disk inverted index and the in-memory inverted index; moving postings of the input buffer to the blocks of the output buffer for each block and attaching new postings of the in-memory inverted index to the block corresponding to the output buffer; and updating the on-disk inverted index by using the postings of each block of the output buffer. | 11-27-2014 |
20140351491 | MAPPING BETWEEN PROGRAM STATES AND DATA PATTERNS - The present disclosure includes methods and apparatuses for mapping between program states and data patterns. One method includes: programming a group of G memory cells such that a combination of respective program states of the group maps to a constellation point corresponding to a received N unit data pattern, the group used to store N/G units of data per memory cell; wherein the constellation point is one of a number of constellation points of a constellation associated with mapping respective program state combinations of the group of memory cells to N unit data patterns; and wherein the constellation comprises a first mapping shell and a second mapping shell, the constellation points corresponding to the respective first and second mapping shells determined, at least partially, based on a polynomial expression of order equal to G. | 11-27-2014 |
20140351492 | SYSTEM AND METHOD FOR NON-VOLATILE RANDOM ACCESS MEMORY EMULATION - Described herein is a system and method for high speed non-volatile random access memory (NVRAM) emulation. The system and method may utilize a primary storage device and a volatile random access memory (RAM) device to emulate NVRAM functionality. The system and method may allocate a range of the primary storage device. The storage capacity or size of the allocated range may correspond or be at least partially based on a storage capacity or size of the volatile RAM device. Data, such as write requests, may be migrated from the primary storage device to the volatile RAM device. In the event of the unavailability, loss of power, or other such circumstances of the volatile RAM device, data from the volatile RAM device may be migrated back to the previously allocated range of the primary storage device. | 11-27-2014 |
20140351493 | WEAR LEVELING FOR ERASABLE MEMORIES - In accordance with some embodiments, wear leveling may be done based on the difference in age of discarded blocks and engaged blocks. Data is moved to an older discarded block from a younger engaged block. Two wear leveling bits may be used for each logical block, such that the wear leveling bits are used in alternating cycles. | 11-27-2014 |
20140351494 | Writing Data in a Non-Volatile Memory of a Smart Card - The invention relates in particular to a method for writing data in a non-volatile memory of a smart card. The invention also relates to a smart card and a computer program capable of implementing such a method, to a storage medium including such a computer program, and to a system including a smart card and a device making it possible to write in the card. | 11-27-2014 |
20140351495 | LOCAL CHECKPOINTING USING A MULTI-LEVEL CELL - Local checkpointing using a multi-level call is described herein. An example method includes storing a first datum in a first level of a multi-level cell. A second datum is stored in a second level of the multi-level cell, the second datum representing a checkpoint of the first datum. The first datum is copied from the first level to the second level of the multi-level cell to create the checkpoint. | 11-27-2014 |
20140351496 | Optimized Configurable NAND Parameters - Configurable parameters may be used to access NAND flash memory according to schemes that optimize such parameters according to predicted characteristics of memory cells, for example, as a function of certain memory cell device geometry, which may be predicted based on the location of a particular device within a memory array. | 11-27-2014 |
20140351497 | MEMORY SYSTEM AND CONTROL METHOD THEREOF - A memory system includes a nonvolatile memory including a plurality of blocks as data erase units, a measuring unit which measures an erase time at which data of each block is erased, and a block controller which writes data supplied from at least an exterior into a first block which is set in a free state and whose erase time is oldest. | 11-27-2014 |
20140351498 | SYSTEMS AND METHODS FOR READ CACHING IN FLASH STORAGE - A flash controller receives a read request for reading a page of data from the flash memory from a host system, and identifies, in a cache tag table stored in the random access memory, a virtual unit address associated with the page of data. In response to identifying the virtual unit address in the cache tag table, controller determines whether a valid tag line for the page of data is associated with the virtual unit address in the cache tag table. In response to determining that the valid tag line is associated with the virtual unit address in the cache tag table, the controller reads the page of data from the random access memory in accordance with the read request and returns the read data to the host system. | 11-27-2014 |
20140351499 | MEMORY DEVICE, HOST DEVICE, AND SAMPLING CLOCK ADJUSTING METHOD - A memory card includes a memory controller configured to perform control for sending and receiving a command signal, a response signal, a data signal, and a status signal in synchronization with a clock signal, and a memory-side pattern signal storage unit configured to store a tuning pattern signal to be sent to a host device. The tuning pattern signal is used by the host device to adjust the phase of the clock signal for use as a sampling clock signal. The memory card sends a first tuning pattern signal through a command line and a second tuning pattern signal through a data line concurrently. | 11-27-2014 |
20140351500 | HYBRID VOLATILE AND NON-VOLATILE MEMORY DEVICE - Non-transitory computer-readable media having information embodied therein that includes a description of an integrated circuit device. The information includes descriptions of a volatile storage die having a first addressable range of storage cells and a non-volatile storage die. The description of the non-volatile storage die having a second addressable range of storage cells that defines an overlapping region with the first addressable range of storage cells. The information also includes a description of an interface circuit coupled to the volatile and non-volatile storage die to selectively transfer data stored in the overlapping region of storage cells between the die. | 11-27-2014 |
20140359197 | IMPLEMENTING REINFORCEMENT LEARNING BASED FLASH CONTROL - A method and system are provided for implementing enhanced flash storage control using reinforcement learning to provide enhanced performance metrics. A flash controller, such as a Reinforcement Learning (RL) flash controller, is coupled to a flash storage. The flash controller defines a feature set of flash parameters determined by a predefined one of a plurality of optimization metrics. The optimization metric is adapted dynamically based upon system workload and system state. The flash controller employing the feature set including at least one feature responsive to erase operations; computes a current system state responsive to the employed feature set; selects actions at each time step by sensing the computed current system state for performing an action to maximize a long term reward, and moves to another state in the system while obtaining a short-term reward for the performed action. | 12-04-2014 |
20140359198 | NOTIFICATION OF STORAGE DEVICE PERFORMANCE TO HOST - A method includes, in a storage device that stores data for a host in a memory, estimating an impact of an amount of free memory space in the memory on a storage performance of the storage device. The storage device sends to the host a notification that is indicative of the estimated impact. | 12-04-2014 |
20140359199 | MULTI-PROCESSOR COMPUTER ARCHITECTURE INCORPORATING DISTRIBUTED MULTI-PORTED COMMON MEMORY MODULES - A multi-processor computer architecture incorporating distributed multi-ported common memory modules wherein each of the memory modules comprises a control block functioning as a cross-bar router in conjunction with one or more associated memory banks or other data storage devices. Each memory module has multiple I/O ports and the ability to relay requests to other memory modules if the desired memory location is not found on the first module. A computer system in accordance with the invention may comprise memory module cards along with processor cards interconnected using a baseboard or backplane having a toroidal interconnect architecture between the cards. | 12-04-2014 |
20140359200 | High Performance System Topology for NAND Memory Systems - A topology for memory circuits of a non-volatile memory system reduces capacitive loading. For a given channel, a single memory chip can be connected to the controller, but is in turn connected to multiple other memory devices that fan out in a tree-like structure, which can also fan back in to a single memory device. In addition to the usual circuitry, such as a memory arrays and associated peripheral circuitry, the memory chip also includes a flip-flop circuit and can function in several modes. The modes include a pass-through mode, where the main portions of the memory circuit are inactive and commands and data are passed through to other devices in the tree structure, and an active mode, where the main portions of the memory circuit are active and can receive and supply data. Reverse active and reverse pass-through modes, where data flows in the other direction, can also be used. The pads of the memory chip can be configurable to swap input and output pads to more efficiently form the memory chips into a package. | 12-04-2014 |
20140359201 | PERSISTENT MEMORY GARBAGE COLLECTION - A technique includes identifying a dependency between a first persistent memory region and at least one other persistent memory region. The technique includes using a process having access to the first persistent memory region to selectively perform garbage collection for the first persistent memory region based at least in part on whether the process has access to the other persistent memory region(s) from which the first persistent memory region depends. | 12-04-2014 |
20140359202 | READING VOLTAGE CALCULATION IN SOLID-STATE STORAGE DEVICES - An error management system for a data storage device includes adjusted reading voltage level calculation functionality. Adjusted reading voltage level calculation may be based on the generation and use of an index in which data retention characteristics of a drive are used to look-up corresponding reading voltage levels. In certain embodiments, reading voltage level calculation is based at least in part on curve-fitting procedures/algorithms, wherein curves are fitted to bit error rate data points or cumulative memory cell distributions and are solved according to one or more algorithms to determine optimal reading voltage levels. | 12-04-2014 |
20140359203 | STORAGE SYSTEMS AND ALIASED MEMORY - Aspects of the subject matter described herein relate to storage systems and aliased memory. In aspects, a file system driver or other component may send a request to a memory controller to create an alias between two blocks of memory. One of the blocks of memory may be used for main memory while the other of the blocks of memory may be used for a storage system. In response, the memory controller may create an alias between the blocks of memory. Until the alias is severed, when the memory controller receives a request for data from the block in main memory, the memory controller may respond with data from the memory block used for the storage system. The memory controller may also implement other actions as described herein. | 12-04-2014 |
20140359204 | NON-VOLATILE MEMORY DEVICE AND METHOD FOR OPERATING THE SAME, AND SYSTEM INCLUDING THE SAME - Disclosed are a non-volatile memory device capable of performing memory operations in parallel and a method for operating the non-volatile memory device, and a system including the non-volatile memory device. A non-volatile memory system may include a memory controller suitable for controlling a memory; and the memory suitable for performing read and program operations in response to commands from the memory controller, and wherein the memory controller and the memory operate in a high interface mode, and operate in a low interface mode when an operation to read internal data or an operation to receive (N+1)th data is performed during an operation to program Nth data in the memory. | 12-04-2014 |
20140359205 | MOUNTING METHOD IN AN ELECTRONIC APPARATUS - An MTD number identifying unit | 12-04-2014 |
20140359206 | HEALTH REPORTING FROM NON-VOLATILE BLOCK STORAGE DEVICE TO PROCESSING DEVICE - Methods and devices are provided for adapting an I/O pattern, with respect to a processing device using a non-volatile block storage device based on feedback from the non-volatile block storage device. The feedback may include information indicating a status of the non-volatile block storage device. In response to receiving the feedback, a storage subsystem, included in an operating system executing on processing device, may change a behavior with respect to the non-volatile block storage device in order to avoid, or reduce, a negative impact to the non-volatile block storage device or to enhance an aspect of the non-volatile block storage device. The feedback may include performance information and/or operating environmental information of the non-volatile block storage device. When the non-volatile block storage device is not capable of providing the feedback, the processing device may request information about the non-volatile block storage device from a database service. | 12-04-2014 |
20140365709 | Electronic computer program product and an electronic computer system for producing a location report - A method, an electronic computer program product, and an electronic computer system for producing a location report, utilizing look-up tables, the report comprising precautionary statements, emergency metadata, critical operational metadata, executable instructions, National Fire Protection Association ratings, and combinations thereof. | 12-11-2014 |
20140365710 | DATA STORAGE APPARATUS AND MANAGEMENT METHOD THEREOF - A data storage apparatus has a transmission interface, a nonvolatile memory and a controller. The controller records a non-completed flag. When the controller starts a card opening process, the nonvolatile memory is configured under card opening, and the non-completed flag is set non-completed status. When the controller receives a format command form the transmission interface, the nonvolatile memory is formatted and the non-completed flag is set as completed status. When the controller receives a write command, the write data are scrambled before being written to the nonvolatile memory. When in non-completed status, when the controller receives a read command from the transmission interface, no matter whether the data corresponding to the requested address are scrambled, the data are descrambled and descrambled are provided via the transmission interface. | 12-11-2014 |
20140365711 | MEMORY SYSTEM - According to one embodiment, a memory system includes a nonvolatile memory, a storage unit, and a comparison unit. The nonvolatile memory stores an address translation table recording a first address and a second address corresponding to the first address and a write data. The storage unit stores a list and the address translation table. The list stores a third address. The address translation table is loaded from the nonvolatile memory in response to an access request to the nonvolatile memory. The address translation table includes the first address as a target of the access request. The comparison unit compares the third address stored in the list and the second address recorded in the address translation table and outputs a comparison result. | 12-11-2014 |
20140365712 | MEMORY SYSTEM - The present invention provides a memory system which contributes to improvement in efficiency of a data process accompanying a memory access. A memory system has a rewritable nonvolatile memory, a buffer memory, and a controller. The controller controls, in response to an access request from an external apparatus, first data transfer between the controller and the external apparatus, second data transfer between the controller and the nonvolatile memory, and third data transfer between the controller and the buffer memory, controls transfer from the controller to the buffer memory in the third data transfer and transfer from the buffer memory to the controller in a time sharing manner, and enables the first data transfer or the second data transfer to be performed in parallel with the transfer carried out in the time sharing manner. | 12-11-2014 |
20140365713 | ELECTRONIC SYSTEM AND OPERATING METHOD THEREOF - An electronic system and an operating method thereof are provided. When a computer host is booting up and an external storage device is connected with the computer host, the BIOS of the computer host may read the parameter information recorded in a memory of a bridge unit via a bridge unit of the external device and displays the parameter information without initializing the storage unit and reading the parameter information from a magnetic region of the storage unit. | 12-11-2014 |
20140365714 | PERIPHERAL COMPONENT INTERCONNECT EXPRESS (PCIe) SOLID STATE DRIVE (SSD) ACCELERATOR - A peripheral component interconnect express (PCIe) solid state drive (SSD) accelerator, having a PCIe card and separate a flash daughter-card, is provided. By including flash memory devices on a separate daughter-card, the flash memory devices are thermally decoupled from the hotter devices on the main PCIe providing additional thermal operating margins for the entire design. Furthermore, as flash memory devices are the most likely part of the subsystem to wear out over time due, including flash memory devices on a separate daughter-card allows the flash memory devices to become a field replaceable unit that can be easily replaced. EEPROMs may be included on the flash daughter-card to record the current wear state of the NAND flash devices. Knowing the wear history of the flash memory device allows the seller to replace the flash daughter-card of a customer with a daughter-card having a similar wear state. | 12-11-2014 |
20140365715 | NON-VOLATILE MEMORY STORAGE FOR MULTI-CHANNEL MEMORY SYSTEM - A memory system that has a multi-channel volatile memory subsystem is coupled to a non-volatile memory subsystem to provide independent, configurable backup of data. The volatile memory subsystem has one or more main memory modules that use a form of volatile memory such as DRAM memory, for which the NV subsystem provides selective persistent backup. The main memory modules are dual in-line memory modules or DIMMs using DDR SDRAM memory devices. The non-volatile memory subsystem (NV backup) includes an NV controller and non-volatile memory NVM. The NV backup can also include a memory cache to aid with handling and storage of data. In certain embodiments, the NV controller and the non-volatile memory are coupled to the one or more DIMM channels of the main memory via associated signal lines. Such signal lines can be, for example, traces on a motherboard, and may include one or more signal buses for conveying data, address, and/or control signals. The NV controller and the non-volatile memory can be mounted on the motherboard. | 12-11-2014 |
20140365716 | INTERFACE BETWEEN MULTIPLE CONTROLLERS - A second controller is communicated with from a first controller via an interface. Storage is also communicated with from the first controller via the interface. The first controller is configured to be a master on the interface and the second controller and the storage are configured to be targets on the interface. | 12-11-2014 |
20140365717 | INTRA-DEVICE DATA PROTECTION IN A RAID ARRAY - A system and method for intra-device data protection in a RAID array. A computer system comprises client computers and data storage arrays coupled to one another via a network. A data storage array utilizes solid-state drives and Flash memory cells for data storage. A storage controller within a data storage array is configured to identify a unit of data stored in the data storage subsystem, wherein said unit of data is stored across at least a first storage device and a second storage device of the plurality of storage devices, each of the first storage device and the second storage device storing intra-device redundancy data corresponding to the unit of data; and change an amount of intra-device redundancy data corresponding to the unit of data on only the first storage device. | 12-11-2014 |
20140365718 | DEMOTING TRACKS FROM A FIRST CACHE TO A SECOND CACHE BY USING A STRIDE NUMBER ORDERING OF STRIDES IN THE SECOND CACHE TO CONSOLIDATE STRIDES IN THE SECOND CACHE - Information on strides configured in the second cache includes information indicating a number of valid tracks in the strides, wherein a stride has at least one of valid tracks and free tracks not including valid data. A determination is made of tracks to demote from the first cache. A first stride is formed including the determined tracks to demote. The tracks from the first stride are added to a second stride in the second cache that has no valid tracks. A target stride in the second cache is selected based on a stride most recently used to consolidate strides from at least two strides into one stride. Data from the valid tracks is copied from at least two source strides in the second cache to the target stride. | 12-11-2014 |
20140365719 | MEMORY CONTROLLER THAT PROVIDES ADDRESSES TO HOST FOR MEMORY LOCATION MATCHING STATE TRACKED BY MEMORY CONTROLLER - This disclosure provides for host-controller cooperation in managing NAND flash memory. The controller maintains information for each erase unit which tracks memory usage. This information assists the host in making decisions about specific operations, for example, initiating garbage collection, space reclamation, wear leveling or other operations. For example, metadata can be provided to the host identifying whether each page of an erase unit has been released, and the host can specifically then command each of consolidation and erase using direct addressing. By redefining host-controller responsibilities in this manner, much of the overhead association with FTL functions can be substantially removed from the memory controller, with the host directly specifying physical addresses. This reduces performance unpredictability and overhead, thereby facilitating integration of solid state drives (SSDs) with other forms of storage. The disclosed techniques are especially useful for direct-attached and/or network-attached storage. | 12-11-2014 |
20140365720 | TRANSLATION LAYER IN A SOLID STATE STORAGE DEVICE - Solid state storage devices and methods for flash translation layers are disclosed. In one such translation layer, a sector indication is translated to a memory location by a parallel unit look-up table is populated by memory device enumeration at initialization. Each table entry is comprised of communication channel, chip enable, logical unit, and plane for each operating memory device found. When the sector indication is received, a modulo function operates on entries of the look-up table in order to determine the memory location associated with the sector indication. | 12-11-2014 |
20140365721 | DATA TRANSFER IN MEMORY CARD SYSTEM - A memory card system includes a host that issues a read command and a memory card that upon receiving the read command sends read data to the host in synchronism with a read clock signal generated within the memory card. In addition, the memory card sends the read clock signal to the host, and the host receives the read data in synchronism with the read clock signal, for increasing the allowable setup time period at the host. | 12-11-2014 |
20140365722 | Solid-State Disk Caching the Top-K Hard-Disk Blocks Selected as a Function of Access Frequency and a Logarithmic System Time - A solid state disk (SSD) caches disk-based volumes in a heterogeneous storage system, improving the overall storage-system performance. The hottest data blocks are identified based on two factors: the frequency of access, and temporal locality. Temporal locality is computed using a logarithmic system time. IO latency is reduced by migrating these hottest data blocks from hard-disk-based volumes to the solid-state flash-memory disks. Some dedicated mapping metadata and a novel top-K B-tree structure are used to index the blocks. Data blocks are ranked by awarding a higher current value for recent accesses, but also by the frequency of accesses. A non-trivial value for accesses in the past is retained by accumulating the two factors over many time spans expressed as a logarithmic system time. Having two factors, access frequency and the logarithmic system time, provides for a more balanced caching system. | 12-11-2014 |
20140372665 | NON-VOLATILE MEMORY OPERATIONS - An apparatus includes an interface module, a controller, a key storage module, where the key storage module is configured to store a key, and a non-volatile storage module that is configured to store data. The non-volatile storage module has a first partition and a second partition, where the first partition is designated as a read-only storage area for the data and the second partition is designated as a write-only storage area for new data. The first partition is re-designated as the write-only storage area for other new data and the second partition is re-designated as the read-only storage area for the new data in response to the new data being written to the second partition with a signature and the controller verifying the signature using the key stored in the key storage module. | 12-18-2014 |
20140372666 | SEMICONDUCTOR DEVICE WITH CONFIGURABLE SUPPORT FOR MULTIPLE COMMAND SPECIFICATIONS, AND METHOD REGARDING THE SAME - A device includes a NAND flash memory, and a generic command interface configured to interpret both an Open NAND Flash Interface specification and a first NAND flash specification to perform an associated one of command operations on the NAND flash memory, the Open NAND Flash Interface specification and the first NAND flash specification being different from each other. | 12-18-2014 |
20140372667 | DATA WRITING METHOD, MEMORY CONTROLLER AND MEMORY STORAGE APPARATUS - A data writing method for a rewritable non-volatile memory module is provided. The method includes receiving a write command and data corresponding to the write command from a host system and temporarily storing the data into a buffer memory, and the data includes a plurality of sub-data streams. The method still includes transmitting the sub-data streams into the rewritable non-volatile memory module, thereby writing the sub-data streams into at least one physical erasing unit of the rewritable non-volatile memory module. The method further includes generating parity information based on at least portion of the sub-data streams; storing the parity information into the buffer memory and deleting the data from the buffer memory. Accordingly, the method can effectively utilize the storage space of the buffer memory. | 12-18-2014 |
20140372668 | DATA WRITING METHOD, MEMORY CONTROLLER AND MEMORY STORAGE APPARATUS - A data writing method for a rewritable non-volatile memory module is provided. The method includes selecting at least one physical erasing unit as a global random area and building a global random area searching table for recording update information corresponding to updated logical pages that data stored in the global random area belongs to. The method also includes receiving updated data belonging to a logical page; and determining whether a data dispersedness degree corresponding to the global random area is smaller than a data dispersedness degree threshold. The method further includes, if the data dispersedness degree corresponding to the global random area is smaller than the data dispersedness degree threshold, writing the update data into the global random area and recording update information corresponding to the logical page in the global random area searching table. | 12-18-2014 |
20140372669 | MEMORY CONTROL SYSTEM AND MEMORY INTERFACE METHOD USING THE SAME - A memory control system includes: a memory that stores data; a memory controller that controls operation of the memory by a memory control signal; and a CPU that forms a single link with the memory controller and transmits the memory control signal to the memory controller via the single link. | 12-18-2014 |
20140372670 | NAND Flash memory interface controller with GNSS receiver firmware booting capability - An architecture of a NAND Flash memory module interface controller (NAND-controller) provides access to data stored in an external NAND Flash memory module, and a method of booting firmware. NAND-controller automatically boots firmware from the NAND Flash memory into primary RAM of a system-on-a chip used for GNSS receivers. NAND-controller has a first external interface to connect NAND Flash memory, a second external interface to set parameters of booting firmware, and two internal interfaces: a high-speed one (system interface) and a low-speed one (control interface) to be connected to two types of SoC internal busses. Data exchange between the CPU and NAND Flash memory is implemented using a static RAM buffer which is a part of the NAND-controller and available for reading and writing via high-speed interface. Parameters of the first external interface are set and current state of data exchange process is controlled by the CPU. | 12-18-2014 |
20140372671 | AUTHENTICATION DEVICE, AUTHENTICATION METHOD, AND COMPUTER PROGRAM PRODUCT - According to an embodiment, an authentication device includes an acquiring unit, a predicting unit, and an authenticating unit. The acquiring unit is configured to acquire performance information of a first device that is a device to be authenticated. The predicting unit is configured to predict performance information of a second device that is a device being a reference for authentication according to a change with time from initial performance information. The authenticating unit is configured to perform an authentication process of determining whether or not the first device falls into the second device on a basis of a degree of agreement between the performance information acquired by the acquiring unit and the performance information predicted by the predicting unit. | 12-18-2014 |
20140372672 | SYSTEM AND METHOD FOR PROVIDING IMPROVED SYSTEM PERFORMANCE BY MOVING PINNED DATA TO OPEN NAND FLASH INTERFACE WORKING GROUP MODULES WHILE THE SYSTEM IS IN A RUNNING STATE - Aspects of the disclosure pertain to a system and method for providing improved system performance by moving pinned data to ONFI module(s) while the system is in a running state. Further, when a virtual array of the system is offline, the system allows for scheduling and performance of background operations on virtual arrays which are still online. These characteristics promote the ability of the online virtual arrays to operate efficiently in the presence of the pinned data. | 12-18-2014 |
20140372673 | INFORMATION PROCESSING APPARATUS, CONTROL CIRCUIT, AND CONTROL METHOD - An information processing apparatus includes a storage device that includes a plurality of storage areas, and a processor coupled to the storage device. The processor executes a process including: first counting, among blocks each including a plurality of storage areas included in the storage device, number of transfer candidate blocks including the storage areas in which written data is invalidated; second counting, among the blocks, number of reserve blocks in which no data is written in the respective storage areas; determining whether transfer processing is to be started, in accordance with a result of comparing a count value of the first counting with a count value of the second counting; and transferring only valid data written in the respective storage areas of the transfer candidate block to the reserve block when it is determined that the transfer processing is to be started. | 12-18-2014 |
20140372674 | MEMORY CONTROLLER, OPERATING METHOD, AND MEMORY SYSTEM INCLUDING SAME - A method of operating a memory controller includes determining an access property for a target address region and controlling a threshold voltage distribution of memory cells included in the target address region according to the determined access property. | 12-18-2014 |
20140372675 | INFORMATION PROCESSING APPARATUS, CONTROL CIRCUIT, AND CONTROL METHOD - An information processing apparatus includes a storage device that includes a plurality of storage areas, and a processor coupled to the storage device. The processor executes a process comprising: selecting a logical address identifying data stored in the storage device; acquiring a physical address associated with the selected logical address, from a conversion table storing therein the logical addresses and physical addresses identifying the storage areas in which the data is stored in association with each other; determining whether the stored data indicated by the acquired physical address is to be transferred; transferring the stored data to another storage area when it is determined that the data is to be transferred; and updating the physical address associated with the selected logical address in the conversion table to the physical address indicating the other storage area. | 12-18-2014 |
20140372676 | ELECTRONIC DEVICE AND METHOD FOR MOUNTING FILE SYSTEM USING VIRTUAL BLOCK DEVICE - A method is provided including: generating a virtual block device including a file allocation table area located in an internal storage of an electronic device, and a cluster heap area located in a memory card that is inserted in the electronic device; and mounting a file system of the memory card using the generated virtual block device. | 12-18-2014 |
20140372677 | Wearable Device Assembly with Ability to Mitigate Data Loss Due to Component Failure - A wrist-worn device monitors movements of a user with a flexible circuit member. The flexible circuit member is fault tolerant. It may contain extra and/or redundant traces as well as the ability to store data on RAM if the flash memory fails or if some or all trace connections between the processor and flash memory fail. Data stored on the RAM may or may not contain less fidelity. Lower fidelity data may be used to alleviate issues arising if the RAM has less storage capacity than the flash memory. | 12-18-2014 |
20140372678 | USER DEVICE INCLUDING A NONVOLATILE MEMORY DEVICE AND A DATA WRITE METHOD THEREOF - An access method of a nonvolatile memory device included in a user device includes receiving a write request to write data into the nonvolatile memory device; detecting an application issuing the write request, a user context, a queue size of a write buffer, an attribute of the write-requested data, or an operation mode of the user device; and deciding one of a plurality of write modes to use for writing the write-requested data into the nonvolatile memory device according to the detected information. The write modes have different program voltages and verify voltage sets. | 12-18-2014 |
20140372679 | SYSTEMS AND METHODS FOR IDENTIFYING STORAGE RESOURCES THAT ARE NOT IN USE - An apparatus, system, and method are disclosed for managing a non-volatile storage medium. A storage controller receives a message that identifies data that no longer needs to be retained on the non-volatile storage medium. The data may be identified using a logical identifier. The message may comprise a hint, directive, or other indication that the data has been erased and/or deleted. In response to the message, the storage controller records an indication that the contents of a physical storage location and/or physical address associated with the logical identifier do not need to be preserved on the non-volatile storage medium. | 12-18-2014 |
20140372680 | EMBEDDED STORAGE AND EMBEDDED STORAGE SYSTEM - Provided are an embedded storage and an embedded storage system. The embedded storage includes a flash memory control unit, a host interface unit, and at least one off-chip flash memory interface unit. The embedded storage system includes the embedded memory and at least one expanded flash memory. The expanded flash memory performs data interaction with the flash memory control unit through the off-chip flash memory interface unit. The embedded storage and the embedded storage system can solve that because an embedded memory does not have an off-chip flash memory interface for connection to an off-chip flash memory, resulting in poor expandability for storage capacity of the embedded memory. A storage cost may further be lowered through a combination of various types of NAND flash memories. | 12-18-2014 |
20140372681 | APPARATUS AND METHOD FOR INDICATING FLASH MEMORY LIFE - The present invention relates to an apparatus and method for indicating flash memory life. While data is being stored in a flash memory, the number of writes in a plurality of blocks of the flash memory increases. The amount of flash memory life is calculated on the basis of the number of write times in the plurality of blocks. The calculated amount of life can be transmitted to a host. In addition, when the calculated amount of life is greater than a threshold value, a signal providing notice that the life of the flash memory has reached a dangerous level can be output. | 12-18-2014 |
20140372682 | NONVOLATILE MEMORY BANK GROUPS - A nonvolatile memory ( | 12-18-2014 |
20140372683 | FAST BLOCK DEVICE AND METHODOLOGY - A method, device and system directed to fast data storage on a block storage device. New data is written to an empty write block. A location of the new data is tracked. Meta data associated with the new data is written. A lookup table may be updated based in part on the meta data. The new data may be read based the lookup table configured to map a logical address to a physical address. | 12-18-2014 |
20140372684 | Enabling Throttling on Average Write Throughput for Solid State Storage Devices - A mechanism is provided for enabling throttling on average write throughput instead of peak write throughput for solid-state storage devices. The mechanism assures an average write throughput within a range but allows excursions of high throughput with periods of low throughput offsetting against those of heavy usage. The mechanism periodically determines average throughput and determines whether average throughput exceeds a high throughput threshold for a certain amount of time without being offset by periods of low throughput. | 12-18-2014 |
20140372685 | MEMORY SYSTEM, DATA STORAGE DEVICE, USER DEVICE AND DATA MANAGEMENT METHOD THEREOF - A data management method of a data storage device having a data management unit different from a data management unit of a user device receives information regarding a storage area of a file to be deleted, from the user device, selects a storage area which matches with the data management unit of the data storage device, from among the storage area of the deleted file, and performs an erasing operation on the selected storage area which matches with the data management unit. | 12-18-2014 |
20140372686 | METHODS AND SYSTEMS FOR MARKING DATA IN A FLASH-BASED CACHE AS INVALID - A storage device includes a flash memory-based cache for a hard disk-based storage device and a controller that is configured to limit the rate of cache updates through a variety of mechanisms, including determinations that the data is not likely to be read back from the storage device within a time period that justifies its storage in the cache, compressing data prior to its storage in the cache, precluding storage of sequentially-accessed data in the cache, and/or throttling storage of data to the cache within predetermined write periods and/or according to user instruction. | 12-18-2014 |
20140372687 | MAPPING DATA TO NON-VOLATILE MEMORY - An apparatus includes, in at least one aspect, a memory interface configured to connect with a plurality of multi-level memory cells and a circuitry coupled with the memory interface. The plurality of multi-level memory cells include a first page and a second page. The first page is associated with bits of a first significance. The second page is associated with bits of a second significance. The circuitry is configured to map a first portion of an encoded data sector to the first page and map a second portion of the encoded data sector to the second page. The first portion excludes the second portion and the second portion excludes the first portion such that each of the first page and the second page contains different data from the encoded data sector. | 12-18-2014 |
20140372688 | MEMORY SYSTEM - A memory system includes a management-information restoring unit. The management-information restoring unit determines whether a short break has occurred referring to a pre-log or a post-log in a NAND memory. The management-information restoring unit determines that a short break has occurred when the pre-log or the post-log is present in the NAND memory. In that case, the management-information restoring unit determines timing of occurrence of the short break, and, after selecting a pre-log or a post-log used for restoration, performs restoration of the management information reflecting these logs on a snapshot. Thereafter, the management-information restoring unit applies recovery processing to all write-once blocks in the NAND memory, takes the snapshot again, and opens the snapshot and the logs in the past. | 12-18-2014 |
20140372689 | LOGICAL SECTOR MAPPING IN A FLASH STORAGE ARRAY - A system and method for efficiently performing user storage virtualization for data stored in a storage system including a plurality of solid-state storage devices. A data storage subsystem supports multiple mapping tables. Records within a mapping table are arranged in multiple levels. Each level stores pairs of a key value and a pointer value. The levels are sorted by time. New records are inserted in a created newest (youngest) level. No edits are performed in-place. All levels other than the youngest may be read only. The system may further include an overlay table which identifies those keys within the mapping table that are invalid. | 12-18-2014 |
20140379957 | Firmware Storage and Maintenance - A mechanism is provided for improved firmware storage and maintenance. For each master device in a plurality of master devices: an amount of flash memory space required by the master device is identified and the amount of Flash memory space from a Flash component is allocated to the master device as a virtual Flash memory allocation. An initial sector location of the virtual Flash memory allocation in a data structure is recorded as an offset into the Flash component and a length of the virtual Flash memory allocation and device information is also recorded in the data structure. Data that allows the master device to boot up is then loaded into the virtual Flash memory allocation. | 12-25-2014 |
20140379958 | Firmware Storage and Maintenance - A mechanism is provided for improved firmware storage and maintenance. For each master device in a plurality of master devices: an amount of Flash memory space required by the master device is identified and the amount of Flash memory space from a Flash component is allocated to the master device as a virtual Flash memory allocation. An initial sector location of the virtual Flash memory allocation in a data structure is recorded as an offset into the Flash component and a length of the virtual Flash memory allocation and device information is also recorded in the data structure. Data that allows the master device to boot up is then loaded into the virtual Flash memory allocation. | 12-25-2014 |
20140379959 | MAP RECYCLING ACCELERATION - An apparatus having a processor and a circuit is disclosed. The processor is generally configured to initiate an operation to recycle a plurality of source blocks in a memory that is nonvolatile. The circuit is generally configured to (i) search through a first of a plurality of levels in a map that defines a plurality of translations between a plurality of logical addresses used at an interface to a computer and a plurality of physical addresses used in the memory and (ii) notify the processor in response to a detection in the first level of one or more of the source blocks to be recycled that contain valid data. | 12-25-2014 |
20140379960 | BACKGROUND REORDERING - A PREVENTIVE WEAR-OUT CONTROL MECHANISM WITH LIMITED OVERHEAD - Embodiments of the present disclosure describe background reordering techniques and configurations to prevent wear-out of an integrated circuit device such as a memory device. In one embodiment, a method includes receiving information about one or more incoming access transactions to a memory device from a processor, determining that a wear-leveling operation is to be performed based on a cumulative number of access transactions to the memory device, the cumulative number of access transactions including the one or more incoming access transactions, and performing the wear-leveling operation by mapping a first physical address of the memory device to a second physical address of the memory device based on a pseudo-random mapping function, and copying information from the first physical address to the second physical address. Other embodiments may be described and/or claimed. | 12-25-2014 |
20140379961 | DATA ENCODING FOR NON-VOLATILE MEMORY - A data storage device includes a memory and a controller. Mapping circuitry is configured to apply a mapping to received data to generate mapped data to be stored into the memory. The mapping is configured to reduce an average number of state changes of storage elements per write operation and is independent of the states of the storage elements prior to the writing of the mapped data. | 12-25-2014 |
20140379962 | DATA ENCODING FOR NON-VOLATILE MEMORY - A data storage device includes a memory and a controller. Mapping circuitry is configured to apply a mapping to received data to generate mapped data to be stored into the memory. The mapping is configured to increase average reliability by reducing an average number of state changes of storage elements per write operation and to reduce average write time by reducing a number of operations for storing the mapped value into the storage elements. | 12-25-2014 |
20140379963 | STORAGE SYSTEM, STORAGE DEVICE, AND CONTROL METHOD OF STORAGE SYSTEM - The storage device includes multiple NAND devices each of which performs a process on the basis of a command; a command management unit that issues the command from a host to one of the NAND devices specified by the command and that sends an issue completion notification of the issued command to the host; and a state notifying unit that notifies, based on whether each of the NAND devices performs a predetermined process, the host whether each of the NAND devices is ready to accept the command. The host includes a NAND control unit that selects one of the NAND devices that is ready to accept the command based on the notification from the state notifying unit when the issue completion notification is received and sends, to the command management unit, a command to allow the selected one of the NAND devices to perform the process. | 12-25-2014 |
20140379964 | DATA STORAGE DEVICE AND DATA FETCHING METHOD FOR FLASH MEMORY - A data storage device is provided. The data storage device, coupled to a host, includes: a flash memory; and a controller, configured to control accessing of the flash memory; wherein when the host performs random data accessing to the flash memory, the controller retrieves address information of a corresponding block and a corresponding page in the flash memory associated with first data to be read based on a global mapping table, and pre-fetches the corresponding page from the flash memory based on the address information; wherein when the controller obtains the address information, the controller further determines whether the first data is located in a current buffer block based on a local mapping table; wherein when the first data is located in the current buffer block, the controller further cancels the pre-fetched corresponding page, and reads the first data from the current buffer block. | 12-25-2014 |
20140379965 | ADAPTIVE CACHE MEMORY CONTROLLER - A system comprises a partitioning module and a writing module. The partitioning module is configured to partition each of a plurality of solid-state disks into a plurality of blocks. Each of the plurality of blocks has a predetermined size. The writing module is configured to write data to one or more of the plurality of solid-state disks in a sequence starting from a first block of a first solid-state disk of the plurality of solid-state disks to a first block of a last solid-state disk of the plurality of solid-state disks, and subsequently starting from a second block of the first solid-state disk to a second block of the last solid-state disk. In each of each of the plurality of the plurality of solid-state disks, the second block is subsequent to the first block. | 12-25-2014 |
20140379966 | Distributed Storage Service Systems and Architecture - Various methods, devices and systems are described for providing distributed storage services. A data storage device is capable of initiating a communication session with an external entity such as a local host computer (and vice versa) coupled directly to the data storage device, a remote server computer, or directly with remote data storage devices with or without intervention by a local host computer. | 12-25-2014 |
20140379967 | CLOCK SIGNAL GENERATOR FOR A DIGITAL CIRCUIT - A computer has a mother board upon which is mounted, a millimetre wave oscillator and a central processing unit (CPU). The millimetre wave oscillator is operable to generate a clock signal and transmit this to the CPU via a link. The clock signal may be employed as a system clock signal and a processing clock signal for the CPU. The millimetre wave oscillator allows higher frequency clock signals than are currently available whilst generating significantly less heat. Therefore, the CPU may not require any cooling system and if it does then a smaller cooling system than is required by the prior art will suffice. Furthermore, the CPU will be more stable. This arrangement requires less power than prior art arrangements and therefore may increase the battery life of a computer. | 12-25-2014 |
20140379968 | MEMORY SYSTEM HAVING A PLURALITY OF WRITING MODE - According to one embodiment, a memory system includes a non-volatile semiconductor memory, a block management unit, and a transcription unit. The semiconductor memory includes a plurality of blocks to which data can be written in both the first mode and the second mode. The block management unit manages a block that stores therein no valid data as a free block. When the number of free blocks managed by the block management unit is smaller than or equal to a predetermined threshold value, the transcription unit selects one or more used blocks that stores therein valid data as transcription source blocks and transcribes valid data stored in the transcription source blocks to free blocks in the second mode. | 12-25-2014 |
20140379969 | MEMORY CHANNEL CONNECTED NON-VOLATILE MEMORY - An apparatus includes a printed circuit board with a plurality of printed circuit board traces, a memory controller mounted on the printed circuit board coupled to one or more of the plurality of printed circuit board traces, a plurality of non-volatile type of memory integrated circuits coupled to the printed circuit board, and a plurality of support integrated circuits coupled between the memory controller and the plurality of non-volatile type of memory integrated circuits. | 12-25-2014 |
20140379970 | FLASH MEMORY DEVICE WITH MULTI-LEVEL CELLS AND METHOD OF WRITING DATA THEREIN - In one aspect, a method of writing data in a flash memory system is provided. The flash memory system forms an address mapping pattern according to a log block mapping scheme. The method includes determining a writing pattern of data to be written in a log block, and allocating one of SLC and MLC blocks to the log block in accordance with the writing pattern of the data. | 12-25-2014 |
20140379971 | VIDEO DISTRIBUTION SERVER AND SSD CONTROL METHOD - According to one embodiment, a video distribution server includes an SSD and an SSD operator. The SSD includes a storage medium and a controller. The controller executes a wear leveling process on the storage medium. The SSD operator gives the controller an instruction to disable a wear leveling function. The wear leveling function provides the wear leveling process. | 12-25-2014 |
20140379972 | MEMORY DEVICE, CONTROL METHOD FOR THE MEMORY DEVICE, AND CONTROLLER - During normal power operation, an erased free block is prepared in nonvolatile memory so that at least one erased free block is continuously available as a standby block. If a power failure occurs, volatile data and its address conversion information are written into the standby block in the nonvolatile memory. | 12-25-2014 |
20140379973 | GARBAGE COLLECTION MANAGEMENT IN MEMORIES - The disclosure is related to systems and methods of managing a memory. In a particular embodiment, a memory channel is disclosed that includes multiple memory units, with each memory unit comprising multiple garbage collection units. The memory channel also includes a controller that is communicatively coupled to the multiple memory units. The controller selects a memory unit of the multiple memory units for garbage collection based on a calculated number of memory units, of the multiple memory units, to garbage collect. | 12-25-2014 |
20140379974 | STORAGE SYSTEM COMPRISING FLASH MEMORY, AND STORAGE CONTROL METHOD - A storage system has a plurality of flash packages, and a storage controller for receiving a write request from a host and sending a write-data write request based on data conforming to this write request to a write-destination flash package. A virtual capacity, which is larger than the physical capacity of the flash package, is defined in the storage controller. The storage system compresses the write data, and writes the compressed write data to the write-destination flash chip. | 12-25-2014 |
20150012684 | Write Operations with Full Sequence Programming for Defect Management in Nonvolatile Memory - Data that is stored in a higher error rate format in a nonvolatile memory is backed up in a lower error rate format. Data to be stored may be transferred once to on-chip data latches where it is maintained while it is programmed in both the high error rate format and the low error rate format without being resent to the nonvolatile memory. High error rate format may be MLC format and programming in the high error rate format may program both lower page and upper page data together in a full sequence programming scheme that is suitable for handling high data volume. | 01-08-2015 |
20150012685 | Write Operations for Defect Management in Nonvolatile Memory - Data that is stored in a higher error rate format in a nonvolatile memory is backed up in a lower error rate format. Data to be stored may be transferred once to on-chip data latches where it is maintained while it is programmed in both the high error rate format and the low error rate format without being resent to the nonvolatile memory. | 01-08-2015 |
20150012686 | UNEVEN WEAR LEVELING IN ANALOG MEMORY DEVICES - A method for data storage in a memory that includes multiple analog memory cells, includes defining, based on a characteristic of the memory cells, an uneven wear leveling scheme that programs and erases at least first and second subsets of the memory cells with respective different first and second Programming and Erasure (P/E) rates. Data is stored in the memory in accordance with the uneven wear leveling scheme. | 01-08-2015 |
20150012687 | METHOD FOR MANAGING COMMANDS IN COMMAND QUEUE, MEMORY CONTROL CIRCUIT UNIT AND MEMORY STORAGE APPARATUS - A method for managing commands in a command queue, a memory controller, and a memory storage apparatus are provided. The method includes: storing at least one first command in a command queue register according to a plurality of first indication bits and updating the first indication bits according to a current storage status of the command queue register; generating a plurality of updated second indication bits according to the updated first indication bits and a plurality of second indication bits. The method also includes: obtaining at least one first command index corresponding to at least one register block storing the at least one first command in the command queue register according to the updated second indication bits and adding the at least one first command index into a command index register; executing commands corresponding to un-executed command indices in the command queue register. | 01-08-2015 |
20150012688 | COMPUTER SYSTEM AND OPERATING METHOD THEREOF - A computer system and an operating method thereof are disclosed herein. The operating method includes: dividing a file into a plurality of file segments; transmitting the file segments to an integrated circuit (IC) sequentially: receiving, through the IC, the file segments sequentially, and writing an operating file segment in a target storage page of a target block when the operating file segment is received; determining whether the operating file segment s successfully written in the target storage page; commanding the IC to erase the target block in a case that the operating file segment is not successfully written in the target storage page; searching a re-transmission start file segment corresponding to a start address of the target block; and, sequentially transmitting a plurality of remaining file segments of the file started from the re-transmission start file segment to the IC. | 01-08-2015 |
20150012689 | SYSTEMS AND METHODS FOR PERSISTENT ADDRESS SPACE MANAGEMENT - Data is stored on a non-volatile storage media in a sequential, log-based format. The formatted data defines an ordered sequence of storage operations performed on the non-volatile storage media. A storage layer maintains volatile metadata, which may include a forward index associating logical identifiers with respective physical storage units on the non-volatile storage media. The volatile metadata may be reconstructed from the ordered sequence of storage operations. Persistent notes may be used to maintain consistency between the volatile metadata and the contents of the non-volatile storage media. Persistent notes may identify data that does not need to be retained on the non-volatile storage media and/or is no longer valid. | 01-08-2015 |
20150012690 | Multi-Leveled Cache Management in a Hybrid Storage System - A hybrid storage system is described having a mixture of different types of storage devices comprising rotational drives, flash devices, SDRAM, and SRAM. The rotational drives are used as the main storage, providing lowest cost per unit of storage memory. Flash memory is used as a higher-level cache for rotational drives. Methods for managing multiple levels of cache for this storage system is provided having a very fast Level 1 cache which consists of volatile memory (SRAM or SDRAM), and a non-volatile Level 2 cache using an array of flash devices. It describes a method of distributing the data across the rotational drives to make caching more efficient. It also describes efficient techniques for flushing data from L1 cache and L2 cache to the rotational drives, taking advantage of concurrent flash devices operations, concurrent rotational drive operations, and maximizing sequential access types in the rotational drives rather than random accesses which are relatively slower. Methods provided here may be extended for systems that have more than two cache levels. | 01-08-2015 |
20150012691 | STORAGE CONTROL APPARATUS, CONTROL PROGRAM, AND CONTROL METHOD - A storage control apparatus which receives a command from a higher-level apparatus for a storage volume constructed by a plurality of storage devices one of which is a first storage device in which physically erasing data is performed on an area in which undesired data is stored in advance in preparation for next write and controls the storage devices, the storage control apparatus includes an identifying section configured to identify, as an erasing area, the area in which undesired data is stored in the first storage device, and an instructing section configured to instruct the first storage device to erase data in the erasing area identified by the identifying section. | 01-08-2015 |
20150012692 | SYSTEMS AND METHODS FOR MANAGING DATA - Systems and methods for managing data input/output operations are described. In one aspect, a device driver identifies a data read operation generated by a virtual machine in a virtual environment. The device driver is located in the virtual machine and the data read operation identifies a physical cache address associated with the data requested in the data read operation. A determination is made regarding whether data associated with the data read operation is available in a cache associated with the virtual machine. | 01-08-2015 |
20150019793 | SELF-MEASURING NONVOLATILE MEMORY DEVICES WITH REMEDIATION CAPABILITIES AND ASSOCIATED SYSTEMS AND METHODS - Several embodiments of systems incorporating nonvolatile memory devices are disclosed herein. In one embodiment, a system can include a central processor (CPU) and a nonvolatile memory device operably coupled to the CPU. The nonvolatile memory device can include a memory that stores pre-measurement instructions that are executable by the nonvolatile memory upon startup, but not executable by the CPU upon startup. In operation, the pre-measurement instructions direct the nonvolatile memory to take a measurement of at least a portion of its contents and to cryptographically sign the measurement to indicate that the measurement was taken by the nonvolatile memory device. In one embodiment, the CPU can use the measurement to determine whether the nonvolatile memory device is trustworthy. | 01-15-2015 |
20150019794 | DATA STORAGE DEVICE AND OPERATING METHOD THEREOF - A data storage device and a method of operating the same. The data storage device includes a nonvolatile memory device and a working memory device. The working memory device is configured to store an address mapping table to map a physical address associated with the nonvolatile memory device to a logical address associated with a host device. The data storage device further includes a controller configured to identify a hot address mapping table from a plurality of address mapping tables, based on an address mapping table classification, and store the hot address mapping table into the working memory device at an operation start time of the data storage device. | 01-15-2015 |
20150019795 | MEMORY SYSTEM FOR SHADOWING VOLATILE DATA - An apparatus configured to shadow volatile data while minimizing read latency is described. In an implementation, the apparatus includes a memory controller configured to operatively couple to a volatile memory device and a non-volatile memory device. The volatile memory device includes a volatile memory cell and the non-volatile memory device includes a corresponding non-volatile memory cell. The volatile memory device has a first transfer speed and the non-volatile memory device has a second transfer speed. The memory controller is configured to cause storage of data to the volatile memory cell and the non-volatile memory cell and to determine an occurrence of an unanticipated power outage. The memory controller is configured set a read speed to the second transfer speed and to cause replication of the data from the non-volatile memory cell to a corresponding volatile memory cell upon recovery from the unanticipated power outage. | 01-15-2015 |
20150019796 | DATA STORAGE DEVICE AND OPERATING METHOD THEREOF - An operating method of a data storage device, which includes a first memory area and a second memory area, includes selecting a victim block for securing a free area from the first memory area, calculating a first cost required when a merge operation for the victim block is performed in the first memory area, calculating a second cost required when the merge operation for the victim block is performed in the second memory area, and performing the merge operation in the first memory area or the second memory area based on the first and second costs. | 01-15-2015 |
20150019797 | Method and Apparatus for Providing Improved Garbage Collection Process In Solid State Drive - An improved garbage collection (“GC”) process configured to recover new blocks from used storage space is disclosed. After initiating the GC process for a flash memory in accordance with at least one of predefined triggering events, a first valid page within a first block marked as an erasable block is identified. Upon determining a first signature representing the content of the first valid page according to a predefined signature generator, the process identifies a second valid page within a second block as a duplicated page of the first valid page in response to the first signature. The process subsequently associates the logical block address (“LBA”) of the first valid page to the second valid page. In an alternative embodiment, page compression and sequential order of page arrangement can also be implemented to further enhance efficiency of garbage collection. | 01-15-2015 |
20150019798 | Method and Apparatus for Providing Dual Memory Access to Non-Volatile Memory - A method and system for providing a dual memory access to a non-volatile memory device using expended memory addresses are disclosed. The digital processing system such as a computer includes a non-volatile memory device, a peripheral bus, and a digital processing unit. The non-volatile memory device such as a solid state drive can store data persistently. The peripheral bus, which can be a peripheral component interconnect express (“PCIe”) bus, is used to support memory access to the non-volatile memory device. The digital processing unit such as a central processing unit (“CPU”) is capable of accessing storage space in the non-volatile memory device in accordance with an extended memory address and offset. | 01-15-2015 |
20150019799 | MULTI-LEVEL MEMORY, MULTI-LEVEL MEMORY WRITING METHOD, AND MULTI-LEVEL MEMORY READING METHOD - A memory comprising a memory array unit including a plurality of data units, and a controller. The controller is configured to receive data; convert the data into converted data using a conversion rule for converting a data piece into another data piece, wherein the conversion rule is selected based on the data received and independent of current data written in a data unit; and write the converted data and a conversion rule identifier corresponding to the conversion rule into the data unit. | 01-15-2015 |
20150019800 | Firmware Package to Modify Active Firmware - A computing device includes a non-volatile storage component with a first portion to include active firmware for components of the computing device and a second portion to include a firmware package to modify the active firmware. The computing device installs firmware from the firmware package and determines if the firmware is successfully installed before proceeding to install subsequent firmware from the firmware package. The computing device uninstalls the firmware package to restore the active firmware if a firmware from the firmware package fails to install. | 01-15-2015 |
20150019801 | SEMICONDUCTOR STORAGE DEVICE AND METHOD OF THROTTLING PERFORMANCE OF THE SAME - A semiconductor storage device and a method of throttling performance of the same are provided. The semiconductor storage device includes a non-volatile memory device; and a controller configured to receive a write command from a host and program write data received from the host to the non-volatile memory device in response to the write command. The controller inserts idle time after receiving the write data from the host and/or after programming the write data to the non-volatile memory device. | 01-15-2015 |
20150026386 | Erase Management in Memory Systems - Computer processor hardware receives notification that data stored in a region of storage cells in a non-volatile memory system stores invalid data. In response to the notification, the computer processor hardware marks the region as storing invalid data. The computer processor hardware controls the magnitude of erase dwell time (i.e., the amount of time that one or more cells are set to an erased state) associated with overwriting of the invalid data in the storage cells with replacement data. For example, to re-program respective storage cells, the data manager must erase the storage cells and then program the storage cells with replacement data. The data management logic can control the erase dwell time to be less than a threshold time value to enhance a life of the non-volatile memory system. | 01-22-2015 |
20150026387 | METHOD AND APPARATUS FOR SELECTING A MEMORY BLOCK FOR WRITING DATA, BASED ON A PREDICTED FREQUENCY OF UPDATING THE DATA - Some of the embodiments of the present disclosure provide a method for programming a flash memory having a plurality of memory blocks, wherein each memory block of the plurality of memory blocks is either a single-level cell (SLC) memory block or a multi-level cell (MLC) memory block, the method comprising assigning a weighting factor to each memory block of the plurality of memory blocks based on whether the memory block is an SLC memory block or an MLC memory block, tracking a number of write-erase cycles for each memory block, and selecting one or more memory blocks for writing data based at least in part on the weighting factor and the tracked number of write-erase cycles of each memory block of the plurality of memory blocks. Other embodiments are also described and claimed. | 01-22-2015 |
20150026388 | STORAGE CONTROL APPARATUS, DATA STORAGE APPARATUS, AND MEMORY CONTROL METHOD - According to one embodiment, a storage control apparatus includes an interface and a controller. The interface transfers data or a command to or from a nonvolatile memory including a storage area for each of banks. The controller controls read operations for the banks in accordance with generation of access requests to the banks, respectively. The controller prioritizes performing read-command issuance processing included in each of the read operations. | 01-22-2015 |
20150026389 | BLOCK GROUPING METHOD FOR SOLID STATE DRIVE - A block grouping method for a solid state drive includes the following steps. Firstly, plural blocks are classified into a high valid data count group and a low valid data count group according to valid data counts of respective blocks. An average erase count is set according to a specified number of blocks of the low valid data count group. A first block is selected from the high valid data count. A difference between the average erase count and a first erase count of the first block is calculated. If the difference exceeds a threshold value, a wear leveling operation is performed on the first block. | 01-22-2015 |
20150026390 | GARBAGE COLLECTION CONTROL METHOD FOR SOLID STATE DRIVE - A garbage collection control method for a solid state drive includes the following steps. Firstly, when a garbage collection is started by the solid state drive, a type of a write command from a host is judged. If the write command is not a sequential write command, a first type garbage collection is performed for obtaining a released space smaller than one free block space from a flash memory, and the write command is executed to store a write data into the flash memory. If the write command is the sequential write command, a second type garbage collection is performed for obtaining a released space larger than one free block space from the flash memory, and the write command is executed to store the write data into the flash memory. | 01-22-2015 |
20150026391 | BLOCK GROUPING METHOD FOR GARBAGE COLLECTION OF SOLID STATE DRIVE - A block grouping method includes the following steps. Firstly, a link list is established. In the link list, plural blocks are classified into plural groups according to valid data counts of respective blocks. If a host refreshes a stored data of a flash memory of the solid state drive or adds a new data into the flash memory, the valid data count of the block corresponding to the refreshed data or the new data is changed, and the link list is updated according to the changed valid data count of the block. After the garbage collection is started by the solid state drive, the block to be subject to the garbage collection is selected according to the link list, and the garbage collection is performed. | 01-22-2015 |
20150026392 | HOST-MANAGED Logical MASS STORAGE DEVICE USING MAGNETIC RANDOM ACCESS MEMORY (MRAM) - A mass storage device includes a storage media with magnetic random access memory (MRAM) devices and a NAND flash interface and NAND flash memory devices that are coupled to the MRAM devices. The storage media has partitions (Logical Units (LUNs)) made of a combination of MRAM and NAND flash memory and further includes a controller with a host interface and a NAND flash interface coupled to the MRAM and NAND flash memory devices through a flash interface. A host is coupled to the controller through the host interface and the storage media communicates attributes to the host, an attribute being associated with one of the partitions, where the host uses the partition based on their attributes to optimize its performance. | 01-22-2015 |
20150026393 | Semiconductor Memory Device - A semiconductor memory device includes a memory array, a setting unit and a control unit. The memory array consists of non-volatile memory cells. The setting unit set a page address of the memory array which is initially read out at startup. The control unit performs an internal sequence to read out the page address from the setting unit at startup and, according to the read-out page address, transmits page data corresponding to the read-out page address from the memory array to a page buffer. | 01-22-2015 |
20150026394 | MEMORY SYSTEM AND METHOD OF OPERATING THE SAME - A method of operating a memory system includes the operations of outputting dirty cache lines from a data cache to a volatile memory device as instructions are executed, and outputting from the volatile memory device to a non-volatile memory device as many dirty cache lines as the size of a page of the non-volatile memory. | 01-22-2015 |
20150026395 | STORAGE SYSTEM AND MANAGEMENT METHOD OF CONTROL INFORMATION THEREIN - An embodiment of this invention divides a cache memory of a storage system into a plurality of partitions and information in one or more of the partitions is composed of data different from user data and including control information. The storage system dynamically swaps data between an LU storing control information and a cache partition. Through this configuration, in a storage system having an upper limit in the capacity of the cache memory, a large amount of control information can be used while access performance to control information is kept. | 01-22-2015 |
20150026396 | MEMORY CARD AND HOST DEVICE THEREOF - A memory card is attached to a host device, and includes a data control circuit which transfers data with respect to the host device in synchronism with a rise edge and a fall edge of a clock signal. | 01-22-2015 |
20150032936 | Techniques for Identifying Read/Write Access Collisions for a Storage Medium - Examples are disclosed for identifying read/write access collisions for a storage medium. In some examples, a plurality of write access requests for access to a storage medium may be received at a controller for a storage medium. The plurality of write access requests may be associated with separate logical block address (LBA) ranges. The separate write LBA ranges may be stored to sets of first registers. A read access request to the storage medium may also be received and a read LBA range associated with the read access request may be stored to a set of second registers. The separate stored write LBA ranges may then be compared to the read LBA range to identify overlapping ranges that may indicate read/write access collisions to the storage medium. Other examples are described and claimed. | 01-29-2015 |
20150032937 | SYSTEM AND METHOD FOR PERFORMING EFFICIENT SEARCHES AND QUERIES IN A STORAGE NODE - A system and method of providing enhanced data processing and analysis in a storage node, such as a solid state drive (SSD). The SSD includes flash memory and an SSD processing unit capable of executing searches and analysis on the data in the flash memory without returning all of the data to be searched to a host CPU outside of the SSD. Other processing capabilities incorporated into the SSD may include encryption and decryption, compression and decompression, and in-line indexing of data, and data analytics. | 01-29-2015 |
20150032938 | SYSTEM AND METHOD FOR PERFORMING EFFICIENT PROCESSING OF DATA STORED IN A STORAGE NODE - A system and method of providing enhanced data processing and analysis in a storage device, such as a solid state drive (SSD). The SSD includes flash memory and an SSD processing unit capable of executing searches on the data in the flash memory without returning all of the data to be searched to a host CPU outside of the SSD. Other processing capabilities incorporated into the SSD may include encryption and decryption, compression and decompression, and in-line indexing of data. | 01-29-2015 |
20150032939 | SEMICONDUCTOR MEMORY GARBAGE COLLECTION - For semiconductor memory garbage collection, an identification module identifies a garbage collection time window for at least one block of a flash memory array. A garbage collection module garbage collects a first block of the flash memory array with a highest garbage collection level and an open garbage collection time window. | 01-29-2015 |
20150032940 | METHODS OF MANAGING POWER IN NETWORK COMPUTER SYSTEMS - In one embodiment of the invention, a memory apparatus is disclosed. The memory apparatus includes a memory array, a block read/write controller, and a random access read memory controller. The memory array is block read/write accessible and random read accessible. The block read/write controller is coupled between the memory array and an external interconnect. The block read/write controller performs block read/write operations upon the memory array to access blocks of consecutive memory locations therein. The random access read memory controller is coupled between the memory array and the external interconnect in parallel with the block read/write access controller. The random access read memory controller performs random read memory operations upon the memory array to access random memory locations therein. | 01-29-2015 |
20150032941 | NON-VOLATILE MEMORY INTERFACE - In an embodiment, a memory interface may send an indication that a request is being sent. The indication may be sent to a non-volatile memory via a point-to-point bus between a memory interface and the non-volatile memory. The memory interface may send the request to the non-volatile memory via the bus. The request may include an address that may be used to identify a location for storing or reading data. The non-volatile memory may acquire the request from the bus and process the request. After processing the request, the non-volatile memory may send an indication to the memory interface that indicates the non-volatile memory has a response to send to the memory interface. The memory interface may grant access to the bus to the non-volatile memory. After being granted access to the bus, the non-volatile memory may send the response to the memory interface. | 01-29-2015 |
20150032942 | SYSTEM FOR INCREASING UTILIZATION OF STORAGE MEDIA - A storage system creates an abstraction of flash Solid State Device (SSD) media allowing random write operations of arbitrary size by a user while performing large sequential write operations of a uniform size to an SSD array. This reduces the number of random write operations performed in the SSD array and as a result increases performance of the SSD array. A control element determines when blocks from different buffers should be combined together or discarded based on fragmentation and read activity. This optimization scheme increases memory capacity and improves memory utilization and performance. | 01-29-2015 |
20150032943 | CONTROLLER MANAGEMENT OF MEMORY ARRAY OF STORAGE DEVICE USING MAGNETIC RANDOM ACCESS MEMORY (MRAM) - A mass storage device includes a controller configured to communicate with a host. The controller is coupled to a first memory and a second memory, the first and second memories being of different types. The mass storage device includes a storage media partitioned into a plurality of Logical Units (LUNs) based on capabilities and resources of the mass storage device. The mass storage device further includes the first memory and the second memories and a hybrid reserved area spanning at least a portion of the first and second memories. | 01-29-2015 |
20150032944 | DATA STORAGE DEVICE AND FLASH MEMORY CONTROL METHOD - A FLASH memory control technique with wear leveling between the different blocks of the FLASH memory. By a controller managing the blocks of a FLASH memory within a data storage device, some of the blocks are pushed into a spare queue waiting to be allocated as data blocks or system blocks and some blocks are pushed into a jail queue to be inaccessible. When the jail queue is full and any block within the spare queue has an erase count greater than any block within the jail queue, for wear leveling between the different blocks within the FLASH memory, the controller releases a first block selected from the jail queue and pushes a second block selected from the spare queue into the jail queue. | 01-29-2015 |
20150032945 | METHOD FOR FLASH COMPRESSED INSTRUCTION CACHING FOR LIMITED RAM/FLASH DEVICE ARCHITECTURES - Compression and the caching of decompressed code in RAM is described by using an uncompressed paged instruction caching fault method to keep all of code compressed in a FLASH memory. The method only decompresses and caches in DRAM memory the portion of code that is miming at a certain instance in time (i.e., DRAM window), which maintains a pre-fetched portion of code based on static windowing FLASH. | 01-29-2015 |
20150032946 | METHODS, APPARATUS, AND SYSTEMS FOR SECURE DEMAND PAGING AND OTHER PAGING OPERATIONS FOR PROCESSOR DEVICES - A secure demand paging system ( | 01-29-2015 |
20150032947 | CONTROLLER MANAGEMENT OF MEMORY ARRAY OF STORAGE DEVICE USING MAGNETIC RANDOM ACCESS MEMORY (MRAM) IN A MOBILE DEVICE - A mass storage device includes a controller configured to communicate with a host. The controller is coupled to a first memory and a second memory, the first and second memories being of different types. The mass storage device includes a storage media partitioned into a plurality of Logical Units (LUNs) based on capabilities and resources of the mass storage device. The mass storage device further includes the first memory and the second memories and a hybrid reserved area spanning at least a portion of the first and second memories. | 01-29-2015 |
20150032948 | SEMICONDUCTOR STORAGE DEVICE AND METHOD OF THROTTLING PERFORMANCE OF THE SAME - A semiconductor storage device and a method of throttling performance of the same are provided. The semiconductor storage device includes a non-volatile memory device configured to store data in a non-volatile state; and a controller configured to control the non-volatile memory device. The controller calculates a new performance level, compares the calculated performance level with a predetermined reference, and determines the calculated performance level as an updated performance level according to the comparison result. | 01-29-2015 |
20150032949 | Semiconductor Device and Method of Controlling Non-Volatile Memory Device - A control circuit of a semiconductor device (memory module) realizes long life and others by a mechanism that suppresses and smoothes variations in use of a memory by equalizing the sizes of data write and data erase with respect to a data write request and sequentially allocating and using addresses of the memory in data write to an overwritable non-volatile memory device without carrying out an overwriting operation even in the case of an overwrite request. The control circuit realizes data write by a set of two types of operations of (a) an operation of erasing data of a first address or an operation of setting a flag value to an invalid state and (b) an operation of writing data to a second address different from the first address or an operation of setting a flag value to a valid state. | 01-29-2015 |
20150039805 | System and Method to Emulate an Electrically Erasable Programmable Read-Only Memory - The disclosure relates to an electronic memory system, and more specifically, to a system to emulate an electrically erasable programmable read-only memory, and a method to emulate an electrically erasable programmable read-only memory. According to an embodiment of the disclosure, a system to emulate an electrically erasable programmable read-only memory is provided, the system including a first memory section and a second memory section, wherein the first memory section comprises a plurality of storage locations configured to store data partitioned into a plurality of data segments and wherein the second memory section is configured to store information mapping a physical address of a data segment stored in the first memory section to a logical address of the data segment. | 02-05-2015 |
20150039806 | SYSTEM AND METHOD FOR CONTROLLING A STORAGE DEVICE - A method of controlling a storage device includes detecting a cumulative usage condition associated with the storage device, comparing the cumulative usage condition to a usage value, and adjusting the operation of the storage device based on the comparison. Another method of controlling a storage device includes detecting an operating condition associated with the storage device, comparing the operating condition to a warranty condition, and limiting the operation of the storage device to read-only operation based on the comparison. | 02-05-2015 |
20150039807 | NOR-TYPE FLASH MEMORY DEVICE CONFIGURED TO REDUCE PROGRAM MALFUNCTION - Embodiments of the present invention include a NOR-type flash memory device capable of reducing or eliminating program malfunctions. In some embodiments, the device includes a memory array, row selection circuit, column selection circuit, and program driver circuit. The memory array includes a memory sector having a first sector bit line and a second sector bit line. The memory array also includes a plurality of flash memory cells disposed on a matrix structure having a plurality of cell bit lines and a plurality of word lines arranged sequentially. The cell bit lines are alternately defined as first cell bit lines and second cell bit lines in sequential order. The first cell bit lines are connected to the first sector bit line in response to column selection signals thereof, and the second cell bit lines are connected to the second sector bit line in response to column selection signals thereof. | 02-05-2015 |
20150039808 | MEMORY SYSTEM - According to one embodiment, a memory system includes nonvolatile memories each storing data and an address table for acquiring an address of the data, and a control unit which is configured to be capable of accessing the nonvolatile memories in parallel, and issues table read requests for reading the address tables and data read requests for reading the data to the nonvolatile memories in response to read commands from a host. When a table read request and a data read request are issued to a same nonvolatile memory, the control unit processes the data read request in priority to the table read request. | 02-05-2015 |
20150039809 | NONVOLATILE MEMORY SYSTEM AND PROGRAMMING METHOD INCLUDING REPROGRAM OPERATION - A program method for a nonvolatile memory system including a reprogram operation that does not require a reload of first program data to page buffers of a constituent nonvolatile memory device between execution of a first coarse program step and execution of a first fine program step being performed after the execution of an intervening second coarse program step. | 02-05-2015 |
20150039810 | METHOD FOR MANAGING MEMORY APPARATUS, ASSOCIATED MEMORY APPARATUS THEREOF AND ASSOCIATED CONTROLLER THEREOF - A method for managing a memory apparatus and the associated memory apparatus thereof and the associated controller thereof are provided, where the method includes: temporarily storing data received from a host device into a volatile memory in the controller and utilizing the data in the volatile memory as received data, and dynamically monitoring the data amount of the received data to determine whether to immediately write the received data into at least one non-volatile memory element; and when determining to immediately write the received data into the at least one non-volatile memory element, directly writing the received data into a specific block configured to be a Multiple Level Cell memory block within a specific non-volatile memory element, rather than indirectly writing the received data into the specific block by first temporarily writing the received data into any other block configured to be Single Level Cell memory block. | 02-05-2015 |
20150039811 | METHOD FOR MANAGING MEMORY APPARATUS, ASSOCIATED MEMORY APPARATUS THEREOF AND ASSOCIATED CONTROLLER THEREOF - A method for managing a memory apparatus and the associated memory apparatus thereof and the associated controller thereof are provided, where the method includes: temporarily storing data received from a host device into a volatile memory in the controller and utilizing the data in the volatile memory as received data, and dynamically monitoring the data amount of the received data to determine whether to immediately write the received data into at least one NV memory element; and when a specific signal is received and it is detected that specific data having not been written into a same location in a specific block configured to be an MLC memory block within a specific NV memory element of the at least one NV memory element for a predetermined number of times exists in the received data, immediately writing the specific data into another block in the at least one NV memory element. | 02-05-2015 |
20150039812 | Modify Executable Bits of System Management Memory Page Table - A computing device to create a system management memory page table in response to the computing device powering on. The system management memory page table includes pages with executable bits. The computing device modifies the executable bits of the pages before launching an option read only memory of the computing device. | 02-05-2015 |
20150039813 | NAND Interface Capacity Extender Device For Extending Solid State Drives Capacity, Performance, And Reliability - A system and method for a solid state drive comprising a system controller and one or more extender devices coupled to the system controller is disclosed, where each extender device is coupled to a plurality of NAND storage devices and each NAND storage device comprising a plurality of NAND flash memory cells. | 02-05-2015 |
20150039814 | STORAGE DEVICE AND STORAGE SYSTEM INCLUDING THE SAME - A storage device may include a nonvolatile storage and a storage controller. The nonvolatile storage may include a map table which stores information including a logical address, a physical address corresponding to the logical address and a correlation index designating the physical address. The storage controller is configured to transmit the information to an external host device, and to access the nonvolatile storage based on a request and the correlation index, each of the request and the correlation index transmitted from the host device. | 02-05-2015 |
20150039815 | SYSTEM AND METHOD FOR INTERFACING BETWEEN STORAGE DEVICE AND HOST - A system and method of use thereof that include a mass storage device connected to a host computer running host software modules. The mass storage device includes at least one non-volatile memory device, at least one volatile memory device, and a memory controller attached to the non-volatile and volatile memory devices wherein the memory controller is connected to the host computer via a computer bus interface. Firmware executing on the memory controller provides software primitive functions, a software protocol interface, and an application programming interface to the host computer. The host software modules run by the host computer access the software primitives functions and the application programming interface of the mass storage device. | 02-05-2015 |
20150039816 | UTILIZATION OF DISK BUFFER FOR BACKGROUND REPLICATION PROCESSES - A method for replicating data from a first volume to a second volume includes receiving a first data request comprising a request for a first portion of data, wherein the first portion is part of a first volume. The first portion of data is read, and so is at least a second portion of data in addition to the first portion of data requested in the first data request. In response to determining that the second portion of data should be replicated to the second volume, the second portion of data is written to the second volume. | 02-05-2015 |
20150039817 | METHOD AND APPARATUS FOR PARALLEL TRANSFER OF BLOCKS OF DATA BETWEEN AN INTERFACE MODULE AND A NON-VOLATILE SEMICONDUCTOR MEMORY - A system including a non-volatile semiconductor memory (NVSM), an interface module and a control module. The NVSM stores first and second blocks of data. The first or second block of data is non-page based such that a size of the first block of data or a size of the second block of data is not an integer multiple of a page of data. The interface module transfers the first and second blocks of data during respectively a first data transfer event and a second data transfer event. The control module, based on descriptors, controls the first and second data transfer events such that the interface module transfers the first block of data between the interface module and the NVSM while transferring the second block of data between the interface module and the NVSM. The descriptors include respective sets of instructions for transferring the first and second blocks of data. | 02-05-2015 |
20150039818 | USE OF PREDEFINED BLOCK POINTERS TO REDUCE DUPLICATE STORAGE OF CERTAIN DATA IN A STORAGE SUBSYSTEM OF A STORAGE SERVER - A method and system for eliminating the redundant allocation and deallocation of special data on disk, wherein the redundant allocation and deallocation of special data on disk is eliminated by providing an innovate technique for specially allocating special data of a storage system. Specially allocated data is data that is pre-allocated on disk and stored in memory of the storage system. “Special data” may include any pre-decided data, one or more portions of data that exceed a pre-defined sharing threshold, and/or one or more portions of data that have been identified by a user as special. For example, in some embodiments, a zero-filled data block is specially allocated by a storage system. As another example, in some embodiments, a data block whose contents correspond to a particular type document header is specially allocated. | 02-05-2015 |
20150039819 | Apparatus and Method to Share Host System RAM with Mass Storage Memory RAM - A method includes, in one non-limiting embodiment, sending a request from a mass memory storage device to a host device, the request being one to allocate memory in the host device; writing data from the mass memory storage device to allocated memory of the host device; and subsequently reading the data from the allocated memory to the mass memory storage device. The memory may be embodied as flash memory, and the data may be related to a file system stored in the flash memory. The method enables the mass memory storage device to extend its internal volatile RAM to include RAM of the host device, enabling the internal RAM to be powered off while preserving data and context stored in the internal RAM. | 02-05-2015 |
20150039820 | FLASH MEMORY STORAGE SYSTEM AND CONTROLLER AND DATA WRITING METHOD THEREOF - A flash memory storage system having a flash memory controller and a flash memory chip is provided. The flash memory controller configures a second physical unit of the flash memory chip as a midway cache physical unit corresponding to a first physical unit and temporarily stores first data corresponding to a first host write command and second data corresponding to a second host write command in the midway cache physical unit, wherein the first and second data corresponding to slow physical addresses of the first physical unit. Then, the flash memory controller synchronously copies the first and second data from the midway cache physical unit into the first physical unit, thereby shortening time for writing data into the flash memory chip. | 02-05-2015 |
20150046630 | Patching of Programmable Memory - A programmable memory | 02-12-2015 |
20150046631 | APPARATUSES AND METHODS FOR CONFIGURING I/Os OF MEMORY FOR HYBRID MEMORY MODULES - Apparatuses, hybrid memory modules, memories, and methods for configuring I/Os of a memory for a hybrid memory module are described. An example apparatus includes a non-volatile memory, a control circuit coupled to the non-volatile memory, and a volatile memory coupled to the control circuit. The volatile memory is configured to enable a first subset of I/Os for communication with a bus and enable a second subset of I/O for communication with the control circuit, wherein the control circuit is configured to transfer information between the volatile memory and the non-volatile memory. | 02-12-2015 |
20150046632 | MEMORY ADDRESS MANAGEMENT METHOD, MEMORY CONTROLLER AND MEMORY STORAGE DEVICE - A memory address management method, a memory controller, and a memory storage device are provided. The memory address management method includes: obtaining memory information of a rewritable non-volatile memory module and formatting logical addresses according to the memory information to establish a file system, such that an allocation unit of the file system includes a lower logical programming unit and an upper logical programming unit. Here, the memory information includes a programming sequence, the allocation unit starts with the lower logical programming unit and ends with the upper logical programming unit, and an initial logical address of a data region in the file system belongs to the lower logical programming unit. Accordingly, an access bandwidth of the memory storage device is expanded. | 02-12-2015 |
20150046633 | CACHE CONTROL METHOD AND STORAGE DEVICE - According to one embodiment of the present invention, a cache control method of a storage device is provided, the storage device including: a storage unit that stores data, and a buffer memory having a first cache area and a second cache area serving as a cache of the storage unit. The cache control method according to the embodiment includes: storing data read from the storage unit in the first cache area in response to a read command from a host; moving retried data, on which a read retry has occurred upon the readout from the storage unit, to the second cache area from the first cache area in order that the retried data amount in the second cache area is not more than a predetermined data amount; and transferring data in the first cache area or the second cache area to the host. | 02-12-2015 |
20150046634 | MEMORY SYSTEM AND INFORMATION PROCESSING DEVICE - According to embodiments a memory system is connectable to a host which includes a host controller and a host memory including a first memory area and a second memory area. The memory system includes an interface unit, a non-volatile memory, and a controller unit. The interface unit receives a read command and a write command. The controller unit writes write-data to the non-volatile memory according to the write command. The controller unit determines whether read-data requested by the read command is in the first memory area. If the read-data is in the first memory area, the controller unit causes the host controller to copy the read-data from the first memory area to the second memory area. If the read-data is not in the first memory area, the controller unit reads the read-data from the non-volatile memory and causes the host controller to store the read-data in the second memory area. | 02-12-2015 |
20150046635 | Electronic System with Storage Drive Life Estimation Mechanism and Method of Operation Thereof - Systems, methods and/or devices are used to enable storage drive life estimation. In one aspect, the method includes (1) determining two or more age criteria of a storage drive, and (2) determining a drive age of the storage drive in accordance with the two or more age criteria of the storage drive. | 02-12-2015 |
20150046636 | STORAGE DEVICE, COMPUTER SYSTEM AND METHODS OF OPERATING SAME - A method of operating a storage device which includes a non-volatile memory including a normal unit configured to store normal data and a swap unit configured to store swap data and a controller configured to control the non-volatile memory is provided. The method includes receiving the swap data and a unit selection signal for selecting the swap unit from a host; and processing the swap data according to a data processing policy of the swap unit and writing the processed swap data to the swap unit. The data processing policy of the swap unit may be different from a data processing policy of the normal unit. | 02-12-2015 |
20150046637 | DATA STORAGE DEVICE AND METHOD FOR RESTRICTING ACCESS THEREOF - A data storage device including a flash memory, a temperature sensor and a controller. The flash device is arranged to store data. The temperature sensor is arranged to detect surrounding ambient temperature. The controller is configured to receive a write command from a host, and perform a protection mechanism when the detected surrounding ambient temperature is outside a predetermined rage, wherein the write command is arranged to enable the controller to write data into the flash, and the controller is configured to restrict writing during the protect mode. | 02-12-2015 |
20150046638 | MULTI-BIT MEMORY DEVICE AND ON-CHIP BUFFERED PROGRAM METHOD THEREOF - A program method of a multi-bit memory device is provided. First page data is programmed in a first region of a memory cell array. The first page data is stored in a first buffer of a page buffer. Second page data is programmed in the first region of the memory cell array. The second page data is stored in a third buffer of the page buffer. Third page data is stored in the first region of the memory cell array. The second page data stored in the third buffer is transferred to a second buffer of the page buffer and the third page data is stored in the third buffer. The first to third page data stored in page buffer are programmed in a second region of the memory cell array. | 02-12-2015 |
20150046639 | SYSTEM AND METHOD OF PAGE BUFFER OPERATION FOR MEMORY DEVICES - Systems and methods are provided for using page buffers of memory devices connected to a memory controller through a common bus. A page buffer of a memory device is used as a temporary cache for data which is written to the memory cells of the memory device. This can allow the memory controller to use memory devices as temporary caches so that the memory controller can free up space in its own memory. | 02-12-2015 |
20150046640 | Method for Utilizing a Memory Interface to Control Partitioning of a Memory Module - Described herein are at least one apparatus and methods for implementing partitioning in memory cards and modules. A representative memory card/module in accordance with the invention may include a memory device(s), and a memory interface which includes a data bus, a command line and a clock line. The memory card/module may further include a memory controller coupled to the memory device(s) and to the memory interface. The memory card/module may include means for controlling the partitioning of the memory device(s). The memory controller may be configured to operate the memory device(s) in accordance with the partition information. | 02-12-2015 |
20150052288 | APPARATUSES AND METHODS FOR PROVIDING DATA FROM A BUFFER - Apparatuses and methods for providing data from a buffer are disclosed herein. An example apparatus may include an array, a buffer, and a memory control unit. The buffer may be coupled to the array and configured to store data. The data may include data intended to be stored in the storage area. The memory control unit may be coupled to the array and the buffer. The memory control unit may be configured to cause the buffer to store the data responsive, at least in part, to a write command and may further be configured to cause the buffer to store the data intended to be stored in the storage area in the storage area of the array responsive, at least in part, to a flush command. | 02-19-2015 |
20150052289 | Memory System Performance Configuration - A nonvolatile memory die is tested to determine certain parameters such as read time, which are then recorded in the nonvolatile memory die. After the die is incorporated into a memory system, and firmware is downloaded, the nonvolatile memory system uses the recorded parameters to determine how to configure the memory system for operation within specified limits, such as determining how much delay to apply to read operations. | 02-19-2015 |
20150052290 | DATA STORAGE DEVICE AND OPERATING METHOD THEREOF - An operating method of a data storage device includes comparing the number of address mapping table segments containing changed address mapping information with a backup reference value, and backing up the address mapping table segments containing the changed address mapping information in response to the comparison result. | 02-19-2015 |
20150052291 | SEMICONDUCTOR STORAGE DEVICE AND SEMICONDUCTOR STORAGE DEVICE CONTROL METHOD - A semiconductor storage device includes: a storage; an address translater configured to translate a logical address for access to the storage to a physical address based on address translation information; and a controller configured to output the address translation information to the address translater, wherein the controller, when the address translation information is changed, interchanges a first physical address based on first address translation information before the change and a second physical address based on second address translation information after the change in the storage. | 02-19-2015 |
20150052292 | METHOD FOR ERASING DATA ENTITY IN MEMORY MODULE - A method including storing a data entity using at least two sectors of a memory device, the at least two sectors associated to the same data entity, and maintaining, at a memory controller, context information of the data entity comprising a pointer to at least one of the at least two sectors of the memory device. The method further includes erasing the at least two sectors of the memory device using the context information. | 02-19-2015 |
20150052293 | HIDDEN CORE TO FETCH DATA - A computing device includes a home node controller to couple a home processor socket to the computing device. The home processor socket includes a home core hidden from the computing device and the home core fetches data to a home cache of the home processor socket. The computing device includes a source processor socket including a source core to request for data and the home node controller forwards requested data from the home cache to the source core if the requested data is included on the home cache. | 02-19-2015 |
20150052294 | NONVOLATILE MEMORY DEVICE AND OPERATING METHOD THEREOF - An operating method of a nonvolatile memory device includes receiving a read command from a memory controller; determining a read mode based on the received read command, controlling a precharge time and an offset of a precharge control signal according to the determination result, and precharging a sensing bit line among bit lines to a precharge voltage based on the controlled precharge control signal. The sensing bit line is a bit line being precharged according to the determined read mode among the bit lines. | 02-19-2015 |
20150052295 | ADDRESS TRANSLATION FOR A NON-VOLATILE MEMORY STORAGE DEVICE - Techniques are described for accessing data from a storage device. In one example, the storage device may include a storage medium comprising non-volatile memory, a network connection, and one or more processing entities. The one or more processors may be configured to receive a request from the network connection at the non-volatile memory storage device for accessing data associated with a file system object, the request comprising a virtual address offset, a file object identifier and a size of the data access, perform, at a flash translation layer of a storage device software stack executing on the one or more processing entities of the storage device, a translation from the virtual address offset to a physical address for the data stored on the non-volatile memory, using the virtual address offset and the file object identifier, and access the data from the physical address from the storage medium. | 02-19-2015 |
20150052296 | Semiconductor Device - Provided is a user-friendly information processing system which is capable of maintaining latency within a fixed range and ensuring the expandability of a memory capacity at high speed and low cost. The information processing system, including an information processing device, a volatile memory, and nonvolatile memories, is configured. The information processing device, the volatile memory, and the nonvolatile memories are connected in series with one another to reduce the number of connection signals, thereby realizing speeding-up while maintaining the expandability of the memory capacity. The information processing device manages response time zones and time zones where responses overlap one another, and performs a correction operation on the latency, thereby realizing fast data transfer while maintaining the latency within the fixed range. The information processing device performs an error correction to improve the reliability when transferring the data of the nonvolatile memories to the volatile memory. The information processing system composed of a plurality of chips is configured as an information processing system/module in which the respective chips are arranged in layers, and wired together by a through via. | 02-19-2015 |
20150052297 | STORAGE SYSTEM AND DATA CONTROL METHOD THEREFOR - Package controller of a flash package, upon receiving an update data write request with respect to a first logical storage area corresponding to a first LU that is treated as a backup target, manages a first physical storage area as a backup storage area in a state where pre-update data is maintained, allocates a second physical storage area to the first logical storage area, and writes the update data to the second physical storage area. The package controller, upon receiving an update data write request with respect to a second logical storage area corresponding to a second LU that is treated as a non-backup target, manages a third physical storage area allocated to the second logical storage area as an invalid storage area, and writes the update data to a fourth physical storage area newly allocated to the second logical storage area. | 02-19-2015 |
20150058524 | BIMODAL FUNCTIONALITY BETWEEN COHERENT LINK AND MEMORY EXPANSION - Methods and apparatus relating to provide bimodal functionality between a coherent link and memory expansion are described. In one embodiment, a processor is coupled to one or more agents via a coherent interconnect. The processor is also coupled to one or more Dual Inline Memory Modules (DIMMs) via a link logic. The logic supports read or write commands directed at the one or more DIMMs based on a single bit of data. Other embodiments are also disclosed and claimed. | 02-26-2015 |
20150058525 | GARBAGE COLLECTION IN HYBRID MEMORY SYSTEM - A hybrid memory system includes a primary memory and a secondary memory. A garbage collection operation is performed on the hybrid memory system. A read operation comprising reading data from a first cluster of a plurality of clusters is performed. Responsive to a determination that the read operation failed, the first cluster is unmapped without writing the data to a second cluster and the first cluster continues to be used for subsequent data storage. Responsive to a determination that the read operation did not fail, data is written to the second cluster. | 02-26-2015 |
20150058526 | MEMORY ACCESS REQUESTS IN HYBRID MEMORY SYSTEM - Incoming memory access requests are routed in a set of incoming queues, the incoming memory access requests comprise a range of host logical block addresses (LBAs) that correspond to a memory space of a primary memory. The host LBA range is directly mapped to clusters of secondary memory, the secondary memory corresponding to a memory space of a secondary memory. Each incoming memory access request queued in the set of incoming queues is transformed into one or more outgoing memory access requests that include a range of secondary memory clusters or one or more clusters of secondary memory clusters. The outgoing memory access requests are routed in a set of outgoing queues. The secondary memory is accessed using the outgoing memory access requests. | 02-26-2015 |
20150058527 | HYBRID MEMORY WITH ASSOCIATIVE CACHE - A hybrid memory system includes a primary memory comprising a host memory space arranged as memory sectors corresponding to host logical block addresses (host LBAs). A secondary memory is implemented as a cache for the primary host memory. A hybrid controller is configured directly map the clusters of host LBAs to clusters of secondary memory. The secondary memory clusters correspond to a memory space of the cache. Mapping of the host LBA secondary memory clusters is fully associative such that any host LBA cluster can be mapped to any secondary memory cluster. | 02-26-2015 |
20150058528 | RELOCATING DATA BASED ON MATCHING ADDRESS SEQUENCES - A data storage device includes a non-volatile memory and a controller. The controller is configured to store a first sequence of addresses based on a first sequence of read instructions received from a host device. Subsequent to storing the first sequence of addresses, the controller is configured to receive a second sequence of read instructions from the host device and to determine whether a second sequence of addresses that is based on the second sequence of read instructions matches the first sequence of addresses. The controller is configured to relocate at least one page of the non-volatile memory at least partially based on the second sequence of addresses matching the first sequence of addresses. | 02-26-2015 |
20150058529 | SYSTEMS AND METHODS OF PROCESSING ACCESS REQUESTS AT A DATA STORAGE DEVICE - A data storage device includes a non-volatile memory and a controller. A method performed in the data storage device includes sending multiple access requests to a plurality of non-volatile memory devices of the data storage device. The multiple access requests correspond to a command and are associated with a first order. The method further includes receiving a plurality of output data items from the plurality of non-volatile memory devices. The plurality of output data items is based on the multiple access requests and is received in a second order that is different from the first order. The method also includes reordering the plurality of output data items according to the first order. | 02-26-2015 |
20150058530 | SMART DYNAMIC WEAR BALANCING BETWEEN MEMORY POOLS - A memory system or flash card may include a dynamic system-level process for the management of blocks in the different memory pools. There may be spare blocks available to the pools that are over provisioned to the pool which increases the efficiency of data compaction and helps reduce the average hot count for that pool and compensate for the grown defects. The block wear and grown defects in each memory pool may be tracked so that remaining spare blocks can be re-allocated. | 02-26-2015 |
20150058531 | DATA WRITING METHOD, MEMORY CONTROL CIRCUIT UNIT AND MEMORY STORAGE APPARATUS - A data writing method for a memory storage apparatus having a first buffer memory, a second buffer memory and a rewritable non-volatile memory module is provided, and the transmission bandwidth of the first buffer memory is larger than the transmission bandwidth of the second buffer memory. The method includes: receiving a write command and first data thereof; determining whether the first data belongs to the successive big data; if the first data belongs to the successive big data, temporarily storing the first data into a first data buffer area of the first buffer memory, writing the first write data from the first data buffer area to the rewritable non-volatile memory module; and if the first data does not belongs to the successive big data, temporarily storing the first data into a second data buffer area of the second buffer memory. | 02-26-2015 |
20150058532 | MEMORY DEVICE, INFORMATION-PROCESSING DEVICE AND INFORMATION-PROCESSING METHOD - A memory device of an embodiment includes a non-volatile storage device, and a volatile storage device that stores observation information indicating a state of the memory device. The memory device is provided with a controller that executes an observation information sending process that sends a write command, which is an instruction to write the observation information in the host-side storage device, and the observation information to the host device. Further, the controller repeats the observation information sending process plural times in response to one sending request from the host device. | 02-26-2015 |
20150058533 | DATA STORAGE CONTROLLER AND METHOD FOR EXPOSING INFORMATION STORED IN A DATA STORAGE CONTROLLER TO A HOST SYSTEM - A data storage controller exposes information stored in a locally managed volatile memory store to a host system. The locally managed volatile memory store is mapped to a corresponding portion of a peripheral component interconnect express (PCIe) compliant memory space managed by the host system. Backup logic in the data storage controller responds to a power event detected at the interface between the data storage controller and the host system by copying the contents of the volatile memory store to a non-volatile memory store on the data storage controller. Restore logic restores a data storage controller state by copying the contents of the non-volatile memory store to the locally managed volatile memory store upon the application of power such that the data in the volatile memory store is persistent even in the event of a loss of power to the host system and or the data storage controller. | 02-26-2015 |
20150058534 | MANAGING METHOD FOR CACHE MEMORY OF SOLID STATE DRIVE - A managing method for a cache memory of a solid state drive includes the following steps. When the solid state drive decides to perform a garbage collection, a storing space of the cache memory is divided into plural storing portions. A first storing portion of the cache memory is set as a buffering unit for a garbage collection purpose. A second storing portion of the cache memory is set as a buffering unit for a writing purpose. | 02-26-2015 |
20150058535 | RELOCATING DATA BASED ON MATCHING ADDRESS SEQUENCES - A data storage device includes a non-volatile memory that includes a three-dimensional (3D) memory. A controller of the data storage device is configured to store a first sequence of addresses based on a first sequence of read instructions received from a host device. Subsequent to storing the first sequence of addresses, the controller is configured to receive a second sequence of read instructions from the host device and to determine whether a second sequence of addresses that is based on the second sequence of read instructions matches the first sequence of addresses. The controller is configured to relocate at least one page of the non-volatile memory at least partially based on the second sequence of addresses matching the first sequence of addresses. | 02-26-2015 |
20150058536 | MEMORY CONTROLLER HAVING STATE SHAPING ENGINE AND METHOD OF OPERATING SAME - A memory controller includes a state shaping encoder that receives k-bit write data, selects a logical page with reference to state shape mapping information, and changes data of the logical page to decrease an occurrence probability of a high-order program state among program states used to program the k-bit data in multi-level memory cells. | 02-26-2015 |
20150058537 | Methods for Accessing a Storage Unit of a Flash Memory and Apparatuses using the Same - An embodiment of a method for accessing a storage unit of a flash memory, performed by a processing unit, includes at least the following steps. A storage-unit access interface is directed to program data into the nth wordline of a storage unit. The storage-unit access interface is directed to program the same data into the (n−1)th wordline of the storage unit after the storage unit completes the data programming of the nth wordline of the storage unit. The storage-unit access interface is directed to program the same data into the (n−2)th wordline of the storage unit after the storage unit completes the data programming of the (n−1)th wordline of the storage unit, where n is an integer greater than 2. | 02-26-2015 |
20150058538 | TECHNIQUES FOR UPDATING MEMORY OF A CHASSIS MANAGEMENT MODULE - A technique for data roll-back includes in response to a first external static memory device being coupled to a first chassis management module and the first chassis management module being coupled to a middle plane board, determining whether the first external static memory device operates normally. In response to the first external static memory device operating normally, a controller of the first chassis management module writes data in the first external static memory device into a non-volatile memory of the first chassis management module to perform data roll-back. | 02-26-2015 |
20150058539 | Method and Apparatus for Restoring Flash Translation Layer (FTL) in Non-Volatile Storage device - A method and apparatus configured to restore a flash translation layer (“FTL”) in a non-volatile (“NV”) storage device are disclosed. After reactivating the NV storage device from an unintended system crash, a process of recovering FTL, in one embodiment, receives a request for restoring at least a portion of the FTL or FTL database. After identifying sequence numbers (“SNs”) associated with flash memory blocks (“FMBs”) which are generated during write cycle(s), the SNs are retrieved from the information storage locations such as state information in the FMBs. A portion of the FTL database is subsequently reconstructed in a random access memory (“RAM”) according to the SNs. In an alternative embodiment, logical block addresses (“LBAs”), LBA lists, and/or index tables can also be used to restore the FTL database or table. | 02-26-2015 |
20150058540 | HYBRID-DEVICE STORAGE BASED ON ENVIRONMENTAL STATE - A hybrid storage device that includes a hard-disk drive (HDD) and a flash memory is described. When control logic in the hybrid storage device receives a request from an external device to write a block of data to a logical address in a first portion of an address space that maps to the HDD, the control logic writes the block of data to the HDD. However, if there is a change in environmental state information of the hybrid storage device during the write operation, the control logic writes at least a portion of the block of data to a logical address for the block of data in a second portion of the address space which maps to the flash memory. Note that the address space may be common to the external device and the hybrid storage device. | 02-26-2015 |
20150058541 | MEMORY MANAGEMENT DEVICE AND METHOD - According to one embodiment, a device includes a determination unit, compression unit, selecting unit, write updating unit, writing unit. The determination unit determines whether to compress write data based on specific information. The specific information including at least one of the type, number of accesses, access frequency and importance level of the write data. The compression unit compresses the write data when determining to compress the write data. The selecting unit selects a write region for the write data in nonvolatile memory based on the specific information. The write updating unit updates the specific information. The writing unit writes compressed write data into the write region when determining to compress the write data. The writing unit writes uncompressed write data into the write region when not determining to compress the write data. | 02-26-2015 |
20150058542 | UPDATING TECHNIQUES FOR MEMORY OF A CHASSIS MANAGEMENT MODULE - A technique for data roll-back includes in response to a first external static memory device being coupled to a first chassis management module and the first chassis management module being coupled to a middle plane board, determining whether the first external static memory device operates normally. In response to the first external static memory device operating normally, a controller of the first chassis management module writes data in the first external static memory device into a non-volatile memory of the first chassis management module to perform data roll-back. | 02-26-2015 |
20150058543 | SYSTEM AND METHOD FOR PROTECTING DATA STORED ON A REMOVABLE DATA STORAGE DEVICE - A system for protecting data stored in a removable data storage device includes a personal electronic device, a removable solid state data storage device operatively coupled to the personal electronic device, and a circuit configured to protect data stored in the data storage device in response to detecting impending removal of the data storage device from the personal electronic device. | 02-26-2015 |
20150058544 | FLASH MEMORY APPARATUS WITH SERIAL INTERFACE AND RESET METHOD THEREOF - A flash memory apparatus with serial interface is disclosed. The flash memory apparatus includes a command receiver, a command decoder and a core circuit. The command receiver sequentially receives a plurality of command data through the data input pin and the clock pin. The command decoder receives a command sequence formed by the command data, and compares the command sequence with a reference sequence to generate a reset signal. The core circuit receives the reset signal to activate a reset operation according to the reset signal. | 02-26-2015 |
20150058545 | USING EXTERNAL MEMORY DEVICES TO IMPROVE SYSTEM PERFORMANCE - The invention is directed towards a system and method that utilizes external memory devices to cache sectors from a rotating storage device (e.g., a hard drive) to improve system performance. When an external memory device (EMD) is plugged into the computing device or onto a network in which the computing device is connected, the system recognizes the EMD and populates the EMD with disk sectors. The system routes I/O read requests directed to the disk sector to the EMD cache instead of the actual disk sector. The use of EMDs increases performance and productivity on the computing device systems for a fraction of the cost of adding memory to the computing device. | 02-26-2015 |
20150058546 | SOLID STATE DRIVE DEVICE - The solid state drive device includes a memory device including a plurality of flash memories and a memory controller connected with a host and configured to control the memory device. The memory controller includes first and second cores, a host interface configured to interface with the host, and a flash memory controller configured to control the plurality of flash memories. The first core is configured to control transmission and reception of data to and from the host. The second core is configured to control transmission and reception of data to and from the memory device. | 02-26-2015 |
20150058547 | APPARATUS, SYSTEM, AND METHOD FOR ALLOCATING STORAGE - An apparatus, system, and method are disclosed for allocating non-volatile storage. The storage device may present a logical address, which may exceed a physical storage capacity of the device. The storage device may allocate logical capacity in the logical address space. An allocation request may be allowed when there is sufficient unassigned and/or unallocated logical capacity to satisfy the request. Data may be stored on the non-volatile storage device by requesting physical storage capacity. A physical storage request, such as a storage request or physical storage reservation, when there is sufficient available physical storage capacity to satisfy the request. The device may maintain an index to associate logical identifiers (LIDs) in the logical address space with storage locations on the storage device. This index may be used to make logical capacity allocations and/or to manage physical storage space. | 02-26-2015 |
20150067231 | On-Demand Snapshot and Prune in a Data Storage System - A method of data progression in a data storage system having at least two tiers of storage space. A first tier may include storage space in a SLC SSD and a second tier may include storage space in a MLC SSD. The method may include setting a predetermined free space threshold for the first tier of storage space, monitoring free space in the first tier of storage space, and when the amount of available free space in the first tier of storage space decreases to the predetermined free space threshold, generating an on-demand snapshot of at least a portion of the data of the first tier of storage space by designating that data as read-only. The on-demand snapshot may then be transferred to the second tier of storage space, thereby freeing the corresponding portion of data of the first tier of storage space for new writes. | 03-05-2015 |
20150067232 | SUB-SECTOR WEAR LEVELING IN MEMORIES - Methods and memories for wear leveling by sub-sectors of a block are provided. In one such method, data are transferred from a first block of the memory to a second block of the memory, excluding a sub-sector of the first block that is to be erased, logical addresses for the first block and the second block are swapped with each other, the first block is erased, data are transferred from a third block to the first block, logical addresses for the first block and the third block are swapped with each other, and the third block is erased. | 03-05-2015 |
20150067233 | DATA STORAGE DEVICE AND FLASH MEMORY CONTROL METHOD THEREOF - A mapping table H | 03-05-2015 |
20150067234 | UNIFIED MEMORY CONTROLLER FOR HETEROGENEOUS MEMORY ON A MULTI-CHIP PACKAGE - An enhanced multi chip package (eMCP) is provided including a unified memory controller. The UMC is configured to manage different types of memory, such as NAND flash memory and DRAM on the eMCP. The UMC provides storage memory management, DRAM management, DRAM accessibility for storage memory management, and storage memory accessibility for DRAM management. The UMC also facilitates direct data copying from DRAM to storage memory and vice versa. The direct copying may be initiated by the UMC without interaction from a host, or may be initiated by a host. | 03-05-2015 |
20150067235 | MEMORY SYSTEM AND DATA WRITING METHOD - According to one embodiment, a memory system including plural processing units, each of which is provided for each transmission path, and a data distribution unit, is provided. The data distribution unit distributes a data frame to a write control unit that has execution management information including identification information equal to identification information in the received data frame, in the case where the same address is set to the input/output units in the plural processing units. The data distribution unit transfers the data frame to the write control unit in the processing unit including the input/output unit from which the data frame is received, in the case where a different address is set to the input/output unit in each of the processing units. | 03-05-2015 |
20150067236 | MEMORY SYSTEM - According to one embodiment, the memory controller outputs a first command, then outputs N pieces of second commands to first and second memory chips, and reads out the read data from the first and second memory chips. First time is for reading out the read data from a memory cell array to a buffer, and second time is for transferring data of the one-Nth of the read data from the buffer to the memory controller. The memory controller outputs the first command, then outputs M pieces of the second commands to the first memory, then outputs a first command to the second memory chip, and then outputs (N−M) pieces of the second commands to the first memory chip. A relationship of (N−M−1)×(second time)03-05-2015 | |
20150067237 | MEMORY CONTROLLER, SEMICONDUCTOR MEMORY SYSTEM, AND MEMORY CONTROL METHOD - According to one embodiment, a memory controller includes an address translation information storage unit that stores plural translation information formed by classifying a correspondence between a logical address and a physical address into two or more hierarchies, a tag management unit that sores a cache line tag, which includes hierarchy information corresponding to each of the translation information stored in the translation information storage unit, and a control unit that identities whether the translation information is stored in the translation information storage unit or not by using a cache line tag. | 03-05-2015 |
20150067238 | Computing Device and Method for Predicting Low Memory Conditions - A computing device and method for predicting low memory conditions are disclosed. In one embodiment, a computing device is provided having volatile memory, non-volatile memory, and a processor. The processor generates a metric predictive of an upcoming low-memory condition in the volatile memory. The processor then compares the metric to a threshold. If the metric exceeds the threshold, the processor creates free space in the volatile memory. Other embodiments are possible, and each of the embodiments can be used alone or together in combination. | 03-05-2015 |
20150067239 | DATA STORAGE DEVICE AND FLASH MEMORY CONTROL METHOD - A FLASH memory control technique with wear leveling between the different blocks of the FLASH memory. By a controller managing the blocks of a FLASH memory within a data storage device, some of the blocks are pushed into a spare queue waiting to be allocated as data blocks or system blocks. When the number of blocks within the spare queue is lower than a clean threshold and any block within the spare queue has an erase count greater than an overused lower threshold, the controller performs a garbage correction operation with wear leveling between the different blocks. | 03-05-2015 |
20150067240 | STORAGE APPARATUS AND ITS DATA PROCESSING METHOD - A storage apparatus has a controller for controlling data input to and output from a plurality of storage devices composed of flash memories and the controller manages the number of times data are written to each storage device on the basis of each storage device, wherein when the controller receives a write command from an access requestor and if any of the storage devices is a storage device whose number of times of data write exceeds a threshold value, the controller determines that the data write mode is an intensive mode, selects the storage device, whose number of times of data write exceeds the threshold value, as a specified storage device and writes data, which are to be processed for the write command, intensively to the selected specified storage device. | 03-05-2015 |
20150067241 | Hibernation Based on Page Source - Example embodiments disclosed herein relate to hibernation. A device includes a non-volatile memory including a solid state memory and a volatile memory. The volatile memory includes a plurality of pages. One or more of the pages are caused to be stored to non-volatile memory based on whether the respective pages are sourced from the solid state memory. | 03-05-2015 |
20150067242 | INFORMATION PROCESSING DEVICE - In an information processing device, a NAND flash memory has a first area and a second area in each of which a boot code is stored. A processor expands the boot code from the NAND flash memory onto the random access memory, executes the expanded boot code, and rewrites the boot code in the first area and the boot code in the second area at different timings based on the number of times that boot is performed. A boot area setting portion sets access destination of the processor at boot to either the first area or the second area. A controller controls the boot area setting portion so that the access destination of the processor at boot is switched alternately between the first area and the second area at every predetermined number of times that boot is performed. | 03-05-2015 |
20150067243 | SYSTEM AND METHOD FOR EXECUTING MAP-REDUCE TASKS IN A STORAGE DEVICE - A system and method of providing enhanced data processing and analysis in an infrastructure for distributed computing and large-scale data processing. This infrastructure uses the Hadoop™ framework to divide an application into a large number of small fragments of work, each of which may be performed on one of a large number of compute nodes. The work may involve map tasks and reduce tasks which may be used to categorize and analyze large amounts of data in distributed systems. This infrastructure includes a cluster with a master node and a plurality of slave nodes. The slave nodes may include, or may be, intelligent solid-state drives capable of executing Map-Reduce functions. The use of intelligent solid-state drives reduces the need to exchange data with a CPU in a server. | 03-05-2015 |
20150067244 | Method and System for Migrating Data Between Flash Memory Devices - The embodiments described herein include systems, methods and/or devices that may enhance the endurance of a storage system including a storage medium. The method includes: dividing a plurality of flash memory devices into logical chunks each logical chunk including one or more flash memory blocks; and detecting a trigger condition with respect to a respective flash memory device of the plurality of flash memory devices. In response to detecting the trigger condition, the method includes: selecting one of the logical chunks of the respective flash memory device for migration in accordance with predefined selection criteria; and storing a replicated logical chunk, comprising a copy of the selected logical chunk, at a second flash memory device. The method includes: remapping an address of the selected logical chunk to a physical location of the replicated logical chunk; and decreasing a number of logical chunks associated with the respective flash memory device. | 03-05-2015 |
20150067245 | Method and System for Rebalancing Data Stored in Flash Memory Devices - The embodiments described herein include systems, methods and/or devices that may enhance the endurance of a storage system including a storage medium. The method includes: dividing a plurality of flash memory devices into logical chunks each logical chunk including one or more flash memory blocks; assigning a weight to each of the flash memory devices for a distribution algorithm, where the weight is based on at least a number of available logical chunks; and storing data in the logical chunks in accordance with the distribution algorithm. The method includes detecting a trigger condition for a respective flash memory device. In response to detecting the trigger condition, the method includes: decreasing the weight of the respective flash memory device; updating the distribution algorithm to reflect the decreased weight of the respective flash memory device; and rebalancing data stored in the plurality of flash memory devices in accordance with the updated distribution algorithm. | 03-05-2015 |
20150074327 | Active Recycling for Solid State Drive - A solid state drive and a method for providing active recycling for the solid state drive are disclosed. The solid state drive includes a plurality of blocks and each of the plurality of blocks includes a plurality of pages. The method steps include receiving a read request from a data requester; identifying at least one page containing data requested by the read request; determining whether the at least one page belongs to a block identified for active recycling; writing the at least one page to a different block when the at least one page belongs to the block identified for active recycling; and sending the at least one page to the data requester in response to the read request. | 03-12-2015 |
20150074328 | DYNAMIC MAP PRE-FETCHING FOR IMPROVED SEQUENTIAL READS OF A SOLID-STATE MEDIA - Described embodiments provide a solid-state drive (SSD) including a media controller and a solid-state media. A control processor of the media controller determines a logical address, a transfer size, and map data based on the logical address and transfer size, associated with a read request received from a host device. Based on the logical address and a sequential zone defined based on one or more previous read requests, the control processor determines whether the received read request is a sequential read. A map data pre-fetch size is adjusted based on the transfer size of the received read request and whether the received read request is a sequential read. A corresponding portion of the map data is transferred from the solid-state media to a map cache coupled to the control processor, the transferred portion having a size equal to the adjusted map data pre-fetch size. | 03-12-2015 |
20150074329 | INFORMATION PROCESSING DEVICE - A device of one embodiment includes a host device including a first memory unit and host controller, and memory device. The host controller controls input/output accesses to the first memory unit. The memory device includes a nonvolatile semiconductor memory, second memory unit, protection circuit, and device controller. The second memory unit temporarily stores data to be transferred between the first memory unit and the nonvolatile semiconductor memory. The protection circuit protects data to be transferred from the second memory unit to the first memory unit by converting the data into an incomprehensible format. The device controller switches according to a control program whether or not to protect the data by the protection circuit. | 03-12-2015 |
20150074330 | MEMORY DEVICE, INFORMATION-PROCESSING DEVICE AND INFORMATION-PROCESSING METHOD - A memory device according to an embodiment includes a non-volatile storage device, a volatile storage device that stores saved data which is saved in the host-side storage device when a first operation mode changing process is executed by the memory device, and a control unit. The control unit transmits, to the host device, a write command that is an instruction to write the saved data to the host-side storage device and the saved data, when the first operation mode changing process is executed by the memory device. | 03-12-2015 |
20150074331 | NONVOLATILE MEMORY PACKAGE AND NONVOLATILE MEMORY CHIP - A nonvolatile memory package of an embodiment includes: a data terminal configured to receive a write command for a data; a first CE terminal; a second CE terminal; a CE selection terminal; and a selector coupled to the first CE terminal and the second CE terminal. The selector outputs one of a first chip-enable signal and a second chip-enable signal based on a CE selection signal. The nonvolatile memory package of the embodiment further includes: a first nonvolatile memory chip that executes the write command for the data using the first chip-enable signal as an activate signal; and a second nonvolatile memory chip that changes an offset value for a write-destination address contained in the write command for the data based on the CE selection signal. The second nonvolatile memory chip executes the write command for the data using an output signal from the selector as an activate signal. | 03-12-2015 |
20150074332 | MEMORY CONTROLLER AND MEMORY SYSTEM - A memory controller that reads data from nonvolatile memory according to an embodiment of the present invention includes: first and second ports that receive commands; a thread executing unit that executes a first thread that is a set of processes based on the command received by the first port, and a second thread that is a set of processes based on the command received by the second port; a buffer; and a buffer managing unit that manages a first buffer area to be allotted to the first thread and a second buffer area to be allotted to the second thread, wherein the thread executing unit stores read data in the first buffer area upon executing the first thread, and stores read data in the second buffer area upon executing the second thread, and the buffer managing unit dynamically allots regions in the buffer to the first and second buffer areas. | 03-12-2015 |
20150074333 | MEMORY CONTROLLER AND MEMORY SYSTEM - According to an embodiment, an access controller refers to state information upon an erase operation, causes the erase operation to be performed on all the collection of physical blocks included in a first logical block, and causes the erase operation to be performed on a part of the collection of physical blocks included in a second logical block and does not causes the erase operation to be performed on rest of the collection of the physical blocks in the second logical block. | 03-12-2015 |
20150074334 | INFORMATION PROCESSING DEVICE - According to one embodiment, an information processing device is disclosed. The device includes a host device and a memory device. The host device includes a first memory portion to store first data and tag information corresponding to the first data, and a host controller to control input and output of data for the first memory portion. The memory device includes a nonvolatile semiconductor memory, and a device controller to control input and output of data for the nonvolatile semiconductor memory, and to transmit an input and output request for data to the host controller. In response to the device controller transmits an output request, the host controller reads the first data and the tag information from the first memory portion based on the output request, and outputs the first data and the tag information to the device controller. | 03-12-2015 |
20150074335 | MEMORY SYSTEM, CONTROLLER AND CONTROL METHOD OF MEMORY - According to one embodiment, a memory system includes non-volatile memory, a block management table that stores whether data in the non-volatile memory is valid or invalid in a unit of cluster, and a controller configured to execute compaction. In the block management table, first information related to likelihood that valid data within the block is invalidated is registered for each of the blocks. The controller is configured to select a block to be a target of the compaction based on the first information and use the selected block to execute the compaction. | 03-12-2015 |
20150074336 | MEMORY SYSTEM, CONTROLLER AND METHOD OF CONTROLLING MEMORY SYSTEM - According to one embodiment, a log information generating unit generates log information that write logs are collected for each of data of a predetermined size, wherein the write log includes a change in a physical address relative to a logical address before and after writing to a write target by an atomic write process, and a process identifier that identifies the atomic write process. In a case where an interruption occurs in the atomic write process, and a memory system recovers from the interruption, a restoration processing unit extracts a first process identifier of the interrupted atomic write process, and restores address conversion information to a state before the atomic write process by using the write logs having the first process identifier. | 03-12-2015 |
20150074337 | STORAGE DEVICE AND DATA PROCESSING METHOD THEREOF - A data storage device which exchanges multi-stream data with a host includes a nonvolatile memory device; a buffer memory configured to temporarily store data to be stored in the nonvolatile memory device or data read from the nonvolatile memory device; and a storage controller configured to receive from the host an access command for accessing segments of the multi-stream data, the accessing including reading the segments of the multi-stream data from or writing the segments of the multi-stream data to the nonvolatile memory device, wherein the storage controller is configured to store the access-requested segments in the buffer memory, the access-requested segments being the segments of data for which access is requested in the access command, the multi-stream data including a plurality of data streams that correspond respectively to a plurality of multi-stream indexes, the first multi-stream index being one of a plurality of multi-stream indexes. | 03-12-2015 |
20150074338 | ASCERTAINING COMMAND COMPLETION IN FLASH MEMORIES - Ascertaining command completion in flash memories is disclosed. An exemplary aspect includes eliminating the software lock and the outstanding requests variable and replacing them with a transfer request completion register. The transfer request completion register may be mapped to the universal flash storage (UFS) Transfer Protocol (UTP) Transfer Request List (UTRL) slots. The controller of the host—a hardware component—may set the bit in the transfer request completion register on transfer request completion at the same time the doorbell register is cleared. After this bit has been read, the bit in the transfer request completion register is cleared. | 03-12-2015 |
20150074339 | HYBRID MAIN MEMORY USING A FINE-GRAIN LEVEL OF REMAPPING - Accessing a hybrid memory using a translation line is disclosed. The hybrid memory comprises a first portion. The translation line maps a first physical memory address to a first line in the first portion. Said mapping provides an indication that the first line is not immediately accessible in the first portion. | 03-12-2015 |
20150074340 | ELECTRONIC DEVICE DATA DISTRIBUTION - A non-transitory computer-readable storage medium may include instructions that cause a system to perform operations, the operations may include receiving an operation associated with data and managing storage of the data on a first storage medium of an electronic device and in a cache on a second storage medium of the electronic device based on the operation and a cache policy. The cache policy may be based on one or more characteristics of the data that include a duration since a previous access of the data. | 03-12-2015 |
20150074341 | MEMORY SYSTEM INCLUDING KEY-VALUE STORE - According to one embodiment, a memory system including a key-value store containing key-value data as a pair of a key and a value corresponding to the key, includes an interface, a memory block, an address acquisition circuit and a controller. The interface receives a data write/read request or a request based on the key-value store. The memory block has a data area for storing data and a metadata table containing the key-value data. The address acquisition circuit acquires an address in response to input of the key. The controller executes the data write/read request for the memory block, and outputs the address acquired to the memory block and executes the request based on the key-value store. The controller outputs the value corresponding to the key via the interface. | 03-12-2015 |
20150074342 | METHOD FOR MANAGING STORAGE SYSTEM USING FLASH MEMORY, AND COMPUTER - To facilitate the management of a storage system that uses a flash memory as a storage area. A controller of the storage system provided with a flash memory chip manages a surplus capacity value of the flash memory chip, and transmits a value based on the surplus capacity value to a management server, on the basis of at least one of a definition of a parity group, a definition of an internal LU, and a definition of a logical unit. The management server displays a state of the storage system by using the received value based on the surplus capacity value. | 03-12-2015 |
20150074343 | LOGIC DEVICE - A logic device for communicating with a memory package with a first protocol, communicating with a memory controller with a second protocol, and for performing a protocol conversion between the first and the second protocol. | 03-12-2015 |
20150074344 | ADAPTIVE MEMORY SYSTEM FOR ENHANCING THE PERFORMANCE OF AN EXTERNAL COMPUTING DEVICE - An adaptive memory system is provided for improving the performance of an external computing device. The adaptive memory system includes a single controller, a first memory type (e.g., Static Random Access Memory or SRAM), a second memory type (e.g., Dynamic Random Access Memory or DRAM), a third memory type (e.g., Flash), an internal bus system, and an external bus interface. The single controller is configured to: (i) communicate with all three memory types using the internal bus system; (ii) communicate with the external computing device using the external bus interface; and (iii) allocate cache-data storage assignment to a storage space within the first memory type, and after the storage space within the first memory type is determined to be full, allocate cache-data storage assignment to a storage space within the second memory type. | 03-12-2015 |
20150074345 | Cache Management Method and Apparatus for Non-Volatile Storage Device - Embodiments of the present invention disclose a method and apparatus of cache management for a non-volatile storage device. The method embodiment includes: determining a size relationship between a capacity sum of a clean page subpool and a dirty page subpool and a cache capacity; determining, when the capacity sum is equal to the cache capacity, whether identification information of a to-be-accessed page is in a history list of clean pages or a history list of dirty pages; and when it is determined that the identification information of the to-be-accessed page is in the history list of clean pages, adding a first adjustment value to a clean page subpool capacity threshold; and when the identification information of the to-be-accessed page is in the history list of dirty pages, subtracting a second adjustment value from the clean page subpool capacity threshold. | 03-12-2015 |
20150081948 | CONTROLLING DATA STORAGE INPUT/OUTPUT REQUESTS - Controlling data storage input/output requests is described, for example, to apply a policy to an end-to-end flow of data input/output requests between at least one computing entity and at least one store. In various examples a plurality of queues are configured at one or more stages of the end-to-end flow and controlled to adhere to a policy. In examples, each stage has a control interface enabling it to receive and execute control instructions from a controller which may be centralized or distributed. For example, the control instructions comprise queuing rules and/or queue configurations. In various examples queues and queuing rules are dynamically created and revised according to feedback about any of: flow behavior, changes in policy, changes in infrastructure or other factors. In examples, high level identifiers of the flow endpoints are resolved, on a per stage basis, to low level identifiers suitable for use by the stage. | 03-19-2015 |
20150081949 | APPARATUS AND METHOD OF USING DUMMY DATA WHILE STORING DATA AT A MULTI-BIT STORAGE ELEMENT - A storage device includes non-volatile memory and a controller. A method performed in the data storage device includes receiving, at the controller, first data and second data to be stored at the non-volatile memory. The method further includes sending, from the controller, the first data, the second data, and dummy data to the non-volatile memory to be stored at respective logical pages of a single physical page in the non-volatile memory. The single physical page includes multiple storage elements that are programmable into multiple voltage states according to a mapping of bits to states. The dummy data prevents a storage element of the single physical page from being programmed to a particular voltage state of the multiple voltage states. | 03-19-2015 |
20150081950 | MEMORY SYSTEM AND INFORMATION PROCESSING DEVICE - A memory system includes a non-volatile memory which is configured in units of erasable blocks each having a first size and units of pages each having a second size within each block, a page size identification information storage unit configured to store a third size that is smaller than the second size, and a control unit configured to convert a first address designated in a command received by the memory system into a second address. The first address specifies a page number of pages having the third size and the second address specifies a page number of pages having the second size. | 03-19-2015 |
20150081951 | Memory card access device, control method thereof, and memory card access system - The present invention discloses a memory card access device, the control method thereof and a memory card access system. Said device comprises: a memory card interface circuit to generate card-read data according to a card-read signal or generate a card-writing signal according to card-writing data; a host interface circuit to generate host-read data according to a host-read signal or generate the host-writing signal according to host-writing data; and a control circuit, coupled to the memory card and host interface circuits respectively, operable to generate the host-writing data by processing the card-read data according to a predetermined cache protocol or generating the card-writing data by processing the host-read data according to the predetermined cache protocol, so as to treat a memory card as a cache device. | 03-19-2015 |
20150081952 | APPARATUS AND METHOD OF USING DUMMY DATA WHILE STORING DATA AT A MULTI-BIT STORAGE ELEMENT - A storage device includes a controller and a non-volatile memory that includes a three-dimensional (3D) memory. A method performed in the data storage device includes receiving, at the controller, first data and second data to be stored at the non-volatile memory. The method further includes sending, from the controller, the first data, the second data, and dummy data to the non-volatile memory to be stored at respective logical pages of a single physical page in the non-volatile memory. The single physical page includes multiple storage elements that are programmable into multiple voltage states according to a mapping of bits to states. The dummy data prevents a storage element of the single physical page from being programmed to a particular voltage state of the multiple voltage states. | 03-19-2015 |
20150081953 | SSD (SOLID STATE DRIVE) DEVICE - The present invention provides an SSD device that uses non-volatile memory as a cache to contribute to reduced power consumption. | 03-19-2015 |
20150081954 | STORAGE SYSTEM COMPRISING FLASH MEMORY, AND STORAGE CONTROL METHOD - A storage system comprises a plurality of flash packages comprising a plurality of flash chips, and a storage controller for receiving a first write request from a higher-level apparatus and sending a second write request of write data based on data conforming to this first write request to a write-destination flash package, and demonstrates a capacity virtualization function for causing a storage capacity to appear larger than an actual storage capacity for the higher-level apparatus, and for configuring a storage space using page units. The storage system generates a second VOL (logical volume) based on a first VOL, manages a plurality of VOLs comprising the first VOL and one or more second VOLs generated based on the first VOL as a VOL group, and allocates the same page to areas of the same address of the plurality of VOLs configuring the VOL group. | 03-19-2015 |
20150081955 | ACKNOWLEDGEMENT-LESS PROTOCOL FOR SOLID STATE DRIVE INTERFACE - The present disclosure relates to methods and systems for performing operations in a communications protocol. An example method can include submitting, from a device, a request for a queue entry representing a command from a host comprising a request for data stored at a device memory location; receiving the command from the host; and executing the command. An example method can also include selecting a bit string representing whether a requested data stream has been received, and storing the bit string into a memory buffer portion to mark the buffer portion. The method can include receiving, into the memory buffer, the stream. The method can include retrieving contents of the buffer portion, and determining whether the contents contain the bit string. If so, the method can include determining that portions of the stream have not been received. Otherwise, the method can include determining that the stream has been received. | 03-19-2015 |
20150081956 | DOORBELL-LESS PROTOCOL FOR SOLID STATE DRIVE INTERFACE - The present disclosure relates to methods and systems for performing operations in a communications protocol. An example method can include submitting, from a device, a request for a queue entry representing a command from a host comprising a request for data stored at a device memory location; receiving the command from the host; and executing the command. An example method can also include selecting a bit string representing whether a requested data stream has been received, and storing the bit string into a memory buffer portion to mark the buffer portion. The method can include receiving, into the memory buffer, the stream. The method can include retrieving contents of the buffer portion, and determining whether the contents contain the bit string. If so, the method can include determining that portions of the stream have not been received. Otherwise, the method can include determining that the stream has been received. | 03-19-2015 |
20150081957 | OUTPUTTING A PARTICULAR DATA QUANTIZATION FROM MEMORY - The present disclosure includes methods, devices, and systems for outputting data particular quantization of data from memory devices and systems. Outputting data particular quantization of data can include enabling a particular one of a plurality of different quantizations of data. The particular one of the plurality of quantizations of data can then be output. | 03-19-2015 |
20150081958 | METHOD FOR BACKING UP DATA IN A CASE OF POWER FAILURE OF STORAGE SYSTEM, AND STORAGE SYSTEM CONTROLLER - The present invention discloses a method for backing up data in a case of a power failure of a storage system including: when a power failure is detected, acquiring current refresh progress of a buffer in a storage system, an address, in the buffer, of data that is in the buffer and needs to be backed up to a non-volatile memory in the storage system, and a first time required for backing up the data; calculating, according to the current refresh progress of the buffer and the address of the data in the buffer, a second time for which the data can at least keep being not lost since a last refresh; and stopping refreshing the buffer, and backing up the data to the non-volatile memory, if the second time is greater than the first time. | 03-19-2015 |
20150081959 | MEDICAL DATA COLLECTION APPARATUS - A physiological data collection device obtains physiological data from a subject interface on a subject. The physiological data collection device includes a data connector such as a USB connector for connecting directly to a computer. When the physiological data collection device is connected to the computer, the physiological data is uploaded to a remote data processing center for computer-based analysis and review by a medical professional. A report can be provided to the subject based on the analysis and review. When the subject interface is physically connected to the physiological data collection device, the data connector is prevented from being connected to an external device such as the computer. | 03-19-2015 |
20150081960 | MEMORY DEVICE AND OPERATING METHOD THEREOF - The invention provides a memory device. The memory device includes a flash memory, a memory, and a controller. The flash memory includes a plurality of blocks for data storage. The memory stores an address mapping table recording relationships between logical addresses and physical addresses of the blocks therein. The controller divides the address mapping table stored in the memory to a plurality of mapping table units, updates relationships between the logical addresses and the physical addresses stored in the mapping table units, determines whether data access performed to the flash memory fulfills the conditions of a specific requirement, and when the data access fulfills the conditions of the specific requirement, the controller selects a target mapping table unit from the mapping table units, and stores the target mapping table unit and a corresponding time stamp as a mapping table unit data to the flash memory. | 03-19-2015 |
20150081961 | METHOD AND DEVICE FOR IDENTIFYING INFORMATION FOR CHIP-LEVEL PARALLEL FLASH MEMORY - The present invention relates to an information identifying algorithm, and more particularly, to a method and device for identifying write operation information transmitted from a file system to a page-set or block-set type flash memory by utilizing an attribute information page-set buffer and a user information page-set buffer. In order to achieve such an object, the present invention includes a buffering layer for efficiently re-configuring write operation information from a file system to a page-set or block-set type flash memory. The device for identifying write operation information according to one embodiment of the present invention includes: a size determination unit; a logical address determination unit; an attribute information page-set buffer; a user information page-set buffer; a partial user information page-set buffer; a full page-set determination unit; and a session end determination unit. | 03-19-2015 |
20150081962 | CACHE MEMORY DEVICE AND DATA PROCESSING METHOD OF THE DEVICE - A cache memory device is provided. The cache memory device includes a memory including a first cache memory region and a second cache memory region, and a control block. The control block determines a type of data to be received. The control block also performs at least one of transmitting a head of received data to a first cache memory region, transmitting a body of the received data to a second cache memory region and transmitting a tail of the received data to the first cache memory region based on the type of the data to be received. | 03-19-2015 |
20150089118 | METHODS, SYSTEMS, AND COMPUTER READABLE MEDIA FOR PARTITION AND CACHE RESTORE - Methods, systems, and computer readable media for partition and cache restore are disclosed. According to one aspect, a method for partition and cache restore includes, in a computing platform having a mass storage device and a non-volatile cache storage device that operates as a cache for the mass storage device: providing, in a first location within the mass storage device, a first image of data; providing, in a second location within the mass storage device, a second image of data; copying the first image of data from the first location within the mass storage device to a third location within the mass storage device; and copying the second image of data from the second location within the mass storage device into the non-volatile cache storage device. | 03-26-2015 |
20150089119 | COMMAND EXECUTION USING EXISTING ADDRESS INFORMATION - Method and apparatus for managing data in a memory, such as a flash memory. In accordance with some embodiments, a memory module has a plurality of solid-state non-volatile memory cells. A controller communicates a first command having address information and a first operation code. The first operation code identifies a first action to be taken by the memory module in relation to the address information. The controller subsequently communicates a second command having a second operation code without corresponding address information. The memory module takes a second action identified by the second command using the address information from the first command. | 03-26-2015 |
20150089120 | REFRESH OF DATA STORED IN A CROSS-POINT NON-VOLATILE MEMORY - Embodiments including systems, methods, and apparatuses associated with refreshing memory cells are disclosed herein. In embodiments, a memory controller may be configured to perform a read operation on one or more memory cells in a cross-point non-volatile memory such as a phase change memory (PCM). The one or more memory cells may have voltage values respectively set to a first threshold voltage or a second threshold voltage. Based on the read, the memory controller may identify the memory cells in the cross-point non-volatile memory that are set to the second threshold voltage, and refresh the voltage values of those cells without altering the voltage values of the memory cells in the cross-point non-volatile memory that are set to the first threshold voltage. Other embodiments may be described or claimed. | 03-26-2015 |
20150089121 | Managing A Cache On Storage Devices Supporting Compression - Flash memory on a flash memory device is virtualized using compression that is native to the flash memory device. Through compression, the flash memory device is used to logically store more data in a virtual address space that is larger than the physical address space of the flash memory device. Physical storage capacity of a flash memory device may prevent further storage of data even when the virtual address space is not fully populated. Because compressibility may vary, the extent to which the virtual address space may be populated before physical storage capacity is reached varies. The approaches for virtual memory described herein rely on the memory device client to monitor when this point is reached. In addition, the memory device client is responsible for freeing space as needed to accommodate subsequent requests to store data in the flash memory. | 03-26-2015 |
20150089122 | APPARATUS, CONTROL APPARATUS, CONTROL METHOD AND STORAGE MEDIUM - An apparatus, when a storage unit is initialized, writes dummy data to an area of the storage unit, and when actual data is written to the storage unit, releases the dummy data written in the area of the storage unit, and writes the actual data in the released area, and also when the actual data is deleted from the storage unit, writes dummy data to an area in which the actual data is written. | 03-26-2015 |
20150089123 | COMPUTER SYSTEM WITH PHYSICALLY-ADDRESSABLE SOLID STATE DISK (SSD) AND A METHOD OF ADDRESSING THE SAME - A storage system includes a Central Processing Unit (CPU) that has a physically-addressed solid state disk (SSD), addressable using physical addresses associated with user data and provided by a host. The user data is to be stored in or retrieved from the physically-addressed SSD in blocks. Further, a non-volatile memory module is coupled to the CPU and includes flash tables used to manage blocks in the physically addressed SSD. The flash tables have tables that are used to map logical to physical blocks for identifying the location of stored data in the physically addressed SSD. The flash tables are maintained in the non-volatile memory modules thereby avoiding reconstruction of the flash tables upon power interruption. | 03-26-2015 |
20150089124 | DATA ACCESSING METHOD FOR FLASH MEMORY STORAGE DEVICE HAVING DATA PERTURBATION MODULE, AND STORAGE SYSTEM AND CONTROLLER USING THE SAME - A data accessing method, and a storage system and a controller using the same are provided. The data accessing method is suitable for a flash memory storage system having a data perturbation module. The data accessing method includes receiving a read command from a host and obtaining a logical block to be read and a page to be read from the read command. The data accessing method also includes determining whether a physical block in a data area corresponding to the logical block to be read is a new block and transmitting a predetermined data to the host when the physical block corresponding to the logical block to be read is a new block. Thereby, the host is prevented from reading garbled code from the flash memory storage system having the data perturbation module. | 03-26-2015 |
20150095550 | GENERATING RANDOM NUMBERS UTILIZING ENTROPIC NATURE OF NAND FLASH MEMORY MEDIUM - Methods and apparatus related to generating random numbers utilizing the entropic nature of NAND flash memory medium are described. In one embodiment, a data pattern is written to a portion of a non-volatile memory device and is subsequently read multiple times. Based on the read operations, at least one bit is marked for random number generation based at least partially on comparison of a number of flips by the at least one bit and a threshold value. Other embodiments are also disclosed and claimed. | 04-02-2015 |
20150095551 | VOLATILE MEMORY ARCHITECUTRE IN NON-VOLATILE MEMORY DEVICES AND RELATED CONTROLLERS - In some embodiments, one register of a non-volatile memory can be used for read operations and another register of the non-volatile memory can be used for programming operations. For instance, a cache register of a NAND flash memory can be used in connection with read operations and a data register of the NAND flash memory can be used in connection with programming operations. Data registers of a plurality of non-volatile memory devices, such as NAND flash memory devices, can implement a distributed volatile cache (DVC) architecture in a managed memory device, according to some embodiments. According to certain embodiments, data can be moved and/or swapped between registers to perform certain operations in the non-volatile memory devices without losing the data stored while other operations are performed. | 04-02-2015 |
20150095552 | MEMORY SYSTEM FOR MIRRORING DATA - A memory system is disclosed, which may include a memory unit of a first type, susceptible to loss of data from corrupting events, and a memory unit of a second type, less susceptible to loss of data from corrupting events than the memory unit of the first type, and a mirrored memory interface (MMI). The MMI may be coupled to a memory controller, the memory unit of the first type, and the memory unit of the second type. The MMI may, in response to a memory controller write command, receive data from the memory controller and write the data to the memory unit of the first type and to the memory unit of the second type. The MMI may also, in response to a memory controller read command, read data from the memory unit of the first type and send the data to the memory controller. | 04-02-2015 |
20150095553 | SELECTIVE SOFTWARE-BASED DATA COMPRESSION IN A STORAGE SYSTEM BASED ON DATA HEAT - In a data storage system, in response to receipt from a processor system of a write input/output operation (IOP) including an address and data, a storage controller of the data storage system determines whether or not the address is a hot address that is more frequently accessed. In response to determining that the address is a hot address, the storage controller stores the data in the data storage system in uncompressed form. In response to determining that the address is not a hot address, the storage controller compresses the data to obtain compressed data and stores the compressed data in the data storage system. | 04-02-2015 |
20150095554 | STORAGE PROCESSOR MANAGING SOLID STATE DISK ARRAY - A method of writing to one or more solid state disks (SSDs) employed by a storage processor includes receiving a command, creating sub-commands from the command based on a granularity, and assigning the sub-commands to the SSDs independently of the command thereby causing striping across the SSDs. | 04-02-2015 |
20150095555 | METHOD OF THIN PROVISIONING IN A SOLID STATE DISK ARRAY - A method of thin provisioning in a storage system is disclosed. The method includes communicating to a user a capacity of a virtual storage, the virtual storage capacity being substantially larger than that of a storage pool. Further, the method includes assigning portions of the storage pool to logical unit number (LUN) logical block address (LBA)-groups only when the LUN LBA-groups are being written to and maintaining a mapping table to track the association of the LUN LBA-groups to the storage pool. | 04-02-2015 |
20150095556 | MEMORY SYSTEM - A memory system includes a first memory chip, a second memory chip, and a memory controller. The first memory chip and the second memory chip are connected to the memory controller via a plurality of data lines including a first data line and a second data line. The first memory chip is configured to outputs status information via the first data line to the memory controller. The second memory chip is configured to output status information via the second data line to the memory controller at the same time as the first memory chip. | 04-02-2015 |
20150095557 | SEMICONDUCTOR APPARATUS AND SYSTEM - A semiconductor apparatus and system are provided. The semiconductor apparatus includes a host core configured to drive at least one device drive and a solid state drive (SSD), a flash interface configured to interface with the host core and the SSD, and an internal bus configured to transmit signals between the host core and the flash interface, wherein the host core, the flash interface, and the internal bus are disposed on a single chip substrate, and the SSD is not disposed on the single chip substrate. | 04-02-2015 |
20150095558 | STORAGE AND PROGRAMMING METHOD THEREOF - A program method of a storage device which includes at least one nonvolatile memory device and a memory controller to control the at least one nonvolatile memory device, the program method comprising: performing a first normal program operation to store first user data in a memory block; detecting, at the memory controller, a first event; performing a dummy program operation to store dummy data in at least one page of the memory block in response to the detection of the first event; and performing a second normal program operation to store second user data in the memory block after the dummy program operation, dummy program operations being operations in which random data is programmed into the memory block, normal program operations being operations in which data other than random data is programmed in the memory block. | 04-02-2015 |
20150095559 | PERFORMANCE IMPROVEMENT OF A CAPACITY OPTIMIZED STORAGE SYSTEM INCLUDING A DETERMINER - A system for storing data comprises a performance storage unit and a performance segment storage unit. The system further comprises a determiner. The determiner determines whether a requested data is stored in the performance storage unit. The determiner determines whether the requested data is stored in the performance segment storage unit in the event that the requested data is not stored in the performance storage unit. | 04-02-2015 |
20150095560 | PROGRAM-DISTURB MANAGEMENT FOR PHASE CHANGE MEMORY - Subject matter disclosed herein relates to a memory device, and more particularly to read or write performance of a phase change memory. | 04-02-2015 |
20150095561 | PROMOTION OF PARTIAL DATA SEGMENTS IN FLASH CACHE - For efficient track destage in secondary storage in a more effective manner, for temporal bits employed with sequential bits for controlling the timing for destaging the track in a primary storage, a preference of movement to lower speed cache level is implemented based on at least one of an amount of holes and a data heat metric. If a first bit has at least one of a lower amount of holes and a hotter data heat metric, it is moved to the lower speed cache level ahead of a second bit that has at least one of a higher amount of holes and a cooler data heat. If the first bit has a hotter data heat and greater than a predetermined number of holes, the first bit is discarded. | 04-02-2015 |
20150095562 | METHOD FOR MANAGING A MEMORY APPARATUS - A memory apparatus includes at least one NV memory element, which includes a plurality of blocks. A method for managing the memory apparatus includes: receiving a first access command from a host; analyzing the first access command to obtain a first host address; linking the first host address to a first page of the physical block; receiving a second access command from the host; analyzing the second access command to obtain a second host address; linking the second host address to a second page of the physical block; recording a valid/invalid page count of the physical block corresponding to accessing pages of the physical block; and determining whether to erase a portion of the blocks according to the valid/invalid page count. A difference value of the first host address and the second host address is greater than a number of pages of the physical block. | 04-02-2015 |
20150100719 | DATA BACKUP METHOD AND DEVICE THEREOF - A data backup method and device for a NAND storage unit are provided. The method includes determining whether a portion of data stored in the NAND storage unit is critical data in compliance with a predetermined backup rule, and backing up the critical data if the data is the critical data. Through the provided method and device, the present invention solves the problem of wasting the storage space caused by backing up the data without distinguish the data. | 04-09-2015 |
20150100720 | APPARATUS, SYSTEM, AND METHOD FOR DATA BLOCK USAGE INFORMATION SYNCHRONIZATION FOR A NON-VOLATILE STORAGE VOLUME - An apparatus, system, and method are disclosed for data block usage information synchronization for a non-volatile storage volume. The method includes referencing first data block usage information for data blocks of a non-volatile storage volume managed by a storage manager. The first data block usage information is maintained by the storage manager. The method also includes synchronizing second data block usage information managed by a storage controller with the first data block usage information maintained by the storage manager. The storage manager maintains the first data block usage information separate from second data block usage information managed by the storage controller. | 04-09-2015 |
20150100721 | STORAGE SYSTEM AND METHOD OF CONTROL FOR STORAGE SYSTEM - The storage system includes a plurality of storage devices and a storage controller. The storage controller stores a data request quantity indicating the data quantity of write data written to the target area in a specific period, and estimates, based on the quantity of request data and relationship information received from storage devices, the estimated data quantity written to the nonvolatile semiconductor memory chips based on the write data written to the target area in the specific period. The storage controller selects a second logical storage area with an estimated data quantity less than an estimated data quantity for the first logical storage area and assigned to a storage device different from a storage device assigned to the first logical storage area, and migrates the first data stored in the first logical storage area to the second logical storage area. | 04-09-2015 |
20150106547 | DISTRIBUTED MEMORY SYSTEMS AND METHODS - Apparatuses and methods are disclosed herein, including those that operate to receive memory requests from a processor over a high-speed communication interface and distribute the requests among a plurality of memory storage devices over lower-speed communication interfaces. | 04-16-2015 |
20150106548 | Managed-NAND With Embedded Random-Access Non-Volatile Memory - Systems and methods embed a random-access non-volatile memory array in a managed-NAND system to execute the boot code or other time-sensitive applications. By embedding this random-access non-volatile memory in the managed-NAND system, either on the memory controller chip or as a separate chip within the managed-NAND system package, an application may be read with fast initial access time, alleviating the slow access time limitations of NAND Flash technology. Depending on the size of the application, the system may be configured to read the whole application content or only a time-critical portion from this embedded random-access non-volatile memory array. | 04-16-2015 |
20150106549 | Robust Data Replication - Disclosed is a system for replicating data. The system may comprise a plurality of nodes preferably organised in groups with one of the nodes acting as a coordinator node. The nodes are configured to receive write requests from an external server and to apply these write requests to a data storage source of the data storage system. The write requests typically belong to a batch of independent write actions identified by a batch sequence number. Each node stores the write request in non-volatile memory with the coordinator node monitoring which batches are secured in their entirety in non-volatile memory. The coordinator node authorises all other nodes to sequentially replicate the write requests in their non-volatile memory to the data storage source for all writes up to the highest batch sequence number for which all writes have been secured in non-volatile memory. | 04-16-2015 |
20150106550 | INFORMATION PROCESSING APPARATUS, METHOD OF CONTROLLING THE SAME AND STORAGE MEDIUM - An information processing apparatus determines, when data is written to a semiconductor storage including a plurality of flash memories, whether or not the data to be written is specific data (data associated with the complete erasure) for which it is set that unnecessary data relating to the data is made to be erasable so that the unnecessary data does not remain in the semiconductor storage. In a case where it is determined that the data to be written is not the specific data, the information processing apparatus performs data write processing in a state where an interleave is enabled. Meanwhile, in a case where it is determined that the data to be written is not the specific data, the information processing apparatus performs data write processing in a state where the interleave is disabled. | 04-16-2015 |
20150106551 | SEMICONDUCTOR DEVICE AND OPERATING METHOD THEREOF - A semiconductor device remaps the relationship between logical addresses and physical addresses of a semiconductor memory device at each first interval. The semiconductor device may include a wear leveling controller configured to select a first physical address of the semiconductor memory device to remap a logical address corresponding to the first physical address of the semiconductor memory device to a second physical address of the semiconductor memory device, and to adjust the first interval. | 04-16-2015 |
20150106552 | METHOD FOR READING A DATA BLOCK OF A NONVOLATILE MEMORY OF A CONTROL UNIT - A method for reading a data block of a nonvolatile memory of a processing unit, the nonvolatile memory being subdivided into sectors; the sectors being written to consecutively in each case from a sector beginning to a sector end with different versions of different data blocks; a current version of a data block being written to a current position in a current sector; in a cache memory, for each data block, an entry being present that characterizes the respective data block. | 04-16-2015 |
20150106553 | SOLID STATE DRIVE CARD AND AN ELECTRONIC SYSTEM INCLUDING THE SAME - Provided are a solid state drive (SSD) card and an electronic system including the same. The electronic system includes a main board to which an input device and an output device are connected. A central processing unit (CPU) and a platform hub (PH) are provided on the main board. The PH is electrically connected to a hybrid interface socket. The hybrid interface socket includes a secure digital (SD) card interface and a non-SD card interface. When the SSD card and the electronic system including the same are used, a storage capacity may be conveniently upgraded to a higher capacity. Also, since the hybrid interface socket is provided in place of a conventional SD card socket, additional space is not required and thus space may be efficiently used. | 04-16-2015 |
20150106554 | Regrouping and Skipping Cycles in Non-Volatile Memory - A non-volatile memory system utilizes multiple programming cycles to write units of data, such as a logical page of data, to a non-volatile memory array. User data is evaluated before writing to determine whether programming can be skipped for bay addresses. The system determines whether programming can be skipped for an initial set of bay groups. If a bay group cannot be skipped, the system determines whether the bay group includes individual bays that may be skipped. Bays are regrouped into new bay groups to reduce the number of BAD cycles during programming. Independent column addressing for multiple bays within a bay group is provided. During a column address cycle, a separate column address is provided to the bays to select different columns for programming within each bay. By simultaneously programming multiple column addresses during a single column address cycle, the system may skip programming for some column address cycles. | 04-16-2015 |
20150106555 | NONVOLATILE SEMICONDUCTOR STORAGE SYSTEM - A nonvolatile semiconductor storage system has multiple nonvolatile semiconductor storage media, a control circuit having a media interface group (one or more interface devices) coupled to the multiple nonvolatile semiconductor storage media, and multiple switches. The media interface group and the multiple switches are coupled via data buses, and each switch and each of two or more nonvolatile chips are coupled via a data bus. The switch is configured so as to switch a coupling between a data bus coupled to the media interface group and a data bus coupled to any of multiple nonvolatile chips that are coupled to this switch. The control circuit partitions write-target data into multiple data elements, switches a coupling by controlling the multiple switches, and distributively sends the multiple data elements to multiple nonvolatile chips. | 04-16-2015 |
20150106556 | Endurance Translation Layer (ETL) and Diversion of Temp Files for Reduced Flash Wear of a Super-Endurance Solid-State Drive - A flash drive has increased endurance and longevity by reducing writes to flash. An Endurance Translation Layer (ETL) is created in a DRAM buffer and provides temporary storage to reduce flash wear. A Smart Storage Switch (SSS) controller assigns data-type bits when categorizing host accesses as paging files used by memory management, temporary files, File Allocation Table (FAT) and File Descriptor Block (FDB) entries, and user data files, using address ranges and file extensions read from FAT. Paging files and temporary files are never written to flash. Partial-page data is packed and sector mapped by sub-sector mapping tables that are pointed to by a unified mapping table that stores the data-type bits and pointers to data or tables in DRAM. Partial sectors are packed together to reduce DRAM usage and flash wear. A spare/swap area in DRAM reduces flash wear. Reference voltages are adjusted when error correction fails. | 04-16-2015 |
20150106557 | Virtual Memory Device (VMD) Application/Driver for Enhanced Flash Endurance - A Virtual-Memory Device (VMD) driver and application execute on a host to increase endurance of flash memory attached to a Super Enhanced Endurance Device (SEED) or Solid-State Drive (SSD). Host accesses to flash are intercepted by the VMD driver using upper and lower-level filter drivers and categorized as data types of paging files, temporary files, meta-data, and user data files, using address ranges and file extensions read from meta-data tables. Paging files and temporary files are optionally written to flash. Full-page and partial-page data are grouped into multi-page meta-pages by data type before storage by the SSD. Ramdisks and caches for storing each data type in the host DRAM are managed and flushed to the SSD by the VMD driver. Write dates are stored for pages or blocks for management functions. A spare/swap area in DRAM reduces flash wear. Reference voltages are adjusted when error correction fails. | 04-16-2015 |
20150106558 | SEMICONDUCTOR DEVICE AND DATA PROCESSING METHOD - A semiconductor device has: as security states to which the nonvolatile memory device can transition, an unprotected state in which, when secret information is not set in the nonvolatile memory device, rewriting the nonvolatile memory device is permitted, and reading the stored information is permitted; a protection unlocked state in which, when the secret information is set in the nonvolatile memory device, rewriting the nonvolatile memory device is permitted on condition that a result of authentication using the secret information is correct, and reading the stored information is permitted; and a protection locked state in which, when the secret information is set in the nonvolatile memory device, rewriting the nonvolatile memory device is inhibited until correctness as a result of authentication using the secret information is confirmed, and reading the stored information is inhibited under a predetermined condition. | 04-16-2015 |
20150106559 | NONVOLATILE STORAGE DEVICE AND OPERATING SYSTEM (OS) IMAGE PROGRAM METHOD THEREOF - A nonvolatile storage device in accordance with the inventive concepts includes a nonvolatile memory device comprising a first memory area, a second memory area, and a memory controller. The memory controller includes a first register configured to store reliable mode information, and a second register configured to store operating system (OS) image information. The memory controller is configured to receive a command from a host based on the reliable mode information; determine whether the command is a write request for an OS image and whether OS image information accompanying the command matches the OS image information stored in the second register; write the OS image to the first memory area if the OS image information accompanying the command matches the OS image information stored in the second register, and block data migration of the OS image from the first memory area to the second memory area. | 04-16-2015 |
20150113204 | DATA STORAGE DEVICE AND COMPUTING SYSTEM WITH THE SAME - A data storage device is in communication with a host through a bus. The data storage device includes a storage medium and a controlling unit. The controlling unit is connected with the host and the storage medium for receiving an analysis data, or storing a write data into the storage medium or retrieving a read data from the storage medium to the host according to a command from the host. The controlling unit includes an arithmetic logic unit. The arithmetic logic unit has a built-in algorithm for analyzing and processing the analysis data, the write data or the read data, thereby generating an analysis result. Moreover, the algorithm may be updated or expanded by the host. | 04-23-2015 |
20150113205 | Systems and Methods for Latency Based Data Recycling in a Solid State Memory System - Systems and method relating generally to solid state memory, and more particularly to systems and methods for recycling data in a solid state memory. | 04-23-2015 |
20150113206 | Biasing for Wear Leveling in Storage Systems - The various implementations described herein include systems, methods and/or devices used to enable biasing for wear leveling in storage systems. In one aspect, the method includes (1) determining, for each erase unit of a plurality of erase units in the storage medium, an age metric, (2) determining a representative age metric of the plurality of erase units, (3) for each respective erase unit of the plurality of erase units, biasing a respective garbage collection control metric for the respective erase unit in accordance with the age metric of the respective erase unit in relation to the representative age metric of the plurality of erase units to generate an adjusted garbage collection control metric for the respective erase unit, and (4) performing garbage collection for the storage medium in accordance with the adjusted garbage collection control metrics of the plurality of erase units. | 04-23-2015 |
20150113207 | OPERATING METHOD OF DATA STORAGE DEVICE - A method for operating a data storage device includes grouping memory blocks of a nonvolatile memory device based on program counts or erase counts of the respective memory blocks, into a first group and a second group, which has program counts or erase counts larger than the first group, performing a reprogram operation for memory blocks included in the first group, and performing a read retry operation for a selected memory cell of a memory block included in the first group or the second group, based on a read retry voltage set for each of the first group and the second group, when an error of data read from the selected memory cell is not correctable. | 04-23-2015 |
20150113208 | STORAGE APPARATUS, CACHE CONTROLLER, AND METHOD FOR WRITING DATA TO NONVOLATILE STORAGE MEDIUM - According to one embodiment, a storage apparatus includes a first storage medium which is nonvolatile, a second storage medium which is nonvolatile, a cache controller, and a main controller. An access speed of the second storage medium is lower, and a storage capacity of the second storage medium is larger than the first storage medium. The main controller controls the cache controller and accesses the second storage medium based on an access request from a host apparatus. The cache controller writes, in a multiplexed manner, data to be stored in the first storage medium to at least two areas in which deterioration of storage performance has been detected based on a result of access to the first storage medium. | 04-23-2015 |
20150113209 | EMBEDDED SYSTEM CONTROLLER - An embedded system controller comprises a main chip and a flash memory. The main chip comprises: a bus; a random access memory; and a storage control module which is configured to copy program data to be used to the random access memory from the flash memory, and also configured to read required program data from the random access memory when receiving a read access request from the bus and write program data to be written into the random access memory and the flash memory when receiving a write access request from the bus. The present application can allow the main chip of an embedded system controller to be manufactured using an advanced standard circuit manufacturing process and achieve excellent performance and power consumption. | 04-23-2015 |
20150113210 | DATA STORAGE FLASH MEMORY MANAGEMENT METHOD AND PROGRAM - There is provided a data storage flash memory management method that does not require a management area and can reduce an access load. A data storage flash memory management method for storing k time-varying parameters (k is a positive integer) in a flash memory including j blocks (j is an even number not less than 2) as erase units is configured as follows. The j blocks are divided into two areas which are a primary macroblock and a secondary macroblock, each including j/2 blocks. Each of the primary macroblock and the secondary macroblock is divided into k or more segments each having an equal memory capacity, with one of the macroblocks as an active system and the other as a standby system. The k parameters are one-to-one associated with k segments of the k or more segments, and each parameter is written or read to/from a corresponding segment in an active-system macroblock. | 04-23-2015 |
20150113211 | MULTI-LEVEL DATA PROTECTION FOR MEMORY SYSTEM - The disclosed embodiments are directed to methods and apparatuses for providing efficient and enhanced protection of data stored in a nonvolatile memory system. The methods and apparatuses involve a system controller for a plurality of nonvolatile memory devices in the nonvolatile memory system that is capable of protecting data using two layers of data protection, including inter-card card stripes and intra-card page stripes. | 04-23-2015 |
20150113212 | INFORMATION DEVICE EQUIPPED WITH CACHE MEMORIES, APPARATUS AND PROGRAM USING THE SAME DEVICE - A read cache and a write cache are made up of two kinds of nonvolatile memories whose characteristics are different. For example, nonvolatile memory whose write endurance is high is assigned to the write cache, nonvolatile memory whose write endurance is low is assigned to the read cache, and the management tables of data in these caches are stored in the nonvolatile memory whose write endurance is high. Alternatively, nonvolatile memory that has a fast write speed but has a slow read speed is adopted for the write cache and nonvolatile memory that has a fast read speed but has a slow write speed is adopted for the read cache. | 04-23-2015 |
20150120988 | Method of Accessing Data in Multi-Layer Cell Memory and Multi-Layer Cell Storage Device Using the Same - A method of accessing data in a multi-layer cell (MLC) memory includes using single-layer cell (SLC) configuration to transfer a portion of a plurality of memory units in the MLC memory to an SLC area to form a plurality of MLC memory units and a plurality of SLC memory units; storing data in the plurality of SLC memory units when the data is assigned to be stored in an MLC memory unit; mapping the MLC memory unit to the SLC memory units; reading the data by obtaining the data in the SLC memory units corresponding to the MLC memory unit; and reallocating the SLC memory units to use MLC configuration when an update of data is involved in the MLC memory unit or a new data is assigned to be stored in at least one of the SLC memory units. | 04-30-2015 |
20150120989 | Tracking and Utilizing Second Level Map Index for Recycling of Solid State Drive Blocks - A recycling method for a solid state drive is disclosed. The method includes selecting a logical block for recycle wherein the logical block includes a plurality of pages across a plurality of flash dies. The method also includes retrieving an address map index record associated with the logical block selected for recycle. For each particular address map index stored in the address map index record, the recycling method retrieves a set of address map entries referenced by the particular address map index, determines whether any page in the logical block is referenced by the set of address map entries, and if at least one page in the logical block is referenced by the set of address map entries, the method writes the at least one page to a different logical block. The method further includes erasing the plurality of pages in the logical block. | 04-30-2015 |
20150120990 | METHOD OF DETECTING MEMORY MODULES, MEMORY CONTROL CIRCUIT UNIT AND STORAGE APPARATUS - A method of detecting a rewritable non-volatile memory module is provided. The method includes setting an output voltage of a write protect pin of a memory interface as a first logic level, giving a read status command and receiving a first status message. The method further includes determining whether a corresponding bit data in the first status message conforms to a status corresponding to the first logic level; and if yes, identifying that the rewritable non-volatile memory module has connected to the memory interface. | 04-30-2015 |
20150120991 | DATA PROCESSING SYSTEM AND OPERATING METHOD THEREOF - A data processing system includes a host device comprising an application and suitable for generating information on an attribute of the application and providing the information on the attribute of the application together with a request of the application and a data storage device suitable for writing data based on the information on the attribute of the application in response to the request of the application. | 04-30-2015 |
20150120992 | NON-VOLATILE MEMORY DEVICE, NON-VOLATILE MEMORY CONTROL DEVICE, AND NON-VOLATILE MEMORY CONTROL METHOD - A non-volatile memory device includes a non-volatile memory unit, a control unit, and an interface. The control unit receives a write request, determines whether data is an object of a write of sequential management when a write size of the received data is smaller than a management unit of erasure, performs first write processing in which the received data smaller than the management unit of the erasure is sequentially written when the data is the object of the write of the sequential management, and performs second write processing in which the received data smaller than the management unit of the erasure is written by the management unit of the write when the data is not the object of the write of the sequential management. | 04-30-2015 |
20150120993 | INFORMATION PROCESSING APPARATUS, STORAGE DEVICE CONTROL CIRCUIT, AND STORAGE DEVICE CONTROL METHOD - Channels have NAND flash memories. Data processing units perform data processing on the NAND flash memories by using the channels according to a data processing command from a CPU. A configuration register stores therein a configuration of groups into which the channels are classified based on processing performances of the respective channels, and stores therein assignments of the data processing units that perform data processing by using the channels contained in each of the groups. The group identifying unit selects a group for performing data processing from among the groups stored in the configuration register based on the data processing command from the CPU, and causes the data processing unit assigned to the selected group to perform the data processing. | 04-30-2015 |
20150120994 | AUTOMATED SPACE MANAGEMENT FOR SERVER FLASH CACHE - Techniques for automatically allocating space in a flash storage-based cache are provided. In one embodiment, a computer system collects I/O trace logs for a plurality of virtual machines or a plurality of virtual disks and determines cache utility models for the plurality of virtual machines or the plurality of virtual disks based on the I/O trace logs. The cache utility model for each virtual machine or each virtual disk defines an expected utility of allocating space in the flash storage-based cache to the virtual machine or the virtual disk over a range of different cache allocation sizes. The computer system then calculates target cache allocation sizes for the plurality of virtual machines or the plurality of virtual disks based on the cache utility models and allocates space in the flash storage-based cache based on the target cache allocation sizes. | 04-30-2015 |
20150127882 | READ OPERATION PRIOR TO RETRIEVAL OF SCATTER GATHER LIST - A data storage device includes a non-volatile memory and a controller coupled to the non-volatile memory. The controller is configured to receive a read command from a host device. The read command includes a starting logical block address (LBA) of the non-volatile memory, a number of logical blocks to be read (NLB), and a pointer to a scatter gather list (SGL). The controller is also configured to instruct the non-volatile memory to read a plurality of logical blocks from the non-volatile memory based on the starting LBA and the NLB. The controller is further configured to, after instructing the non-volatile memory to read the plurality of logical blocks, retrieve the SGL based on the pointer. The controller is configured to transfer a subset of the plurality of logical blocks identified by the SGL to the host device. | 05-07-2015 |
20150127883 | REDUCTION OR ELIMINATION OF A LATENCY PENALTY ASSOCIATED WITH ADJUSTING READ THRESHOLDS FOR NON-VOLATILE MEMORY - Channel information and channel conditions that are determined by an Offline Tracking process are used to determine whether or not an adjustment to the read reference voltage can be avoided altogether without detrimentally affecting performance, or, alternatively, to determine a precision with which a read reference voltage adjustment should be made. If it is determined based on the channel conditions that a read reference voltage adjustment can be avoided altogether, read performance is improved by reducing the probability that a read reference voltage adjustment needs to be made during normal read operations. If it is determined based on the channel conditions that a read reference voltage adjustment needs to be made with a particular precision, the read reference voltage is adjusted with that precision. This latter approach is advantageous in that a determination that the precision with which the adjustments can be made is relatively low leads to fewer adjustments having to be made during normal read operations. | 05-07-2015 |
20150127884 | MEMORY DEVICE AND SYSTEM INCLUDING THE SAME - A memory device include a memory array, a transmitter suitable for outputting data to the outside of the memory device, and a data bus suitable for transmitting data of a selected memory cell in the memory array to the transmitter during a read operation. When successive read commands for the same memory cell are applied, data transmission from the memory array to the data bus is blocked, and data previously loaded in the data bus is outputted through the transmitter. | 05-07-2015 |
20150127885 | MEMORY CONTROLLING METHOD, MEMORY STORAGE DEVICE AND MEMORY CONTROLLING CIRCUIT UNIT - A memory controlling method, a memory storage device and a memory controlling circuit unit are provided. The method includes: providing a first clock signal to a rewritable non-volatile memory module and reading a first data in the rewritable non-volatile memory module according to the first clock signal; providing a second clock signal to the rewritable non-volatile memory module and writing a second data into the rewritable non-volatile memory module according to the second clock signal. A frequency of the second clock signal is different from a frequency of the first clock signal. Accordingly, an operation speed of the rewritable non-volatile memory module may be increased and probabilities of having errors for some operations are decreased. | 05-07-2015 |
20150127886 | MEMORY SYSTEM AND METHOD - According to an embodiment, a memory system is provided with a nonvolatile memory, which is configured by a plurality of memory cells, and a controller. The memory is provided with a plurality of first blocks and a plurality of second blocks. The plurality of first blocks are provided with a third block in which no valid data is stored. The plurality of second blocks are provided with a fourth block in which no valid data is stored. When a host makes a request for writing data, the controller writes the data in the third block in a case where the number of the third blocks is larger than a first threshold. In a case where the number of the third blocks is smaller than the first threshold, the controller writes the data in the fourth block. | 05-07-2015 |
20150127887 | DATA STORAGE SYSTEM AND OPERATING METHOD THEREOF - An operating method of a data storage system may include detecting a sudden power-off during a program operation on pages in a memory block, identifying a dummy program target page in the memory block when power is on after the sudden power-off, and performing the program operation on the dummy program target page using dummy data, and performing the program operation on pages in the memory block subsequent to the dummy program target page using normal data. | 05-07-2015 |
20150127888 | Data Storage Device and Error Correction Method Thereof - A firmware loading system including a first memory device and a calculation unit. The first memory device includes a first firmware code, wherein the first firmware code has a predetermined code and a plurality of parameter tables, and the parameter tables are arranged to set up a plurality of registers of a second memory device. The calculation unit is arranged to perform a firmware insertion procedure, wherein, during the firmware insertion procedure, the calculation unit selects one of the parameter tables according to a selection signal, compiles the selected parameter table and the predetermined code into a second firmware code, and writes the second firmware code in a flash memory of the second memory device. | 05-07-2015 |
20150127889 | NONVOLATILE MEMORY SYSTEM - A non-volatile memory system includes a NAND flash memory device including a first flash translation layer that performs a garbage collection operation, and a host device including a file system and a second flash translation layer that controls an operation of the NAND flash memory device by interacting with the file system. Here, the host device provides application data in an in-ordered form to the NAND flash memory device. Thus, the non-volatile memory system can perform a random write operation at high speed, and can minimize power consumption due to unnecessary data transfer. | 05-07-2015 |
20150127890 | MEMORY MODULE WITH A DUAL-PORT BUFFER - A computer system includes a memory module. The memory module includes volatile memory, a non-volatile memory subsystem, a host port, and a dual-port buffer device. The dual-port buffer device synchronously couples the non-volatile memory subsystem and the host port to the volatile memory. The dual port buffer device includes routing logic to selectably route address information provided by the host port and the non-volatile memory subsystem to the volatile memory. | 05-07-2015 |
20150127891 | WRITE PERFORMANCE PRESERVATION WITH SNAPSHOTS - Storage systems and methods for performing write commands and preserving data. A write is received to a first logical page in first memory. The first logical page corresponds to a first physical page. The write command is redirected to a second physical page different from the first physical page. Data is written to the new physical page in response to the write request. After writing the data to the new physical page, the data is copied from the first physical page to second memory. The write operation is not, therefore, delayed while data is copied for preservation. The first memory may comprise NAND based flash memory, for example, such as an SSD. | 05-07-2015 |
20150127892 | METADATA STORAGE ASSOCIATED WITH WEAR-LEVEL OPERATION REQUESTS - A method includes responding to a wear-level operation request by copying data from a first portion of a first memory array to a second portion of the first memory array, and copying metadata associated with the data from a third portion of a second memory array to a fourth portion of the second memory array. The first memory array includes a NAND or NAND-based memory array, and the second memory array includes non-volatile memory including at least one of the group consisting of: phase-change memory, EEPROM, and NOR flash memory. | 05-07-2015 |
20150127893 | SYSTEM AND METHOD FOR DATA INVERSION IN A STORAGE RESOURCE - A method may comprise receiving a page of data to be stored on a storage resource. The method may also comprise determining, for each particular inversion mode of a plurality of inversion modes, the number of bits of the page of data to be inverted to store a representation of the page of data in accordance with the particular inversion mode. The method may additionally comprise determining a selected inversion mode from the plurality of inversion modes for the page of data, the selected inversion mode comprising the inversion mode for which the least number of physical bit transitions are required to store the representation of the page of data in accordance with the selected inversion mode. The method may further comprise storing the representation of the page of data in a data memory in accordance with the inversion mode. | 05-07-2015 |
20150127894 | FLASH MEMORY CONTROLLER - A flash memory controller for controlling a flash memory module includes a communication interface for receiving a first data and a second data; and a processing circuit for dynamically controlling a data writing mode of the flash memory module according to an amount of stored data in the flash memory module. If the amount of stored data in the flash memory module is less than a first threshold when the communication interface receives the first data, the processing circuit controls the flash memory module so that the first data is written into the first data block under an one-bit-per-cell mode. If the amount of stored data in the flash memory module is greater than the first threshold when the communication interface receives the second data, the processing circuit controls the flash memory module so that the second data is written into the second data block under a two-bit-per-cell mode. | 05-07-2015 |
20150127895 | PROCESSOR AGNOSTIC DATA STORAGE IN A PCIE BASED SHARED STORAGE ENVIRONMENT - A controller device associated with a disk array that comprises a plurality of storage devices and a processor receives a request from a host machine that is at a remote location from the disk array. The controller device determines that the request is a data request or a control request based on metadata of the request. Responsive to determining that the request is a data request the controller device converts a format of the data request from a first format to a second format that is compatible with the plurality of storage devices. The data request is then routed in the second format directly to at least one storage device of the plurality of storage devices. | 05-07-2015 |
20150127896 | STORAGE SYSTEM AND STORAGE METHOD - A storage system comprises a storage comprising a nonvolatile storage medium, and a storage control apparatus for inputting/outputting data to/from the storage. The storage control apparatus comprises a memory for storing management information, which is information used in inputting/outputting data to/from the storage, and a control part for controlling access to the storage. The control part stores the management information, which is stored in the memory, in the storage as a base image, and when the management information is updated subsequent to the base image being stored in the storage, creates a journal comprising information related to this update, and stores the journal in the storage as a journal group which is configured from multiple journals. | 05-07-2015 |
20150134877 | DATA STORAGE SYSTEM WITH PASSIVE PARTITIONING IN A SECONDARY MEMORY - A data storage system may be configured at least with a primary memory that is coupled to a host via a controller and coupled to at least one external interface. The controller may be adapted to passively partition a secondary memory into cache and user memory space regions in response to the secondary memory engaging the at least one external interface and the cache region can be allocated as cache for the primary memory by the controller. | 05-14-2015 |
20150134878 | NONVOLATILE STORAGE THRESHOLDING FOR ULTRA-SSD, SSD, AND HDD DRIVE INTERMIX - Embodiments for efficient thresholding of nonvolatile storage (NVS) for a plurality of types of storage rank groups by a processor. Target storage devices are determined in a pool of target storage devices as one of a hard disk drive (HDD) and a solid-state drive (SSD) device. Each target storage device classified into an SSD rank group, a Nearline rank group, an Enterprise rank group, and an Ultra-SSD rank group in the pool of target storage devices. The Nearline rank group and the Enterprise rank group comprise a HDD rank group, and the Nearline rank group, the Enterprise rank group, and the SSD rank group comprise the Non-Ultra-SSD rank group. Thresholds are adjusted for preventing space allocation in the NVS for at least one of the classified target storage devices based on one of the presence and absence of identified types of the classified target storage devices. | 05-14-2015 |
20150134879 | SNAPSHOTS AND CLONES OF VOLUMES IN A STORAGE SYSTEM - In one embodiment, a node coupled to one or more storage devices executes a storage input/output (I/O) stack having a volume layer that manages volume metadata. The volume metadata is organized as one or more dense tree metadata structures having a top level residing in memory and lower levels residing on the one or more storage devices. The dense tree metadata structures include a first dense tree metadata structure associated with a parent volume and a second dense tree metadata structure associated with a copy of the parent volume. The top level of the first dense tree metadata structure may be copied to the second dense tree metadata structure. The lower levels of the first dense tree metadata structure are initially shared with the second dense tree metadata structure. The shared lower levels may eventually be split as the parent volume diverges from the copy of the parent volume. | 05-14-2015 |
20150134880 | APPARATUS AND METHOD FOR ROUTING INFORMATION IN A NON-VOLATILE MEMORY-BASED STORAGE DEVICE - Various systems, methods, apparatuses, and computer-readable media for accessing a storage device are described. In certain example embodiments, an active/active fault-tolerant storage device comprising two or more controllers may be implemented. In one aspect, each controller may have two or more processing entities for distributing the processing of the I/O requests. In one embodiment, the configuration of the components, modules and the controller board may be arranged in a manner to enhance heat dissipation, reduce power consumption, spread the power and work load, and reduce latency. In one embodiment, each controller may be coupled to the non-volatile memory (NVM) blades comprising the non-volatile memory (NVM) storage medium. In one example implementation, a standardized protocol, such as the Peripheral Component Interconnect Express protocol may be used for communicating amongst the various components of the controller and also the NVM storage medium. | 05-14-2015 |
20150134881 | APPARATUS AND METHOD FOR ACCESSING A NON-VOLATILE MEMORY BLADE USING MULTIPLE CONTROLLERS IN A NON-VOLATILE MEMORY BASED STORAGE DEVICE - Various systems, methods, apparatuses, and computer-readable media. for accessing a storage device are described. In certain example embodiments, an active/active fault tolerant storage device comprising two or more controllers may be implemented. In one embodiment, each controller may be coupled to the non-volatile memory (NVM) blades comprising the non-volatile memory (NVM) storage medium. In one example implementation, a standardized protocol, such as Peripheral Component Interconnect Express protocol may be used for communicating amongst the various components of the controller and also the NVM storage medium. | 05-14-2015 |
20150134882 | METHOD AND SYSTEM FOR USING TEMPLATES TO COMMUNICATE WITH NON-VOLATILE MEMORY - Systems and methods implemented therein are disclosed for communicating data between a memory controller and a first flash device. The system comprises a memory controller having a flash interface module. The memory controller is adapted to be communicatively coupled to a host system. The memory controller configured to receive a template. The template comprises a first set of resources for communicating data between the memory controller and the flash device and based on the template. The memory controller is adapted to configure the first set of resources for communicating data between the memory controller and the first flash device. The flash interface module is communicatively coupled to the memory controller. The flash interface module is configured to communicate data between the memory controller and the first flash device via the first set of resources. | 05-14-2015 |
20150134883 | METHOD AND SYSTEM FOR COMMUNICATING WITH NON-VOLATILE MEMORY VIA MULTIPLE DATA PATHS - Systems and methods implemented therein are disclosed for communicating data in a flash memory system. The system comprises a memory system, a data path manager (DPM) and a memory controller. The memory system is configured to receive a flash command from a host processor. In response to receiving the flash command, the memory system is configured to communicate a flash command sequence to one of the first flash device or the second flash device. Separately, the data path manager (DPM) is configured to select a subset of logical data paths from a set of logical data paths. Data is communicated between the memory controller and either one of the first flash device or the second flash device via the subset of logical data paths. | 05-14-2015 |
20150134884 | METHOD AND SYSTEM FOR COMMUNICATING WITH NON-VOLATILE MEMORY - Apparatus and methods implemented therein are disclosed for communicating with flash memories. The apparatus comprises a flash interface module and a processor in communication with the flash interface module. The flash interface module is configured for communication with a first and second flash bank. The processor is configured to generate a plurality of command sequences in response to receiving a plurality of flash commands from a host system. Each of the plurality of command sequences corresponds to a respective one of the plurality of flash commands. Some of the plurality of command sequences comprises a first portion and a second portion and each of the first portion and second portion are atomic. The processor associates each of the plurality of command sequences with a priority, and via the flash interface module, selects one of the plurality of the command sequences based on the priority associated with the one of the plurality of the command sequences and transmits sequentially the first portion of the one of the plurality of the command sequences to either one of the first flash bank or the second flash bank. | 05-14-2015 |
20150134885 | Identification and Operation of Sub-Prime Blocks in Nonvolatile Memory - In a block-erasable nonvolatile memory array, blocks are categorized as bad blocks, prime blocks, and sub-prime blocks. Sub-prime blocks are identified from their proximity to bad blocks or from testing. Sub-prime blocks are configured for limited operation (e.g. only storing non-critical data, or data copied elsewhere, or using some additional or enhanced redundancy scheme). | 05-14-2015 |
20150134886 | DATA STORAGE DEVICE - A data storage device includes a first memory device, a second memory device including a system region and a buffer region and a controller suitable for controlling the first memory device in response to a request from a host device, and allocating the system region and the buffer region according to an attribute of data involved with the request from the host device. | 05-14-2015 |
20150134887 | DATA WRITING METHOD, MEMORY CONTROL CIRCUIT UNIT AND MEMORY STORAGE APPARATUS - A data writing method for a rewritable non-volatile memory module having a plurality of physical erasing units, and a memory control circuit unit and the memory storage apparatus are provided. The method includes: grouping the physical erasing units into at least a data area and a spare area; configuring a plurality of logical units for mapping to the physical erasing units of the data area; and dynamically reserving a predetermined number of physical erasing units dedicating to write sequential data. Accordingly, the method can fast write the sequential data with the page-based memory management. | 05-14-2015 |
20150134888 | Fail Safe Refresh of Data Stored in NAND Memory Device - Methods, systems and devices provide for refreshing a data image stored on a NAND memory device. Aspects include sequentially copying each of a series of static data partitions into a scrub portion that does not store data image partitions identified in the partition table. The sequential copying begins with a last static data partition and proceeds sequentially to a first static data partition when the scrub portion occupies higher order addresses than the last address of the last static data partition. Alternatively, the sequential copying begins with the first static data partition and proceeds sequentially to the last static data partition when the scrub portion occupies addresses that are lower than the first address of the first static data partition. The partition table may be updated as each static data partition is stored to the scrub portion. Such operations enable fail-safe scrubbing and refreshing of data in a NAND device. | 05-14-2015 |
20150134889 | DATA STORAGE SYSTEM AND MANAGEMENT METHOD THEREOF - Data storage system and management method thereof are provided. The method, adopted by a data storage device coupled to a host device via a bus, includes: determining the data storage device requires to use a first temporary memory of the host device to access data in a second temporary memory of the data storage device; based on the determination, issuing a Device Bus Master (DBM) request message via the bus to the host to request for a right to control data transfer on the bus; in response to the DBM request message, detecting the bus to determine whether to receive a first DBM acknowledgement message from the host device; and if the first DBM acknowledgement message is received, then accessing the first temporary memory of the host device. | 05-14-2015 |
20150134890 | MEMORY CONTROLLER, COMPUTING DEVICE WITH A MEMORY CONTROLLER, AND METHOD FOR CALIBRATING DATA TRANSFER OF A MEMORY SYSTEM - A memory controller comprises a connection interface connected or connectable to a memory. The memory controller is arranged to read data from the memory via the connection interface The memory controller further comprises a clock unit arranged to provide a data transfer clock signal having a first frequency. The data transfer clock signal may be provided to the memory via the connection interface The data transfer clock signal is arranged for clocking a data transfer from the memory to the memory controller via the connection interface as well as an oversampling circuit arranged to sample a calibration data pattern read by the memory controller via the connection interface at a second frequency to provide an over-sampled calibration data pattern. The second frequency is larger than the first frequency. The memory controller is arranged to determine a timing shift of a data transfer from the memory to the memory controller based on the oversampled calibration data pattern. | 05-14-2015 |
20150134891 | NONVOLATILE MEMORY SYSTEM AND OPERATING METHOD THEREOF - A nonvolatile memory system includes a nonvolatile memory; a buffer memory having first and second buffers; and a memory controller configured to manage the first and second buffers based on first and second indexes and to control the nonvolatile memory in response to a write request provided from an external device. The memory controller allocates a part of the first buffer to a Direct Memory Access (hereinafter, referred to as DMA) buffer in response to the write request, stores write data received from the external device in the allocated DMA buffer based on a DMA operation, partially swaps the first and second indexes to shift the write data stored in the allocated DMA buffer to the second buffer, and transmits the write data shifted to the second buffer to the nonvolatile memory. | 05-14-2015 |
20150134892 | INFORMATION PROCESSING APPARATUS, METHOD OF CONTROLLING THE SAME, AND STORAGE MEDIUM - In an information processing apparatus and a method of controlling the information processing apparatus having a non-volatile main memory, allocates a memory area to be used for processing of an application in the non-volatile main memory, in a case where an instruction of processing by the application is received, and stores data in the allocated memory area. The apparatus and method clear data stored in the memory area and release the memory area, when processing for the data stored in the memory area by the application has completed. | 05-14-2015 |
20150134893 | FLASH DRIVE SHAPED TO UTILIZE SPACE BEHIND A MOBILE DEVICE - A flash drive that can utilize space behind a mobile device is disclosed. In some embodiments, a body of the flash drive has three portions, a front portion, a back portion, and an intermediate portion that runs from the front portion to the back portion. A mobile device connector extends from a first end of the front portion, and a second connector extends from a second end of the back portion. The intermediate portion is configured to cause, when the mobile device connector is connected to the mobile device, the second connector and part of the back portion of the body to be located behind and, in some embodiments, adjacent to the back of the mobile device. This can enable part of the body to fit in a gap that can form between the back of the mobile device and a user's palm when the user holds the mobile device. | 05-14-2015 |
20150134894 | PARTIAL R-BLOCK RECYCLING - An apparatus includes a non-volatile memory and a controller. The non-volatile memory includes a plurality of R-blocks. The controller is coupled to the non-volatile memory. The controller is configured to (i) write data using the R-blocks as a unit of allocation and (ii) perform recycling operations selectively on either an entire one of the R-blocks or a portion less than all of one of the R-blocks. | 05-14-2015 |
20150143021 | EQUALIZING WEAR ON STORAGE DEVICES THROUGH FILE SYSTEM CONTROLS - Data stored in file blocks and storage blocks of a storage device may be tracked by the file system. The file system may track a number of writes performed to each file block and storage block. The file system may also track a state of each storage block. The file system may use information, such as the write count and the block state, to determine locations for updated data to be stored on the storage device. Placement of data by the file system allows the file system to manage wear on storage devices, such as solid state storage devices. | 05-21-2015 |
20150143022 | REMOVABLE MEMORY CARD DISCRIMINATION SYSTEMS AND METHODS - Removable memory card discrimination systems and methods are disclosed. In particular, exemplary embodiments discriminate between secure digital (SD) cards and other removable memory cards that comply with the SD form factor, but support the Universal Flash Storage (UFS) protocol. That is, a host may have a receptacle that supports the SD card form factor and is configured to receive a device. In use, a removable memory card is inserted into the receptacle and, using an SD compliant interrogation signal, the host interrogates a common area on the card so inserted. The common area includes information related to capability descriptors of the card. An SD compliant card will respond with information such as capability descriptors about the SD protocol capabilities, while a UFS compliant card will respond with an indication that the card is UFS compliant. The host may then restart the communication with the card using the UFS protocol. | 05-21-2015 |
20150143023 | Detecting Access Sequences for Data Compression on Non-Volatile Memory Devices - Techniques are presented to allow non-volatile memory system to operate more efficiently by determining ranges of logical addresses that a host typically accesses as together. For example, the system's controller can determine that the host always, or most always, writes or reads a contiguous set of logical addresses as a single unit. The controller can exploit this information by operating on these ranges as single a unit for data operations it performs. To take one example, the memory system can treat such ranges as single units for on-system data compression prior to writing the data to non-volatile memory, thereby increasing the efficiency of such data compression. | 05-21-2015 |
20150143024 | REDUNDANT ARRAY OF INDEPENDENT MODULES - A Redundant Array of Independent Modules (RAIM) system has the similar function and architecture as Redundant Array of Independent Disk (RAID) system. It includes a RAID controller coupled to send and receive information to and from a host through an interface and a plurality of modules coupled to the RAID controller, wherein the plurality of modules are not disk drives, but SD/MMC/eMMC modules. Each such kind of modules in RAIM system acts as a single drive in RAID system. | 05-21-2015 |
20150143025 | Update Block Programming Order - Certain MLC blocks that tend to be reclaimed before they are full may be programmed according to a programming scheme that programs lower pages first and programs upper pages later. This results in more lower page programming than upper page programming on average. Lower page programming is generally significantly faster than upper page programming so that more lower page programming (and less upper programming) reduces average programming time. | 05-21-2015 |
20150143026 | TEMPERATURE BASED FLASH MEMORY SYSTEM MAINTENANCE - A memory system or flash card may include memory maintenance scheduling that improves the endurance of memory. Certain parameters, such as temperature, are measured and used for scheduling maintenance. For example, memory maintenance may be performed or postponed depending on the ambient temperature of the card. The memory maintenance operations may be ranked or classified (e.g. in a memory maintenance queue based on priority) to correspond with threshold values of the parameters for a more efficient scheduling of memory maintenance. For example, at a low temperature threshold, only high priority maintenance operations are performed, while at a higher temperature threshold, any priority maintenance operation is performed. | 05-21-2015 |
20150143027 | SOLID STATE DRIVE WITH RAID FUNCTIONS - A single solid state drive (SSD) includes an SSD controller coupled to send and receive information to and from a host through an interface. The SSD controller includes an embedded RAID controller and a plurality of non-volatile memory modules (NVMs) coupled to the SSD controller. The SSD controller causes storage of the received information in the NVMs and sending of the information from the NVMs under the control of the embedded RAID controller. | 05-21-2015 |
20150143028 | DATA STORAGE APPARATUS AND OPERATING METHOD THEREOF - A data storage apparatus includes a translation section suitable for performing a translation operation for translating first address mapping data to second address mapping data, and an operation memory device suitable for storing the second address mapping data. | 05-21-2015 |
20150143029 | DYNAMIC LOGICAL GROUPS FOR MAPPING FLASH MEMORY - A memory system or flash card may include a controller that indexes a global address table (GAT) with a single data structure that addresses both large and small chunks of data. The GAT may include both large logical groups and smaller logical groups for optimizing write amplification. The addressing space may be organized with a large logical group size for sequential data. For fragmented data, the GAT may reference an additional GAT page or additional GAT chunk that has a smaller logical group size. | 05-21-2015 |
20150143030 | Update Block Programming Order - Certain MLC blocks that tend to be reclaimed before they are full may be programmed according to a programming scheme that programs lower pages first and programs upper pages later. This results in more lower page programming than upper page programming on average. Lower page programming is generally significantly faster than upper page programming so that more lower page programming (and less upper programming) reduces average programming time. | 05-21-2015 |
20150143031 | METHOD FOR WRITING DATA INTO STORAGE DEVICE AND STORAGE DEVICE - A storage device includes a buffer memory and a flash memory, which can be connected with the host computer communicably. A method for writing data into the storage device includes: receiving a first write command from the host, the first write command including the data to be written, the address for the flash memory and the address or the buffer memory; based on the address for the buffer memory, writing the data to be written to the buffer memory; based on the address for the flash memory, writing the data to be written to the flash memory. | 05-21-2015 |
20150143032 | STORAGE MEDIUM STORING CONTROL PROGRAM, METHOD OF CONTROLLING INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING SYSTEM, AND INFORMATION PROCESSING DEVICE - According to an embodiment, when data read from a first storage unit which is a backup source is not identical with data indicated by a first function, the read data is written to a second storage unit which is a backup destination. When the data read from the first storage unit is identical with the data indicated by the first function, the read data is not written to the second storage unit and a deletion notification is sent to the second storage unit. | 05-21-2015 |
20150143033 | CONTROLLING WRITE SPEED OF NONVOLATILE MEMORY DEVICE - A system comprises a nonvolatile memory device having multiple download speeds, and a computing device connected to the nonvolatile memory device and configured to determine a download environment of the nonvolatile memory device and to set the nonvolatile memory device to one of the download speeds according to the determined download environment. | 05-21-2015 |
20150143034 | HYBRID MEMORY ARCHITECTURES - Methods and apparatuses for providing a hybrid memory module having both volatile and non-volatile memories to replace a DDR channel in a processing system. | 05-21-2015 |
20150143035 | USER DEVICE HAVING A HOST FLASH TRANSLATION LAYER (FTL), A METHOD FOR TRANSFERRING AN ERASE COUNT THEREOF, A METHOD FOR TRANSFERRING REPROGRAM INFORMATION THEREOF, AND A METHOD FOR TRANSFERRING A PAGE OFFSET OF AN OPEN BLOCK THEREOF - A user device includes a storage device including a flash memory; and a host connected to the storage device via an interface and adapted to transmit data to the storage device. The host provides the storage device with erase count information of the flash memory using a host flash translation layer (FTL), provides the storage device with reprogram information when the flash memory uses a reprogram method, or provides the storage device with page offset information of an open block of the flash memory. | 05-21-2015 |
20150143036 | EXPORTING COMPUTATIONAL CAPABILITIES INTO A BLOCK-ORIENTED DISK MEMORY - A memory controller is provided that includes a host system interface that receives requests from applications and sends read or write commands to a disk for data retrieval. A threadlet core provides threadlets to the host system interface that enable the host system interface to use a logical bit address that can be sent to a memory device for execution without having to read and write entire blocks to and from the memory device. | 05-21-2015 |
20150143037 | SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR MULTI-THREAD OPERATION INVOLVING FIRST MEMORY OF A FIRST MEMORY CLASS AND SECOND MEMORY OF A SECOND MEMORY CLASS - An apparatus, computer program product, and associated method/processing unit are provided for utilizing a memory subsystem including a first memory of a first memory class, and a second memory of a second memory class communicatively coupled to the first memory. In operation, data is fetched using a time between a plurality of threads. | 05-21-2015 |
20150143038 | STORAGE PROCESSOR MANAGING SOLID STATE DISK ARRAY - A method of writing to one or more solid state disks (SSDs) employed by a storage processor includes receiving a command, creating sub-commands from the command based on a granularity, and assigning the sub-commands to the SSDs independently of the command thereby causing stripping across the SSDs. | 05-21-2015 |
20150143039 | Restoring Virtualized GCU State Information - Method and apparatus for managing a memory, such as but not limited to a flash memory. In accordance with some embodiments, initial state information is stored which identifies an actual state of a garbage collection unit (GCU) of a memory during a normal operational mode. During a restoration mode after a memory power cycle event, a virtualized state of the GCU is determined responsive to the initial state information and to data read from the GCU. The memory is transitioned from the restoration mode to the normal operational mode once the virtualized state for the GCU is determined. | 05-21-2015 |
20150143040 | MEMORY DEVICE AND METHOD HAVING ON-BOARD PROCESSING LOGIC FOR FACILITATING INTERFACE WITH MULTIPLE PROCESSORS, AND COMPUTER SYSTEM USING SAME - A memory device includes an on-board processing system that facilitates the ability of the memory device to interface with a plurality of processors operating in a parallel processing manner. The processing system includes circuitry that performs processing functions on data stored in the memory device in an indivisible manner. More particularly, the system reads data from a bank of memory cells or cache memory, performs a logic function on the data to produce results data, and writes the results data back to the bank or the cache memory. The logic function may be a Boolean logic function or some other logic function. | 05-21-2015 |
20150149691 | Directly Coupled Computing, Storage and Network Elements With Local Intelligence - An apparatus that collapses computing, storage and networking elements into a tightly coupled, deeply vertically integrated highly scalable system that additionally provides augmented intelligence within each of the computing, storage and networking elements. A method to collapse computing, storage and networking elements while augmenting each of their intelligence. A system consisting of one or more scalable apparatus that collapse computing, storage and networking elements with augmented intelligence. | 05-28-2015 |
20150149692 | EFFICIENT REUSE OF SEGMENTS IN NONOVERWRITE STORAGE SYSTEMS - A non-overwrite storage system, such as a log-structured file system, that includes a non-volatile storage having multiple storage segments, a volatile storage having an unsafe free segments list (UFSL), and a controller for managing storage resources of the non-volatile storage. The controller can be configured to copy page data from used segment(s) of the non-volatile storage, write the copied page data to free segment(s) of the non-volatile storage, index the UFSL with indications of the used segment(s), and thereafter prevent reuse of the used segment(s) while the indications of the used segment(s) remain indexed in the UFSL. In some implementations, the non-overwrite storage system may be associated with flash storage system, and a flash controller can be configured perform a flush track cache operation to clear the indications of the used segment(s) from the UFSL, to enable reuse of segment(s) that were previously indexed to the UFSL. | 05-28-2015 |
20150149693 | Targeted Copy of Data Relocation - In a nonvolatile memory array that has a binary cache formed of SLC blocks and a main memory formed of MLC blocks, corrupted data along an MLC word line is corrected and relocated, along with any other data along the MLC word line, to binary cache, before it becomes uncorrectable. Subsequent reads of the relocated data directed to binary cache. | 05-28-2015 |
20150149694 | Adaptive Context Disbursement for Improved Performance in Non-Volatile Memory Systems - A controller circuit for a non-volatile memory of one or more memory circuits is described. The controller is connectable by a port with the memory circuits through a bus structure and can operate the memory circuits according to one or more threads. The controller includes a command processing section to issue high level commands for execution in the memory circuits and a memory circuit interface module to issue in sequence by the port to the memory circuits a series of instruction derived from the high level commands. A queue manager on the controller derives the series of instructions from the high level commands. When deriving a series of instruction from a set of high level data access commands, the queue manager can modify the timing for the issuance to the memory circuit interface module of memory circuit check status instructions based upon feedback from the memory circuit interface module and the state of earlier instruction in the series. | 05-28-2015 |
20150149695 | SYSTEM AND METHOD FOR COMPUTING MESSAGE DIGESTS - A data de-duplication approach leverages acceleration hardware in SSDs for performing digest computations used in de-duplication operations and support on behalf of an attached host, thereby relieving the host from the computing burden of the digest computation in de-duplication (de-dupe) processing. De-dupe processing typically involve computation and comparison of message digests (MD) and/or hash functions. Such MD functions are often also employed for cryptographic operations such as encryption and authentication. Often, SSDs include onboard hardware accelerators for MD functions associated with security features of the SSDs. However, the hardware accelerators may also be invoked for computing a message digest result and returning the result to the host, effectively offloading the burden of MD computation from the host, similar to an external hardware accelerator, but without redirecting the data since the digest computation is performed on a data stream passing through the SSD for storage. | 05-28-2015 |
20150149696 | Auto Resume of Irregular Erase Stoppage of a Memory Sector - Disclosed herein are system, method and/or computer program product embodiments for automatically resuming an irregular erasure stoppage in a sector of a memory system. An embodiment includes storing information related to any completed sub-stage of a multi stage erasure process and the corresponding memory sector address in a dedicated memory. After an irregular erasure stoppage occurs, an embodiment reads the information from the dedicated memory and resumes the erasure process of the memory sector from the last sub-stage completed. | 05-28-2015 |
20150149697 | SYSTEM AND METHOD FOR SUPPORTING ATOMIC WRITES IN A FLASH TRANSLATION LAYER - A method of maintaining and updating a logical-to-physical (LtoP) table in a storage device including a processor, a volatile memory, and a non-volatile memory, the storage device being in communication with a host utilizing atomic writes, the method including receiving, by the processor, data for storing at a plurality of physical addresses in the non-volatile memory, the data being associated with a plurality of logical addresses of the host, storing, by the processor, the plurality of physical addresses in an atomic segment in the volatile memory, storing, by the processor, one or more of zones of the LtoP table in the non-volatile memory, the one or more zones of the LtoP table corresponding in size to the atomic segment, and updating the one or more zones of the LtoP table with the plurality of physical addresses in the atomic segment. | 05-28-2015 |
20150149698 | ELIMINATING OR REDUCING PROGRAMMING ERRORS WHEN PROGRAMMING FLASH MEMORY CELLS - Mis-programming of MSB data in flash memory is avoided by maintaining a copy of LSB page data that has been written to flash memory and using the copy rather than the LSB page data read out of the flash cells in conjunction with the MSB values to determine the proper reference voltage ranges to be programmed into the corresponding flash cells. Because the copy is free of errors, using the copy in conjunction with the MSB values to determine the proper reference voltage ranges for the flash cells ensures that mis-programming of the reference voltage ranges will not occur. | 05-28-2015 |
20150149699 | Adaptive Erase of a Storage Device - The various implementations described herein include systems, methods and/or devices used to enable adaptive erasure in a storage device. The method includes performing a plurality of memory operations including read operations and respective erase operations on portions of one or more non-volatile memory devices specified by the read operations and respective erase operations, where the respective erase operations are performed using a first set of erase parameters that has been established as a current set of erase parameters prior to performing the respective erase operations. The method includes, in accordance with each erase operation of at least a subset of the respective erase operations, updating one or more erase statistics that correspond to performance of multiple erase operations. The method includes, in accordance with a comparison of the erase statistics with an erasure performance threshold, establishing a second set of erase parameters as the current set of erase parameters. | 05-28-2015 |
20150149700 | DIMM Device Controller Supervisor - The various implementations described herein include systems, methods and/or devices used to enable performing supervisory functions for a dual in-line memory module (DIMM), at a controller in the DIMM. The method includes upon power-up, determining a power supply voltage provided to the DIMM. In accordance with a determination that power supply criteria are satisfied, the method includes: (1) performing one or more power-up operations, including initiating a usage counter, (2) monitoring a temperature of the DIMM, (3) monitoring the DIMM for occurrence of one or more of a set of predetermined trigger events, and (4) in response to detecting one of the set of predetermined trigger events, logging information corresponding to the detected predetermined event. | 05-28-2015 |
20150149701 | TIME ESTIMATING METHOD, MEMORY STORAGE DEVICE, AND MEMORY CONTROLLING CIRCUIT UNIT - A time estimating method, a memory storage device, and a memory controlling circuit unit are provided for a rewritable non-volatile memory module having memory cells. The method includes: writing first data into first memory cells of the memory cells; reading the first memory cells according to a reading voltage, so as to determine whether each of the first memory cells belongs to a first state or a second state; and calculating a quantity of the first memory cells belonging to the first state, and obtaining a time information of the rewritable non-volatile memory module according to the quantity. | 05-28-2015 |
20150149702 | METHOD FOR DATA MANAGEMENT AND MEMORY STORAGE DEVICE AND MEMORY CONTROL CIRCUIT UNIT - A method for data management and a memory storage device and a memory control circuit unit thereof. The method includes: configuring a NVRAM and a VRAM; storing first data which includes writing data from a host system in the NVRAM; storing second data read from a rewritable non-volatile memory module in the VRAM; when the memory storage device is re-powered on after power failure, reading the first data from the NVRAM, so as to write the writing data into the rewritable non-volatile memory module. | 05-28-2015 |
20150149703 | APPARATUSES FOR SECURING PROGRAM CODE STORED IN A NON-VOLATILE MEMORY - An embodiment of an apparatus for securing program code stored in a non-volatile memory is introduced. A non-volatile memory contains a first region and a second region. Two NVMMCS (non-volatile memory management controllers respectively coupled to the two regions. A programming command-and-address decoder is coupled to the NVMMCS. The programming command-and-address decoder instructs the first NVMMC to erase data from the first region when receiving a command to erase the first region via a programming interface, and instructs the second NVMMC to erase data from the second region when receiving a command to erase the second region via the programming interface. | 05-28-2015 |
20150149704 | Transaction Private Log Buffering for High Performance of Transaction Processing - For each data change occurring transaction created as part of a write operation initiated for one or more tables in a main-memory-based DBMS, a transaction log entry can be written to a private log buffer corresponding to the transaction. All transaction log entries in the private log buffer can be flushed to a global log buffer upon completion of the transaction to which the private log buffer corresponds. | 05-28-2015 |
20150149705 | INFORMATION-PROCESSING SYSTEM - Information-processing system including a first information-processing unit, and a second information-processing unit, when the concept of wear leveling is applied to distribution of workloads to the respective information-processing units, the lives of the nonvolatile memories of the first information-processing unit and the second information-processing unit come to ends at almost exactly the same time, comprising a first counter that counts a number of times of writing in the first memory device, and a second counter that counts a number of times of writing in the second memory device, and assignment of workloads to the first information-processing unit and the second information-processing unit is performed based on a replacement time of the first memory device, a replacement time of the second memory device, output of the first counter, and output of the second counter. Thereby, the above described problem is solved. | 05-28-2015 |
20150149706 | SYSTEM AND METHOD FOR EFFICIENT FLASH TRANSLATION LAYER - A method of maintaining and updating a logical-to-physical (LtoP) table in a storage device including a processor, a volatile memory, and a non-volatile memory, the storage device being in communication with a host, the method including receiving, by the processor, data for storing at a physical address in the non-volatile memory, the data being associated with a logical address of the host, storing, by the processor, the physical address in a first LtoP zone of a plurality of LtoP zones of the LtoP table, the LtoP table being stored in the volatile memory, adding, by the processor, the first LtoP zone to a list of modified zones, and storing, by the processor, a second LtoP zone of the plurality of LtoP zones in the non-volatile memory when a size of the list of modified zones exceeds a threshold. | 05-28-2015 |
20150149707 | MICROCONTROLLER WITH INTEGRATED INTERFACE ENABLING READING DATA RANDOMLY FROM SERIAL FLASH MEMORY - A microcontroller includes a microprocessor, a serial flash memory interface, and input/output (I/O) terminals for coupling the serial flash memory interface to external serial flash memory. The microprocessor is operable to generate instruction frames that trigger respective commands to read data from specified addresses in the external serial flash memory. The serial flash memory interface receives and processes the instruction frames, obtains the data contained in the specified addresses in the external serial flash memory regardless of whether the specified addresses are sequential or non-sequential, and provides the data for use by the microprocessor. | 05-28-2015 |
20150149708 | B-FILE ABSTRACTION FOR EFFICIENTLY ARCHIVING SELF-EXPIRING DATA - Systems and methods are provided for data processing and storage management. In an illustrative implementation an exemplary computing environment comprises at least one data store, a data processing and storage management engine (B-File engine) and at least one instruction set to instruct the B-File engine to process and/or store data according to a selected data processing and storage management paradigm. In an illustrative operation, the illustrative B-File engine can generate a B-File comprising multiple buckets and store sample items in a random bucket according to a selected distribution. When the size of the B-FILE grows to reach a selected threshold (e.g., maximum available space), the B-File engine can shrink the B-File by discarding the largest bucket. Additionally, the B-File engine can append data to existing buckets and explicitly cluster data when erasing data such that data can be deleted together into the same flash block. | 05-28-2015 |
20150149709 | HYBRID STORAGE - Example control methods of hybrid storage are provided, which are applied to each HDD-type storage device and each SSD-type storage device in a storage system having one or more HDD-type storage devices and one or more SSD-type storage devices. Each HDD-type storage device in the storage system is connected to the SSD-type storage device. Each HDD-type storage device and each SSD-type storage device stores one or more data blocks respectively. Access information of each data block stored in a storage device is periodically acquired. A storage location of each data block in the storage system is adjusted according to the acquired access information of each data block. By using the technical solution of the present disclosure, the storage location of the data block is dynamically configured according to an access frequency so that advantages of different storage devices are fully utilized. | 05-28-2015 |
20150149710 | NONVOLATILE MEMORY DEVICE AND SUB-BLOCK MANAGING METHOD THEREOF - A nonvolatile memory device includes a memory block, a row decoder, a voltage generator and control logic. The memory block includes memory cells stacked in a direction intersecting a substrate, the memory block being divided into sub-blocks configured to be erased independently. The row decoder is configured to select the memory block by a sub-block unit. The voltage generator is configured to generate an erase word line voltage to be provided to a first word line of a selected sub-block of the sub-blocks and a cut-off voltage, higher than the erase word line voltage, to be provided to a second word line of the selected sub-block during an erase operation. The control logic is configured to control the row decoder and the voltage generator to perform an erase operation on the selected sub-block. | 05-28-2015 |
20150149711 | CACHE DECICE AND MEMORY SYSTEM - A virtual memory management apparatus of an embodiment is embedded in a computing machine | 05-28-2015 |
20150149712 | TRANSLATION LAYER IN A SOLID STATE STORAGE DEVICE - Solid state storage devices and methods for flash translation layers are disclosed. In one such translation layer, a sector indication is translated to a memory location by a parallel unit look-up table is populated by memory device enumeration at initialization. Each table entry is comprised of communication channel, chip enable, logical unit, and plane for each operating memory device found. When the sector indication is received, a modulo function operates on entries of the look-up table in order to determine the memory location associated with the sector indication. | 05-28-2015 |
20150293710 | STORAGE SYSTEM - A storage system includes a memory unit group that includes a first memory unit and a plurality of second memory units, and the first memory unit is connected to the plurality of second memory units so that data can be transmitted between the first memory unit and the second memory units. The plurality of second memory units is mounted on a same first substrate. One second memory unit of the plurality of second memory units cooperates with the first memory unit and does not cooperate with the other second memory units of the plurality of second memory units. | 10-15-2015 |
20150293713 | STORAGE CONTROLLER, STORAGE DEVICE, STORAGE SYSTEM AND METHOD OF OPERATING THE STORAGE CONTROLLER - A storage controller is for improving performance of a storage device by reducing the number of data I/O operations. A storage device, a storage system and a method of operating the storage controller are also included. The storage controller includes a host interface receiving data requested for storage from a host and lifetime information indicating a change period of the data, and a data placement manager determining a storage position of the data in a flash memory based on the lifetime information of the data. | 10-15-2015 |
20150293839 | DATA EXCHANGE SYSTEM - A data exchange system including: a microprocessor; a non-volatile memory; a first communication channel linking the microprocessor to the non-volatile memory; a first supply channel configured to supply electrical energy to the microprocessor and to the non-volatile memory; a control device; a second communication channel through which an external device can exchange data with the non-volatile memory; a second supply channel configured to supply the control device and the non-volatile memory. | 10-15-2015 |
20150293840 | MEMORY CONTROLLER AND ASSOCIATED METHOD - A memory controller is arranged for controlling the process of writing a page data to a memory, wherein the page data possesses a logical address. The memory controller includes a page buffer, a data pattern detector and a logical-physical address mapping table. The page buffer is used for buffering the page data. The data pattern detector is coupled to the page buffer, and used to detect whether the page data is a predetermined pattern, to generate a data pattern flag, and determine whether to write the page data to a physical address of the memory according to the data pattern flag. The logical-physical address mapping table is coupled to the data pattern detector, and is arranged for storing the data pattern flag and the logical address of the page data, and selectively generating and storing the physical address. | 10-15-2015 |
20150293843 | DIRECT MAPPING OF DATA IN A STORAGE SYSTEM WITH A FLASH CACHE - A storage device made up of multiple storage media is configured such that one such media serves as a cache for data stored on another of such media. The device includes a controller configured to manage the cache by consolidating information concerning obsolete data stored in the cache with information concerning data no longer desired to be stored in the cache, and erase segments of the cache containing one or more of the blocks of obsolete data and the blocks of data that are no longer desired to be stored in the cache to produce reclaimed segments of the cache. | 10-15-2015 |
20150294720 | STORAGE DEVICE WITH 2D CONFIGURATION OF PHASE CHANGE MEMORY INTEGRATED CIRCUITS - A storage device, apparatus, and method to write and/or read data from such storage device. The storage device, comprises a channel controller and phase change memory integrated circuits (PCM ICs) arranged in sub-channels, wherein each of the sub-channels comprises several PCM ICs connected by at least one data bus line, which at least one data bus line connects to the channel controller. The channel controller is configured to write data to and/or read data from the PCM ICs according to a matrix configuration of PCM ICs, wherein: a number of columns of the matrix configuration respectively corresponds to a number of the sub-channels, the sub-channels forming a channel, and a number of rows of the matrix configuration respectively corresponds to a number of sub-banks, the sub-banks forming a bank, wherein each of the sub-banks comprises PCM ICs that belong, each, to distinct sub-channels of the sub-channels. | 10-15-2015 |
20150301589 | NON-VOLATILE MEMORY SYSTEM, MEMORY CARD HAVING THE SAME, AND OPERATING METHOD OF NON-VOLATILE MEMORY SYSTEM - A non-volatile memory system includes a memory controller, where the memory controller includes a first region including a first memory that stores compressed code, and a second region including a second memory that stores decompressed code. Power supplied to the first region and the second region is controlled according to an operation mode of the non-volatile memory system. | 10-22-2015 |
20150301744 | MEMORY SYSTEM AND METHOD OF OPERATING THE SAME - A method of operating a memory system, which includes a memory controller and at least one non-volatile memory, includes storing, in the memory system, temperature-dependent performance level information received from a host disposed external to the memory system, setting an operation performance level of the memory system to a first performance level, operating the memory controller and the at least one non-volatile memory device according to the first performance level, detecting an internal temperature of the memory system, and changing the operation performance level of the memory system to a second performance level that is different from the first performance level. The operation performance level is changed by the memory controller of the memory system, and changing the operation performance level is based on the temperature-dependent performance level information and the detected internal temperature. | 10-22-2015 |
20150301748 | STORAGE OPERATING SYSTEM - A storage system includes a plurality of unit storages each including at least one flash memory chip. Performance of at least a first storage of the unit storages is monitored. A first type of request for the first storage is processed using a second storage of the unit storages, instead of using the first storage, if the performance monitoring indicates that the first unit storage has reached an end-of-life state. | 10-22-2015 |
20150301754 | Storage Module and Method for Configuring the Storage Module with Memory Operation Parameters - A storage module and method for configuring the storage module with memory operation parameters are provided. In one embodiment, a storage module is provided comprising a memory and a controller. The controller is configured to receive a selection of one of a plurality of sets of memory operation parameters stored in the storage module and perform at least one of a read operation and a write operation on the memory in accordance with the selected set of memory operation parameters. | 10-22-2015 |
20150301756 | MEMORY WITH MULTIPLE SELECTABLE SPECIFICATION GRADES AND OPERATING METHOD THEREOF - The present invention relates to a memory and operating method thereof, the memory can be selected more than one standard specification grade. The memory includes a plurality of storage bit units to store bits and some control units corresponding to the stored bits, and bit line WL control units which can store bits and a selector unit to control different grades of the memory. The selector unit to control different grades of the memory outputs selector signal to choose memory with different grades. The bit line WL control units storing bits control the bit line WL required for different specification grades according to the received signal of the selector unit with the same specification grade of the memory. To achieve the selection of different specification grades memory one corresponding WL bit line can be controlled at one time, or two corresponding WL bit lines can be controlled at the same time; or multiple corresponding WL bit lines can be controlled at the same time. The memory with compact structure can reduce the time of the product to the market, and reduce the cost of the chip for a wide application scope. | 10-22-2015 |
20150301760 | CORRECTION OF BLOCK ERRORS FOR A SYSTEM HAVING NON-VOLATILE MEMORY - Systems and methods are disclosed for correction of block errors for a system having non-volatile memory (“NVM”). In particular, the system can store a parity page per page-modulo, where a pre-determined number of pages of a block or a band of the NVM may be allocated as page-modulo XOR (“PMX”) parity pages. This can be a space efficient approach for recovering from single-block data errors such as, for example, single-page uncorrectable error-correcting codes (“uECCs”) and/or errors caused by word line shorts. | 10-22-2015 |
20150301907 | Storage Module and Method for Determining Whether to Back-Up a Previously-Written Lower Page of Data Before Writing an Upper Page of Data - A storage module and method are disclosed for determining whether to back-up a previously-written lower page of data before writing an upper page of data. In one embodiment, a storage module receives a command to write an upper page of data to memory cells that have already been programmed with a lower page of data. The storage module determines whether a command to protect the lower page of data was previously received. The storage module backs-up the lower page of data in another area of the memory before writing the upper page of data to the memory cells only if it is determined that the command to protect the lower page of data was previously received. The storage module then writes the upper page of data to the memory cells. | 10-22-2015 |
20150301934 | FLASH-BASED DATA STORAGE WITH DUAL MAP-BASED SERIALIZATION - A RAID storage system serializes data blocks to be stored in a RAID storage array and uses a primary map table and a number of secondary map tables to relate host addresses to logical block addresses in the storage array. Secondary map tables and other metadata can be cached from the storage array. The dual or two-tier map scheme and metadata caching promote scalability. | 10-22-2015 |
20150301935 | MICROCOMPUTER AND NONVOLATILE SEMICONDUCTOR DEVICE - A program counter ( | 10-22-2015 |
20150301936 | INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING TERMINAL, INFORMATION PROCESSING METHOD, AND PROGRAM - An information processing apparatus which stores process target data in a non-volatile memory, cancels a writing distribution function with respect to the non-volatile memory according to a job input to the information processing apparatus or a mode of the information processing apparatus, and can efficiently perform overwrite erasure. | 10-22-2015 |
20150301937 | WEAR LEVELING FOR A MEMORY DEVICE - Methods of operating a memory device are useful in managing wear leveling operations. Such methods include receiving an instruction from a host device in communication with the memory device, wherein the instruction comprises a command portion indicating a desire to identify portions of the memory device to be excluded from wear leveling operations and an argument portion comprising information identifying a particular group of one or more blocks of the plurality of blocks; storing the information identifying the particular group of one or more blocks to a non-volatile memory of the memory device as a portion of information identifying blocks to be excluded from wear leveling operations; and performing one or more wear leveling operations only on a subset of the plurality of blocks responsive to the information identifying blocks to be excluded from wear leveling operation | 10-22-2015 |
20150301938 | LBA BITMAP USAGE - Systems and methods are disclosed for logical block address (“LBA) bitmap usage for a system having non-volatile memory (“NVM”). A bitmap can be stored in volatile memory of the system, where the bitmap can store the mapping statuses of one or more logical addresses. By using the bitmap, the system can determine the mapping status of a LBA without having to access the NVM. In addition, the system can update the mapping status of a LBA with minimal NVM accesses. By reducing the number of NVM accesses, the system can avoid triggering a garbage collection process, which can improve overall system performance. | 10-22-2015 |
20150301941 | SYSTEM AND METHOD INCLUDING THREE DIMENSIONAL NONVOLATILE MEMORY DEVICE AND RANDOM ACCESS MEMORY - A program method for a memory system including a three-dimensional nonvolatile memory having multi-level memory cells and a random access memory. The method uses the random access memory to variously store selected bits of multi-bit data during the programming of a row of memory cells in the three-dimensional nonvolatile memory. | 10-22-2015 |
20150301958 | Field Lockable Memory - The present principles relate to a method of imprinting new identifying information to a flash memory device. The method includes receiving, at a flash memory, a new identifying information to be written to the flash memory, the flash memory having a plurality of sectors and a pointer associated therewith, the plurality of sectors including a locked first sector that includes previously written identifying information, the pointer including an address of the first sector; writing the new identifying information to a second sector of the plurality of sectors, the second sector being open and lockable; and locking the second sector. | 10-22-2015 |
20150309727 | DEVICE AND METHOD OF INTERFACE BETWEEN DEVICES OR INPUT/OUTPUT PERIPHERALS AND ELECTRONIC COMPUTERS - An electronic device ( | 10-29-2015 |
20150309728 | MEMORY SYSTEM AND METHOD FOR CONTROLLING A NONVOLATILE SEMICONDUCTOR MEMORY - A memory system includes a nonvolatile semiconductor memory having blocks, the block being data erasing unit; and a controller configured to execute; an update processing for; writing superseding data in a block, the superseding data being treated as valid data; and invalidating superseded data having the same logical address as the superseding data, the superseded data being treated as invalid data; and a compaction processing for; retrieving blocks having invalid data using a management table, the management table managing blocks in a linked list format for each number of valid data included in the block; selecting a compaction source block having at least one valid data from the retrieved blocks; copying a plurality of valid data included in the compaction source blocks into a compaction target block; invalidating the plurality of valid data in the compaction source blocks; and releasing the compaction source blocks in which all data are invalidated. | 10-29-2015 |
20150309729 | APPLICATION-TRANSPARENT HYBRIDIZED CACHING FOR HIGH-PERFORMANCE STORAGE - Systems, apparatus, and computer-implemented methods are provided for the hybridization of cache memory utilizing both magnetic and solid-state memory media. A solid-state cache controller apparatus can be coupled to a host computing system to maximize efficiency of the system in a manner that is transparent to the high-level applications using the system. The apparatus includes an associative memory component and a solid-state cache control component. Solid-state memory is configured to store data blocks of host read operations. If a host-read operation is requested, the controller communicates with a solid-state cache memory controller to determine whether a tag array data structure indicates a cached copy of the requested data block is available in solid-state memory. | 10-29-2015 |
20150309732 | Selectively Configuring Hard-Disk Drive System - In one embodiment of the disclosure, a hard-disk drive (HDD) controller for an HDD system is selectively configurable to operate with a first type of host system having a first logical block size and a second type of host system having a second logical block size, different from the first logical block size. Another embodiment of the disclosure is a method implemented by the HDD system. | 10-29-2015 |
20150309737 | MEMORY SYSTEM AND METHOD OF OPERATING THE MEMORY SYSTEM - According to example embodiments, a memory system includes a memory device and a memory controller configured to control the memory device. The memory device includes a plurality of memory cells. The memory controller includes a storage unit configured to sequentially store a plurality of commands received from a host, a distance determination unit configured to determine a distance between a program command and a read command, associated with the same word line, from among the plurality of commands stored in the storage unit, and a read voltage determination unit configured to determine a read voltage level corresponding to the read command based on the determined distance. | 10-29-2015 |
20150309752 | Storage System Power Management Using Controlled Execution of Pending Memory Commands - The various embodiments described herein include methods and/or systems for throttling power in a storage device. In one aspect, a method of operation in a storage system includes obtaining a power metric corresponding to a count of active memory commands in the storage system, where active memory commands are commands being executed by the storage system. The method further includes, in accordance with a determination that the power metric satisfies one or more power thresholds, deferring execution of one or more pending memory commands. | 10-29-2015 |
20150309753 | Memory Control System for a Non-Volatile Memory and Control Method - A memory control system for controlling read and write operations of a non-volatile memory, wherein the memory control system comprises a memory controller that is adapted to implement a write operation for writing at least one block of data to the memory as a sequence of memory write and validation cycles for part of all of the data. In one example, the number of cycles is a function of the amount of successfully written data per cycle and is thus variable in dependence on the success of the data writing. The system also includes a power management unit, which is adapted to authorize or prevent the memory controller from conducting the write operation at the level of the write cycles thereby to control the timing of power consumption resulting from the cycles of the write operation. | 10-29-2015 |
20150309924 | CONTROL APPARATUS AND CONTROL METHOD WITH MULTIPLE FLASH MEMORY CARD CHANNELS - A control apparatus with multiple flash memory card channels includes a host side port unit, an instruction data processing unit, and flash memory card port units. The host side port unit exchanges a host side instruction and host side read/write data with a high-speed serial communication protocol host side. The flash memory card port units respectively exchange flash memory card instructions and flash memory card read/write data with a plurality of flash memory cards. An instruction from the high-speed serial communication protocol host side is divided into multiple sub-instructions to be respectively transmitted to the flash memory card port units and exchange of instruction and data with a plurality of flash memory cards is carried out in a coincident period of time so as to achieve the purposes of expanding access capacity and increasing access speed, reducing the operation cost of products, and enhancing flexibility of use of flash memory cards. | 10-29-2015 |
20150309925 | METHOD FOR COMPLETING A SECURE ERASE OPERATION - A system that may reliably erase a storage device, such as a solid state drive. The system issues an erasure command to the storage device. Such a command may be issued over a bus connecting a processing unit to one or more storage devices to be erased. The system, including the storage device, may be prepared for the erasure operation via performing one or more operations. Those operations may include: using hardware of the system to initiate a hard reset of the storage device; preventing access to the storage device while the erasure operation is being performed; and/or erasing hidden areas on the storage device. The system may be configured to perform the hard reset and may be configured not to alter a command to perform secure erase. Further, the erasure process may include writing a signature to certain areas of the storage device to confirm that erasure was performed. | 10-29-2015 |
20150309926 | FLEXIBLE WEAR MANAGEMENT FOR NON-VOLATILE MEMORY - Systems and methods of memory cell wear management that can achieve a more uniform distribution of write cycles across a memory cell address space. The systems and methods allow physical addresses of memory cells subjected to a high number of write cycles to be swapped with physical addresses of memory cells subjected to a lower number of write cycles. The physical address of a group of memory cells is a “hot address” if the write cycle count for that memory cell group exceeds a specified threshold. If the write cycle count for a group of memory cells does not exceed the specified threshold, then the physical address of that memory cell group is a “cold address”. The systems and methods allow the specified threshold of write cycle counts to be dynamically incremented to assure that cold addresses are available for swapping with hot addresses in the memory cell address space. | 10-29-2015 |
20150309927 | Hybrid Non-Volatile Memory System - A hybrid non-volatile system uses non-volatile memories based on two or more different non-volatile memory technologies in order to exploit their relative advantages. In an exemplary embodiment, the memory system includes a controller and a flash memory, where the controller has a non-volatile RAM based on an alternate technology such as FeRAM. The flash memory is used for the storage of user data and the non-volatile RAM in the controller is used for system control data. The use of an alternate non-volatile memory technology in the controller allows for a non-volatile copy of the most recent control data to be accessed more quickly as it can be updated on a bit by bit basis. In another exemplary embodiment, the alternate non-volatile memory is used as a cache where data can safely be staged prior to its being written to the memory or read back to the host. | 10-29-2015 |
20150309928 | METADATA REDUNDANCY SCHEMES FOR NON-VOLATILE MEMORIES - Systems and methods are provided for storing data to or reading data from a non-volatile memory (“NVM”), such as flash memory, using a metadata redundancy scheme. In some embodiments, an electronic device, which includes an NVM, may also include a memory interface for controlling access to the NVM. The memory interface may receive requests to write user data to the NVM. The user data from each request may be associated with metadata, such as a logical address, flags, or other data. In response to a write request, the NVM interface may store the user data and its associated metadata in a first memory location (e.g., page), and may store a redundant copy of the metadata in a second memory location. This way, even if the first memory location becomes inaccessible, the memory interface can still recover the metadata from the backup copy stored in the second memory location. | 10-29-2015 |
20150309932 | WRITE ADMITTANCE POLICY FOR A MEMORY CACHE - A method includes monitoring a number of read access requests to an address for data stored on a backing store. The method also includes comparing the number of read access requests to a read access threshold. The read access threshold includes a threshold number of read access requests for the address. The method also includes caching data corresponding to a write access request to the address in response to determining that the number of read access requests satisfies the read access threshold. | 10-29-2015 |
20150309933 | APPARATUS, SYSTEM, AND METHOD FOR MANAGING EVICTION OF DATA - An apparatus, system, and method are disclosed for managing eviction of data. A cache write module stores data on a non-volatile storage device sequentially using a log-based storage structure having a head region and a tail region. A direct cache module caches data on the non-volatile storage device using the log-based storage structure. The data is associated with storage operations between a host and a backing store storage device. An eviction module evicts data of at least one region in succession from the log-based storage structure starting with the tail region and progressing toward the head region. | 10-29-2015 |
20150310913 | ELECTRONIC DEVICE - Provided are, among others, memory circuits or devices and their applications in electronic devices or systems and various implementations of an electronic device which includes a semiconductor memory unit comprising one or more columns and a date line and a data line bar connected with a column selected among the one or more columns. Each of the one or more columns includes a plurality of storage cells each configured to store 1-bit data, each storage cell including a first and second variable resistance elements; a bit line and a source line connected to the first variable resistance element; connected to the other end of the first variable resistance element; a bit line bar and a source line bar connected to the second variable resistance element; and a driving block configured to latch data of the data line and the data line bar. | 10-29-2015 |
20150310916 | NONVOLATILE MEMORY SYSTEM - A nonvolatile memory system is provided. The memory system includes a nonvolatile memory device and a memory controller. The memory controller transmits first to fourth control signals to the nonvolatile memory device, sends a command, an address, and input data via a data bus, and receives output data via the data bus. The nonvolatile memory device receives the first to fourth control signals, and recognizes signals received via the data bus at a rising edge or a falling edge of the fourth control signal, as one of the command, the address, and the input data in response to the first to third control signals, and transfers the output data to the memory controller via the data bus based on the fourth control signal. | 10-29-2015 |
20150310937 | METHODS AND SYSTEMS INCLUDING AT LEAST TWO TYPES OF NON-VOLATILE CELLS - Methods and systems that include receiving data to be written to a NAND array in a controller; and writing the data to the NAND array, the NAND array including both type A NAND cells and type B NAND cells, wherein the type A NAND cells and the type B NAND cells have at least one structural difference. | 10-29-2015 |
20150317079 | COORDINATING REPLICATION OF DATA STORED IN A NON-VOLATILE MEMORY-BASED SYSTEM - A technique includes, in response to a first stream of writes to a first non-volatile memory system, generating a second stream of writes for a second non-volatile memory system; and coordinating replication of data stored in the first non-volatile memory system. The coordinating includes embedding at least one command in the second stream of writes to create a synchronization point for data storage in the second non-volatile memory system in response to at least one corresponding command in the first stream to create a synchronization point for data storage in the first non-volatile memory system. | 11-05-2015 |
20150317080 | APPARATUS INCLUDING MEMORY SYSTEM CONTROLLERS AND RELATED METHODS - Memory system controllers can include non-volatile memory control circuitry including a plurality of channel control circuits. Each of the plurality of channel control circuits can be configured to be coupled to a respective number of logical units (LUNs). Memory management circuitry can be coupled to the non-volatile memory control circuitry and configured to allocate a write block cluster for host writes based on an information width of a host bus and a protocol of the host bus. The write block cluster can include one block from fewer than all of the LUNs. | 11-05-2015 |
20150317083 | Synergetic deduplication - Flash memory devices can be implemented with deduplication mechanism through a synergetic deduplication mapping that combines the logical-to-physical address mapping of the flash memory devices with the deduplication mapping. A deduplication algorithm can be implemented in the application layer, which can freely communicate with the flash memory devices and perform computationally expensive operations. | 11-05-2015 |
20150317088 | SYSTEMS AND METHODS FOR NVME CONTROLLER VIRTUALIZATION TO SUPPORT MULTIPLE VIRTUAL MACHINES RUNNING ON A HOST - A new approach is proposed that contemplates systems and methods to virtualize a physical NVMe controller associated with a computing device or host so that every virtual machine running on the host can have its own dedicated virtual NVMe controller. First, a plurality of virtual NVMe controllers are created on a single physical NVMe controller, which is associated with one or more storage devices. Once created, the plurality of virtual NVMe controllers are provided to VMs running on the host in place of the single physical NVMe controller attached to the host, and each of the virtual NVMe controllers organizes the storage units to be accessed by its corresponding VM as a logical volume. As a result, each of the VMs running on the host has its own namespace(s) and can access its storage devices directly through its own virtual NVMe controller. | 11-05-2015 |
20150317090 | System and Method of Life Management for Low Endurance SSD NAND Devices Used as Secondary Cache - A system and method for managing the life expectancy of at least one solid state drive (SSD) within a cache device of a storage subsystem includes determining a baseline rate of decline for each SSD based on its guaranteed life expectancy. At intervals, each SSD of the cache device is polled for remaining life and power-on time, and a current rate of decline (based on time since initialization) and a cumulative rate of decline (based on total lifespan of the SSD) is determined. When both the current rate of decline and the cumulative rate of decline exceed the baseline rate of decline for any SSD of the cache device, write requests to that SSD are blocked and redirected to the virtual device until either the current rate of decline or cumulative rate of decline drop below the baseline rate. | 11-05-2015 |
20150317091 | SYSTEMS AND METHODS FOR ENABLING LOCAL CACHING FOR REMOTE STORAGE DEVICES OVER A NETWORK VIA NVME CONTROLLER - A new approach is proposed that contemplates systems and methods to support mapping/importing remote storage devices as NVMe namespace(s) via an NVMe controller using a storage network protocol and utilizing one or more storage devices locally coupled to the NVMe controller as caches for fast access to the mapped remote storage devices. The NVMe controller exports and presents the NVMe namespace(s) of the remote storage devices to one or more VMs running on a host attached to the NVMe controller. Each of the VMs running on the host can then perform read/write operations on the logical volumes. During a write operation, data to be written to the remote storage devices by the VMs is stored in the locally coupled storage devices first before being transmitted over the network. The locally coupled storage devices may also cache data intelligently pre-fetched from the remote storage devices based on reading patterns and/or pre-configured policies of the VMs in anticipation of read operations. | 11-05-2015 |
20150317094 | Non-Volatile Storage Systems with Go To Sleep Adaption - A non-volatile memory system goes into a low-power standby sleep mode to reduce power consumption if a host command is not received within delay period. The duration of this delay period is adjustable. In one set of embodiments, host commands can specify the delay value, the operation types to which it applies, and whether the value is power the current power session or to be used to reset a default value as well. In other aspects, the parameters related to the delay value are kept in a host resettable parameter file. In other embodiments, the memory system monitors the time between host commands and adjusts this delay automatically. | 11-05-2015 |
20150317097 | DE-DUPLICATION IN FLASH MEMORY MODULE - Data capacity efficiency is improved by de-duplicating data assigned with a code that is different for each data. A storage apparatus comprising a flash memory control device equipped with one or more flash memory modules, wherein the flash memory module comprises at least one flash memory chip for providing a storage area, and a controller for controlling writing/reading of data including user data and a guarantee code accompanying the user data to and from the storage area provided by the flash memory chip, wherein the controller respectively divides a plurality of the data having the common user data into the user data and the guarantee code, stores one of the user data in an area of a predetermined unit of the storage area, and links and stores each of the guarantee codes accompanying the plurality of user data in an area of a predetermined unit of the storage area. | 11-05-2015 |
20150317102 | MEMORY SYSTEM IN WHICH EXTENDED FUNCTION CAN EASILY BE SET - According to one embodiment, a memory system, such as a SDIO card, includes a nonvolatile semiconductor memory device, a control section, a memory, an extended function section, and an extension register. The extended function section is controlled by the control section. A first command reads data from the extension register in units of given data lengths. A second command writes data to the extension register in units of given data lengths. A extension register includes a first area, and second area different from the first area, information configured to specify a type of the extended function and controllable driver, and address information indicating a place to which the extended function is assigned, the place being on the extension register, are recorded in the first area, and the second area includes the extended function. | 11-05-2015 |
20150317245 | BIDIRECTIONAL COUNTER IN A FLASH MEMORY - A method of storing a counter in at least two non-volatile memory pages, including: a step of initializing a page with an initial value and then, on each update of the counter value, a step of storing an update value and an opcode associated with this value, selected from a set of opcodes, the current value of the counter being given by application of the successive update operations to the initial value of the page. | 11-05-2015 |
20150317258 | SEMICONDUCTOR DEVICE AND DATA PROCESSING METHOD - A semiconductor device has: as security states to which the nonvolatile memory device can transition, an unprotected state in which, when secret information is not set in the nonvolatile memory device, rewriting the nonvolatile memory device is permitted, and reading the stored information is permitted; a protection unlocked state in which, when the secret information is set in the nonvolatile memory device, rewriting the nonvolatile memory device is permitted on condition that a result of authentication using the secret information is correct, and reading the stored information is permitted; and a protection locked state in which, when the secret information is set in the nonvolatile memory device, rewriting the nonvolatile memory device is inhibited until correctness as a result of authentication using the secret information is confirmed, and reading the stored information is inhibited under a predetermined condition. | 11-05-2015 |
20150318049 | TAG-BASED IMPLEMENTATIONS ENABLING HIGH SPEED DATA CAPTURE AND TRANSPARENT PRE-FETCH FROM A NOR FLASH - Embodiments disclosed herein generally relate for efficiently retrieving boot code for a processor from serial NOR flash memory. When a boot code request is received, a request handler in data capture logic tags successive address read requests to indicate whether the requests indicate contiguous addresses in the NOR flash memory for the boot code. Different circuitry in the data capture logic operates on different mesochronous clock signals. One clock signal drives the capture of boot code from NOR flash, and the other controls synchronized tagging, storing, pre-fetching, and transmitting of the captured boot code data. | 11-05-2015 |
20150324119 | Method and System for Improving Swap Performance - A method and system for improving swap performance are provided. In one embodiment, a computing device is provided with a volatile memory and a non-volatile memory, wherein the non-volatile memory has a first swap area with multi-level cell (MLC) memory and a second swap area with single-level cell (SLC) memory. One of the characteristics of SLC memory is that data is written more quickly in the SLC memory than the MLC memory. A determination is made whether the computing device is operating in normal mode or burst mode. If it is determined that the computing device is operating in normal mode, data is moved from the volatile memory to the first swap area during a swap operation. If it is determined that the computing device is operating in burst mode, data is moved from the volatile memory to the second swap area during a swap operation. | 11-12-2015 |
20150324120 | Method and Computing Device for Controlling Bandwidth of Swap Operations - The following embodiments generally relate to the use of a “swap area” in a non-volatile memory as an extension to volatile memory in a computing device. These embodiments include techniques to use both volatile memory and non-volatile swap memory to pre-load a plurality of applications, to control the bandwidth of swap operations, to encrypt data stored in the swap area, and to perform a fast clean-up of the swap area. | 11-12-2015 |
20150324121 | HYBRID-HDD THAT GIVES UP OLD NAND DATA AT THE LAST MOMENT - A method and a system are provided for improving performance of a hybrid drive including a non-volatile semiconductor memory device partitioned into blocks, each of the blocks containing a plurality of sectors, and a magnetic storage device. Performance of the hybrid drive is improved by tracking data types of each sector stored in the blocks, the data types including a first data type, which is data that is unconditionally available for host accesses, a second data type, which is data that is conditionally available for host accesses, and a third data type, which is data unavailable for host accesses, and collecting erasable blocks from the blocks of the non-volatile semiconductor memory device according to the data types. The erasable blocks include a block that contains data of the second data type, such that the host may access from this block even though this block is erasable. | 11-12-2015 |
20150324122 | SEMICONDUCTOR MEMORY DEVICE, SEMICONDUCTOR SYSTEM AND READING METHOD - The invention provides a flash memory which may effectively protect information with a high security level. A flash memory includes a setting part. When the setting part is inputted a specific command, the setting part sets up specific address information to a nonvolatile configuration register, and sets up specific data in a hidden storage region. The flash memory also includes: a comparing part, which compares inputted address information and the specific address information during a reading operation; and a control part, which reads specific data set in the storage region and erases a specific address when two address information are consistent, and reads data stored in a memory array according to the inputted address information when two address information are inconsistent. | 11-12-2015 |
20150324124 | CLUSTER SOLID STATE DRIVES - Described herein are techniques for arranging a plurality of M.2 solid state drive (SSD) modules and flash storage elements into a compact form factor. On a first side of an SSD sled, a plurality of M.2 SSD modules may be communicatively coupled to a port expander. On a second side of the SSD sled, a plurality of flash storage elements (not packaged into M.2 SSD modules) may be present. A plurality of SSD sleds (with the above-described characteristics) may be sized so as to collectively fit into a single hard disk drive (HDD) compatible compartment of a chassis. | 11-12-2015 |
20150324125 | STORAGE COMPUTE DEVICE WITH TIERED MEMORY PROCESSING - A data object is received at a storage compute device in response to a request from a host. A requirement of the data object is determined based on a computation to be performed on the data object. The requirement related to at least speed and capacity of media used to store the data object. A tier is selected from the storage compute device based on speed and capacity characteristics of the selected tier corresponding to the requirement of the data object. The data object is stored in the selected tier. | 11-12-2015 |
20150324142 | MEMORY DEVICE, ELECTRONIC SYSTEM, AND METHODS ASSOCIATED WITH MODIFYING DATA AND A FILE OF A MEMORY DEVICE - A memory device, system and method of editing a file in a non-volatile memory device is described. The memory device includes a controller and a memory array configured to copy an existing first file into a second file during editing and to maintain the first file while applying edits to the second file. When editing is completed, a first cluster pointer of the first file is redirected to point at the first cluster of the second file that has been edited. | 11-12-2015 |
20150324148 | PROCESSING SHAPED DATA - Systems and methods of processing shaped data to include selectively performing a modification operation. The modification operation may be performed in response to determining that shaped data satisfies one or more shaping adjustment criteria. Shaping of data may be discontinued to at least a portion of a memory based on a health metric for the portion satisfying a threshold. | 11-12-2015 |
20150324280 | FLASH COPY RELATIONSHIP MANAGEMENT - For flash copy relationship management, a management module identifies a data unit in a flash copy relationship with an extent range using a flash copy table. A resolution module erases the flash copy relationship from the flash copy table in response to the flash copy relationship completing. | 11-12-2015 |
20150324281 | SYSTEM AND METHOD OF IMPLEMENTING AN OBJECT STORAGE DEVICE ON A COMPUTER MAIN MEMORY SYSTEM - A system and method for implementing an object storage device is disclosed. According to one embodiment, the system includes a first controller configured to interface with a main memory controller of a computer system to receive a data object and a first request for storing the data object, the first request including a key value. The system also includes a second controller configured to: allocate memory in one or more non-volatile memory storage units for storing the data object, store the data object in the allocated memory, and maintain an association between the key value and allocated memory. | 11-12-2015 |
20150324284 | NONVOLATILE MEMORY SYSTEM INCLUDING NONVOLATILE MEMORY DEVICE AND MEMORY CONTROLLER AND METHOD OF OPERATING THE MEMORY CONTROLLER - A method of operating a memory controller controlling a nonvolatile memory device including a user area and a meta area is provided. The method includes selecting a source block among a plurality of memory blocks included in the user area, loading a mapping table stored in the meta area on the basis of a sub-bitmap of the selected source block, and generating a valid page layout constituted by valid pages among pages included in the source block on the basis of the loaded mapping table. The sub-bitmap includes information of a valid mapping table with respect to the selected source block. | 11-12-2015 |
20150324296 | BUFFER MANAGEMENT STRATEGIES FOR FLASH-BASED STORAGE SYSTEMS - Techniques are generally described related to a flash-based buffer management strategy. One example method to manage a buffer for a computer system may include maintaining a page-action list for monitoring a plurality of operations being executed on the computer system and utilizing a plurality of buffer pages of the buffer. An example page-action list may contain a hot-access queue for recently accessed buffer pages and a cold-access queue for less accessed buffer pages. The example method may also include, upon a determination that the buffer is full, identifying a victim buffer page from the plurality of buffer pages for eviction and evicting the victim buffer page from the buffer. The victim buffer page may be selected from the cold-access queue and based on a page weight, which is calculated based on a page state of the specific buffer page and a page hotness prediction for the specific buffer page might be accessed by an incoming operation. | 11-12-2015 |
20150331607 | SYSTEM AND METHOD FOR SIMULATING A PERSISTENT BYTE ADDRESSABLE STORAGE DEVICE ON A PERSISTENT BLOCK ADDRESSABLE STORAGE DEVICE - A persistent random-access, byte-addressable storage device may be simulated on a persistent random-access, block-addressable storage device of a storage system configured to enable asynchronous buffered access to information persistently stored on the block-addressable device. Buffered access to the information is provided, in part, by a portion of kernel memory within the storage system allocated as a staging area for the simulated byte-addressable storage device to temporarily store the information destined for persistent storage. One or more asynchronous interfaces may be employed by a user of the simulated byte-addressable device to pass metadata describing the information to a driver of the device, which may process the metadata to copy the information to the staging area. The driver may organize the staging area as one or more regions to facilitate buffering of the information (data) prior to persistent storage on the block-addressable storage device. Each asynchronous access interface is configured to ensure that an order of changes to the data in the persistent storage is consistent with the order of arrival of the changes at the driver. | 11-19-2015 |
20150331611 | SYSTEM AND METHOD FOR DIGITAL SIGNALING AND DIGITAL STORAGE - Systems and methods for storing and/or communicating digital data associated with amplitudes and phases of a virtual periodic waveform having a designated period between components include, in one embodiment, circuitry that converts a first amplitude and a first phase to a first corresponding voltage or current and applies the first corresponding voltage or current to a first one of the plurality of components, such as conductors connecting integrated circuit chips or capacitors of a DRAM device, and converts the first amplitude and the first phase to (n−1) corresponding voltages or currents based on amplitudes of the periodic waveform phase shifted by about m*(360/n) relative to the first phase where m is indexed from one to (n−1) and applies each corresponding voltage or current to an associated component. Decoding is performed by comparing magnitudes of the component signals relative to one another rather that to a plurality of thresholds. | 11-19-2015 |
20150331615 | MULTI-ELEMENT SOLID-STATE STORAGE DEVICE MANAGEMENT - The present disclosure describes various techniques related to control of solid state drives. | 11-19-2015 |
20150331620 | METHOD OF SECURELY ERASING A NON-VOLATILE SEMICONDUCTOR MASS MEMORY, COMPUTER SYSTEM, AND COMPUTER PROGRAM PRODUCT - A method of securely erasing a non-volatile semiconductor mass memory has a plurality of physical memory units assigned either to a first memory area which can be addressed via an interface of the semiconductor mass memory or to a second memory area which cannot be addressed via the interface, and a controller that changes assignment of the memory units to the first memory area and to the second memory area according to an algorithm that produces wear leveling upon receiving a command to overwrite memory units assigned to the first memory area via the interface. | 11-19-2015 |
20150331624 | HOST-CONTROLLED FLASH TRANSLATION LAYER SNAPSHOT - A flash translation layer (FTL) map stored in the non-volatile portion of a solid-state drive is updated when a firmware flag indicates the contents of this FTL map are not consistent with the contents of an FTL map stored in a volatile memory device of the SSD (e.g., the drive DRAM). Given this flag indication, the solid-state drive may copy the contents of the FTL map stored in the drive DRAM to the non-volatile portion of the SSD under various circumstances, including when a host command to flush the updated data structure is received, when a link state between the data storage device and the host changes, when a power connection to the data storage device is broken, or upon receiving a host command to go into a sleep state or a lower power state. | 11-19-2015 |
20150331625 | MEMORY SYSTEM AND METHOD OF CONTROLLING MEMORY SYSTEM - According to one embodiment, a memory system includes a nonvolatile memory including a plurality of blocks, and a controller controlling the nonvolatile memory. The controller cyclically executes patrol read, the patrol read including reading data and testing the read data, the read data being data of pages connected to some of word lines in each of the blocks of the nonvolatile memory. | 11-19-2015 |
20150331626 | In-Situ Block Folding for Nonvolatile Memory - In a nonvolatile memory, hybrid blocks are initially written with only lower page data. The hybrid blocks later have middle and upper page data written. For high speed writes, data is written to a hybrid block and two or more Single Level Cell (SLC) blocks. The data from the SLC blocks are copied to the hybrid block at a later time in a folding operation. | 11-19-2015 |
20150331627 | NONVOLATILE MEMORY DEVICE AND OPERATION METHOD OF STORAGE DEVICE INCLUDING THE NONVOLATILE MEMORY DEVICE - A method of operating a storage device having a nonvolatile memory including at least one memory block having a plurality of sub-blocks includes reading backup data of backup memory cells having a highest program state among a plurality of memory cells connected to at least one word line of a sub-block which is not erase-requested adjacent to an erase-requested sub-block among the sub-blocks. The method includes storing the backup data, erasing the erase-requested sub-block, and reprogramming the backup memory cells having the highest program state on the basis of the backup data. | 11-19-2015 |
20150331628 | MEMORY SWAPPING METHOD, AND HOST DEVICE, STORAGE DEVICE, AND DATA PROCESSING SYSTEM USING THE SAME - A memory swapping method and a data processing system using the same, the memory swapping method including receiving queue information for a memory swapping task from a host device; performing part of the memory swapping task in a storage device based on the queue information; receiving a command corresponding to the queue information from the host device after performing of the part of the memory swapping task is completed; and performing a remaining part of the memory swapping task according to the command by using a result of the part of the memory swapping task that had been previously performed. | 11-19-2015 |
20150331637 | VIBRATION MITIGATION FOR A DATA STORAGE DEVICE - Vibration mitigation for a Data Storage Device (DSD) including a disk for storing data and a solid-state memory for storing data. An input is received indicating a vibration condition for the DSD and a write command is received from a host to store data in the DSD. At least a portion of the data for the write command is stored in a dedicated segment of the solid-state memory based on the received input indicating the vibration condition. | 11-19-2015 |
20150331790 | INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, AND STORAGE MEDIUM - In a non-volatile memory such as a NAND flash memory, notification of an area that is no longer needed is provided by a TRIM command, and deletion of the unneeded area is executed by garbage collection. The TRIM command and execution of the garbage collection are detected, and notification thereof is provided, whereby the user can confirm that the data on a solid state drive is invalidated. | 11-19-2015 |
20150331791 | FAST BLOCK DEVICE AND METHODOLOGY - A device, memory, method and system directed to fast data storage on a block storage device. New data is written to an empty write block. A location of the new data is tracked. Meta data associated with the new data is written. A lookup table may be updated based in part on the meta data. The new data may be read based the lookup table configured to map a logical address to a physical address. | 11-19-2015 |
20150331792 | MEMORY DEVICES WITH REGISTER BANKS STORING ACTUATORS THAT CAUSE OPERATIONS TO BE PERFORMED ON A MEMORY CORE - A bus controller has a displacer, an arithmetic logic unit coupled to the displacer, and a replacer selectively coupled to the displacer and the arithmetic logic unit. | 11-19-2015 |
20150331806 | MANAGING ASYMMETRIC MEMORY SYSTEM AS A CACHE DEVICE - Some implementations provide a method for managing data in a storage system that includes a persistent storage device and a non-volatile random access memory (NVRAM) cache device. The method includes: accessing a direct mapping between a logical address associated with data stored on the persistent storage device and a physical address on the NVRAM cache device; receiving, from a host computing device coupled to the storage system, a request to access a particular unit of data stored on the persistent storage device; using the direct mapping as a basis between the logical address associated with the data stored on the persistent storage device and the physical address on the NVRAM cache device to determine whether the particular unit of data being requested is present on the NVRAM cache device. | 11-19-2015 |
20150339057 | NONVOLATILE MEMORY SYSTEM AND OPERATION METHOD OF A MEMORY CONTROLLER - A nonvolatile memory system includes a nonvolatile memory device and a memory controller. The nonvolatile memory device includes memory blocks each having a plurality of pages and performs a read operation on the plurality of pages on the basis of read voltages. The memory controller is configured to manage page serial numbers of some of the plurality of pages according to a program elapsed time of each of the plurality of pages. When the memory controller receives a read command and a logical address from an external device, the memory controller is configured to select at least one of the managed page serial numbers, to compare the selected at least one of the page serial numbers with a page serial number of a page corresponding to the received logical address, and to control levels of the read voltages according to a comparison result. | 11-26-2015 |
20150339058 | STORAGE SYSTEM AND CONTROL METHOD - A storage controller stores a data block related to a received write command in a first cache memory as an undefined state, and transmits, to a storage device, an undefining write command of requesting to store the data block as an undefined state, the undefining write command being a command associated with an address of a target logical area corresponding to a write destination according to the write command. The storage device has a non-volatile memory configured by a plurality of physical areas, stores a data block related to the undefining write command transmitted from the storage controller in an empty physical area of the plurality of physical areas, and assigns the physical area to the target logical area as a physical area in an undefined state. | 11-26-2015 |
20150339064 | READ CACHE MEMORY - The present disclosure includes methods and apparatuses for read cache memory. One apparatus includes a read cache memory apparatus comprising a first DRAM array, a first and a second NAND array, and a controller configured to manage movement of data between the DRAM array and the first NAND array, and between the first NAND array and the second NAND array. | 11-26-2015 |
20150339065 | ENHANCED DATA RELIABILITY USING SOLID-STATE MEMORY-ENABLED STORAGE DEVICES - Methods and systems for enhanced data reliability using solid-state memory-enabled storage devices may involve a solid-state hybrid drive (SSHD) with a safe zone in a solid-state memory. The safe zone may mirror a storage structure stored in a magnetic memory of the SSHD. When an error or failure in at least a portion of the magnetic memory occurs, the SSHD may continue to provide external access to the safe zone and may enable an information handling system to boot from the safe zone. | 11-26-2015 |
20150339066 | NON-VOLATILE COMPLEMENT DATA CACHE - The disclosed systems include features to mitigate a risk of data corruption attributable to unexpected power loss events. In particular, the disclosed system identifies and retrieves complement data associated with each received write command and stores the complement data in a non-volatile cache while the complement data is overwritten via execution of the write command. | 11-26-2015 |
20150339069 | MEMORY SYSTEM AND METHOD - According to one embodiment, a memory system includes a first memory, a second memory, and a processor. The second memory stores first management information and second management information. The first management information has an information that associates a logical address with a physical address. The second management information has an information which has a volume of valid data in each block included in the first memory. The controller updates the first management information and the second management information. When saving a differential data in the first memory, the controller stores the differential data and the second management information in one page of the first memory. The differential data is a difference between before and after update of the first management information. When restoring the second management information, the controller loads to the second memory the second management information stored in the first memory. | 11-26-2015 |
20150339070 | MEMORY CONTROLLER OPERATION - A memory controller controls a nonvolatile memory device including a plurality of user blocks and a plurality of reserved blocks. A ratio of the number of used reserved blocks among the reserved blocks during a predetermined period to an operation count during the predetermined period is calculated and an end of lifetime warning signal to an external device based on the calculated ratio is transmitted. Bad blocks among the user blocks are replaced by one or more of the reserved blocks If at least one block among the user blocks becomes a bad block, the memory controller replaces the bad block with any one of the reserved blocks, and the reserved block used indicates a reserved block replaced with at least one of the user blocks. The operation count can be, for example, an erase count of the nonvolatile memory device, a program count of the nonvolatile memory device, and/or a time count indicating usage time. | 11-26-2015 |
20150339075 | NON-VOLATILE MEMORY SYSTEMS AND METHODS OF MANAGING POWER OF THE SAME - A non-volatile memory system and a method of managing the power of the same are provided. The non-volatile memory system includes a non-volatile memory configured to store a first mapping table comprising a list of a logical address and a physical address corresponding to the logical address with respect to a code region and a list of a logical address and a physical address corresponding to the logical address with respect to a general purpose (GP) region, and a controller configured to load the first mapping table from the non-volatile memory to a first memory and load the second mapping table from the non-volatile memory to a second memory. Power-up of the second memory is delayed with respect to power-up of the non-volatile memory system and the first or second memory is powered down if a condition is satisfied, so that power consumption of the non-volatile memory system is reduced. | 11-26-2015 |
20150339198 | SEMICONDUCTOR MEMORY DEVICE INCLUDING NONVOLATILE SEMICONDUCTOR MEMORY, CONTROL METHOD OF MEMORY CONTROLLER, AND MEMORY CONTROLLER - In a semiconductor memory device of an embodiment, a backup section writes backup data to a memory. The backup data corresponds to management data which associates identification data of data written to the memory with a write position of the data. A first generator generates update data indicating an updating state when the management data is updated after the backup data is written to the memory. A second generator generates update accumulated data including the update data and past update data which has been generated before the update data and written to the memory. A writer writes the update accumulated data to the memory. A restoration section restores the management data based on the backup data read from the memory and the update accumulated data. | 11-26-2015 |
20150339223 | MEMORY SYSTEM AND METHOD - According to one embodiment, a memory system includes a nonvolatile semiconductor memory and a controller. The nonvolatile semiconductor memory includes a plurality of parallel operation elements each having a plurality of physical blocks. The controller drives the plurality of parallel operation elements in parallel. The controller associates each of a plurality of logical blocks with a plurality of physical blocks each belonging to different parallel operation elements. The controller levels, among the plurality of logical blocks, the numbers of Bad blocks included in the plurality of physical blocks being associated with each of the plurality of logical blocks. | 11-26-2015 |
20150339225 | MEMORY MANAGEMENT METHOD, MEMORY STORAGE DEVICE AND MEMORY CONTROL CIRCUIT UNIT - A memory management method, a memory storage device and a memory control circuit unit are provided. The memory management method includes: grouping a plurality of non-spare physical erasing units into a first physical erasing unit and a second physical erasing unit, and a data updating frequency of the first physical erasing unit is lower than the data updating frequency of the second physical erasing unit; selecting a third physical erasing unit from the physical erasing units belonging to the first physical erasing unit; selecting a fourth physical erasing unit from spare physical erasing units, and copying valid data stored in the third physical erasing unit to the fourth physical erasing unit. | 11-26-2015 |
20150339236 | FALSE POWER FAILURE ALERT IMPACT MITIGATION - A method includes receiving a signal indicating a loss of power, starting a timer, the timer configured to expire after a specific time period, copying, by a distributed storage system having volatile memory configured as a write cache, write cache data from the volatile memory to a solid state device, upon receiving the signal indicating the loss of power to the storage system, configuring, the solid state device as both a read cache and the write cache, performing a health test on the storage system upon receiving the signal indicating the loss of power, determining the loss of power as a false alarm if the timer expires and the storage system passes a health test on the storage system, and upon the timer expiring and the storage system passing the health test, copying the write cache data from the solid state device back to the volatile memory. | 11-26-2015 |
20150340099 | OPERATING METHOD OF STORAGE DEVICE - An operating method of a storage device which includes a nonvolatile memory is provided. The operating method includes performing a first program operation on selected memory cells of the nonvolatile memory and storing a first time when the first program operation is performed; and adjusting a program parameter according to a difference between the first time and a second time, and performing a second program operation on the selected memory cells using the adjusted program parameter, the second time being a time when the second program operation is performed. | 11-26-2015 |
20150347013 | Using Sub-Region I/O History to Cache Repeatedly Accessed Sub-Regions in a Non-Volatile Storage Device - Systems, methods and/or devices are used to enable using sub-region I/O history to cache repeatedly accessed sub-regions in a non-volatile storage device. In one aspect, the method includes (1) receiving a plurality of input/output (I/O) requests including read requests and write requests to be performed in a plurality of regions in a logical address space of a host, and (2) performing one or more operations for each region of the plurality of regions in the logical address space of the host, including, for each sub-region of a plurality of sub-regions of the region: (a) determining whether the sub-region is accessed more than a predetermined threshold number of times during a predetermined time period, and (b) if so, caching, from a storage medium of the storage device to a cache of the storage device, data from the sub-region. | 12-03-2015 |
20150347016 | INPUT/OUTPUT VIRTUALIZATION (IOV) HOST CONTROLLER (HC) (IOV-HC) OF A FLASH-MEMORY-BASED STORAGE DEVICE - An input/output virtualization (IOY) host controller (HC) (IOV-HC) of a flash-memory-based storage device is disclosed. In one aspect, an IOV-HC is coupled to input/output (I/O) clients via corresponding client register interfaces (CRIs), and is also coupled to a flash-memory-based storage device. The IOV-HC comprises transfer request list (TRL) slot offset registers indicating slots of a shared TRL that are assigned as base slots to each of the CRIs. The IOV-HC further comprises TRL slot count registers indicating how many slots of the shared TRL are assigned to each of the CRIs. When a transfer request (TR) directed to the flash-memory-based storage device is received from a CRI, the IOV-HC is configured to map the TR to a slot of the shared TRL based on a TRL slot offset register and a TRL slot count register of the plurality of TRL slot count registers corresponding to the CRI. | 12-03-2015 |
20150347017 | COMMAND TRAPPING IN AN INPUT/OUTPUT VIRTUALIZATION (IOV) HOST CONTROLLER (HC) (IOV-HC) OF A FLASH-MEMORY-BASED STORAGE DEVICE - Command trapping in an input/output virtualization (IOV) host controller (HC) (IOV-HC) of a flash-memory-based storage device is disclosed. In one aspect, an IOV-HC is configured to receive a request from a client register interface (CRI) of one of multiple input/output (I/O) clients. The IOV-HC inspects a content of the request prior to the request being passed to a transport protocol engine. Based on the content, the IOV-HC determines whether the request should be further processed or should be trapped. If the IOV-HC determines that the request should be trapped, the IOV-HC traps the request using a request trap. In some aspects, the IOV-HC generates an interrupt to a virtual machine manager (VMM) to notify the VMM that the request was trapped. In some aspects, the IOV-HC provides a response generation circuit to receive instructions from the VMM to generate a response to the CRI from which the trapped request originated. | 12-03-2015 |
20150347020 | SEMICONDUCTOR STORAGE DEVICE WITH VOLATILE AND NONVOLATILE MEMORIES TO ALLOCATE BLOCKS TO A MEMORY AND RELEASE ALLOCATED BLOCKS - A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second and third memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data outputted from the first memory area by a first management unit in the second memory area, and a third processing for storing data outputted from the first memory area by a second management unit in the third memory area. | 12-03-2015 |
20150347025 | HOST-CONTROLLED GARBAGE COLLECTION - In an array of solid-state drives (SSDs), SSDs in the array are each configured to initiate generation of additional erased memory blocks when an initiation command is received from a host or when the number of erased memory blocks in the SSD falls below a minimum threshold of erased memory blocks for the SSD. The minimum threshold value may be adjusted by the host. | 12-03-2015 |
20150347026 | METHOD AND SYSTEM FOR INTERLEAVING PIECES OF A MAPPING TABLE FOR A STORAGE DEVICE - A method and system are disclosed for handling logical-to-physical mapping in a storage device. The method includes the storage device storing in fast access memory, such as DRAM, only a fixed-size subset of the primary mapping table in non-volatile memory, along with contiguity information of physical addresses for logical address not in the subset that are adjacent to the logical addresses in the subset. The system includes a storage device having volatile memory, non-volatile memory and a controller in communication with the volatile and non-volatile memory that is configured to carry out the method noted above. | 12-03-2015 |
20150347027 | METHOD AND APPARATUS FOR IMPROVING MEMORY READ PERFORMANCE - The present technology is directed to a method for accessing a memory device in response to read requests is described. The method comprises, in response to a first request, composing a first read sequence using a command protocol of the memory device. The first read sequence includes a command code and a starting physical address. Upon receipt of a second request, the method determines a starting physical address of a second read sequence according to the command protocol of the memory device. If the starting physical address of the second read sequence is sequential to an ending physical address of the first read sequence, then the method composes the second read sequence using the command protocol without a command code, else the method composes the second read sequence using the command protocol with a read command. | 12-03-2015 |
20150347029 | Identification of Hot Regions to Enhance Performance and Endurance of a Non-Volatile Storage Device - Systems, methods and/or devices are used to enable identification of hot regions to enhance performance and endurance of a non-volatile storage device. In one aspect, the method includes (1) receiving a plurality of input/output (I/O) requests to be performed in a plurality of regions in a logical address space of a host, and (2) performing one or more operations for each region of the plurality of regions in the logical address space of the host, including (a) determining whether the region is accessed by the plurality of I/O requests more than a predetermined threshold number of times during a predetermined time period, (b) if so, marking the region with a hot region indicator, and (c) while the region is marked with the hot region indicator, identifying open blocks associated with the region, and marking each of the identified open blocks with a hot block indicator. | 12-03-2015 |
20150347033 | STORAGE CONTROLLING DEVICE, STORAGE CONTROLLING METHOD, STORAGE SYSTEM AND PROGRAM - According to one embodiment, there is provided a storage controlling device including a receiving unit and a controlling unit. The receiving unit receives a read command or a write command for a storage device, from an internal or external command issuing device. The controlling unit holds the write command received by the receiving unit until at least a first interval time has elapsed after outputting a write command received most recently before the write command is received, and then outputs the write command which is held after the first interval time has elapsed. The controlling unit outputs the read command received by the receiving unit, prior to outputting the write command that is held, when the read command is received during a time when the write command is held. | 12-03-2015 |
20150347038 | APPARATUSES AND METHODS FOR PERFORMING WEAR LEVELING OPERATIONS - Apparatuses and methods for commands to perform wear leveling operations are described herein. An example apparatus may include a memory configured to receive a wear leveling command and to perform a wear leveling operation responsive to the wear leveling command. The memory may further be configured to recommend a wear leveling command be provided to the memory responsive to a global write count exceeding a threshold. The global write count may be indicative of a number of write operations performed by the memory since the memory performed a wear leveling operation. | 12-03-2015 |
20150347039 | Method and System for Recharacterizing the Storage Density of a Memory Device or a Portion Thereof - A storage system includes a memory controller and a storage device with one or more memory devices, each with a plurality of memory portions. The memory controller determines an initial storage capacity for each of the one or more memory devices, where the one or more memory devices are configured in a first storage density. The memory controller detects a trigger condition as to at least one memory portion of a respective device of the one or more memory devices and, in response to detecting the trigger condition, recharacterizes the at least one memory portion of the respective memory device so as to be configured in a second storage density, where the at least one recharacterized memory portion of the respective memory device has a reduced storage capacity. After the recharacterizing, the memory controller determines a revised storage capacity for the respective memory device. | 12-03-2015 |
20150347040 | Using History of I/O Sizes and I/O Sequences to Trigger Coalesced Writes in a Non-Volatile Storage Device - Systems, methods and/or devices are used to enable using history of I/O sizes and I/O sequences to trigger coalesced writes in a non-volatile storage device. In one aspect, the method includes (1) receiving a plurality of input/output (I/O) requests to be performed in a plurality of regions in a logical address space of a host, and (2) performing one or more operations for each region of the plurality of regions in the logical address space of the host, including (a) determining whether the region has a history of I/O requests to access data of size less than a predefined small-size threshold during a predetermined time period, (b) determining whether the region has a history of sequential write requests during the predetermined time period, and (c) if both determinations are true, coalescing subsequent write requests to the region. | 12-03-2015 |
20150347041 | Using History of I/O Sequences to Trigger Cached Read Ahead in a Non-Volatile Storage Device - Systems, methods and/or devices are used to enable using history of I/O sequences to trigger cached read ahead in a non-volatile storage device. In one aspect, the method includes (1) receiving, at a storage device, a plurality of input/output (I/O) requests from a host, the plurality of I/O requests including read requests and write requests to be performed in a plurality of regions in a logical address space of the host, and (2) performing one or more operations for each region of the plurality of regions in the logical address space of the host, including (a) determining whether the region has a history of sequential read requests during a predetermined time period, and (b) in accordance with a determination that the region has a history of sequential read requests during the predetermined time period, enabling read ahead logic for the region. | 12-03-2015 |
20150347048 | SYSTEMS AND METHODS FOR REORDERING PACKET TRANSMISSIONS IN A SCALABLE MEMORY SYSTEM PROTOCOL - A memory device includes a plurality of memory components that store data and a processor communicatively coupled to the plurality of memory components. The processor may receive a plurality of packets associated with a plurality of data operations, such that each of the plurality of packets includes a transaction window field indicating a type of memory component associated with a respective data operation of the respective packet. The processor may also perform the plurality of data operations in a first order based on the type of memory component indicated in the transaction window field of each of the plurality of packets. | 12-03-2015 |
20150347053 | Systems and Methods for Immediate Physical Erasure of Data Stored In a Memory System In Response to a User Command - Systems and methods for immediate physical erasure of data in a memory system in response to a user command are disclosed. In one implementation, a memory system includes a non-volatile memory and a controller in communication with the non-volatile memory. The controller comprises a processor that is configured to receive from a host in communication with the memory system, a destruct command that indicates a user request to make the memory system inoperable. The processor is further configured to perform one or more operations to render the memory system inoperable in response to the destruct command received from the host. | 12-03-2015 |
20150347054 | MEMORY WITH MIXED CELL ARRAY AND SYSTEM INCLUDING THE MEMORY - A memory system, system including the memory system and method of reducing memory system power consumption. The memory system includes multiple memory units allocable to one of a number of processor units, e.g., processors or processor cores. A memory controller receives requests for memory from the processor units and allocates sufficient space from the memory to each requesting processor unit. Allocated memory can include some Single Level per Cell (SLC) memory units storing a single bit per cell and other memory units storing more than one bit per cell. Thus, two processor units may be assigned identical memory space, while half, or fewer, than the number of cells of one are assigned to the other. | 12-03-2015 |
20150347058 | SYSTEM AND METHOD FOR DISTRIBUTED COMPUTING IN NON-VOLATILE MEMORY - A system and method are disclosed for incorporating mathematical and/or logical functionality within a memory system (such as a solid state drive (SSD)). The mathematical and/or logical functionality may comprise an arithmetic logic unit (ALU). The ALU may be resident in one or both of flash memory chips or the SSD controller. When resident in the flash memory chips, a single ALU or multiple ALUs may be used. For example, a single ALU may be assigned to one, some, or each block of flash memory within the flash memory chip. As another example, an ALU may be assigned to a sub-block construct, such as to each bit line in the block. Having ALUs resident in the SSD enables more processing to be performed within the SSD and reduces the need to transmit data outside of the SSD for processing. | 12-03-2015 |
20150347288 | LOG-STRUCTURED FILED SYSTEM WITH FILE BRANCHING - Disclosed are systems, computer-readable mediums, and methods for reading a sequence number from regions of a solid state storage device. A latest region is determined based upon the sequence numbers and a checkpoint file is read within the latest region. A request for a block of data of a first branch is received. A first block of pointers associated with the first branch from the checkpoint file is read. A first pointer from the first block of pointers and a second block of pointers pointed to by the first pointer are read. A second pointer from the second block of pointers and a third block of pointers pointed to by the second pointer are read. A third pointer from the third block of pointers and data pointed to by the third pointer are read. The block of data of the first branch is determined based upon the read data. The block of data is returned. | 12-03-2015 |
20150347289 | Forced Map Entry Flush to Prevent Return of Old Data - A data storage device flushes newly written data in response to certain events such that, when the device has acknowledged newly written data, the device cannot return old data of the referenced logical block address to the host in any case. If the data of the logical block address has been corrupted, the device returns an uncorrectable error, not old data. A “force map entry flush” flushes modified map entries to NAND when an upper page is programmed. After a power failure and restoration, a storage device is able to analysis map entries to determine whether there is some host data in the uncorrectable die, then prevent return of old data to a host. | 12-03-2015 |
20150347290 | SEMICONDUCTOR DEVICE - A semiconductor device may include a first memory cell array configured to store data according to a first address on a first basis, a second memory cell array configured to store data according to a second address on a second basis that is relatively smaller than the first basis, a memory selector configured to select one of the first memory cell array and the second memory cell array to store data during a write request, and an address map table configured to store mapping information between the first and second addresses for data stored in the second memory cell array. | 12-03-2015 |
20150347291 | FLASH MEMORY BASED STORAGE SYSTEM AND OPERATING METHOD - A flash memory based storage system and operating method are provided. A host of the storage system requests an erase unit size from the storage device and uses a multiple of the erase unit size to partition a logical address. Each host block may be assigned a state selected from a group of states including: an open state in which an erase unit of the storage device is allocated, a write state in which data is written at an erase unit of the storage device, a close state in which a write operation is no longer performed, and an invalidate state in which valid data of a host block is invalidated. | 12-03-2015 |
20150347292 | WRITING AN ADDRESS CONVERSION TABLE FOR NONVOLATILE MEMORY WEAR LEVELING - An apparatus configured to write, in a non-volatile memory, an address conversion table for wear leveling of the non-volatile memory includes a holding unit configured to hold a first address conversion table for wear leveling of a first block of the non-volatile memory, a second address conversion table for wear leveling of a second block other than the first block of the non-volatile memory, and a third address conversion table for wear leveling of a third block other than the first block of the non-volatile memory; and a writing unit configured to write, in the first block, a replication of the second address conversion table in addition to one replication of the first address conversion table and to write, in the third block, another replication of the first address conversion table in addition to a replication of the third address conversion table. | 12-03-2015 |
20150347293 | METHOD AND APPARATUS FOR PREVENTION OF FRAGMENTATION OF NON-VOLATILE MEMORY FOR BLACK BOX DEVICE - In accordance with a first exemplary embodiment, there is provided a device for black box. The device includes one or more camera module; a non-volatile memory, in which a program for operating a file system is stored; and a processor that executes the program stored in the non-volatile memory. Wherein according to execution of the program, the processor divides the whole storage area of the non-volatile memory into a plurality of file storage areas, and stores a file generated by the camera module in one of the plurality of the divided file storage areas according to a type of the file. | 12-03-2015 |
20150347294 | Method and Apparatus for Implementing Compatibility between Different Nand Flash Memories - A method and an apparatus for implementing compatibility of different Nand flashes are provided. Based on the technical solution provided by the disclosure, the problem that a driver and a file system of a Nand flash are not easy to be compatible with a Nand flash of a different architecture in the prior art is solved, one product can be compatible with the existing Nand flashes in the mark, a good expansion interface is provided, and a new Nand flash can be supported quickly, so that the time to market of the product is shortened and the competitiveness of the product is | 12-03-2015 |
20150347295 | METHOD OF OPERATING A MEMORY SYSTEM USING A GARBAGE COLLECTION OPERATION - A memory system may include a nonvolatile memory including a plurality of memory blocks; and a memory controller including a garbage collection unit, the garbage collection unit configured to generate a garbage collection level, the garbage collection unit configured to perform a garbage collection operation based on the garbage collection level and a garbage collection trigger level, and the garbage collection level being generated based on a free block generation time of the nonvolatile memory. | 12-03-2015 |
20150347296 | Prioritizing Garbage Collection and Block Allocation Based on I/O History for Logical Address Regions - Systems, methods and/or devices are used to enable prioritizing garbage collection and block allocation based on I/O history for logical address regions. In one aspect, the method includes (1) receiving, at a storage device, a plurality of input/output (I/O) requests from a host, the plurality of I/O requests including read requests and write requests to be performed in a plurality of regions in a logical address space of the host, (2) in accordance with the plurality of I/O requests over a predetermined time period, identifying an idle region of the plurality of regions in the logical address space of the host, and (3) in accordance with the identification of the idle region, enabling garbage collection of data storage blocks, in the storage device, that store data in the idle region. | 12-03-2015 |
20150347314 | NONVOLATILE MEMORY SYSTEM AND A METHOD OF OPERATING THE NONVOLATILE MEMORY SYSTEM - A nonvolatile memory system includes: a nonvolatile memory device that includes a nonvolatile memory cell array and a page buffer; and a memory controller that loads into the page buffer mapping data that is stored in the nonvolatile memory cell array, and in response to a logical address received from outside the memory controller, translates the logical address into a physical address based on the mapping data that is loaded into the page buffer. | 12-03-2015 |
20150347318 | THINLY PROVISIONED FLASH CACHE WITH SHARED STORAGE POOL - For data processing in a computing storage environment by a processor device, the computing storage environment incorporating at least high-speed and lower-speed caches, and managed tiered levels of storage, a Solid State Device (SSD) tier is variably shared between the lower-speed cache and the managed tiered levels of storage such that the managed tiered levels of storage are operational on large data segments, and the lower-speed cache is allocated with the large data segments, yet operates with data segments of a smaller size than the large data segments and within the large data segments, where if selected data segments are cached in the lower-speed cache and are determined to become uniformly hot, the selected group from the lower-speed cache are migrated to the SSD tier. | 12-03-2015 |
20150347327 | I/O SCHEDULING - In one embodiment, input-output (I/O) scheduling system detects and resolves priority inversions by expediting previously dispatched requests to an I/O subsystem. In response to detecting the priority inversion, the system can transmit a command to expedite completion of the blocking I/O request. The pending request can be located within the I/O subsystem and expedited to reduce the pendency period of the request. | 12-03-2015 |
20150348939 | ENHANCED FLASH CHIP AND METHOD FOR PACKAGING CHIP - An enhanced Flash chip and a method for packaging chip are provided to solve the problems of high design complexity. The enhanced Flash chip comprises: a FLASH and a RPMC packaged integrally, wherein the same IO pins in the FLASH and in the RPMC are mutually connected and are connected to the same external sharing pin of the chip; an external instruction is transmitted to the FLASH and the RPMC through the external sharing pin of the chip, and the controller of the FLASH and the controller of the RPMC respectively judge whether to execute the external instruction; and the FLASH and the RPMC further comprise internal IO pins, respectively, the internal IO pins of the FLASH and the internal IO pins of the RPMC are mutually connected, and internal mutual communication between the FLASH and the RPMC is performed through the pair of mutually connected internal IO pins. | 12-03-2015 |
20150355701 | POWER SOURCE EQUIPMENT AND POWER SUPPLY METHOD THEREOF - A power supply method includes providing a plurality of output powers to a plurality of power devices (PDs); acquiring a plurality of power statuses of the PDs (power devices); calculating a summation of the output powers provided to the PDs (power devices); determining whether the summation of the output powers exceeds a predetermined threshold; and under a condition that the summation of the output powers exceeds the predetermined threshold, adjusting the output powers provided to the PDs (power devices) based upon the power statuses of the PDs (power devices). | 12-10-2015 |
20150355706 | ELECTRONIC DEVICE AND METHOD FOR CONTROLLING ELECTRONIC DEVICE - An electronic device includes: a nonvolatile memory; a volatile memory stacked over the nonvolatile memory; and a controller configured to store setting information of the volatile memory in the nonvolatile memory before cutting off power supply to the volatile memory, and to set the setting information stored in the nonvolatile memory to the volatile memory after resuming power supply to the volatile memory. | 12-10-2015 |
20150355838 | ESTIMATING READ REFERENCE VOLTAGE BASED ON DISPARITY AND DERIVATIVE METRICS - An adaptive channel tracking algorithm performed by a flash memory system obtains disparity metrics and derivative metrics and uses a combination of the disparity and derivative metrics to estimate an optimal read reference voltage. The estimation of the optimal read reference voltage does not rely on assumptions about the underlying cell voltage distributions and results in a good estimate of the read reference voltage even if the standard deviations of the cell voltage distributions are different. In addition, the algorithm is relatively simple and less computationally intensive to perform than the known tracking algorithms. | 12-10-2015 |
20150355839 | Solid State Drive and Operation Method Thereof - A solid state drive in accordance with embodiments of the present inventive concepts may include a nonvolatile memory, a volatile memory, a memory controller controlling the nonvolatile memory and the volatile memory, and a power generator providing power to the nonvolatile memory, the volatile memory, and the memory controller. A method of operating the solid state drive may include designating a bank that will perform a self refresh among a plurality of banks included in the volatile memory in response to a power saving mode signal. Information of the designated bank may be stored in a register in response to a command and an address signal; and a self refresh of the designated bank may be performed on the basis of the information stored in the register. | 12-10-2015 |
20150355841 | MEMORY SYSTEM - According to one embodiment, a memory system includes an interface, a storage, and a controller. The interface is configured to connect to a plurality of initiators. The storage is configured to store data. The controller is configured to refer to a connection condition of the interface and transmit data to be transmitted to an initiator being connected from the storage. | 12-10-2015 |
20150355842 | MANAGEMENT METHOD OF HYBRID STORAGE UNIT AND ELECTRONIC APPARATUS HAVING THE HYBRID STORAGE UNIT - A management method of a hybrid storage unit and an electronic apparatus of the hybrid storage unit are provided. The electronic apparatus includes a hybrid storage unit. The hybrid storage unit includes a first storage unit and a second storage unit. The second storage unit includes a first storage area and a second storage area. If a relationship between the electronic apparatus and an external apparatus is detected as being an undocked relationship, the first storage unit is disabled by a controller of the hybrid storage unit, and the second storage area serves to simulate and replace the first storage unit. The controller reports a storage unit status change notification to an operating system, so as to allow the operating system to re-enumerate the hybrid storage unit. | 12-10-2015 |
20150355845 | MEMORY SYSTEMS THAT SUPPORT READ RECLAIM OPERATIONS AND METHODS OF OPERATING SAME TO THEREBY PROVIDE REAL TIME DATA RECOVERY - Methods of operating nonvolatile memory devices include counting a number of consecutive read operations performed on a first memory region within the nonvolatile memory device, and executing a page reclaim operation on the first memory region in response to detecting that a count in the number of consecutive read operations meets or exceeds a threshold count. A page reclaim operation may include checking an error bit level within a page of data stored in a multi-level cell block within the memory device. The page reclaim operation may further include moving page data from the multi-level cell block to a single-level cell block in the memory device and error correcting the page data during the moving. | 12-10-2015 |
20150355846 | DRAM with SDRAM Interface, and Hybrid Flash Memory Module - When DRAMs that are high-speed memories and flash memories that are lower in speed but can be larger in capacity than the DRAM are to be mounted on a DIMM, what matters in maximizing CPU memory bus throughput is the arrangement of the mounted components. The present disclosure provides a memory module (DIMM) that includes memory controllers arranged on the module surface closer to a socket terminal and DRAMs serving as high-speed memories arranged on the back surface. Nonvolatile memories as large-capacity memories are arranged on the side farther from the socket terminal. | 12-10-2015 |
20150355847 | TRANSFER SIZE MONITOR, DETERMINATION, AND OPTIMIZATION ENGINE FOR STORAGE DEVICES - A method of monitoring, optimizing, and dynamically varying transfer size in a storage device is provided, including: receiving data transfer parameters for a Solid State Disk (SSD) device; selecting a data transfer size from the disk characterization data associated with the SSD device, based on a SSD device identifier in the received data transfer parameters matching the SSD device identifier in the disk characterization data; searching a weight-age table for a process identifier (PID) matching the PID from the received data transfer parameters; determining a heuristic representing a statistical distribution of Input/Output (I/O) operations per second (IOPS) and transfer sizes over time; modifying the received data transfer parameters based on at least one of: the selected data transfer size from the disk characterization data; the weight-age table; and the heuristic; and completing one or more (I/O) operations with the SSD device using the modified data transfer parameters. | 12-10-2015 |
20150355848 | STORAGE CLUSTER - A plurality of storage nodes in a single chassis is provided. The plurality of storage nodes in the single chassis is configured to communicate together as a storage cluster. Each of the plurality of storage nodes includes nonvolatile solid-state memory for user data storage. The plurality of storage nodes is configured to distribute the user data and metadata associated with the user data throughout the plurality of storage nodes such that the plurality of storage nodes maintain the ability to read the user data, using erasure coding, despite a loss of two of the plurality of storage nodes. A plurality of compute nodes is included in the single chassis, each of the plurality of compute nodes is configured to communicate with the plurality of storage nodes. A method for accessing user data in a plurality of storage nodes having nonvolatile solid-state memory is also provided. | 12-10-2015 |
20150355849 | SENSING OPERATIONS IN A MEMORY DEVICE - Methods for sensing, method for programming, memory devices, and memory systems are disclosed. In one such method for sensing, a counting circuit generates a count output and a translated count output. The count output is converted into a time varying voltage that biases a word line coupled to memory cells being sensed. Target data for each memory cell is stored in a data cache associated with that particular memory cell. When it is detected that a memory cell has turned on, the translated count output associated with the count output that is indicative of the voltage level that turned on the memory cell is compared to the target data. The comparison determines the state of the memory cell. | 12-10-2015 |
20150355850 | MEMORY LIFE EXTENSION SYSTEM AND METHOD - A memory life extension system and method is provided for managing operation of rewritable memory used to store a monotonically increasing sequence of multiple-byte binary values in a set of one or more memory locations in the rewritable memory. A first value is read in from a set of one or more memory locations. On detection of an instruction to store an incremented value, the incremented value is permuted by applying an encoding, in which a value of a least significant bit changes only on every second increment, to two least significant bits of the incremented value. On overflow of a least significant byte as a result of the increment, a cyclic byte-wise shift is applied to the incremented value. The permuted incremented value is then stored in the one or more memory locations. | 12-10-2015 |
20150355854 | SEMICONDUCTOR MEMORY DEVICE, MEMORY SYSTEM INCLUDING THE SAME, AND OPERATING METHOD THEREOF - A semiconductor memory device may include a memory cell array, and a program and verify circuit configured to perform a write operation on the memory cell array by repeating a plurality of program and verify operations. When the write operation is stopped after a first program operation is performed according to a first program condition, the PNV circuit may perform a first verify operation corresponding to the first program operation according to a first target value, after the write operation has resumed. | 12-10-2015 |
20150355861 | TRANSFER SIZE MONITOR, DETERMINATION, AND OPTIMIZATION ENGINE FOR STORAGE DEVICES - A method of monitoring, optimizing, and dynamically varying transfer size in a storage device is provided, including: receiving data transfer parameters for a Solid State Disk (SSD) device; selecting a data transfer size from the disk characterization data associated with the SSD device, based on a SSD device identifier in the received data transfer parameters matching the SSD device identifier in the disk characterization data; searching a weight-age table for a process identifier (PID) matching the PID from the received data transfer parameters; determining a heuristic representing a statistical distribution of Input/Output (I/O) operations per second (IOPS) and transfer sizes over time; modifying the received data transfer parameters based on at least one of: the selected data transfer size from the disk characterization data; the weight-age table; and the heuristic; and completing one or more (I/O) operations with the SSD device using the modified data transfer parameters. | 12-10-2015 |
20150356006 | NONVOLATILE MEMORY ARRAY LOGIC - A method for implementing nonvolatile memory array logic includes configuring a crosspoint memory array in a first configuration and applying an input voltage to the crosspoint array in the first configuration to produce a setup voltage. The crosspoint array is configured in a second configuration and an input voltage is applied to the crosspoint array in the second configuration to produce a sense voltage. The setup voltage and the sense voltage compared to perform a logical operation on data stored in the crosspoint array. A system for performing nonvolatile memory array logic is also provided. | 12-10-2015 |
20150356010 | DATA STORAGE IN A MOBILE DEVICE WITH EMBEDDED MASS STORAGE DEVICE - A mobile device ( | 12-10-2015 |
20150356016 | METHOD OF ESTABLISHING PRE-FETCH CONTROL INFORMATION FROM AN EXECUTABLE CODE AND AN ASSOCIATED NVM CONTROLLER, A DEVICE, A PROCESSOR SYSTEM AND COMPUTER PROGRAM PRODUCTS - A method of establishing pre-fetch control information from an executable code is described. The method comprises inspecting the executable code to find one or more instructions corresponding to an unconditional change in program flow during an execution of the executable code when the executable code is retrieved from a non-volatile memory [NVM] comprising a plurality of NVM lines. For each unconditional change of flow instruction in the executable code, the method comprises establishing a NVM line address of the NVM line containing said unconditional change of flow instruction; establishing a destination address associated with the unconditional change of flow instruction; determining whether the destination address is in an address range corresponding to a NVM-pre-fetch starting from said NVM line address; establishing a pre-fetch flag indicating whether the destination address is in the address range corresponding to a NVM-pre-fetch starting from said NVM line address; and recording the pre-fetch flag in a pre-fetch control information record. Also, a NVM controller, a device, a processor system and computer program products are described. | 12-10-2015 |
20150356020 | METHODS, SYSTEMS, AND COMPUTER READABLE MEDIA FOR SOLID STATE DRIVE CACHING ACROSS A HOST BUS - Methods, systems, and computer readable media for solid state drive caching across a host bus are disclosed. According to one aspect, a method for solid state caching across host bus includes, during operation of a solid state drive (SSD) having non-volatile memory (NVM) for bulk storage of data and metadata, a first random access memory (RAM), and a host bust interface for accessing a second RAM memory located on a host and separate from the first RAM, using the first RAM as a cache for storing a first portion of metadata, and using the second RAM as a cache for storing a second portion of metadata, where the second RAM is accessed by the SSD via the host bus interface. | 12-10-2015 |
20150356040 | REMOVABLE MEMORY CARD TYPE DETECTION SYSTEMS AND METHODS - Removable memory card type detection systems and methods are disclosed. In one aspect, a removable memory card is inserted into a receptacle of a host. The host determines a type of removable memory card based upon either electrical or physical properties of the removable memory card. In this manner, if the host detects that the removable memory card possesses certain electrical or physical properties associated with a microSD card, the host determines that the removable memory card is a microSD type card. If the host detects that the removable memory card possesses certain electrical or physical properties associated with a UFS card, the host determines that the removable memory card is a UFS type card. By determining the card type based on detection of certain electrical or physical properties, aspects disclosed herein are able to distinguish between UFS and microSD cards without requiring an additional pin or card initialization time. | 12-10-2015 |
20150357031 | PROGRAMMING MEMORIES WITH STEPPED PROGRAMMING PULSES - Memories and methods for programming memories with multi-step programming pulses are provided. One method includes applying a plurality of programming pulses to cells of the memory device to be programmed, with each programming pulse of the plurality of programming pulses being configured to contribute towards programming a cell of the plurality of cells to each data state of a plurality of programmed data states. A first portion of each programming pulse is used to program certain cells towards a target data state associated with a first threshold voltage level, and a later portion of each programming pulse is used to program other cells towards a target data state associated with a second threshold voltage level that is lower than the first threshold voltage level. | 12-10-2015 |
20150357557 | ELECTRONIC DEVICE - This technology provides an electronic device. An electronic device in accordance with an implementation of this document includes semiconductor memory, and the semiconductor memory includes a first magnetic layer having a variable magnetization direction; a second magnetic layer having a pinned magnetization direction; and a tunnel barrier layer interposed between the first magnetic layer and the second magnetic layer, wherein the second magnetic layer includes a ferromagnetic material with molybdenum (Mo) added thereto. | 12-10-2015 |
20150362967 | Memory Controller with Processor for Generating Interface Adjustment Signals - Described are a system and method to control interface timing and/or voltage operations of signals transmitted between devices. A processor may be coupled through one or more bus interfaces of a bus to one or more corresponding interface timing and/or voltage comparison circuits and corresponding interface timing and/or voltage adjustment circuits. | 12-17-2015 |
20150363105 | STORAGE DEVICE, MEMORY CONTROLLER, AND CONTROL METHOD - A storage device includes a first nonvolatile memory that includes memory cells, each capable of storing data of a first number of bits, a second nonvolatile memory of which memory capacity is larger than a memory capacity of the first nonvolatile memory, and a memory controller is configured to control the first nonvolatile memory to store data of a second number of bits that is smaller than the first number in each of at least a part of the memory cells according to a usage amount of the memory cells. | 12-17-2015 |
20150363120 | ON DEMAND BLOCK MANAGEMENT - Methods and memories for embedded systems, and systems with managed memories, are provided. In one such method, a managed memory determines when housekeeping operations are indicated, conveys that information to a host, and the host initiates the housekeeping operation at a time determined by the host not to affect real-time system operation. | 12-17-2015 |
20150363130 | COMMUNICATION DEVICE, RFID SYSTEM, AND RECORDABLE MEDIUM HAVING DATA WRITING PROGRAM RECORDED THEREON - A communication device ( | 12-17-2015 |
20150363131 | SYSTEMS AND METHODS FOR A MASS DATA STORAGE SYSTEM HAVING A FILE-BASED INTERFACE TO A HOST AND A NON-FILE-BASED INTERFACE TO SECONDARY STORAGE - System and method for transferring data between a host system and a data storage system is provided. The system includes an interface that uses a file based protocol to transfer data between the data storage system and the host system, wherein the data storage system includes a first mass storage device and a second mass storage device; wherein the first mass storage device is a solid state non-volatile memory device and the second mass storage device is a non-solid state memory device. The first mass storage device is a flash memory device that operates as a primary storage device that stores data on a file by file basis. The second mass storage device is a magnetic disk drive that operates as secondary storage device and stores data received via a logical interface. | 12-17-2015 |
20150363135 | SYSTEMS AND METHODS FOR A MASS DATA STORAGE SYSTEM HAVING A FILE-BASED INTERFACE TO A HOST AND A NON-FILE-BASED INTERFACE TO SECONDARY STORAGE - System and method for transferring data between a host system and a data storage system is provided. The system includes an interface that uses a file based protocol to transfer data between the data storage system and the host system, wherein the data storage system includes a first mass storage device and a second mass storage device; wherein the first mass storage device is a solid state non-volatile memory device and the second mass storage device is a non-solid state memory device. The first mass storage device is a flash memory device that operates as a primary storage device that stores data on a file by file basis. The second mass storage device is a magnetic disk drive that operates as secondary storage device and stores data received via a logical interface. | 12-17-2015 |
20150363208 | UPDATING A COMMIT LIST TO INDICATE DATA TO BE WRITTEN TO A FIRMWARE INTERFACE VARIABLE REPOSITORY - Examples disclosed herein relate to updating a commit list to indicate data to be written to a firmware interface (FI) variable repository. Examples include storing target data in a variable repository cache of system management memory of a computing device during a given SMM event, updating a commit list, during the given SMM event, to indicate that the target data is to be written to the FI variable repository, and ending the given SMM event without at least some portion of the target data being written to the FI variable repository during the given SMM event. | 12-17-2015 |
20150363280 | Conditional Storage - In one aspect of the present disclosure, a method involves obtaining, by a body-mountable device, sensor data, where the body-mountable device includes a data storage. The method further involves making a determination that each condition in a condition set has been satisfied. In addition, the method involves responsive to making the determination that each condition in the condition set has been satisfied, storing the obtained sensor data in the data storage. | 12-17-2015 |
20150363307 | ADDRESS MAPPING FOR SOLID STATE DEVICES - Technologies are generally described for systems, devices and methods relating to swapping bits in memory addresses in solid state devices. In some examples, a bit swap module may receive a first memory address. The first memory address may include a first bit value at a first position of the first memory address and/or a second bit value at a second position of the first memory address. The bit swap module may swap the first bit value with the second bit value to produce a second memory address. The second memory address may be sent to a memory controller. In some examples, the first memory address may relate to a first package of memory and the second memory address may relate to a second package of memory. | 12-17-2015 |
20150363308 | METHOD FOR OPERATING CONTROLLER AND METHOD FOR OPERATING DEVICE INCLUDING THE SAME - A method of operating a controller includes receiving write data having chunks from a host, assigning each of finger prints to each of the chunks, counting the number of duplications of each of the finger prints, and changing a physical address assigned to each of first finger prints among the finger prints based on a count value of each of the finger prints based on a count value of each of the finger prints, and the physical address is assigned by a flash translation layer (FTL). | 12-17-2015 |
20150363309 | SYSTEM AND METHOD OF INCREASING RELIABILITY OF NON-VOLATILE MEMORY STORAGE - Various embodiments are described herein for a system and a method for increasing reliability of a secondary storage device used with a computing system where the secondary storage device contains a memory buffer, a controller, and non-volatile memory. The method may comprise initializing a test of the memory buffer; testing at least one memory block of the memory buffer; discontinuing use of a given memory block of the memory buffer if a defective memory location is detected for the given memory block; and storing test results for the memory buffer. | 12-17-2015 |
20150363311 | MEMORY MANAGEMENT METHOD - A method for managing main memory including DRAM and NVRAM in a computer depending on the operation state of the computer is provided. The method includes: (a) upon start of the computer, loading a program and the like into the DRAM, and loading predetermined read-only data and the like into the NVRAM; (b) in a state transition from a normal operation to a suspend state, moving data in the DRAM to the NVRAM; (c) in a state transition from the suspend state to the normal operation, reading data from the NVRAM for program execution; (d) in the case where a data write to the NVRAM occurs, stopping the data write, and moving data in a data area of the NVRAM subjected to the data write, to the DRAM; and (e) performing the data write to the DRAM to which the data has been moved. | 12-17-2015 |
20150363313 | SENSE OPERATION FLAGS IN A MEMORY DEVICE - Memory devices, methods for programming sense flags, methods for sensing flags, and memory systems are disclosed. In one such memory device, the odd bit lines of a flag memory cell array are connected with a short circuit to a dynamic data cache. The even bit lines of the flag memory cell array are disconnected from the dynamic data cache. When an even page of a main memory cell array is read, the odd flag memory cells, comprising flag data, are read at the same time so that it can be determined whether the odd page of the main memory cell array has been programmed. If the flag data indicates that the odd page has not been programmed, threshold voltage windows can be adjusted to determine the states of the sensed even memory cell page. | 12-17-2015 |
20150363320 | WRITE BACK CACHING OF BOOT DISK IN A UEFI ENVIRONMENT - Write back caching of Operating System (OS) boot data in a UEFI environment is disclosed. One embodiment is an apparatus that includes a non-volatile memory, a storage device, and a processor. The non-volatile memory caches boot data for an OS. The storage device stores the OS. The processor receives a write request for the storage device, and determines whether the write request modifies boot data accessed within a UEFI pre-OS boot environment. The processor directs the write request to the storage device responsive to determining that the write request modifies boot data accessed within the UEFI pre-OS boot environment, and directs the write request to the non-volatile memory responsive to determining that the write request does not modify boot data accessed within the UEFI pre-OS boot environment. | 12-17-2015 |
20150363327 | FLASH STORAGE DEVICES AND METHODS FOR ORGANIZING ADDRESS MAPPING TABLES IN FLASH STORAGE DEVICES - In some example embodiments, a method of organizing an address mapping table of a flash storage device based on Logical Block Address (LBA) size may comprise: identifying an extent of correlation between the LBA and flash page sizes, wherein the extent of correlation indicates greater or lesser extent; computing a total number of entries in each meta page of the table; and/or organizing the table with the total number of entries. In some example embodiments, a method of organizing an address mapping table of a flash storage device based on LBA size may comprise: determining flash page size of the flash storage device; determining the LBA size; and/or comparing the flash page and LBA sizes. When the flash page size is greater, the table may be organized based on flash page size. When the flash page size is less, the table may be organized based on LBA size. | 12-17-2015 |
20150363455 | PREPLAYING TRANSACTIONS THAT MIX HOT AND COLD DATA - Methods and systems for performing database transactions include executing a first transaction request in a preplay mode that locks the requested data with a prefetch-lock and reads one or more requested data items from storage into a main memory buffer; locking the requested data items with a read/write lock after said data items are read into the main memory buffer; and performing the requested transaction on the data items in the main memory buffer using a processor. | 12-17-2015 |
20150364162 | MULTIPORT MEMORY - A data storage device includes a memory that has a three-dimensional (3D) memory configuration, a controller, and a plurality of memory ports. The controller is configured to read mapping data from the memory. The mapping data maps the plurality of memory ports to the plurality of storage elements. The controller is further configured to, in response to receiving a command associated with a logical address, determine a physical address of the memory corresponding to the logical address, the physical address corresponding to a group of storage elements of the plurality of storage elements. The controller is further configured to select a memory port of the plurality of memory ports, where the memory port is mapped to the group of storage elements. The controller is further configured to access the group of storage elements via the memory port to perform first command. | 12-17-2015 |
20150370300 | METHODS AND SYSTEMS FOR CALIBRATION OF VOLTAGE REGULATOR SYSTEMS WITH MULTIPLE TYPES OF POWER STAGES - Methods and systems are disclosed that may be employed to enable multi-phase voltage regulator (VR) system calibration during the development phase of a multi-phase VR system so as to meet defined accuracy targets and, in one example, to avoid the need for system level calibration in a production environment. The disclosed systems and methods may be further implemented to enable use of multiple sources for and types of integrated power stages (IPstages) in a common multi-phase VR system configuration while still achieving the required current sense accuracy, thus reducing or substantially eliminating continuity of supply (COS) concerns. The disclosed methods and systems may also be implemented to improve accuracy of current sense in a manner that improves VR system performance, power saving and reliability. | 12-24-2015 |
20150370302 | FIRMWARE INTERFACE WITH DURABLE MEMORY STORAGE - Generally, this disclosure provides systems, devices, methods and computer readable media for a Unified Extensible Firmware Interface (UEFI) with durable storage to provide memory write persistence, for example, in the event of power loss. The system may include a processor to host the firmware interface which may be configured to control access to system variables in a protected region of a volatile memory. The system may also include a power management circuit to provide power to the processor and further to provide a power loss indicator to the firmware interface. The system may also include a reserve energy storage module to provide power to the processor in response to the power loss indicator. The firmware interface is further configured to copy the system variables from the volatile memory to a non-volatile memory in response to the power loss indicator. | 12-24-2015 |
20150370480 | SYSTEM AND METHOD FOR DATA STORAGE ARCHIECTURE FOR HIGH PERFORMANCE COMPUTING HASH ON METADATA IN REFERENCE TO STORAGE REQUEST - Data storage systems and methods for storing data are described herein. The storage system may be integrated with or coupled with a compute cluster or super computer having multiple computing nodes. A plurality of nonvolatile memory units may be included with computing nodes, coupled with computing nodes or coupled with input/output nodes. The input/output nodes may be included with the compute cluster or super computer, or coupled thereto. The nonvolatile memory units store data items provided by the computing nodes, and the input/output nodes maintain where the data items are stored in the nonvolatile memory units via a hash table distributed among the input/output nodes. The use of a distributed hash table allows for quick access to data items stored in the nonvolatile memory units even as the computing nodes are writing large amounts of data to the storage system quickly in bursts. | 12-24-2015 |
20150370481 | SEMICONDUCTOR DEVICE - A semiconductor device may include a memory block including a plurality of memory cells, and an operation circuit configured to perform a first program loop, a second program loop, and a third program loop based on data stored in the memory cells. The first program loop may distribute threshold voltages of the memory cells into four levels. The second program loop may distribute the threshold voltages of the memory cells into seven levels. The third program loop may distribute the threshold voltages of the memory cells into eight levels. | 12-24-2015 |
20150370488 | MEMORY DEVICE, COMPUTER SYSTEM, AND METHOD OF CONTROLLING MEMORY DEVICE - An example of the invention is a memory device including a controller and a plurality of randomly accessible memories that are capable of storing user data from a host. The controller includes data management information managing correspondence relations between address areas to be designated by the host and the plurality of memories, and compression policy management information managing associations of the address areas to be designated by the host with priorities in compressing user data to be stored in the plurality of memories. The controller is configured to determine a compression policy associated with a designated address area included in an access request from the host based on a priority associated with the designated address area and information on free space of the plurality of memories. | 12-24-2015 |
20150370490 | OPTIMIZING SSD-BASED CONTENT CACHES IN CONTENT DELIVERY NETWORKS - A method for caching using a solid-state drive (SSD)-based cache includes: determining a set of potential objects for storage at the SSD-based cache; ranking the potential objects for storage based on expected utility values corresponding to each potential object for storage; selecting objects for storage from the potential objects for storage based on the ranking; and causing the selected objects to be written to the SSD-based cache. Further, a reserve capacity for the SSD-based cache may be dynamically adjusted based on the write speed associated with an object being written to the SSD-based cache. | 12-24-2015 |
20150370491 | FLASH MEMORY DEVICE WITH MULTI-LEVEL CELLS AND METHOD OF WRITING DATA THEREIN - In one aspect, a method of writing data in a flash memory system is provided. The flash memory system forms an address mapping pattern according to a log block mapping scheme. The method includes determining a writing pattern of data to be written in a log block, and allocating one of SLC and MLC blocks to the log block in accordance with the writing pattern of the data. | 12-24-2015 |
20150370493 | NONVOLATILE MEMORY SYSTEM AND OPERATING METHOD OF MEMORY CONTROLLER - An operating method of a storage device includes determining whether a nonvolatile memory device performs a program operation on at least one of a plurality of pages. Either a program time stamp table, managed with program elapsed times of the plurality of pages, or an update count of the program time stamp table is updated, based on the determination result. | 12-24-2015 |
20150370498 | NVRAM DATA ORGANIZATION USING SELF-DESCRIBING ENTITIES FOR PREDICTABLE RECOVERY AFTER POWER-LOSS - In one embodiment, a node coupled to a plurality of storage devices executes a storage input/output (I/O) stack having a plurality of layers including a persistence layer. A portion of non-volatile random access memory (NVRAM) is configured as one or more logs. The persistence layer cooperates with the NVRAM to employ the log to record write requests received from a host and to acknowledge successful receipt of the write requests to the host. The log has a set of entries, each entry including (i) write data of a write request and (ii) a previous offset referencing a previous entry of the log. After a power loss, the acknowledged write requests are recovered by replay of the log in reverse sequential order using the previous record offset in each entry to traverse the log. | 12-24-2015 |
20150370630 | FLASH MEMORY CONTROL APPARATUS UTILIZING BUFFER TO TEMPORARILY STORING VALID DATA STORED IN STORAGE PLANE, AND CONTROL SYSTEM AND CONTROL METHOD THEREOF - A flash memory controlling apparatus includes a data read/write interface and a controller. The data read/write interface is arranged to couple a first flash memory and a second flash memory, wherein the first flash memory includes a first storage plane and a first buffer, and the second flash memory includes a second storage plane and a second buffer. When the read/write interface couples the first flash memory and the second flash memory, the controller is arranged to temporary store a plurality of valid data stored in the first storage plane into the second buffer. After an erase cycle is performed on the first storage plane, the controller further programs the plurality of valid data temporarily stored in the second buffer into the first storage plane. | 12-24-2015 |
20150370646 | MEMORY SYSTEM STORING MANAGEMENT INFORMATION AND METHOD OF CONTROLLING SAME - A memory system includes a management-information restoring unit. The management-information restoring unit determines whether a short break has occurred referring to a pre-log or a post-log in a NAND memory. The management-information restoring unit determines that a short break has occurred when the pre-log or the post-log is present in the NAND memory. In that case, the management-information restoring unit determines timing of occurrence of the short break, and, after selecting a pre-log or a post-log used for restoration, performs restoration of the management information reflecting these logs on a snapshot. Thereafter, the management-information restoring unit applies recovery processing to all write-once blocks in the NAND memory, takes the snapshot again, and opens the snapshot and the logs in the past. | 12-24-2015 |
20150370700 | MANAGING STORAGE DEVICES - Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for managing storage devices. In some implementations, a memory controller receives a logical write request over a logical interface that the memory controller provides for accessing a non-volatile storage device. The logical write request indicates a logical address at which to write data to the non-volatile storage device. In response to receiving the logical write request, the memory controller sends a write request event to a host system. The memory controller receives a physical write command from the host system over a physical interface that the memory controller provides for accessing the non-volatile storage device. In response to receiving the physical write command, the memory controller stores the data in the non-volatile storage device according to the physical write command. | 12-24-2015 |
20150370701 | Sub-Block Garbage Collection - Systems, methods and/or devices are used to enable garbage collection of a sub-block of an individually erasable block of a storage medium in a storage device. In one aspect, the method includes determining a first trigger parameter in accordance with one or more operating conditions of a first sub-block of an erase block in the storage medium, and determining a second trigger parameter in accordance with one or more operating conditions of a second sub-block of the erase block in the storage medium. In accordance with a determination that the first trigger parameter meets a first vulnerability criterion, garbage collection of the first sub-block is enabled. Furthermore, in accordance with a determination that the second trigger parameter meets a second vulnerability criterion, garbage collection of the second sub-block is enabled. | 12-24-2015 |
20150370705 | ADDRESS SCHEDULING METHODS FOR NON-VOLATILE MEMORY DEVICES WITH THREE-DIMENSIONAL MEMORY CELL ARRAYS - At least one address scheduling method includes selecting a first bit line, selecting a first string connected to the first bit line, performing address scheduling on N pages of each of multi-level cells in the first string sequentially from a bottom word line to a top word line, and after completing the address scheduling on all word lines in the first string, performing address scheduling on second to k-th strings sequentially in the same manner as performed with respect to the first string, where “k” is 2 or a natural number greater than 2. | 12-24-2015 |
20150371027 | MEMORY SYSTEM, MEMORY CONTROLLER AND METHOD OF CONTROLLING MEMORY SYSTEM - According to an embodiment, a memory device includes: a first controller configured to register, to a first memory, access restriction information received over a short-range radio communication by using power generated in the short-range radio communication; and a second controller configured to, at a startup of the memory device, read the access restriction information registered in the first memory and perform an access restriction to a file stored in a second memory based on the read access restriction information. | 12-24-2015 |
20150378605 | NVM EXPRESS CONTROLLER FOR REMOTE ACCESS OF MEMORY AND I/O OVER ETHERNET-TYPE NETWORKS - A method and system for enabling Non-Volatile Memory express (NVMe) for accessing remote solid state drives (SSDs) (or other types of remote non-volatile memory) over the Ethernet or other networks. An extended NVMe controller is provided for enabling CPU to access remote non-volatile memory using NVMe protocol. The extended NVMe controller is implemented on one server for communication with other servers or non-volatile memory via Ethernet switch. The NVMe protocol is used over the Ethernet or similar networks by modifying it to provide a special NVM-over-Ethernet frame. | 12-31-2015 |
20150378606 | NVM EXPRESS CONTROLLER FOR REMOTE ACCESS OF MEMORY AND I/O OVER ETHERNET-TYPE NETWORKS - A method and system for enabling Non-Volatile Memory express (NVMe) for accessing remote solid state drives (SSDs) (or other types of remote non-volatile memory) over the Ethernet or other networks. An extended NVMe controller is provided for enabling CPU to access remote non-volatile memory using NVMe protocol. The extended NVMe controller is implemented on one server for communication with other servers or non-volatile memory via Ethernet switch. The NVMe protocol is used over the Ethernet or similar networks by modifying it to provide a special NVM-over-Ethernet frame. | 12-31-2015 |
20150378607 | Data Updating in Non-Volatile Memory - Various embodiments of the present invention are generally directed to an apparatus and associated method for updating data in a non-volatile memory array. In accordance with some embodiments, a memory block is formed with a plurality of types of memory cell sectors arranged in data pages of a first type and log pages of a second type that can be updated in-place. A first updated sector is written to a first log page while maintaining an outdated sector in an original data page, and overwritten with a second updated sector. | 12-31-2015 |
20150378609 | METHOD FOR INITIALIZING NAND FLASH - A method for initializing a NAND flash serving as a booting device includes the following steps. A NAND flash storing a boot table being identified by an identification (ID) of the NAND flash is provided. A current block of the NAND flash is searched to read the boot table. Configuration information of the boot table is read to initialize the NAND flash. | 12-31-2015 |
20150378613 | STORAGE DEVICE - A storage device comprises plural memory units and a storage controller that controls the memory units as a RAID group. Each memory unit is provided with a nonvolatile semiconductor memory (e.g. flash memory) chip and a memory controller that compresses data and stores the compressed data into the nonvolatile semiconductor memory chips. The memory controller makes a logical memory area available to the storage controller. The storage controller divides the logical memory area into plural entries each of which is a logical memory area of a prescribed size, acquires from respective memory unit capacity information on the data capacity stored into the nonvolatile semiconductor memory, and exchanges data of entries between the semiconductor memory units on the basis of the capacity information. | 12-31-2015 |
20150378615 | ACCELERATING BOOT TIME ZEROING OF MEMORY BASED ON NON-VOLATILE MEMORY (NVM) TECHNOLOGY - Methods and apparatus to accelerate boot time zeroing of memory based on Non-Volatile Memory (NVM) technology are described. In an embodiment, a storage device stores a boot version number corresponding to a portion of a non-volatile memory. A memory controller logic causes an update of the stored boot version number in response to each subsequent boot event. The memory controller logic returns a zero in response to a read operation directed at the portion of the non-volatile memory and a mismatch between the stored boot version number and a current boot version number. Other embodiments are also disclosed and claimed. | 12-31-2015 |
20150378642 | FILE SYSTEM BACK-UP FOR MULTIPLE STORAGE MEDIUM DEVICE - A device may comprise a first data storage medium, a second data storage medium, and a controller. The controller may be configured to store file system information to the first data storage medium, storing a copy of file system information for the first data storage medium to the second data storage medium as a backup, loading the file system information from the first data storage medium to a cache memory when the file system information in the first data storage medium contains valid data, and loading the copy of the file system information from the second data storage medium to the cache when the file system information in the first data storage medium does not contain valid data. | 12-31-2015 |
20150378885 | SOLID STATE DRIVING INCLUDING NONVOLATILE MEMORY, RANDOM ACCESS MEMORY AND MEMORY CONTROLLER - A solid state drive includes a nonvolatile memory, a random access memory, and a memory controller. The nonvolatile memory contains a plurality of nonvolatile memories chips and a buffer chip. The memory controller is formed of an internal bus, a host interface, a memory interface, a buffer control circuit, and a processor. | 12-31-2015 |
20150378886 | SOFTWARE-DEFINED SSD AND SYSTEM USING THE SAME - Flash geometry information of the solid state disk (SSD) is maintained as is a logically-addressable SSD (laSSD) geometry information of the SSD. Based on the flash geometry and the laSSD geometry, virtual super blocks are configured by dynamically binding logical SSD logical block addresses (SLBAs) of a virtual super block with a physical super block within the laSSD. A virtual super block is made of a number of virtual blocks and each virtual block made of a number of virtual pages. Each of the virtual blocks corresponds to a physical block of a physical super block within the laSSD such that the virtual pages of the virtual block correspond to like physical pages of a corresponding physical block. Host logical block addresses (LBAs) are assigned to laSSD LBAs (SLBAs), which identify the virtual super blocks used for striping across physical super blocks. | 12-31-2015 |
20150378887 | NONVOLATILE MEMORY DEVICE AND OPERATING METHOD THEREOF - A nonvolatile memory device includes a mat including a plurality of memory blocks, an address decoder configured to select one of the memory blocks in response to an address, an input/output circuit including first and second page buffers configured to program a plurality of data pages into a single physical page of the selected one of the memory blocks or store the plurality of data pages read from the single physical page of the selected one of the memory blocks, and a control logic configured to perform a dumping operation at an other one of the first page buffers and second page buffers when a data input operation or a data output operation is performed at one of the first and second page buffers of the input/output circuit. The input/output circuit includes a plurality of page buffers. The plurality of page buffers include the first and second page buffers. | 12-31-2015 |
20150378888 | CONTROLLER, FLASH MEMORY APPARATUS, AND METHOD FOR WRITING DATA INTO FLASH MEMORY APPARATUS - A storage controller for determining an amount of data to be sent to a flash memory apparatus for storage comprises a communications interface for communicating with the flash memory apparatus and a processor. The flash memory apparatus comprises a block including a plurality of pages. And at least one of the pages is unavailable for storage. The processor is configured to receive information of the block sent by the flash memory apparatus, wherein the information includes capacity of one or more unavailable pages in the block. And then, the processor determines an available capacity of the block, based on the information and a total capacity of the block. Further, the processor obtains data to be sent to the flash memory apparatus, wherein an amount of the data is equal to the available capacity of the block. At last, the processor sends the data to the flash memory apparatus. | 12-31-2015 |
20150378889 | PERSISTENT CONTENT IN NONVOLATILE MEMORY - Applications may request persistent storage in nonvolatile memory. The persistent storage is maintained across power events and application instantiations. Persistent storage may be maintained by systems with or without memory management units. | 12-31-2015 |
20150378929 | SYNCHRONOUS AND ANSYNCHRONOUS DISCARD SCANS BASED ON THE TYPE OF CACHE MEMORY - A computational device maintains a first type of cache and a second type of cache. The computational device receives a command from the host to release space. The computational device synchronously discards tracks from the first type of cache, and asynchronously discards tracks from the second type of cache. | 12-31-2015 |
20150380110 | STORAGE CONTROL DEVICE AND STORAGE CONTROL METHOD - A storage control device that controls a solid state drive group including two or more solid state drives sharing data storage includes a detector that detects a wear state of each of the solid state drives, a separation controller that separates a solid state drive having a wear value, which represents a wear state, exceeding a first threshold among the solid state drives, and an enlargement controller that, when detecting a solid state drive having a wear value, which represents a wear state, exceeding a second threshold less than the first threshold among the solid state drives in the solid state drive group, enlarges a difference in a wear value, which represents a wear state, between the solid state drive having the wear value exceeding the second threshold and a remainder of the solid state drives. | 12-31-2015 |
20160004438 | STORAGE DEVICE INCLUDING NONVOLATILE MEMORY AND MEMORY CONTROLLER, AND OPERATING METHOD OF STORAGE DEVICE - An operation method of a storage device includes receiving quality of service (QoS) information of a plurality of virtual channels and storing the QoS information. A nonvolatile memory is accessed using different schemes according to the stored QoS information and commands received by virtual channels. The virtual channels are channels through which the storage device communicates with an external device. | 01-07-2016 |
20160004440 | SEMICONDUCTOR STORAGE DEVICE - According to an embodiment, a semiconductor storage device includes a first storage unit, a read control unit, a second storage unit, and a write control unit. The first storage unit is configured to store data supplied from a host device. The read control unit is configured to perform control of reading the data in accordance with a read request. The second storage unit is configured to store a logical address used for reading the data from the first storage unit by the read control unit. The write control unit is configured to perform control of adding the stored logical address to the data and write the resulting data into the first storage unit in a case where a size of the data requested to be written into the first storage unit by the host device is smaller than a threshold. | 01-07-2016 |
20160004446 | SYSTEM AND METHOD FOR PERFORMING DATA RETENTION IN SOLID-STATE MEMORY - Systems and methods for retaining data in non-volatile solid-state memory are disclosed in which refresh copy operations are performed on data stored in non-volatile solid-state memory. A controller may be configured to issue copy commands and to maintain usage data on a storage subsystem. A refresh copy operation helps ensure that data written to memory retain integrity by causing data to be programmed again onto the memory, which minimizes the risk of data error caused by electron leak in the non-volatile solid-state memory. The controller may be configured to maintain a list of physical memory locations storing data in non-volatile solid-state memory array, where the list is sorted by a least recently used criterion. In one embodiment, the controller may select a first entry from a top of the list for processing and issue a copy command stored in a current physical memory location associated with the first entry to a new physical memory location. The controller may be configured to remove the first entry from the top of the list and add a new entry associated with the new physical memory location to a bottom of the list. The controller may be further configured to repeat the select, repeat the select, issue, remove and add steps for a plurality of entries in the list, where the select, issue, remove and add steps are timed to be performed for all of the plurality of entries in the list within a set period of time. | 01-07-2016 |
20160004458 | SYSTEM AND METHOD FOR MEMORY BLOCK POOL WEAR LEVELING - A system and method for memory block pool wear leveling in a nonvolatile memory device. An improved bit error rate for the nonvolatile memory system is attained by identifying a plurality of memory block pools of the nonvolatile memory system, identifying a relaxation time delay for each of the plurality of memory block pools and executing a predetermined number of program/erase cycles for each of the plurality of memory block pools based upon the relaxation time delay of the memory block pools. | 01-07-2016 |
20160004459 | STORAGE SYSTEM AND STORAGE CONTROL METHOD - In executing a balancing process for moving data between a plurality of storage device groups constituted by a plurality of storage devices, a storage system determines whether or not to execute a balancing process for satisfying a first avoidance requirement for avoiding the occurrence of a problem in any one storage device only, on the basis of a second avoidance requirement which is satisfied by a second balancing process executed prior to a first balancing process for satisfying the first avoidance requirement, and executes the first balancing process in a case where the result of this determination is affirmative. | 01-07-2016 |
20160004463 | ELECTRONIC FLASH MEMORY EXTERNAL STORAGE METHOD AND DEVICE - An electronic flash memory external storage method and device for data processing system includes firmware which directly controls the access of electronic storage media and implements standard interface functions, adopts particular reading and writing formats of the external storage media, receives power via USB, externally stores data by flash memory and access control circuit with the cooperation of the firmware and the driver with the operating system, and has write-protection so that the data can be safely transferred. The method according to present invention is highly efficient and all parts involved are assembled as a monolithic piece so that it has large-capacity with small size and high speed. The device operates in static state and is driven by software. It is plug-and-play and adapted to data processing system. | 01-07-2016 |
20160004464 | SYSTEM AND METHOD OF UPDATING METABLOCKS - A method includes, in a data storage device that includes a non-volatile memory having multiple memory dies, determining whether one or more metablocks are metablock update candidates based on relinking metrics corresponding to the one or more metablocks. Each memory die of the multiple memory dies includes multiple blocks of storage elements and metablocks are formed through linking of blocks from the multiple memory dies. The method also includes comparing a number of the metablock update candidates to a relinking pool threshold. The method further includes, in response to the number of the metablock update candidates satisfying the relinking pool threshold, updating the linking of the blocks of the metablock update candidates to form updated metablocks. | 01-07-2016 |
20160004465 | CACHING SYSTEMS AND METHODS WITH SIMULATED NVDRAM - Systems and methods presented herein provide for simulated NVDRAM operations. In a host system, a host memory is sectioned into pages. An HBA in the host system comprises a DRAM and an SSD. The DRAM and the SSD are also sectioned into pages and mapped to pages of the host memory. A host processor is operable to generate Input/Output (I/O) requests. An HBA driver is operable to process the I/O requests. The HBA driver is also operable to detect when the pages of the DRAM are accessed, to determine a rate of page reclamation based on the detection, and to reclaim pages of data in the DRAM by moving pages of data from the DRAM into the pages of the SSD based on the determined rate of page reclamation. | 01-07-2016 |
20160004468 | DATA-STORAGE DEVICE AND FLASH MEMORY CONTROL METHOD - A data-storage device having a flash memory allocated to provide data-storage space, a valid page count table, logical-to-physical address mapping information, and an invalid block record. The data-storage device further having a controller, allocating the data-storage space to store data issued from a host, and establishing and maintaining the valid page count table, the logical-to-physical address mapping information, and the invalid block record in the FLASH memory to manage the data-storage space. A FLASH memory control method is also provided. | 01-07-2016 |
20160004469 | OPERATING METHOD OF MEMORY SYSTEM INCLUDING NAND FLASH MEMORY, VARIABLE RESISTANCE MEMORY AND CONTROLLER - An operating method is for a memory system which includes a NAND flash memory, a resistance variable memory, and a controller controlling the NAND flash memory and the resistance variable memory. The operating method includes receiving data, programming the received data in the NAND flash memory when the received data is at least a super page of data, programming the received data in the resistance variable memory when the received data is not a super page of data, and programming data accumulated in the resistance variable memory in the NAND flash memory when the accumulated data is a super page of data. A super page of data is an entirety of data that is programmable in memory cells connected to a same word line of the NAND flash memory. | 01-07-2016 |
20160004470 | NONVOLATILE STORAGE DEVICE AND OPERATING SYSTEM (OS) IMAGE PROGRAM METHOD THEREOF - A nonvolatile storage device in accordance with the inventive concepts includes a nonvolatile memory device comprising a first memory area, a second memory area, and a memory controller. The memory controller includes a first register configured to store reliable mode information, and a second register configured to store operating system (OS) image information. The memory controller is configured to receive a command from a host based on the reliable mode information; determine whether the command is a write request for an OS image and whether OS image information accompanying the command matches the OS image information stored in the second register; write the OS image to the first memory area if the OS image information accompanying the command matches the OS image information stored in the second register, and block data migration of the OS image from the first memory area to the second memory area. | 01-07-2016 |
20160004474 | Data Erasing Method and Apparatus Applied to Flash Memory - A data erasing method and apparatus applied to a flash memory. The method includes receiving a data erasing instruction, where the data erasing instruction instructs to erase data or at least one data section of data sections corresponding to data, when the data erasing instruction instructs to erase the data, searching for recorded storage addresses of all the data sections corresponding to the data, and erasing all the data sections corresponding to the data according to the storage addresses that are found; and when the data erasing instruction instructs to erase the at least one data section of the data sections corresponding to the data, searching for a recorded storage address of the at least one data section, and erasing the at least one data section according to the storage address that is found. The data erasing method and apparatus may be used in an implementation technology of the flash memory. | 01-07-2016 |
20160004479 | Scheduling Policy for Queues in a Non-Volatile Solid-State Storage - A method of applying scheduling policies is provided. The method includes distributing user data throughout a plurality of storage nodes through erasure coding, wherein the plurality of storage nodes are housed within a single chassis coupling the storage nodes as a cluster. The method includes receiving operations relating to a non-volatile memory of one of the plurality of storage nodes into a plurality of operation queues. The method includes evaluating each of the operations in the plurality of operation queues as to benefit to the non-volatile solid-state storage according to a plurality of policies. For each channel of a plurality of channels coupling the operation queues to the non-volatile memory, the method includes iterating a selection and an execution of a next operation from the plurality of operation queues, with each next operation having a greater benefit than at least a subset of operations remaining in the operation queues. | 01-07-2016 |
20160004599 | FILE BASED INCREMENTAL BLOCK BACKUP FROM USER MODE - A system for incremental backup comprises a storage device and a processor. The processor is configured to: 1) start tracking, wherein a file changed block info is tracked in map(s), wherein each of the map(s) tracks writes indicated via a node of a set of nodes; 2) receive request for an incremental backup of a volume of one or more volumes, wherein the map(s) track changed blocks from writes to the volume; 3) halt writes to the volume and queue writes to the volume after halting; 4) freeze the map(s) of changed blocks; 5) change tracking, wherein the change block info is tracked to a new set of maps; 6) determine changed blocks using the map(s); 7) write changed blocks to a backup volume; and 8) release writes to volume. | 01-07-2016 |
20160004612 | SYNCHRONOUS MIRRORING IN NON-VOLATILE MEMORY SYSTEMS - First data is received for storing in a first asymmetric memory device. A first writing phase is identified as a current writing phase. A first segment included in the first asymmetric memory device is identified as next segment available for writing data. The first data is written to the first segment. Information associated with the first segment is stored, along with information indicating that the first segment is written in the first writing phase. Second data is received for storing in the asymmetric memory. A second segment included in the first asymmetric memory device is identified as the next segment available for writing data. The second data is written to the second segment. Information associated with the second segment and the second memory block is stored along with information indicating that the second segment is written in the second writing phase. | 01-07-2016 |
20160004631 | Profile-Dependent Write Placement of Data into a Non-Volatile Solid-State Storage - A method for storing user data is provided. The method includes distributing the user data throughout a plurality of storage nodes through erasure coding, wherein the plurality of storage nodes are housed within a single chassis that couples the storage nodes as a cluster, each of the plurality of storage nodes having nonvolatile solid-state memory for user data storage. The method includes performing analytics on user data and grouping portions of the user data according to results of the analytics. The method includes writing the user data to blocks of flash memory in the non-volatile solid-state memory, wherein each block receives portions of the user data grouped according to at least one of the results of the analytics. | 01-07-2016 |
20160004632 | COMPUTING SYSTEM - A computing system is adapted to be coupled with a storage device or a remote device and includes a logic module with a first firmware, a control module coupled with the storage device, a management module coupled with the control module and the logic module, and a central process unit (CPU). The storage device includes a second firmware and an operating system. The remote device includes the second firmware. The CPU is coupled with the control module and operates the operating system. When the CPU receives a burning instruction, the CPU burns the second firmware into the logic module through the control module and the management module. | 01-07-2016 |
20160004633 | MEMORY MODULE SET, SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME, AND SEMICONDUCTOR MEMORY SYSTEM INCLUDING THE MEMORY MODULE SET - A memory module set includes a main integrated circuit (IC) for transmitting and receiving an electrical signal, a first group of memory modules including at least one memory module having a first pin unit connected to the main IC, and a second group of memory modules including at least one memory module having a second pin unit connected to the main IC. The groups of memory modules and the main IC are arrayed in a first direction on a substrate, and the second group of memory modules is offset with respect to the first group of memory modules in a second direction that is perpendicular to the first direction so as to have a position relative to the main IC in the second direction that is different from that of the first group of memory modules. | 01-07-2016 |
20160004634 | INTERNAL STORAGE, EXTERNAL STORAGE CAPABLE OF COMMUNICATING WITH THE SAME, AND DATA PROCESSING SYSTEM INCLUDING THE STORAGES - A memory controller, a data processing system, and an electronic device are provided. The memory controller is configured to share a function of one of an internal storage and an external storage in a union mode in which the external storage and the internal storage are logically unified with each other. | 01-07-2016 |
20160004635 | Managing the Write Performance of an Asymmetric Memory System - Some implementations include a method of managing a hosted non-volatile random-access memory (NVRAM) based storage subsystem that includes NVRAM devices. The method includes: receiving, at a device driver on the host computing device, write requests each requesting to write a respective unit of data to the NVRAM-based storage subsystem; categorizing the write requests into subgroups of write requests, where write requests within respective subgroups are mutually exclusive; ascertaining a load condition of each of several of the NVRAM devices of the NVRAM-based storage subsystem; identifying a target location on at least one NVRAM device to service a particular subgroup of write requests according to the ascertained load conditions of the NVRAM devices of the NVRAM-based storage subsystem; and servicing the particular subgroup of write requests by writing the corresponding units of data to the identified target location on the at least one NVRAM device of the NVRAM-based storage subsystem. | 01-07-2016 |
20160005454 | METHODS FOR MANUFACTURING AND OPERATING A MEMORY DEVICE AND A METHOD FOR OPERATING A SYSTEM HAVING THE SAME - A method for manufacturing a memory device includes detecting, with a tester, whether memory cells included in a memory device are defective, and programming, with the tester, start addresses of defect-free memory regions for addressing modes of the memory device based on a result of the detection. | 01-07-2016 |
20160005495 | REDUCING DISTURBANCES IN MEMORY CELLS - Methods for reducing program disturb in non-volatile memories are described. In some embodiments, a non-volatile storage system may acquire a first set of intermediate data to be written to a plurality of memory cells, determine a current set of intermediate data written in the plurality of memory cells, determine whether to invert the first set of intermediate data based on the current set of intermediate data, invert the first set of intermediate data, and write the inverted first set of intermediate data to the plurality of memory cells. The memory cells that are already at the correct state may be skipped over and not programmed, thereby improving programming speed and reducing the cumulative voltage stress applied to unselected memory cells. | 01-07-2016 |
20160011779 | NONVOLATILE MEMORY DEVICE, MEMORY CONTROLLER, AND OPERATING METHOD OF THE SAME | 01-14-2016 |
20160011781 | MEMORY CHIP, MEMORY SYSTEM, AND METHOD OF ACCESSING THE MEMORY CHIP | 01-14-2016 |
20160011785 | DATA MANAGEMENT METHOD, MEMORY CONTROL CIRCUIT UNIT AND MEMORY STORAGE APPARATUS | 01-14-2016 |
20160011786 | STORAGE SYSTEM AND DATA WRITE METHOD | 01-14-2016 |
20160011790 | SYSTEMS AND METHODS TO ENABLE ACCESS TO A HOST MEMORY ASSOCIATED WITH A UNIFIED MEMORY ARCHITECTURE (UMA) | 01-14-2016 |
20160011795 | ELECTRONIC CONTROL UNIT FOR VEHICLE AND DATA COMMUNICATION METHOD | 01-14-2016 |
20160011797 | INTELLIGENT ELECTRONIC DEVICE FOR RECEIVING AND SENDING DATA AT HIGH SPEEDS OVER A NETWORK | 01-14-2016 |
20160011799 | SOLID STATE DISK DEVICE | 01-14-2016 |
20160011801 | STORAGE REGION METADATA MANAGEMENT | 01-14-2016 |
20160011810 | SOLID-STATE MEMORY DEVICE WITH PLURALITY OF MEMORY DEVICES | 01-14-2016 |
20160011812 | Memory System | 01-14-2016 |
20160011818 | INFORMATION PROCESSING SYSTEM | 01-14-2016 |
20160011819 | STORAGE IN TIERED ENVIRONMENT WITH CACHE COLLABORATION | 01-14-2016 |
20160011878 | System-Level Dual-Boot Capability in Systems Having One or More Devices Without Native Dual-Boot Capability | 01-14-2016 |
20160011884 | Communicating With An Update Logic Image | 01-14-2016 |
20160011964 | PREDICTED DATA STORED AT A HOST MEMORY | 01-14-2016 |
20160011965 | PASS THROUGH STORAGE DEVICES | 01-14-2016 |
20160011966 | SOLID STATE MEMORY COMMAND QUEUE IN HYBRID DEVICE | 01-14-2016 |
20160011967 | STORAGE SYSTEM | 01-14-2016 |
20160011968 | LOGIC BLOCK ADDRESSING (LBA) CONFIGURATION METHOD AND NON-VOLATILE MEMORY DEVICE HAVING THE SAME | 01-14-2016 |
20160011969 | METHOD FOR ACCESSING DATA IN SOLID STATE DISK | 01-14-2016 |
20160011970 | MEMORY CONTROLLER, STORAGE DEVICE AND MEMORY CONTROL METHOD | 01-14-2016 |
20160011971 | STORAGE MEDIUM, MEMORY SYSTEM, AND METHOD OF MANAGING STORAGE AREA IN MEMORY SYSTEM | 01-14-2016 |
20160011972 | APPARATUS, SYSTEM, AND METHOD FOR A STORAGE LAYER | 01-14-2016 |
20160011973 | FLASH MEMORY CONTROLLER WITH CALIBRATED DATA COMMUNICATION | 01-14-2016 |
20160011974 | TECHNIQUES FOR CONTROLLING RECYCLING OF BLOCKS OF MEMORY | 01-14-2016 |
20160018990 | ELECTRONIC DEVICE AND METHOD FOR MANAGING MEMORY OF ELECTRONIC DEVICE - A method for managing a memory of an electronic device is provided. The method includes the operations of analyzing data to be stored, determining a memory to store a part or all of the data based on a type of a first memory, a type of a second memory, and a preset policy, and storing a part or all of the data in the determined memory. | 01-21-2016 |
20160018994 | MEMORY SYSTEM AND METHOD - According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller reads write data associated with a first write command from a host memory by a unit of a first size in response to the first write command from a host. The host memory is included in the host. In a case where the size of first data not yet read from the host memory out of the write data is less than a second size, in response to a second write command, the controller reads second data of the second size and writes the read second data into the nonvolatile memory. The second data includes the first data and third data included in write data associated with the second write command. After writing the second data into the nonvolatile memory, the controller transmits a notice for the first write command to the host. | 01-21-2016 |
20160018997 | MEMORY STORAGE DEVICE AND CONTROL METHOD THEREOF AND MEMORY CONTROL CIRCUIT UNIT AND MODULE - A memory storage device including a first and a second connection interface units, a memory control circuit unit and an interfacing circuit is provided. The first connection interface unit and the second connection interface unit are electrically connected to an input/output channel of the memory control circuit unit. The interfacing circuit is disposed between the memory control circuit unit and at least one of the first and the second connection interface units. The interfacing circuit is configured to provide determination information of an electrically connecting configuration between at least one host system and the at least one of the first and the second connection interface units. The memory control circuit unit is configured to provide different operation functions to the at least one host system based on the determination information. | 01-21-2016 |
20160018998 | Methods and Systems for Scalable Reliability Management of Non-Volatile Memory Modules - The various implementations described herein include systems, methods and/or devices used to perform a method of reliability management of data in a storage device having a plurality of memory modules. The method includes receiving or accessing a host command to perform a specified operation on a portion of non-volatile memory within a storage device. The method also includes, at a storage controller for the storage device, identifying a module of the plurality of modules, in accordance with the host command. The method includes, at the identified module, retrieving health information for the portion of non-volatile memory within the identified module, modifying one or more memory operation parameters in accordance with the specified operation and the retrieved health information, and executing the specified operation on the portion of non-volatile memory in the identified module in accordance with the one or more modified memory operation parameters. | 01-21-2016 |
20160019000 | PROMOTION OF PARTIAL DATA SEGMENTS IN FLASH CACHE - For efficient track destage in secondary storage in a more effective manner, for temporal bits employed with sequential bits for controlling the timing for destaging the track in a primary storage, if a first bit has at least one of a lower amount of holes and a hotter data heat metric, it is moved to the lower speed cache level. If the first bit has a hotter data heat and greater than a predetermined number of holes, the first bit is discarded. | 01-21-2016 |
20160019137 | Methods and Systems for Flash Buffer Sizing - The embodiments described herein are used to allocate memory in a storage system. The method includes, at a memory controller in the storage system, determining a current memory allocation for a set of memory devices, wherein the set of memory devices is formatted with a ratio of first storage density designated portions to second storage density designated portions in accordance with the current memory allocation. The method further includes detecting satisfaction of one or more memory reallocation trigger conditions. The method further includes, in response to detecting satisfaction of one or more memory reallocation trigger conditions, modifying the ratio of the first storage density designated portions to the second storage density designated portions in the set of memory devices to generate a second memory allocation for the set of memory devices. | 01-21-2016 |
20160019138 | MEMORY MODULE AND SYSTEM AND METHOD OF OPERATION - A memory module comprises a volatile memory subsystem configured to coupled to a memory channel in computer system and capable of serving as main memory for the computer system, a non-volatile memory subsystem providing storage for the computer system, and a module controller coupled to the volatile memory subsystem, the non-volatile memory subsystem, and the C/A bus. The module controller reads first data from the non-volatile memory subsystem in response to a Flash access request received via the memory channel, and causes at least a portion of the first data to be written into the volatile memory subsystem in response to a dummy write memory command received via the C/A bus. The module control device includes status registers accessible by the computer system via the memory bus. | 01-21-2016 |
20160019139 | MEMORY CONTROLLER AND METHOD FOR INTERLEAVING DRAM AND MRAM ACCESSES - A memory system and memory controller for interleaving volatile and non-volatile memory accesses are described. In the memory system, the memory controller is coupled to the volatile and non-volatile memories using a shared address bus. Activate latencies for the volatile and non-volatile memories are different, and registers are included on the memory controller for storing latency values. Additional registers on the memory controller store precharge latencies for the memories as well as page size for the non-volatile memory. A memory access sequencer on the memory controller asserts appropriate chip select signals to the memories to initiate operations therein. | 01-21-2016 |
20160019140 | SYNCHRONIZING A TRANSLATION LOOKASIDE BUFFER WITH AN EXTENDED PAGING TABLE - A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system. | 01-21-2016 |
20160019141 | METHOD AND APPARATUS FOR MAPPING A LOGICAL ADDRESS BETWEEN MEMORIES OF A STORAGE DRIVE BASED ON WRITE FREQUENCY RANKINGS - A storage drive including a first and second memories and a controller. The second memory has a write cycle lifetime that is less than a write cycle lifetime of the first memory. Each of the first and second memories includes solid-state memory. The controller: determines a write frequency for a first logical address; and based on the write frequency, determines a write frequency ranking for the first logical address. The write frequency ranking is based on a weighted time-decay average of write counts or an average of elapsed times of write cycles. The controller also: determines whether the write frequency ranking is greater than a lowest write frequency ranking of logical addresses of the first memory; and if the write frequency ranking of the first logical address is greater, maps the logical address with the lowest write frequency ranking in the first memory to the second memory. | 01-21-2016 |
20160019142 | Method of collecting garbage blocks in a solid state drive - A method of collecting garbage blocks in a solid state drive includes collecting a garbage block of a multiple level cell flash memory, selecting a spare block as a target block, copying effective data of the garbage block to a physical cell of the target block, searching for unprogrammed physical pages of the physical cell of the target block, using dummy data to complete programming of the unprogrammed physical pages of the physical cell, deleting the effective data in the garbage block, and recycling the garbage block to be a new spare block. | 01-21-2016 |
20160019164 | SYNCHRONIZING A TRANSLATION LOOKASIDE BUFFER WITH AN EXTENDED PAGING TABLE - A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system. | 01-21-2016 |
20160019165 | SYNCHRONIZING A TRANSLATION LOOKASIDE BUFFER WITH AN EXTENDED PAGING TABLE - A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system. | 01-21-2016 |
20160019166 | SYNCHRONIZING A TRANSLATION LOOKASIDE BUFFER WITH AN EXTENDED PAGING TABLE - A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system. | 01-21-2016 |
20160019968 | FLASH MEMORY DEVICE - A flash memory device includes a first page buffer, a second page buffer neighboring the first page buffer, a source-pick-up region disposed between the first page buffer and the second page buffer, and a source line extending in a direction. The source line includes a first portion that corresponds to the first page buffer and a second portion that corresponds to the second page buffer. A first resistance value of the first portion is substantially the same as a second resistance value of the second portion. | 01-21-2016 |
20160026386 | Suspending and Resuming Non-Volatile Memory Operations - A method of operation in a non-volatile memory system includes starting execution of a first memory operation from a first queue and in conjunction with starting a first timer, set to expire after a first predetermined time interval. The method further includes, in accordance with a determination that the first timer has expired, determining whether a second queue contains at least one memory operation for execution, and if so, suspending the first memory operation, executing a second memory operation from the second queue, and after completing execution of the second memory operation from the second queue, performing one or more subsequent operations (e.g., resuming execution of the first memory operation and restarting the first timer). In addition, the method includes, when the second queue does not contain at least one memory operation for execution, restarting the first timer, and continuing execution of the first memory operation from the first queue. | 01-28-2016 |
20160026387 | Method of writing data in a solid state drive - A method of writing data in a solid state drive includes receiving data, converting the data to a logical page having a logical allocation address and logical allocation data, a first connection table is searched for another logical page the same as the logical page, the logical page is merged with the another logical page, the logical allocation address is temporarily stored in the first connection table, the logical allocation data is temporarily stored in the data cache unit, it is determined if the first connection table is filled, and the logical page temporarily stored in the cache memory is written to a corresponding flash memory to increase efficiency. | 01-28-2016 |
20160026388 | DATA STORAGE DEVICE AND METHOD OF PROCESSING DATA THEREOF - A method of operating a data storage device includes fetching a first plurality of commands from at least one submission queue generated in a host memory, determining whether a ratio of a second plurality of commands from among the fetched first plurality of commands exceeds a reference ratio, and adjusting a number of a plurality of pointers being fetched at substantially a same time based on determining whether the ratio exceeds the reference ratio. The second plurality of commands has a same property, the plurality of pointers indicates a physical address of the host memory corresponding to the first plurality of commands, and the data storage device includes a storage controller configured to perform an interfacing operation with a host including the host memory. | 01-28-2016 |
20160026394 | IMAGE PROCESSING DEVICE, DATA ACCESSING METHOD, AND COMPUTER PROGRAM PRODUCT - According to an embodiment, an information processing device includes a storage, an access controller, a counter, a determination processor, and a deleter. The storage includes a NAND-type flash memory to store data. The access controller is configured to output an access request for accessing the data stored in the storage. The counter is configured to, when the access request represents a request for reading, increment a reading count for a memory area of the storage specified in the access request by one. The determination processor is configured to determine whether or not the reading count reaches a predetermined count. The deleter is configured to, when the determination processor determines that the reading count reaches the predetermined count, delete first data that is stored in the memory area corresponding to the reading count. | 01-28-2016 |
20160026399 | BLOCK I/O INTERFACE FOR A HOST BUS ADAPTER THAT UTILIZES NVDRAM - A block I/O interface for a HBA is disclosed that dynamically loads regions of a SSD of the HBA to a DRAM of the HBA. One embodiment is an apparatus that includes a host system and a HBA. The HBA includes a SSD and DRAM. The host identifies a block I/O read request for the SSD, identifies a region of the SSD that corresponds to the read request, and determines if the region is cached in the DRAM. If the region is cached in the DRAM, then the HBA copies data for the read request to the host memory and a response to the read request utilizes the host memory. If the region is not cached, then the HBA caches the region of the SSD in the DRAM, copies the data for the read request to the host memory, and a response to the read request utilizes the host memory. | 01-28-2016 |
20160026406 | METHODS, SYSTEMS, AND COMPUTER READABLE MEDIA FOR PROVIDING FLEXIBLE HOST MEMORY BUFFER - Methods, systems, and computer readable media for providing a flexible host memory buffer are disclosed. One method includes allocating an amount of host memory as a host memory buffer accessible by a solid state drive (SSD) as a cache for SSD data. The method further includes caching data from the solid state drive in the host memory buffer. The method further includes monitoring utilization of the host memory buffer. The method further includes dynamically increasing or decreasing the amount of host memory allocated for the host memory buffer based on the utilization. | 01-28-2016 |
20160026408 | STORAGE DEVICE METADATA SYNCHRONIZATION - Embodiments are disclosed relating to garbage collecting storage blocks in a storage device. In one embodiment, data is selected for relocation from a storage block in a storage device during reclaiming of the storage block. The data may be selected based on metadata that identifies whether data is valid at a time when the reclaiming is initiated. In some embodiments, prior to relocating data from the storage block, the metadata is captured from a data structure that identifies whether data on the storage device is valid. In one embodiment, a determination of whether the selected data has become invalid due to other data that is stored during the reclaiming is made. In some embodiments, in response to determining that the selected data has become invalid, the selected data is specified as invalid in the data structure. | 01-28-2016 |
20160026410 | Weighted Read Scrub for Nonvolatile Memory - In a nonvolatile memory array, such as a three-dimensional array of charge-storage memory cells, data is scrubbed according to a scheme which weights particular data that is exposed to potentially damaging voltages. Data that may cause damage to other data is moved to a location where such potential damage is reduced. | 01-28-2016 |
20160026471 | SEMICONDUCTOR DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor device includes one or more internal circuits; a nonvolatile memory circuit including a first region suitable for storing first data for the nonvolatile memory circuit and a second region suitable for storing second data for the internal circuits; a first register suitable for temporarily storing the first data; one or more second registers suitable for temporarily storing the second data; and a control circuit suitable for controlling the nonvolatile memory circuit to transmit the first data and the second data to the first register and to the second registers, respectively, when a boot-up operation is performed. | 01-28-2016 |
20160026472 | METHOD FOR IMPLEMENTING "INSTANT BOOT" IN A CUSTOMIZABLE SOC - A method for implementing an instant boot function in a customizable system on a chip (SoC) integrated circuit having an application specific integrated circuit portion including configuration registers includes providing a field programmable gate array fabric on the SoC, providing non-volatile memory cells on the SoC, and initializing the configuration registers using data from the non-volatile memory cells during a system reset mode of operation of the integrated circuit. | 01-28-2016 |
20160026544 | Using the Short Stroked Portion of Hard Disk Drives for a Mirrored Copy of Solid State Drives - Mechanisms for storing data to a storage system comprising a set of one or more solid state storage devices and a set of non-solid state storage devices are provided. A request to write data to the storage system is received and the data is written to the set of one or more solid state storage devices in response to receiving the request. Moreover, a mirror copy of the data is written to the set of non-solid state storage devices in response to receiving the request. Thus, the non-solid state storage devices serve as a mirror backup copy of the data stored to the solid state storage devices. | 01-28-2016 |
20160026563 | ELECTRONIC APPARATUS HAVING NONVOLATILE MEMORY AND PROGRAM WRITING METHOD FOR UPDATING - Provided is an electronic apparatus avoiding to be a starting failure status even if power off happens during the writing of a program. The electronic apparatus includes a rewritable nonvolatile memory, volatile memory, and a processor. The nonvolatile memory memorizes a plurality of programs. The volatile memory memorizes a plurality of programs for updating. The processor makes the plurality of programs memorize in volatile memory and writes in the plurality of programs for updating in a nonvolatile memory. In this case, in the state of reserving the start processing program and the header information before updating, a processor writes in the start processing program for updating, beforehand. Subsequently, the processor writes in the header information for updating. After that, the processor writes in the executive operation program for updating. | 01-28-2016 |
20160026564 | DETERMINING A LOCATION OF A MEMORY DEVICE IN A SOLID STATE DEVICE - A solid state device has a controller. The controller is configured to perform a first division operation that divides a received logical block address that indicates a physical memory block in a memory device of a plurality of memory devices in the solid state device by a number of logical block addresses per page of the physical memory block to obtain a result of the first division operation, configured to perform a second division operation that divides the obtained result of the first division operation by a number of memory devices in the plurality of memory devices, and configured to determine a location of the memory device of the plurality of memory devices within the solid state device from a location in a memory device table, the location in the memory device table identified by a remainder of the second division operation. | 01-28-2016 |
20160026575 | SELECTIVE MIRRORING IN CACHES FOR LOGICAL VOLUMES - Methods and structure for selective cache mirroring. One embodiment includes a control unit and a memory. The memory is able to store indexing information for a multi-device cache for a logical volume. The control unit is able to receive an Input/Output (I/O) request from a host directed to a Logical Block Address (LBA) of the logical volume, to consult the indexing information to identify a cache line for storing the I/O request, and to store the I/O request at the cache line on a first device of the cache. The control unit is further able to mirror the I/O request to another device of the cache if the I/O request is a write request, and to complete the I/O request without mirroring the I/O request to another device of the cache if the I/O request is a read request. | 01-28-2016 |
20160026578 | USE OF DIFFERING GRANULARITY HEAT MAPS FOR CACHING AND MIGRATION - For data processing in a computing storage environment by a processor device, the computing storage environment incorporating at least high-speed and lower-speed caches, and tiered levels of storage, groups of data segments are migrated between the tiered levels of storage such that if a selected group is cached in the lower-speed cache and is determined to become uniformly hot, migrating the selected group from the lower-speed cache to the SSD portion while refraining from processing data retained in the lower-speed cache until the selected group is fully migrated to the SSD portion. | 01-28-2016 |
20160026598 | STORAGE CONTROL DEVICES AND INVOKING METHOD THEREOF - A storage control device comprises a storage control module and a memory module. The storage control module is coupled between a central processing unit and a plurality of hard disk drives. The memory module is coupled with the storage control module and keeps a plurality of configuration files and a firmware for being executed by the storage control module. In one embodiment, the storage control module comprises at least one general-purpose input/output (GPIO) port and selects, according to whether the GPIO port is at a logical high or low electric potential, one of the configuration files to configure the firmware. The selected configuration file is invoked from a memory area of the memory module. In one embodiment, the storage control device further comprises at least one jumper point and selects, according to an open/close status of the jumper point, one of the configuration files to configure the firmware. | 01-28-2016 |
20160026783 | SYSTEM, APPARATUS, AND METHOD FOR ANTI-REPLAY PROTECTION OF DATA STORED IN A NON-VOLATILE MEMORY DEVICE - Embodiments of the present disclosure generally relate to a system, apparatus, and method for providing anti-replay protection of data stored in a non-volatile memory device. Some embodiments describe an anti-replay protection (ARP) device that may protect an external non-volatile memory device from replay attacks. | 01-28-2016 |
20160027511 | Computing Register with Non-Volatile-Logic Data Storage - A digital system includes a non-volatile calculating register having a set of latches configured to perform a calculation. A set of non-volatile storage cells is coupled to the set of latches. Access detection logic is coupled to the calculating register and is operable to initiate a calculation of a next value by the calculating register each time the calculating register is accessed by an accessing module. The access detection logic is operable to cause the next value to be stored in the set of non-volatile storage cells at the completion of the calculation as an atomic transaction. After a power loss or other restore event, the contents of the calculating register may be restored from the non-volatile storage cells. | 01-28-2016 |
20160027516 | EFFICIENT MODIFICATION OF DATA IN NON-VOLATILE MEMORY - Techniques are disclosed herein for efficient modification of data in non-volatile memory. In some examples, an update, such as a firmware update, may be generated for a first portion of data, such as firmware or a portion of firmware. In some cases, the first portion of data may be used in combination with a respective second portion of data. Also, in some cases, in combination with the update, various modifications may be determined for the second portion of data. Additionally, a set of tasks may be generated for performing the modifications to the second portion of data. The update may then be transmitted along with the set of tasks from one or more control devices to one or more update devices that are being updated with the update. | 01-28-2016 |
20160034189 | STORAGE DEVICE AND CONTROLLING METHOD THEREOF - A storage device includes a nonvolatile memory and a memory controller. The nonvolatile memory performs read, write, and erase operations. The memory controller operates in an operating mode where the memory controller exchanges a voltage signal, set to a reference voltage level within an allowable range, with the nonvolatile memory or receives the voltage signal from an external device. When operating in the operating mode, the memory controller optimizes an operating frequency of the nonvolatile memory depending on a voltage level of the voltage signal and a temperature. | 02-04-2016 |
20160034190 | Method for scheduling operation of a solid state disk - A method for scheduling operations of a solid state disk includes receiving accessing operations from a host, temporarily storing the accessing operations, setting a higher priority to the accessing operations having a shorter operation time, rearranging sequence of the accessing operations according to the set priorities, distributing the accessing operations to corresponding flash memories to process data according to the accessing operations, and transmitting processed data to the host to increase efficiency of the accessing operations. | 02-04-2016 |
20160034191 | GRID ORIENTED DISTRIBUTED PARALLEL COMPUTING PLATFORM - A distributed computing system includes a group of interconnected memory nodes, where one of the memory nodes is configured as a transaction ID manager. The transaction ID manager is configured to manage concurrency of database transactions by issuing a transaction ID for each database transaction performed in the system. In some embodiments, each memory node in the two-dimensional matrix is configured as a transaction ID manager. In such embodiments, the unique transaction IDs generated by the transaction ID manager at each memory node are transmitted with node-specific information, so that the unique transaction IDs generated at each memory node are distinguished from the unique transaction IDs generated by other memory nodes. | 02-04-2016 |
20160034194 | READ DISTURB AND DATA RETENTION HANDLING FOR NAND DEVICES - Systems, methods, and apparatus are herein disclosed for reducing read disturb and data retention errors in FLASH memory devices designed for long lifespans, such as greater than 10 or 15 years. Read disturb errors can be reduced by maintaining a read counter stored in a volatile memory and a FASTMAP memory block of the FLASH memory. When the read counter meets a threshold, then the associated memory block can be scheduled for scrubbing. Data retentions errors can be reduced by maintaining a last-erase timestamp in metadata of each memory block of a FLASH memory. When the last-erase timestamp associated with a given memory block meets a threshold, then the memory block can be scheduled for scrubbing. | 02-04-2016 |
20160034196 | Techniques to Configure a Solid State Drive to Operate in a Storage Mode or a Memory Mode - Examples are disclosed for configuring a solid state drive (SSD) to operate in a storage mode or a memory mode. In some examples, one or more configuration commands may be received at a controller for an SSD having one or more non-volatile memory arrays. The SSD may be configured to operate in at least one of a storage mode, a memory mode or a combination of the storage mode or the memory mode based on the one or more configuration commands. Other examples are described and claimed. | 02-04-2016 |
20160034198 | SYSTEM AND METHOD FOR MANAGING DISCARDABLE OBJECTS - A method and system of managing data in a storage device is provided. The method includes receiving a request to store content in a storage device. If the content is discardable content, the content is divided into a plurality of discardable data objects, each associated with at least one type of discarding priority data. The discardable data objects in the storage device are managed based on the discarding priority data associated with each discardable data object. Management of discardable objects may include selection and deletion of discardable objects based on discarding priority data, as well as further subdivision of existing discardable objects, to maintain a desired amount of free space on the storage device. The system may include a host having a processor and a storage device interface configured to execute the method, or a storage device having a processor configured to execute the disclosed methods. | 02-04-2016 |
20160034206 | Adaptive Flash Tuning - The present invention includes embodiments of systems and methods for increasing the operational efficiency and extending the estimated operational lifetime of a flash memory storage device (and its component flash memory chips, LUNs and blocks of flash memory) by monitoring the health of the device and its components and, in response, adaptively tuning the operating parameters of flash memory chips during their operational lifetime, as well as employing other less extreme preventive measures in the interim, via an interface that avoids the need for direct access to the test modes of the flash memory chips. In an offline characterization phase, “test chips” from a batch of recently manufactured flash memory chips are used to simulate various usage scenarios and measure the performance effects of writing and attempting to recover (read) test patterns written with different sets of operating parameters over time (simulating desired retention periods). | 02-04-2016 |
20160034207 | SYSTEMS AND METHODS TO IMPROVE THE RELIABILITY AND LIFESPAN OF FLASH MEMORY - A method for controlling flash memory is described. The method includes selecting a new forward error correction (FEC) parameter set that provides more redundancy than a current FEC parameter set. The method also includes coding source information bits, using the new FEC parameter set, during write operations to a first corrupted page in the flash memory. The method further includes mapping the first corrupted page and at least one additional corrupted page in the flash memory to a single logical page with an expected page size. | 02-04-2016 |
20160034211 | MEMORY SYSTEM AND INFORMATION PROCESSING DEVICE - According to an embodiment, a memory includes OS startup data, an OS and user data, and a program for copying the OS startup data, the OS, and the user data onto another memory system. In a case of a read-only mode, when receiving a read command for the OS startup data from the host device, a controller reads the program stored in the memory and transmit the program to a host device. | 02-04-2016 |
20160034216 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first processing unit configured to perform a calculation by using data stored in a memory; and a memory path controller configured to communicate with the first processing unit and control the memory for the first processing unit to perform the calculation, wherein the memory path controller includes an address region control unit configured to divide an address space of the memory to include a secure address and a non-secure address and permit the first processing unit to access the secure address or the non-secure address, and a first content firewall unit connected with the address region control unit and configured to prevent the first processing unit from writing secure contents in the non-secure address. | 02-04-2016 |
20160034217 | MEMORY CONTROLLER CONFIGURED TO CONTROL DATA SANITIZATION AND MEMORY SYSTEM INCLUDING THE SAME - Provided is a memory controller configured to control data sanitization. The memory controller includes a sanitization information storing unit configured to store first information or second information in a non-volatile manner, and a control unit configured to store the first information in the sanitization information storing unit when sanitization of data stored in a non-volatile memory has completed in response to a sanitization command of a host and store the second information in the sanitization information storing unit in response to a write command of the host. | 02-04-2016 |
20160034218 | MULTI-LEVEL DATA PROTECTION FOR NONVOLATILE MEMORY SYSTEM - The disclosed embodiments are directed to methods and apparatuses for providing efficient and enhanced protection of data stored in a nonvolatile memory system. The methods and apparatuses involve a system controller for a plurality of nonvolatile memory devices in the nonvolatile memory system that is capable of protecting data using two layers of data protection, including inter-card card stripes and intra-card page stripes. | 02-04-2016 |
20160034221 | MEMORY SYSTEM AND CONTROL METHOD THEREOF - According to one embodiment, a memory system is provided with a nonvolatile memory, a controller, a volatile memory and an address translation table. The address translation table includes a high level and a plurality of low levels. The high level indicates positions in the nonvolatile memory in which the low levels are recorded. The low levels indicate positions in the nonvolatile memory in which data is recorded. The controller holds the high level of the address translation table in the first area of the volatile memory, and shuts off the supply of power to the second area of the volatile memory based on a transition from a normal-power state to a low-power state. | 02-04-2016 |
20160034224 | IN-PLACE CHANGE BETWEEN TRANSIENT AND PERSISTENT STATE FOR DATA STRUCTURES ON NON-VOLATILE MEMORY - Methods and apparatus related to in-place change between transient and persistent state for data structures on non-volatile memory are described. In one embodiment, controller logic causes a change in a state of a first portion of one or more non-volatile memory devices between a persistent state and a transient state and without moving data stored in the first portion of the one or more non-volatile memory devices. Other embodiments are also disclosed and claimed. | 02-04-2016 |
20160034227 | Flash Storage Controller Execute Loop - A storage controller is provided that contains multiple processors. In some embodiments, the storage controller is coupled to a flash memory module having multiple flash memory groups, each flash memory group corresponding to a distinct flash port in the storage controller, each flash port comprising an associated processor. Each processor handles a portion of one or more host commands, including reads and writes, allowing multiple parallel pipelines to handle one or more host commands simultaneously. | 02-04-2016 |
20160034386 | CONTROLLING WEAR AMONG FLASH MEMORY DEVICES BASED ON REMAINING WARRANTY - A computer readable storage medium embodies program instructions executable by a processor to perform a method including identifying a product warranty for each of a plurality of flash memory devices within a system, wherein the product warranty includes a maximum number of writes and a maximum age, and tracking the number of writes and the age of each flash memory device. The method further includes determining, for each flash memory device, a number of pro rata writes remaining in the product warranty, which is determined as a number of writes remaining until the flash memory device reaches the maximum number of writes divided by an amount of time remaining until the flash memory reaches the maximum age. The method then causes data to be written to the flash memory device having the greatest number of pro rata writes remaining in the product warranty. | 02-04-2016 |
20160034387 | CONTROLLING WEAR AMONG FLASH MEMORY DEVICES BASED ON REMAINING WARRANTY - A method includes identifying a product warranty for each of a plurality of flash memory devices within a system, wherein the product warranty includes a maximum number of writes and a maximum age, and tracking the number of writes made to each flash memory device and the age of each flash memory device. The method further includes determining, for each flash memory device, a number of pro rata writes remaining in the product warranty, which is determined as a number of writes remaining until the flash memory device reaches the maximum number of writes identified in the product warranty divided by an amount of time remaining until the flash memory reaches the maximum age identified in the product warranty. The method then causes data to be written to the flash memory device having the greatest number of pro rata writes remaining in the product warranty. | 02-04-2016 |
20160034388 | DATA MANAGEMENT METHOD, MEMORY CONTROL CIRCUIT UNIT AND MEMORY STORAGE APPARATUS - A data management method is provided, and the method includes: receiving first data and identifying a first address. The method also includes: determining whether the first data is incompressible; and, if the first data is incompressible, determining whether the first address is meeting a requirement of start address. The method further includes: if the first address is not meeting the requirement of start address, storing the padding data starting from the first address, and storing the first data starting from a following address, wherein the following address is meeting the requirement of start address. | 02-04-2016 |
20160034389 | DATA STORAGE DEVICE AND METHOD FOR OPERATING THE SAME - A data storage device includes a memory including a plurality of memory blocks each of which includes a plurality of pages suitable for storing data transmitted from a host, and a controller suitable for storing data storage information on the data stored in the memory, wherein the data storage information is updated based on valid pages where the data are stored among the plurality of the pages. | 02-04-2016 |
20160034390 | MEMORY CONTROLLER, METHOD THEREOF, AND ELECTRONIC DEVICES HAVING THE MEMORY CONTROLLER - A method for operating a memory controller is provided. The method includes generating a pseudo random number by using a seed included in a stored seed group corresponding to a page to be currently programmed, wherein the stored seed group is stored among a plurality of seed groups. Data to be programmed into the current page is randomizing by using the pseudo random number and the memory controller outputs the randomized data. A solid state drive (SSD) or other memory storage device such as a memory card includes the memory controller and includes a read only memory (ROM) storing the plurality of seed groups. The memory controller includes a micro-processor and a read only memory (ROM) storing executable code for causing the micro-processor to access the plurality of stored seed groups and to select a seed therefrom corresponding to a page to be currently programmed. | 02-04-2016 |
20160041599 | Determining A Write Operation - Technologies are generally described herein for writing data to either volatile or nonvolatile memory. An estimated time for a last write operation to occur and an estimated time to a power down event are determined. A threshold time is generated from the estimated time for a last write operation to occur and the estimated time to a power down event. The threshold time represents time at which a cost to write to volatile memory may become greater than a cost to write to nonvolatile memory. The cost may be based at least in part on the need to copy data stored in a volatile memory to be persisted after a power down event from the volatile to the nonvolatile memory. | 02-11-2016 |
20160041758 | TAPE-MANAGED PARTITION SUPPORT FOR EFFECTIVE WORKLOAD ALLOCATION AND SPACE MANAGEMENT - In one embodiment, a system includes a disk cache and a controller configured to create a cache resident partition in the disk cache, the cache resident partition being configured to store data thereto that is not subject to HSM, manage the cache resident partition to have a size that is greater than a first minimum size and less than or equal to a total size of the disk cache, receive data to store to the disk cache, store the data to the cache resident partition at least initially, create tape-managed partitions in the disk cache, each of the tape-managed partitions being configured to store data that is subject to HSM, and manage the tape-managed partitions to have a size that is greater than a second minimum size and less than or equal to a total size of the disk cache less a size of all other partitions combined. | 02-11-2016 |
20160041759 | STORAGE SYSTEM AND DATA TRANSMITTING METHOD THEREOF - A storage system comprises: a storage device including a NAND flash memory and a storage controller for controlling the NAND flash memory, and a host device including a host controller for interacting with the storage controller and a file system for generating a read command or a write command for data pieces in the unit of blocks. At this time, when the read command or the write command for the data pieces is generated, the host device and the storage device transmit/receive the data pieces in the unit of data transmission corresponding to a sector size. When read data pieces are determined by the write command, the host device collects first space data pieces related to the write data pieces and transmits the first spare data pieces to the storage device first and then the write data pieces. | 02-11-2016 |
20160041760 | Multi-Level Cell Flash Memory Control Mechanisms - Mechanisms are provided, in multi-layer cell (MLC) flash memory device comprising a MLC flash memory and a controller, for controlling an operation of the MLC flash memory device. The controller controls accesses to a block of memory pages in the MLC flash memory to be performed to the full block of memory pages in a MLC mode of operation. The controller determines whether a MLC retirement threshold has been met or exceeded by an operating characteristic of the block of memory pages. The controller, in response to detecting that the operating characteristic of the block of memory pages has met or exceeded the MLC retirement threshold, switches an operating mode associated with the block of memory pages from the MLC mode of operation to a single-level cell (SLC) mode of operation. The controller enforces the SLC mode of operation when performing access operations to the block of memory pages. | 02-11-2016 |
20160041762 | MEMORY SYSTEM, HOST DEVICE AND INFORMATION PROCESSING SYSTEM - According to one embodiment, a memory system includes a nonvolatile memory and a controller which controls the nonvolatile memory. The controller notifies to an outside an extensive signal which indicates a predetermined state of the nonvolatile memory or the controller. | 02-11-2016 |
20160041767 | MEMORY SYSTEM AND CONTROL METHOD THEREOF - A memory system includes a nonvolatile memory including a plurality of blocks as data erase units, a measuring unit which measures an erase time at which data of each block is erased, and a block controller which writes data supplied from at least an exterior into a first block which is set in a free state and whose erase time is oldest. | 02-11-2016 |
20160041771 | Techniques for Surfacing Host-Side Flash Storage Capacity to Virtual Machines - Techniques for surfacing host-side flash storage capacity to a plurality of VMs running on a host system are provided. In one embodiment, the host system creates, for each VM in the plurality of VMs, a flash storage space allocation in a flash storage device that is locally attached to the host system. The host system then causes the flash storage space allocation to be readable and writable by the VM as a virtual flash memory device. | 02-11-2016 |
20160041773 | SYSTEM AND METHOD FOR MULTISTAGE PROCESSING IN A MEMORY STORAGE SUBSYSTEM - Embodiments of this disclosure relate to improving solid-state non-volatile memory management. Embodiments improve the management of solid-state non-volatile memory by providing an execution manager responsible for controlling the timing of providing a request to a memory unit for execution. In embodiments, the execution manager traverses a list of received requests for memory access and dispatches commands for execution. In embodiments, if a request is directed to memory units which have reached a threshold for outstanding requests, the request may be skipped so that other requests can be dispatched for memory units which have not yet reached the threshold. | 02-11-2016 |
20160041783 | MEMORY DEVICE, MEMORY SYSTEM, AND METHOD OF OPERATING THE MEMORY SYSTEM - A method of operating a memory system, having a non-volatile memory device, includes processing a response to a first request toward the memory device by using an original key, in response to the first request, generating and storing first parity data corresponding to the original key, and deleting the original key. | 02-11-2016 |
20160041786 | Storage Module and Method for Optimized Power Utilization - A storage module and method are provided for optimized power utilization. In one embodiment, a storage module is provided comprising a storage controller and a plurality of memory dies in communication with the storage controller. The storage controller determines if sufficient power is available to perform an operation on one of the memory dies. In response to determining that sufficient power is not available to perform the operation on one of the memory dies, the storage controller determines if suspending an in-progress operation on another one of the memory dies would provide enough power to perform the operation. In response to determining that suspending the in-progress operation would provide enough power to perform the operation, the storage controller suspends the in-progress operation and performs the operation. Instead of suspending an in-progress operation, the storage controller can instead use a reduced power version of the operation or the in-progress operation. | 02-11-2016 |
20160041793 | SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR CONTROLLING NONVOLATILE SEMICONDUCTOR MEMORY - According to embodiments, a controller comprises a write control unit that performs writing in a nonvolatile semiconductor memory, and an area management unit that causes the write control unit to perform write processing until a spare area not storing valid data is not present in the nonvolatile semiconductor memory, and transmits an error to a host when the spare area is not present. | 02-11-2016 |
20160041902 | APPARATUS, SYSTEM, AND METHOD FOR DESTAGING CACHED DATA - Apparatuses, systems, methods, and computer program products are disclosed for destaging cached data. A method includes caching write in a nonvolatile solid-state cache by appending the data to a log of the nonvolatile solid-state cache. The log includes a sequential, log-based structure preserved in the nonvolatile solid-state cache. A method includes destaging at least a portion of the data from the nonvolatile solid-state cache to the backing store in a cache log order. The cache log order comprises an order in which the data was appended to the log of the nonvolatile solid-state cache. | 02-11-2016 |
20160041903 | Garbage collection based on temperature - A storage device made up of multiple storage media is configured such that one such media serves as a cache for data stored on another of such media. The device includes a controller configured to manage the cache by consolidating information concerning obsolete data stored in the cache with information concerning data no longer desired to be stored in the cache, and erase segments of the cache containing one or more of the blocks of obsolete data and the blocks of data that are no longer desired to be stored in the cache to produce reclaimed segments of the cache. | 02-11-2016 |
20160041904 | FILE SYSTEM INDIRECTION TECHNIQUE FOR DIRECTLY MANAGING SOLID STATE DEVICES - A technique uses file system indirection to manage solid state devices (SSDs). Based on relocation of data on the SSDs from a first SSD storage block to a second SSD storage block, a flash translation layer (FTL) driver may update a per-volume indirection file to reference the second SSD storage block and no longer reference the first SSD storage block. Based on a mismatch between the per-volume indirection file and a buffer tree, the buffer tree is updated to reference the second SSD storage block. Alternatively, the FTL driver may create and insert an entry into a mapping table, wherein the entry may reference the first SSD storage block and also reference the second SSD storage block. The buffer tree may then be updated to reference the second SSD storage block based on the new entry, and the new entry may then be deleted after the buffer tree is updated. | 02-11-2016 |
20160041918 | KEY VALUE-BASED DATA STORAGE SYSTEM AND OPERATION METHOD THEREOF - The present invention relates to a data storage system. The present invention provides a key value-based data storage system and an operation method thereof, the data storage system comprising: computing nodes, each of which includes a substrate module, a central processing unit, a memory arranged in the substrate module, and a NAND flash storage for cache storage; and a communication interface for interconnecting the computing nodes, wherein the computing nodes support key value-based data processing. | 02-11-2016 |
20160042005 | TECHNIQUES FOR IMPLEMENTING HYBRID FLASH/HDD-BASED VIRTUAL DISK FILES - Techniques for utilizing flash storage as an extension of hard disk (HDD) storage are provided. In one embodiment, a computer system stores a subset of blocks of a logical file in a first physical file, associated with a first data structure that represents a filesystem object, on flash storage and a subset of blocks, associated with a second data structure that represents a filesystem object comprising tiering configuration information that includes an identifier of the first physical file, in a second physical file on HDD storage. The computer system processes an I/O request directed to the logical file by directing it to either the physical file on the flash storage or the HDD storage by verifying that the tiering configuration information exists in the data structure and determining whether the one or more blocks are part of the first subset of blocks or the second subset of blocks. | 02-11-2016 |
20160048328 | MEMORY SYSTEM - A memory system in the embodiment includes an address conversion table including a first conversion table and a second conversion table, a management table storing the first information that indicates whether the second conversion table is a first state, and a controller. In the case where determining based on the first information that the second conversion table written from a volatile second memory to a nonvolatile first memory is in the first state, the controller updates the first conversion table and releases the storage area of the second conversion table used for the writing from the second memory. | 02-18-2016 |
20160048332 | SET-ASSOCIATIVE HASH TABLE ORGANIZATION FOR EFFICIENT STORAGE AND RETRIEVAL OF DATA IN A STORAGE SYSTEM - The embodiments described herein are directed to the use of hashing in a file system metadata arrangement that reduces an amount of metadata stored in a memory of a node in a cluster and that reduces the amount of metadata needed to process an input/output (I/O) request at the node. Illustratively, the embodiments are directed to cuckoo hashing and, in particular, to a manner in which cuckoo hashing may be modified and applied to construct the file system metadata arrangement. In an embodiment, the file system metadata arrangement may be illustratively include a hash collision technique that employs a hash collision computation to determine a unique candidate extent key (having a candidate hash table index) in the event of a collision, i.e., a hash table index collides with a slot of a hash table matching a key found in the slot. | 02-18-2016 |
20160048333 | DENSE TREE VOLUME METADATA UPDATE LOGGING AND CHECKPOINTING - The embodiments described herein are directed to efficient merging of metadata managed by a volume layer of a storage input/output (I/O) stack executing on one or more nodes of a cluster. The metadata managed by the volume layer, i.e., the volume metadata, is illustratively organized as a multi-level dense tree metadata structure, wherein each level of the dense tree metadata structure (dense tree) includes volume metadata entries for storing the volume metadata. The volume metadata entries of an upper level of the dense tree metadata structure are merged with the volume metadata entries of a next lower level of the dense tree metadata structure when the upper level is full. The volume metadata entries of the merged levels are organized as metadata pages and stored as one or more files on the SSDs. | 02-18-2016 |
20160048336 | Electronic Control Unit and Method for Rewriting Data - An electronic control unit includes: a nonvolatile memory capable of erasing data in units of erasure blocks and also writing data in units of write blocks smaller than the erasure blocks; and a processor. In response to a data rewrite request from outside, the processor of the electronic control unit erases data in a portion of the nonvolatile memory in units of erasure blocks and writes data into the portion of the nonvolatile memory in units of write blocks. The amount of data sent to the electronic control unit from outside is thereby decreased and the time needed to rewrite data in the nonvolatile memory is reduced. | 02-18-2016 |
20160048338 | MEMORY BLOCK QUALITY IDENTIFICATION IN A MEMORY - Methods of operating electronic systems having a memory include reading indications of memory block quality from a plurality of memory blocks of the memory in which a memory defect has been detected, wherein a value of the indication of memory block quality stored in a respective memory block of the plurality of memory blocks indicates a type of memory defect detected in the respective memory block, and, in response to the values of the indications of memory block quality, deeming a first portion of memory blocks of the plurality of memory blocks as usable, allocating a second portion of memory blocks of the plurality of memory blocks for storing only data of a particular type, and indicating a third portion of memory blocks of the plurality of memory blocks as defective. | 02-18-2016 |
20160048343 | APPARATUSES AND METHODS FOR CONCURRENTLY ACCESSING DIFFERENT MEMORY PLANES OF A MEMORY - Apparatuses and methods for performing concurrent memory access operations for different memory planes are disclosed herein. An example apparatus may include a memory array having a plurality of memory planes. Each of the plurality of memory planes comprises a plurality of memory cells. The apparatus may further include a controller configured to receive a group of memory command and address pairs. Each memory command and address pair of the group of memory command and address pairs may be associated with a respective memory plane of the plurality of memory planes. The internal controller may be configured to concurrently perform memory access operations associated with each memory command and address pair of the group of memory command and address pairs of the group of memory command and address pairs regardless of page types associated with the pairs of the group (e.g., even if two or more of the memory command and address pairs may be associated with different page types). | 02-18-2016 |
20160048344 | DISTRIBUTED CACHING SYSTEMS AND METHODS - Example distributed caching systems and methods are described. In one implementation, a system has multiple host systems, each of which includes a cache resource that is accessed by one or more consumers. A management server is coupled to the multiple host systems and presents available cache resources and resources associated with available host systems to a user. The management server receives a user selection of at least one available cache resource and at least one host system. The selected host system is then configured to share the selected cache resource. | 02-18-2016 |
20160048352 | SYSTEM DATA STORAGE MECHANSIM PROVIDING COHERENCY AND SEGMENTED DATA LOADING - A data storage subsystem is disclosed that implements a process for storing and/or reconstructing system data, such as a system mapping table. In certain embodiments, table pages are systematically copied, or flushed, to non-volatile memory in a progressive manner, according to a fixed ratio of flushed table pages per table update trigger, thereby facilitating write and/or load efficiency. Full or partial reconstruction of a table may be performed within a bounded number of operations based on the size of the table, the ratio implemented, and/or other characteristics. | 02-18-2016 |
20160048353 | MEMORY SYSTEM AND METHOD OF CONTROLLING MEMORY SYSTEM - According to one embodiment, a first controller stores access restriction information in a non-volatile first memory. A second controller reads the access restriction information from the first memory and controls access by a host device to a non-volatile second memory based on the access restriction information. The access restriction information includes a start address or a size for each of segmented areas obtained by segmenting an address space of the second memory into a plurality of areas, and first access information indicating accessibility to the segmented areas. | 02-18-2016 |
20160048354 | METHOD AND SYSTEM FOR ATOMICALLY WRITING SCATTERED INFORMATION IN A SOLID STATE STORAGE DEVICE - Disclosed herein are several methods and systems for handling atomic write commands that reach scattered address ranges. One embodiment includes a method of performing an operation in a data storage device, the method comprising: receiving an atomic write command; obtaining a plurality of ranges of logical addresses affected by the atomic write command; for each of the plurality of affected ranges, assigning metadata information to track completion of a write operation performed at that range; performing the write operations in the ranges of logical addresses; updating the metadata information upon completion of the write operations in the ranges; and deferring an update to a translation map of the data storage device until the metadata information has been updated. | 02-18-2016 |
20160048448 | METHOD FOR MAPPING PAGE ADDRESS BASED ON FLASH MEMORY AND SYSTEM THEREFOR - The present invention relates to a method for a page-level address mapping based on flash memory and a system thereof. A method for a page-level address mapping based on a flash memory according to an embodiment of the present invention includes the steps of: receiving a write operation from a file system; generating condensed mapping information using a size of data information of the write operation and a start logical address of sequentially allocated logical addresses of the write operation; and storing the condensed mapping information as a first mapping table in a memory of a flash translation. | 02-18-2016 |
20160048459 | OPERATION METHOD OF MEMORY CONTROLLER AND NONVOLATILE MEMORY SYSTEM INCLUDING THE MEMORY CONTROLLER - A nonvolatile memory system includes a nonvolatile memory device having a physical storage area, and a memory controller managing the physical storage area on the basis of first and second logical areas. The memory controller is configured to receive a logical block address range corresponding to a part of the first logical area and a command from a host and is configured to receive data, a logical block address and a write command from the host to perform an update with respect to the second logical area. When, in the update operation, the received logical block address is included in the logical block address range, the memory controller, in response to the write command, redirects the received logical block address to a logical page number of the second logical area so that the data is written in the second logical area. | 02-18-2016 |
20160054922 | DATA MANAGEMENT SCHEME IN VIRTUALIZED HYPERSCALE ENVIRONMENTS - According to one general aspect, a memory management unit (MMU) may be configured to interface with a heterogeneous memory system that comprises a plurality of types of storage mediums. Each type of storage medium may be based upon a respective memory technology and may be associated with performance characteristic(s). The MMU may receive a data access for the heterogeneous memory system. The MMU may also determine at least one of the storage mediums of the heterogeneous memory system to service the data access. The target storage medium may be selected based upon at least one performance characteristic associated with the target storage medium and a quality of service tag that is associated with the virtual machine and that indicates one or more performance characteristics. The MMU may route the data access by the virtual machine to the at least one of the storage mediums. | 02-25-2016 |
20160054925 | CONFIGURATION INFORMATION BACKUP IN MEMORY SYSTEMS - According to one configuration, a memory system includes a configuration manager and multiple memory devices. The configuration manager includes status detection logic, retrieval logic, and configuration management logic. The status detection logic receives notification of a failed attempt by a first memory device to be initialized with custom configuration settings stored in the first memory device. In response to the notification, the retrieval logic retrieves a backup copy of configuration settings information from a second memory device in the memory system. The configuration management logic utilizes the backup copy of the configuration settings information retrieved from the second memory device to initialize the first memory device. | 02-25-2016 |
20160054931 | STORAGE DEVICES AND METHODS FOR OPTIMIZING USE OF STORAGE DEVICES BASED ON STORAGE DEVICE PARSING OF FILE SYSTEM METADATA IN HOST WRITE OPERATIONS - The subject matter described herein includes processing file system metadata in host write requests to determine information about future host write operations. The information regarding future host write operations can be used by a device controller to prepare the non-volatile memory for the future host write operations. For example, the device controller may prepare the non-volatile storage device for future sequential host write access patterns or random host write access patterns depending on the content of the file system metadata. The file system metadata may also be usable to determine when it is optimal to perform memory management operations. | 02-25-2016 |
20160054933 | UNIFIED ADDRESSING AND HIERARCHICAL HETEROGENEOUS STORAGE AND MEMORY - According to one general aspect, an apparatus may include a processor, a heterogeneous memory system, and a memory interconnect. The processor may be configured to perform a data access on data stored in a memory system. The heterogeneous memory system may include a plurality of types of storage mediums. Each type of storage medium may be based upon a respective memory technology and may be associated with one or more performance characteristics. The heterogeneous memory system may include both volatile and non-volatile storage mediums. The memory interconnect may be configured to route the data access from the processor to at least one of the storage mediums based, at least in part, upon the one or more performance characteristic associated with the respective memory technologies of the storage media. | 02-25-2016 |
20160054934 | METHODS, SYSTEMS, AND COMPUTER READABLE MEDIA FOR AUTOMATICALLY DERIVING HINTS FROM ACCESSES TO A STORAGE DEVICE AND FROM FILE SYSTEM METADATA AND FOR OPTIMIZING UTILIZATION OF THE STORAGE DEVICE BASED ON THE HINTS - Methods, systems, and computer readable media for automatically deriving hints from storage device accesses and from file system metadata and for utilizing the hints to optimize utilization of the memory storage device are provided. One method includes analyzing an input/output operation involving non-volatile memory or file system metadata. The method further includes automatically deriving, based on results from the analyzing, a hint regarding an expected access pattern to the non-volatile memory. The method further includes using the hint to optimize utilization of the non-volatile memory. | 02-25-2016 |
20160054935 | DATA STORING METHOD AND MEMORY CONTROLLER AND MEMORY STORAGE DEVICE USING THE SAME - A data storing method for a rewritable non-volatile memory module and a memory controller and a memory storage device using the same are provided. The data storing method includes moving or writing data into a physical erase unit of the rewritable non-volatile memory module and determining whether the physical erase unit contains a dancing bit. The data storing method further includes when the physical erase unit contains the dancing bit, restoring the rewritable non-volatile memory module to the state before the data is moved or moving the data from the physical erase unit to another physical erase unit. Thereby, the data storing method can effectively ensure the reliability of the data. | 02-25-2016 |
20160054936 | INFORMATION PROCESSING SYSTEM AND NONVOLATILE STORAGE UNIT - According to one embodiment, a memory system includes a nonvolatile storage device and an information processing apparatus. The information processing apparatus includes a first control circuit configured to send a delete notification to the nonvolatile storage device to invalidate data in a first logical address area when read data corresponding to the first logical address area is the same as data expressed by a first function. The nonvolatile storage device include a nonvolatile storage medium, a management table configured to associate a logical address corresponding to valid data for the nonvolatile storage device with a physical address, and a second control circuit configured to update the management table to invalidate a logical address designated by the delete notification, and to send the data expressed by the first function to the information processing apparatus when a logical address included in a read instruction received from the information processing apparatus is invalid. | 02-25-2016 |
20160054937 | TEMPERATURE ACCELERATED STRESS TIME - A memory system or flash card may be exposed to elapsed time or increased temperature conditions which may degrade the memory. For example, extended time periods or high temperature conditions may hinder data retention in a memory device. An estimate of elapsed time and temperature conditions may be useful for memory management. An algorithm that periodically identifies one or more sentinel blocks in the memory device and measures the data retention shift in those sentinel blocks can calculate a scalar value that approximates the combined effect of elapsed time and/or temperature conditions. | 02-25-2016 |
20160054938 | MEMORY MANAGEMENT DEVICE AND METHOD - According to one embodiment, a device includes a determination unit, compression unit, selecting unit, write updating unit, writing unit. The determination unit determines whether to compress write data based on specific information. The specific information including at least one of the type, number of accesses, access frequency and importance level of the write data. The compression unit compresses the write data when determining to compress the write data. The selecting unit selects a write region for the write data in nonvolatile memory based on the specific information. The write updating unit updates the specific information. The writing unit writes compressed write data into the write region when determining to compress the write data. The writing unit writes uncompressed write data into the write region when not determining to compress the write data. | 02-25-2016 |
20160054943 | INFORMATION PROCESSING APPARATUS - According to one embodiment, an information processing apparatus includes a memory system and a host. The memory system includes a nonvolatile first memory and a first control unit. The host includes a volatile second memory and a second control unit. The second memory includes a first area which is used by the host and a second area which is used by the memory system. The second control unit transmits an access request to the first control unit. The access request contains an address. The first control unit determines whether an access destination is the first memory or the second area based on the address and accesses the determined access destination. | 02-25-2016 |
20160055080 | MEMORY SYSTEM - A memory system according to an embodiment of the present invention comprises: speed of processing for searching through management tables is increased by providing a forward lookup table for searching for, respectively in track and cluster units, from a logical address, a storage device position where data corresponding to the logical address and a reverse lookup table for searching for, from a position of the storage device, a logical address stored in the position and linking these tables. | 02-25-2016 |
20160055092 | ADAPTIVE RECORD CACHING FOR SOLID STATE DISKS - A storage controller receives a request that corresponds to an access of a track. A determination is made as to whether the track corresponds to data stored in a solid state disk. Record staging to a cache from the solid state disk is performed, in response to determining that the track corresponds to data stored in the solid state disk, wherein each track is comprised of a plurality of records. | 02-25-2016 |
20160055098 | COMPUTER SYSTEM WITH MEMORY AGING FOR HIGH PERFORMANCE - A memory manager in a computer system that ages memory for high performance. The efficiency of operation of the computer system can be improved by dynamically setting an aging schedule based on a predicted time for trimming pages from a working set. An aging schedule that generates aging information that better discriminates among pages in a working set based on activity level enables selection of pages to trim that are less likely to be accessed following trimming. As a result of being able to identify and trim less active pages, inefficiencies arising from restoring trimmed pages to the working set are avoided. | 02-25-2016 |
20160062656 | Command Set Extension for Non-Volatile Memory - A method and apparatus are provided for generating an adjusted internal electrical parameter for accessing a NAND Flash memory array based on an adjustment control parameter conveyed by a memory access instruction, where the memory access instruction is compliant with an Open NAND Flash Interface (ONFI) protocol to include a two command cycle sequence to specify a command for accessing the NAND Flash memory with the adjusted internal electrical parameter. | 03-03-2016 |
20160062657 | DYNAMIC HOST COMMAND REJECTION - A data storage device includes a non-volatile memory and host interface circuitry. The host interface circuitry is configured, in response to receiving a first command from a host device, to access a table to determine whether to reject the first command based on an operating state of the data storage device. The data storage device also includes a processor coupled to the non-volatile memory and to the host interface circuitry. The processor is configured to program the table. | 03-03-2016 |
20160062660 | MEMORY MANAGEMENT DEVICE - A memory management device of an example of the invention controls writing into and reading from a main memory including a nonvolatile semiconductor memory and a volatile semiconductor memory in response to a writing request and a reading request from a processor. The memory management device includes a coloring information storage unit that stores coloring information generated based on a data characteristic of write target data to be written into at least one of the nonvolatile semiconductor memory and the volatile semiconductor memory, and a writing management unit that references the coloring information to determines a region into which the write target data is written from the nonvolatile semiconductor memory and the volatile semiconductor memory. | 03-03-2016 |
20160062662 | Host System and Process to Reduce Declared Capacity of a Storage Device by Trimming - Systems, methods, and/or devices are used to reduce declared capacity of non-volatile memory of a storage device in a storage system. In one aspect, the method includes, detecting an amelioration trigger for reducing declared capacity of non-volatile memory of the storage device of the storage system, and in accordance with the detected amelioration trigger, performing an amelioration process to reduce declared capacity of the non-volatile memory of the storage device, the performing including: trimming at least a portion of a set of logical addresses in a logical address space; and reducing declared capacity of the non-volatile memory of the storage device. In some embodiments, the storage device includes one or more flash memory devices. In some embodiments, the method is performed by a host to which a storage device of the storage system is operatively coupled. | 03-03-2016 |
20160062663 | Process and Apparatus to Reduce Declared Capacity of a Storage Device by Altering an Encoding Format - Systems, methods and/or devices are used to reduce declared capacity of non-volatile memory of a storage device in a storage system. In one aspect, the method includes, detecting an amelioration trigger for reducing declared capacity of non-volatile memory of a storage device of the storage system, and in accordance with the detected amelioration trigger, performing an amelioration process to reduce declared capacity of the non-volatile memory of the storage device, the performing including: altering an encoding format of at least a portion of the non-volatile memory of the storage device, and reducing declared capacity of the non-volatile memory of the storage device. In some embodiments, the storage device includes one or more flash memory devices. In some embodiments, the detecting, the performing, or both are performed by the storage device, or by one or more subsystems of the storage system distinct from the storage device, or by the host. | 03-03-2016 |
20160062664 | Triggering, at a Host System, a Process to Reduce Declared Capacity of a Storage Device - Systems, methods and/or devices are used to enable triggering, at a host system, a process to reduce declared capacity of a storage device. In one aspect, the method includes, at a host to which a storage device of the storage system is operatively coupled: (1) obtaining one or more metrics of the storage device, the storage device including non-volatile memory, (2) detecting a trigger condition in accordance with the one or more metrics of the storage device, and (3) enabling an amelioration process associated with the detected trigger condition, the amelioration process to reduce declared capacity of the non-volatile memory of the storage device. In some embodiments, the storage device includes one or more flash memory devices. | 03-03-2016 |
20160062665 | Triggering a Process to Reduce Declared Capacity of a Storage Device in a Multi-Storage-Device Storage System - Systems, methods and/or devices are used to enable triggering a process to reduce declared capacity of a storage device in a multi-storage-device storage system. In one aspect, the method includes: (1) obtaining, for each storage device of a plurality of storage devices of the storage system, one or more metrics of the storage device, the storage device including non-volatile memory, (2) detecting a trigger condition for reducing declared capacity of the non-volatile memory of a respective storage device of the plurality of storage devices, the trigger condition detected in accordance with the one or more metrics of one or more storage devices, and (3) enabling an amelioration process associated with the detected trigger condition, the amelioration process to reduce declared capacity of the non-volatile memory of the respective storage device. In some embodiments, the respective storage device includes one or more flash memory devices. | 03-03-2016 |
20160062666 | Process and Apparatus to Reduce Declared Capacity of a Storage Device by Making Specific Logical Addresses Unavailable - Systems, methods and/or devices are used to reduce declared capacity of non-volatile memory of a storage device in a storage system. In one aspect, the method includes, detecting an amelioration trigger for reducing declared capacity of non-volatile memory of a storage device of the storage system, and in accordance with the detected amelioration trigger, performing an amelioration process to reduce declared capacity of the non-volatile memory of the storage device, the performing including making specific logical addresses of a logical address space unavailable to a host. In some embodiments, the storage device includes one or more flash memory devices. In some embodiments, the detecting, the performing, or both are performed by the storage device, or by one or more subsystems of the storage system distinct from the storage device, or by the host. | 03-03-2016 |
20160062667 | Process and Apparatus to Reduce Declared Capacity of a Storage Device by Reducing a Count of Logical Addresses - Systems, methods and/or devices are used to reduce declared capacity of non-volatile memory of a storage device in a storage system. In one aspect, the method includes, detecting an amelioration trigger for reducing declared capacity of non-volatile memory of a storage device of the storage system, and in accordance with the detected amelioration trigger, performing an amelioration process to reduce declared capacity of the non-volatile memory of the storage device, the performing including reducing a count of logical addresses of a logical address space available to a host. In some embodiments, the storage device includes one or more flash memory devices. In some embodiments, the detecting, the performing, or both are performed by the storage device, or by one or more subsystems of the storage system distinct from the storage device, or by the host. | 03-03-2016 |
20160062669 | LATENCY COMMAND PROCESSING FOR SOLID STATE DRIVE INTERFACE PROTOCOL - The present disclosure relates to methods, apparatuses, systems, and computer program products for processing commands for accessing solid state drives. Example methods can include receiving, from a host, a loaded command availability message. The loaded command availability message can indicate that a command associated with the loaded command availability message uses a low latency mode. The methods can further include executing the associated command. | 03-03-2016 |
20160062675 | MEMORY SYSTEM - A memory system includes a volatile first storing unit, a nonvolatile second storing unit in which data is managed in a predetermined unit, and a controller that writes data requested by a host apparatus in the second storing unit via the first storing unit and reads out data requested by the host apparatus from the second storing unit to the first storing unit and transfers the data to the host apparatus. The controller includes a management table for managing the number of failure areas in a predetermined unit that occur in the second storing unit and switches, according to the number of failure areas, an operation mode in writing data in the second storing unit from the host apparatus. | 03-03-2016 |
20160062676 | THERMALLY SENSITIVE WEAR LEVELING FOR A FLASH MEMORY DEVICE THAT INCLUDES A PLURALITY OF FLASH MEMORY MODULES - Thermally sensitive wear leveling for a flash memory device that includes a plurality of flash memory modules, the flash memory device included in a computing system that includes a plurality of additional computing components, including: identifying a thermal sensitivity coefficient for each flash memory module in dependence upon a physical topology of the flash memory device and one or more of the additional computing components; identifying wear leveling information for each flash memory module; receiving a request to write data to the flash memory device; selecting, in dependence upon the thermal sensitivity coefficient for each flash memory module and the wear leveling information for each flash memory module, a target flash memory module for servicing the request to write data to the flash memory device; and writing the data to the target flash memory module. | 03-03-2016 |
20160062677 | Process and Apparatus to Reduce Declared Capacity of a Storage Device by Trimming - Systems, methods, and/or devices are used to reduce declared capacity of non-volatile memory of a storage device in a storage system. In one aspect, the method includes, detecting an amelioration trigger for reducing declared capacity of non-volatile memory of the storage device of the storage system, and in accordance with the detected amelioration trigger, performing an amelioration process to reduce declared capacity of the non-volatile memory of the storage device, the performing including: trimming, in accordance with a trim command received from a host, at least a portion of a set of logical addresses in a logical address space; and reducing declared capacity of the non-volatile memory of the storage device. In some embodiments, the storage device includes one or more flash memory devices. In some embodiments, the method is performed by the storage device. | 03-03-2016 |
20160062678 | Process and Apparatus to Reduce Declared Capacity of a Storage Device by Deleting Data - Systems, methods and/or devices are used to reduce declared capacity of non-volatile memory of a storage device in a storage system. In one aspect, the method includes, detecting an amelioration trigger for reducing declared capacity of non-volatile memory of a storage device of the storage system, and in accordance with the detected amelioration trigger, performing an amelioration process to reduce declared capacity of the non-volatile memory of the storage device, the performing including: deleting from the storage device discardable data that is used by a host, and reducing declared capacity of the non-volatile memory of the storage device. In some embodiments, the storage device includes one or more flash memory devices. In some embodiments, the detecting, the performing, or both are performed by the storage device, or by one or more subsystems of the storage system distinct from the storage device, or by the host. | 03-03-2016 |
20160062679 | Process and Apparatus to Reduce Declared Capacity of a Storage Device by Moving Data - Systems, methods and/or devices are used to reduce declared capacity of non-volatile memory of a storage device in a storage system. In one aspect, the method includes, detecting an amelioration trigger for reducing declared capacity of non-volatile memory of a storage device, and in accordance with the detected amelioration trigger, performing an amelioration process to reduce declared capacity of the non-volatile memory of the storage device, the performing including: moving a portion of data used by a host from the storage device to another storage device of the storage system, and reducing declared capacity of the non-volatile memory of the storage device. In some embodiments, the storage device includes one or more flash memory devices. In some embodiments, the detecting, the performing, or both are performed by the storage device, or by one or more subsystems of the storage system distinct from the storage device, or by the host. | 03-03-2016 |
20160062680 | Triggering a Process to Reduce Declared Capacity of a Storage Device - Systems, methods and/or devices are used to enable triggering a process to reduce declared capacity of a storage device. In one aspect, the method includes, at a storage device of a storage system: (1) generating one or more metrics of the storage device, the storage device including non-volatile memory, (2) detecting a trigger condition in accordance with the one or more metrics of the storage device, and (3) enabling an amelioration process associated with the detected trigger condition, the amelioration process to reduce declared capacity of the non-volatile memory of the storage device. In some embodiments, the storage device includes one or more flash memory devices. | 03-03-2016 |
20160062681 | Process and Apparatus to Reduce Declared Capacity of a Storage Device by Reducing a Range of Logical Addresses - Systems, methods and/or devices are used to reduce declared capacity of non-volatile memory of a storage device in a storage system. In one aspect, the method includes, detecting an amelioration trigger for reducing declared capacity of non-volatile memory of a storage device of the storage system, and in accordance with the detected amelioration trigger, performing an amelioration process to reduce declared capacity of the non-volatile memory of the storage device, the performing including reducing a range of logical addresses of a logical address space available to a host. In some embodiments, the storage device includes one or more flash memory devices. In some embodiments, the detecting, the performing, or both are performed by the storage device, or by one or more subsystems of the storage system distinct from the storage device, or by the host. | 03-03-2016 |
20160062683 | SUB-SECTOR WEAR LEVELING IN MEMORIES - Methods of wear leveling in a memory, and memories configured to perform such methods, are useful in extending cycling endurance in memories. Such methods include transferring data from a first block of the memory to a second block of the memory, erasing the first block, transferring data from a third block of the memory to the first block, erasing the third block, transferring data from the second block to the third block, swapping logical addresses for the first block and the third block with each other, and erasing the second block. Transferring data from the third block to the first block excludes a sub-sector of the third block that is to be erased. | 03-03-2016 |
20160062684 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR INCREASING SPARE SPACE IN MEMORY TO EXTEND A LIFETIME OF THE MEMORY - A method including increasing spare space in a storage subsystem including a flash memory, wherein the storage subsystem includes compressed data stored in the flash memory; extending a lifetime of the storage subsystem to achieve a stored selected minimum lifetime, based at least in part as a result of the increasing spare space; identifying at least one aspect associated with the lifetime of the storage subsystem; and delaying, based at least upon one identified aspect, at least one operation that reduces the lifetime of the storage subsystem, wherein the delaying at least one operation includes delaying a command that initiates the at least one operation. | 03-03-2016 |
20160062686 | SEMICONDUCTOR DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor device and a method of operating the same are provided. A plurality of memory blocks are erased. It is determined whether a selected memory block among the memory blocks is a lastly erased memory block. The selected memory block or another memory block is programmed according to a result of determination. | 03-03-2016 |
20160062688 | FLASH MEMORY DEVICE, FLASH MEMORY SYSTEM, AND OPERATING METHOD - A flash memory device includes: a memory unit that includes a cell area that has one or more memory blocks each including a plurality of pages; a page buffer that includes a valid data area storing valid data to be programmed to the pages and a pad area storing non-valid data to be programmed to the pages, in response to an external data program command for the one or more pages; and a control logic that retains the non-valid data stored in the pad area and stores the valid data in the valid data area, in response to the data program command. | 03-03-2016 |
20160062690 | DATA STORAGE DEVICE, DATA PROCESSING SYSTEM INCLUDING THE SAME, AND OPERATING METHOD THEREOF - A data processing system includes a host device including a first memory, and a data storage device including a second memory and a third memory, and suitable for storing data to be accessed by the host device, wherein the host device requests the data storage device to upload data stored in the second memory. | 03-03-2016 |
20160062693 | Notification of Trigger Condition to Reduce Declared Capacity of a Storage Device - Systems, methods and/or devices are used to enable notification of a trigger condition to reduce declared capacity of a storage device. In one aspect, the method includes, at a storage device of a storage system, the storage device including non-volatile memory: (1) detecting a trigger condition for reducing declared capacity of the non-volatile memory of the storage device, and (2) notifying a host to which the storage device is operatively coupled of the trigger condition for reducing declared capacity of the non-volatile memory of the storage device, the trigger condition for enabling performance of an amelioration process to reduce declared capacity of the non-volatile memory of the storage device. In some embodiments, the storage device includes one or more flash memory devices. | 03-03-2016 |
20160062695 | NON-VOLATILE MEMORY WITH LPDRAM - Low power DRAM (LPDRAM) memory devices for communication with a non-volatile memory coupled to the LPDRAM memory device, and systems containing such LPDRAM and non-volatile memory facilitate configuring the LPDRAM memory device using routines stored on the non-volatile memory. | 03-03-2016 |
20160062699 | Notification of Trigger Condition to Reduce Declared Capacity of a Storage Device in a Multi-Storage-Device Storage System - Systems, methods and/or devices are used to enable notification of a trigger condition to reduce declared capacity of a storage device in a multi-storage-device storage system. In one aspect, the method includes: (1) obtaining, for each storage device of a plurality of storage devices, one or more metrics of the storage device, the storage device including non-volatile memory, (2) detecting a trigger condition for reducing declared capacity of the non-volatile memory of a respective storage device of the plurality of storage devices, the trigger condition detected in accordance with the one or more metrics of two or more of the storage devices, and (3) notifying a host of the trigger condition for reducing declared capacity of the non-volatile memory of the respective storage device, the trigger condition for enabling performance of an amelioration process to reduce declared capacity of the non-volatile memory of the respective storage device. | 03-03-2016 |
20160062702 | TUNING OVERPROVISIONING BASED ON THE USED BLOCK COUNT - Software that performs the following steps: (i) collecting a set of sampling value(s), where each sampling value of the set of sampling value(s) respectively corresponds to an amount of overprovisioning-related data stored in a non-volatile memory device (NVMD) at the time the corresponding sampling value is collected; and (ii) determining an overprovisioning ratio for use with the NVMD based, at least in part, on the set of sampling value(s). The overprovisioning-related data is any data stored in overprovisioning space as a result of overprovisioning-type operations. | 03-03-2016 |
20160062762 | SELF-CONTAINED STORAGE DEVICE FOR SELF-CONTAINED APPLICATION EXECUTION - A storage device that is pre-configured to execute one or more related applications when connected to a computer device or system. The storage device may contain a suite of applications that are pre-configured to execute without requiring “installation” on the computer device or system prior to execution. The storage device may be a secure (e.g., protected) storage drive for use with the associated computer device or system. The secure storage drive allows access only when properly authenticated to the computer device or system attempting to access the secure storage drive. Additionally, other levels of authentication may be required prior to allowing access. For example, access may only be allowed if both the computer device or system and a user authenticated to the computer device are recognized by the secure storage drive. | 03-03-2016 |
20160062881 | METABLOCK RELINKING SCHEME IN ADAPTIVE WEAR LEVELING - Systems and methods for metablock relinking may be provided. A first physical block of a first metablock may be determined to have a different health than a second physical block of a second metablock based on health indicators of the first and second physical blocks. Each of the health indicators may indicate an extent to which a respective one of the first and second physical blocks may be written to and/or erased before the respective one of the first and second physical blocks becomes defective. The first physical block of the first metablock may be replaced with the second physical block of the second metablock based on a determination that the health of the first physical block of the first metablock is different than the health of the second physical block of the second metablock. | 03-03-2016 |
20160062882 | METHOD AND SYSTEM FOR GARBAGE COLLECTION IN A STORAGE SYSTEM BASED ON LONGEVITY OF STORED DATA - A method for managing data. The method includes receiving a first request to write data to persistent storage and in response to the first request, writing the data to a short-lived block in the persistent storage, where the data is short-lived data or data of unknown longevity. The method further includes performing a modified garbage collection operation that includes: selecting a first frag page in a first block, determining that the first frag page is live, and migrating, based on the determination that the first frag page is live, the first frag page to a long-lived block in the persistent storage, where the long-lived block is distinct from the short-lived block and wherein the long-lived block does not include any short-lived data. | 03-03-2016 |
20160062883 | DATA STORAGE DEVICE AND OPERATING METHOD THEREOF - A data storage device may include: a nonvolatile memory device; and a controller suitable for generating a mapping table based on one or more of write logical addresses for access to the nonvolatile memory device. The mapping table may include information of: correspondence between a physical address for access to the nonvolatile memory device and one of the write logical addresses; and a number of successive physical addresses corresponding to successive logical addresses starting from the write logical addresses corresponding to the correspondence information. | 03-03-2016 |
20160062884 | DATA STORAGE DEVICE AND METHOD FOR OPERATING THE SAME - An operating method of a data storage device includes receiving a write request, determining whether it is possible to perform a first write operation of simultaneously writing a plurality of bits in each of memory cells coupled to one word line of a nonvolatile memory apparatus, and performing a garbage collection operation for the nonvolatile memory apparatus, according to a determination result, and generating first merged data. | 03-03-2016 |
20160062885 | GARBAGE COLLECTION METHOD FOR NONVOLATILE MEMORY DEVICE - A garbage collection method for a nonvolatile memory includes performing an urgent garbage collection operation by coping at least one page of a first logical area to a free block of a second logical area and remapping a page of the second logical area to the first logical area in response to a remapping command received from a host. | 03-03-2016 |
20160062898 | Method for dynamically adjusting a cache buffer of a solid state drive - A method for dynamically adjusting a cache buffer of a solid state drive includes receiving data, determine if the data are continuous according to logical allocation addresses of the data, increasing a memory size of the cache buffer, searching the cache buffer for same data as at least one portion of the data, modifying and merging of the at least one portion of the data with the same data already temporarily stored in the cache buffer, temporarily storing the data in the cache buffer. | 03-03-2016 |
20160062908 | Methods for Maintaining a Storage Mapping Table and Apparatuses using the Same - A method for maintaining a storage mapping table. An access interface is directed to read a group mapping table from the last page of a block of a storage unit. The block is allocated to store data of a plurality of groups, each group stores information indicating which location in the storage unit stores data of an LBA (Logical Block Address) range, and the group mapping table stores information indicating which unit of the block stores the latest data of each group. The group mapping table is stored in a DRAM (Dynamic Random Access Memory). The access interface is directed to read data of each group from the storage unit according to the group mapping table. The data of each group is stored in a specified location of a storage mapping table of the DRAM. | 03-03-2016 |
20160062922 | MEMORY SYSTEM CAPABLE OF WIRELESS COMMUNICATION AND METHOD OF CONTROLLING MEMORY SYSTEM - According to one embodiment, a memory controller allows access to a first non-volatile memory from a host device when a wireless communication unit is communicable or communicating with any one of wireless communication devices, and denies access to the first non-volatile memory from the host device when the wireless communication unit is not communicable or communicating with any one of the wireless communication devices. The memory controller does not allow the host device to access information in the first non-volatile memory after the access field specification information is updated. | 03-03-2016 |
20160064053 | SEMICONDUCTOR DEVICE AND INFORMATION PROCESSING DEVICE - A semiconductor device has a plurality of units, each of which includes a first memory cell that stores a value indicating a state of one node of an interaction model, a second memory cell that stores an interaction coefficient indicating an interaction from a node connected to the one node, and a third memory cell that stores a bias coefficient of the one node. Furthermore, the semiconductor device has a computing circuit that determines a value indicating a next state of the one node based on a value indicating a state of the connected node, the interaction coefficient and the bias coefficient. Also, each of the second memory cell and the third memory cell in the plurality of units includes multi-valued memory cells. | 03-03-2016 |
20160070336 | MEMORY SYSTEM AND CONTROLLER - In a memory system in an embodiment, in a case of normal operation, a control unit returns a write completion response upon completion of reception of write data from a host, and writes the write data into nonvolatile memory in a multiple values. In a case of unordinary power-off, changeover to operation using a backup battery is conducted and the control unit writes dirty data that is not completed in writing into the nonvolatile memory, into the nonvolatile memory with two values. When next boot, the control unit reads the dirty data from the nonvolatile memory into the volatile memory, and thereafter writes the dirty data into the nonvolatile memory in a multiple values. | 03-10-2016 |
20160070470 | MEMORY DEVICE AND MEMORY CONTROLLER - According to one embodiment, a memory device includes a nonvolatile first memory, a second memory, a controller, and an interface unit. When receiving a first packet from the interface unit, the controller transmits a second packet to an initiator via the interface unit. In the case where a header of a third packet does not match the second packet, the controller does not store the third packet to a second memory, the third packet being discarded. | 03-10-2016 |
20160070471 | MEMORY SYSTEM - According to one embodiment, a memory system includes a memory and a memory controller. The memory includes a first buffer and a memory cell array. The memory controller includes a second buffer for receiving first data from a host. The memory controller transfers the first data to the first buffer without accumulating a predetermined size of the first data in the second buffer. The memory controller creates second data in the first buffer and programs the second data created in the first buffer into the memory cell array. The second data is formed of a plurality of third data. The third data is first data received from the memory controller by the memory. The size of the second data is equal to a size of a unit in which to program into the memory cell array. | 03-10-2016 |
20160070472 | MEMORY SYSTEM - According to one embodiment, a memory system comprises a non-volatile semiconductor memory, a memory and a controller. The memory stores a management table including a plurality of parameters for managing the non-volatile semiconductor memory. The controller is configured to control the operation of the non-volatile semiconductor memory based on a first value of the parameters contained in the management table. The controller obtains a second value corresponding to the parameters from an operation log of the non-volatile semiconductor memory, compares the second value of the parameters with the first value, calculates the difference between the second value of the parameters and the first value when they are different from each other, calculates a correction value for correcting the first value when the difference is greater than a third value, and updates the first value of the management table based on the correction value. | 03-10-2016 |
20160070474 | Data-Retention Controller/Driver for Stand-Alone or Hosted Card Reader, Solid-State-Drive (SSD), or Super-Enhanced-Endurance SSD (SEED) - A Green NAND SSD Driver (GNSD) driver executes on a host to increase data-retention of flash memory attached to a Super Enhanced Endurance Device (SEED) or Solid-State Drive (SSD). Host accesses to flash are intercepted by the GNSD driver using upper and lower-level filter drivers. A retention-check timer causes a retention routine to be periodically executed. The routine sends high-level commands to the SEED that causes the SEED to refresh either all data or just data blocks with older write dates. Data is refreshed by moving to a new physical block. The retention routine can track write dates of logical blocks and command a SSD to move logical blocks with older write dates. A retention card has a controller that performs the retention routine when not connected to a host, while a SEED power card allows the SEED to refresh data when no host is attached to the SEED. | 03-10-2016 |
20160070476 | OPERATION MANAGEMENT IN A MEMORY DEVICE - Methods of operating a memory device include performing a first memory operation having an associated timing requirement; after completing the first memory operation, determining whether a timing margin between completion of the first memory operation and expiration of its associated timing requirement exceeds a length of time to perform a particular portion of a second memory operation; and performing the particular portion of the second memory operation between completion of the first memory operation and the expiration of its associated timing requirement if it is determined that the timing margin between completion of the first memory operation and expiration of its associated timing requirement exceeds the length of time to perform the particular portion of the second memory operation. | 03-10-2016 |
20160070477 | MEMORY SYSTEM - According to one embodiment, upon reception of a command and an archive file for updating first firmware, a controller selects first information corresponding to information for identifying the memory system from a plurality of first information included in the header. The controller acquires second information included in the selected first information, and acquires one of a plurality of second firmware included in the archive file based on the acquired second information, to update the first firmware by the acquired second firmware. | 03-10-2016 |
20160070486 | DEBUG DATA SAVING IN HOST MEMORY ON PCIE SOLID STATE DRIVE - A method, apparatus, and system are provided for implementing debug data saving in host memory on a Peripheral Component Interconnect Express (PCIE) solid state drive (SSD). Upon Power Loss Interruption (PLI) event detected in a solid state drive (SSD), the SSD transfers debug data directly to the host system main (DRAM) memory via a Peripheral Component Interconnect Express (PCIE) bus. | 03-10-2016 |
20160070488 | MULTI-STAGE PROGRAMMING AT A STORAGE DEVICE USING MULTIPLE INSTRUCTIONS FROM A HOST - A method performed by a data storage device includes receiving, from a host device, a first instruction of a first set of instructions to write a first group of pages of data to a memory of the data storage device and receiving a second instruction of the first set of instructions to write the first group of pages of data. A first stage of a multi-stage programming operation is performed at a first physical address of the memory using a first copy of the first group of pages, and a second stage of the multi-stage programming operation is performed at the first physical address of the memory using a second copy of the first group of pages. The first copy and the second copy are received from the host device in association with the first instruction and the second instruction, respectively. | 03-10-2016 |
20160070489 | MEMORY SYSTEM - According to one embodiment, a memory system includes a plurality of memories, a plurality of first processing units, and a second processing unit. The plurality of first processing units are respectively connected to one of the memories. The second processing unit sequentially distributes a plurality of first data inputted externally sequentially to the plurality of first processing units. Each of the first processing units outputs first data distributed thereto to the one of the memories. The second processing unit, until finishing transmission of a second data to one of the first processing units, keeps the others of the first processing units standing by outputting already-distributed first data. The second data is a last data from among the plurality of first data inputted externally. | 03-10-2016 |
20160070493 | DATA STORAGE DEVICE AND METHOD OF OPERATING THE SAME - A data storage device includes a memory including a first region that stores an application executed by a host, a second region that stores user data, and a meta region, as well as a storage controller configured to control an operation of the memory. The storage controller transmits first data including the application stored in the first region to the host in response to a first request received from the host after being connected with the host, stores product registration information transmitted from the host in the meta region, resets a connection between the data storage device and the host in response to a connection reset command received from the host, and transmits second data stored in the second region to the host in response to a second request received from the host after the connection is reset. | 03-10-2016 |
20160070496 | Scalable Data Structures for Control and Management of Non-Volatile Storage - Method and apparatus for managing data in a Non-Volatile Memory (NVD). In some embodiments, management information is stored in a buffer memory using a Solid-State Disk (SSD) controller circuit, the management information comprising a map data structure that associates storage addresses of a host device to physical addresses of the NVD. A location in the management information is determined responsive to a selected host storage address and a programmable parameter by arithmetically dividing in accordance with a divisor specified at least in part by the programmable parameter. The location in the management information is used to direct a transfer of user data by the SSD control circuit between the host device and the NVM. | 03-10-2016 |
20160070500 | System, Method, and Computer Program Product for Detecting Access to a Memory Device - Discrete events that take place with respect to a hard disk drive or other I/O device or port are indicated to logic that implements Self-Monitoring Analysis and Reporting Technology (SMART) or similar technology. These events are communicated to SMART as event data. Examples of such discrete events include power on, power off, spindle start, and spindle stop, positioning of the actuator, and the time at which such events occur. SMART then compiles event data to create compiled activity data. Compiled activity data represents summary statistical information that is created by considering some or all of the event data. Examples of compiled activity data include the Time Powered On and Power Cycle Count. Collection logic then writes the compiled activity data to a memory medium. An analyst can then read data from log file(s). | 03-10-2016 |
20160070502 | MEMORY SYSTEM - According to one embodiment, there is provided a memory system including a non-volatile memory, a controller, a first interface circuit, a first signal line, and a second signal line. The controller is configured to control the non-volatile memory. The first interface circuit is configured to perform level conversion between a first power source level and a second power source level which is lower than the first power source level. The second power source level is used as a driving voltage of the controller. The first signal line is configured to connect to the first interface circuit. The second signal line is configured to connect the first interface circuit and a signal terminal of the controller. A potential of the second signal line is able to be pulled up to the second power source level. | 03-10-2016 |
20160070503 | MEMORY SYSTEM - According to one embodiment, a memory system includes a nonvolatile memory, a buffer memory, a power management unit, and a controller. The buffer memory is divided into a plurality of first subbuffers. The power management unit acquires a power consumption value. The power management unit starts and stops power supply to the first subbuffers with respect to each first subbuffer, based on the acquired power consumption value. The controller selects a second subbuffer from one or more third subbuffers being supplied with power. The controller buffers transfer data between the outside and the nonvolatile memory in the second subbuffer. | 03-10-2016 |
20160070643 | SYSTEM AND METHOD OF COUNTING PROGRAM/ERASE CYCLES - A method includes, in a data storage device that includes a memory, detecting an operation associated with a block of the memory. The operation is associated with a program/erase cycle. The method further includes, responsive to detecting the operation, performing a comparison between a random number and at least one value of a set of values. The method includes selectively adjusting a value of a counter associated with the block based on the comparison. | 03-10-2016 |
20160070647 | MEMORY SYSTEM - According to one embodiment, a memory system includes a non-volatile memory, a read control unit, a read-ahead unit, a buffer memory, and a resource management unit. The read control unit is configured to perform a sequential read of two threads from the non-volatile memory. The read-ahead unit is configured to perform read-ahead to the non-volatile memory for each thread. The buffer memory is configured to include two read-ahead buffers. The respective read-ahead buffers hold data which is read-ahead from the non-volatile memory. The data held by the respective read-ahead buffers belong to threads different from each other. The resource management unit is configured to obtain a peak request amount from outside for each thread and adjust a size of each read-ahead buffer based on the obtained peak request amount for each thread. | 03-10-2016 |
20160070934 | MEMORY CONTROLLER - A memory controller used to verify authenticity of data stored in a first memory unit. The memory controller includes a secure memory unit which stores a pre-stored value representative of the authenticity of the data to be written in the first memory unit. A processing system calculates a value which is representative of the data in the first memory unit after a write cycle. The calculation of the calculated value is triggered by the write cycle. The calculated value is compared with the pre-stored value in order to verify whether the data stored in the first memory unit after the write cycle has been altered in accordance with the authenticity. By comparing the calculated value with the pre-stored value authenticity of the data stored in the first memory unit after the write cycle is verified, thus preventing the memory controller from operating in case the data written to the first memory unit is not authentic. | 03-10-2016 |
20160077737 | INFORMATION PROCESSING APPARATUS AND MEMORY SYSTEM - According to one embodiment, an information processing apparatus includes a host and a memory system. The host includes a main memory. The memory system includes a memory access unit and an interface unit. The memory access unit converts a first request into transmission information. The first request is a request for data transfer toward a memory region as a part of the main memory. The interface unit transmits transmission information according to an instruction from the memory access unit. | 03-17-2016 |
20160077739 | SYSTEM AND METHOD FOR SUPPORTING A LOW CONTENTION QUEUE IN A DISTRIBUTED DATA GRID - A system and method which supports a low contention queue in a multithreaded processing environment such as a distributed data grid. The queue is optimized to reduce memory contention and queue processing overhead, and is lock-free. The queue includes a doubly-linked list of nodes, wherein each node is associated with a value, a reference to a next node and a reference to a previous node. Furthermore, the queue allows one or more consumer threads to access the queue via a reference to a last removed node from the doubly linked list, and allows one or more producer threads to insert a new node via a reference to a tail node in the doubly-linked list. The low queue efficiently serves large number of threads with reduced contention, overhead, and latency, thereby improving performance in a multithreaded processing environment such as a distributed data grid. | 03-17-2016 |
20160077740 | SYSTEMS AND METHODS FOR ENABLING LOCAL CACHING FOR REMOTE STORAGE DEVICES OVER A NETWORK VIA NVME CONTROLLER - A new approach is proposed that contemplates systems and methods to support mapping/importing remote storage devices as NVMe namespace(s) via an NVMe controller using a storage network protocol and utilizing one or more storage devices locally coupled to the NVMe controller as caches for fast access to the mapped remote storage devices. The NVMe controller exports and presents the NVMe namespace(s) of the remote storage devices to one or more VMs running on a host attached to the NVMe controller. Each of the VMs running on the host can then perform read/write operations on the logical volumes. During a write operation, data to be written to the remote storage devices by the VMs is stored in the locally coupled storage devices first before being transmitted over the network. The locally coupled storage devices may also cache data intelligently pre-fetched from the remote storage devices based on reading patterns and/or pre-configured policies of the VMs in anticipation of read operations. | 03-17-2016 |
20160077744 | DEFERRED REFERENCE COUNT UPDATE TECHNIQUE FOR LOW OVERHEAD VOLUME METADATA - A deferred refcount update technique efficiently frees storage space for metadata (associated with data) to be deleted during a merge operation managed by a volume layer of a node. The metadata is illustratively volume metadata embodied as mappings from logical block addresses (LBAs) of a logical unit (LUN) to extent keys maintained by an extent store layer of the node. One or more requests to delete (or overwrite) an LBA range within a LUN may be captured as page keys associated with metadata pages during the merge operation and the storage space associated with those metadata pages may be freed in an out-of-band fashion. The page keys of the metadata pages may be persistently recorded in a reference count (refcount) log to thereby allow the merge operation to complete without resolving deletion of the keys. A batch of page keys may be organized as one or more delete requests and, once the merge completes, the keys may be inserted into the refcount log. Subsequently, a deferred reference count update process may be spawned (instantiated) to walk through the page keys stored in the refcount log and delete each key, e.g., from the extent store layer, independently and out-of-band from the merge operation. | 03-17-2016 |
20160077749 | Adaptive Block Allocation in Nonvolatile Memory - In a multi-plane non-volatile memory, good blocks of different planes are linked for parallel operation for storing long host writes. Where bad blocks in one or more planes result in unlinked blocks, the unlinked blocks are configured for individual operation to store short host writes and/or memory system management data. Unlinked blocks may be configured as Single Level Cell (SLC) blocks while linked blocks may be configured as SLC blocks or Multi Level Cell (MLC) blocks. | 03-17-2016 |
20160077753 | DETERMINING BIAS INFORMATION FOR OFFSETTING OPERATING VARIATIONS IN MEMORY CELLS - Disclosed is an apparatus and method for determining memory cell bias information for use in memory operations. One or more memory die are selected from a group of memory die, and one or more memory blocks selected from the selected one or more memory die. A group of cells within the selected memory blocks are programmed and cycled. Bias values are generated based on comparing one or more program levels associated with respective wordlines with predetermined programming levels. The bias values are stored lookup table that is configured to be accessible at runtime by a memory controller for retrieval of the bias value during a memory operation. | 03-17-2016 |
20160077762 | MEMORY SYSTEM, STORAGE SYSTEM - According to one embodiment, a memory system includes a plurality of nonvolatile memories, a generator which generates a select information, an issuing unit which issues a select command including the select information, a decoder which decodes the select information and the select command, and a selector which selects one of the plurality of nonvolatile memories on the basis of the decoding result from the decoder. | 03-17-2016 |
20160077765 | DATA STORAGE BASED ON RANK MODULATION IN SINGLE-LEVEL FLASH MEMORY - Technologies are generally described to store data in single-level memory using rank modulation. In some examples, data to be encoded to single-level memory may be represented with a bit ranking for a group of bits. A program vector may then be determined from the bit ranking and partial program characteristics associated with the memory group(s). The memory group(s) may then be programmed according to the program vector. The encoded data may be subsequently retrieved by performing a series of partial programming operations on the memory group(s) to recover the bit ranking and derive the data represented. | 03-17-2016 |
20160077958 | INITIATING OPERATION OF A TIMING DEVICE USING A READ ONLY MEMORY (ROM) OR A ONE TIME PROGRAMMABLE NON VOLATILE MEMORY (OTP NVM) - The present invention provides a method and a programmable timing device that includes a timing device circuit for generating at least one timing signal, a static random access memory (SRAM) coupled to the timing device circuit, a read only memory (ROM) having a first timing device configuration stored therein, a one time programmable non volatile memory (OTP NVM) for storing a second timing device configuration and selection logic. The selection logic includes an output coupled to the SRAM, a first input coupled to the ROM and a second input coupled to the OTP NVM. The selection logic is operable to receive input indicating whether SRAM is to be loaded from the ROM or the OTP NVM, and operable to load either the first timing device configuration from the ROM or the second timing device configuration from the OTP NVM based on the input. | 03-17-2016 |
20160077960 | ADAPTIVE COMPRESSION DATA STORING METHOD FOR NON-VOLATILE MEMORIES AND SYSTEM USING THE SAME - An adaptive compression data storing method for non-volatile memories and a system using the method are disclosed. The system includes a host interface unit, a data compressor, a padding unit, a buffer, a combining unit, and a mapping table unit. By combining some compressed data in one page, the present invention can settle the problem that space for storing a compressed data that can not be utilized. Further, lifetime of non-volatile memories can be extended. | 03-17-2016 |
20160077961 | Storage Module and Method for Scheduling Memory Operations for Peak-Power Management and Balancing - A storage module and method for scheduling memory operations for peak-power management and balancing are provided. In one embodiment, a storage module maintains a count of time slots over a period of time. The period of time corresponds to an amount of time between periodic power peaks of a memory operation. For each time slot, the storage module determines whether to commence a memory operation on one or more of the plurality of memory dies based on whether a power peak generated in the time slot by the memory operation would exceed a power threshold allowed for the time slot. Other embodiments are provided. | 03-17-2016 |
20160077962 | HYBRID-HDD POLICY FOR WHAT HOST-R/W DATA GOES INTO NAND - In a cache policy for a hybrid drive having a magnetic storage device and a non-volatile solid-state device, the hybrid drive is configured to write the most recent version of data associated with a logical block address to the non-volatile solid-state device when the logical block address is associated with previously written data and is overlapped by a subsequent disk write operation. Advantageously, the most recent version of data associated with the overlapped logical block address is stored in cache in the non-volatile solid-state device, even when the subsequent disk write operation results in the overlapped logical block address being trimmed from cache or otherwise invalidated. Consequently, data associated with the overlapped logical block address can be accessed more quickly than data written to the magnetic storage device. | 03-17-2016 |
20160077963 | Apparatus and Method to Share Host System RAM with Mass Storage Memory RAM - A method includes, in one non-limiting embodiment, sending a request from a mass memory storage device to a host device, the request being one to allocate memory in the host device; writing data from the mass memory storage device to allocated memory of the host device; and subsequently reading the data from the allocated memory to the mass memory storage device. The memory may be embodied as flash memory, and the data may be related to a file system stored in the flash memory. The method enables the mass memory storage device to extend its internal volatile RAM to include RAM of the host device, enabling the internal RAM to be powered off while preserving data and context stored in the internal RAM. | 03-17-2016 |
20160077964 | STORAGE DEVICE AND GARBAGE COLLECTION METHOD OF DATA STORAGE SYSTEM HAVING THE STORAGE DEVICE - A garbage collection method of a data storage system having storage devices is provided. The method includes determining whether a garbage collection is needed in one of the storage devices, transferring a multicast garbage collection command from one of the storage devices to at least one other storage device in a write group through a multicast operation, and performing the garbage collection in one of the storage devices. | 03-17-2016 |
20160077971 | METHODS AND SYSTEMS FOR CACHING DATA IN A STORAGE SYSTEM BASED ON USER INPUT - A storage device includes a flash memory-based cache for a hard disk-based storage device and a controller that is configured to limit the rate of cache updates through a variety of mechanisms, including determinations that the data is not likely to be read back from the storage device within a time period that justifies its storage in the cache, compressing data prior to its storage in the cache, precluding storage of sequentially-accessed data in the cache, and/or throttling storage of data to the cache within predetermined write periods and/or according to user instruction. | 03-17-2016 |
20160079524 | ELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SAME - An electronic device includes a semiconductor memory that includes: a variable resistance element formed over a substrate; and a carbon-containing aluminum nitride layer formed on sidewalls and in an upper portion of the variable resistance element. | 03-17-2016 |
20160085445 | METHOD OPERATING RAID SYSTEM AND DATA STORAGE SYSTEMS USING WRITE COMMAND LOG - A method of operating a data storage device includes receiving a log start command from a controller, generating a log for write commands communicated from the controller in response to the log start command, storing the log in a memory, receiving a log read command from the controller, and communicating the log stored in the memory to the controller in response to the log read command. | 03-24-2016 |
20160085453 | RAIDed MEMORY SYSTEM MANAGEMENT - A memory system is described, where a plurality of memory modules is connected to a memory controller. Erase operations of the memory modules are coordinated by the memory controller such that, when data is stored in a group of memory modules configured to be a RAID (Redundant Array of Independent “Disks”) group, erase or refresh operations performed on the memory modules of the RAID group are synchronized, scheduled, or controlled to reduce the latency in reading the data stored on the RAID modules. | 03-24-2016 |
20160085455 | Nonvolatile Memory Adaptive to Host Boot Up Routine - A nonvolatile memory that stores boot data from a host learns which data is boot data by monitoring read commands received from a host during a powering up operation. Boot data is then arranged in a manner that makes subsequent reading of the boot data faster when it is accessed during a subsequent powering up operation. | 03-24-2016 |
20160085456 | DATA READ APPARATUS, DATA READ METHOD, AND STORAGE MEDIUM STORING DATA READ PROGRAM - A data read apparatus includes a nonvolatile memory comprising a plurality of blocks, each of the blocks including an area storing block information, in which a position of a next block is written, or storing the block information and file management information, and an area storing actual data; a volatile memory; a power-on circuit configured to turn on supply of power to the nonvolatile memory and the volatile memory; and a processor. The processor is configured to: read out the block information stored in each of the blocks of the nonvolatile memory, or the block information and the file management information, when the supply of power was turned on by the power-on circuit, and register the read-out block information, or the block information and the file management information, in the volatile memory as file position information. | 03-24-2016 |
20160085457 | WRITE REORDERING IN A HYBRID DISK DRIVE - A hybrid drive and associated methods increase the rate at which data are transferred to a nonvolatile storage medium in the hybrid drive. By using a large nonvolatile solid state memory device as cache memory for a magnetic disk drive, a very large number of write commands can be cached and subsequently reordered and executed in an efficient manner. In addition, strategic selection and reordering of only a portion of the write commands stored in the nonvolatile solid state memory device increases efficiency of the reordering process. | 03-24-2016 |
20160085465 | Validating the Status of Memory Operations - The various implementations described herein include systems, methods and/or devices used to validate the status of memory operations in a storage device. In one aspect, the method includes sending a first set of command instructions to a first device of the plurality of non-volatile memory devices, including: a memory operation command; a first status polling command to determine a status of the first device, and a second status polling command to determine a status of the first device. The first status polling command is sent after the memory operation command is sent, and the second status polling command is sent after receiving a response to the first status polling command that meets predefined completion criteria. The method further includes forgoing sending any subsequent set of command instructions to the first device until a response to the second status polling command that meets the predefined completion criteria is received. | 03-24-2016 |
20160085470 | EFFICIENT ERROR HANDLING MECHANISMS IN DATA STORAGE SYSTEMS - A data storage system configured to efficiently search and update system data is disclosed. In one embodiment, the data storage system can attempt to correct errors in retrieved data configured to index system data. Metadata stored along with user data in a memory location can be configured to indicate a logical address associated in a logical-to-physical location mapping with a physical address at which user data and metadata are stored. The data storage system can generate modified versions of logical address indicated by the metadata and determine whether such modified versions match the physical address in the logical-to-physical mapping. Modified versions of the logical address can be generated by flipping one or more bits in the logical address indicated by the metadata. Efficiency can do increased and improved performance can be attained. | 03-24-2016 |
20160085476 | MULTI-PARTITIONING OF MEMORIES - Various embodiments comprise devices to manage multiple memory types and reconfigure partitions in a memory device as directed by a host. In one embodiment, the apparatus is to manage commands through a first interface controller to mapped portions of a first memory not having an attribute enhanced set, and map portions of a second memory having the attribute enhanced set through a second interface controller. Additional devices are described. | 03-24-2016 |
20160085668 | TECHNIQUES FOR IMPROVING RELIABILITY AND PERFORMANCE OF PARTIALLY WRITTEN MEMORY BLOCKS IN MODERN FLASH MEMORY SYSTEMS - Methods and apparatus to improve reliability and/or performance of partially written memory blocks in flash memory systems are described. In some embodiments, a storage device stores information corresponding to a partial write operation performed on a partially programmed memory block of a non-volatile memory. Memory controller logic then cause application of a reduced voltage level and/or an offset value to portion(s) of the non-volatile memory during a read or write operation to the non-volatile memory based at least in part on the stored information. Other embodiments are also disclosed and claimed. | 03-24-2016 |
20160085671 | Three-Dimensional Mask-Programmed Read-Only Memory With Reserved Space - The present invention discloses a 3D-MPROM with reserved space (3D-MPROM | 03-24-2016 |
20160085681 | SMART FLASH CACHE LOGGER - Techniques herein are for chaining nonvolatile storage devices to achieve high availability. A method involves a storage server receiving a write request to store data blocks in a first nonvolatile memory device. The storage server comprises a plurality of nonvolatile memory devices that cache data blocks stored on primary storage. The plurality of nonvolatile memory devices comprises the first nonvolatile memory device. The storage server maintains a cache index of data blocks that reside in the plurality of nonvolatile memory devices. Based on one or more criteria, the storage server reroutes the write request to a second nonvolatile memory device of the plurality of nonvolatile memory devices and stores an identifier of the second nonvolatile memory device in the cache index. | 03-24-2016 |
20160092110 | SYSTEMS AND METHODS FOR CONFIGURING NON-VOLATILE MEMORY - Systems and methods are disclosed for configuring a non-volatile memory (“NVM”). In some embodiments, each block of the NVM can include a block table-of-contents (“TOC”), which can be encoded (e.g., run-length encoded) and dynamically-sized. Thus, as user data is being programmed to a block, the size of a block TOC can be concurrently recalculated and increased only if necessary. In some embodiments, the NVM interface can use a weave sequence stored in the context information and at least one weave sequence associated with each page of a block to determine whether to replay across the pages of the block after system boot-up. | 03-31-2016 |
20160092113 | HOST-MANAGED NON-VOLATILE MEMORY - One embodiment provides a computing device. The computing device includes a processor; a chipset; a memory; and indirection logic. The indirection logic is to receive a host logical block address (LBA) associated with a first sector of data, map the host LBA from a host address space to a first device LBA in a device address space, the device address space related to a non-volatile memory (NVM) storage device physical memory address space, and provide the first sector of data and the first device LBA to the NVM storage device. | 03-31-2016 |
20160092116 | MULTI-TIER SCHEME FOR LOGICAL STORAGE MANAGEMENT - A storage device may include a controller and a memory array including a plurality of dies arranged into a plurality of channels. In some examples, the controller may be configured to define, from the memory array, a plurality of die-sets based on respective chip enable lines associated with the plurality of dies, wherein each die-set of the plurality of die-sets includes at least one die from each of the plurality of channels; define, from a selected die-set of the plurality of die-sets, a plurality of blocksets, wherein each blockset includes a block from each die of the selected die-set; receive a unit of data to be stored; and issue commands that cause the unit of data to be stored in blocks of a selected blockset of the plurality of blocksets | 03-31-2016 |
20160092117 | REDUCTION OF PERFORMANCE IMPACT OF UNEVEN CHANNEL LOADING IN SOLID STATE DRIVES - Provided are a method and system for allocating read requests in a solid state drive coupled to a host. An arbiter in the solid state drive determines which of a plurality of channels in the solid state drive is a lightly loaded channel of a plurality of channels. Resources for processing one or more read requests intended for the determined lightly loaded channel are allocated, wherein the one or more read requests have been received from the host. The one or more read requests are placed in the determined lightly loaded channel for the processing. In certain embodiments, the lightly loaded channel is the most lightly loaded channel of the plurality of channels. | 03-31-2016 |
20160092120 | STORAGE DEVICE HEALTH DIAGNOSIS - A storage device may include a plurality of memory devices logically divided into a plurality of blocks and a controller. In some examples, the controller may be configured to determine a respective fullness percentage for each respective block of the plurality of blocks; determine the smallest fullness percentage for the plurality of respective fullness percentages; and responsive to determining that the smallest fullness percentage exceeds a predetermined threshold value, perform an action related to health of the storage device. | 03-31-2016 |
20160092121 | UNMAP STORAGE SPACE - A system that includes a storage drive and a controller communicatively coupled to the storage drive. The storage drive includes a first region of storage space that is mapped to a virtual volume and at least a second region of storage space reserved for over-provisioning operations. The controller is to unmap an operable portion of the first region of storage space in response to aging of the storage drive so that the unmapped portion can be used for over-provisioning operations. | 03-31-2016 |
20160092122 | METHOD AND APPARATUS FOR WEAR-LEVELLING NON-VOLATILE MEMORY - Apparatus and method for performing wear leveling are disclosed. An ordered list of references to each of a set of memory blocks is stored. A set of memory blocks in the ordered list is sequentially allocating. The allocated set of memory blocks in the ordered list are erased in the sequence in which they were allocated. | 03-31-2016 |
20160092124 | APPEND-ONLY STORAGE SYSTEM SUPPORTING OPEN AND CLOSED EXTENTS - The disclosed embodiments relate to the design of an append-only data storage system that stores sets of data blocks in extents that are located in storage devices in the system. During operation of the system, when an extent is in an open state, the system allows data blocks to be appended to the extent, and disallows operations to be performed on the extent that are incompatible with data being concurrently appended to the extent. When the extent becomes full, the system changes the extent from the open state to a closed state. Then, while the extent is in the closed state, the system disallows data blocks to be appended to the extent, and allows operations to be performed on the extent that are incompatible with data being concurrently appended to the extent. | 03-31-2016 |
20160092125 | CONSTRUCTING AN INDEX TO FACILITATE ACCESSING A CLOSED EXTENT IN AN APPEND-ONLY STORAGE SYSTEM - The disclosed embodiments relate to the design of an append-only data storage system that stores sets of data blocks in extents that are located in storage devices in the system. During operation of the system, when an extent becomes full, the system changing the extent from an open state, wherein data can be appended to the extent, to a closed state, wherein data cannot be appended to the extent. Changing the extent from the open state to the closed state includes performing the following operations at one or more storage devices that contain copies of the extent: constructing an index to facilitate accessing data blocks in a copy of the extent contained in the storage device; and appending the index to the copy of the extent in non-volatile storage in the storage device. | 03-31-2016 |
20160092128 | MOVING AND COMMITTING VALID DATA ON A SET-BY-SET BASIS - A storage module may be configured to organize data to be moved from an initial storage location to a destination storage location into sets, and to determine whether to commit the data to the destination storage location on a set-by-set basis. Error correction and/or a post write and read process may be performed on the sets that are copied to the destination storage location to determine whether to commit each of the copied sets. | 03-31-2016 |
20160092138 | OFFLINE DEDUPLICATION FOR SOLID-STATE STORAGE DEVICES - A method for managing a flash storage system includes reading flash data units from flash memory into a buffer, wherein each of the flash data units includes host data units, and determining an identifier for each host data unit. The method includes selecting a set of unique identifiers from the determined identifiers based on a number of host data units sharing the respective unique identifier. For each unique identifier in the set of unique identifier, the method includes designating one of the host data units as a master data unit, wherein the logical address of the designated host data unit is mapped to a physical address. The logical addresses of the other host data units sharing the unique identifier are remapped to the master physical address, and the physical addresses previously mapped to the remapped logical addresses are invalidated. | 03-31-2016 |
20160092143 | OPTIMIZED GARBAGE COLLECTION FOR SOLID-STATE STORAGE DEVICES - A method for managing a flash storage system includes reading a plurality of flash data units in the flash storage system, and identifying host data units having a first metadata tag from the host data units stored in the plurality of read flash data units. The method also includes buffering the identified host data units in a first transfer buffer, and writing the buffered host data units from the first transfer buffer to a first available flash data unit in the flash storage device. | 03-31-2016 |
20160092351 | MEMORY MODULE HAVING DIFFERENT TYPES OF MEMORY MOUNTED TOGETHER THEREON, AND INFORMATION PROCESSING DEVICE HAVING MEMORY MODULE MOUNTED THEREIN - A memory module having different types of memory mounted together on a double-sided substrate has a first edge and opposite second edge and includes a plurality of memory controllers, a plurality of flash memories, and a plurality of second memories having a higher signal transmission rate than the flash memories. A socket terminal for connecting the double-sided substrate to a motherboard is formed on the front surface and the back surface of the double-sided substrate on the first edge side; the memory controllers are disposed on the second edge side; the second memories are disposed on the second edge side at positions opposite the positions at which the memory controllers are disposed; and the flash memories are disposed on at least the back surface thereof at positions that are closer to the first edge than are the positions at which the memory controllers and the second memories are disposed. | 03-31-2016 |
20160092352 | REDUCING WRITE AMPLIFICATION IN SOLID-STATE DRIVES BY SEPARATING ALLOCATION OF RELOCATE WRITES FROM USER WRITES - In one embodiment, a method includes maintaining a first open logical erase block for user writes, maintaining a second open logical erase block for relocate writes, wherein the first and second open logical erase blocks are different logical erase blocks, receiving a first data stream having the user writes, transferring the first data stream to the first open logical erase block, receiving a second data stream having the relocate writes, and transferring the second data stream to the second open logical erase block. Other systems, methods, and computer program products are described in additional embodiments. | 03-31-2016 |
20160093377 | NONVOLATILE MEMORY MODULE - Memory modules, controllers, and electronic devices comprising memory modules are described. In one embodiment, a memory module comprises a nonvolatile memory and an interface to a volatile memory bus, at least one input power rail to receive power from a host platform, and a controller comprising logic, at least partially including hardware logic, to convert the power from the input power rail from an input voltage to at least one output voltage, different from the input voltage. Other embodiments are also disclosed and claimed. | 03-31-2016 |
20160093397 | METHOD AND SYSTEM FOR IMPROVING FLASH STORAGE UTILIZATION USING READ-THRESHOLD TABLES - A method for reading data from persistent storage. The method includes receiving a client read request that includes a logical address for data from a client, determining a physical address using the logical address where the physical address includes a page number for a physical page in the persistent storage, determining a retention time for the data, determining a program/erase (P/E) cycle value associated with the physical page, obtaining at least one read threshold value using the P/E cycle value, the retention time, and the page number, issuing a control module read request including the at least one read threshold value to a storage module that includes the physical page, and obtaining the data from the physical page using the at least one read threshold value. | 03-31-2016 |
20160098197 | NONVOLATILE MEMORY AND METHOD WITH STATE ENCODING AND PAGE-BY-PAGE PROGRAMMING YIELDING INVARIANT READ POINTS - A flash memory allows a range of charges to be programmed into its cells to represent 8 distinct memory states, which are encoded by 3 bits (upper, middle, lower) of data. A page of memory cells which is programmed or read in parallel yields corresponding upper, middle and lower data pages. In page-by-page schemes, each data page can be programmed and read independently. Each data page has a predetermined set of read points to distinguish between “1” and “0” bits. Prior state encodings have to use different sets of read points for a lower data page depending on whether or not the higher data pages are already programmed, as indicated by maintaining a flag. The present programming and state encoding schemes have invariant read points, independent of the program status of the higher order pages and do not require maintaining a flag, thereby improving read performance. | 04-07-2016 |
20160098201 | DATA STORAGE DEVICE AND OPERATING METHOD THEREOF - A data storage device includes a controller configured to update an access request count and an access count corresponding to a target region based on an access request for the target region, and initialize the access count each time the access request count reaches a first threshold, and a nonvolatile memory apparatus including the target region, and configured to access the target region based on a control of the controller. | 04-07-2016 |
20160098211 | IMPLEMENTING ENHANCED PHASE CHANGE MEMORY (PCM) READ LATENCY THROUGH CODING - A method, apparatus, and storage device are provided for implementing enhanced performance with enhanced phase-change-memory (PCM) read latency through coding. A coding algorithm is used to write data to the PCM including a redundancy chip enabling recovery of inaccessible partition data by reading other partitions. A read operation is served by reading parity lines and computing data for the read operation from a blocked written-to partition. | 04-07-2016 |
20160098213 | HYBRID STORAGE SYSTEM EMPLOYING RECONFIGURABLE MEMORY - A method includes comparing a number of memory blocks in a first pool of free memory blocks in a memory to a threshold. The memory includes memory blocks that are logically divided into the first pool, a second pool, and a third pool of memory blocks. The first pool of free memory blocks is expanded based on determining that the number of memory blocks in the first pool of free memory blocks is less than the threshold. The expanding includes: selecting a first memory block from the second pool of memory blocks, the first memory block comprising active and non-active content; selecting a second memory block from the third pool of memory blocks; copying the active content of the first memory block to the second memory block; erasing the first memory block; and adding the first memory block to the first pool of free memory blocks. | 04-07-2016 |
20160098214 | DATA STORAGE DEVICE AND OPERATING METHOD THEREOF - A data storage device includes a nonvolatile memory apparatus suitable for accessing a target region corresponding to an access command, and a processor suitable for calculating a first hash value corresponding to the target region based on a first hash function, and updating an access count that is indexed by the first hash value. | 04-07-2016 |
20160098215 | Method and System for Adaptively Assigning Logical Block Address Read Counters Using a Tree Structure - Systems, apparatuses, and methods are provided that dynamically reassign counters (or other memory monitors) in a memory. A plurality of counters may be assigned to different address ranges within an overall address range of a memory. The value of the counter may be indicative of activity, such as reads, within a respective assigned address range. Depending on the value of the counter, the respective address range of the counter may be dynamically changed. For example, a counter with a high value (indicating higher activity within the address range) may have its respective address range divided, with two counters being assigned to each of the divided address ranges. Likewise, counters with low values (indicating less activity within the address ranges) may have their respective address ranges combined, with a single counter being assigned to the combined address ranges. Thus, in subdividing and combining address ranges, the number of counters assigned may remain the same, while still monitoring the activity with the overall address range. | 04-07-2016 |
20160098220 | METHOD FOR WEAR LEVELING IN A NONVOLATILE MEMORY - A method for writing and reading data in memory cells, comprising, when writing a data in a block of a first memory zone, a step consisting of writing in a second memory zone a temporary information structure metadata comprising a start flag, an identifier of the temporary information structure, an information about the location of the block in the first memory zone, and a final flag, and, after a power on of the first memory zone, searching for an anomaly in temporary information structures present in the second memory zone. | 04-07-2016 |
20160098222 | CONTROLLING DEVICE, CONTROLLED DEVICE, AND OPERATING METHOD - A controlled device includes a non-volatile memory, a power pin, and a controller. The controller is configured for performing, through a negotiation module, a power negotiation operation with a controlling device via the power pin; receiving a programming declaration from the controlling device via the power pin; disabling the negotiation module according to the programming declaration; receiving a programming data from the controlling device via the power pin after the negotiation module is disabled; and writing the programming data into the non-volatile memory. In other embodiment, the controlled device can further includes at least one configuration channel pin for receiving the programming declaration therethrough. | 04-07-2016 |
20160098223 | CONTROLLER TO MANAGE NAND MEMORIES - A single virtualized ECC NAND controller executes an ECC algorithm and manages a stack of NAND flash memories. The virtualized ECC NAND controller allows the host processor to drive the stack of flash memory devices as a single NAND chip while the controller redirects the data to the selected NAND memory device in the stack. | 04-07-2016 |
20160098227 | System and Method to Provide File System Functionality Over a PCIe Interface - Techniques for providing file system functionality over a PCIe interface are disclosed. In some embodiments, the techniques may be realized as a method for providing file system functionality over a PCIe interface including receiving from a host device a storage command, specially devised for such a standard protocol, at a PCIe-based device controller, parsing, using at least one computer processor of the PCIe-based device controller, the storage command, traversing, using PCIe-based device controller, one or more portions of file system metadata of an associated storage media device, wherein the PCIe-based device controller is configured to traverse the one or more portions of file system metadata based on the parsed storage command independent of any subsequent communication with the host device, and returning data to the host device. | 04-07-2016 |
20160098350 | SIZING A CACHE WHILE TAKING INTO ACCOUNT A TOTAL BYTES WRITTEN REQUIREMENT - A total bytes written (TBW) requirement associated with solid state storage is obtained. A size of a cache associated with the solid state storage is determined based at least in part on the TBW requirement. The size of the cache is adjusted to be the determined size | 04-07-2016 |
20160103617 | SYSTEM AND METHOD FOR DYNAMICALLY ADJUSTING GARBAGE COLLECTION POLICIES IN SOLID-STATE MEMORY - Embodiments of the invention are directed to optimizing the selection of memory blocks for garbage collection in solid state devices to efficiently maximize the amount of memory freed by garbage collection operations. The systems and methods disclosed herein provide for the efficient selection of optimal or near-optimal garbage collection candidate blocks, with the most optimal selection defined as block(s) with the most invalid pages. In one embodiment, a controller classifies memory blocks into various invalid block pools by the amount of invalid pages each block contains. In one embodiment, the controller selects for garbage collection a block from a non-empty pool of blocks with the highest minimum amount of invalid pages. One or more of the pools have minimum thresholds that can be dynamically adjusted according to an observed usage condition, such as a change of an over-provisioning amount in the storage state device. | 04-14-2016 |
20160103621 | Multi-Block Data Storage Using Data Compression - Method and apparatus for data storage using data compression techniques. In some embodiments, a data recording medium has a recording surface with a plurality of concentric tracks accessible using a moveable data read/write transducer. A cache memory temporarily stores data during transfer operations with the data recording medium. A controller is configured to, responsive to receipt of input write data, retrieve from the data recording medium to the cache memory a selected multi-block data set associated with the input write data, use the received input data to update the retrieved multi-block data set, compress the updated retrieved multi-block data set to generate a compressed data set, and write the compressed data set to a selected band of adjacent tracks on the data recording surface. A portion of the compressed data set is generated during movement of the data read/write transducer to the selected band of adjacent tracks. | 04-14-2016 |
20160103622 | NON-VOLATILE MEMORY DEVICES AND CONTROLLERS - In recovery operations performed after non-volatile memory devices (i.e., flash memories and so on) experience abnormal status, when unstable data pages are found, valid data pages are copied to another physical block from the original physical block directly and the original physical block is not utilized any more, in order to prevent from spreading error. Further, in order to accelerate the determination process, only partial data of a page is read and whether the page is a valid page is determined based on statistic, when finding out which page is a valid page. | 04-14-2016 |
20160103623 | METHOD FOR CONTROLLED COLLISION OF HASH ALGORITHM BASED ON NAND FLASH MEMORY - The following description provides method for controlled collision of hash algorithm based on NAND flash memory improving data process performance by applying a hash structure on an optimized data structure in a NAND flash memory, using a coalesced chaining scheme. Further, the following description provides a method for controlled collision of hash algorithm based on NAND flash memory including a) setting one bucket size and an NAND flash memory page size identical; and b) storing a record regarding a plurality of hash values in the one bucket in NAND flash memory based hash index method. Further, when using a coalesced chaining and bucket separation scheme on a coalesced chaining scheme, storage space smaller than the separation chaining scheme, fast insert, fast retrieving are all possible, thereby data processing may be improved. | 04-14-2016 |
20160103625 | DEVICE, HOST APPARATUS, HOST SYSTEM, AND MEMORY SYSTEM - According to one embodiment, a device includes a semiconductor memory and a controller. The semiconductor memory includes first and second areas which are accessible from an outside. The controller controls the semiconductor memory. The device includes an unlocked state where accessing the first area is allowed, and a locked state where the accessing the first area is prohibited. The device is capable of holding one or more user key in the device. The device includes a function of configuration operation to register, change, and delete the user key in the semiconductor memory. | 04-14-2016 |
20160103626 | SYSTEM AND METHOD FOR REDUCING INFORMATION LEAKAGE FROM MEMORY - A system and method includes a processing unit connected with a memory, the processing unit configured to access data from the memory. A memory transaction unit is added between the processing unit and the memory. The memory transaction unit is configured to perform dummy read- and write-operations at random memory locations at random times and/or insert random delays before real accesses by the processing unit from the memory. | 04-14-2016 |
20160103629 | STORAGE SYSTEM HAVING A PLURALITY OF FLASH PACKAGES - A storage system | 04-14-2016 |
20160103631 | NON-VOLATILE MEMORY DEVICES AND CONTROL METHODS THEREFOR - A non-volatile memory device is provided. The non-volatile memory device includes a non-volatile memory, a connection interface, and a controller. The non-volatile memory is divided into a plurality of physical blocks. Each physical block is divided into a plurality of physical pages. The connection interface is connected to a host. The controller is connected to the connection interface. When the controller performs a block-reconfiguration operation, the controller re-adjusts a position in the physical blocks where data is disposed to obtain a usable physical block. Movement of one portion of the data related to the block-reconfiguration operation is performed when the controller operations an initial operation. Movement of another portion of the data related to the block-reconfiguration operation is performed when the controller processes a read command from the host. | 04-14-2016 |
20160103762 | APPARATUS, SYSTEMS, AND METHODS FOR PROVIDING WEAR LEVELING IN SOLID STATE DEVICES - Embodiments of the present disclosure provides a memory-efficient mechanism for identifying memory blocks with a low wear count. More particularly, embodiments of the present disclosure provides a mechanism for identifying a memory block whose wear count is within the bottom p % of all wear counts associated with memory blocks in a storage system. If a memory controller always performs the garbage collection operation on a memory block whose wear count is within the bottom p % of all wear counts, then the memory controller is expected to utilize the remaining memory blocks (e.g., memory blocks whose wear count is within the upper (100−p) % of all wear counts) efficiently and level the wear count of at least the remaining memory blocks. | 04-14-2016 |
20160104522 | METHOD OF USE TIME MANAGEMENT FOR SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE INCLUDING USE TIME MANAGING CIRCUIT - A use time managing method of a semiconductor device may include (1) measuring an amount of accumulated operation time of the semiconductor device and when the amount is reached to a predetermined value, generating a unit storage activation signal; (2) repeating step (1) to generate one or more additional unit storage activation signals, thereby generating a plurality of unit storage activation signals, wherein the predetermined values are different for each repeating step; (3) storing data indicating each occurrence of generating the unit storage activation signals; and (4) detecting use time of the semiconductor device based on the cumulatively stored data. | 04-14-2016 |
20160104538 | SEMICONDUCTOR DEVICE - The semiconductor device may include a memory block including a memory string electrically coupled between a bit line and a common source line, the memory string including source select transistors and memory cells configured to operate in response to operating voltages applied to select lines and word lines coupled to the memory cells and the source select transistors. The semiconductor device may include an operation circuit configured to apply a source voltage to the common source line for an erase operation, and to control floating states of the select lines and the word lines. The operation circuit may be configured to set the select lines to a floating state after the source voltage starts to increase from a precharge level to an erase level. | 04-14-2016 |
20160110102 | HYBRID MEMORY MODULE STRUCTURE AND METHOD OF DRIVING THE SAME - A hybrid memory module structure includes a channel for receiving data from and transmitting data to a device external to the hybrid memory module structure, a first memory module connected to the channel, and a second memory module connected to the channel. The first memory module includes at least a first memory and a second memory, the first memory being a working memory and the second memory being a storage memory. The second memory module includes at least a third memory and a fourth memory, the third memory being a working memory and the fourth memory being a storage memory. The channel includes a first data line commonly connected to the first memory and the second memory, and a second data line commonly connected to the third memory and the fourth memory. | 04-21-2016 |
20160110103 | DATA PROCESSING SYSTEM AND METHOD OF OPERATING THE SAME - A method of operating a data processing system includes transmitting process information indicating that a first process is classified as a critical process or a non-critical process to a kernel area, wherein the process information is generated in an application area, and the application area and the kernel area define a host. When the first process is classified as a critical process based on the process information, a first fastpath write signal is provided, using the kernel area, to a memory system to perform a fastpath write operation of first data for performing the first process. When the first process is classified as a non-critical process, a first slowpath write signal is provided to the memory system to perform a slowpath write operation of the first data. The fastpath write operation has a higher write speed than the slowpath write operation. | 04-21-2016 |
20160110106 | MULTI-LEVEL MEMORY WITH DIRECT ACCESS - Examples of a multi-level memory with direct access are described. Examples include designating an amount of a non-volatile random access memory (NVRAM) for use as memory for a computer system. Examples also include designating a second amount of the NVRAM to for use as storage for the computing device. Examples also include re-designating at least a first portion of the first amount of NVRAM from use as memory to use as storage. | 04-21-2016 |
20160110107 | METHOD FOR WRITING DATA INTO FLASH MEMORY APPARATUS, FLASH MEMORY APPARATUS, AND STORAGE SYSTEM - A flash memory apparatus for controlling storage of data comprises a plurality of blocks for storing data and a controller. Each block includes a plurality of pages. The controller receives first target data and identifies a first block to store the first target data. Then, the controller divides the first target data into two parts. A size of a first part is equal to the available capacity of the first block. And a size of a second part is equal to the size of the first target data minus the size of the first part. The controller further determines a second block that has stored data but is not full. At last, the controller writes the first part into the first block and write the second part into the second block. | 04-21-2016 |
20160110111 | EFFICIENT INITIALIZATION OF A THINLY PROVISIONED STORAGE ARRAY - In at least one embodiment, a data storage system has a plurality of non-volatile storage devices, a higher level controller and one or more lower level controllers. In response to one or more inputs, the higher level controller of the data storage system issues an initialization command specifying initialization of a storage extent. In response to the initialization command, one or more lower level controllers issue dataless initialization commands to the plurality of non-volatile storage devices. In response to the dataless initialization commands, multiple first non-volatile storage devices among the plurality of non-volatile storage devices each initialize a respective data portion of the storage extent and a second non-volatile storage device among the plurality of non-volatile storage devices initializes a data protection portion of the storage extent. | 04-21-2016 |
20160110112 | DATA WRITING METHOD, MEMOEY CONTROL CIRCUIT UNIT AND MEMORY STORAGE APPARATUS - A data writing method for a rewritable non-volatile memory module is provided. The method includes: if data belongs to a first pattern, using a first compression/decompression circuit to compress the data to generate compressed data and writing the compressed data into the rewritable non-volatile memory module; and if data belongs to a second pattern, using a second compression/decompression circuit to compress the data to generate another compressed data and writing the another compressed data into the rewritable non-volatile memory module, wherein the compression speed of the first compression/decompression circuit is higher than that of the second compression/decompression circuit, and the compression rate of the first compression/decompression circuit is lower than that of the second compression/decompression circuit. | 04-21-2016 |
20160110114 | DATA STORAGE DEVICE INCLUDING NONVOLATILE MEMORY DEVICE AND OPERATING METHOD THEREOF - A method of operating a data storage device includes programming non-fully programmed memory blocks at a point in time when a reference time elapses from a point in time when each of the memory blocks is physically erased, acquiring a first interval and a second interval, calculating a disturb index based on the first interval and the second interval, selecting a victim block for garbage collection based on the disturb index, and copying valid page data of the victim block into a free block. The first interval is defined by a point in time when each of the memory blocks is physically erased and a point in time when each of the memory blocks is fully programmed. The second interval is an interval during which a fully programmed state is maintained after a point in time when each of the memory blocks is fully programmed. | 04-21-2016 |
20160110118 | STORAGE OF DATA REFERENCE BLOCKS AND DELTAS IN DIFFERENT STORAGE DEVICES - A data storage architecture is composed of an array of a flash memory solid state disk and a hard disk drive or any nonvolatile random access storage that are intelligently coupled by an intelligent processing unit such as a multi-core graphic processing unit. The solid state disk stores seldom-changed and mostly read reference data blocks while the hard disk drive stores compressed deltas between currently accessed I/O blocks and their corresponding reference blocks in the solid state disk so that random writes are not performed on the solid state disk during online I/O operations. The solid state disk and hard disk drive are controlled by the intelligent processing unit, which carries out high speed computations including similarity detection and delta compression/decompression. The architecture exploits the fast read performance of solid state disks and the high speed computation of graphic processing units to replace mechanical operations on hard disk drives while avoiding slow and wearing solid state drive writes. | 04-21-2016 |
20160110119 | DIRECT MEMORY ACCESS FOR COMMAND-BASED MEMORY DEVICE - In a processing system, an integrated function controller (IFC) for one or more memory devices, including a NAND flash memory device, provides direct memory access (DMA) functionality for writing data to and reading data from the NAND flash memory device, thereby reducing the level of CPU intervention required to support such operations. In one implementation, the CPU stores in system memory a descriptor-based DMA operation sequence of NAND flash operations and then triggers the IFC to implement the descriptor sequence. The IFC sequentially fetches and implements individual stored descriptors without interrupting the CPU or requiring any real-time CPU intervention using, for example, a “repeat while busy” polling descriptor type. The IFC frees up the CPU to perform other system-level operations, thereby increasing the efficiency of the processing system. | 04-21-2016 |
20160110126 | ALL-FLASH-ARRAY PRIMARY STORAGE AND CACHING APPLIANCES IMPLEMENTING TRIPLE-LEVEL CELL (TLC)-NAND SEMICONDUCTOR MICROCHPS - A computer-implemented method for storing and caching data in an all-flash-array includes erasing a TLC-NAND flash cell and programming the cell with a binary value multiple times in sequence corresponding to multiple sequential stages between erasures. The method also includes processing the binary value in relation to a respective threshold voltage at each of the multiple sequential stages. The method further includes storing metadata corresponding to a current stage associated with the number of times the TLC-NAND flash cell has been programmed since being erased. | 04-21-2016 |
20160110133 | Flash memory controller - A flash memory controller for controlling a flash memory module includes a communication interface for receiving a first data and a second data; and a processing circuit for dynamically controlling a data writing mode of the flash memory module according to an amount of stored data in the flash memory module. If the amount of stored data in the flash memory module is less than a first threshold when the communication interface receives the first data, the processing circuit controls the flash memory module so that the first data is written into the first data block under an one-bit-per-cell mode. If the amount of stored data in the flash memory module is greater than the first threshold when the communication interface receives the second data, the processing circuit controls the flash memory module so that the second data is written into the second data block under a two-bit-per-cell mode. | 04-21-2016 |
20160110292 | EFFICIENT KEY COLLISION HANDLING - Inventive aspects include a key value store engine including non-volatile memory configured to store key-value inode descriptors each including a key and an associated value. The key value store engine can include a volatile memory to store a key hash tree and a collision hash tree. The key hash tree can include nodes each having a hash of one of the keys. The collision hash tree can include nodes each having a collided hash associated with two or more different keys. Each of the nodes of the key hash tree can include a collision flag indicating whether two or more different hashes correspond to a collided hash. The volatile memory can store a collision linked list including linked list nodes each having a key-value inode number indicating a location of a corresponding key-value inode descriptor stored in the non-volatile memory. The key value store engine can include a key value logic section. | 04-21-2016 |
20160110566 | APPARATUS, SYSTEMS AND METHODS FOR SECURELY STORING MEDIA CONTENT EVENTS ON A FLASH MEMORY DEVICE - Systems and methods are operable to securely store media content events on a flash memory device. An exemplary embodiment receives user-provided authorization information, compares the received user-provided authorization information with authorization information associated with the flash memory device, and permits access to a flash memory of the flash memory device when the received user-provided authorization information corresponds to the authorization information. | 04-21-2016 |
20160117099 | Tracking Intermix of Writes and Un-Map Commands Across Power Cycles - Systems, methods and/or devices are used to enable tracking intermix of writes and un-map commands across power cycles. In one aspect, the method includes (1) receiving, at a storage device, a plurality of commands from a host, the storage device including non-volatile memory, (2) maintaining a log corresponding to write commands and un-map commands from the host, (3) maintaining a mapping table in volatile memory, the mapping table used to translate logical addresses to physical addresses, (4) saving the mapping table, on a scheduled basis that is independent of the un-map commands, to the non-volatile memory of the storage device, (5) saving the log to the non-volatile memory, and (6) upon power up of the storage device, rebuilding the mapping table from the saved mapping table in the non-volatile memory of the storage device and from the saved log in the non-volatile memory of the storage device. | 04-28-2016 |
20160117101 | MEMORY SYSTEM, MEMORY MODULE, AND METHODS OF OPERATING THE SAME - A memory system includes a memory controller, a first memory module and second through k-th memory modules. The first memory module is directly coupled to the memory controller without any other memory modules communicatively coupled therebetween, through a first memory bus, and the first memory module exchanges first data with the memory controller. | 04-28-2016 |
20160117102 | METHOD FOR OPERATING DATA STORAGE DEVICE, MOBILE COMPUTING DEVICE HAVING THE SAME, AND METHOD OF THE MOBILE COMPUTING DEVICE - A method for operating a data storage device includes receiving a command including a set bit transmitted from a host, storing the set bit in a register in response to the command, receiving a first state check command from the host, and transmitting a response which includes state information of the data storage device and processing information corresponding to a write command in the data storage device to the host based on the first state check command and the set bit stored in the register. | 04-28-2016 |
20160117105 | Method and System for Throttling Bandwidth Based on Temperature - Systems, methods, and/or devices are used to manage a storage system. In one aspect, the method includes, during a first time period: maintaining a credit pool for the first time period; limiting bandwidth used for transmitting data between a storage device of the storage system and a host operatively coupled with the storage device according to a status of the credit pool, where the storage device includes one or more memory devices; monitoring a temperature of the storage device; and, in accordance with a determination that a current temperature of the storage device exceeds a predetermined threshold temperature and the current temperature of the storage device satisfies one or more temperature criteria, reducing an initial value of the credit pool for a second time period according to a first adjustment factor corresponding to the predetermined temperature threshold, where the second time period is subsequent to the first time period. | 04-28-2016 |
20160117110 | MEMORY SYSTEMS INCLUDING AN INPUT/OUTPUT BUFFER CIRCUIT - Memory systems are provided. A memory system may include a plurality of nonvolatile memories and a memory controller configured to control the plurality of nonvolatile memories. Moreover, the memory system may include an input/output buffer circuit connected between the memory controller and the plurality of nonvolatile memories. A data channel may be connected between the memory controller and the input/output buffer circuit, and first and second internal data channels may be connected between the input/output buffer circuit and respective first and second groups of the plurality of nonvolatile memories. The input/output buffer circuit may be configured to connect the data channel to one of the first and second internal data channels. | 04-28-2016 |
20160117112 | TRIM COMMAND PROCESSING IN A SOLID STATE DRIVE - A device may comprise a plurality of non-volatile memories configured to store a plurality of physical pages and a controller coupled thereto, configured to program and read data to and from the plurality of memory devices. The data may be stored in a plurality of logical pages (L-Pages) of non-zero length at starting addresses within the plurality of physical pages and execute first and second commands to indicate that first and second physical locations within the plurality of non-volatile memories no longer contains valid data and are now free space. This may be done by carrying out first and second virtual write operations of first and second L-Pages of a predetermined length at first and second unique addresses within a virtual address range that does not correspond to any of the physical pages, and accounting for an amount of free space gained as a result of executing the commands. | 04-28-2016 |
20160117119 | STORAGE DEVICE AND OPERATING METHOD OF THE SAME - An operating method of a storage device including a nonvolatile memory and a memory controller configured to control the nonvolatile memory may include selecting one of a plurality of submission queues; fetching, from the selected submission queue, a command for accessing the storage device; executing the fetched command; outputting an execution result of the fetched command to a selected completion queue corresponding to the selected submission queue; determining whether a submission queue is a full submission queue, the full submission queue corresponding to a full completion queue; and inhibiting the selecting from selecting the full submission queue until the full completion queue becomes a normal completion queue, when the determining determines a submission queue is the full submission queue, wherein the plurality of submission queues are sequentially selected in accordance with round robin scheduling. | 04-28-2016 |
20160117131 | ASYMMETRIC MEMORY MIGRATION IN HYBRID MAIN MEMORY - Main memory is managed by receiving a command from an application to read data associated with a virtual address that is mapped to the main memory. A memory controller determines that the virtual address is mapped to one of the symmetric memory components of the main memory, and accesses memory use characteristics indicating how the data associated with the virtual address has been accessed, The memory controller determines that the data associated with the virtual address has access characteristics suited to an asymmetric memory component of the main memory and loads the data associated with the virtual address to the asymmetric memory component of the main memory. After the loading and using the memory management unit, a command is received from the application to read the data associated with the virtual address, and the data associated with the virtual address is retrieved from the asymmetric memory component. | 04-28-2016 |
20160117244 | DATA WRITING METHOD, MEMORY CONTROL CIRCUIT UNIT AND MEMORY STORAGE APPARATUS - A data writing method for a rewritable non-volatile memory module is provided. The method includes: compressing data to generate first data; determining whether a data length of the first data meets a predetermined condition. The method also includes: if the data length of the first data meets the predetermined condition, writing the first data into a first physical erasing unit among a plurality of physical erasing units; if the data length of the first data does not meet the predetermined condition, generating dummy data according to a predetermined rule, padding the first data with the dummy data to generate second data and writing the second data into the first physical erasing unit. A data length of the second data meets the predetermined condition. | 04-28-2016 |
20160117253 | Method for Improving Mixed Random Performance in Low Queue Depth Workloads - Systems, methods and/or devices are used to enable improving mixed random performance in low queue depth workloads in a storage device (e.g., comprising a plurality of non-volatile memory units, such as one or more flash memory devices). In one aspect, the method includes (1) maintaining a write cache corresponding to write commands from a host, (2) determining a workload in accordance with commands from the host, (3) in accordance with a determination that the workload is a non-qualifying workload, scheduling a regular flush of the write cache, and (4) in accordance with a determination that the workload is a qualifying workload, scheduling an optimized flush of the write cache. | 04-28-2016 |
20160117256 | NONVOLATILE MEMORY DEVICES AND METHODS OF CONTROLLING THE SAME - At least one example embodiment discloses a method of controlling a nonvolatile memory device including a plurality of blocks, each block including a plurality of physical pages. The method includes receiving a plurality of logical pages associated with a first plurality of logical addresses, respectively, and writing the first plurality of logical pages to the plurality physical addresses according to an ascending order of the logical addresses of the first plurality of logical pages. | 04-28-2016 |
20160118126 | NONVOLATILE MEMORY DEVICES AND PROGRAM METHOD THEREOF - A program method of a nonvolatile memory device is provided which includes programming memory cells to a target state using a verification voltage and an incremental step pulse, selecting memory cells, each having a threshold voltage lower than a supplementary verification voltage, from among the memory cells programmed to the target state, and applying a supplementary program voltage to the selected memory cells. The supplementary verification voltage is equal to or higher than the verification voltage, and the supplementary program voltage is equal to or lower than a program voltage provided in a program loop where a programming of the memory cells to the target state is completed. | 04-28-2016 |
20160118130 | PERFORMANCE ACCELERATION DURING SHUTDOWN OF A DATA STORAGE DEVICE - A storage device may include a non-volatile memory; and a controller. The controller may be configured to: operate the data storage device in a standard mode by at least throttling performance, and, responsive to detecting a power loss condition, operate the data storage device in a shutdown mode by at least disabling the throttling. | 04-28-2016 |
20160124640 | MEMORY SYSTEM AND METHOD OF OPERATING THE SAME - A memory system includes a first control circuit part configured to communicate with a host through a first host channel, a second control circuit part configured to communicate with the host through a second host channel, a first chip group configured to communicate with the first control circuit part through a first internal channel, and a second chip group configured to communicate with the second control circuit part through a second internal channel, wherein the first control circuit part and the second control circuit part alternately receive a plurality of data inputted through one of the first and second host channels, which is selected during a single channel operation, and transmit the data to the first chip group and the second chip group. | 05-05-2016 |
20160124649 | METHOD TO REDUCE FLASH MEMORY IOs WITH HOST MAINTAINED ADDRESS MAPPING TABLE - A system, method and program product for transferring contiguous blocks of data between a host storage and a flash memory. A method is disclosed that includes: receiving from a host at a flash controller a host command that specifies a contiguous set of LBAs and specifies a corresponding sub-section of an LBA to PBA mapping table; fetching the sub-section of the LBA to PBA mapping table from the host and storing the sub-section in a sub-mapping table; and for each LBA in the contiguous set of LBAs, performing a look-up into the sub-mapping table to retrieve a corresponding PBA and using the corresponding PBA to effectuate a data transfer between the host and flash memory from the flash controller. | 05-05-2016 |
20160124650 | Data Storage Device and Flash Memory Control Method - A flash memory control technology with high performance efficiency is provided. A microcontroller is configured to build an ending logical address table in a random access memory to record ending logical addresses of a plurality of old write commands issued from a host. The microcontroller is further configured to compare a starting address of a current write command issued from the host and information in the ending logical address table, to determine whether any of the plurality of old write commands is a former string write command with respect to the current write command that the former string write command and the current write command combined together form sequential data writing. The microcontroller is further configured to overwrite an ending logical address of the current write command onto a column in the ending logical address table recording the ending logical address of the former string write command. | 05-05-2016 |
20160124654 | SYSTEM AND METHOD FOR DISTRIBUTED COMPUTING IN NON-VOLATILE MEMORY - A system and method are disclosed for incorporating mathematical and/or logical functionality within a memory system (such as a solid state drive (SSD)). The mathematical and/or logical functionality may comprise an arithmetic logic unit (ALU). The ALU may be resident in one or both of flash memory chips or the SSD controller. When resident in the flash memory chips, a single ALU or multiple ALUs may be used. For example, a single ALU may be assigned to one, some, or each block of flash memory within the flash memory chip. As another example, an ALU may be assigned to a sub-block construct, such as to each bit line in the block. Having ALUs resident in the SSD enables more processing to be performed within the SSD and reduces the need to transmit data outside of the SSD for processing. | 05-05-2016 |
20160124655 | Automatically Preventing Large Block Writes From Starving Small Block Writes In a Storage Device - A mechanism is provided in a storage device for performing a write operation. The mechanism configures a write buffer memory with a plurality of write buffer portions. Each write buffer portion is dedicated to a predetermined block size category within a plurality of block size categories. For each write operation from an initiator, the mechanism determines a block size category of the write operation. The mechanism performs each write operation by writing to a write buffer portion within the plurality of write buffer portions corresponding to the block size category of the write operation. | 05-05-2016 |
20160124656 | RECORDING DWELL TIME IN A NON-VOLATILE MEMORY SYSTEM - In at least one embodiment, a data storage system includes a non-volatile memory array, such as a flash memory array, and a controller coupled to the memory array. The controller records, for each of a plurality of valid pages in the memory array, a respective indication of a dwell time of each valid page. | 05-05-2016 |
20160124662 | SKEWING EXPECTED WEAROUT TIMES OF MEMORY DEVICES - Aspects of the present invention include a system, method, and computer program product for skewing expected wearout times of memory devices in an array are provided according to some embodiments of the present invention. In general, the method includes determining or receiving an amount of spare space to provide in an array of memory devices, allocating the spare space non-uniformly to the memory devices in the array, and skewing expected wearout times of the memory devices by controlling writing of data to the array according to the allocation of the spare space. | 05-05-2016 |
20160124664 | Block Level Local Column Redundancy Methods for Higher Yield - A non-volatile flash memory has bit lines spanning multiple blocks grouped into columns, where each block is connected along multiple regular columns and one or more redundancy columns. When there is a local column defect, so that the defect is not at the level of the whole block or global column, the portions of a column at an individual block can be remapped to a portion of the same block along a redundant column. Sections of multiple columns from different blocks can be remapped to the same redundancy column. | 05-05-2016 |
20160124679 | Read Scrub with Adaptive Counter Management - A number of complimentary techniques for the read scrub process using adaptive counter management are presented. In one set of techniques, in addition to maintaining a cumulative read counter for a block, a boundary word line counter can also be maintained to track the number of reads to most recently written word line or word lines of a partially written block. Another set of techniques used read count threshold values that vary with the number of program/erase cycles that a block has undergone. Further techniques involve setting the read count threshold for a closed (fully written) block based upon the number reads it experienced prior to being closed. These techniques can also be applied at a sub-block, zone level. | 05-05-2016 |
20160124682 | DATA STORAGE SYSTEM - A data storage system including a processor configured to execute a plurality of tasks, wherein the processor is configured to generate writing status information based on the data relevant information and otre the data relevant information and the writing status information in association with each other in the nonvolatile memory when the processor write data in the recording medium based on demand of the task and writing to the recording medium is configured to be controlled based on the data relevant information and the write-in status information stored in nonvolatile memory. | 05-05-2016 |
20160124684 | METHOD TO REALIZE OBJECT-ORIENTED IN-MEMORY DATA STORAGE AND PROCESSING - A system and method of providing in-memory data processing for object-oriented data with a flash memory storage. A system is disclosed that includes: a first logic process for providing intra-object data processing involving a single data object with an expansion factor greater than one; a second logic process for providing intra-object data processing involving a single data object with an expansion factor less than one; and a third logic process for providing inter-object data processing involving multiple objects. | 05-05-2016 |
20160124831 | HEALTH REPORTING FROM NON-VOLATILE BLOCK STORAGE DEVICE TO PROCESSING DEVICE - Methods and devices are provided for adapting an I/O pattern, with respect to a processing device using a non-volatile block storage device based on feedback from the non-volatile block storage device. The feedback may include information indicating a status of the non-volatile block storage device. In response to receiving the feedback, a storage subsystem, included in an operating system executing on processing device, may change a behavior with respect to the non-volatile block storage device in order to avoid, or reduce, a negative impact to the non-volatile block storage device or to enhance an aspect of the non-volatile block storage device. The feedback may include performance information and/or operating environmental information of the non-volatile block storage device. When the non-volatile block storage device is not capable of providing the feedback, the processing device may request information about the non-volatile block storage device from a database service. | 05-05-2016 |
20160124842 | MEMORY SYSTEM AND NON-TRANSITORY COMPUTER READABLE RECORDING MEDIUM - According to one embodiment, a memory system includes a nonvolatile memory, configuration unit, address translation unit, write unit and control unit. The configuration unit assigns write management areas included in the nonvolatile memory to spaces. The write management area is a unit of an area which manages the number of write. The address translation unit translates a logical address of write data into a physical address of a space corresponding to the write data. The write unit writes the write data to a position indicated by the physical address in the nonvolatile memory. The control unit controls the spaces individually with respect to the nonvolatile memory. | 05-05-2016 |
20160124843 | MEMORY SYSTEM AND NON-TRANSITORY COMPUTER READABLE RECORDING MEDIUM - According to one embodiment, a memory system includes a nonvolatile memory, configuration unit, address translation unit, write unit and control unit. The configuration unit assigns write management areas included in a nonvolatile memory to spaces and an input space. The write management area is a unit of an area which manages the number of write. The address translation unit associates a logical address of write data with a physical address which indicates a position of the write data in the nonvolatile memory. The write unit writes the write data to the input space and then writes the write data in the input space to a space corresponding to the write data amongst the spaces. The control unit controls the spaces individually with respect to the nonvolatile memory. | 05-05-2016 |
20160124844 | DATA STORAGE DEVICE AND FLASH MEMORY CONTROL METHOD - A flash memory control technology with high performance efficiency. A logical block table is managed on a random access memory to record logical blocks of breakpoints of sequential write operations issued from a host to write a flash memory. It is prohibited from performing garbage collection on the logical blocks recorded in the logical block table. In this manner, the system resources are no longer wasted by hastily organizing incomplete sequential write data. | 05-05-2016 |
20160124845 | Data Storage Device and Flash Memory Control Method - A flash memory control technology with high efficiency, which records a logical page table in a random access memory. The logical pages that have been collected from a data-interspersed block into a destination block of a flash memory are recorded in the logical page table. Without accessing a logical-to-physical address mapping table stored in the flash memory, the physical pages in the data-interspersed block corresponding to the logical pages recorded in the logical page table are regarded as containing invalid data. | 05-05-2016 |
20160124846 | ADAPTIVE SPANNING CONTROL - The disclosed technology provides for a solid state device that adaptively determines, responsive to receipt of a write command, whether or not to partition one or more individual logical blocks of data between multiple pages of a flash storage device. According to one implementation, the partitioning (e.g., spanning) determination is based on read frequency characteristics and the internal error correction code rate of the data. | 05-05-2016 |
20160124847 | SCHEDULED GARBAGE COLLECTION FOR SOLID STATE STORAGE DEVICES - A processing device identifies a plurality of solid state storage devices arranged in an array and determines, for at least one solid state storage device of the plurality of solid state storage devices, a first time window during which the at least one solid state storage device is permitted to perform one or more garbage collection operations. The processing device then sends, to the at least one solid state storage device, a message comprising the first time window allocated to the at least one storage device, wherein the at least one solid state storage device is to perform the garbage collection operations during the first time window allocated to the at least one solid state storage device. | 05-05-2016 |
20160124848 | MEMORY SYSTEM AND MEMORY MANAGEMENT METHOD THEREOF - A memory system include a memory device including a plurality of blocks, each of the blocks having a plurality of pages, and a controller suitable for determining valid pages from among the plurality of pages based on data temperature, and performing a garbage collection process based on a number of valid pages and data temperature of the valid pages. | 05-05-2016 |
20160132237 | DATA STORAGE DEVICE, DATA PROCESSING SYSTEM AND METHOD OF OPERATION - A data processing system includes a host capable of pipelining execution of a command set including a plurality of commands by storing the commands in a buffer, and a data storage device including a NVMe controller that receives the commands and controls execution of data access operations corresponding to the respective commands, generates a completion response upon successfully executing each one of the commands, and stores the resulting completion responses in a buffer, wherein the NVMe controller extracts at least two of the completion responses stored in the buffer to generate a completion packet and transmits the completion packet to the host during a single transaction. | 05-12-2016 |
20160132241 | METHODS AND SYSTEMS FOR MAPPING A PERIPHERAL FUNCTION ONTO A LEGACY MEMORY INTERFACE - A memory system includes a CPU that communicates commands and addresses to a main-memory module. The module includes a buffer circuit that relays commands and data between the CPU and the main memory. The memory module additionally includes an embedded processor that shares access to main memory in support of peripheral functionality, such as graphics processing, for improved overall system performance. The buffer circuit facilitates the communication of instructions and data between CPU and the peripheral processor in a manner that minimizes or eliminates the need to modify CPU, and consequently reduces practical barriers to the adoption of main-memory modules with integrated processing power. | 05-12-2016 |
20160132242 | NETWORK STORAGE SYSTEM USING FLASH STORAGE - A system can comprise an I/O circuitry, a processor, reconfigurable circuitry, an array of flash storage devices, and a serial interconnect network that is coupled to transfer data between the I/O circuitry, the processor, the reconfigurable circuitry and the flash storage devices. The processor can be configured to designate an interconnect address space for use in communication over the interconnect network among the I/O circuitry, the processor, the reconfigurable circuitry and the flash storage devices. The reconfigurable circuitry can be configured to translate data addresses during transfers of data between the I/O circuitry and the array of flash storage devices. A method to access an array of flash storage devices that are coupled to I/O circuitry over a serial interconnect network can comprise using reconfigurable circuitry to capture data during transfers of data over the serial interconnect network. | 05-12-2016 |
20160132243 | SYSTEMS, METHODS, AND INTERFACES FOR VECTOR INPUT/OUTPUT OPERATIONS - Data of a vector storage request pertaining to one or more disjoint, non-adjacent, and/or non-contiguous logical identifier ranges are stored contiguously within a log on a non-volatile storage medium. A request consolidation module modifies one or more sub-requests of the vector storage request in response to other, cached storage requests. Data of an atomic vector storage request may comprise persistent indicators, such as persistent metadata flags, to identify data pertaining to incomplete atomic storage requests. A restart recovery module identifies and excludes data of incomplete atomic operations. | 05-12-2016 |
20160132249 | Methods for Accessing a Storage Unit of a Flash Memory and Apparatuses using the Same - An embodiment of a method for accessing a storage unit of a flash memory, performed by a processing unit, includes at least the following steps. A storage-unit access interface is directed to program data into the nth wordline of a storage unit. The storage-unit access interface is directed to program the same data into the (n−1)th wordline of the storage unit after the storage unit completes the data programming of the nth wordline of the storage unit. The storage-unit access interface is directed to program the same data into the (n−2)th wordline of the storage unit after the storage unit completes the data programming of the (n−1)th wordline of the storage unit, where n is an integer greater than 2. | 05-12-2016 |
20160132253 | Data Storage Device and Operating Method - A data storage device includes a FLASH memory and a controller. The FLASH memory includes a plurality of blocks wherein each of the blocks includes a plurality of pages. The controller is coupled to the FLASH memory and utilized to execute a garbage-collection process on the FLASH memory according to a number of spare blocks in the FLASH memory and a number of inefficient blocks where most of the pages are spare in the FLASH memory. The garbage-collection process is utilized for merging at least two inefficient blocks to release at least one spare block from the inefficient blocks. | 05-12-2016 |
20160132256 | OPERATING METHOD FOR NONVOLATILE MEMORY DEVICE, MEMORY CONTROLLER, AND NONVOLATILE MEMORY SYSTEM INCLUDING THEM - An operating method of a nonvolatile memory system includes receiving a read request for at least one page from a host. Upon receiving the read request, read voltages are adjusted using a read history table to perform a first read operation in which data stored at the nonvolatile memory is read. An optimal read voltage set is detected when data read according to the first read operation includes an uncorrectable error, and a second read operation is performed in which the stored data is read based on the detected optimal read voltage set. The read history table is updated based on a reliability parameter indicating a characteristic of the nonvolatile memory, a characteristic of the data at the first or second read operation, the optimal read voltage, or the read history table. | 05-12-2016 |
20160139812 | HOT-COLD DATA SEPARATION METHOD IN FLASH TRANSLATION LAYER - A method of data separation includes receiving a host write command operation identifying temperature of data contained in memory blocks during the host write command operation, selecting a victim block of the memory blocks based on the identified temperature, moving data from the victim block to a destination block, and assigning a sequence number to the destination block when the destination block is full. | 05-19-2016 |
20160139813 | RE-BUILDING MAPPING INFORMATION FOR MEMORY DEVICES - Devices and methods storing user data along with a plurality of addresses corresponding to physical pages storing valid data corresponding to a logical data block are useful in re-building mapping information for the logical data block. | 05-19-2016 |
20160139814 | CACHE MEMORY DEVICE AND DATA PROCESSING METHOD OF THE DEVICE - A cache memory device is provided. The cache memory device includes a memory including a first cache memory region and a second cache memory region, and a control block. The control block determines a type of data to be received. The control block also performs at least one of transmitting a head of received data to a first cache memory region, transmitting a body of the received data to a second cache memory region and transmitting a tail of the received data to the first cache memory region based on the type of the data to be received. | 05-19-2016 |
20160139821 | TIER BASED DATA FILE MANAGEMENT - A hierarchal storage management method is provided. The method includes detecting a first portion of a first file being deleted from a hybrid storage device including a hard disk drive (HDD) memory device, a solid state drive (SSD) memory device, and an archival storage memory device. A first set of memory blocks associated with the first portion of the first file is identified. The first set of memory blocks are determined to reside on the SSD memory device. In response, the first set of memory blocks are transferred from the SSD memory device to a first portion of the hybrid storage device. | 05-19-2016 |
20160139822 | MEMORY SYSTEM - According to one embodiment, there is provided a memory system including a nonvolatile memory, a host interface, and a controller. The host interface is configured to receive a first read command including a logical address to access the nonvolatile memory from a host system. The controller is configured to, when a size of read data requested in the first read command matches a predetermined data size, execute a process according to a second read command including a logical address sequential to the logical address included in the first read command before the host interface receives the second read command. | 05-19-2016 |
20160139826 | Memory Wear Leveling - Systems and methods for intra-sector re-ordered wear leveling include: detecting, in a memory device, a high wear sub-sector having a high wear level, the sub-sector residing in a first sector; determining a second sector of the memory device having a low wear level; swapping the first sector with the second sector; and re-ordering a position of at least one sub-sector of the first sector, the second sector, or both. | 05-19-2016 |
20160139827 | DATA RANDOMIZATION FOR FLASH MEMORY - Data words written to an SSD device, or other device or output data stream, may be randomized using a seed based on physical addressing information, such as a page address, column address, and a cycle count for the page address. This enables the storage and de-randomization of variable length data blocks stored at random locations within a page without requiring storage of additional data, which would make recovery impossible if lost in prior approaches. The page address, column address, and block address are physical attributes of the storage location for the data word and do not need to be saved and therefore will not be lost making recovery of the seed always possible. The cycle count can be saved and, if lost, limited trials with range of cycle counts can be exercised to de-randomize the data word and decoding may be used to determine whether descrambling was successful. | 05-19-2016 |
20160139828 | INDEPENDENT SET/RESET PROGRAMMING SCHEME - Methods for operating a non-volatile memory that includes a plurality of memory arrays in which each memory array of the plurality of memory arrays may independently perform a SET operation, a RESET operation, or a read operation are described. The ability to independently SET or RESET memory arrays allows a SET operation to be performed on a first set of memory cells within a first memory array at the same time as a RESET operation is performed on a second set of memory cells within a second memory array. In some cases, the first memory array may be associated with a first memory bay and the second memory array may be associated with a second memory bay. Each memory bay may include a memory array, read/write circuits, and control circuitry for determining memory cell groupings and programming memory cells within the memory array based on the memory cell groupings. | 05-19-2016 |
20160139832 | MEMORY DEVICE, CONTROL METHOD FOR THE MEMORY DEVICE, AND CONTROLLER - During normal power operation, an erased free block is prepared in nonvolatile memory so that at least one erased free block is continuously available as a standby block. If a power failure occurs, volatile data and its address conversion information are written into the standby block in the nonvolatile memory. | 05-19-2016 |
20160139847 | MEMORY DEVICE AND STORAGE SYSTEM HAVING THE SAME - A memory device includes a nonvolatile memory and a memory controller. The memory controller is configured to receive an access command with respect to a cluster of the nonvolatile memory, the access command including a size of the cluster and a logical address corresponding to a part of the cluster, translate the logical address to a physical address in the nonvolatile memory, by referring to a table storing physical addresses corresponding to part of logical addresses of the nonvolatile memory, identify all physical addresses corresponding to the cluster, based on the size of the cluster, the translated physical address, and an algorithm that generates a sequence for accessing the nonvolatile memory, and access the cluster of the nonvolatile memory in accordance with the identified physical addresses. | 05-19-2016 |
20160139853 | DYNAMIC RAM SHARING IN SOFTWARE-DEFINED TDD COMMUNICATION - Dynamic sharing of RAM in a software-defined communication system includes storing program code in a flash memory, categorizing parts of the code into groups of transmit categories according to when a part of the code needs to be copied into a section of a RAM and then executed during a first state of a TX state machine and according to how another part of the code can be later fit into the same section and then executed during a second state. Similarly, parts of the code are categorized into groups of receive categories according to when a part of the code needs to be copied into a section of RAM and then executed during a first state of a RX state machine and according to how another part of the code can be later fit into that section and then executed during a second state of the RX state machine, to reduce the amount of RAM without sacrificing speed performance. | 05-19-2016 |
20160140041 | ELECTRONIC SYSTEM WITH PARTITIONING MECHANISM AND METHOD OF OPERATION THEREOF - An electronic system includes: an interface block of a storage device configured to process system information from a system device; a memory block of the storage device, coupled to the interface block, partitioned by the interface block configured to process the system information for partitioning the memory block; and a storage block of a storage device, coupled to the memory block, configured to access a data block of the storage block provided to the system device. | 05-19-2016 |
20160141029 | HEALTH DATA ASSOCIATED WITH A RESISTANCE-BASED MEMORY - A method of fabricating a resistance-based memory includes initiating formation of a conductive path through a storage element of the resistance-based memory. The method further includes recording data of one or more parameters associated with the formation of the conductive path. | 05-19-2016 |
20160141031 | NON-VOLATILE REGISTER FILE INCLUDING MEMORY CELLS HAVING CONDUCTIVE OXIDE MEMORY ELEMENT - Some embodiments include apparatuses and methods having a memory element included in a non-volatile memory cell, a transistor, an access line coupled to a gate to the transistor, a first conductive line, and a second conductive line. The memory element can include a conductive oxide material located over a substrate and between the first and second conductive lines. The memory element includes a portion coupled to a drain of the transistor and another portion coupled to the second conductive line. The first conductive line is coupled to a source of the transistor and can be located between the access line and the memory element. The access line has a length extending in a first direction and can be located between the substrate and the memory element. The first and second conductive lines have lengths extending in a second direction. | 05-19-2016 |
20160141036 | NONVOLATILE MEMORY AND RELATED REPROGRAMMING METHOD - A method of reprogramming a nonvolatile memory device, comprising setting up bit lines of selected memory cells according to logic values of first and second latches of a page buffer connected to the bit lines, supplying a program pulse to the selected memory cells, performing a program verify operation on the selected memory cells using the first and second latches, and performing a predictive program operation on the selected memory cells according to a result of the program verify operation. In the predictive program operation, bit lines of the selected memory cells are setup according to a logic value of a third latch of the page buffer that corresponds to each of the selected memory cells. | 05-19-2016 |
20160142910 | STORAGE DEVICE WITH SRWC (SHORT-RANGE WIRELESS COMMUNICATION) DEVICE TAG AND METHOD FOR ACCESSING STORAGE DEVICE - A short-range wireless communication (SRWC) mobile storage device includes a portable storage device and a SRWC device tag. The SRWC device tag has a non-volatile memory for storing an access-control setting information. If the access-control setting information has already been set with required parameters and when the portable storage device with the SRWC device tag is connected to a master equipment, the portable storage device is automatically switched to a secured private zone for the master equipment to access. | 05-19-2016 |
20160147443 | Caching Policies for Solid State Disks - Aspects of the disclosure provide for caching policies for solid state drives. A method of the disclosure includes receiving a request to perform a write operation of a first size; determining, by a processing device, a threshold of input/output I/O size in view of an average bandwidth of a solid state drive (SSD) and information related to I/O operations performed by at least one of the SSD or a hard disk drive (HDD); comparing the first size with the threshold of I/O size; and determining, by the processing device, whether the write operation is to be performed on the SSD or on the HDD in view of the comparison. | 05-26-2016 |
20160147444 | PARALLEL DATA STORAGE IN GROUPS OF MEMORY BLOCKS HAVING SIMILAR PERFORMANCE CHARACTERISTICS - A method for data storage includes, in a memory that includes multiple memory blocks, assessing a performance characteristic of the multiple memory blocks. At least some of the memory blocks are grouped into groups using a grouping criterion that groups together the memory blocks based on similarity in the assessed performance characteristic. Data is stored in the memory by applying parallel memory access operations in the groups of the memory blocks. | 05-26-2016 |
20160147446 | SOLID STATE DRIVE (SSD) MEMORY CACHE OCCUPANCY PREDICTION - Embodiments of the inventive concept include a solid state drive (SSD) shared array memory cache system including memory cache occupancy prediction. The system can include multiple SSD modules each including a non-volatile memory section, a cache, and a prediction agent generator logic section. The system can further include a host agent including an occupancy prediction logic section that can receive prediction agents from the prediction agent generator logic section of each of the SSD modules, and predict content occupancy of the cache based at least on the prediction agents. A method for predicting SSD memory cache occupancy can include processing write requests, predicting content occupancy of an SSD's cache, determining whether an address in the cache is probably logically contiguous to the logical memory address, re-directing at least one write request, and coalescing multiple write requests including the re-directed write request into a single I/O for storage on the non-volatile memory of the SSD. | 05-26-2016 |
20160147452 | STORAGE DEVICE AND OPERATING METHOD OF STORAGE DEVICE - An operating method of a storage device which includes a nonvolatile memory and a memory controller configured to control the nonvolatile memory, may include tracking a clock signal; entering a vendor mode of the storage device when the clock signal corresponds to a vendor pattern; and maintaining a normal mode of the storage device when the clock signal does not correspond to the vendor pattern, wherein, in the normal mode, a command received from an external host device is executed according to a first rule, and wherein, in the vendor mode, the command received from the external host device is executed according to a second rule different from the first rule. | 05-26-2016 |
20160147455 | MEMORY SYSTEM WITH SELECTIVE ACCESS TO FIRST AND SECOND MEMORIES - A memory system includes a nonvolatile memory having a plurality of nonvolatile memory chips incorporated therein, a control circuit that controls the nonvolatile memory, an MPU that controls the control circuit, and an interface circuit that communicates with a host, all of which are mounted on a board of the memory system, and the memory system further includes a bus switch that switches connection of a signal line between the control circuit and the nonvolatile memory chips. | 05-26-2016 |
20160147464 | MEMORY ORPRATING METHOD AND MEMORY DEVICE USING THE SAME - An operating method for a memory, the memory comprising at least one memory block including a plurality of first pages and a plurality of second pages corresponding to the first pages, the operating method including the following steps: determining whether a target first page of the first pages is valid, wherein the target first page is corresponding to a target second page of the second pages; if the target first page is valid, performing first type programming on the target second page; if the target first page is invalid, performing second type programming on the target second page. | 05-26-2016 |
20160147467 | RELIABLE WEAR-LEVELING FOR NON-VOLATILE MEMORY AND METHOD THEREFOR - In one form, a data processor comprises a memory accessing agent and a memory controller. The memory accessing agent selectively initiates read accesses to and write accesses from a memory. The memory controller is coupled to the memory accessing agent and is adapted to be coupled to the memory and to access the memory using a start-gap wear-leveling algorithm. The memory controller is adapted to maintain a metadata log in a region of the memory and to store in the metadata log a start address and a gap address used in the start-gap wear-leveling algorithm, and upon initialization to access the metadata log to retrieve an initial start address and an initial gap address for use in the start-gap wear-leveling algorithm. In another form, a memory module may comprise a memory buffer including such a memory controller. | 05-26-2016 |
20160147473 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a nonvolatile memory, a volatile memory, and a controller. The controller is configured to transition a part of the volatile memory to a self-refresh mode when a request for stopping supplying of power to the nonvolatile memory is received. | 05-26-2016 |
20160147482 | STORAGE DEVICE INCLUDING NONVOLATILE MEMORY DEVICE AND METHOD OF PROGRAMMING THE SAME - According to example embodiments, a storage device in accordance includes a nonvolatile memory device and a memory controller. The nonvolatile memory device includes memory blocks divided into a buffer region and a main region. The memory controller is configured to control the nonvolatile memory device to perform a buffer program operation that includes storing data provided from the outside in the buffer region, to perform a main program operation that includes storing data provided from the outside in the main region, and to perform a closing program operation that includes writing data stored in the buffer region in the main region such the that at least part of the data stored in the buffer region is written to open pages of a memory block including a page programmed last in the main program operation. | 05-26-2016 |
20160147651 | Data Integrity Enhancement to Protect Against Returning Old Versions of Data - Systems, methods and/or devices are used to enhance data integrity to protect against returning old versions of data. In one aspect, a method includes (1) receiving a write request from a host that specifies write data for a set of logical block addresses, (2) mapping, using a mapping table, the set of logical block addresses to a set of physical addresses, where the mapping table includes a plurality of subsets, and (3) performing operations for each subset of the mapping table that includes at least one entry corresponding to a logical block specified by the set of logical block addresses, including: (a) generating metadata for the subset, the metadata including a version number for the subset, (b) calculating a Cyclic Redundancy Check (CRC) checksum for the subset, and (c) storing the version number for the subset and the CRC checksum for the subset in a version data structure. | 05-26-2016 |
20160147652 | DATA STORAGE SYSTEM AND CONTROL METHOD THEREOF - Degradation in processing capability due to copying during garbage collection is reduced. A data storage system includes a memory unit provided with a memory, into which data are written in units of pages, and a memory controller that controls writing of data to the memory; and a controller that indicates, to the memory controller, a logical page address to which data are to be written. The memory controller determines a target block that is a block to be erased when garbage collection is next performed and provides the controller with information on a logical page address corresponding to a physical page address of a valid page in the target block. The controller instructs the memory controller to write data to the logical page address received from the memory controller. | 05-26-2016 |
20160148692 | PAGE BUFFER CIRCUIT AND OPERATING METHOD OF SAME - A page buffer circuit includes a plurality of page buffers including a first page buffer. The first page buffer is configured to load input data of the first page buffer, and input data of at least one neighboring page buffer. The first page buffer is also configured to apply a bias corresponding to the input data of the first page buffer, and the input data of the at least one neighboring page buffer to a bit line. | 05-26-2016 |
20160154594 | METHOD FOR MANAGING ADDRESS MAP FOR FAST OPEN OPERATION AND MEMORY SYSTEM | 06-02-2016 |
20160154598 | HIGH-PERFORMANCE SAS TARGET | 06-02-2016 |
20160154607 | METHOD AND APPARATUS FOR MEMORY MANAGEMENT | 06-02-2016 |
20160154610 | USE OF FLASH CACHE TO IMPROVE TIERED MIGRATION PERFORMANCE | 06-02-2016 |
20160154732 | SEMICONDUCTOR STORAGE DEVICE AND CONTROL METHOD THEREOF | 06-02-2016 |
20160154733 | METHOD OF OPERATING SOLID STATE DRIVE | 06-02-2016 |
20160162185 | DATA PROGRAMMING FOR A MEMORY HAVING A THREE-DIMENSIONAL MEMORY CONFIGURATION - A data storage device includes a memory die. The memory die includes a memory having a three-dimensional (3D) memory configuration. A method includes sensing information stored at a region of the memory to generate sensed information. The method further includes adjusting one or more write parameters associated with the region in response to an error rate associated with the sensed information satisfying an error threshold. | 06-09-2016 |
20160162186 | Re-Ordering NAND Flash Commands for Optimal Throughput and Providing a Specified Quality-of-Service - Techniques are presented to help keep all possible independent-NAND-access-channels busy even when the traffic from the host is not arriving evenly. Incoming commands from a flash translation layer for a device are directed by a command issuer to separate queues for admin (device management), reads, writes, erases and, in the exemplary embodiment, high-priority reads. A queue-picker can then switch between various command queues, where individual read, write and erase queues for a device can be further divided into die-based queues. A complementary set of techniques provide a certain level of performance, termed as Quality-Of-Service (QoS), by implementing QoS in terms of physical addresses. The flash translation layer, which has access to information on the physical addresses typically hidden from the host, is used for optimizing and guaranteeing input/output (I/O) access times | 06-09-2016 |
20160162187 | Storage System And Method For Processing Writing Data Of Storage System - A method of processing write-data in a storage system includes an operation of storing write-data related to a write-request in a data I/O queue when the write-request is generated by a file system, an operation of classifying data stored in the data I/O queue into a full storage logical page and a partial storage logical page, an operation of transmitting data related to the full storage logical page to a storage device in response to the write-request, and An operation of leaving data related to the partial storage logical page in the data I/O queue in response to the write-request. | 06-09-2016 |
20160162196 | PAGE RETIREMENT IN A NAND FLASH MEMORY SYSTEM - In a data storage system including a non-volatile random access memory (NVRAM) array, a page is a smallest granularity of the NVRAM array that can be accessed by read and write operations, and a memory block containing multiple pages is a smallest granularity of the NVRAM array that can be erased. Data are stored in the NVRAM array in page stripes distributed across multiple memory blocks. In response to detection of an error in a particular page of a particular block of the NVRAM array, only the particular page of the particular block is retired, such that at least two of the multiple memory blocks across which a particular one of the page stripes is distributed include differing numbers of active (non-retired) pages. | 06-09-2016 |
20160162201 | EMMC FUNCTIONALITY EXPANDER - An eMMC functionality expander, and methods there for, are provided herein. For example, provided herein is a device comprising: a first processor; a multimedia card memory (“eMMC”); a second processor; a client eMMC interface between the second processor and the first processor; a host eMMC interface between the second processor and the eMMC; and an NVRAM (“Non-Volatile Random Access Memory”) in communication with the second processor, the second processor configured to manage data storage to the eMMC and the NVRAM so that the eMMC and the NVRAM appears as a single storage device to the first processor. The NVRAM can also be used to provide communication between the first processor and a slave processor. Furthermore, the NVRAM can store boot data, and the like, to decrease the boot times of the processors and the boot time of the device. | 06-09-2016 |
20160162202 | PROGRAMMABLE, HIGH PERFORMANCE SOLID STATE DRIVE CONTROLLER ARCHITECTURE - Systems and methods for designing a programmable solid state drive (SSD) controller and a non-volatile memory apparatus are provided. The disclosed systems and methods utilize data structures, termed “Superbufs” for organizing internal activities in an SSD controller. Superbufs can be used for providing control flow services, such as, sequencing, synchronization, completion, and interrupt generation, as well as data flow services, for example, data transfer, data transformation, and data distribution. | 06-09-2016 |
20160162203 | Techniques to Manage Multiple Sequential Write Streams to a Solid State Drive - Examples may include techniques to manage multiple sequential write streams to a solid state drive (SSD). Wrap around times for each sequential write stream may be determined. Respective wrap around times for each sequential write stream may be changed for at least some of the sequential write streams to cause the multiple sequential write streams to have matching wrap around times. | 06-09-2016 |
20160162205 | DETERMINING ADJUSTMENTS TO THE SPARE SPACE IN A STORAGE DEVICE UNAVAILABLE TO A USER BASED ON A CURRENT CONSUMPTION PROFILE OF A STORAGE DEVICE - Provided are a computer program product, system and method for determining adjustments to the spare space in a storage device unavailable to a user based on a current consumption profile of a storage device. A current write amplification is based on storage writes to a media at a storage device and host writes from a host to the storage device. An adjustment to the current write amplification is determined to produce an adjusted write amplification based on an estimated lifespan of the storage device, a maximum storage writes for the storage device, and the storage writes at the storage device since the storage device was powered-on. A determination is made to an adjustment to spare space based on the adjusted write amplification. The spare space and the free space available to the user are reconfigured to adjust the spare space by the determined adjustment to the spare space. | 06-09-2016 |
20160162208 | DATA REALLOCATION UPON DETECTION OF ERRORS - A device includes one or more data storage media having a main storage area. The device also includes a non-volatile cache memory and a controller. The controller stores a plurality of data packets into a plurality of physical locations in the main storage area of the one or more data storage media. Each of the plurality of data packets is associated with a different logical block address (LBA), and each of the plurality of physical locations is associated with a different physical location address. The controller generates mapping information that links the different LBAs associated with the different data packets to the different physical location addresses associated with the different physical locations. Upon detecting a soft error when reading at least one data packet of the plurality of data packets stored in at least one physical location of the plurality of physical locations, the controller relocates the at least one data packet associated with the soft error to at least one physical location of a non-volatile cache memory. The controller also makes an indication that the at least one physical location of the plurality of physical locations is a suspect location. The controller updates the mapping information to reflect the relocation of the at least one data packet associated with the soft error to the at least one physical location in the non-volatile cache memory. | 06-09-2016 |
20160162211 | Efficient Reduction of Read Disturb Errors - Methods and apparatuses for reduction of Read Disturb errors in a NAND FLASH memory system comprise a controller configured to organize FLASH memory devices into blocks, each block having a plurality of pages, and each page defining an individually addressable physical memory location. The controller is further configured to accumulate a Block READ Count corresponding to the number of times any pages in a first block of pages have been read since the first block was last erased. Once the READ count reaches a predetermined number, the controller responds to subsequent READ requests for pages within the first block by moving data associated with a requested page to a page in a second, different block without moving data associated with other pages in the first block, and modifying a logical-to-physical translation table to associate the moved data with the physical address of the page in the second block. | 06-09-2016 |
20160162212 | NONVOLATILE STORAGE DEVICE AND OPERATING SYSTEM (OS) IMAGE PROGRAM METHOD THEREOF - A nonvolatile storage device in accordance with the inventive concepts includes a nonvolatile memory device comprising a first memory area, a second memory area, and a memory controller. The memory controller includes a first register configured to store reliable mode information, and a second register configured to store operating system (OS) image information. The memory controller is configured to receive a command from a host based on the reliable mode information; determine whether the command is a write request for an OS image and whether OS image information accompanying the command matches the OS image information stored in the second register; write the OS image to the first memory area if the OS image information accompanying the command matches the OS image information stored in the second register, and block data migration of the OS image from the first memory area to the second memory area. | 06-09-2016 |
20160162215 | META PLANE OPERATIONS FOR A STORAGE DEVICE - A method of operating a data storage device having a memory includes scheduling a first operation to be performed at one or more memory dies of a first meta plane of a plurality of meta planes of the memory. The first operation is to be performed during a particular time period. The method also includes determining that performance of the first operation consumes less than a threshold amount of power. The method further includes scheduling a second operation to be performed at one or more memory dies of a second meta plane of the plurality of meta planes, or at one of the dies in the same meta plane, during the particular time period and performing the first operation concurrently with the second operation. A peak amount of power corresponding to concurrent execution of the first operation and the second operation is less than the threshold amount of power. | 06-09-2016 |
20160162219 | Memory System and Method for Selecting Memory Dies to Perform Memory Access Operations in Based on Memory Die Temperatures - A memory system and method are provided for selecting memory dies for memory access operations based on memory die temperatures. The memory system has a plurality of memory dies, where each memory die has its own temperature sensor. In one embodiment, the memory system selects which memory dies to perform memory access operations in based on the temperatures of the memory dies. In another embodiment, a controller of the memory system selects which memory dies to thermal throttle memory access operations in based on the detected temperatures. In yet another embodiment, a temperature-aware media management layer module of the memory l system routes a memory access operation from a first memory die to a second memory die based on the temperatures of the memory dies. | 06-09-2016 |
20160162403 | PROGRAMMING NON-VOLATILE MEMORY USING A RELAXED DWELL TIME - In at least one embodiment, a data storage system includes a non-volatile memory array including a plurality of blocks of physical memory, each including multiple pages. The data storage system further includes a controller that maintains a data structure identifying blocks of physical memory in the memory array that currently do not store valid data. The controller, responsive to receipt of a write input/output operation (IOP) specifying an address and write data, selects a particular block from among the blocks identified in the data structure prior to a dwell time threshold for the particular block being satisfied, programs a page within the selected block with the write data, and associates the address with the selected block. | 06-09-2016 |
20160162420 | INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, AND RECORDING MEDIUM - A deletion instruction of data stored in a nonvolatile memory is input, a determination is made whether the nonvolatile memory has reached an end of its rewrite operating life in accordance with the input deletion instruction, an instruction for setting a password to the nonvolatile memory is accepted when it is determined that the nonvolatile memory has reached the end of its rewrite operating life, and the password is set to the nonvolatile memory in accordance with the accepted instruction. | 06-09-2016 |
20160170641 | GRADUAL CONTEXT SAVING IN A DATA STORAGE DEVICE | 06-16-2016 |
20160170642 | MEMORY SYSTEM | 06-16-2016 |
20160170643 | MEMORY SYSTEM AND DRIVING METHOD THEREOF | 06-16-2016 |
20160170646 | IMPLEMENTING ENHANCED PERFORMANCE FLASH MEMORY DEVICES | 06-16-2016 |
20160170647 | MEMORY CELL PROGRAMMING METHOD, MEMORY CONTROL CIRCUIT UNIT AND MEMORY STORAGE APPARATUS | 06-16-2016 |
20160170656 | IMPLEMENTING ENHANCED PERFORMANCE FLASH MEMORY DEVICES | 06-16-2016 |
20160170664 | SEMICONDUCTOR STORAGE DEVICE HAVING NONVOLATILE SEMICONDUCTOR MEMORY | 06-16-2016 |
20160170671 | DATA STORAGE DEVICE AND DATA WRITING METHOD THEREOF | 06-16-2016 |
20160170672 | NAND FLASH RELIABILITY WITH RANK MODULATION | 06-16-2016 |
20160170674 | OPTIMIZED MANAGEMENT OF OPERATION DATA IN A SOLID-STATE MEMORY | 06-16-2016 |
20160170675 | Superconducting Fiber and Efficient Cryogenic Cooling | 06-16-2016 |
20160170676 | MEMORY DEVICE RESPONDING TO DEVICE COMMANDS FOR OPERATIONAL CONTROLS | 06-16-2016 |
20160170682 | TAG-BASED WEAR LEVELING FOR A DATA STORAGE DEVICE | 06-16-2016 |
20160170683 | Method, Apparatus, and Controller for Managing Storage Array | 06-16-2016 |
20160170684 | FLASH MEMORIES USING MINIMUM PUSH UP, MULTI-CELL AND MULTI-PERMUTATION SCHEMES FOR DATA STORAGE | 06-16-2016 |
20160170869 | SYSTEMS AND METHODS FOR IN-PLACE REORGANIZATION OF DEVICE STORAGE | 06-16-2016 |
20160170870 | NON-VOLATILE MEMORY SYSTEM HAVING AN INCREASED EFFECTIVE NUMBER OF SUPPORTED HEAT LEVELS | 06-16-2016 |
20160170871 | MODEL BASED CONFIGURATION PARAMETER MANAGEMENT | 06-16-2016 |
20160170872 | OPERATING METHOD OF STORAGE DEVICE | 06-16-2016 |
20160170874 | METHODS AND SYSTEMS FOR PRESERVING BLOCKS THAT ARE NEITHER OBSOLETE NOR COLD | 06-16-2016 |
20160170891 | DISK APPARATUS AND CONTROL METHOD | 06-16-2016 |
20160170898 | CONTROLLER INCLUDING MAP TABLE, MEMORY SYSTEM INCLUDING SEMICONDUCTOR MEMORY DEVICE, AND METHOD OF OPERATING THE SAME | 06-16-2016 |
20160170903 | INFORMATION PROCESSING DEVICE, NON-TRANSITORY COMPUTER READABLE RECORDING MEDIUM, AND INFORMATION PROCESSING SYSTEM | 06-16-2016 |
20160179371 | SYSTEM AND METHOD FOR MANAGING DATA IN A MEMORY DEVICE | 06-23-2016 |
20160179372 | SYSTEM AND METHOD FOR ADAPTIVE MEMORY LAYERS IN A MEMORY DEVICE | 06-23-2016 |
20160179376 | METHOD AND APPARATUS FOR IMPROVING READ PERFORMANCE OF A SOLID STATE DRIVE | 06-23-2016 |
20160179378 | DELAYED TRIM OF MANAGED NAND FLASH MEMORY IN COMPUTING DEVICES | 06-23-2016 |
20160179379 | SYSTEM AND METHOD FOR DATA MANAGEMENT ACROSS VOLATILE AND NON-VOLATILE STORAGE TECHNOLOGIES | 06-23-2016 |
20160179380 | SYSTEM MANAGING A PLURALITY OF FLASH MEMORY DEVICES | 06-23-2016 |
20160179381 | REDUCTION OF INTERMINGLING OF INPUT AND OUTPUT OPERATIONS IN SOLID STATE DRIVES | 06-23-2016 |
20160179386 | ADAPTIVE GARBAGE COLLECTION | 06-23-2016 |
20160179388 | METHOD AND APPARATUS FOR PROVIDING PROGRAMMABLE NVM INTERFACE USING SEQUENCERS | 06-23-2016 |
20160179392 | NON-VOLATILE MEMORY DEVICE | 06-23-2016 |
20160179395 | COOPERATIVE DATA DEDUPLICATION IN A SOLID STATE STORAGE ARRAY | 06-23-2016 |
20160179398 | Two-Level Hierarchical Log Structured Array Architecture Using Coordinated Garbage Collection for Flash Arrays | 06-23-2016 |
20160179399 | System and Method for Selecting Blocks for Garbage Collection Based on Block Health | 06-23-2016 |
20160179401 | MEMORY SYSTEM AND THE OPERATION METHOD THEREOF | 06-23-2016 |
20160179402 | MEMORY SYSTEM | 06-23-2016 |
20160179404 | EFFICIENT SCHEDULING OF INPUT/OUTPUT REQUESTS TO REDUCE LATENCY AND MAXIMIZE THROUGHPUT IN A FLASH STORAGE DEVICE | 06-23-2016 |
20160179406 | DYNAMIC PROGRAMMING ADJUSTMENTS BASED ON MEMORY WEAR, HEALTH, AND ENDURANCE | 06-23-2016 |
20160179407 | TRADE-OFF ADJUSTMENTS OF MEMORY PARAMETERS BASED ON MEMORY WEAR OR DATA RETENTION | 06-23-2016 |
20160179412 | ENDURANCE ENHANCEMENT SCHEME USING MEMORY RE-EVALUATION | 06-23-2016 |
20160179413 | HYBRID MEMORY HAVING ONE-BIT SYNCHRONIZATION FUNCTION AND BOOTING METHOD AND BOOTING SYSTEM USING THE SAME | 06-23-2016 |
20160179422 | METHOD OF PERFORMING GARBAGE COLLECTION AND RAID STORAGE SYSTEM ADOPTING THE SAME | 06-23-2016 |
20160179425 | CHECKPOINTING MODULE AND METHOD FOR STORING CHECKPOINTS | 06-23-2016 |
20160179426 | PROCESSOR SYSTEM AND CONTROL METHOD THEREOF | 06-23-2016 |
20160179428 | DYNAMIC PROGRAMMING ADJUSTMENTS IN MEMORY FOR NON-CRITICAL OR LOW POWER MODE TASKS | 06-23-2016 |
20160179431 | INDIVIDUAL IDENTIFICATION DEVICE, STORAGE DEVICE, INDIVIDUAL IDENTIFICATION SYSTEM, METHOD OF INDIVIDUAL IDENTIFICATION, AND PROGRAM PRODUCT | 06-23-2016 |
20160179433 | De-Duplication as Part of Other Routinely Performed Processes | 06-23-2016 |
20160179625 | DATA STORAGE DEVICE AND OPERATING METHOD THEREOF | 06-23-2016 |
20160179663 | SYSTEMS AND METHODS FOR GENERATING A UNIQUE DEVICE ID | 06-23-2016 |
20160179664 | PAGE-LEVEL HEALTH EQUALIZATION | 06-23-2016 |
20160179678 | NON-VOLATILE MEMORY CONTROLLER CACHE ARCHITECTURE WITH SUPPORT FOR SEPARATION OF DATA STREAMS | 06-23-2016 |
20160179683 | SSD CACHING SYSTEM FOR HYBRID STORAGE | 06-23-2016 |
20160179684 | NONVOLATILE MEMORY DEVICE AND OPERATING METHOD THEREOF | 06-23-2016 |
20160180898 | MEMORY CONTROLLER AND MEMORY SYSTEM INCLUDING THE SAME | 06-23-2016 |
20160188206 | Non-Volatile Memory Systems Utilizing Storage Address Tables - Non-volatile memory systems utilizing storage address tables are disclosed. A non-volatile memory system may include a non-volatile memory, a memory die command manager in communication with the memory, and a command manager in communication with the memory die command manager. The memory die command manager is configured to identify a free die of the memory to store data, where the free die of the memory is identified independent of a host logical block address associated with the data; store the data at a physical block address at the free die; and generate an entry in a first address table, the first address table associating the physical block address with a virtual logical block address. The command manager is configured to generate an entry in a second address table, the second address table associating the virtual logical block address with a host logical block address received with the host write command. | 06-30-2016 |
20160188208 | NONVOLATILE MEMORY SYSTEM AND OPERATION METHOD OF THE SAME - An operation method of a nonvolatile memory system including a nonvolatile memory and a memory controller configured to control the nonvolatile memory includes receiving a write command including size information indicating a size of write data from an external device; determining whether or not garbage collection is being executed; executing the garbage collection for a first period of time based on the size information according to a result of the determination; and programming the write data into the nonvolatile memory after executing the garbage collection. | 06-30-2016 |
20160188213 | MEMORY MANAGEMENT METHOD, MEMORY STORAGE DEVICE AND MEMORY CONTROLLING CIRCUIT UNIT - A memory management method, a memory storage device and a memory controlling circuit unit are provided. The method includes: programming data into a plurality of memory cells of a rewritable non-volatile memory module; determining whether a storage state of the data conforms with a first condition or a second condition based on a default bias range and a threshold voltage distribution of the memory cells storing the data; performing a first operation if the storage state of the data conforms with the first condition; and performing a second operation if the storage state of the data conforms with the second condition. Accordingly, the probability of misidentifying the valid data as the invalid data may be reduced. | 06-30-2016 |
20160188215 | INFORMATION PROCESSING APPARATUS, MEMORY CONTROL METHOD FOR INFORMATION PROCESSING APPARATUS, AND PROGRAM - In an information processing apparatus including a first memory storing data, whether the first memory is in a state where the stored data is readable and data is unwritable is determined. When it is determined that the first memory is in the state, whether particular data is stored in the first memory is determined. When it is determined that the particular data is stored in the first memory, whether a second memory is connected to the information processing apparatus is determined. When it is determined that the second memory is connected, the particular data is read from the first memory and is written into the second memory. | 06-30-2016 |
20160188219 | SYSTEMS AND METHODS FOR STORAGE RECOVERY - Storage divisions are selected for garbage collection by use of a first selection criterion that is based on an amount of storage capacity freed by reclaiming the respective storage divisions. The first selection criterion may be overridden by a second, different selection criterion in response to determining that a wear variance of the storage divisions exceeds a threshold. The second selection criterion may select a storage division to reclaim based on a wear-level of the storage division. Overrides of the first selection criterion may be limited to a particular override frequency and/or period. The first selection criterion may comprise a logarithmic comparison of the amount of invalid data within the storage divisions. The amount of invalid data in a storage division may be calculated in terms of recovery blocks, having a size that exceeds the size of the physical storage locations within the storage divisions. | 06-30-2016 |
20160188220 | Memory system and information processing system - According to one embodiment, a memory system includes a nonvolatile memory, and a controller configured to control the nonvolatile memory. The controller includes an access controller configured to control access to the nonvolatile memory, based on a first request which is issued from an outside, and a processor configured to execute a background process for the nonvolatile memory, based on a second request which is issued from the outside before the first request is issued. | 06-30-2016 |
20160188221 | SYSTEMS AND METHODS FOR MANAGING STORAGE ENDURANCE - Storage divisions of a non-volatile storage medium may have a writable state and an unwritable state. Storage divisions may be reclaimed by, inter alia, resetting the storage division from an unwritable state to a writable state. Writable storage divisions may be used to service incoming storage requests. If no writable storage divisions are available, requests may stall. One or more storage divisions may be held in a writable state to avoid stall conditions. This, however, may increase the erase dwell time of the storage divisions, which can result in increased wear and reduce the usable life of the storage device. Storage divisions may be prepared for use such that the storage divisions are transitioned to a writable state such that erase dwell time of the storage divisions is reduced, and the storage divisions are available as needed to service incoming requests. | 06-30-2016 |
20160188223 | PROMOTING CONSISTENT RESPONSE TIMES IN A DATA STORAGE SYSTEM HAVING MULTIPLE DATA RETRIEVAL MECHANISMS - A data storage system includes a higher level controller, a lower level controller, and a plurality of storage components including a particular storage component. Data is stored within the data storage system utilizing at least one level of striping across the plurality of storage components. Latencies of input/output operations (IOPs) requesting access to the data stored within the data storage system are monitored. In response to determining that a latency of a read IOP requesting read data stored in the particular storage component exceeds a latency threshold and in absence of a data error, the read IOP is serviced by reconstructing the read data from storage components among the plurality of storage components other than the particular storage component. The lower level controller also provides feedback to the higher level controller to cause the higher level controller to reduce IOPs directed to at least the particular storage component. | 06-30-2016 |
20160188226 | DATA SEGREGATION IN A STORAGE DEVICE - An example method includes providing at least two data storage areas in a memory, providing a first amount of over-provisioning for a first of the at least two data storage areas and a second amount of over-provisioning for a second of the at least two data storage areas, categorizing data based on a characteristic of the data, and storing the data in one of the at least two data storage areas based on the categorization. | 06-30-2016 |
20160188233 | METHOD FOR INTERRUPTING CLEANING PROCEDURE OF FLASH MEMORY - A controller for interfacing between a host and a flash memory is provided. The flash memory includes a plurality of data blocks and a plurality of spare blocks. The controller includes a memory unit and a computation unit. The computation unit is configured to perform a cleaning procedure of the flash memory, wherein whenever the computation unit has finished copying a valid page of a source block in the plurality of data blocks to a spare page of a destination block in the plurality of spare blocks during the cleaning procedure, the computation unit determines whether a request is coming from the host, if so, the computation unit suspends the cleaning procedure and responds to the request from the host, if not, the computation unit continues the cleaning procedure. | 06-30-2016 |
20160188234 | METHOD AND APPARATUS FOR MEMORY MANAGEMENT - One or more circuits of a device may comprise a memory. A first portion of a first block of the memory may store program code and/or program data, a second portion of the first block may store an index associated with a second block of the memory, and a third portion of the first block may store an indication of a write status of the first portion. Each bit of the third portion of the first block may indicate whether an attempt to write data to a corresponding one or more words of the first portion of the first block has failed since the last erase of the corresponding one or more words of the first portion of the first block. Whether data to be written to a particular virtual address is written to the first block or the second block may depend on the write status of the first block and the second block. | 06-30-2016 |
20160188252 | METHOD AND APPARATUS FOR PRESEARCHING STORED DATA - A memory module or a storage device comprises a volatile memory subsystem, a non-volatile memory subsystem, and a controller coupled to the volatile memory subsystem and to the non-volatile memory subsystem. The memory module or storage device further comprises a data selection circuit that pre-search data from the non-volatile memory with respect to one or more search criteria received from a computer system to pre-select data relevant to the one or more search criteria for loading into the volatile memory subsystem. | 06-30-2016 |
20160188254 | LIFECYCLE MANAGEMENT OF SOLID STATE MEMORY ADAPTORS - Embodiments relate to lifecycle management of solid state memory adaptors. Aspects of the invention include monitoring a remaining life of each of a plurality of solid state memory adaptors in a system and creating a log of a wearing of each of the plurality of solid state memory adaptors. Aspects further include transmitting the log to a service element and receiving a supplemental data from the service element and determining a threshold value for each of the plurality of solid state memory adaptors. Based on determining that the remaining life of one of the plurality of solid state memory adaptors is below the threshold value for the one of the plurality of solid state memory adaptors, aspects also include creating a service call to request that the one of the solid state memory adaptors be replaced. | 06-30-2016 |
20160188255 | METHOD AND SYSTEM FOR PREVENTING UNRELIABLE DATA OPERATIONS AT COLD TEMPERATURES - Systems and methods for reducing problems and disadvantages associated with protecting data during cold excursions are provided. A method for preventing unreliable data operations at cold temperatures may include determining whether a first temperature of a solid state drive (SSD) is below a threshold temperature. The method may also include initiating an artificial read/write operation if the first temperature is below the threshold temperature. | 06-30-2016 |
20160188259 | FAST PROGRAMMING MEMORY DEVICE - In an embodiment of a memory device including a matrix of memory cells wherein the memory cells are arranged in a plurality of memory cells strings each one including at least two serially-connected memory cells, groups of at least two memory cells strings being connected to a respective bit line, and wherein said memory cells are adapted to be programmed into at least a first programming state and a second programming state, a method of storing data comprising exploiting a single memory cell for each of the memory cells string for writing the data, wherein said exploiting includes bringing the single memory cell to the second programming state, the remaining memory cells of the string being left in the first programming state. | 06-30-2016 |
20160188414 | FAULT TOLERANT AUTOMATIC DUAL IN-LINE MEMORY MODULE REFRESH - Methods and apparatus to fault tolerant Automatic DIMM (Dual In-line Memory Module) Refresh or ADR are described. In an embodiment, a processor includes non-volatile memory to store data from one or more volatile buffers of the processor. The data from the one or more volatile buffers of the processor are stored into the non-volatile memory in response to occurrence of an event that is to lead to a system reset or shut down. Other embodiments are also disclosed and claimed. | 06-30-2016 |
20160188456 | NVRAM-AWARE DATA PROCESSING SYSTEM - In one form, a computer system includes a central processing unit, a memory controller coupled to the central processing unit and capable of accessing non-volatile random access memory (NVRAM), and an NVRAM-aware operating system. The NVRAM-aware operating system causes the central processing unit to selectively execute selected ones of a plurality of application programs, and is responsive to a predetermined operation to cause the central processing unit to execute a memory persistence procedure using the memory controller to access the NVRAM. | 06-30-2016 |
20160188457 | NON-VOLATILE STATIC RANDOM ACCESS MEMORY (NVSRAM) - A nonvolatile memory device includes a shared port block, a plurality of decoded address signals, a read signal, and a read word line. The shared port block includes a shared port communicatively coupled to a block, the block comprising a plurality of memory cells, wherein the shared port is operable to sense a voltage level at each of the plurality of memory cells. The plurality of decoded address signals are communicatively coupled to the block. Each of the plurality of decoded address signals is operable to enable a corresponding one of the plurality of memory cells. The read signal is communicatively coupled to the shared port. The read signal is operable to enable a read operation associated with the block. The read word line signal is communicatively coupled to the shared port block. The read word line signal is operable to enable the read operation. | 06-30-2016 |
20160188458 | CACHE MEMORY DEVICE AND NON-TRANSITORY COMPUTER READABLE RECORDING MEDIUM - According to one embodiment, a cache memory device includes a nonvolatile cache memory, write unit, determination unit, selection unit, and erase unit. The nonvolatile cache memory includes a plurality of erase unit areas. Each of the erase unit areas includes a plurality of write unit areas. The write unit writes data to the nonvolatile cache memory. The determination unit determines whether the plurality of erase unit areas satisfy an erase condition or not. The selection unit selects an area to be erased from the plurality of erase unit areas when the plurality of erase unit areas satisfy the erase condition. The erase unit erases the data written to the area to be erased. | 06-30-2016 |
20160188459 | MEMORY DEVICE AND NON-TRANSITORY COMPUTER READABLE RECORDING MEDIUM - According to one embodiment, a memory device includes a nonvolatile memory, address translation unit, generation unit, and reception unit. The nonvolatile memory includes erase unit areas. Each of the erase unit areas includes write unit areas. The address translation unit generates address translation information relating a logical address of write data written to the nonvolatile memory to a physical address indicative of a write position of the write data in the nonvolatile memory. The generation unit generates valid/invalid information indicating whether data written to the erase unit areas is valid data or invalid data. The reception unit receives deletion information including a logical address indicative of data to be deleted in the erase unit area. | 06-30-2016 |
20160188460 | INFORMATION PROCESSING DEVICE AND NON-TRANSITORY COMPUTER READABLE RECORDING MEDIUM - According to one embodiment, an information processing device includes a transmission unit and reception unit. The transmission unit transmits write data and a logical address of the write data to a memory device. The memory device includes a plurality of erase unit areas. Each of the erase unit areas includes a plurality of write unit areas. The reception unit receives, from the memory device, area information including data identification information indicative of data written to an erase unit area to be subjected to garbage collection. | 06-30-2016 |
20160188461 | DATA MANAGEMENT APPARATUS AND METHOD - A data management apparatus for reducing the occurrence of garbage collection, and preventing deterioration in the performance of writing data into an SSD. The data management apparatus includes a data management unit which manages key-value data stored in the SSD, and a file management unit which creates a file of a predetermined size in accordance with a request from the data management unit, and manages the created file. The file management unit creates a file having a size of an integral multiple of a block in the SSD, the data management unit requests file management unit to write the key-value data to be stored in the file, and manages a number of the effective key-value data in each file by invalidating pre-update data of the updated key-value data and the deleted key-value data, and requests the file management unit to delete the file no longer storing the effective key-value data. | 06-30-2016 |
20160188463 | POLARITY BASED DATA TRANSFER FUNCTION FOR VOLATILE MEMORY - Apparatus, systems, and methods to implement polarity based data transfer function for volatile memory power reduction are described. The transfer function take into account certain data values, all zeroes in particular, that are common and transforms them to predetermined values that consume less power and are less common. Similarly, these predetermined values are transformed to the common values. | 06-30-2016 |
20160188464 | Method and System for Using Non-Volatile Memory as a Replacement for Volatile Memory - A method and system for using non-volatile memory as a replacement for volatile memory are provided. In one embodiment, a host is in communication with a memory system having volatile memory, a first non-volatile memory, and a second non-volatile memory, wherein the first non-volatile memory has a faster performance and a higher endurance than the second non-volatile memory. The host analyzes data to be stored in the volatile memory to determine if it should instead be stored in the first non-volatile memory. If the data should be stored in the volatile memory, the host stores the data in the volatile memory. If the data should be stored in the first non-volatile memory, the host stores the data in the first non-volatile memory. | 06-30-2016 |
20160188495 | EVENT TRIGGERED ERASURE FOR DATA SECURITY - One aspect of the present description provides for automatically erasing at least a portion of a memory such as a nonvolatile memory, for example, of a device in response to a detected event such as a power shutdown or power-up process, for example. In one embodiment, an on-board erasure assistance device such as an electro-magnet, for example, facilitates sensitive data erasure. In accordance with another aspect of the present description, a satisfactory level of sensitive data erasure may be achieved by resetting a portion of the bits of the sensitive data, instead of resetting all the bits of sensitive data. In one embodiment, the bits which are reset to erase sensitive data may be randomly distributed over a subarray. Other aspects are described herein. | 06-30-2016 |
20160188890 | SECURITY MODE DATA PROTECTION - In one embodiment, a device containing sensitive information may be placed in a data security mode. In such a data security mode, certain activities may trigger the partial or full erasure of the sensitive date before the data can be retrieved by an unauthorized user. In one embodiment, the data security mode may be a “park” mode in which unauthorized physical movement of the device triggers the partial or full erasure of the sensitive data stored in a nonvolatile memory before the data can be retrieved by an unauthorized user. In another aspect of the present description, the earth's magnetic field may be used to detect movement of a device in the park mode, and may be used to power the erasure of sensitive data as the device is moved relative to the earth's magnetic field. Other aspects are described herein. | 06-30-2016 |
20160189785 | DATA SAMPLING CIRCUIT MODULE, DATA SAMPLING METHOD AND MEMORY STORAGE DEVICE - A data sampling circuit module, a data sampling method and a memory storage device are provided. The method includes: receiving a differential signal and generating an input data stream according to the differential signal; sampling a clock signal according to a plurality of turning points of the input data stream and outputting a sampling signal; and outputting a bit data stream corresponding to the input data stream according to the sampling signal. | 06-30-2016 |
20160196062 | MEMORY SYSTEM | 07-07-2016 |
20160196063 | APPARATUS AND METHOD FOR MANAGING BUFFER HAVING THREE STATES ON THE BASIS OF FLASH MEMORY | 07-07-2016 |
20160196075 | STORAGE APPARATUS AND STORAGE CONTROL METHOD | 07-07-2016 |
20160196076 | MEMORY SYSTEM AND METHOD FOR CONTROLLING SAME | 07-07-2016 |
20160196207 | HEAT-BASED KEY-VALUE SLOT ORGANIZATION FOR FLASH-OPTIMIZED DATA PLACEMENT IN MULTI-TIERED STORAGE SYSTEMS | 07-07-2016 |
20160202908 | WRITING METHOD FOR SOLID STATE DRIVE | 07-14-2016 |
20160202909 | I/O SCHEDULING METHOD USING READ PRIORITIZATION TO REDUCE APPLICATION DELAY | 07-14-2016 |
20160202910 | ADDRESSING, INTERLEAVE, WEAR LEVELING, AND INITIALIZATION SCHEMES FOR DIFFERENT CHIP ENABLES AND MEMORY ARRAYS OF DIFFERENT TYPES | 07-14-2016 |
20160202922 | METHOD AND APPARATUS FOR OPTIMIZING THE PERFORMANCE OF A STORAGE SYSTEM | 07-14-2016 |
20160202934 | METHODS OF SYSTEM OPTIMIZATION BY OVER-SAMPLING READ | 07-14-2016 |
20160203075 | STORAGE DEVICE INCLUDING BUFFER AND MAIN MEMORIES, AND USER DEVICE INCLUDING THE SAME | 07-14-2016 |
20160203103 | INTEGRATED FRAMEWORK OF MEMORY STORAGE MODULE AND SENSOR MODULE | 07-14-2016 |
20160253091 | METHODS AND SYSTEMS TO REDUCE SSD IO LATENCY | 09-01-2016 |
20160253095 | HOST READ COMMAND RETURN REORDERING BASED ON TIME ESTIMATION OF FLASH READ COMMAND COMPLETION | 09-01-2016 |
20160253097 | INFORMATION PROCESSING DEVICE THAT EXTENDS SERVICE LIFE OF NON-VOLATILE SEMICONDUCTOR MEMORY AND RECORDING MEDIUM | 09-01-2016 |
20160253099 | SYSTEM AND METHOD INCLUDING THREE DIMENSIONAL NONVOLATILE MEMORY DEVICE AND RANDOM ACCESS MEMORY | 09-01-2016 |
20160253113 | DATA-REFRESH APPARATUS | 09-01-2016 |
20160253123 | NVMM: An Extremely Large, Logically Unified, Sequentially Consistent Main-Memory System | 09-01-2016 |
20160253124 | NONVOLATILE MEMORY DEVICE, OPERATING METHOD THEREOF, AND DATA STORAGE DEVICE INCLUDING THE SAME | 09-01-2016 |
20160253125 | Raided MEMORY SYSTEM | 09-01-2016 |
20160253270 | PROTECTED MEMORY AREA | 09-01-2016 |
20160378337 | SOLID-STATE MASS STORAGE DEVICE AND METHOD FOR PERSISTING VOLATILE DATA TO NON-VOLATILE MEDIA - A mass storage device and method for storing data originally written to a volatile memory with byte level I/O protocol commands to a non-volatile memory using block level I/O protocol commands. The mass storage device includes a host interface for communicating with the host computer system, at least one non-volatile memory, at least one volatile memory, a memory controller configured to accept block level I/O protocol commands from the host computer system to read data from and write data to the non-volatile memory, and additionally accept byte level memory I/O commands from the host computer system for reading data from and writing data to the at least one volatile memory, and means for retrieving the data written by the host computer system using the byte level memory I/O commands from the volatile memory and writing the data retrieved from the volatile memory to the at least one non-volatile memory. | 12-29-2016 |
20160378340 | Apparatus, System, and Method of Sequencing, Shadowing, and Queuing Operations in a Non-Volatile Storage Memory - An improved way of communicating data operation commands within a non-volatile storage controller is presented. The non-volatile storage controller includes an internal processing unit that is communicatively coupled with an associated host system, a master controller, and a plurality of local controllers that are communicatively coupled with a non-volatile memory. Upon receiving a series of data operations commands from the host system, the internal processing unit is configured to apply address shadowing when communicating the series of commands to the master controller such that the internal processing unit does not need to repetitively send the same set memory addresses to the master controller when issuing the series of commands. | 12-29-2016 |
20160378341 | NON-VOLATILE MEMORY DRIVE PARTITIONS WITHIN MICROCONTROLLERS - A method for managing data on a microcontroller. The method includes a computer processor receiving data to write to the memory of a microcontroller of a field-replaceable unit (FRU). The method further includes a computer processor determining that the received data is a type of data that is stored in a first logical partition, wherein the first logical partition is a logical partition of non-volatile memory of the microcontroller. The method further includes a computer processor determining whether the first logical partition includes sufficient space to store the received data. | 12-29-2016 |
20160378343 | NON-VOLATILE MEMORY DRIVE PARTITIONS WITHIN MICROCONTROLLERS - A method for managing data on a microcontroller. The method includes a computer processor receiving data to write to the memory of a microcontroller of a field-replaceable unit (FRU). The method further includes a computer processor determining that the received data is a type of data that is stored in a first logical partition, wherein the first logical partition is a logical partition of non-volatile memory of the microcontroller. The method further includes a computer processor determining whether the first logical partition includes sufficient space to store the received data. | 12-29-2016 |
20160378344 | PROCESSOR AND PLATFORM ASSISTED NVDIMM SOLUTION USING STANDARD DRAM AND CONSOLIDATED STORAGE - Methods and apparatus for effecting a processor- and platform-assisted NVDIMM solution using standard DRAM and consolidated storage. The methods and apparatus enable selected data in DRAM devices, such as DIMMs to be automatically copied to a persistent storage device such as an SSD in response to detection of a power unavailable event or an operating system error or failure without any operating system intervention. In one aspect, a platform includes a power supply and a temporary power source, such as a capacitor-based energy storage device, a small battery, or a combination of the two, either integrated in the power supply or separate. When power becomes unavailable, the temporary power source is use to continue to provide power to selected components in one or more power protected domains. The energy stored in the temporary power source is sufficient to temporarily power the components to enable DRAM data to be written to the persistent storage device. Upon system restart, the previously-stored DRAM data is restored to one or more DRAM devices from which the data was originally copied. | 12-29-2016 |
20160378345 | HANDLING MOVEMENT OF A PHYSICAL DRIVE - Embodiments of the present disclosure provide a method and apparatus for handling the movement of a physical drive by generating a provision drive for a physical drive that is moved; establishing a connection from the provision drive to the physical drive; and updating the provision drive via the connection according to location information of the physical drive. | 12-29-2016 |
20160378352 | EFFICIENT SOLID STATE DRIVE DATA COMPRESSION SCHEME AND LAYOUT - Methods and apparatus related to efficient Solid State Drive (SSD) data compression scheme and layout are described. In one embodiment, logic, coupled to non-volatile memory, receives data (e.g., from a host) and compresses the data to generate compressed data prior to storage of the compressed data in the non-volatile memory. The compressed data includes a compressed version of the data, size of the compressed data, common meta information, and final meta information. Other embodiments are also disclosed and claimed. | 12-29-2016 |
20160378357 | HYBRID STORAGE DEVICE AND METHOD FOR OPERATING THE SAME - A storage device includes a disk medium having a first recording region and a second recording region, a non-volatile semiconductor memory, and a controller. The controller is configured to write data of a first type into tracks of the first recording region that partially overlap with each other, to write for caching data of a second type into tracks of the second recording region, and to write for caching the data of the second type stored in the disk medium into the non-volatile semiconductor memory. | 12-29-2016 |
20160378358 | MEMORY CARD AND HOST DEVICE THEREOF - A memory card is attached to a host device, and includes a data control circuit which transfers data with respect to the host device in synchronism with a rise edge and a fall edge of a clock signal. | 12-29-2016 |
20160378373 | DATA BACKUP METHOD AND DATA RECOVERY METHOD BY USING A CABLE WITH STORAGE FUNCTION - A data backup method and a data recovery method by using a cable with storage function are disclosed in the present invention. When an electronic device is connected with a cable, the data backup or data recovery can be processed. Since the cable is required when the electronic device needs to be charged or be connected with a computer, the user will carry the cable all the time and the data backup and the data recovery can be executed at anytime and anywhere. The drawbacks that the data has not been backed up for a long time and the backup data is very different from the data within the electronic device can be avoided. The convenience of the data backup and the data recovery is increased. | 12-29-2016 |
20160378375 | MEMORY SYSTEM AND METHOD OF OPERATING THE SAME - A memory system includes a semiconductor memory device including a plurality of ways suitable for storing normal data and reading stored data, and a system way suitable for storing system data, and a controller suitable for controlling the semiconductor memory device to perform overall operations of the plurality of ways and an update operation of the system data of the system way. | 12-29-2016 |
20160378379 | MULTI-LAYER MEMORY SYSTEM HAVING MULTIPLE PARTITIONS IN A LAYER - A multi-layer memory and method for operation is disclosed. The memory includes multiple layers, where each layer includes flash memory cells having a greater bit per cell capacity than then prior layer and each layer may include a plurality of partitions having blocks exclusively associated with a particular data type. The method may include the steps of directing host data directly into a particular partition of a particular layer of the multi-layer memory upon receipt depending on a type of the data. The method may also include copying data within the same partition in a respective layer in a data relocation operation to generate more free blocks of memory so that data preferably stays within each layer and in the same partition, as well as transferring data from one layer to the next higher bit per cell layer within a same partition when layer transfer criteria are met. | 12-29-2016 |
20160378402 | Apparatus, System, and Method of Look-Ahead Address Scheduling and Autonomous Broadcasting Operation to Non-Volatile Storage Memory - A non-volatile memory system performs data operations efficiently for a host system by having a multi-layered architecture. The system includes multiple local controllers that are connected to an array of non-volatile memories, a master controller connected to the multiple local controllers, and an internal processing unit that communicates with the master controller. The internal processing unit receives data operation requests from the host system and generates groups of related operations. A group of related operations include a set of common addresses and multiple commands. The internal processing unit sends a group of related operations to the master controller, which in turn broadcasts the group of related operations to the local controllers, by first broadcasting addresses to the local controllers, broadcasting a first command to the local controllers, and then broadcasts a second command to the local controllers while the local controllers are still executing the first command. | 12-29-2016 |
20160378775 | MAINTAINING VERSIONS OF DATA IN SOLID STATE MEMORY - Various embodiments are directed to maintaining versions of data within a solid state memory. At least one request to write at least one dataset to a logical page of a solid state memory is received from a file system. At least one physical page in a data block of the solid state memory associated with the logical page is identified. A processor stores the dataset in the at least one physical page. At least one data versioning tag is associated with the at least one dataset in a data structure associated with the logical page. The data versioning tag identifies the at least one dataset as a given version of the logical page. The at least one dataset is maintained as accessible from the at least one physical page irrespective of subsequent write operations to the logical page in response to associating the at least one data versioning tag. | 12-29-2016 |
20170235486 | ENHANCED MULTI-STREAMING THOUGH STATISTICAL ANALYSIS | 08-17-2017 |
20170235487 | MEMORY SYSTEM AND OPERATION METHOD THEREOF | 08-17-2017 |
20170235488 | WINDOW BASED MAPPING | 08-17-2017 |
20170235489 | DATA STORAGE DEVICE AND DATA MAINTENANCE METHOD THEREOF | 08-17-2017 |
20170235495 | SOLID STATE DRIVE AND FLASH TRANSLATION LAYER TABLE REBUILDING METHOD THEREOF | 08-17-2017 |
20170235524 | Nonvolatile Memory Modules Comprising Volatile Memory Devices and Nonvolatile Memory Devices | 08-17-2017 |
20170235675 | LEVERAGING NON-VOLATILE MEMORY FOR PERSISTING DATA | 08-17-2017 |
20170235682 | VOLATILE/NON-VOLATILE MEMORY DEVICE ACCESS PROVISIONING SYSTEM | 08-17-2017 |
20170236541 | HYBRID STORAGE DEVICE HAVING A HEATER IN A HEAD AND METHOD OF OPERATING THE SAME | 08-17-2017 |
20180024533 | NUMERICALLY CONTROLLED SYSTEM AND NUMERICALLY CONTROLLED MACHINE TOOL | 01-25-2018 |
20180024738 | DATA READING METHOD, DATA WRITING METHOD AND STORAGE CONTROLLER USING THE SAME | 01-25-2018 |
20180024744 | DATA STORAGE DEVICES AND COMPUTING SYSTEMS INCLUDING THE SAME | 01-25-2018 |
20180024745 | MEMORY SYSTEM AND OPERATING METHOD THEREOF | 01-25-2018 |
20180024751 | METADATA MANAGEMENT ON A STORAGE DEVICE | 01-25-2018 |
20180024753 | INTERNALLY PRECONDITIONING SOLID STATE DRIVES FOR VARIOUS WORKLOADS | 01-25-2018 |
20180024756 | TECHNOLOGIES FOR ENHANCED MEMORY WEAR LEVELING | 01-25-2018 |
20180024758 | Replica Bit-Line Control Circuit | 01-25-2018 |
20180024764 | TECHNOLOGIES FOR ACCELERATING DATA WRITES | 01-25-2018 |
20180024768 | PARTITIONING MEMORY MODULES INTO VOLATILE AND NON-VOLATILE PORTIONS | 01-25-2018 |
20180024772 | MEMORY DEVICE INCLUDING CONCURRENT SUSPEND STATES FOR DIFFERENT OPERATIONS | 01-25-2018 |
20180024777 | Selectively Throttling Host Reads for Read Disturbs in Non-Volatile Memory System | 01-25-2018 |
20180024778 | SYSTEM AND METHOD OF ORCHESTRATING EXECUTION OF COMMANDS IN A NON-VOLATILE MEMORY EXPRESS (NVMe) DEVICE | 01-25-2018 |
20180024779 | STORAGE DEVICE AND STORAGE CONTROL METHOD | 01-25-2018 |
20180024781 | SECURITY EXTENSIONS FOR NON-VOLATILE MEMORY | 01-25-2018 |
20180024919 | MAPPING TABLES FOR STORAGE DEVICES | 01-25-2018 |
20180024920 | SYSTEM AND METHOD FOR TRACKING BLOCK LEVEL MAPPING OVERHEAD IN A NON-VOLATILE MEMORY | 01-25-2018 |
20180024921 | MEMORY SYSTEM EXECUTING GARBAGE COLLECTION | 01-25-2018 |
20180025784 | MEMORY DEVICE AND OPERATING METHOD THEREOF | 01-25-2018 |
20190146669 | METHOD, SYSTEM, AND APPARATUS FOR NESTED SUSPEND AND RESUME IN A SOLID STATE DRIVE | 05-16-2019 |
20190146670 | DATA MANAGEMENT SCHEME IN VIRTUALIZED HYPERSCALE ENVIRONMENTS | 05-16-2019 |
20190146671 | BACKGROUND THRESHOLD VOLTAGE SHIFTING USING BASE AND DELTA THRESHOLD VOLTAGE SHIFT VALUES IN NON-VOLATILE MEMORY | 05-16-2019 |
20190146679 | METHOD OF PERFORMING GARBAGE COLLECTION, STORAGE DEVICE PERFORMING THE SAME AND COMPUTING SYSTEM INCLUDING THE SAME | 05-16-2019 |
20190146682 | METHODS TO CONFIGURE AND ACCESS SCALABLE OBJECT STORES USING KV-SSDS AND HYBRID BACKEND STORAGE TIERS OF KV-SSDS, NVME-SSDS AND OTHER FLASH DEVICES | 05-16-2019 |
20190146683 | SEMICONDUCTOR DEVICE, DATA PROCESSING SYSTEM, DATA READING METHOD, AND DATA READING PROGRAM | 05-16-2019 |
20190146685 | SEMICONDUCTOR STORAGE DEVICE AND CONTROLLER | 05-16-2019 |
20190146687 | METHOD FOR PERFORMING REFRESH MANAGEMENT IN A MEMORY DEVICE, ASSOCIATED MEMORY DEVICE AND CONTROLLER THEREOF | 05-16-2019 |
20190146688 | MEMORY DEVICE AND RECLAIMING METHOD OF THE MEMORY DEVICE | 05-16-2019 |
20190146689 | Flash Device Access Method, Apparatus, and System | 05-16-2019 |
20190146698 | TECHNOLOGY TO MANAGE CAPACITY LOSS IN STORAGE DRIVES | 05-16-2019 |
20190146704 | Data Storage Device and Methods for Processing Data in the Data Storage Device | 05-16-2019 |
20190146705 | Data Storage Device and Methods for Processing Data in the Data Storage Device | 05-16-2019 |
20190146708 | TENANT-BASED TELEMETRY FOR PERSISTENT STORAGE MEDIA | 05-16-2019 |
20190146709 | STORAGE DEVICE SHARING ATTRIBUTE INFORMATION WITH HOST DEVICE TO USE HOST MEMORY BUFFER AND ELECTRONIC DEVICE INCLUDING THE SAME | 05-16-2019 |
20190146712 | MEMORY SYSTEM AND OPERATING METHOD THEREOF | 05-16-2019 |
20190146713 | FLASH REGISTRY WITH ON-DISK HASHING | 05-16-2019 |
20190146715 | MEMORY DEVICE | 05-16-2019 |
20190146812 | EXECUTING APPLICATIONS FROM A SEMICONDUCTOR NONVOLATILE MEMORY | 05-16-2019 |
20190146872 | METHOD FOR CONTROLLING OPERATIONS OF MEMORY DEVICE, ASSOCIATED MEMORY DEVICE AND CONTROLLER THEREOF, AND ASSOCIATED ELECTRONIC DEVICE | 05-16-2019 |
20190146906 | RAID STRIPE PHYSICAL PLACEMENT | 05-16-2019 |
20190146907 | NAMESPACE MAPPING OPTIMIZATION IN NON-VOLATILE MEMORY DEVICES | 05-16-2019 |
20190146908 | METHOD FOR ACCESSING FLASH MEMORY MODULE AND ASSOCIATED FLASH MEMORY CONTROLLER AND ELECTRONIC DEVICE | 05-16-2019 |
20190146909 | VALID DATA MANAGEMENT METHOD AND STORAGE CONTROLLER | 05-16-2019 |
20190146910 | DATA STORAGE DEVICE AND OPERATING METHOD THEREOF | 05-16-2019 |
20190146911 | MEMORY SYSTEM AND OPERATING METHOD THEREOF | 05-16-2019 |
20190146912 | Namespace Change Propagation in Non-Volatile Memory Devices | 05-16-2019 |
20190146913 | ON-DEVICE-COPY FOR HYBRID SSD | 05-16-2019 |
20190146914 | Data File Handling in a Volatile Memory | 05-16-2019 |
20190146925 | METHOD AND SYSTEM FOR ENHANCING FLASH TRANSLATION LAYER MAPPING FLEXIBILITY FOR PERFORMANCE AND LIFESPAN IMPROVEMENTS | 05-16-2019 |
20190146927 | NAMESPACE MAPPING STRUCTUAL ADJUSTMENT IN NON-VOLATILE MEMORY DEVICES | 05-16-2019 |
20220137814 | MULTIPLE OPEN BLOCK FAMILIES SUPPORTING MULTIPLE CURSORS OF A MEMORY DEVICE - An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to open a first block family associated with the memory device; assign a first cursor of a plurality of cursors of the memory device to the first block family; responsive to programming a first block associated with the first cursor, associate the first block with the first block family; open, while the first block family is open, a second block family associated with the memory device; assign a second cursor of the plurality of cursors of the memory device to the second block family; and responsive to programming a second block associated with the second cursor, associate the second block with the second block family. | 05-05-2022 |