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Solid-state read only memory (ROM)

Subclass of:

711 - Electrical computers and digital processing systems: memory


711101000 - Specific memory composition

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Deeper subclasses:

Class / Patent application numberDescriptionNumber of patent applications / Date published
711103000 Programmable read only memory (PROM, EEPROM, etc.) 2538
20130031296SYSTEM AND METHOD FOR MANAGING ADDRESS MAPPING INFORMATION DUE TO ABNORMAL POWER EVENTS - A method and apparatus for managing address map information are disclosed. In one embodiment, an apparatus may comprise a processor configured to store address map changes to a first data storage medium, save the address map changes to a nonvolatile data storage medium when an abnormal power state is detected, and when the power state is no longer abnormal retrieve the last saved address map information and address map changes and update the address map information using the address map changes. The apparatus may be configured to retrieve the instructions for the processor operation over a network connection.01-31-2013
20130031295ADAPTIVE RECORD CACHING FOR SOLID STATE DISKS - A storage controller receives a request that corresponds to an access of a track. A determination is made as to whether the track corresponds to data stored in a solid state disk. Record staging to a cache from the solid state disk is performed, in response to determining that the track corresponds to data stored in the solid state disk, wherein each track is comprised of a plurality of records.01-31-2013
20100077130Multiprocessor system with booting function using memory link architecture - The multiprocessor system includes first and second multiport semiconductor memory devices, first, second and third processors individually storing a first boot loader, the first and second processors being configured to access the first multiport semiconductor memory device, and the second and third processors being configured to access the second multiport semiconductor memory device, and a memory link architecture including the second multiport semiconductor memory device, the third processor, and a nonvolatile semiconductor memory device. The nonvolatile semiconductor memory device includes a plurality of storage areas storing a second boot loader and software for the first, second and third processors. The third processor is configured to access the nonvolatile semiconductor memory device and configured to apply the second boot loader to the first and second processors through a serial communication to perform a portion of booting the system.03-25-2010
20130086300STORAGE CACHING ACCELERATION THROUGH USAGE OF R5 PROTECTED FAST TIER - A data storage system with redundant SSD cache includes an SSD cache organized into logical stripes, each logical stripe having several logical blocks. The logical blocks of each stripe are organized into logical data blocks and one logical parity block. Data may be written to the SSD cache by performing an exclusive disjunction operation on the logical parity block, the new data and the existing data in logical stripe to update the parity block, then writing the new data over the existing data in a logical data block in the same logical stripe.04-04-2013
20130080680MEMORY STORAGE DEVICE, MEMORY CONTROLLER, AND TEMPERATURE MANAGEMENT METHOD - A temperature management method suitable for a memory storage device having a rewritable non-volatile memory module and a memory controller used for controlling the rewritable non-volatile memory module are provided. The temperature management method includes detecting and determining whether the hot-spot temperature of the memory storage device is higher than a predetermined temperature; and when affirmative, making the memory controller execute a cooling process, so as to reduce the hot-spot temperature of the memory storage device. Accordingly, the problem of heat buildup of the (rewritable non-volatile) memory storage device can be mitigated, as well as the problems of data loss and device aging of the (rewritable non-volatile) memory storage device.03-28-2013
20130080681EFFICIENT TWO WRITE WOM CODES, CODING METHODS AND DEVICES - The invention provides a family of 2-write WOM-codes, preferred embodiments of which provide improved WOM-rates. Embodiments of the invention provide constructs for linear codes C having a 2-write WOM-code. Embodiments of the invention provide 2-write WOM-codes that improve the best known WOM-rates known to the present inventors at the time of filing with two writes. Preferred WOM-codes are proved to be capacity achieving when the parity check matrix of the linear code C is chosen uniformly at random. Preferred embodiments of the invention provide an electronic device utilizing an efficient coding scheme of WOM-codes with two write capability. The coding) method is based on linear binary codes and allows the electronic device to write information to the memory twice before erasing it This method can be applied for any kind of memory systems, and in particular for flash memories. The method is shown to outperform all well-known codes.03-28-2013
20130080679SYSTEM AND METHOD FOR OPTIMIZING THERMAL MANAGEMENT FOR A STORAGE CONTROLLER CACHE - The present invention is directed to a method for optimizing thermal management for a storage controller cache of a data storage system. The method allows for pending writes of a storage controller to be selectively provided to solid-state device (SSD) module(s) of the controller in a manner which allows operating temperatures of the SSD module(s) to be maintained within a thermal envelope.03-28-2013
20130138865SYSTEMS, METHODS, AND DEVICES FOR RUNNING MULTIPLE CACHE PROCESSES IN PARALLEL - Certain embodiments of the present disclosure related to systems, methods, and devices for increasing data access speeds.05-30-2013
20130042047MEMORY SYSTEM, MEMORY DEVICE AND MEMORY INTERFACE DEVICE - In memory system in which the processing unit (02-14-2013
20100106886Transparent Self-Hibernation of Non-Volatile Memory System - A memory system self-initiates hibernation mode and responds to host commands issued during hibernation within a host protocol timeout period. Hibernation mode is entered after controller state data has been stored and while no host command to the memory system is pending. Power to volatile data storage is diminished during hibernation mode. Upon receiving a host command during hibernation mode, power is restored and a reduced portion of the controller state data is read from non-volatile memory. A removable data storage device or a portable electronic device with embedded data storage may be constructed with such a self-hibernating memory system.04-29-2010
20100095046METHOD AND APPARATUS FOR IMPROVING SMALL WRITE PERFORMANCE IN A NON-VOLATILE MEMORY - An invention is provided for improving performance in block based non-volatile memory when performing random small write operations. When requests for small page updates are received for a memory page currently storing data, the updated page data is written to a reserve memory page. The reserve memory page can be in the same memory block as the target memory page, or in an associated reserve memory block. In addition, the associated logical page address is temporarily remapped to the reserve page. Later, when time permits, the page data for the block can be reorganized into continuous pages in a new block.04-15-2010
20090043946ARCHITECTURE FOR VERY LARGE CAPACITY SOLID STATE MEMORY SYSTEMS - To provide a feasible means to connect many non-volatile memory modules into a very large capacity solid-state memory, a group modules may be connected in a serial manner to form a unidirectional loop with the memory controller. In some embodiments the same serial connection may be used to communicate commands, write data, and/or configuration data from the memory controller to each memory module, and to communicate read data and/or configuration status from each memory module to the memory controller. Some memory controllers may have capacity to handle multiple such loops.02-12-2009
20130073782METHOD AND DEVICE FOR STORING DATA - The invention discloses a method for storing data and a device of implementing the same. The method comprises receiving a request for storing data sent by a user and storing the data to an SSD according to the received request. The device comprises a request receiving module used to receive the request storing data and an SSD storage module used to store the data to an SSD according to the received request. The invention ensures consistency of data storage by storing data to an SSD according to the received request, thereby reducing data redundancy caused by using a cache layer to cache the data in the prior art. Additionally, the use of a single layer of an SSD to store data avoids the need of reloading data in the cache layer once a machine is power-down, thereby reducing the complexity of system design and the cost of operation and maintenance.03-21-2013
20130073781INFORMATION RECORDING DEVICE, INFORMATION RECORDING SYSTEM, AND INFORMATION COMMUNICATION METHOD - An information recording device comprises a memory component configured to hold data, a first file system controller configured to manage data held in the memory component on the basis of a first file name formed by a first code, and a wireless component configured to send and receive wireless signals. The first file system controller receives, from an access device connected to the information recording device, the first file name and a second file name that corresponds to the first file name and is formed by a second code that is different from the first code, identifies specific data having the first file name out of the data held in the memory component, and sends the second file name and the specific data to another information recording device connected via the wireless component.03-21-2013
20120226850VIRTUAL MEMORY SYSTEM, VIRTUAL MEMORY CONTROLLING METHOD, AND PROGRAM - Disclosed herein is a virtual memory system including a nonvolatile memory allowing random access, having an upper limit to a number of times of rewriting, and including a physical address space accessed via a virtual address; and a virtual memory control section configured to manage the physical address space of the nonvolatile memory in page units, map the physical address space and a virtual address space, and convert an accessed virtual address into a physical address; wherein the virtual memory control section is configured to expand a physical memory capacity allocated to a virtual page in which rewriting occurs.09-06-2012
20090031072Hybrid nonvolatile RAM - A memory subsystem includes a volatile memory, a nonvolatile memory, and a controller including logic to interface the volatile memory to an external system. The volatile memory is addressable for reading and writing by the external system. The memory subsystem includes a power controller with logic to detect when power from the external system to at least one of the volatile and nonvolatile memories and to the controller fails. When external system power fails, backup power is provided to at least one of the volatile and nonvolatile memories and to the controller for long enough to enable the controller to back up data from the volatile memory to the nonvolatile memory.01-29-2009
20120117302System and Method for Providing Instant Video in an Information Handling System - Before initializing a memory of an information handling system, a method includes loading an image of a video option ROM code for a graphics interface device to a cache associated with a processor of the information handling system, and executing the video option ROM code to initialize the graphics interface device. The method also includes executing a memory reference code to initialize the memory, and while executing the memory reference code, providing status information from the graphics interface device.05-10-2012
20090006717EMULATION OF READ-ONCE MEMORIES IN VIRTUALIZED SYSTEMS - The subject matter herein relates to computer systems and, more particularly, to emulation of read-once memories in virtualized systems. Various embodiments described herein provide systems, methods, and software that leverage the value of read-once memory for purposes such as keeping data or instructions secret and protected from unauthorized viewers, applications, hackers, and other processes. Some such embodiments include a virtual machine manager that emulates hardware memories in a system memory to facilitate virtual access to the hardware memories.01-01-2009
20130166816Apparatus, System, and Method for Managing Contents of a Cache - Apparatuses, systems, and methods are disclosed for managing contents of a cache. A method includes receiving a read request for data stored in a non-volatile cache. A method includes determining whether a read request satisfies a frequent read threshold for a cache. A method includes writing data of a read request forward on a sequential log-based writing structure of a cache in response to determining that the read request satisfies a frequent read threshold.06-27-2013
20130166815Memory controllers to output data signals of a number of bits and to receive data signals of a different number of bits - A memory controller has a digital signal processor. The digital signal processor is configured to output a digital data signal of M+N bits of program data intended for programming a memory cell of a memory device. The digital signal processor is configured to receive a digital data signal of M+L bits read from the memory cell of the memory device and to retrieve from the received digital data signal M bits of data that were stored in the memory cell.06-27-2013
20100070680MEMORY MANAGEMENT METHOD DURING POWER-ON SELF TEST - A memory management method during a power-on self test is used to perform an access management on an option ROM during a power-on self test after a personal computer is powered on. The memory management method includes the following steps. When a BIOS is booted, an option ROM is detected. A memory segment is designated in a conventional memory. It is determined whether the memory segment is empty or not. If the memory segment is not empty, a register segment with the same capacity as the memory segment is applied for from an extended memory, and data in the memory segment is moved to the register segment for being stored. If the memory segment is empty, data in the option ROM is moved to the memory segment. The option ROM in the memory segment is set.03-18-2010
20120311228METHOD AND APPARATUS FOR PERFORMING MEMORY WEAR-LEVELING USING PASSIVE VARIABLE RESISTIVE MEMORY WRITE COUNTERS - Method and apparatus for performing wear-leveling using passive variable resistive memory (PVRM) based write counters are provided. In one example, a method for performing wear-leveling using passive PVRM based write counters is disclosed. The method includes associating a logical address of a memory array with a physical address of the memory array via at least one mapping table. Additionally, the method includes, in response to writing to the physical address of the memory array, incrementally updating at least one PVRM based write counter associated with the physical address of the memory array. The at least one PVRM based write counter may be incrementally updated by varying an amount of resistance stored in the at least one PVRM based write counter.12-06-2012
20110283045EVENT PROCESSING IN A FLASH MEMORY-BASED OBJECT STORE - Approaches for processing an event in an objects store, such as an MySQL database management system or a memcached caching system, that are maintained on one or more solid state devices. A plurality of threads may be instantiated. Each of the threads may be configured to retrieve items from a queue of items. Each item in the queue of items may be associated with a particular event occurring within the object store. Each event is a message that indicates an activity requiring work has occurred within the object store. When a particular thread retrieves an item from the queue of items, the particular thread processes the particular event associated with the item retrieved by the particular thread. In this way, event handling in object stores such as MySQL and memcached may be performed more efficiently on a solid state device.11-17-2011
20110283044DEVICE AND METHOD FOR RELIABLE DATA STORAGE - A data storage device comprising at least one non-volatile storage medium having a plurality of data blocks, and a controller configured to allocate at least one of the data blocks for a writing operation based at least in part on data integrities of the data blocks.11-17-2011
20100268863INFORMATION PROCESSING APPARATUS - According to one embodiment, if a nonvolatile memory which stores format information of an HDD, a CD/DVD, an FDD and a USB storage device, and the USB storage device are connected, the drive letter of the USB storage device is virtually assigned as FDD or HDD on the basis of the format information.10-21-2010
20110302352Memory system and method of accessing a semiconductor memory device - A memory system is provided with a processor, a main memory, and a flash memory. Performance of the memory system is improved through achievement of speed-up and high data reliability. The memory system includes a nonvolatile memory device and a controller configured to drive a control program to control the nonvolatile memory device. The control program executes a second access operation for the nonvolatile memory device even before a first access operation to the nonvolatile memory device is completed.12-08-2011
20090164699SECURITY STORAGE OF ELECTRONIC KEYS WITHIIN VOLATILE MEMORIES - It is described a method for providing an electronic key within an integrated circuit (06-25-2009
20110219166USB CONTROLLER AND EXECUTION METHOD THEREOF - A universal serial bus (USB) controller and an execution method thereof are presented. The USB controller stores settings of different sensors in an external memory, or stores modified program codes when an originally stored program has bugs. With the execution of the set configurations, the program section to be execute is dynamically loaded into the random access memory (RAM) of the USB controller, so as to reduce the size of the RAM, thereby providing a large program modification space and avoiding the entire chip (the USB controller) from being stretched by an excessive large RAM.09-08-2011
20100169539IMAGE PROCESSING APPARATUS, ACCESS CONTROL METHOD, RECORDING MEDIUM - An image processing apparatus includes a nonvolatile memory device including a first storage area configured to store one or more predetermined information items; a secondary storage device including a second storage area configured to store the predetermined information items; and an access control unit configured to control access to the first storage area and the second storage area in response to an access request to access the predetermined information items.07-01-2010
20110271030Wear Leveling For Erasable Memories - In accordance with some embodiments, wear leveling may be done based on the difference in age of discarded blocks and engaged blocks. Data is moved to an older discarded block from a younger engaged block. Two wear leveling bits may be used for each logical block, such that the wear leveling bits are used in alternating cycles.11-03-2011
20120110238DATA SECURITY IN SOLID STATE MEMORY - The invention concerns data security in solid state memory. The solid state memory contains at least one specific area directed to storing sensitive information. The invention is for handling security relevant data in solid state memories and to protect the data from unauthorized access. According to the invention, the solid state memory includes a security element for deleting the specific memory area at start up.05-03-2012
20090094405Method and apparatus for writing data to and reading data from phase-change random access memory - A method and apparatus for writing data to and reading data from a phase-change random access memory (PRAM) include encoding original data using a predetermined encoding function, selecting data, from among the original data and the encoded data, which require less power when being written to the PRAM, writing the selected data to the PRAM, generating marking information related to the selected data, and writing the marking information to the PRAM. Therefore, power consumption can be reduced when data are written to the PRAM.04-09-2009
20090259796DATA WRITING METHOD FOR NON-VOLATILE MEMORY AND STORAGE SYSTEM AND CONTROLLER USING THE SAME - A data writing method for a non-volatile memory and a storage system and a controller using the same are provided. The data writing method includes executing a non-volatile memory writing program pre-stored in the non-volatile memory on a host, managing data desired to be written through the non-volatile memory writing program, executing a write-enabling command to temporarily disable a write protection of the non-volatile memory and executing a write command through the non-volatile memory writing program to write the data in a writing unit not recorded with any data in the non-volatile memory, and re-enabling the write protection after completing the writing by executing a write-protecting command. Accordingly, it is possible to avoid damage to the non-volatile memory due to multiple writings which are not desired in the non-volatile memory.10-15-2009
20100131694Secure Boot ROM Emulation - Secure boot ROM emulation with locking storage device. A locking storage device is provided by combining a nonvolatile memory device such as flash or EEPROM with one-shot locking logic which write enables at least a portion of the nonvolatile memory device upon power cycling of the overall digital device. This write enable is cleared during the stage 1 bootloader process, thus providing a protected update interval for updating a stage 2 bootloader once per power cycle.05-27-2010
20110173372METHOD AND APPARATUS FOR INCREASING FILE COPY PERFORMANCE ON SOLID STATE MASS STORAGE DEVICES - A mass storage device and method that utilize storage memory and a shadow memory capable of increasing the speed associated with copying data from one location to another location within the storage memory without the need to access a host computer for the copy transaction. A controller of the mass storage device receives a file copy request for a file to be copied between first and second locations within the storage memory. Data from the first location within the storage memory is then loaded into a shadow memory means of the mass storage device, and then the data is written from the shadow memory means to the second location within the storage memory.07-14-2011
20110271033Method and Apparatus for Detecting the Presence of Subblocks in a Reduced-Redundancy Storage System - Method and apparatus for rapidly determining whether a particular subblock of data is present in a reduced-redundancy storage system. An aspect of the invention achieves this by hashing each subblock in the storage system into a bitfilter that contains a ‘1’ bit for each position to which at least one subblock hashes. This bitfilter provides an extremely fast way to determine whether a subblock is in the storage system. In a further aspect of the invention, index entries for new subblocks may be buffered in a subblock index write buffer so as to convert a large number of random access read and write operations into a single sequential read and a single sequential write operation. The combination of the bitfilter and the write buffer yields a reduced-redundancy storage system that uses significantly less high speed random access memory than is used by systems that store the entire subblock index in memory.11-03-2011
20110271031Storage Medium with Data Memory and Charging Station - There is provided a storage medium for use as a source of energy for vehicles. An exemplary storage medium comprises a data memory that stores information about the charge status of the storage medium. The exemplary storage medium also comprises a SIM card.11-03-2011
20100005223Method for field-programming a solid-state memory device with a digital media file - The preferred embodiments described herein provide a method for field-programming a solid-state memory device with a digital media file. In one preferred embodiment, a solid-state memory device is provided that comprises a memory array comprising a plurality of field-programmable memory cells. A digital media file is selected for storage in the memory device, and a digital media source field-programs the memory cells of the memory device with the selected digital media file. After the digital media file is stored in the memory device, the stored digital media file can be played using a digital playback device. In some embodiments, the memory array is a three-dimensional memory array, and the memory cells are write-once memory cells. Other preferred embodiments are provided, and each of the preferred embodiments described herein can be used alone or in combination with one another.01-07-2010
20130219104METHOD AND APPARATUS FOR COMPRESSING DATA SECTORS IN STORAGE DRIVE - A storage drive includes a non-volatile semiconductor memory, and interface, a compression module, a sector module, and a control module. The interface is configured to receive first data sectors transmitted from a host to the storage drive. The compression module is configured to compress the first data sectors to generate second data sectors. Lengths of the second data sectors vary. The first sector module is configured to generate third data sectors by adding nuisance data to (i) the second data sectors, or (ii) an encrypted version of the second data sectors, wherein lengths of the third data sectors do not vary. The control module is configured to store the third data sectors in the non-volatile semiconductor memory.08-22-2013
20080282022Partially storing software functions that are not expected to change over time in ROM instead of RAM - A technique to identify portions of software that does not change over time, in order to store that portion in ROM, instead of RAM, to reduce RAM size. The smaller RAM conserves space on a chip and consumes less power. The technique allows wireless devices, such as cell phones, to use less RAM.11-13-2008
20080288710Semiconductor Memory Device and Its Control Method - A card information storage part (11-20-2008
20080288711Multimedia Platform - A device comprising a multimedia platform with a plurality of memories and a method of sharing a non-volatile memory. The multimedia platform in accordance with an embodiment of the present invention can have a non-volatile memory, a multimedia processor setting a route in accordance with a route selection signal received from the main processor such that the main processor accesses the non-volatile memory or the display unit, a first volatile memory which is a temporary memory device of the main processor, and a second volatile memory which is a temporary memory of the multimedia processor. With the present invention, the portable terminal can be made smaller by putting a memory chip and a multimedia platform in a single chip by use of the POP (package on package) technology.11-20-2008
20090187699NON-VOLATILE MEMORY STORAGE SYSTEM AND METHOD FOR READING AN EXPANSION READ ONLY MEMORY IMAGE THEREOF - A non-volatile memory storage system including a connecting interface, a non-volatile memory, a buffer memory, a microcontroller, and a virtual host module is provided. The connecting interface is used for connecting to a host. The non-volatile memory is used for storing user data, wherein the non-volatile memory further stores an expansion read only memory (ROM) image to be read by the host. The buffer memory is used for temporarily storing the expansion ROM image. The microcontroller controls the operation between the connecting interface, the buffer memory, and the non-volatile memory. The virtual host module provides an activation code in the expansion ROM image to the host through the microcontroller. Thereby, both the size and the fabrication cost of the non-volatile memory storage system can be effectively reduced.07-23-2009
20090055573SEMICONDUCTOR DEVICE CONNECTABLE TO MEMORY CARD AND MEMORY CARD INITIALIZATION METHOD - A semiconductor device includes first and second interfaces, and a control unit. The first interface is capable of being connected to a memory card and communicating with the memory card. The memory card has a nonvolatile semiconductor memory and has an unlock state and a lock state. The memory card in the unlock state permits an access to the nonvolatile semiconductor memory. The memory card in the lock state prohibits the access. The second interface is capable of being connected to a host device and communicating with the host device. The host device generates an access command to access the memory card. The control unit operates based on the access command sent from the host device through the second interface so as to release the lock state of the memory card, when the memory card is connected to the first interface.02-26-2009
20090144486DIRECT INTERCONNECTION BETWEEN PROCESSOR AND MEMORY COMPONENT - Conventional processor and memory configurations place holes into silicon or use expensive multi-layer-laminates/substrates to connect the processor with memory. Using a direct contact between the memory and processor allows for signaling between the two units. By judicious arrangement of the contact areas as well as employing other structures such as carriers and redistributors, adequate power and ground supply can be maintained for the processor. Therefore, there is little-to-no damage done to the silicon and expensive multi-layer-laminates/substrates can be avoided. Furthermore, there can be faster processing speeds since the memory and processor are close together.06-04-2009
20100274948COPY-PROTECTED SOFTWARE CARTRIDGE - A cartridge preferably for use with a game console. The cartridge comprises a ROM, a non-volatile memory, a processor and a dispatcher. An application running on the console may communicate with the dispatcher using predefined addresses, which enables the dispatcher to access the ROM, the non-volatile memory, or the processor, as the case may be. The invention improves on the prior art copy protection as no generic copy method may be found if the addresses are changed from one cartridge to another. In addition, to copy the software, the processor must be emulated.10-28-2010
20090248955REDUNDANCY FOR CODE IN ROM - A memory device capable of replacing code in read-only memory (ROM) by using a ROM redundancy register is disclosed. The memory device includes a controller that accesses code in ROM by use of a ROM address. The memory device further includes a ROM redundancy register capable of storing one or more ROM addresses and storing code corresponding to the one or more ROM addresses. The one or more ROM addresses may represent address locations in ROM that need code replacement. The ROM redundancy register may determine whether code corresponding to the ROM address should be replaced by code stored in the ROM redundancy register.10-01-2009
20100153619DATA PROCESSING AND ADDRESSING METHODS FOR USE IN AN ELECTRONIC APPARATUS - An electronic apparatus is disclosed. The electronic apparatus comprises a random access memory (RAM), a read-only memory (ROM) and a processing unit. The RAM stores a call transfer table, wherein the code transfer table comprising at least one transferred address in the RAM. The ROM stores at least one code to call one address of the code transfer table. The processing unit executes the code in the ROM and reads the transfer table accordingly, then transfers to run the data in the transferred address of the RAM.06-17-2010
20080307153Method and device for reorganizing data in a memory system, in particular for control devices in motor vehicles - A method for reorganizing performance quantity data in a segment of a non-volatile memory. The method encompasses the tasks or operations of generating a cohesive data block at an address space of a working memory, of performance quantity data from a first segment of the non-volatile memory and/or from the working memory, and of copying the data block to a predefined address space of the first or a second segment of the non-volatile memory in a block write operation, the performance quantity data of the data block in essence being written to the predefined address space simultaneously in the block write process.12-11-2008
20080307152Memory Module, Memory Controller, Nonvolatile Storage, Nonvolatile Storage System, and Memory Read/Write Method - In a storage having a nonvolatile RAM of destructive read type, the number of restorations attributed to data read from the nonvolatile RAM is decreased, and the overall life of the storage is prolonged. In a storage having a nonvolatile RAM of destructive read type and a volatile RAM and holding the same data in the nonvolatile and volatile RAMs, data is read out of the volatile RAM in reading and data is written in both volatile and nonvolatile RAMs in writing.12-11-2008
20100153618SHARED MEMORY ACCESS TECHNIQUES - Memory access techniques, in accordance with embodiments of the present technology, redirect memory access requests received from a baseband processor to shared memory coupled to an application processor. The techniques enable substantially real time read and write accesses by the application and baseband processors to the shared memory coupled to the application processor.06-17-2010
20100228904CIRCUIT ARRANGEMENT AND METHOD FOR DATA PROCESSING - In order to further develop a circuit arrangement (09-09-2010
20100235562SWITCH MODULE BASED NON-VOLATILE MEMORY IN A SERVER - A switch module having shared memory that is allocated to other blade servers. A memory controller partitions and enables access to partitions of the shared memory by requesting blade servers.09-16-2010
20100205348FLASH BACKED DRAM MODULE STORING PARAMETER INFORMATION OF THE DRAM MODULE IN THE FLASH - A device includes volatile memory; one or more non-volatile memory chips, each of which is for storing data moved from the volatile-memory; an interface for connecting to a backup power source arranged to temporarily power the volatile memory upon a loss of power from a primary power source; a controller in communication with the volatile memory and the non-volatile memory, wherein: the controller is programmed to move data from the volatile memory to the non-volatile memory chips upon a loss of power of the primary power source of the volatile memory; and parameters describing the volatile memory are stored in at least one of the non-volatile memory chips that store the data moved from the volatile memory. In some aspects the parameters include serial presence detect information.08-12-2010
20120246383MEMORY SYSTEM AND COMPUTER PROGRAM PRODUCT - According to an embodiment, a memory system includes semiconductor memories each having a plurality of blocks; a first table; a receiving unit; a generating unit; a second table; and a writing unit. The first table includes a plurality of memory areas each associated with each block and in each of which defect information is stored. The generating unit generates a set of blocks by selecting one block to which data are to be written in each semiconductor memory based on an index number indicating one of a plurality of rows in the first table and the first table. In the second table, an index number and a channel number are stored for each logical block address in association with one another. When a write command is received by the receiving unit, the writing unit writes data to a block associated with a selected channel number among blocks constituting the set.09-27-2012
20120144090STORAGE DEVICE AND USER DEVICE INCLUDING THE SAME - A storage device includes a host interface, a buffer memory, a storage medium, and a controller. The host interface is configured to receive storage data and an invalidation command, where the invalidation command is indicative of invalid data among the storage data received by the host interface. The buffer memory is configured to temporarily store the storage data received by the host interface. The controller is configured to execute a transcribe operation in which the storage data temporarily stored in the buffer memory is selectively stored in the storage medium. Further, the controller is responsive to receipt of the invalidation command to execute a logging process when a memory capacity of the invalid data indicated by the invalidation command is equal to or greater than a reference capacity.06-07-2012
20110113182Devices, Systems and Methods for Time-Sensitive Data and Limited-Persistent Storage - Devices, systems, and methods are disclosed which relate to devices utilizing time-sensitive memory storage. The time-sensitive memory storage acts as normal device memory, allowing the user of the device to store files or other data to it; however the information stored on the time-sensitive memory storage is automatically erased, based on some storage time period. A limited amount of persistent storage is used for names and message headers.05-12-2011
20090113112DATA STORAGE DEVICE, MEMORY SYSTEM, AND COMPUTING SYSTEM USING NONVOLATILE MEMORY DEVICE - Provided is a data storage device including two or more data storage areas including may have two or more (heterogeneous) types of nonvolatile memory cells. At least one of the data storage areas includes a plurality of memory blocks that are sequentially selected, and metadata are stored in the currently selected memory block. The memory blocks can be sequentially used and metadata can be stored in a uniformly-distributed manner throughout the data storage device. Therefore, separate merging and wear-leveling operations are unnecessary. Thus, it is possible to improve the lifetime and writing performance of a data storage device having two or more heterogeneous nonvolatile memories.04-30-2009
20120144091Mask-Programmed Read-Only Memory with Reserved Space - The present invention discloses a mask-ROM with reserved space (mask-ROM06-07-2012
20100306446METHOD AND DEVICES FOR CONTROLLING POWER LOSS - Described herein are methods and devices for controlling power loss. For one embodiment, a method includes issuing a controlled power off command with a controller. The method includes determining whether a memory device is performing a background operation. The method includes safely suspending the background operation or completing the background operation if the memory device is performing the background operation. The method includes safely removing a supply power.12-02-2010
20090070517MEMORY APPARATUS, MEMORY CONTROL METHOD, AND PROGRAM - Disclosed herein is a memory apparatus comprising: a nonvolatile memory configured to allow data to be written thereto and read therefrom in units of a cluster and to permit data to be deleted therefrom in units of a block made up of a plurality of sectors; a control circuit configured to control access operations to said nonvolatile memory; a management area; a user data area; and a cache area; said management area includes a logical/physical table, and the addresses of physical blocks in said cache area.03-12-2009
20130145074LOGIC DEVICE HAVING A COMPRESSED CONFIGURATION IMAGE STORED ON AN INTERNAL READ ONLY MEMORY - Systems and methods for using an internal read only memory (ROM) to configure a logic device are described. The ROM and the logic device may be located on a single chip. The ROM may be adapted to store highly compressed configuration images and be non-reprogrammable. The logic device may be configured based on the compressed configuration image.06-06-2013
20110029714RESISTIVE SENSE MEMORY ARRAY WITH PARTIAL BLOCK UPDATE CAPABILITY - Various embodiments of the present invention are generally directed to a method and apparatus for carrying out a partial block update operation upon a resistive sense memory (RSM) array, such as formed from STRAM or RRAM cells. The RSM array is arranged into multi-cell blocks (sectors), each block having a physical block address (PBA). A first set of user data is written to a selected block at a first PBA. A partial block update operation is performed by writing a second set of user data to a second block at a second PBA, the second set of user data updating a portion of the first set of user data in the first PBA. The first and second blocks are thereafter read to retrieve the second set of user data and a remaining portion of the first set of user data.02-03-2011
20110113181SYSTEM AND METHOD FOR UPDATING A BASIC INPUT/OUTPUT SYSTEM (BIOS) - There is provided a system and method for updating a basic input output system (BIOS). An exemplary method comprises obtaining a BIOS update package comprising a BIOS image update, a BIOS Signature, and a plurality of Public Key regions, wherein each Public Key region comprises a Public Key area and a signature area. The exemplary method also comprises updating a current Public Key with a new Public Key if the new Public Key is identified in one of the Public Key regions. The exemplary method additionally comprises validating the BIOS Signature using the current Public Key.05-12-2011
20100070679SYSTEM AND METHOD OF MANAGING MEMORY - The disclosure is related to systems and methods of management of memory. In a particular embodiment, a system is disclosed that comprises a control circuit adapted to compare a second data set to a first data set and to selectively replace the first data set with the second data set without performing an erase operation based on the comparison, wherein the erase operation is not performed when the first data set and the second data set differ only when locations of the second data set include a first logic value corresponding to one or more locations of the first data set that include a second logic value.03-18-2010
20110072188MEMORY SYSTEM INCLUDING NON-VOLATILE STORAGE MEDIA, COMPUTING SYSTEM INCLUDING MEMORY SYSTEM AND METHOD OF OPERATING MEMORY SYSTEM - In one aspect, meta data corresponding to a non-volatile storage media is read from the non-volatile storage media. Meta data to be updated is detected from the read meta data. Based on the read meta data and the detected meta data to be updated, storage areas of the non-volatile storage media are invalidated.03-24-2011
20120303860Method and Controller for Identifying a Unit in a Solid State Memory Device for Writing Data To - In a method for identifying a unit in a solid state memory device for writing data to a tier structure is maintained the tier structure comprising at least two tiers for assigning units available for writing data to. In response to receiving a request for writing data it is determined if a unit for writing data to is available in a first tier of the at least two tiers. In response to determining that a unit is available for writing data to in the first tier this unit is identified for writing data to, and in response to determining that no unit is available for writing the data to in the first tier it is determined if a unit is available for writing data to in a second tier of the at least two tiers subject to a priority of the write request.11-29-2012
20120303859IMPLEMENTING STORAGE ADAPTER PERFORMANCE OPTIMIZATION WITH PARITY UPDATE FOOTPRINT MIRRORING - A method and controller for implementing storage adapter performance optimization with parity update footprint mirroring between dual adapters minimizing firmware operations, and a design structure on which the subject controller circuit resides are provided. Each of a first controller and a second controller includes a plurality of hardware engines, a control store configured to store parity update footprint (PUFP) data; a data store; and a nonvolatile random access memory (NVRAM). One controller operates in a first initiator mode for transferring PUFP data to the other controller operating in a target mode. Respective initiator hardware engines transfers PUFP data from the initiator control store, selectively updating PUFP data, and writing PUFP data to the initiator data store and to the initiator NVRAM, and simultaneously transmitting PUFP data to the other controller. Respective target hardware engines write PUFP data to the target data store and the target NVRAM, eliminating firmware operations.11-29-2012
20110252183METHODS OF STORING DATA IN STORAGE MEDIA, DATA STORAGE DEVICES USING THE SAME, AND SYSTEMS INCLUDING THE SAME - A method of storing data in a storage media can include determining whether a size of data to be stored in the storage media satisfies a reference condition and compressing the data to provide compressed data for storage in the storage media upon determining that the size satisfies a reference condition.10-13-2011
20100332724Accessing a Serial Number of a Removable Non-Volatile Memory Device - A removable non-volatile memory device durably stores a serial number or identifier, which is used to mark multimedia content legally stored on the removable non-volatile memory device. In order to retrieve the serial number, a host electronic system coupled to the removable non-volatile memory device sends a sequence of multiple file access commands to access a predefined target file stored on the removable non-volatile memory device. In accordance with the executed predefined sequence of multiple file access commands, a corresponding sequence of data access commands are received at the removable non-volatile memory device and are interpreted as a request by the host electronic device to read the serial number. The removable non-volatile memory device outputs the serial number in response to the sequence of data access commands.12-30-2010
20110252184METHOD OF STORING DATA IN STORAGE MEDIA, DATA STORAGE DEVICE USING THE SAME, AND SYSTEM INCLUDING THE SAME - A method of storing data in a storage media is provided which includes sequentially compressing data by a compression unit, and storing the compressed data in the storage media, the compression unit being varied according to a compression characteristic of data to be stored in the storage media.10-13-2011
20120203951APPARATUS, SYSTEM, AND METHOD FOR DETERMINING A CONFIGURATION PARAMETER FOR SOLID-STATE STORAGE MEDIA - An apparatus, system, and method are disclosed to improve the utility of solid-state storage media by determining one or more configuration parameters for the solid-state storage media. A media characteristic module references one or more storage media characteristics for a set of storage cells of solid-state storage media. A configuration parameter module determines a configuration parameter for the set of storage cells based on the one or more storage media characteristics. A storage cell configuration module configures the set of storage cells to use the determined configuration parameter.08-09-2012
20080320205LONG-TERM DIGITAL DATA STORAGE - Embodiments are directed to recording digital data on an optically ablatable digital storage media. In one embodiment, a device configured to ablate portions of ablatable material on an optically ablatable digital storage media receives digital data that is to be recorded on a recording layer of an optically ablatable digital storage media. The recording layer is formed on a substrate with zero or more intervening layers between the recording layer and the substrate. The recording layer includes ablatable material capable of storing digital data. The device ablates the ablatable material in the recording layer according to a sequence defined by the received digital data such that the ablated portions correspond to data points of the received digital data.12-25-2008
20080228994Solid memory module structure with extensible capacity - A solid memory module structure with extensible capacity includes at least a non-volatile memory module, each of which has at least a memory chip, a first connector, and a control unit. And A Solid memory module includes at least a second connector, which electrically connects the first connector of the volatile memory module, and a system interfac09-18-2008
20120151119VIRTUAL MEMORY MANAGEMENT APPARATUS - A virtual memory management apparatus of an embodiment is embedded in a computing machine 06-14-2012
20110035533SYSTEM AND METHOD FOR DATA-PROCESSING - Disclosed is a data processing system and method. The data processing system may include a plurality of servers to process data, and a controller to shut off a power supplied to a server, among the plurality of servers, having data throughput less than a predetermined data throughput.02-10-2011
20120311229SYSTEM AND METHOD FOR RECORDING NUMBER OF POWER ON TIMES OF MOTHERBOARD - A powering on times recording system records powering on times of a motherboard, and includes a Basic Input/Output System (BIOS) Read Only Memory (ROM) chip installed on the motherboard. The BIOS ROM chip includes a first storage area storing a recording module and a second storage area storing a first variable data. When the motherboard is powered on, the recording module acquires the first variable data from the second storage area and increments the first variable data by one. The changed first variable data is recorded in the second storage area.12-06-2012
20120311227INFORMATION STORAGE SYSTEM, SNAPSHOT ACQUISITION METHOD, AND DATA STORAGE MEDIUM - The information storage system of an aspect of the present invention includes a first differential data storage area which stores differential data of a higher volume from a first point of time to a second point of time, a lower snapshot manager which provides a lower snapshot at the second point of time of the higher volume, and a second differential data storage area which stores differential data of the higher volume after the second point of time. The higher snapshot manager acquires a plurality of generations of higher snapshots from the lower snapshot and the data in the first differential data storage area and acquires a plurality of generations of higher snapshots from the data of the higher volume and the data in the second differential data storage area.12-06-2012
20090300268INFORMATION PROCESSING APPARATUS AND METHOD OF RECORDING USING START DATE THEREOF - According to an aspect of the present invention, there is provided an information processing apparatus including: a date generating module configured to generate date information in a real time; a nonvolatile recording module configured to record the date information in a given area; and a recording control module configured to access to the given area when specific software is started, wherein the recording control module is configured to record present date information generated by the date generating module in the given area when the date information is not recorded in the given area.12-03-2009
20090292859INTEGRATED STORAGE DEVICE AND CONTROL METHOD THEREOF - An integrated storage device and a control method thereof are provided. The integrated storage device includes an interface controller, a microcontroller, a plurality of non-volatile storage devices, and a channel link controller. The interface controller retrieves a master control signal and a slave control signal sent by a motherboard. The microcontroller generates a selecting signal. The non-volatile storage devices have at least two storage types. The non-volatile storage devices are divided into a first group of storage device and a second group of storage device according to the selecting signal. The channel link controller respectively controls the first group of storage device and the second group of storage device according to the master control signal and the slave control signal. Thereby, the accessing efficiency of the integrated storage device is increased.11-26-2009
20110191520STORAGE SUBSYSTEM AND ITS DATA PROCESSING METHOD - The amount of data to be stored in a semiconductor nonvolatile memory can be reduced and overhead associated with data processing can be reduced. When a microprocessor 08-04-2011
20120042116MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME - A memory device includes an interface unit and a memory unit. The interface unit receives a clock signal, a command signal and a data signal, internally adjusts input impedance based upon at least one of the command signal and the clock signal, and generates internal control signal of the memory device based upon the command signal and data signal. The memory unit performs read/write operations based upon the internal control signal.02-16-2012
20120011298INTERFACE MANAGEMENT CONTROL SYSTEMS AND METHODS FOR NON-VOLATILE SEMICONDUCTOR MEMORY - A control system includes a control module configured to control data transfer events of blocks of data between an interface management module and a non-volatile semiconductor memory based on at least two descriptors for each one of the data transfer events. The non-volatile semiconductor memory is prepared for a read event or a program event of the data transfer event. The interface management module and the non-volatile semiconductor memory are configured to operate within a solid-state memory drive. A command management module is configured to generate a parameter signal based on the at least two descriptors. The interface management module is configured to generate instruction signals based on the parameter signal and transmit the instruction signals to the non-volatile semiconductor memory to perform the read event or the program event.01-12-2012
20100095047MULTI-CORE DEVICE WITH OPTIMIZED MEMORY CONFIGURATION - A multi-core device for a piece of electronic equipment includes at least two cores arranged to execute different software portions stored on a memory means. At least one of these cores is associated with a primary RAM that is part of the memory means and arranged for persistent storage without power consumption.04-15-2010
20120166706DATA MANAGEMENT METHOD, MEMORY CONTROLLER AND EMBEDDED MEMORY STORAGE APPARATUS USING THE SAME - A data management method, a memory controller and an embedded memory storage apparatus are provided. The embedded memory storage apparatus has a plurality of physical blocks and each of the physical blocks has fast physical pages and slow physical pages. The method includes detecting a status of a state indication unit. The method further includes automatically reading data stored in the embedded memory storage apparatus, using the fast and slow physical pages of the embedded memory storage apparatus to re-store the data and marking status of the state indication unit as a second status when the status of the state indication unit is a first status. Accordingly, the storage space of the embedded memory storage apparatus can be efficiently used.06-28-2012
20120137046BLOCK CONTROL DEVICE OF SEMICONDUCTOR MEMORY AND METHOD FOR CONTROLLING THE SAME - A block control device for a semiconductor memory and a method for controlling the same are disclosed, which relate to a technology for controlling a block operation state of a Low Power Double-Data-Rate 2 (LPDDR2) non-volatile memory device. A block control device for use in a semiconductor memory includes a block address comparator configured to compare a first block address with a last block address, and output a same pulse or unequal pulse according to the comparison result, a block address driver configured to output a lock state control signal for driving a block address in response to the same pulse, a block address counter configured to count block addresses from the first block address to the last block address in response to the unequal pulse, and generate a block data activation pulse, and a block address register configured to store a lock state of a corresponding block in response to the lock state control signal and the block data activation pulse.05-31-2012
20120215961APPARATUS, SYSTEM, AND METHOD FOR BIASING DATA IN A SOLID-STATE STORAGE DEVICE - An apparatus, system, and method are disclosed for improving performance in a non-volatile solid-state storage device. Non-volatile solid-state storage media includes a plurality of storage cells. The plurality of storage cells is configured such that storage cells in an empty state store initial binary values that satisfy a bias. An input module receives source data for storage in the plurality of storage cells of the non-volatile solid-state storage media. Bits of the source data have a source bias that is different from the bias of the plurality of storage cells. A bit biasing module biases the bits of the source data toward the bias of the plurality of storage cells. A write module writes the biased source data to the plurality of storage cells of the non-volatile solid-state storage media.08-23-2012
20120254499PROGRAM, CONTROL METHOD, AND CONTROL DEVICE - Provided are a program, a control method, and a control device by which an activation time can be shortened. In a computer system which is equipped with a Memory Management Unit (MMU), with respect to a table of the MMU, page table entries are rewritten so that page faults occur at each page necessary for operation of software. At the time of activating, stored memory images are read page by page for the page faults which occurred in the RAM to be accessed. By reading as described above, reading of unnecessary pages is not performed, and thus, the activation time can be shortened. The present invention can be applied to a personal computer and an electronic device provided with an embedded computer.10-04-2012
20120254498SYSTEMS AND METHODS FOR MANAGING READ-ONLY MEMORY - A first virtual memory address is mapped to a real memory in a memory device, and a second virtual memory address is mapped to the real memory. Here, the first virtual memory address is authorized to modify data in the real memory and the second virtual memory address is not authorized to modify the data in the real memory.10-04-2012
20120317332SOLID STATE DRIVE PACKAGES AND RELATED METHODS AND SYSTEMS - Solid state drive (SSD) packages are provided including a controller package and at least one non-volatile memory package. The controller package and the at least one non-volatile memory package are connected to each other using a package-on-package (PoP) technique. A data input/output of the at least one non-volatile memory package is controlled by using the controller package.12-13-2012
20120185636Tamper-Resistant Memory Device With Variable Data Transmission Rate - A high capacity, secure and tamper-resistant computer data memory device. The device uses a plurality of dedicated memory controller elements in communication with an anti-tamper module that generates a tamper response when a predetermined tamper event occurs. The tamper response may be provided as the erasure or zeroization of the contents of a memory in the devices such as erasing one or more encryption keys. The elements of the device are preferably provided in a stacked configuration with rerouted I/O pads to obfuscate the I/O and function of the devices in the stack. In one embodiment, a data transfer governance means is provided. In a further embodiment, a current negotiation means is disclosed to permit the device to request a predetermined current from a host device. In a yet further embodiment, a portable safe house computing device is provided.07-19-2012
20090019210NONVOLATILE MEMORY APPARATUS - The service life of memory cards is to be substantially elongated against the occurrence of faulty blocks. A control logic searches blocks in a nonvolatile memory cell array for any acquired fault on the basis of a fault-inviting code in a management information section. If any faulty block is detected, the faulty block will be subjected to write/read comparison of data to judge whether or not the data in the block are normal. Any block determined to be normal will undergo rewriting of its fault-inviting code and registered as a normal block. Further, the registered block is stored into a write management table in the management area as a writable block. This enables an essentially normal block judged faulty on account of an erratic error or some other reason to be restored.01-15-2009
20120233379METHOD OF CONTROLLING MEMORY, MEMORY CONTROL CIRCUIT, STORAGE DEVICE AND ELECTRONIC DEVICE - A method of controlling a memory including a first storage area and a second storage area. The method includes determining, in response to a request for writing a write data string, whether the write data string changes a logical value stored in the memory from a first logical value to a second logical value, writing, to the first storage area, a logical value that is located in a position of the write data string and does not change an existing logical value of the memory from the first logical value to the second logical value, and writing the second logical value that is located in a position of the write data string and changes an existing logical value of the memory from the first logical value to the second logical value to the second storage area which is different from the first storage area.09-13-2012
20120324145MEMORY ERASING METHOD, MEMORY CONTROLLER, AND MEMORY STORAGE APPARATUS - A memory erasing method and a memory controller and a memory storage apparatus using the same are provided. The memory erasing method includes following steps. Physical blocks of a rewritable non-volatile memory module of the memory storage apparatus are logically grouped into at least a data area and a spare area. After the memory storage apparatus is powered on, an erase mark is configured for each of the physical blocks in the spare area, and each of the erase marks is initially set to an unerased state. After the memory storage apparatus enters a standby state, whether an erase command is executed on the physical blocks in the spare area is determined according to the erase marks. Thereby, the memory erasing method can effectively shorten the time for the memory storage apparatus to enter the standby state after the memory storage apparatus is powered on.12-20-2012
20110276743USING EXTERNAL MEMORY DEVICES TO IMPROVE SYSTEM PERFORMANCE - The invention is directed towards a system and method that utilizes external memory devices to cache sectors from a rotating storage device (e.g., a hard drive) to improve system performance. When an external memory device (EMD) is plugged into the computing device or onto a network in which the computing device is connected, the system recognizes the EMD and populates the EMD with disk sectors. The system routes I/O read requests directed to the disk sector to the EMD cache instead of the actual disk sector. The use of EMDs increases performance and productivity on the computing device systems for a fraction of the cost of adding memory to the computing device.11-10-2011
20110276742Characterizing Multiple Resource Utilization Using a Relationship Model to Optimize Memory Utilization in a Virtual Machine Environment - An approach is provided that uses a hypervisor to allocate a shared memory pool amongst a set of partitions (e.g., guest operating systems) being managed by the hypervisor. The hypervisor retrieves memory related metrics from shared data structures stored in a memory, with each of the shared data structures corresponding to a different one of the partitions. The memory related metrics correspond to a usage of the shared memory pool allocated to the corresponding partition. The hypervisor identifies a memory stress associated with each of the partitions with this identification based in part on the memory related metrics retrieved from the shared data structures. The hypervisor then reallocates the shared memory pool amongst the plurality of partitions based on the identified memory stress of the plurality of partitions.11-10-2011
20120331206APPARATUS, SYSTEM, AND METHOD FOR MANAGING DATA IN A STORAGE DEVICE WITH AN EMPTY DATA TOKEN DIRECTIVE - An apparatus, system, and method are disclosed for managing data with an empty data segment directive at the storage device. The apparatus, system, and method for managing data include a write request receiver module and a data segment token storage module. The write request receiver module receives a storage request from a requesting device. The storage request includes a request to store a data segment in a storage device. The data segment includes a series of repeated, identical characters or a series of repeated, identical character strings. The data segment token storage module stores a data segment token in the storage device. The data segment token includes at least a data segment identifier and a data segment length. The data segment token is substantially free of data from the data segment.12-27-2012
20120331205MEMORY CONTROLLER AND METHOD OF OPERATING THE SAME, AND MEMORY SYSTEM INCLUDING THE SAME - A method for operating a memory controller is disclosed. The method includes receiving data output from a memory block of a non-volatile memory device and changing erase count of the memory block based on the received data.12-27-2012
20120331204DRIFT MANAGEMENT IN A PHASE CHANGE MEMORY AND SWITCH (PCMS) MEMORY DEVICE - The present disclosure relates to the drift management for a memory device. In at least one embodiment, the memory device of the present disclosure may include a phase change memory and switch (hereinafter “PCMS”) memory cell and a memory controller that is capable of implementing drift management to control drift. Other embodiments are described and claimed.12-27-2012
20130013846METHOD FOR STORING DATA AND ELECTRONIC APPARATUS USING THE SAME - A method for storing data and an electronic apparatus using the same are provided. Only data is written to a memory card when the electronic apparatus wants to store the data to the memory card. And file information and location information corresponding to the data stored in the memory card are recorded into a buffer block of the electronic apparatus. After a file closing action is executed, the file information and the location information recorded in the buffer block are written to the memory card.01-10-2013
20130013847STORAGE SUB-SYSTEM FOR A COMPUTER COMPRISING WRITE-ONCE MEMORY DEVICES AND WRITE-MANY MEMORY DEVICES AND RELATED METHOD - Methods and apparatus for a solid state non-volatile storage sub-system of a computer is provided. The storage sub-system may include a write-many storage sub-system memory device including write-many memory cells, a write-once storage sub-system memory device including write-once memory cells, and a page-based interface that is adapted to read and write the write-once and write-many storage sub-system memory devices. Numerous other aspects are provided.01-10-2013
20130024599Method and Apparatus for SSD Storage Access - A media management system including an application layer, a system layer, and a solid state drive (SSD) storage layer. The application layer includes a media data analytics application configured to assign a classification code to a data file. The system layer is in communication with the application layer. The system layer includes a file system configured to issue a write command to a SSD controller. The write command includes the classification code of the data file. The SSD storage layer includes the SSD controller and erasable blocks. The SSD controller is configured to write the data file to one of the erasable blocks based on the classification code of the data file in the write command. In an embodiment, the SSD controller is configured to write the data file to one of the erasable blocks storing other data files also having the classification code.01-24-2013
20110246700Integrated circuits to control access to multiple layers of memory in a solid state drive - Circuits to control access to memory; for example, third dimension memory are disclosed. An integrated circuit (IC) may be configured to control access to memory cells. For example, the IC may include a memory having memory cells that are vertically disposed in multiple layers of memory. The IC may include a memory access circuit configured to control access to a first subset of the memory cells in response to access control data in a second subset of the memory cells. Each memory cell may include a non-volatile two-terminal memory element that stores data as a plurality of conductivity profiles that can be non-destructively sensed by applying a read voltage across the two terminals of the memory element. New data can be written by applying a write voltage across the two terminals of the memory element. The two-terminal memory elements can be arranged in a two-terminal cross-point array configuration.10-06-2011
20110246699MEMORY ACCESS CONTROL - An apparatus comprising: a memory having at least two sections; a security element associated with at least one of said at least two sections; and a processor for controlling access to at least one of the at least two sections of the memory in dependence on a value of the security element. The apparatus may be an integrated circuit and the memory may be a read-only-memory storing generic code in one of the sections and code specific to a mobile communication device provider in the second section. The security element may be a permanently programmed memory element programmed by the IC manufacturer.10-06-2011
20080222346Selectively utilizing a plurality of disparate solid state storage locations - A method for selectively utilizing a plurality of disparate solid state storage locations is disclosed. The technology initially receives class types for a plurality of disparate solid state storage locations. The characteristics of the received data are determined. The received data is then allocated to one of the plurality of disparate solid state storage locations based upon the determined characteristics of the received data.09-11-2008
20110271032ACCESS DEVICE AND MEMORY CONTROLLER - Refresh to be performed together with normal processing may fail to be performed for a sufficiently long period of time due to the specification requirements. In this case, data loss can occur in an area that has not been refreshed for a sufficiently long period of time. An access module (11-03-2011
20130103885ADMINISTERING THERMAL DISTRIBUTION AMONG MEMORY MODULES OF A COMPUTING SYSTEM - A computing system includes a number of memory modules and temperature sensors. Each temperature sensor measures a temperature of a memory module. In such a computing system a garbage collector during garbage collection, determines whether a temperature measurement of a temperature sensor indicates that a memory module is overheated and, if a temperature measurement of a temperature sensor indicates a memory module is overheated, the garbage collector reallocates one or more active memory regions on the overheated memory module to a non-overheated memory module. Reallocating the active memory regions includes copying contents of the active memory regions from the overheated memory module to the non-overheated memory module.04-25-2013
20130103883NONVOLATILE MEMORY APPARATUS AND WRITE CONTROL METHOD THEREOF - A nonvolatile memory apparatus includes a memory cell array, and a write operation controller configured to verify a write operation by comparing input data to the write operation controller with cell data written into the memory cell array, measure a resistance value after a first time is elapsed, and determine whether or not to re-perform the write operation according to the measured resistance value.04-25-2013
20130103884FILE SYSTEM AND CONTROL METHOD THEREOF - A file system including a first memory unit which is non-volatile and has a plurality of blocks, a control unit configured to select one of the plurality of blocks of the first memory unit, determine whether the selected block is a valid block, control a data write with respect to the selected block if the selected block is a valid block, divide the plurality of blocks into valid blocks and bad blocks by checking the plurality of blocks of the first memory unit, generate an address table by mapping the valid blocks and the bad blocks to addresses and control a loading of the address table generated, and a second memory unit which is volatile and stores the address table for the plurality of blocks of the first memory unit. An address table of a flash memory, which is a non-volatile memory, is stored in another memory04-25-2013
20130124776SECURE DATA STORAGE IN RAID MEMORY DEVICES - A redundant array of independent disk (RAID) memory storage system comprising data storage blocks arranged in a first plurality of data rows and a second plurality of data columns, wherein parity data is stored in additionally defined parity blocks, and wherein numbers of data blocks in respective columns are different, to accommodate the additional diagonal parity data block that the geometry of the system requires. The system is suitable for an SSD array in which sequential disk readout is not required.05-16-2013
20130124777STORAGE SYSTEM LOGICAL BLOCK ADDRESS DE-ALLOCATION MANAGEMENT AND DATA HARDENING - A bridge receives a power down command and in response converts the power down command to a data hardening command. The bridge issues the data hardening command to a solid state disk. In response to the data hardening command, data stored on the solid state disk is hardened. The hardening comprises writing data in volatile memory to non-volatile memory. The data that is hardened comprises user data and protected data. The data hardening command optionally comprises one or more of a flush cache command, a sleep command, and a standby immediate command.05-16-2013
20110219167NON-VOLATILE HARD DISK DRIVE CACHE SYSTEM AND METHOD - A non-volatile hard disk drive cache system is coupled between a processor and a hard disk drive. The cache system includes a control circuit, a non-volatile memory and a volatile memory. The control circuit causes a subset of the data stored in the hard disk drive to be written to the non-volatile memory. In response to a request to read data from the hard disk drive, the control circuit first determines if the requested read data are stored in the non-volatile memory. If so, the requested read data are provided from the non-volatile memory. Otherwise, the requested read data are provided from the hard disk drive. The volatile memory is used as a write buffer and to store disk access statistics, such as the disk drive locations that are most frequently read, which are used by the control circuit to determine which data to store in the non-volatile memory.09-08-2011
20130159597HYBRID STORAGE DEVICE AND METHOD OF OPERATING THE SAME - The inventive concept herein relates to data storage devices, and more particularly, to a hybrid storage device including a plurality of storage media. The hybrid storage device may include first and second storage media storing a plurality of data blocks according to a data type and a hybrid controller configured to copy a data block having a change type to the first storage medium if a data type of the data block stored in the second storage medium is changed.06-20-2013
20130159598METHOD OF MASSIVE PARALLEL PATTERN MATCHING AGAINST A PROGRESSIVELY-EXHAUSTIVE KNOWLEDGE BASE OF PATTERNS - A method of pattern and image recognition and identification includes building a data store of known patterns or images having known attributes and comparing those patterns to unknown patterns. The data store and comparison processing may be distributed across processors. A digital pattern recognition engine on each of the processors has the ability to compare a known pattern from the data store and an unknown pattern and compare the two patterns to determine whether the patterns constitute a match based on match criteria. If the comparison indicates a match, the match may be communicated to the data store and added as a known pattern with detected attributes to the data store. If the comparison does not indicate a match, the pattern may be flagged, transmitted to manual recognition, or further processed using character thresholding or cutting or slicing the pattern.06-20-2013
20130185475SYSTEMS AND METHODS FOR CACHE PROFILING - A cache module leverages a logical address space and storage metadata of a storage module (e.g., virtual storage module) to cache data of a backing store. The cache module maintains access metadata to track access characteristics of logical identifiers in the logical address space, including accesses pertaining to data that is not currently in the cache. The access metadata may be separate from the storage metadata maintained by the storage module. The cache module may calculate a performance metric of the cache based on profiling metadata, which may include portions of the access metadata. The cache module may determine predictive performance metrics of different cache configurations. An optimal cache configuration may be identified based on the predictive performance metrics.07-18-2013
20130191578STORING CACHED DATA IN OVER-PROVISIONED MEMORY IN RESPONSE TO POWER LOSS - A power loss condition is detected that affects volatile data that is cached in preparation for storage in a non-volatile, solid-state memory device. The volatile cached data is stored in an over-provisioned portion of the non-volatile, solid-state memory device in response to the power loss condition.07-25-2013
20110320683Information processing system, resynchronization method and storage medium storing firmware program - An information processing system includes sets of multiple processors performing processing synchronously. The system includes: a ROM storing a firmware program activating the processors to a synchronized state; a RAM defined by one address map; a firmware copying section copying the firmware program in the ROM to the RAM, on system boot; and a RAM address register storing an address of the RAM and of a copy destination of the firmware program. The system further includes: a RAM address storing section storing the address of the RAM and of the copy destination of the firmware program; a loss-of-synchronism detection section detecting loss of synchronism of the processors; and an address replacing section referring to the RAM address register upon detection of the loss of synchronism, thereby replacing an address for reading the stored firmware program, with the address of the RAM and of the copy destination of the firmware program.12-29-2011
20120030408APPARATUS, SYSTEM, AND METHOD FOR ATOMIC STORAGE OPERATIONS - A virtual storage layer (VSL) for a non-volatile storage device presents a logical address space of a non-volatile storage device to storage clients. Storage metadata assigns logical identifiers in the logical address space to physical storage locations on the non-volatile storage device. Data is stored on the non-volatile storage device in a sequential log-based format. Data on the non-volatile storage device comprises an event log of the storage operations performed on the non-volatile storage device. The VSL presents an interface for requesting atomic storage operations. Previous versions of data overwritten by the atomic storage device are maintained until the atomic storage operation is successfully completed. Data pertaining to a failed atomic storage operation may be identified using a persistent metadata flag stored with the data on the non-volatile storage device. Data pertaining to failed or incomplete atomic storage requests may be invalidated and removed from the non-volatile storage device.02-02-2012
20120066432Semiconductor Device - Provided is a user-friendly information processing system which is capable of maintaining latency within a fixed range and ensuring the expandability of a memory capacity at high speed and low cost. The information processing system, including an information processing device, a volatile memory, and nonvolatile memories, is configured. The information processing device, the volatile memory, and the nonvolatile memories are connected in series with one another to reduce the number of connection signals, thereby realizing speeding-up while maintaining the expandability of the memory capacity. The information processing device manages response time zones and time zones where responses overlap one another, and performs a correction operation on the latency, thereby realizing fast data transfer while maintaining the latency within the fixed range. The information processing device performs an error correction to improve the reliability when transferring the data of the nonvolatile memories to the volatile memory. The information processing system composed of a plurality of chips is configured as an information processing system/module in which the respective chips are arranged in layers, and wired together by a through via.03-15-2012
20120066431RECOVERABILITY WHILE ADDING STORAGE TO A REDIRECT-ON-WRITE STORAGE POOL - Embodiments include a method comprising detecting addition of a new nonvolatile machine-readable medium to a data storage pool of nonvolatile machine-readable media. The method includes preventing from being performed a first operation of a file system that requires a first parameter that identifies a logical indication of a location within the nonvolatile machine-readable media for the file system, until logical indications of locations within the new nonvolatile machine-readable medium for the file system have been stored in the data storage pool. The method includes allowing to be performed, prior to logical indications of locations within the new nonvolatile machine-readable medium being stored in the data storage pool, a second operation of the file system that does not require a second parameter that identifies a logical indication of a location within the nonvolatile machine-readable media, wherein the second operation causes data to be written into the new nonvolatile machine-readable medium.03-15-2012
20130205064Data Storage Devices Including Multiple Host Interfaces and User Devices Including the Same - Disclosed is an information storing device which includes a first interface for connection with a host; a second interface for connection with the host; a first memory unit including a first controller controlling a first nonvolatile memory, the first controller communicating with the host via the first interface; and a second memory unit including a second controller controlling a second nonvolatile memory, the second controller communicating with the host via the second interface.08-08-2013
20130205063SYSTEMS AND METHODS FOR OUT-OF-BAND BACKUP AND RESTORE OF HARDWARE PROFILE INFORMATION - Systems and methods are provided that may be implemented for out-of-band backup and/or restore of information handling system components. Such out-of-band backup and restore operations may be performed, in one embodiment, to backup and/or restore hardware profile information such as firmware images and corresponding system configuration information.08-08-2013

Patent applications in class Solid-state read only memory (ROM)

Patent applications in all subclasses Solid-state read only memory (ROM)