Inventors list

Assignees list

Classification tree browser

Top 100 Inventors

Top 100 Assignees


Subclass of:

711 - Electrical computers and digital processing systems: memory

Patent class list (only not empty are listed)

Deeper subclasses:

Class / Patent application numberDescriptionNumber of patent applications / Date published
711101000 Specific memory composition 4682
711154000 Control technique 2917
711117000 Hierarchical memories 2121
711170000 Memory configuring 759
711147000 Shared memory area 431
711167000 Access timing 133
20090204743STORAGE SUBSYSTEM AND CONTROL METHOD THEREFOF - Provided is a storage subsystem capable of inhibiting the deterioration in system performance to a minimum while improving reliability and availability. This storage subsystem includes a first controller for controlling multiple drive units connected via multiple first switch devices, and a second controller for controlling the multiple drive units connected via multiple second switch devices associated with the multiple first switch devices. This storage subsystem also includes a connection path that mutually connects the multiple first switch devices and the corresponding multiple second switch devices. When the storage [sub]system detects the occurrence of a failure, it identifies the fault site in the connection path, and changes the connection configuration of the switch device so as to circumvent the fault site.08-13-2009
20090193174READ DISTURBANCE MANAGEMENT IN A NON-VOLATILE MEMORY SYSTEM - An invention is provided for read disturbance management in a non-volatile memory. The invention includes storing a read count data for a memory location in non-volatile memory. The read count data indicating an amount of read operations accessing the memory location since data was last written to the memory location. Then, when data is read from the memory location while the value of the read count data is less than a predetermined threshold value, the value of the read count data is incremented. However, when the value of the read count data equals the predetermined threshold value, the data is moved to a new memory location, thereby avoiding read disturbance effects.07-30-2009
20100077129Data Processing Apparatus, Data Processing Method and Recording Medium - A data processing apparatus includes a connection interface that performs connection to removable memories, and a dividing unit that divides original data into N pieces of subdata (N denotes an integer of 2 or more). The dividing unit stores one to (N−1) pieces of different subdata respectively in L removable memories (L denotes an integer in a range of 1 to N), which are connected to the connection interface.03-25-2010
20100036998STORAGE SYSTEM AND METHOD FOR MANAGING A PLURALITY OF STORAGE DEVICES - A method of managing operation of a plurality of storage devices includes receiving current consumption information from at least one of the plurality of storage devices; and managing operation of at least one storage device, the operation management including permitting current consumption of a first one of the storage devices based on current consumption information that pertains to at least a second one of the storage devices. Also provided is a storage system that includes a plurality of storage devices, where each storage devices is configured to store data. A state machine, connected to each of the storage devices, is operative to permit current consumption of a first storage device based on current consumption information pertaining to at least a second storage device.02-11-2010
20090157943TRACKING LOAD STORE ORDERING HAZARDS - A method and system for processing data. In one embodiment, the method includes receiving a plurality of stores into a store queue, where each store is a result from a processor, and where the plurality of stores are destined for at least one memory address. The method also includes marking a most recent store of the plurality of stores for each unique memory address, comparing a load request against the store queue, and identifying only the most recent store for each unique memory address for the purpose of handling load-hit-store ordering hazards.06-18-2009
20090157945Enhanced Processor Virtualization Mechanism Via Saving and Restoring Soft Processor/System States - A method and system are disclosed for saving soft state information, which is non-critical for executing a process in a processor, upon a receipt of a process interrupt by the processor. The soft state is transmitted to a memory associated with the processor via a memory interface. Preferably, the soft state is transmitted within the processor to the memory interface via a scan-chain pathway within the processor, which allows functional data pathways to remain unobstructed by the storage of the soft state. Thereafter, the stored soft state can be restored from memory when the process is again executed.06-18-2009
20090043945Non-Volatile Memory System and Method for Reading Data Therefrom - A non-volatile memory system and a method for reading data therefrom are provided. The data comprises a first sub-data and a second sub-data. The non-volatile memory system comprises a first storage unit and a second storage unit, adapted for storing the two sub-data respectively. The first storage unit reads a first command from the controller, and stores the first sub-data temporarily as the first temporary sub-data according to the first command. The second storage unit reads a second command from the controller, and stores the second sub-data temporarily as the second temporary sub-data according to the second command. The first temporary sub-data is read from the first storage unit. Then, the first storage unit reads a third command from the controller. The second temporary sub-data is also read from the second storage unit while reading the third command. The time for reading data from the non-volatile memory system is reduced.02-12-2009
20090019209Reservation Required Transactions - A computer readable medium is provided embodying instructions executable by a processor to performing a method for performing a transaction including a transaction head and a transaction tail, the method includes executing die transaction head, including executing at least one memory reserve instruction to reserve a transactional memory location that are accessed in the transaction and executing the transaction tail, wherein the transaction cannot be aborted due to a data race on that transactional memory location while executing the transaction tail, wherein data of memory write operations to the transactional memory location is committed without being buffered.01-15-2009
20090006716PROCESSING WRONG SIDE I/O COMMANDS - A dual ported active-active array controller apparatus is provided having a first policy processor partnered with a first ISP having a first plurality of dedicated purpose FCs, a second policy processor partnered with a second ISP having a second plurality of dedicated purpose FCs, a communication bus interconnecting the ISPs, and programming instructions stored in memory and executed by the array controller to maintain the first policy processor in top level control of transaction requests from both the first plurality of FCs and the second plurality of FCs that are associated with network input/output (I/O) commands directed to a storage logical unit number (LUN) which the first ISP is a logical unit master of.01-01-2009
20090006715Memory Chip for High Capacity Memory Subsystem Supporting Multiple Speed Bus - A memory module contains an interface for receiving memory access commands from an external source, in which a first portion of the interface receives memory access data at a first bus frequency and a second portion of the interface receives memory access data at a second different bus frequency. Preferably, the memory module contains a second interface for re-transmitting memory access data, also operating at dual frequency. The memory module is preferably used in a high-capacity memory subsystem organized in a tree configuration in which data accesses are interleaved. Preferably, the memory module has multiple-mode operation, one of which supports dual-speed buses for receiving and re-transmitting different parts of data access commands, and another of which supports conventional daisy-chaining.01-01-2009
20080282020DETERMINATION OF SAMPLING CHARACTERISTICS BASED ON AVAILABLE MEMORY - A portion of data records of a full input data set are imported into memory of a computer system for processing by an executing application. The full input data set includes data records of a dimensionally-modeled fact collection. An amount of the data of the full input set to import is determined based on an amount of available memory of the computer system. The sampling characteristics for sampling the full input data set are determined based on the amount of the data that can be imported and on characteristics of the full input data set and application involved. The full input data set is then sampled and a portion of the records are imported into the memory of the computer system for processing. The sampling characteristics are determined such that analysis as a result of processing by the executing application of the sampled portion of the records imported is representative of the analysis that could otherwise be carried out on the full input data set, with a calculable statistical relevance.11-13-2008
20090089479Method of managing memory, and method and apparatus for decoding multi-channel data - A memory management method is provided. In the method, a spatial parameter included in an encoding result is represented as a vector of a time slot and a frequency band in a first domain, a temporary matrix is calculated in the first domain by using the difference between vectors of a current time slot and a previous time slot at the same frequency band and then is stored in a memory, and then a matrix needed to decode the encoding result is represented as a matrix for a time slot and a frequency band in a second domain by using the temporary matrix, thereby reducing the load on the memory for storing matrices on which a decoding operation is performed.04-02-2009
20090157944TRACKING STORE ORDERING HAZARDS IN AN OUT-OF-ORDER STORE QUEUR - A method and system for processing data. In one embodiment, the method includes receiving a first store and receiving a second store subsequent to the first store. The method also includes generating a pointer that points to the last store that needs to retire before the second store retires, where the pointer is associated with the second store, and the last store that needs to retire is the first store.06-18-2009
20100169538SYSTEMS, METHODS, AND DEVICES FOR CONFIGURING A DEVICE - Disclosed are methods and devices, among which is a method for configuring an electronic device. In one embodiment, an electronic device may include one or more memory locations having stored values representative of the capabilities of the device. According to an example configuration method, a configuring system may access the device capabilities from the one or more memory locations and configure the device based on the accessed device capabilities.07-01-2010
20080215795STORAGE TERMINAL, INFORMATION PROCESSING APPARATUS, AND INFORMATION PROCESSING SYSTEM - A storage terminal includes a storage unit, a communication unit, and a controlling unit. The storage unit stores first information and second information. The first information is information that is displayed according to a procedure defined in an Internet browser program. The second information is information that is output according to a procedure defined in a program different from the Internet browser program. The communication unit carries out communications with an information processing apparatus on which the Internet browser program is executed. The controlling unit executes processing according to a request received from the information processing apparatus, by executing an Internet server program. When the request received from the information processing apparatus by the communication unit is a request specifying the first information, the controlling unit reads the specified first information from the storage unit, and sends the first information from the communication unit to the information processing apparatus according to a communication standard for communications by the storage terminal. When the request received from the information processing apparatus by the communication unit is a request specifying the second information, the controlling unit reads the specified second information from the storage unit, and sends the second information from the communication unit to the information processing apparatus according to a read/write standard for reading information from or writing information to the storage unit.09-04-2008
20080215794STORAGE TERMINAL AND INFORMATION PROCESSING SYSTEM - A storage terminal includes an information storage unit, an association storage unit, a receiving unit, and a processing unit. The information storage unit includes a plurality of storage areas having individually different identifiers assigned thereto. The association storage unit stores the identifiers individually in association with different communication addresses on a network. The receiving unit receives a request including one of the communication addresses. The processing unit identifies the identifier associated with the communication address included in the request with reference to the association storage unit, and executes processing according to the request on the storage area having the identified identifier assigned thereto.09-04-2008
20080270676Data Processing System and Method for Memory Defragmentation - A data processing system is provided in a stream-based communication environment. The data processing system comprises at least one processing unit (PU10-30-2008
20080270675DEFECT MANAGEMENT FOR A SEMICONDUCTOR MEMORY SYSTEM - A method is provided for managing defects in a semiconductor memory system having a plurality of addressable locations. In the method, a first plurality of the addressable locations is allocated as in-use locations, and a second plurality of the addressable locations is allocated as spare locations. A plurality of sets of the in-use locations, wherein each of the sets is associated with a memory defect, is determined. At least one of the sets includes a different number of in-use locations than another of the sets. Each of the sets of the in-use locations is associated with at least one corresponding set of the spare locations. Each of a plurality of data requests that is associated with one of the sets of the in-use locations is directed to the at least one corresponding set of the spare locations.10-30-2008
20090063755PAPER-SHAPED NON-VOLATILE STORAGE DEVICE - A paper-shaped non-volatile storage device includes a top paper layer, a bottom paper layer and a flexible printed circuit board packaged between the top paper layer and the bottom paper layer. The flexible printed circuit board comprises a data-transmitting interface, a non-volatile memory controller and at least one non-volatile memory disposed thereon. Therefore, the paper-shaped non-volatile storage device features as both of traditional paper and traditional non-volatile storage devices, such as instantly writing, manually binding, and outwardly visible content as provided by the traditional paper sheets, and digital information storage, repeatable editing and rapid search capability as provided by the traditional non-volatile storage devices.03-05-2009
20090248954Storage system - Provided is a storage system capable of holding data by associating main data for long-term retention with sub data for maintaining its readability. The storage system: stores first data in a first location within a storage area upon reception of a storage request for the first data with a first file identifier being specified; holds information for associating the first file identifier, the first location, a retention period of the data, and first version information with one another; stores second data in a second location within the storage area upon reception of a storage request for the second data with the first file identifier and second version information being specified; holds information for associating the first file identifier, the second location, and the second version information with one another; and inhibits the first data and the second data from being changed before elapse of the retention period of the data.10-01-2009
20080313385Process for contiguously streaming data from a content addressed storage system - What is disclosed is process for backing data objects from a content addressed storage system to a tape storage device such that the data objects are written in a contiguous sequential fashion. Data objects are kept together on the storage medium, rather than fragmented. An embodiment of the present invention describes the software modules and memory buffers required to implement this process. Additionally, what is disclosed is a process that restores data objects that have been contiguously written to tape. According to one embodiment of the present invention, recovery of non-fragmented data objects is made more efficient and less prone to failure.12-18-2008
20080209100Hard disk testing method under extensible firmware interface - A hard disk testing method under an extensible firmware interface (EFI) is provided, which includes the following steps. A system file is backed up from the EFI of the hard disk into a storage area of a memory. The backup area of the system file is mapped as a real hard disk. A non-system file storage area is established in the memory, so as to store the non-system files of a hard disk test. Information of the system and non-system files of the hard disk test is acquired, so as to generate a system and a non-system file link table. When performing the test, the non-system files are backed up into the non-system file storage area. The system file link table and/or the non-system file link table is accessed, so as to load the system file and/or the non-system files directly from the storage area of the memory.08-28-2008
20080209102Device, method, and computer product for monitoring cache-way downgrade - A usage-rate measuring unit measures a CPU usage rate. A hit-count measuring unit measures a cache hit count indicating number of hits of a cache. A monitoring unit monitors the CPU usage rate and the cache hit count, and when a downgrade of the cache occurs, determines whether the CPU usage rate and the cache hit count are above a predetermined threshold.08-28-2008
20090300265Compact Encoding Methods, Media and Systems - A method for compact encoding including providing a first value field allocated in a first portion of a memory, wherein a portion of the first value field is utilized to store a fixed-size variable. A most significant zero bit (MSZB) is located in the first value field, and it is determined if the fixed-size variable can be written in a first area without performing an erase operation. The first area includes the N bits following the MSZB in the first value field. The fixed-size variable is written into the first area if the fixed-size variable can be written without performing the erase operation.12-03-2009
20090043944Method, Apparatus And Computer Program Product Providing Energy Reduction When Storing Data In A Memory - A method is disclosed to operate a memory device. The method includes, prior to overwriting a first unit of data at a location in a memory device with a second unit of data, determining if more energy is required to write the second unit of data than to write the second unit of data with at least one sub-unit thereof having bits that are inverted. If it is determined that less energy is required to write the second unit of data with the at least one sub-unit thereof having bits that are inverted, the method further includes overwriting the first unit of data with a modified second unit of data with the at least one sub-unit thereof having bits that are inverted, in conjunction with writing at least one bit memory for indicating a location in the modified unit of data of the sub-unit of data having the inverted bits.02-12-2009
20080244156APPLICATION PROCESSORS AND MEMORY ARCHITECTURE FOR WIRELESS APPLICATIONS - In one embodiment, the invention provides a method for accessing memory. The method comprises sending memory transactions to a memory sub-system for a first processor to an intermediate second processor interposed on a communication path between the first processor and the memory sub-system; and controlling when the memory transactions are allowed to pass through the second processor to reach the memory sub-system.10-02-2008
20080244159DATA TRANSFER CONTROL APPARATUS AND DATA TRANSFER CONTROL METHOD - A data transfer control apparatus includes a memory, a write control part controlling data writing to the memory, a read control part controlling data reading from the memory, a read-start calculation part calculating an output timing of a notification which indicates a read-start operation to the read control part based on each transfer condition of the data writing to the memory and the data reading from the memory, and an asynchronous transfer part asynchronously transferring a clock of the notification, and notifying the read control part of the notification.10-02-2008
20080244161Memory management apparatus and method for same - A memory management apparatus uses a link list memory to manage a use area and a vacant area of a data memory. The use of the use area of the data memory by each of plural ports is restricted, and the use area of the data memory is configured to be always provided for each of the plural ports. In this manner, monopolized use of the data memory by a specific port is prevented and each of the plural ports is securely provided with the use area of the data memory under control of the memory management apparatus.10-02-2008
20080244157Semiconductor memory device - A semiconductor memory device includes: a memory core region; a data transfer unit configured to transfer external data to the memory core region; a data code storage unit configured to store test data; and a data selection unit configured to select one of the test data from the data code storage unit and the data from the data transfer unit and output the selected data to the memory core region.10-02-2008
20090265503Non-Volatile Memory Apparatus and Method for Accessing a Non-Volatile Memory Apparatus - A non-volatile memory apparatus and a method for accessing the non-volatile memory apparatus are provided. The non-volatile memory apparatus comprises a management unit, a look-up table and a controller. The management unit comprises a plurality of data blocks and a plurality of spare blocks. The look-up table is adapted to record the read status of the management unit. The controller is configured to read the management unit and then generate the read status denoting the times that the management unit has been read to the look-up table, and to replace one of the data blocks by one of the spare blocks in response to the read status when the times that the management unit has been read exceeds a reference value.10-22-2009
20080282021DATA MANAGEMENT APPARATUS, DATA MANAGEMENT METHOD, AND PROGRAM - A data management apparatus for managing data stored in a predetermined storage area includes a reader configured to communicate with a plurality of objects each having a memory storing an address indicating a storage area and to read the address from the memory of an object with which communication is to be performed by a user among the plurality of objects; a data obtaining unit configured to obtain data to be stored in the storage area; and a storage controller configured to cause the data obtained by the data obtaining means to be stored in the storage area indicated by the address read by the reader.11-13-2008
20080235433HYBRID DENSITY MEMORY STORAGE DEVICE AND CONTROL METHOD THEREOF - The present invention discloses a control method for a hybrid density memory storage device. The method arranges physical locations for a file system stored in the storage device. The storage device includes a high density storage space, a low density storage space and a hot list capable of recording a plurality of logical locations. The method includes the following steps: receiving a command; verifying whether the logical location of the command belongs to the logical locations recorded in the hot list; and according to the verification, assigning a physical location of the high density storage space or a physical location of the low density storage space as the physical location corresponding to the logical location of the command.09-25-2008
20080235432MEMORY SYSTEM HAVING HYBRID DENSITY MEMORY AND METHODS FOR WEAR-LEVELING MANAGEMENT AND FILE DISTRIBUTION MANAGEMENT THEREOF - The present invention discloses a memory system having a hybrid density memory. The memory system includes a plurality of storage spaces whereby the storage spaces have respective levels of endurance and each storage space has a plurality of blocks and pre-determined weighting factors corresponding to the levels of endurance of the storage spaces. After executing a command of erasing a specific block, the system records the erase in accordance with the weighting factor of the storage space to which the specific block belongs. Whereby, the erase counts of all the blocks of different storage spaces are able to reach respective levels of endurance as simultaneously as possible.09-25-2008
20080244158Drawing Apparatus - A drawing apparatus which can create an exposure pattern rapidly. The drawing apparatus has a raster conversion processing module for converting vector images as wiring patterns into bitmap image data, an image cache module for temporarily storing a predetermined-size cached image supplied from the raster conversion processing module, a first compression module for compressing the cached image stored in the image cache module, a second compression module for compressing the cached image stored in the image cache module in a compression ratio differing from that of the first compression module, a comparison module for comparing data sizes of compressed data generated by the first and second compression modules and selecting one having a smaller data size, a memory access module for writing the compressed data selected by the comparison module, into a storage module, and a cache region control module for controlling a compression status of the cached image.10-02-2008
20080244160Storage Method for a Gaming Machine - In a first aspect the invention provides a storage method for a gaming machine, including allocating program code to one of at least two program categories including a first category of program code that is expected to be modified more frequently than a second category of program code and storing program code from the first and second categories in logically separate storage areas.10-02-2008
20080209104Data Migration Method - A first storage system includes a first storage area for storing data written by a computer. A second storage system includes a second storage area to which the data stored in the first storage area migrates. A third storage system includes a virtual storage area corresponding to the second storage area. An access request to the virtual storage area is converted into an access request to the second storage area to be issued. A management computer transmits, to the third storage system, an instruction to migrate the data of the second storage area to a third storage area of the third storage system based on a determination result between a value of the data migrated to the second storage area and a predetermined threshold value.08-28-2008
20090164698Nonvolatile storage device with NCQ supported and writing method for a nonvolatile storage device - A nonvolatile storage device buffers multiple write commands and selects one or more therefrom according to a choosing policy to execute in priority, so as to increase the probability of continuously executing write commands corresponding to an identical smallest erasable unit, thereby reducing the frequency of backup, erasing and copyback operations and improving the efficiency of the nonvolatile storage device.06-25-2009
20090164697INFORMATION USAGE CONTROL SYSTEM, INFORMATION USAGE CONTROL DEVICE AND MEHTOD, AND COMPUTER READABLE MEDIUM - A system includes a first device and one or more second devices that each provides a user with usage information for using target information, based on control information, wherein the first device has a memory that stores the control information which contains device information and condition information, so as to be associated with the target information, a receiving unit that receives from a requester a request, an inquiry unit that inquires of the second device, when the requester is not managed by its own device, about whether the requester is managed by the device, and a providing unit that provides the requester, when, based on a response to the inquiry and the memory, the requester is managed by the second device designated by the device information, with the usage information, based on the condition information, and the second device has a response unit that sends the response to the inquiry.06-25-2009
20090150592Storage device with multiple management identity and management method thereof - A storage device with multiple management identities and a management method thereof are disclosed. The storage device includes a first storage space corresponding to a first management identity and a second storage space corresponding to a second management identity. By a control unit, the storage device is coupled with the first storage space as well as the second storage space and selects the first storage space or the second storage space according to a selection signal corresponding to the first management identity or the second management identity so as to provide the first storage space or the second storage space being used by a computer space. Thus the convenience of use of the storage device is improved.06-11-2009
20090138648DATA PROCESSING DEVICE, RECORDING MEDIUM, AND DATA PROCESSING METHOD - A first updating unit updates the state of access control of the data to be edited set up in the memory to an exclusive state in response to an exclusion request to the data to be edited. A second updating unit updates the state of access control of the data to be edited set up in the memory to an exclusion removal standby state in response to an exclusion removal request to the data to be edited in which the state of access control is in the exclusive state. A third updating unit updates the state of access control to all data to be edited from the exclusion removal standby state to an exclusion removal state when the data to be edited in which the state of access control is updated.05-28-2009
20090144484MEMORY SYSTEM AND MEMORY CHIP - A memory system includes a memory which asserts a high-power-consumption operation output when an amount of the power consumption is high in internal operations in respective operations, and a controller which has an interface function between a host and the memory and receives the high-power-consumption operation output. The controller switches an operation mode thereof to a low power consumption mode when the high-power-consumption operation output is asserted.06-04-2009
20090024784METHOD FOR WRITING DATA INTO STORAGE ON CHIP AND SYSTEM THEREOF - Disclosed are a method for writing data into a first storage on a chip and a system thereof. The method includes storing an initial firmware into a second storage on the chip, programming the first storage according to a specific data by utilizing the initial firmware, and blocking further programming operations applied to at least part of the specific data after the specific data is successfully stored in the first storage. Therefore the invention can save the external pin connections of the chip to prevent computer hackers from accessing or changing the content of the storage.01-22-2009
20090024785METHOD AND PROGRAM FOR FILE INFORMATION WRITE PROCESSING - The file information write processing method according to the present invention is a file information write processing method wherein a computer executes a process for outputting instruction corresponding to a file information write instruction from an application to a device driver, wherein: searching clusters which are empty areas within an actual data area of a memory unit of the computer, and obtaining the search result; if clusters which are empty areas exist, writing information to overwrite to one or more clusters within the actual data area of the memory unit which is a target of the write instruction from the application, to the clusters which are empty areas; and freeing clusters which were to be overwritten by the information written to the empty area clusters.01-22-2009
20090198867METHOD FOR CHAINING MULTIPLE SMALLER STORE QUEUE ENTRIES FOR MORE EFFICIENT STORE QUEUE USAGE - A computer implemented method, a processor chip, a data processing system, and computer program product in a data processing system process information in a store cache of a data processing system. The store cache receives a first entry that includes a first address indicating a first segment of a cache line. The store cache then receives a second entry including a second address indicating a second segment of the cache line. Responsive to the first segment not being equal to the second segment, the first entry is chained to the second entry.08-06-2009
20090055572OPTIMAL SOLUTION TO CONTROL DATA CHANNELS - A DRAM controller may comprise two sub-controllers, each capable of handling a respective N-bit interface (e.g. 64-bit interface). Each sub-controller may also be configurable to be (2*N)-bit (e.g. 128-bit) capable with respect to control logic, for controlling a logical 128-bit data path. In ganged mode, each sub-controller may logically operate as if it were handling data in 128-bit chunks, (i.e. handling the entire 128-bit data path), while actual full bandwidth may be achieved by having one of the sub-controllers operate on commands and a first N-bit portion of each (2*N)-bit chunk of data, and having the other sub-controller operate on a “copy” of the commands with a corresponding remaining N-bit portion of each (2*N)-bit chunk of data. Once the BIOS has configured and initialized the two DRAM controllers to operate in ganged mode, the BIOS and all software may no longer need to be aware that two memory controllers are used to access a single (2*N)-bit wide channel.02-26-2009
20090063754COMBINED PARALLEL/SERIAL STATUS REGISTER READ - Methods and devices are disclosed, such as those involving a solid state memory device that includes a status register configured to be read with a combined parallel and serial read scheme. One such solid state memory includes a status register configured to store a plurality of bits indicative of status information of the memory. One such method of providing status information in the memory device includes providing the status information of a memory device in a parallel form. The method also includes providing the status information in a serial form after providing the status information in a parallel form in response to receiving at least one read command.03-05-2009
20080263263Implementation-efficient multiple-counter value hardware performance counter - An implementation-efficient, multiple-counter value hardware performance counter is disclosed. A hardware counter of one embodiment includes a memory array and a hardware incrementer. The array stores counter values that are indexable by an index constructed based at least on the number of events to which the counter values correspond. The index may be constructed as a concatenation of a number of bits binarily representing the number of events, and a number of bits binarily representing the number of qualifiers to the events. The incrementer reads the counter values from the array, increments the counter values, and writes the resulting counter values back into the array. The array may be divided into banks over which the counter values are stored, where each bank has a separate instance of the incrementer. Each bank may have a separate instance of the index that indexes only those counters stored in the bank.10-23-2008
20080263262COMMAND INTERFACE FOR MEMORY DEVICES - A method for operating a memory device that includes a plurality of analog memory cells includes accepting at an input of the memory device a self-contained command to perform a memory access operation on at least one of the memory cells. The command includes an instruction specifying the memory access operation and one or more parameters that are indicative of analog settings to be applied to the at least one of the memory cells when performing the memory access operation.10-23-2008
20080263261STORAGE APPARATUS AND MANAGEMENT UNIT SETTING METHOD - A storage apparatus that provides a dynamically extensible virtual volume for a host apparatus that accesses the virtual volume is characterized by including: a management unit setting part for setting a management unit, with which an area for storing data sent from the host apparatus is divided on a predetermined-area basis for management, for a pool area that provides a storage area to be assigned to the virtual volume; and a management unit resetting part for resetting the management unit set by the management unit setting part via analysis of the status of access from the host apparatus to the data at a predetermined time to make the management unit optimum for the status of access from the host apparatus to the data.10-23-2008
20080263260DISPLAY INTERFACE BUFFER - A display interface buffer includes a general purpose memory to store data capable of being displayed on a panel, a plurality of display drivers to receive data from the general purpose memory, each of the display drivers to drive a different portion of the panel with the data, and processor or a direct memory access controller to access data in the general purpose memory and to provide the data to the display drivers for presentation on the panel.10-23-2008
20080263259HINTS MODEL FOR OPTIMIZATION OF STORAGE DEVICES CONNECTED TO HOST AND WRITE OPTIMIZATION SCHEMA FOR STORAGE DEVICES - Architecture for data communications optimization based on generating and communicating “intents” or “hints” to a storage device and faster/slower solid state memory optimization. Data destined for storage on the storage device (capable of hints processing) can be bracketed to take advantage of improved performance associated with the hints processing. Data can be communicated in block format such that individual series of block exchanges can occur. Hints processing can be optional at the storage device. When communicated to the storage device firmware facilitates optimization of internal data flow and device operation. A write optimization schema is provided for storage system such as solid state storage devices. For example, frequently-modified data can be stored in faster memory to provide more efficient overall application data processing, and less-frequently modified data can be processed into and out of lower cost (or slower) memory.10-23-2008
20090094404Self writing storage device - A system for a storage device to indicate that the storage device is to be overwritten to delete the data and files contained on it including remnants of previously deleted files. The system may comprise a jumper pin adapter dedicated to the purpose of overwriting the storage device. Power for the storage device can be provided by a special power adapter and the overwrite procedure can be performed as part of the storage device's power on self test so that the computer containing the storage device does not need to be booted into an operating system in order to perform the overwrite procedure.04-09-2009
20090100213Systems and Methods for Managing Memory Core Surface - Accessing a shared buffer can include receiving an identifier associated with a buffer from a sending process, requesting one or more attributes corresponding to the buffer based on the received identifier, mapping at least a first page of the buffer in accordance with the one or more requested attributes, and accessing an item of data stored in the buffer by the sending process. The identifier also can comprise a unique identifier. Further, the identifier can be passed to one or more other processes. Additionally, the one or more requested attributes can include at least one of a pointer to a memory location and a property describing the buffer.04-16-2009
20090254694MEMORY DEVICE WITH INTEGRATED PARALLEL PROCESSING - A method for data processing includes accepting input data words including bits for storage in a memory, which includes multiple memory cells arranged in rows and columns. The accepted data words are stored so that the bits of each data word are stored in more than a single row of the memory. A data processing operation is performed on the stored data words by applying a sequence of one or more bit-wise operations to at least one row of the memory, so as to produce a result that is stored in one or more of the rows of the memory.10-08-2009
20090259793System and method for effectively implementing an erase mode for a memory device - A system and method for effectively implementing an erase mode for a memory device includes a memory array that is configured to temporarily store confidential or other types of data. A mode switch is provided on the memory device for permitting a device user to readily select between a normal mode and the erase mode for the memory device. A memory controller of the memory device contemporaneously or subsequently erases the data from the memory array if the erase mode has been activated by the mode switch.10-15-2009
20090240867Data processing system and storage area allocation method thereof - When creating a storage pool with external volumes, it is not possible to put together the volumes that have the same level of reliability if consideration is only given to the physical attributes of such volumes. Further, the reliability demanded between a host computer and a storage apparatus does not necessarily match the reliability between storage apparatuses. When creating a storage pool in the data processing system of this invention, not only is consideration given to the characteristics of the physical disks themselves, consideration is also given to the connection status of the backend network between a storage apparatus and a switch loaded with external storage function, and an external storage apparatus. What is more, volumes are allocated to a host machine after said system considers both the redundancy of a backend network of between storage apparatuses and that of a network path between the host machine and storage apparatus.09-24-2009
20090265504MEMORY, COMPUTING SYSTEM AND METHOD FOR CHECKPOINTING - Embodiments of the present invention provide local checkpoint memories that are closely coupled to the processor of a computing system used during normal operation. The checkpoint memory may be coupled to the processor through a peripheral bus or a memory bus. The checkpoint memory may be located on a same semiconductor substrate or circuit board as the processor. The checkpoint memory may be located on a same semiconductor substrate as a main memory used by the processor during normal operation. The checkpoint memory may be included in a memory hub configuration, with a checkpoint memory hub provided for access to the checkpoint memory.10-22-2009
20090248953STORAGE SYSTEM - A storage system capable of managing information in accordance with system configuration changes is provided.10-01-2009
20090248952DATA CONDITIONING TO IMPROVE FLASH MEMORY RELIABILITY - Methods and apparatus for managing data storage in memory devices utilizing memory arrays of varying density memory cells. Data can be initially stored in lower density memory. Data can be further read, compacted, conditioned and written to higher density memory as background operations. Methods of data conditioning to improve data reliability during storage to higher density memory and methods for managing data across multiple memory arrays are also disclosed.10-01-2009
20090259795POLICY FRAMEWORK TO TREAT DATA - Data can be retained upon a storage medium that has characteristics suitable for the data. However, as the storage mediums are used, time passes, etc., characteristics of memory can change and therefore data can reside upon an improper medium. Data can be dynamically moved from one storage location to another automatically and intelligently based upon a change in characteristics. In addition, new data can be placed on a storage medium based upon characteristics of the medium in a current state.10-15-2009
20090259794SERVICEABILITY LEVEL INDICATOR PROCESSING FOR STORAGE ALTERATION - A method, system, and computer program product for implementing Serviceability Level Indicator Processing (SLIPs) for storage alterations in a computer system is provided. A plurality of storage release requests is analyzed to identify an address monitored by a storage alteration slip. Upon identification of the address, the storage alteration slip is disabled and an initialization slip is re-enabled.10-15-2009
20090254693METHOD AND SYSTEM FOR GENERATING CONSISTENT SNAPSHOTS FOR A GROUP OF DATA OBJECTS - Snapshots that are consistent across a group of data objects are generated. The snapshots are initiated by a coordinator, which transmits a sequence of commands to each storage node hosting a data object within a group of data objects. The first command prepares a data object for a snapshot. After a data object has been successfully prepared, an acknowledgment is sent to the coordinator. Once all appropriate acknowledgments are received, the coordinator sends a command to confirm that a snapshot has been created for each data object in the respective group. After receiving this confirmation, the coordinator takes action to confirm or record the successful completion of the group-consistent snapshot.10-08-2009
20100191895SYSTEM, TEST APPARATUS AND RELAY APPARATUS - There is a system comprising a requesting device including a block generating section which generates an access information block storing access information including a target address of an access target and an access command indicating content to be executed for the access target in each of a plurality of accesses, and a block transmitting section which transmits the generated access information block to a relay apparatus, the relay apparatus including a block receiving section which receives the access information block from the requesting device and an access issuing section which sequentially issues corresponding access to a responding device on the basis of the access information included in the transmitted access information block, and the responding device including an access receiving section which receives each access corresponding to the access information included in the access information block from the relay apparatus and an access processing section which executes an access process for a storage area corresponding to a target address of the received access.07-29-2010
20080313384Method and Device for Separating the Processing of Program Code in a Computer System Having at Least Two Execution Units - A method and a device are provided for separating the processing of program code in a computer system having at least two execution units, in which method and device switching over takes place between at least two operating modes, and a first operating mode corresponds to a comparison mode and a second operating mode corresponds to a performance mode, and the at least two execution units process the same program code in the comparison mode. When there is a switchover from the comparison mode to the performance mode, a separation in the program code takes place in that each execution unit has an identifier assigned to it, and, as a function of the identifier, different program code is assigned to at least two execution units.12-18-2008
20090070516INTEGRATED MEMORY CONTROL APPARATUS - An integrated memory control apparatus including a first interface decoder, a second interface decoder and an interface controller is provided. Wherein, the first interface decoder is coupled to a control chip through a first serial peripheral interface (SPI), the second interface decoder is coupled to a micro-processor unit through a general transmission interface, and the interface controller is coupled to a memory through a second SPI. When the interface controller receives the request signals from the control chip and the micro-processor unit, the control chip may correctly read data from the memory through the first and second SPI. On the other hand, the micro-processor unit may stop reading data from the memory through the general transmission interface. Therefore, the control chip and the micro-processor unit may share the same memory.03-12-2009
20090037642METHOD OF MANAGING AND RESTORING IDENTIFIER OF STORAGE DEVICE AND APPARATUS THEREFOR - A method of managing and restoring an identifier of a storage device and an apparatus therefor are provided. The method includes the operations of generating a storage device identifier; recording the storage device identifier in a non-volatile memory of a host; generating an identifier file including the storage device identifier and a host identifier; and recording the identifier file in the storage device. By doing so, the method and apparatus can efficiently and securely manage the storage device.02-05-2009
20090106480COMPUTER STORAGE DEVICE HAVING SEPARATE READ-ONLY SPACE AND READ-WRITE SPACE, REMOVABLE MEDIA COMPONENT, SYSTEM MANAGEMENT INTERFACE, AND NETWORK INTERFACE - A storage device for use with a computer is disclosed. The storage device includes a processor communicably connected to a computer through a computer interface and a system interface. The computer interface enables communications exclusively between the processor and the computer, while the system interface enables to processor to manage one or more hardware components of the computer. A network interface is also included to enable the processor to communicate over a network with select file servers to the exclusion of other file servers. A storage means is communicably connected to the processor and includes first and second designated storage sections. The processor has read-write access to both storage sections, while the computer has read-only access to the first storage section and read-write access to the second storage section. A removable media storage component is also communicably connected to the processor.04-23-2009
20090307409DEVICE MEMORY MANAGEMENT - Methods, systems, devices, and apparatus, including computer program products, for memory management. Usage data associated with one or more files is identified and stored in a volatile memory of a device. The usage data is maintained in the volatile memory is maintained during and after a reset of the device. After the reset, the usage data can be written to a non-volatile memory.12-10-2009
20090313416Computer main memory incorporating volatile and non-volatile memory - A main memory for a computer system comprises a controller including an interface to one or more processors, non-volatile memory, and volatile memory. The main memory comprises one or more contiguous range of real addresses supported by both the non-volatile memory and the volatile memory. The controller may be incorporated into a mainboard and the non-volatile memory and the volatile memory may comprise pluggable memory modules. Alternatively, the controller may be incorporated into a hybrid pluggable memory module including non-volatile memory and volatile memory. The controller may utilize the volatile memory as a cache for the non-volatile memory. One or more subsets of the non-volatile memory may be configured to contain a system image, an operating system managed emulated disk image, and/or an operating system managed a page-file. The controller may encrypt and/or compress data written to and/or decrypt and/or decompress data read from the non-volatile memory.12-17-2009
20090037640SYSTEMS AND METHODS FOR STORING TEST DATA AND ACCESSING TEST DATA - A system and a method for storing test data are provided. The system includes a memory device and a computer operably communicating with the memory device. The computer is configured to receive test data comprising various data types. The computer is further configured to convert the various data types into 8-bit characters that are stored in a character array. The character array can be stored in a memory device utilizing a single write command.02-05-2009
20080228988METHOD FOR TRANSMITTING CONFIGURATION DATA VIA A CONFIGURATION DATA BUS IN A MEMORY ARRANGEMENT, CONFIGURATION DATA BUS STRUCTURE, MEMORY ARRANGEMENT, AND COMPUTER SYSTEM - A method transmits configuration data in a memory arrangement. The method includes controlling, with a control unit of the memory arrangement, data transmissions via a configuration data bus in the memory arrangement, the controlling including controlling transmitting configuration data of the memory arrangement for storing in at least two register units of the memory arrangement via the configuration data bus from the control unit to each of the at least two register units. The method includes storing, in the at least two register units, the configuration data. The at least two register units have a same bus address identifying the at least two register units on the configuration data bus. The method includes requesting, with the control unit, configuration data stored in the at least two register units. The method includes transmitting, under control of the control unit, the stored configuration data via the configuration data bus from only one of the at least two register units to the control unit.09-18-2008
20080320204MEMORY SYSTEM AND METHOD WITH FLASH MEMORY DEVICE - A memory system is provided which includes a host, a flash memory device, and a dual port memory which exchanges data with the host and the flash memory device. The flash memory device utilizes a portion of the dual port memory as a working memory.12-25-2008
20080228992SYSTEM, METHOD AND APPARATUS FOR ACCELERATING FAST BLOCK DEVICES - A system, method and apparatus directed to fast data storage on a block storage device. New data is written to an empty write block. If the new data is compressible, a compressed version of the new is written into the meta data. A location of the new data is tracked. Meta data associated with the new data is written. A lookup table may be updated based in part on the meta data. The new data may be read based the lookup table configured to map a logical address to a physical address. Disk operations may use state data associated with the meta data to determine the empty write block. A write speed-limit may also be determined based on a lifetime period, a number of life cycles and a device-erase-sector-count for the device. A write speed for the device may be slowed based on the determined write speed-limit.09-18-2008
20080228993WIRELESS DATA COMMUNICATIONS USING FIFO FOR SYNCHRONIZATION MEMORY - A microprocessor system architecture is disclosed which allows for the selective execution of programmed ROM microcode or, alternatively, RAM microcode if there has been a correction or update made to the ROM microcode originally programmed into the system. Patched or updated RAM microcode is utilized or executed only to the extent of changes to the ROM microcode, otherwise the ROM microcode is executed in its normal fashion. When a patch is received, it is loaded into system RAM along with instructions or other appropriate signals to direct the execution of the patched or updated microcode from RAM instead of the existing ROM microcode. Various methods are presented for selecting the execution of the appropriate microcode depending upon whether there have been changes made to it.09-18-2008
20080228990STORAGE APPARATUS HAVING UNUSED PHYSICAL AREA AUTONOMOUS MANAGEMENT FUNCTION - A physical extent assurance unit manages correspondence of a logical disk accessed from a host computer with physical extents. A data pattern generation response unit generates a predetermined data pattern, and returns this data pattern in response to a data request from the host computer. A pattern matching unit checks the data pattern of a storage area every access to storage media or periodically. When the entire area of the assured physical extent defines the predetermined data pattern, the pattern matching unit deletes the logical disk allocation of the assured physical extent.09-18-2008
20080228989METHOD AND DEVICE FOR SECURING THE READING OF A MEMORY - A method reads a datum saved in a memory by selecting an address of the memory in which the datum to be read is saved, reading the datum in the memory at the selected address, saving the datum read in a storage space, and when the memory is not being accessed by a CPU, reading the datum in the memory, reading the datum saved in the storage space, and activating an error signal if the datum read in the memory is different from the datum saved. The method can be applied particularly to the protection of smart card integrated circuits.09-18-2008
20100332723Memory Device and Method for Embedding Host-Identification Information into Content - A memory device and method for embedding host-identification information into content are disclosed. In one embodiment, a memory device is provided comprising a memory operative to store content and a controller in communication with the memory. The controller is operative to receive a credential comprising host-identification information from a host in communication with the memory device, authenticate the host using the credential, receive a request from the host to play content stored in the memory, embed the host-identification information into the content, and send the content with the embedded host-identification information to the host.12-30-2010
20090300267Systems and methods for facilitating profiling of applications for efficient loading - Systems and methods to facilitate profiling of applications for efficient loading are described. A method may include identifying a page fault during execution of an application being loaded into memory. The page fault indicates that an application part to be currently executed has not been loaded in the memory yet. The method may further include collecting page fault data associated with the page fault, and causing the page fault data to be stored in a data store for use by a profiler.12-03-2009
20090300266IDENTIFICATION OF READ/WRITE CHAINS DURING STATIC ANALYSIS OF COMPUTER SOFTWARE - A system for identifying read/write chains in computer software, including a static analysis engine identifying within computer software logical container accesses, a string analyzer configured to at least partly resolve any variables identifying the logical container in any of the accesses by determining a set of potential values of any of the variables, and a Logical Container Access Virtualization component (LCAV) configured to identify the type and scope of any permutations of the accesses, where each of the permutations is defined by substituting any of the potential values for any of the access variables, and identify any read/write chains within the computer software by matching any of the access permutations that read from the logical container with any of the access permutations that write to the logical container if there is an intersection between the scopes of the read and write access permutations.12-03-2009
20090037641Memory controller with multi-protocol interface - A multi-protocol memory controller includes one or more memory channel controllers. Each of the memory channel controllers coupled to a single channel of DIMM, where the DIMM in each single channel operate according to a specific protocol. A protocol engine is coupled to the memory channel controllers. The protocol engine is configurable to accommodate one or more of the specific protocols. Finally, a system interface is coupled to the protocol engine and is configurable to provide electrical power and signaling appropriate for the specific protocols.02-05-2009
20090031071METHOD FOR ACQUIRING RELEVENT INFORMATION TO AN OBJECT USING AN INFORMATION ACCESS TAG - A method for retrieving relevant information about an object is disclosed. An information access tag is associated with the object. Relevant information or data about the object are store on a server. The information access tag comprises a link pointing to the address of the server. When a user uses a mobile electronic device to read the information access tag the link is decoded and the electronic device connects to the server via a network. The relevant information is downloaded and displayed on the electronic device for the user to interact with the information or data.01-29-2009
20090144483DISK ACCESS SYSTEM SWITCHING DEVICE - A disk access system switching device is interposed between a first driver accessing an OS boot disk by use of a first disk access system, a second driver accessing by use of a second disk access system capable of accessing the disk faster than by the first disk access system, and a high-order driver issuing disk access commands to the first and second drivers, wherein the disk access command received from the high-order driver with respect to the boot disk directed to the first driver is transferred to the first driver before an end of initializing the second driver, and the disk access command received from the high-order driver with respect to the boot disk directed to the first driver is transferred to the second driver when detecting the end of initialization of the second driver.06-04-2009
20080209101Storage device control apparatus and control method for the storage device control apparatus - A storage device control apparatus includes a mounting part and an internal connection part. The mounting part can removably mount channel control unit, each with a host interface controller formed therein for receiving data I/O requests, disk control units, each with a disk interface controller formed therein for performing I/O control of the data to storage volumes storing data in response to the data I/O requests, cache memory units, each with a memory formed therein for storing the data, and storage control units, each with the host interface controller, the disk interface controller, and the memory formed therein. The internal connection part connects the channel control units, the disk control units, the cache memory units, and the storage control units in a communicable manner.08-28-2008
20100011148Method and Apparatus to Facilitate Using a Policy to Modify a State-to-State Transition as Comprises a Part of an Agnostic Stored Model - A stored model is comprised of a plurality of candidate contextually-described states along with state-to-state transitions between at least some of this plurality of candidate contextually-described states. This stored model can be agnostic with respect to any particular application. One can then access at least one policy as pertains to a particular application to be effected by that platform and apply that policy to modify at least one of the state-to-state transitions to thereby provide a modified version of the stored model that corresponds in particular to the particular application to be effected. By one approach, the aforementioned policy can comprise, at least in part, an indication of a relative preference as pertains to one or more of the state-to-state transitions. This can comprise, for example, a weighting factor to be applied with respect to one or more of the state-to-state transitions.01-14-2010
20080301353Boosting throughput of a computer file server - A software layer for boosting the throughput of a computer file server by reducing the number of required mechanical accesses to the physical storage is provided. The throughput boost is achieved through the combination of extending the data requests along the file path and inserting double-buffered paths in front of each file accessed. The software layer resides on top of the file system, where it can extend requests along the file path, work with network requests arriving over any network using any protocol, and work with any storage system attached to the server. The software layer can also be used in a server to accelerate requests made by local applications in the server or it may be used in any other computer to accelerate requests made by local applications that require data from local storage.12-04-2008
20080301354Multi-Processor Circuit with Shared Memory Banks - A plurality of processors (12-04-2008
20080250189Circuit and Method for Improving Operation Life of Memory - The present invention relates to a circuit and a method for improving operation life of original various internal or external nonvolatile memories by means of long-life nonvolatile memory chips. In the case that the hardware structure, interface type, packaged type and operation condition of existing various nonvolatile memories are not changed yet, only long-life nonvolatile memory chips are added into original hardware structure, and correspondingly, long-life nonvolatile memory addresses are added into original memory addresses in main boot-block for the memories, the original device driver or operating system is modified, so as to increase operation life of the memories greatly.10-09-2008
20080228991RING BUFFER MANAGEMENT - A method is provided for managing access to a ring buffer, for at least one data transfer channel for a determined amount of data, with this ring buffer comprising a series of buffer sub-areas spaced apart by a memory address offset and ordered from a first buffer sub-area to a last buffer sub-area. A starting address is initialized from a first register storing the value of the memory address of the first buffer sub-area, and a counter is initialized from a second register storing the value of the number of buffer sub-areas in the buffer. The buffer sub-areas are successively accessed, from the first buffer sub-area to the last buffer sub-area, starting from the starting address and as a function of the memory address offset, on the basis of the value of the counter. The initialization and access steps are repeated such that the determined amount of data is transferred.09-18-2008
20080215797Method for storing data in a memory in a distributed automation system and method for coupling and automation component to a distributed automation system - Dynamic access is provided to automation resources, where, in a distributed automation system having a plurality of automation components, a first automation component searching for an automation resource sends a request to the automation system and, for this request, receives a response regarding availability of suitable automation resources from all automation components which it has been possible to reach, and then selects that automation component which has the suitable automation resource and uses the automation resource.09-04-2008
20080215796Virtual Appliance Management - Various approaches for virtual appliance management are described. In one approach a virtual appliance repository stores one or more virtual appliances and is coupled to the host computer via a network. A storage device stores a transceiver program capable when executed on said host computer of requesting and receiving the virtual appliances, and generating for each received virtual appliance a respective local copy on the host computer of each received virtual appliance. The local copy is private to the host computer. The transceiver program further binds the virtual appliances to the host computer and obtains user data relevant to the virtual appliances. The transceiver program runs each of the virtual appliances from the respective private local copies on the host computer.09-04-2008
20080209103Storage device control apparatus, storage device, and data storage control method - A storage device stores data therein corresponding to commands from a host computer and includes a buffer memory temporarily storing the data received from the host computer. A data storage control method for the storage device according to the present invention, sequentially writes the data already temporarily stored in the buffer memory to a storage medium until a specific period elapses since reception of a write command, which is received after vibrations in the storage device are detected. When the specific period elapses, a write command completion response is transmitted to the host computer.08-28-2008
20080201517Method for the conversion of Logical Into Real Block Addresses in Flash Memories - The invention relates to a method for managing memory blocks in a non-volatile memory system comprising individually erasable memory blocks which can be addressed with the aid of real memory block numbers (RBN) and can be addressed by converting the address from a logical block number (LBN) into one of the real memory block numbers, respectively, with the aid of allocator tables (LTP, PTR). The logical block number (LBN) is allocated to a physical memory block number (PBN) via a first table (LTP) while the physical memory block number (PBN) is allocated to a real memory block number (RBN) via a second table (PTR), one or several real memory blocks being addressed with the aid of one physical memory block number (PBN).08-21-2008

Patent applications in class STORAGE ACCESSING AND CONTROL

Patent applications in all subclasses STORAGE ACCESSING AND CONTROL