Class / Patent application number | Description | Number of patent applications / Date published |
711002000 | Addressing extended or expanded memory | 13 |
20080244151 | METHOD AND APPARATUS FOR EMULATING REWRITABLE MEMORY WITH NON-REWRITABLE MEMORY IN AN MCU - An integrated circuit having an embedded multiple time programmable memory includes a processing core for executing stored instructions with a data memory and a non volatile memory. The non-volatile memory block provides for storage of program instructions and includes a plurality of blocks of non-volatile memory, each of which can be written to once and read from many times and each having a size that is equal to or less than a program memory address space addressable by the processing core for output of data there from. It also includes a reserve storage location for storing a status word defining the one of the plurality of blocks addressable by the processing core, the status word operable to be changed in response to external signals when another of the plurality of blocks is to be selected, such that once another of the plurality of blocks is selected, the status word cannot indicate as addressable by the processing core a prior one of the plurality of blocks that was defined by the status word as being previously addressable by the processing core. | 10-02-2008 |
20080263256 | Logic Device with Write Protected Memory Management Unit Registers - A logic device. The logic device includes a control module, a memory management unit, a memory module, and at least one first register. The memory management unit controls flow of software code between the control module and the memory module; the control module programs at least one of the first registers during start-up procedures of the logic device to specify at least one data memory section in the memory module. The memory management unit communicates with the first registers to identify the at least one data memory section, and the memory management unit excludes executable code from storage in the at least one data memory section. After completion of the start-up procedures, the first registers are write protected, thereby preventing subsequent programming of the first registers, and the memory management unit cannot be disabled without shutting down the logic device. | 10-23-2008 |
20080270671 | METHOD FOR INITIATING SYSTEM - A method for initiating a system is provided. In the present invention, a specific data, which is not used for executing an initiating program of an interface device, is moved from a conventional memory to an extended memory temporarily, such that the available space of the conventional memory is increased. As a result, the computer system can have enough conventional memory space for loading and executing the initiating program of the interface device during a Power-On Self Test (POST) so as to achieve the purpose of initiating the system. | 10-30-2008 |
20090019208 | Techniques For Implementing Virtual Storage Devices - Some embodiments include a storage device with a storage medium having a memory capacity. The storage device also includes virtual storage device firmware that is configured to directly respond to commands from a guest operating system in a virtual machine for accesses to a subset of the memory capacity of the storage medium when a virtual storage device is enabled. | 01-15-2009 |
20090313414 | MEMORY MANAGEMENT UNIT AND METHOD OF ACCESSING AN ADDRESS - A memory management unit comprises register and control logic and arranged to support a microprocessor controller unit accessing physical address space via an address bus wherein the microprocessor controller unit comprises a program counter having a first address size, the memory management unit wherein the register and control logic comprises a register having a second address size greater than the first address size and arranged to provide an extended address bus between the microprocessor controller unit and physical address space. | 12-17-2009 |
20110283039 | SEMICONDUCTOR DEVICE - To realize a fast and highly reliable phase-change memory system of low power consumption, a semiconductor device includes: a memory device which includes a first memory array having a first area including a plurality of first memory cells and a second area including a plurality of second memory cells; a controller coupled to the memory device to issue a command to the memory device; and a condition table for storing a plurality of trial writing conditions. The controller performs trial writing in the plurality of second memory cells a plurality of times based on the plurality of trial writing conditions stored in the condition table, and determines writing conditions in the plurality of first memory cells based on a result of the trial writing. The memory device performs writing in the plurality of first memory cells based on the writing conditions instructed from the controller. | 11-17-2011 |
20120137044 | METHOD AND APPARATUS FOR PROVIDING PERSISTENT COMPUTATIONS - An approach is provided for providing persistent computations. A persistent computation manager determines at least one non-volatile memory space of a device. The persistent computation manager also determines at least one other non-volatile memory space of at least one other device. The persistent computation manager further determines to form a persistent memory address space based, at least in part, on the at least one non-volatile memory space and the at least one other non-volatile memory space. | 05-31-2012 |
20130326108 | STORAGE DEVICE AND INFORMATION PROCESSING SYSTEM - A storage device able to make a redundant write operation of unselected data unnecessary and able to optimize an arrangement of pages to a state having a high efficiency for rewriting, wherein the storage device has a first memory unit, a second memory unit having a different access speed from the first memory, and a control circuit, wherein the control circuit has a function of timely moving the stored data in two ways between the first memory unit and the second memory unit having different access speeds in reading or rewriting. | 12-05-2013 |
20150113198 | MEMORY EXTENSION SYSTEM AND METHOD - A memory extension system and method are provided. The system includes a processor, an extended memory, an extended chip, and multiple processor installation positions, where a memory installation position is provided in each processor installation position; the multiple processor installation positions are connected through a QuickPath Interconnect (QPI) interface, the processor is installed in at least one processor installation position, and at least one of the other processor installation positions is used as an extended installation position; the extended chip is installed in at least one extended installation position; and the extended memory is installed in a memory installation position. In this memory extension system, an extended chip is installed in another processor installation position, so that an existing processor can access an extended memory of the extended chip by using the extended chip. Thereby, a memory capacity of the existing processor increases while a processing capability does not increase. | 04-23-2015 |
20150370702 | ADDRESS RANGE TRANSFER FROM FIRST NODE TO SECOND NODE - A group address range is mapped to a memory address range of a nonvolatile memory. A first memory address of the memory address range is to be copied to a volatile memory if the first memory address is mapped to the group address range and a write access is requested for the first memory address. The group address range is transferred from a first node to a second node in response to a synch command. The copied address is to be written the NVM after the group address range is transferred. | 12-24-2015 |
20150370703 | METHOD FOR PROCESSING DATA AND ELECTRONIC DEVICE - A method for processing data and an electronic device are provided. The method includes: assigning first and second address sets in relation to data to be stored in a memory, a predetermined address offset is defined between the first address set and the second address set; writing the data to the first address set in response to a data write command; and reading the data from the second address set in response to a data read command. | 12-24-2015 |
20160054928 | SYSTEMS AND METHODS FOR EXPANDING MEMORY FOR A SYSTEM ON CHIP - Systems and methods are disclosed for expanding memory for a system on chip (SoC). A memory card is loaded in an expandable memory socket electrically and is coupled to a system on chip (SoC) via an expansion bus. The memory card comprises a first volatile memory device. In response to detecting the memory card, an expanded virtual memory map is configured. The expanded virtual memory map comprises a first virtual memory space associated the first volatile memory device and a second virtual memory space associated with a second volatile memory device electrically coupled to the SoC via a memory bus. One or more peripheral images associated with the second virtual memory space are relocated to a first portion of the first virtual memory space. A second portion of the first virtual memory space is configured as a block device for performing swap operations associated with the second virtual memory space. | 02-25-2016 |
20160203077 | VERIFICATION OF MANAGEMENT OF REAL STORAGE VIA MULTI-THREADED THRASHERS IN MULTIPLE ADDRESS SPACES | 07-14-2016 |