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ADDRESSING COMBINED WITH SPECIFIC MEMORY CONFIGURATION OR SYSTEM

Subclass of:

711 - Electrical computers and digital processing systems: memory

Patent class list (only not empty are listed)

Deeper subclasses:

Class / Patent application numberDescriptionNumber of patent applications / Date published
711006000 Virtual machine memory addressing 195
711005000 For multiple memory modules (e.g., banks, interleaved memory) 88
711003000 Addressing cache memories 66
711004000 Dynamic-type storage device (e.g., disk, tape, drum) 17
711002000 Addressing extended or expanded memory 7
Entries
DocumentTitleDate
20110004719Memory Element - Disclosed is memory apparatus (01-06-2011
20090006712DATA ORDERING IN A MULTI-NODE SYSTEM - Methods and apparatuses for data ordering in a multi-node system that supports non-snoop memory transactions.01-01-2009
20110302351SYSTEMS AND METHODS FOR AUTOMATED SENSOR POLLING - A device may include polling logic configured to store a table of received addresses, sequentially receive sensor data from each address in the table via a serial data bus, store the sensor data in a memory, receive an address from a processor via a high speed data bus, and provide stored sensor data from the memory to the processor via a parallel data bus.12-08-2011
20110289255APPARATUSES FOR MANAGING AND ACCESSING FLASH MEMORY MODULE - A method for maintaining address mapping for a flash memory module is disclosed including: recording a first set of addresses corresponding to a first set of sequential logical addresses in a first section of a first addressing block; recording a second set of addresses corresponding to a second set of sequential logical addresses in a second section of the first addressing block; recording a third set of addresses corresponding to a third set of sequential logical addresses in a first section of a second addressing block; and recording a fourth set of addresses corresponding to a fourth set of sequential logical addresses in a second section of the second addressing block; wherein the second set of logical addresses is successive to the first set of logical addresses, and the third set of logical addresses is successive to the second set of logical addresses.11-24-2011
20110296077MEMORY HUB ARCHITECTURE HAVING PROGRAMMABLE LANE WIDTHS - A processor-based system includes a processor coupled to a system controller through a processor bus. The system controller is used to couple at least one input device, at least one output device, and at least one data storage device to the processor. Also coupled to the processor bus is a memory hub controller coupled to a memory hub of at least one memory module having a plurality of memory devices coupled to the memory hub. The memory hub is coupled to the memory hub controller through a downstream bus and an upstream bus. The downstream bus has a width of M bits, and the upstream bus has a width of N bits. Although the sum of M and N is fixed, the individual values of M and N can be adjusted during the operation of the processor-based system to adjust the bandwidths of the downstream bus and the upstream bus.12-01-2011
20120036308SUPPORTING A SECURE READABLE MEMORY REGION FOR PRE-BOOT AND SECURE MODE OPERATIONS - In one embodiment, the present invention includes a method for determining whether an address map of a system includes support for a read only region of system memory, and if so configuring the region and storing protected data in the region. This data, at least some of which can be readable in both trusted and untrusted modes, can be accessed from the read only region during execution of untrusted code. Other embodiments are described and claimed.02-09-2012
20090164696PHYSICAL BLOCK ADDRESSING OF ELECTRONIC MEMORY DEVICES - Systems and/or methods that facilitate accessing data to/from a memory are presented. An electronic memory component can operate with reduced data access times by eliminating/reducing the use of logical block addressing and employing physical block addressing. Data access is thereby directly associated with the physical location of the stored bits and the need to translate between a logical address and the physical address is reduced or eliminated. This can be even more efficient under asymmetric data access patterns. Further, legacy support for logical block addressing can be included to provide backward compatibility, mixed mode operation, or complimentary mode operation.06-25-2009
20090106478Managing Memory Systems Containing Components with Asymmetric Characteristics - A memory controller (MC) is associated with a remapping table to enable access to content in a memory system that includes asymmetric memory. The MC receives a request for a memory read or an Input/Output (I/O) write from a central processing unit (CPU) for a physical address specified by the system's memory management unit (MMU). The CPU uses the MMU to manage memory operations for the CPU, by translating the virtual addresses associated with CPU instructions into physical addresses representing system memory or I/O locations. The MC for asymmetric memories is configured to process the MMU-specified physical addresses as an additional type of virtual addresses, creating a layer of abstraction between the physical address specified by the MMU and the physical memory address with which that address is associated by the MC. The MC shields the CPU from the computational complexities required to implement a memory system with asymmetric components.04-23-2009
20100125694MEMORY DEVICE AND MANAGEMENT METHOD OF MEMORY DEVICE - A memory device and a method for managing the memory device is provided. The memory device includes a flash memory including a plurality of pages, a non-volatile RAM storing a first mapping table between a physical page address and a logical page address for each page of the plurality of pages, and a volatile RAM storing a second mapping table between the physical page address and the logical page address for each page of the plurality of pages.05-20-2010
20100005217MULTI-MODE MEMORY DEVICE AND METHOD - Memory device systems, systems and methods are disclosed, such as those involving a plurality of stacked memory device dice and a logic die connected to each other through a plurality of conductors. The logic die serves, for example, as a memory interface device to a memory access device, such as a processor. The logic die can include a command register that allows selective operation in either of two modes. In a direct mode, conventional command signals as well as row and column address signals are applied to the logic die, and the logic die can essentially couple these signals directly to the memory device dice. In an indirect mode, a packet containing a command and a composite address are applied to the logic die, and the logic die can decode the command and composite address to apply conventional command signals as well as row and column address signals to the memory device dice.01-07-2010
20120117296SYSTEM AND DEVICE HAVING ALTERNATIVE BIT ORGANIZATION - A system is disclosed that includes a first memory device operable according to either a first bit organization or a second bit organization, a second memory device operable according to only the first bit organization, and a memory control unit. The memory control unit is commonly connected to the first and second memory devices via a command/address bus and a portion of a data bus, and is connected to the second memory device via another portion of the data bus.05-10-2012
20120137043SECURITY CONFIGURATION FOR MEMORY ACCESS CONTROL - A system for controlling access to resources in an apparatus when the apparatus is not active. Emerging technologies may allow information to be accessed in an apparatus memory without the operating system of the apparatus facilitating the access. In such instances, a subsystem in the apparatus may become active upon reception of wireless signals, and may grant direct access to memory. An access control configuration for the subsystem may be implemented in order to control memory access even when other software systems are inactive. The subsystem access control configuration may be configured (e.g., by the user) when the apparatus is active, and may be established (e.g., installed or updated) upon subsystem activation.05-31-2012
20120254496METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR STORING A DECISION TREE - At least first nodes and second nodes of a decision tree are stored within a memory of an information handling system. The first nodes include a first parent node and first remaining nodes that descend from the first parent node. The second nodes include a second parent node and second remaining nodes that descend from the second parent node. The first nodes are grouped into a first packed node stored in first physically contiguous locations of the memory. The first nodes are sequenced in the first physically contiguous locations according to respective depth levels of the first nodes within the decision tree. The second nodes are grouped into a second packed node stored in second physically contiguous locations of the memory. The second nodes are sequenced in the second physically contiguous locations according to respective depth levels of the second nodes within the decision tree.10-04-2012
20110238884Memory Controller for Setting Page Length and Memory Cell Density for Semiconductor Memory - A memory controller including a type determining module and a page determining module. The type determining module is configured to determine a type of memory to which the memory controller is connected, wherein the memory includes a memory block comprising a plurality of pages, and each page includes a plurality of memory cells. The page configure module is configured to generate a memory map based on the determined type of the memory. The memory map specifies, for each page, (i) a number of memory cells for storing data, and (ii) a number of memory cells for storing overhead. The number of memory cells for storing data and the number of memory cells for storing overhead in a first page is configurable to be different from the number of memory cells for storing data and the number of memory cells for storing overhead in a second page.09-29-2011
20080250188Memory Controller, Nonvolatile Storage, Nonvolatile Storage System, and Memory Control Method - A physical area management table (105) and a pointer table (106) are stored in a nonvolatile auxiliary storage memory (107). When a logical-physical conversion table (108) is updated (restored) in a main storage memory (140), the restored area is determined in a re-arrangement way by the pointer table to avoid rewrite concentration on the main storage memory (140). Immediately after data is written in the main storage memory (140), the state of the physical block on the physical area management table (105) is updated. Consequently, even if power interruption occurs, it is possible to reliably judge if the data is valid or not.10-09-2008

Patent applications in class ADDRESSING COMBINED WITH SPECIFIC MEMORY CONFIGURATION OR SYSTEM

Patent applications in all subclasses ADDRESSING COMBINED WITH SPECIFIC MEMORY CONFIGURATION OR SYSTEM