Class / Patent application number | Description | Number of patent applications / Date published |
710264000 | Interrupt prioritizing | 65 |
20080244138 | MICROCOMPUTER - A microcomputer includes a plurality of processing circuits for executing a plurality of interrupt processes each corresponding to one of a first plurality of causes) a cause register circuit for representing whether each of the first plurality of causes has been solved or unsolved, a processing circuit selection register for defining a plurality of correspondences each between one of the first plurality of causes and one of the plurality of processing circuits responsible to execute one the interrupt processes corresponding to the one of the first plurality of causes, and for outputting, in response to occurrence of one of the causes, to the plurality of processing circuits an interrupt signal representing that one of the interrupt processes should be executed, a vector signal indicating an area in which a content of the one of the interrupt processes corresponding to the one of the causes, and a first selection signal representing which one of the processing circuits should execute the one of the interrupt processes corresponding to the one of the causes, and a processing circuit selection circuit for outputting, in response to the first selection signal, to the processing circuit indicated by the first selection signal, a second selection signal representing that the processing circuit is selected. | 10-02-2008 |
20080288694 | METHOD FOR DYNAMICALLY ARRANGING INTERRUPT PINS - A method for dynamically arranging interrupt pins is provided, which is suitable for arranging a plurality of interrupt pins of a control chip. In this method, a number of interrupts sent from each of a plurality of device paths in a unit time is detected. The device paths are sorted according to the interrupt numbers thereof. Then, from the one in the head of the sequence, the devices paths are arranged to the interrupt pins. Herein, when arranging a device path, an interrupt checking number required to check the device path sending the interrupt every time an interrupt is produced in each of the interrupt pins is calculated. Then, when arranging the next device path, the device path is arranged to the interrupt pin with the least interrupt checking number. | 11-20-2008 |
20080294826 | APPARATUS AND METHOD TO CONTROL ACCESS TO STORED INFORMATION - A method is disclosed to control access to stored information. The method supplies a control unit in communication with a computing device and in communication with stored information. If the computing device requests access to that stored information, the method determines if access to the stored information is available. When access to the stored information becomes available, then the method reserves a communication pathway interconnecting the control unit and the requesting computing device, thereby disallowing the sending of non-MPLF unsolicited status via that reserved communication pathway, and provides a message to the computing device, using that reserved communication pathway, granting access to the stored information. | 11-27-2008 |
20090157935 | Efficient interrupt message definition - An efficient interrupt system for a multi-processor computer. Devices interrupt a processor or group of processors using pre-defined message address and data payload communicated with a memory write transaction over a PCI, PCI-X, or PCI Express bus. The devices are configured with messages that each targets a processor. Upon receiving a command to perform an operation, the device may receive an indication of a preferred message to use to interrupt a processor upon completion of that operation. The efficiency with which each interrupt is handled and the overall efficiency of operation of the computer is increased by defining messages for the devices within the computer so that each device contains messages targeting processors distributed across groups of processors, with each group representing processors in close proximity. In selecting target processors for messages, processors are selected to spread processing across the processor groups and across processors within each group. | 06-18-2009 |
20090157936 | INTERRUPT MORPHING AND CONFIGURATION, CIRCUITS, SYSTEMS, AND PROCESSES - An electronic configuration circuit includes a processing circuit ( | 06-18-2009 |
20090248935 | Hardware Managed Context Sensitive Interrupt Priority Level Control - A flexible interrupt controller circuit and methodology are provided which use an interrupt circuit ( | 10-01-2009 |
20100057967 | RECORDING MEDIUM WITH LOAD DISTRIBUTION PROGRAM RECORDED THEREIN AND LOAD DISTRIBUTION APPARATUS - A recording medium with a load distribution program recorded therein for causing a computer system to execute the following processing includes: acquiring, at every first timing, a processor load status and an input/output device load status; referencing, at every second timing, a load distribution policy and a load distribution executing condition for distributing interrupts and using the processor usage rate by the application job; determining whether a processor satisfying the load distribution initiating condition is present; referencing the processor load statuses and input/output device load statuses when a processor satisfying the load distribution initiating condition is present; calculating processor usage rates of all input/output devices interrupting the processor; determining a processor and an input/output device satisfying the load distribution executing condition based on the calculated processor usage rate; and changing the interrupt destination processor of the input/output device satisfying the load distribution executing condition. | 03-04-2010 |
20100070669 | SMART PROFILER - A method, system, and computer usable program product for a smart profiler are provided in the illustrative embodiments. An allowable number of interrupts for use by a profiler application is determined. A count number for a counter is determined. The counter is configured to count occurrences of an event in a data processing system up to the count number. An interrupt is raised when the counter has counted the occurrences of the event up to the count number. The interrupt is processed. The counting of occurrences of the event, raising the interrupt, and processing the interrupt are repeated for a predetermined time. A decision is made whether a total number of interrupts raised in the predetermined period differs from the allowable number. The count number of the counter is adjusted to cause the difference between the total number of interrupts in the predetermined period and the allowable number to decrease. | 03-18-2010 |
20100088445 | DATA PROCESSING SYSTEM AND SEMICONDUTOR INTEGRATED CIRCUIT - The present invention provides a data processing system having excellent immediacy of interrupting process. Different interrupt request signals are supplied from a circuit module which can be commonly used by a plurality of central processing units to a plurality of interrupt controllers assigned to central processing units, respectively. In response to the input interrupt request signal, each of the interrupt controllers notifies the corresponding central processing unit of an interrupt. The circuit module selects an interrupt controller for supplying an interrupt request signal from the plural interrupt controllers. For example, the circuit module identifies a central processing unit which instructed a start request and supplies an interrupt request signal to an interrupt controller corresponding to the central processing unit. The burden of the interrupting process of the single central processing unit can be lessened. In addition, since the interrupting process in the single central processing unit is not necessary, interruption response of another central processing unit is increased. | 04-08-2010 |
20100095039 | INTERRUPT ACKNOWLEDGMENT IN A DATA PROCESSING SYSTEM - A data processing system has an interrupt controller which provides an interrupt request along with a corresponding interrupt identifier and a corresponding interrupt vector to a processor. If the processor accepts the interrupt, the processor returns the same interrupt identifier value by way of interrupt identifier, along with interrupt acknowledge, to the interrupt controller. An interrupt taken/not taken indicator may also be provided. The communications interface used to coordinate interrupt processing between the interrupt controller and the processor may be asynchronous. | 04-15-2010 |
20100122008 | INTERRUPT MORPHING AND CONFIGURATION, CIRCUITS, SYSTEMS, AND PROCESSES - An electronic configuration circuit includes a processing circuit ( | 05-13-2010 |
20100180060 | Managing Message Signaled Interrupts - Managing Message Signaled Interrupts (MSIs). For example, a method of managing MSI requests in a computing system may include receiving a plurality of MSI requests from one or more components of the computing system; directing data of the plurality of MSI requests to be stored sequentially, according to a First In First Out (FIFO) order, in successive entries of a FIFO structure defined in a main memory of the computing system; and directing a processor of the computing system to retrieve data of one or more of the plurality of MSI requests from the FIFO structure to be processed according to the FIFO order. Other embodiments are described and claimed. | 07-15-2010 |
20100191886 | Resource-limited electronic device comprising means for prioritizing services - An electronic device, including: a storage device operable to store first priority data associated with a first signal, and second priority data associated with a second signal; and a processor operable to compare the first priority data and the second priority data, and when the second priority data is indicative of a higher priority than the first priority data, to use the second signal while suspending use of the first signal. | 07-29-2010 |
20100241778 | INTERRUPT CONTROL APPARATUS AND IMAGE FORMING APPARATUS - An interrupt control apparatus includes: an interrupt request supply unit that supplies interrupt request information; a processing unit that performs interrupt processing based on the interrupt request information supplied by the interrupt request supply unit; and a time measuring unit that is used to measure an elapse of a predefined time period from a time point when the interrupt request supply unit starts to supply the interrupt request information, wherein: even if new interrupt cause information is stored during the time when the time measuring unit is measuring the elapse of the predefined time period, the interrupt request supply unit does not supply interrupt request information based on the new interrupt cause information to the processing unit; and after the elapsed time measured by the time measuring unit reaches the predefined time period, the interrupt request supply unit supplies the interrupt request information to the processing unit. | 09-23-2010 |
20100306433 | INTERRUPT-NOTIFICATION CONTROL UNIT, SEMICONDUCTOR INTEGRATED CIRCUIT AND METHODS THEREFOR - An interrupt-notification control unit that receives interrupt requests from a plurality of interrupt dispatchers and sends the received interrupt requests together to a processor, where the interrupt-notification control unit determines a correlation among the interrupt requests to control a time to send the interrupt requests together to the processor. | 12-02-2010 |
20110016247 | MULTIPROCESSOR SYSTEM AND MULTIPROCESSOR SYSTEM INTERRUPT CONTROL METHOD - A multiprocessor system, which improves processing efficiency of an entire system while concurrently securing appropriate interrupt responsivity according to interrupt priority, includes a plurality of processors each including a register, a plurality of I/O devices, and an interrupt generation device. A multiprocessor system interrupt control method includes: setting, for the register, interrupt permissibility indicating permissibility for an interrupt to be permitted by a corresponding processor; receiving an interrupt request from one of the I/O devices, using the interrupt generation device having a memory which holds the interrupt priority indicating the priority for the interrupt from each I/O device, and notifying the interrupt request from I/O device and the interrupt priority to the plurality of processors; and causing one of the processors that includes the register holding interrupt permissibility lower than the interrupt priority to accept the interrupt request. | 01-20-2011 |
20110040913 | USER-LEVEL INTERRUPT MECHANISM FOR MULTI-CORE ARCHITECTURES - A method includes accepting for a first processor core of a plurality of processor cores in a multi-core system, a user-level interrupt indicated by a user-level interrupt message when an interrupt domain of an application thread executing on the first processor core and a recipient identifier of the application thread executing on the first processor core match corresponding fields in the user-level interrupt message. | 02-17-2011 |
20110055446 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - When an interrupt event occurs, an interrupt request signal and interrupt data are output from an arbitrary peripheral module to an interrupt control circuit. The interrupt control circuit stores the received interrupt data in a register and performs a priority determination of the interrupt request signal. Subsequently, the interrupt control circuit transfers the determination result as an interrupt request signal via a dedicated wiring and the interrupt data of the register via a dedicated bus to the CPU, respectively. Upon reception of the interrupt request, the CPU reads a corresponding interrupt processing function from a ROM and performs the processing of the interrupt data based on the input interrupt request signal. | 03-03-2011 |
20110173362 | HARDWARE VIRTUALIZATION FOR MEDIA PROCESSING - Methods and systems for implementing virtual processors are disclosed. For example, in an embodiment a processing apparatus configured to act as a plurality of virtual processors includes a first virtual program space that includes a first program execution memory, the first program execution memory including code to run a non-real-time operating system capable of supporting a one or more non-real-time applications, a second virtual program space that includes a second program execution memory, the second program execution memory including code to run one or more real-time processes, and a central processing unit (CPU) configured to operate in a first operating mode and a second operating mode, the CPU being configured to perform operating system and application activities using the first virtual program space for the first operating mode without using the second virtual program space and without appreciably interfering with the one or more real-time processes that are running in the second operating mode. | 07-14-2011 |
20110179209 | Terminal Apparatus and Method for Controlling Processing of an Interrupt Event - In a terminal apparatus, the central control section | 07-21-2011 |
20120036300 | CONTROLLER AND ELECTRIC CONTROL UNIT INCLUDING THE SAME - A controller capable of inhibiting storage of prescribed information associated with a control operation when the control operation cannot be normally performed, and resuming the storage immediately after the control operation has again become able to be normally performed. The controller includes determining means for determining whether or not the control operation can be normally performed on the basis of a power level of electrical power supplied to the controller, write-inhibiting means for setting a storage area for storing the information to a write-inhibited area in cases where it is determined that the control operation cannot be normally performed, and releasing means for releasing, as an interrupt process higher in priority than any other process, the write inhibited area in cases where it is determined after the setting of the storage area to the write-inhibited area that the control operation can be normally performed. | 02-09-2012 |
20120072632 | Deterministic and non-Deterministic Execution in One Processor - An application in a data processing system may automatically select when it needs determinism and when it does not. The ability to have the system automatically select when to use each allows optimum system performance while maintaining hard real-time requirements when needed. | 03-22-2012 |
20120131248 | MANAGING COMPRESSED MEMORY USING TIERED INTERRUPTS - Systems and methods to manage memory are provided. A particular method may include initiating a memory compression operation. The method may further include initiating a first interrupt configured to affect a first process executing on a processor in response to a first detected memory level. A second initiated interrupt may be configured to affect the first process executing on the processor in response to a second detected memory level, and a third interrupt may be initiated to affect the first process executing on the processor in response to a third detected memory level. At least of the first, the second, and the third detected memory levels are affected by the memory compression operation. | 05-24-2012 |
20120226842 | ENHANCED PRIORITISING AND UNIFYING INTERRUPT CONTROLLER - An enhanced interrupt controller is provided which is able to receive both hardware-generated and software-generated request signals. Data associated with each received interrupt or request signal is stored in a storage unit within the enhanced interrupt controller in an order which depends on the priority level of the data and, for data of the same level of priority, on the chronological order of receipt. The enhanced interrupt controller instructs the processor, with which it is in communication, to read the stored data from the controller in the stored order ensuring that data of higher priority is read before data of lower priority. A method of routing hardware-generated and software-generated signals from an enhanced interrupt controller to a processor is also disclosed. | 09-06-2012 |
20120226843 | Method and Computer System for Processing Data in a Memory - The invention discloses a method for processing data in a memory for a computer system. The method comprises receiving a first interrupt for triggering a first job, backing up data corresponding to a second interrupt in the memory when a priority degree of the first interrupt is higher than a priority degree of the second interrupt corresponding to a second job currently being executed by the computer system, executing the first job corresponding to the first interrupt, and restoring the data corresponding to the second interrupt to the memory after the first job corresponding to the first interrupt is finished and continue executing the second job corresponding to the second interrupt. | 09-06-2012 |
20120317323 | Processing Interrupt Requests According to a Priority Scheme - An embodiment of the invention relates to an electronic device for processing interrupt requests. Interrupt requests that have the highest priority level are identified out of a plurality of interrupt requests. A priority word corresponding to a priority level is assigned to each interrupt request. The highest bit level of the bits at the most significant bit position of the priority words is identified. The bit level of the bit at the most significant bit position is compared with the highest bit level at this bit position. The priority words are then evaluated and compared consecutively and bit-by-bit. Priority words having a bit level at the respective bit position that corresponds to the highest bit level are further processed whereas priority words having a different bit level at the respected bit position are discarded. | 12-13-2012 |
20130054859 | MANAGING OVERHEAD ASSOCIATED WITH SERVICE REQUESTS VIA SOFTWARE GENERATED INTERRUPTS - An application process operates at a privilege level lower than that of the kernel code of the operating system in which the process executes. When the application process requires performance of an operating system service for which the process lacks sufficient privileges to perform directly, rather than repeatedly requesting the service by issuing separate software interrupts, the process instead accumulates the data corresponding to the different service requests in a data container block and defers performance of the service. Whenever the process needs to complete the service, rather than deferring its performance, the process issues a single software interrupt that causes the kernel to use the accumulated data in the data container block to perform each of the N accumulated service requests. This reduces the number of interrupts that must be handled from N to one, thereby greatly reducing the overhead imposed by interrupt handling. | 02-28-2013 |
20130086290 | Low Latency Two-Level Interrupt Controller Interface to Multi-Threaded Processor - Systems and method for reducing interrupt latency time in a multi-threaded processor. A first interrupt controller is coupled to the multi-threaded processor. A second interrupt controller is configured to communicate a first interrupt and a first vector identifier to the first interrupt controller, wherein the first interrupt controller is configured to process the first interrupt and the first vector identifier and send the processed interrupt to a thread in the multi-threaded processor. Logic is configured to determine when the multi-threaded processor is ready to receive a second interrupt. A dedicated line is used to communicate an indication to the second interrupt controller that the multi-threaded processor is ready to receive the second interrupt. | 04-04-2013 |
20130138849 | MULTICORE PROCESSOR SYSTEM, COMPUTER PRODUCT, ASSIGNING METHOD, AND CONTROL METHOD - A multicore processor system includes core configured to detect a process assignment instruction; acquire a remaining time obtained by subtracting a processing time of interrupt processing assigned to an arbitrary core of a multicore processor from a period that is from a calling time of the interrupt processing to an execution time limit of the interrupt processing, upon detecting the process assignment instruction; judge if the remaining time acquired at the acquiring is greater than or equal to a processing time of processing defined to limit an interrupt in the process; and assign the process to the arbitrary core, upon judging that the remaining time is greater than or equal to the processing time of the processing defined to limit an interrupt in the process. | 05-30-2013 |
20130159578 | System and method for Automatic Hardware Interrupt Handling - A processing system is provided consisting of an interrupt pin, multiple registers, a stack pointer, and an automatic interrupt system. The multiple registers store a number of processor states values. When the system detects an interrupt on the interrupt pin the system prepares to enter an exception mode where the automatic interrupt system causes an interrupt vector to be fetched, the stack pointer to be updated, and the processor state values to be read in parallel from the registers and stored in memory locations based on the updated stack pointer, prior to the execution of an interrupt service routine. A method for automatic hardware interrupt handling is also presented. | 06-20-2013 |
20130179614 | Command Abort to Reduce Latency in Flash Memory Access - In an embodiment, a peripheral component may include a command queue configured to store a set of commands to perform a transfer on a peripheral interface. Some of the commands may be long-latency commands, and the long-latency commands may be aborted to perform higher priority commands. In an embodiment, each command may have an abort attribute assigned by software which indicates whether or not the command is abortable. If a higher priority command needs to be performed while the long-latency command is in progress, the command may be aborted. In an embodiment, software may write an abort field in a control register to cause the long-latency command to be aborted. | 07-11-2013 |
20130205058 | MULTI-THREAD PROCESSOR AND ITS INTERRUPT PROCESSING METHOD - A multi-thread processor includes a plurality of hardware threads each of which generates an independent instruction flow, a thread scheduler that manages in what order a plurality of hardware threads are processed with a pre-established schedule, and an interrupt controller that receives an input interrupt request signal and assigns the interrupt request to an associated hardware thread, wherein the interrupt controller comprises a register in which information is stored for each channel of an interrupt request signal, and the information includes information regarding to which one or more than one of the plurality of hardware threads the interrupt request signal is associated. | 08-08-2013 |
20130262726 | TASK BASED MESSAGE SIGNALED INTERRUPT - Methods and apparatuses are provided for servicing an interrupt in a computer system. The method includes a device driver receiving an interrupt request. The device driver is responsive to the interrupt request to store interrupt data in a portion of the memory. The interrupt data includes identification of at least one processor of the plurality of processors capable of servicing the interrupt request; priority of the interrupt request; a thread context; and an address for instructions to service the interrupt request. The device driver then instructs the peripheral device to issue a memory write to the plurality of processors so that each may determine if it can use the thread context and the instructions to service the interrupt. A computer system is provided with the hardware needed to perform the method. | 10-03-2013 |
20130304958 | System and Method for Processing Device with Differentiated Execution Mode - In accordance with an embodiment of the present invention, a method of operating a system includes operating in a first operating mode to not permit access to an address range, receiving a priority interrupt (PI) signal. The method further includes operating in a second operating mode to permit access to the address range in response to receiving the PI signal. | 11-14-2013 |
20140047149 | Interrupt Priority Management Using Partition-Based Priority Blocking Processor Registers - A method and circuit for a data processing system ( | 02-13-2014 |
20140047150 | Processor Interrupt Interface with Interrupt Partitioning and Virtualization Enhancements - A method and circuit for a data processing system ( | 02-13-2014 |
20140108690 | System And Method for Operating System Aware Low Latency Interrupt Handling - The exemplary embodiments described herein relate to systems and methods for operating system aware low latency handling. One embodiment relates to a non-transitory computer readable storage medium including a set of instructions executable by a processor, the set of instructions, when executed, resulting in a performance of receiving a fast interrupt request asserted by a hardware device while the processor is executing within a kernel critical section, executing a fast interrupt handler at a first priority level, raising a second priority level interrupt by the fast interrupt handler based on the fast interrupt request, wherein the second priority level interrupt invokes a kernel service and processing the second priority level interrupt once the processor has executed the kernel critical section. | 04-17-2014 |
20140181344 | Detection of Abnormal Operation Caused by Interrupt Processing - A controller for controlling interrupt processing in a multiple-interrupt system is provided. The controller includes multiple watchdog timers (WDTs), each provided for each of interrupt priorities. The controller includes interrupt priority selectors, each of which receives each interrupt request signal and outputs an activation signal to a corresponding WDT according to the priority of the interrupt request signal. The controller includes an interrupt processing circuit, which when a WDT has timed out, outputs, to a processor, an interrupt request signal having a priority one or more levels higher than the priority corresponding to the WDT. When multiple causes of interrupt are assigned to one of the interrupt priorities, the interrupt processing circuit gives priority to an interrupt request signal caused by the timeout of a WDT lower in priority level than the interrupt priority to detect that an abnormal operation has occurred in interrupt processing having the lower level priority. | 06-26-2014 |
20140201412 | DATA PROCESSING APPARATUS - A concurrent flag set (changed from a first state to a second state) when generating a plurality of event signals at the same time from one circuit module that operates synchronously is prepared. When it is determined that the concurrent event signals are generated with reference to the concurrent flag, processing corresponding to the concurrent event signals is executed in order of priority, or requests for ordering or starting the processing are issued in order of priority. | 07-17-2014 |
20140237150 | ELECTRONIC COMPUTER AND INTERRUPT CONTROL METHOD - An electronic computer includes a processor that executes a thread and an interrupt handler, and monitors load of the processor; and an interrupt controller that is configured to determine a notification timing for an interrupt request to call the interrupt handler, the notification timing being determined based on the load and an effect of execution of the interrupt handler on user performance of the thread under execution by the processor; and notify the processor of the interrupt request, based on the notification timing. When the load is higher than a threshold, the interrupt controller sets the notification timing for an interrupt request that does not affect the user performance, to be later than the notification timing for an interrupt request that affects the user performance. Based on notification of the interrupt request, the processor calls and executes the interrupt handler that corresponds to the interrupt request. | 08-21-2014 |
20140281088 | SYSTEM AND METHOD FOR DETERMINISTIC TIME PARTITIONING OF ASYNCHRONOUS TASKS IN A COMPUTING ENVIRONMENT - A method of scheduling and controlling asynchronous tasks to provide deterministic behavior in time-partitioned operating systems, such as an ARINC 653 partitioned operating environment. The asynchronous tasks are allocated CPU time in a deterministic but dynamically decreasing manner. In one embodiment, the asynchronous tasks may occur in any order within a major time frame (that is, their sequencing is not statically deterministic); however, the dynamic time allotment prevents any task from overrunning its allotment and prevents any task from interfering with other tasks (whether synchronous or asynchronous). | 09-18-2014 |
20140359185 | SYSTEMS AND METHODS FOR ADAPTIVE INTERRUPT COALESCING IN A CONVERGED NETWORK - An information handling system is provided. The information handling system includes an information handling device having one or more processors in communication with a network interface card. The network interface card includes one or more interfaces for receiving frames the information handling device is coupled to an external network device. The device also includes a memory that is in communication with the one or more processors and stores a classification matrix. The classification matrix is used to generate a current interrupt throttling rate from a plurality of candidate interrupt throttling rates that are applied to the received frames according to at least two properties of each frame of the received frames. A method for providing adaptive interrupt coalescing is also provided. | 12-04-2014 |
20140359186 | System and Method for a Processing Device with a Priority Interrupt - In accordance with an embodiment, a method of operating a processor includes operating in a first operating mode that prohibits access to a protected memory area, receiving a priority interrupt (PI) signal, operating in a second operating mode in response to receiving the PI signal, and executing a first routine by asserting a semi-privileged interrupt (SPI). Access to the protected memory area is permitted in the second operating mode, and the first routine operates in the second operating mode and is interruptible by the PI signal. | 12-04-2014 |
20150074310 | HARDWARE VIRTUALIZATION FOR MEDIA PROCESSING - Methods and systems for implementing virtual processors are disclosed. For example, in an embodiment a processing apparatus configured to act as a plurality of virtual processors includes a first virtual program space that includes a first program execution memory, the first program execution memory including code to run a non-real-time operating system capable of supporting a one or more non-real-time applications, a second virtual program space that includes a second program execution memory, the second program execution memory including code to run one or more real-time processes, and a central processing unit (CPU) configured to operate in a first operating mode and a second operating mode, the CPU being configured to perform operating system and application activities using the first virtual program space for the first operating mode without using the second virtual program space and without appreciably interfering with the one or more real-time processes that are running in the second operating mode. | 03-12-2015 |
20150081943 | VIRTUAL MACHINE SUSPENSION IN CHECKPOINT SYSTEM - Performing a checkpoint includes determining a checkpoint boundary of the checkpoint for a virtual machine, wherein the virtual machine has a first virtual processor, determining a scheduled hypervisor interrupt for the first virtual processor, and adjusting, by operation of one or more computer processors, the scheduled hypervisor interrupt to before or substantially at the checkpoint boundary. | 03-19-2015 |
20150106543 | System and Method for Processing Device with Differentiated Execution Mode - In accordance with an embodiment of the present invention, a method of operating a system includes operating in a first operating mode to not permit access to an address range, receiving a priority interrupt (PI) signal. The method further includes operating in a second operating mode to permit access to the address range in response to receiving the PI signal. | 04-16-2015 |
20150127866 | Secure, Fast and Normal Virtual Interrupt Direct Assignment in a Virtualized Interrupt Controller in a Mobile System-On-Chip - Aspects include apparatuses and methods for secure, fast and normal virtual interrupt direct assignment managing secure and non-secure, virtual and physical interrupts by processor having a plurality of execution environments, including a trusted (secure) and a non-secure execution environment. An interrupt controller may identify a security group value for an interrupt and direct secure interrupts to the trusted execution environment. The interrupt controller may identify a direct assignment value for the non-secure interrupts indicating whether the non-secure interrupt is owned by a high level operating system (HLOS) Guest or a virtual machine manager (VMM), and whether it is a fast or a normal virtual interrupt. The interrupt controller may direct the HLOS Guest owned interrupt to the HLOS Guest while bypassing the VMM. When the HLOS Guest in unavailable, the interrupt may be directed to the VMM to attempt to pass the interrupt to the HLOS Guest until successful. | 05-07-2015 |
20150378945 | EVADING FLOATING INTERRUPTION WHILE IN THE TRANSACTIONAL-EXECUTION MODE - A computer implemented method and system for evading a floating interruption while a processor is in a transactional-execution (TX) mode. A floating interruption request can be detected, by a floating interrupt control mechanism, for a plurality of processors for execution by any one of the plurality of processors. An evasive action can be initiated for at least one of the plurality of processors in a transactional-execution mode, for evading the floating interruption such that another one of the plurality of processors can execute the floating interruption. | 12-31-2015 |
20160085700 | HARDWARE TIMER BASED MECHANISM TO CHECK INTERRUPT DISABLED DURATION - In one embodiment, a timer apparatus is configured to time a duration in which interrupts are disabled on a processor. The apparatus includes an input to receive a start signal indicating that an interrupt on a processor is disabled, a counter to determine the duration in which interrupts are disabled, and an output to signal a timer event based on the counter. The processor may be configured to trigger a hardware exception in response to the timer event signal. When the interrupts are re-enabled on the processor, the counter of the apparatus may be disabled. | 03-24-2016 |
20160117273 | MULTIPLE-INTERRUPT PROPAGATION SCHEME IN A NETWORK ASIC - Embodiments of the present invention are directed to a multiple-interrupt propagation scheme, which is an automated mechanism for the specification and creation of interrupts. Interrupts originating at leaf nodes of a network chip are categorized into different service levels according to their interrupt types and are propagated to a master of the network chip via a manager. For each interrupt, depending on its service level, the manager either instantaneously propagates the interrupt or delays propagation of the interrupt to the master. The master forwards the interrupts to different destinations. A destination can be a processing element that is located on the network chip or externally on a different chip. | 04-28-2016 |
20160179721 | DELIVERING INTERRUPTS TO USER-LEVEL APPLICATIONS | 06-23-2016 |
20160378698 | INSTRUCTION AND LOGIC FOR REAL-TIME BEHAVIOR OF INTERRUPTS - A processor includes a core and an interrupt control unit. The core includes logic to handle an interrupt. The interrupt control unit includes logic to receive another interrupt. Furthermore, the interrupt control unit includes logic to conditionally dispatch the new interrupt to the core based upon priority of the interrupts and time spent by the new interrupt waiting for dispatch to the core. | 12-29-2016 |
20220138133 | DELIVERING INTERRUPTS TO USER-LEVEL APPLICATIONS - Systems and methods for delivering interrupts to user-level applications. An example processing system comprises: a memory configured to store a plurality of user-level APIC data structures and a plurality of user-level interrupt handler address data structures corresponding to a plurality of user-level applications being executed by the processing system; and a processing core configured, responsive to receiving a notification of a user-level interrupt, to: set a pending interrupt bit flag having a position defined by an identifier of the user-level interrupt in a user-level APIC data structure associated with a user-level application that is currently being executed by the processing core, and invoke a user-level interrupt handler identified by a user-level interrupt handler address data structure associated with the user-level application, for a pending user-level interrupt having a highest priority among one or more pending user-level interrupts identified by the user-level APIC data structure. | 05-05-2022 |
710265000 | Variable | 12 |
20090013118 | PRIORITIZATION OF INTERRUPTS IN A STORAGE CONTROLLER BASED ON INTERRUPT CONTROL DIRECTIVES RECEIVED FROM HOSTS - A storage controller receives an interrupt control directive from a host. The storage controller generates a first plurality of interrupts, in response to access requests received from the host for at least one storage device coupled to the storage controller, wherein the first plurality of interrupts indicates whether access to the at least one storage device is allowed to the host. The storage controller generates a second plurality of interrupts, wherein the second plurality of interrupts comprises unsolicited interrupts for the host that are different from the first plurality of interrupts. The storage controller controls how many of the first plurality of interrupts and how many of the second plurality interrupts to send to the host, based on the received interrupt control directive. | 01-08-2009 |
20090013119 | PRIORITIZATION OF INTERRUPTS IN A STORAGE CONTROLLER BASED ON INTERRUPT CONTROL DIRECTIVES RECEIVED FROM HOSTS - A storage controller receives an interrupt control directive from a host. The storage controller generates a first plurality of interrupts, in response to access requests received from the host for at least one storage device coupled to the storage controller, wherein the first plurality of interrupts indicates whether access to the at least one storage device is allowed to the host. The storage controller generates a second plurality of interrupts, wherein the second plurality of interrupts comprises unsolicited interrupts for the host that are different from the first plurality of interrupts. The storage controller controls how many of the first plurality of interrupts and how many of the second plurality interrupts to send to the host, based on the received interrupt control directive. | 01-08-2009 |
20090132744 | Interrupt jitter suppression - A data processing apparatus comprises a processing unit which is responsive to a plurality of interrupt signals to carry out a corresponding interrupt routine. On receipt of an interrupt signal, the processing unit stores data values from a plurality of registers onto a data stack and carries out the corresponding interrupt routine. Thereafter the processor returns the data values from the data stack to the registers and carries on the processing it was performing when the interrupt was received. If a higher priority interrupt is received whilst the processor is transferring register values to or from the data stack, that transferral is abandoned and the processing unit immediately begins transferring data values from the registers to the data stack in response to the higher priority interrupt. | 05-21-2009 |
20100262742 | Interrupt Arbitration For Multiprocessors - Technologies are generally described herein for handling interrupts within a multiprocessor computing system. Upon receiving an interrupt at the multiprocessor computing system, a priority level associated with an interrupt handler for the interrupt can be determined. Current task priority levels can be queried from one or more processors of the multiprocessor computing system. One of the processors can be assigned to execute the interrupt handler in response to the processor having a lowest current task priority level. Interrupt arbitration can schedule and communicate interrupt responses among processor cores in a multiprocessor computing system. Arbitration can query information about current task or thread priorities from a set of processor cores upon receiving an interrupt. The processor core that is currently idle or running the lowest priority task may be selected to service the interrupt. | 10-14-2010 |
20110022759 | MULTIPROCESSOR SYSTEM - The present invention provides a technique capable of processing a plurality of interrupt causes sharing one interrupt request in different processors. An interrupt controller outputs an interrupt request when the interrupt request shared by a plurality of interrupt causes is notified. The interrupt request output by the interrupt controller is accepted by one of the processors. The processor accepting the interrupt request determines whether the interrupt cause that the processor must process has occurred, executes an interrupt processing when such interrupt cause has occurred, and notifies the generation of the interrupt request to another processor that processes another interrupt cause of the plurality of interrupt causes sharing the interrupt request when the relevant interrupt cause has not occurred. | 01-27-2011 |
20120303850 | SYSTEMS AND METHODS FOR ADVANCED INTERRUPT SCHEDULING AND PRIORITY PROCESSING IN A STORAGE SYSTEM ENVIRONMENT - Methods and systems for advanced interrupt processing and scheduling are provided. The system comprises a memory operable to store interrupt priorities, an interface, and a processor operable to acquire incoming interrupts and to handle the incoming interrupts according to the interrupt priorities. The processor is also operable to receive interrupt processing criteria from the interface (sent, for example, from a device not directly coupled with the system), and to modify the interrupt priorities of the memory based upon the interrupt processing criteria without losing incoming processing requests for the system. Additionally, the processor is operable to process the incoming interrupts according to the modified interrupt priorities responsive to modifying the interrupt priorities. | 11-29-2012 |
20130031287 | INTERRUPT CONTROL APPARATUS AND INTERRUPT CONTROL METHOD - An interrupt control apparatus and interrupt control method reduce situations in which the output of interrupt information is suspended and thus reduce stress caused in a user, without missing the appropriate output timing for interrupt information having a high priority level. A priority level setting unit raises the value of a priority level for an interrupt voice message during a period in which the interrupt voice message is being outputted, and a voice output control unit, when interrupts from two or more overlapping interrupt voice messages occurs, carries out control in accordance with priority levels set for each of the two or more interrupt voice messages so that the interrupt voice message having the higher priority level value is preferentially outputted. | 01-31-2013 |
20130159579 | VIRTUALIZING INTERRUPT PRIORITY AND DELIVERY - Embodiments of processors, methods, and systems for virtualizing interrupt prioritization and delivery are disclosed. In one embodiment, a processor includes instruction hardware and execution hardware. The instruction hardware is to receive a plurality of instructions, including a first instruction to transfer the processor from a root mode to a non-root mode for executing guest software in a virtual machine, wherein the processor is to return to the root mode upon the detection of any of a plurality of virtual machine exit events. The execution hardware is to execute the first instruction, execution of the first instruction to include determining a first virtual processor-priority value and storing the first virtual processor-priority value in a virtual copy of a processor-priority field, where the virtual copy of the processor-priority field is a virtual resource corresponding to a physical resource associated with an interrupt controller. | 06-20-2013 |
20130339563 | SYSTEMS AND METHODS FOR ADVANCED INTERRUPT SCHEDULING AND PRIORITY PROCESSING IN A STORAGE SYSTEM ENVIRONMENT - Methods and systems for advanced interrupt processing and scheduling are provided. The system comprises a memory operable to store interrupt priorities, an interface, and a processor operable to acquire incoming interrupts and to handle the incoming interrupts according to the interrupt priorities. The processor is also operable to receive interrupt processing criteria from the interface (sent, for example, from a device not directly coupled with the system), and to modify the interrupt priorities of the memory based upon the interrupt processing criteria without losing incoming processing requests for the system. Additionally, the processor is operable to process the incoming interrupts according to the modified interrupt priorities responsive to modifying the interrupt priorities. | 12-19-2013 |
20140122760 | COMMUNICATION OF MESSAGE SIGNALLED INTERRUPTS - A global interrupt number space | 05-01-2014 |
20140164662 | METHODS AND APPARATUS FOR INTERLEAVING PRIORITIES OF A PLURALITY OF VIRTUAL PROCESSORS - Methods and apparatus for interleaving priorities of a plurality of virtual processors are disclosed. A hypervisor assigns a base priority to each virtual processor and schedules one or more virtual processors to execute on one or more physical processors based on the current priority associated with each virtual processor. When the hypervisor receives an indication from one of the virtual processors that its current priority may be temporarily reduced, the hypervisor lowers the current priority of that virtual processor. The hypervisor then schedules another virtual processor to execute on a physical processor instead of the virtual processor with the temporarily reduced priority. When the hypervisor receives an interrupt for the virtual processor with the lowered priority, the hypervisor raises the priority of that virtual processor and schedules the virtual processor with the restored priority to execute on a physical processor so that processor can handle the interrupt. | 06-12-2014 |
20150058510 | VIRTUALIZING INTERRUPT PRIORITY AND DELIVERY - Embodiments of processors, methods, and systems for virtualizing interrupt prioritization and delivery are disclosed. In one embodiment, a processor includes instruction hardware and execution hardware. The instruction hardware is to receive a plurality of instructions, including a first instruction to transfer the processor from a root mode to a non-root mode for executing guest software in a virtual machine, wherein the processor is to return to the root mode upon the detection of any of a plurality of virtual machine exit events. The execution hardware is to execute the first instruction, execution of the first instruction to include determining a first virtual processor-priority value and storing the first virtual processor-priority value in a virtual copy of a processor-priority field, where the virtual copy of the processor-priority field is a virtual resource corresponding to a physical resource associated with an interrupt controller. | 02-26-2015 |