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710 - Electrical computers and digital data processing systems: input/output

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Class / Patent application numberDescriptionNumber of patent applications / Date published
710267000 Processor status 52
710264000 Interrupt prioritizing 39
710262000 Interrupt inhibiting or masking 36
710269000 Handling vector 29
710263000 Interrupt queuing 27
710266000 Programmable interrupt processing 25
710261000 Multimode interrupt processing 19
710268000 Source or destination identifier 9
20090193168INTERRUPT MITIGATION ON MULTIPLE NETWORK ADAPTERS - A method, information processing system, and computer readable medium, mitigate processor assignments. A first processor in a plurality of processors is assigned to a first communication port in a plurality of communication ports. An interrupt associated with the first communication port is generated. An assignment of a processor other than the first processor to handle the interrupt is inhibited.07-30-2009
20100106875Technique for communicating interrupts in a computer system - A technique to enable efficient interrupt communication within a computer system. In one embodiment, an advanced programmable interrupt controller (APIC) is interfaced via a set of of bits within an APIC interface register using various interface instructions or operations, without using memory-mapped input/output (MMIO).04-29-2010
20100106874Packet Filter Optimization For Network Interfaces - A method and apparatus to reduce the transaction overhead involved with packet I/O on a host bus without sacrificing the latency of packets of important traffic types is described. This involves determining whether a packet is to be aggregated in response to receiving the packet in a receive buffer. If it is determined that the packet should not be aggregated, a host system may be interrupted to indicate availability of the received packet. Subsequently, the packet may be forwarded to an interrupted system via a local bus directly from a receiving buffer without being stored in a local storage. If it is determined that a packet is to be aggregated, it may be stored in a queue in local storage. Subsequently, it may be sent to a host system with a group of other frames using a single bus transaction to eliminate overhead.04-29-2010
20090125660Interrupt and Exception Handling for Multi-Streaming Digital Processors - A multi-streaming processor has a plurality of streams for streaming one or more instruction threads, a set of functional resources for processing instructions from streams, and interrupt handler logic. The logic detects and maps interrupts and exceptions to one or more specific streams. In some embodiments, one interrupt or exception may be mapped to two or more streams, and in others two or more interrupts or exceptions may be mapped to one stream. Mapping may be static and determined at processor design, programmable, with data stored and amendable, or conditional and dynamic, the interrupt logic executing an algorithm sensitive to variables to determine the mapping. Interrupts may be external interrupts generated by devices external to the processor software (internal) interrupts generated by active streams, or conditional, based on variables. After interrupts are acknowledged, streams to which interrupts or exceptions are mapped are vectored to appropriate service routines. In a synchronous method, no vectoring occurs until all streams to which an interrupt is mapped acknowledge the interrupt.05-14-2009
20100095037Information Processing Apparatus, Information Processing Method, and Program - The present invention relates to an information processing apparatus, an information processing method and a program for simplifying an interrupt process to reduce time needed for the interrupt process. If it is determined in step S04-15-2010
20090113100Logic gateway circuit for bus that supports multiple interrupt request signals - A logic gateway circuit is provided for a bus to support multiple interrupt request signals, including an output OR gate having a plurality of input terminals and an interrupt request signal output signal, an inverter having an input terminal connected to the interrupt request signal output terminal of the output OR gate and an output terminal, and a plurality of gateway circuits to respectively and selectively device-end interrupt request signals generated by a plurality of target devices to transmit through the gateway circuit to the output OR gate or to queue the device-end interrupt request signals in the gateway circuit. Each gateway circuit includes an AND gate and an OR gate, wherein the OR gate bases on the states of an output terminal of the AND gate and the interrupt request signal output terminal of the output OR gate to generate a gateway signal to a gateway signal input terminal of the AND gate.04-30-2009
20130073765SEMICONDUCTOR DEVICE AND DATA PROCESSOR - In a data processor having a bus controller that performs timing control of access from the CPU operated in synchronization with a high-speed first clock signal to a peripheral circuit operated in synchronization with a low-speed second clock signal, a timing control circuit is provided between the peripheral circuit and the bus controller, and the bus controller causes, in response to a read instruction from the peripheral circuit, the timing control circuit to output data held by the peripheral circuit to the bus controller in synchronization with the cycle of the high-speed clock signal, causes the timing control circuit to start, in response to a write instruction directed to the peripheral circuit, writing into the peripheral circuit in synchronization with the cycle of the high-speed clock signal, and terminates the writing in synchronization with the cycle of the low-speed clock signal.03-21-2013
20130067132Increasing Turbo Mode Residency Of A Processor - In one embodiment, the present invention includes a method for accessing a task stored in an entry of a task queue that identifies the task and a first core of a processor on which the task has been scheduled, reassigning the task to a coldest idle core of the processor, and sending the task to the coldest idle core and maintaining the processor in a turbo mode. Other embodiments are described and claimed.03-14-2013
20090013117SYSTEM AND METHOD FOR GENERATING INTERRUPT - A system and a method for generating an interrupt are provided. In the interrupt generating method, a time-out mechanism is executed by a second network component of a computer system after a packet processing action is finished. An interrupt is generated by the second network component only if a first network component of the computer system does not execute a polling action during a predefined period after the time-out mechanism is processed. Thus, it is not necessary to generate the interrupt every time after processing a network packet, so that less interrupts are generated and accordingly the loading of the computer system is reduced. Moreover, the reaction time of the computer system is kept to ensure the efficiency of the computer system.01-08-2009
20110087815Interrupt Masking for Multi-Core Processors - Technologies are generally described herein for handling interrupts within a multi-core processor. A core specific interrupt mask (“CIM”) can be adapted to influence the assignment of interrupts to particular processor cores in the multi-core processor. Available processor cores can be identified by evaluating the CIM. An interrupt with an interrupt service routine (“ISR”) that is received by the multi-core processor can be assigned to one or more of the available processor cores identified by the CIM.04-14-2011
20080276026SELECTIVE DEACTIVATION OF PROCESSOR CORES IN MULTIPLE PROCESSOR CORE SYSTEMS - A method includes applying a voltage to a first processor core of a plurality of processor cores to deactivate the first processor core, the voltage less than a retention voltage of the first processor core. The application of the voltage can be in response to a software setting. The software setting can be configured via a user input, a software application, an operating system, or a BIOS setting. Alternately, the application of the voltage can be in response to a permanent hardware setting, such as the state of a fuse associated with the first processor core.11-06-2008
20090271548INTERRUPT RESPONSE CONTROL APPARATUS AND METHOD THEREFOR - An interrupt response control apparatus comprises an input for receiving an interrupt request. A response monitoring module is arranged to detect performance of a first function in response to the interrupt request. A timer is used to determine whether a period of time has elapsed, and if the interrupt request has not been serviced by the first function within the elapsed period of time, a function initiation module initiates a second function in response to failure to provide the first function within the elapsed period of time.10-29-2009
20100095038Driver Transparent Message Signaled Interrupts - Machine-readable media, methods, and apparatus are described to issue message signaled interrupts. In some disclosed embodiments, a device generates message signaled interrupts in a manner that enables a device driver written with level-sensitive semantics to properly service the device despite the edge-triggered characteristics message signaled interrupts.04-15-2010
20120036298INTERRUPT SOURCE CONTROLLER WITH SCALABLE STATE STRUCTURES - A data processing system includes a processor core, a system memory, coupled to the processor core, that includes an interrupt data structure including a plurality of entries each associated with a respective one of a plurality of interrupts. An input/output (I/O) subsystem including at least one I/O host bridge and a plurality of partitionable endpoints (PEs) each having an associated PE number. The I/O host bridge, responsive to receiving a message signaled interrupt (MSI) including at least a message address, determines from the message address a system memory address of a particular entry among the plurality of entries in the interrupt data structure, accesses the particular entry, and, based upon contents of the particular entry, validates authorization of an interrupt source to issue the MSI and presents an interrupt associated with the particular entry for service.02-09-2012
20100122006INTERRUPT DETECTION APPARATUS AND INFORMATION PROCESSING SYSTEM - An interrupt detection apparatus includes a detection address region storing unit configured to store an address region, as a detection address region, to be detected in accordance with a first interrupt message having address information, an issuance interrupt information storing unit configured to store address information of a second interrupt message as issuance interrupt information, an interrupt message detection unit configured to determine that the first interrupt message corresponds to the detection address region, and an interrupt issuing unit configured to issue the second interrupt message having the issuance interrupt information when it is determined that the first interrupt message corresponds to the detection address region.05-13-2010
20100088444CENTRAL PROCESSING UNIT MEASUREMENT FACILITY - A measurement sampling facility takes snapshots of the central processing unit (CPU) on which it is executing at specified sampling intervals to collect data relating to tasks executing on the CPU. The collected data is stored in a buffer, and at selected times, an interrupt is provided to remove data from the buffer to enable reuse thereof. The interrupt is not taken after each sample, but in sufficient time to remove the data and minimize data loss.04-08-2010
20090089471Process Suspension Through Process Model Design - Various implementations are disclosed for designing a process model that includes a task, the task associated with a potential suspension, e.g., in response to an error or other exception. At least one suspension task may be provided in parallel with the task to form a parallel combination thereof within the process model. A first control task, e.g., an AND split task, may be provided prior to the parallel combination, and a second control task, e.g., a synchronize/merge task, may be provided subsequent to the parallel combination, the first control task and the second control task configured to activate and join, respectively, the task and the at least one suspension task during execution of the process model.04-02-2009
20090089470INTERRUPT BALANCING FOR MULTI-CORE AND POWER - A method and apparatus for balancing power savings and performance in handling interrupts is herein described. When an amount of interrupt activity is above a threshold, a performance mode of interrupt handling is selected. During the performance mode, interrupts and/or interrupt sources are distributed among multiple physical sockets, i.e. multiple physical processors. However, if the interrupt activity is below a threshold for a number of periods, which denotes low interrupt activity, then a power save mode is selected. Here, interrupts and/or sources are primarily assigned to a single processor to allow other physical processors to save power. Furthermore, after interrupts are assigned to a physical processor, the interrupts may be further distributed among cache domains of the processor. In addition, high activity classes, interrupt sources, interrupts, or categories may be further assigned to specific processing elements for servicing.04-02-2009
20110173361INFORMATION PROCESSING APPARATUS AND EXCEPTION CONTROL CIRCUIT - An information processing apparatus performs switching between an exception handler and normal processing. The information processing apparatus includes a processor; a data processing unit that performs particular processing upon receiving a processing request from the processor; an interrupt controller that issues an interrupt request to the processor; and an exception control unit that controls the interrupt controller, wherein the data processing unit is connected with the exception control unit via a dedicated line. The data processing unit includes a notification unit that notifies, via the dedicated line, the exception control unit of status information indicating current status of the data processing unit, and based on the notified status information and setup information set by the processor, the exception control unit judges whether to cause the interrupt controller to issue an interrupt request to execute an exception handler to the processor.07-14-2011
20110173360SYSTEM AND METHOD OF MONITORING A CENTRAL PROCESSING UNIT IN REAL TIME - A method of monitoring one or more central processing units in real time is disclosed. The method may include monitoring state data associated with the one or more CPUs in real-time, filtering the state data, and at least partially based on filtered state data, selectively altering one or more system settings.07-14-2011
20080244136Integrated Circuit and Method For Transaction Abortion - An integrated circuit having a plurality of processing modules (M, S) and an interconnect means (N) for coupling said plurality of processing modules (M, S) and for enabling a device-level communication based on transactions between said plurality of processing modules (M, S) is provided. At least one first processing module (M) issues at least one transaction towards at least one second processing module (S). Said integrated circuit comprise at least one transaction abortion unit (TAU) for aborting at least one transaction issued from said first module (M) by receiving an abort request (abt) issued by said first module (M), by initiating a discard of said at least one transaction to be aborted, and by issuing a response (abt ack) indicating the success/failure of the requested transaction abortion.10-02-2008
20080288692SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MICROCOMPUTER - It is intended to improve the efficiency of request retransmission. A high-speed serial interface block is provided which enables split-transaction communication performed through the issuing of a response from a completer to a request issued by a requester. The high-speed serial interface block mentioned above is provided with a reception butter for retrieving received data and with a control unit for causing execution of a process which is performed in the case where there is no response from the completer mentioned above within a predetermined time when the reception buffer mentioned above has overflown. When the reception buffer mentioned above has overflown, a process of issuing a time out even within a prescribed time for time-out determination is allowed to improve the efficiency of request retransmission.11-20-2008
20080235425MANAGING INPUT/OUTPUT INTERRUPTIONS IN NON-DEDICATED INTERRUPTION HARDWARE ENVIRONMENTS - Input/output interruptions are managed in computing environments that do not use dedicated per-guest interruption hardware to present interruptions. Dispatchable guest programs in the environment receive I/O interruptions directly without hypervisor intervention. This is facilitated by using one or more interruption controls stored in memory and associated with each guest program. For those guest programs that are not currently dispatchable, interruptions can be posted for the guests and notifications to the hypervisor can be aggregated. The hypervisor can then process a plurality of notifications for the plurality of guests in a single invocation.09-25-2008
20100146179INTERRUPTION CONTROL SYSTEM AND METHOD - An interruption control system includes two sense elements, a microprocessor, and a controller. The microprocessor includes two registers, two flip-latches, a multiplexer, and a microcontroller. Each sense element senses a device and sends a sense signal. The corresponding register receives and stores the sense signal. The microcontroller sets an identity signal for each of the registers and controls the each of the flip-latch units to record a data signal of the device. The multiplexer alternately outputs the ID signals and the corresponding data signals to the microcontroller to encode into a datagram. The microcontroller sends the datagram to the controller. The controller is interrupted for decoding the datagram.06-10-2010
20090327552Method and System for Secure Communication Between Processor Partitions - A system and method for writing, by a sender, a message into blocks of a memory space, the memory space being shared by the sender of the message and a receiver of the message, and sending, by the sender, an interrupt corresponding to the message.12-31-2009
20110225336IMAGE FORMING APPARATUS AND CONTROL METHOD THEREOF - An image forming apparatus and a control method thereof. The image forming apparatus includes a plurality of image processors which process an image to be formed on a printing medium corresponding to a plurality of colors, a processor which executes an interrupt routine with respect to the plurality of image processors, and a controller which generates an interrupt signal and transmits the interrupt signal to the processor if at least two of the plurality of image processors generate interrupt requests so that the processor executes the interrupt routine.09-15-2011
20110145457APPARATUS AND METHOD FOR MEASURING THE PERFORMANCE OF EMBEDDED DEVICES - The apparatus for measuring the performance of embedded devices includes: a transceiver that transmits and receives data to and from the embedded devices; an interrupt generator that generates interrupt signal; a controller that controls the interrupt generator and the transceiver to generate the interrupt signal and transmits them to the embedded devices and performs a control to calculate real-time performance when the response signal to the interrupt signal are received from the embedded device through the transceiver; and a calculator that calculates the real-time performance of the embedded devices based on the interrupt signal generating time and the response signal receiving time.06-16-2011
20090210599Electronic Circuit - An electronic circuit comprises a bus (08-20-2009
20080307140SIDEBAND SIGNAL FOR USB WITH INTERRUPT CAPABILITY - The invention provides for a sideband signal for the USB that has real-time interrupt capabilities. A system and method for hardware detection of an interrupt signal provides for the ability to superimpose a high frequency interrupt signal on a USB power line for transmission to a controller. Alternatively, an overcurrent flow may be generated from a peripheral device and detected by an overflow current detector on the USB. In response, the overflow current detector may output an interrupt/overflow current detection signal to the controller.12-11-2008
20100191885Guest Interrupt Controllers for Each Processor to Aid Interrupt Virtualization - In one embodiment, a system comprises a processor, a first interrupt controller coupled to the processor, and a second interrupt controller coupled to the processor. The first interrupt controller is configured to signal the processor for an interrupt in response to receiving a first interrupt message communicating a first interrupt that is targeted at a host in the system. The second interrupt controller is configured to signal the processor for an interrupt in response to receiving a second interrupt message communicating a second interrupt that is targeted at a guest that is controlled by the host and that is executable on the processor.07-29-2010
20100262738COMMAND AND INTERRUPT GROUPING FOR A DATA STORAGE DEVICE - A data storage device may include multiple memory chips and a controller that is operably coupled to the memory chips and that is arranged and configured to receive a group of commands from a host, where each of the commands in the group includes a same group number to identify the commands as part of the group, process the group of the commands using the memory chips and generate and send a single interrupt to the host when the group of the commands completes processing.10-14-2010
20100262739IDENTIFIER ASSOCIATED WITH MEMORY LOCATIONS FOR MANAGING MEMORY ACCESSES - Embodiments of apparatuses, articles, methods, and systems for associating identifiers with memory locations for controlling memory accesses are generally described herein. Other embodiments may be described and claimed.10-14-2010
20100262737DYNAMIC, LOCAL RETRIGGERED INTERRUPT ROUTING DISCOVERY METHOD - In some embodiments, the invention involves a dynamic interrupt route discovery method with local APIC (Advanced Programmable Interrupt Controller) retriggering to accommodate architectures that are not PC/AT compatible. In a mobile Internet device (MID) General Purpose Input/Output (GPIO) pins are dynamically allocated and IRQs are retriggered by a GPIO driver to multiplex the requests to an appropriate device. Other embodiments are described and claimed.10-14-2010
20090327551Methods and Media for Managing Interruption of the Out of Box Experience - A method for managing interruption of an out of box experience for an information handling system (IHS) whereby the method includes writing a flag to storage device, wherein the storage device is coupled to a processor within the IHS and executing an interruption handling sequence at the processor within the IHS, wherein the processor is operable to read the flag in the storage device as an input to the interruption handling sequence.12-31-2009
20090077292DATA PROCESSING APPARATUS, METHOD OF CONTROLLING TERMINATION VOLTAGE OF DATA PROCESSING APPARATUS, AND IMAGE FORMING APPARATUS - A processing unit carries out a predetermined data processing on the data in a storage unit. The storage unit is connected to the processing unit with a plurality of connecting lines. A voltage generating unit is connected to each of the connecting lines via a corresponding termination resistor and that generates a termination voltage to be applied to the connecting lines. An interrupting unit is connected between the connecting lines and the termination resistors, and it applies or does not apply the termination voltage to the connecting lines depending on a data processing state of the processing unit.03-19-2009
20100250811INTERRUPT CONTROLLER AND IMAGE-FORMING DEVICE - An interrupt controller includes: a timer that repeatedly measures a predesignated length of time; an interrupt request unit that, when data is received by a receiving unit while the timer is measuring the length of time, outputs an interrupt request after measurement of the length of time is completed; a measurement unit that measures a frequency of data reception of the receiving unit; and an updating unit that changes the length of time measured by the timer so as to be shorter than the predesignated length of time when the frequency of reception measured by the measurement unit exceeds a threshold frequency.09-30-2010
20100250810INTERRUPT-DRIVEN LINK STATUS FEEDBACK MECHANISM FOR EMBEDDED SWITCHES - A computer implemented method, a tangible computer readable medium, and a data processing system intelligently propagate link status information received by a blade server to the various ports of an embedded multi-port switch. The link status of a switch port in an external switch module can be communicated to the operating systems of individual blade servers that are affected by that link status. When an external switch module is unplugged from a server blade chassis, the bus controller broadcasts a link down event, such as a link down interrupt, to the individual server blades where it is received by the embedded multi-port switch for those server blades. The embedded multi-port switch translates the link down interrupt into a hardware link down event, and forwards the hardware link down event to the other elements connected to the embedded multi-port switch.09-30-2010
20100235557COMPUTER AND CONTROL METHOD FOR INTERRUPTING MACHINE OPERATION - A computer that receives a first instruction for interrupting or stopping operation of the virtual machine; that obtains a duration time corresponding to the virtual machine for which the first instruction is received; that determines whether a second instruction for operating the virtual machine has been received during the obtained duration time; and that determines whether to output a third instruction for interrupting or stopping operation of the computer based at least on whether the second instruction for operating the virtual machine has been received during the obtained duration time.09-16-2010
20100122005Method and System for Detecting Interrups From Detachable Electronic Accessories Or Peripherals - Aspects of a method and system for detecting interrupts from detachable electronic accessories or peripherals are provided. In this regard, a hardware audio CODEC may be operable to compare a voltage on one or more biased pins of an accessory or peripheral port to one or more reference voltages and filter one or more output signals generated from the comparison. When an accessory or peripheral is coupled to the accessory or peripheral port, interrupts from the accessory or peripheral may be detected based on results of the comparison and/or the filtering. An interrupt may be detected when the voltage on the one or more pins may be below the one or more reference voltages. An interrupt may be detected when the voltage on the one or more pins may be below the one or more reference voltages for a plurality of consecutive clock cycles.05-13-2010
20090037630INFORMATION PROCESSING APPARATUS AND SMI PROCESSING METHOD THEREOF - An information processing apparatus includes: a CPU; a controller including a signal transmission unit configured to supply an SMI (system management interrupt) signal to the CPU; a multifunctional device having a plurality of functions each potentially causing an SMI; and a plurality of signal lines provided between the controller and the multifunctional device. Each of the signal lines corresponds to one of the plurality of functions and is configured to send a notification of occurrence of an SMI event from the multifunctional device to the controller.02-05-2009
20100325328PORTABLE TERMINAL, SERVER, AND METHOD FOR REALIZING FUNCTION OF PORTABLE TERMINAL USING NETWORK - A portable terminal, capable of accessing to a software executing server having a hardware access layer in which the hardware of a predetermined portable terminal is virtualized, wherein the server executes a virtual portable terminal program realizing a predetermined function of a portable terminal in response to a request from the portable terminal. The portable terminal comprises: a terminal-end hardware access layer that receives a hardware access instruction issued by a virtual portable terminal program executed by the software executing server to the hardware access layer in a hardware access command capable of containing a plurality of hardware access instructions.12-23-2010
20110022758METHOD AND SYSTEM FOR PROCESSING FRAMES IN STORAGE CONTROLLERS - Method and system for transferring data between a computing system and a storage device is provided. The system includes a storage controller including a frame snooper module that detects a TMR and generates a pause signal to a channel that stops the channel from sending any non-data frames to a buffer memory, wherein the channel continues to receive and process data frames while the channel is stopped from sending the command frames to the buffer memory; a counter for counting TMRs; and logic for generating an interrupt if a number of TMRs received exceeds a certain threshold value. The method includes detecting a TMR generating a command to stop a channel from receiving non-data frames while continuing to receive data frames from a Fibre Channel interface; and generating an interrupt to a processor after a certain number of TMRs are received.01-27-2011
20110113173PROCESSING SYSTEM WITH EXTERNAL MEMORY ACCESS CONTROL - A method for executing a processing routine that utilizes an external memory is provided. The processing routine requires more than one external memory access. The method comprises the step of distributing the external memory access after a predetermined number of external memory accesses.05-12-2011
20100153604DATA EXCHANGE BETWEEN A HANDHELD DEVICE AND ANOTHER COMPUTER SYSTEM USING AN EXCHANGE MANAGER VIA SYNCHRONIZATION - A method and electronic system for exchanging data between a handheld device and another computer system are described. A data file is transferred to the handheld device using the install application of a synchronization manager. The transferred file is stored as a digital stream file with its native data encoding. After synchronization, a message is sent to notify the exchange manager about the data file. The exchange manager then uses an application registry to identify the application program that corresponds to the file stream based on the extension of the stream file. The pertinent application program is then invoked and the stream file is dispatched to the application for processing. During processing, the pertinent application then formats the stream file such that the data file becomes a record within the database file that is associated with the pertinent application.06-17-2010
20110087814Enhanced I/O Performance in a Multi-Processor System Via Interrupt Affinity Schemes - Disclosed herein is a method for improving Input/Output (I/O) performance in a host system having multiple CPUs. Under this method, various interrupt affinity schemes are provided, which associate multiple processors, interrupts, and I/O channels for sending the interrupts, thereby allowing the interrupts to be almost evenly loaded among the multiple I/O channels and processors. Also, data locality (“warm cache”) can be achieved through the interrupt affinity schemes that associate each interrupt to its source processor, namely, the processor originating the I/O request that results in the interrupt.04-14-2011
20100138579NETWORK ADAPTOR OPTIMIZATION AND INTERRUPT REDUCTION - A method and system are disclosed for network adaptor optimization and interrupt reduction. The method may generate an immediate I/O interrupt notification to a host device driver in response to receiving data from a network. The method may also update an inbound buffer list based on the received data in the inbound buffer queue. Furthermore, the method may set the buffer state from an empty state to a primed state to indicate that the received data is available for processing. The method may also build an outbound buffer list based on outgoing data and add the outgoing data to an outbound buffer queue. Furthermore, the method may set a buffer state from an empty state to a primed state to indicate that the outgoing data is prepared for transmitting and signal a network adaptor with a notification signal.06-03-2010
20110145458METHODS AND SYSTEMS FOR SERVICING INTERRUPTS GENERATED RESPONSIVE TO ACTUATION OF HARDWARE, VIA VIRTUAL FIRMWARE - The methods and systems described herein describe methods and systems for forwarding an interrupt that is generated by hardware to virtual firmware executing on a virtual machine. A control program receives an interrupt generated by hardware connected to the computing device. The control program forwards the interrupt to virtual firmware executed by a virtual machine executed by the processor of the computing device. The virtual machine receives the interrupt from the virtual firmware and requests, of the virtual firmware by the virtual machine and responsive to receiving the interrupt, objects and methods associated with the interrupt. The control program receives from the virtual firmware, the request for objects and methods associated with the interrupt. The control program extracts, from an ACPI of firmware of the computing device, objects and methods associated with the interrupt and forwards the extracted objects and methods to the virtual machine.06-16-2011
20100241776DEVICE AND METHOD FOR MANIPULATING COMMUNICATION MESSAGES - A device for manipulating an operating state of a deterministic communication system is provided, which communication system includes a physical data bus, a plurality of nodes connected thereto, and an arrangement for transmitting messages in message frames at fixedly predefined communication cycles. The device is situated in the data bus between at least one node, from whose point of view the operating state of the communication system is manipulated, and the other nodes of the communication system. To make any desired manipulation of the operating state of the communication system possible, the manipulation device includes an arrangement for short-circuiting the data bus (09-23-2010
20110087816COMPUTER SYSTEM AND CONTROL METHOD THEREOF - A computer system and a control method thereof, the computer system including: a processor which executes a program; a communication unit which communicates with an external device; a main body which is provided with the processor. A cover which can be opened and shut with regard to the main body; an open/shut sensor which senses whether the cover is open or shut; and a controller which interrupts an operation of the communication unit if the open/shut sensor senses that the cover is shut.04-14-2011
20090307403SYSTEM FOR EXECUTING SYSTEM MANAGEMENT INTERRUPTS AND METHODS THEREOF - An information handling system includes a first processor device to execute a handler in response to a system management interrupt (SMI). While the first processor device executes the SMI handler, a second processor device of the information handling system can continue to execute software and perform other operations in a normal mode. When the first processor device accesses a shared resource in executing the SMI handler, an SMI trap for the shared resource is enabled. In response to the second processor device triggering the SMI trap by accessing the shared resource, the second processor device enters an SMI mode, thereby suspending execution of software and other operations. Accordingly, a second processor device is allowed to continue normal operations while a first processor device executes an SMI handler, improving system efficiency while preventing shared resource conflicts.12-10-2009
20090216928SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR PROVIDING A NEW QUIESCE STATE - A system, method and computer program product for providing a new quiesce state. The method includes receiving a quiesce request at a system controller from an initiating processor. The quiesce request is sent to a plurality of processors. Notification is received at the system controller that the processors have finished purging their translation look aside buffers (TLBs). A fast quiesce reset command is received at the system controller from the initiating processor once updates to the system resources are complete. It is indicated to the processors that the block translation restriction can be dropped in response to receiving the fast quiesce reset command, thereby allowing the processors to continue processing without block translation restrictions.08-27-2009
20110082958Micro Controller Unit (MCU) Capable of Increasing Data Retention Time and Method of Driving the MCU - A method of operating a micro controller unit including maintaining a stop mode operation when a battery level detected in response to a first interrupt signal input from an external source is in a predetermined low voltage level range during the stop mode operation, and performing a normal operation corresponding to a second interrupt signal input from the external when a battery voltage level detected in response to the second interrupt signal is higher than the highest voltage level belonging to the predetermined low voltage level range.04-07-2011
20110072180INTERRUPT ON/OFF MANAGEMENT APPARATUS AND METHOD FOR MULTI-CORE PROCESSOR - Provided are an interrupt on/off management apparatus and method for a multi-core processor having a plurality of central processing unit (CPU) cores. The interrupt on/off management apparatus manages the multi-core processor such that at least one of two or more CPU cores included in a target CPU set can execute an urgent interrupt. For example, the interrupt on/off management apparatus controls the movement of each CPU core from a critical section to a non-critical section such that at least one of the CPU cores is located in the non-critical section. The critical section may include an interrupt-disabled section or a kernel non-preemptible section, and the non-critical section may include an interrupt-enabled section or include both of the interrupt-enabled section and a kernel preemptible section.03-24-2011
20080228979Trigger core - A method to detect an event between a data source and a data sink using a trigger core is described herein. The method comprises monitoring control lines and an associated data stream for a programmable pattern, wherein the pattern is one or more of a condition, state or event. The method further comprises generating an indication by updating a status register, sending an interrupt or asserting a control line upon a pattern match.09-18-2008
20110055445Digital Signal Processing Systems - A signal processing system may include a multiply-accumulate (MAC) unit to generate output data by performing multiply-accumulate operations on first and second input data in response to a stream of MAC instruction words, where the MAC unit is pipelined to enable it to perform a multiply-accumulate operation in response to each MAC instruction word. The system may also include an instruction generator to generate the stream of MAC instruction words by performing loop expansion on a stream of intermediate instruction words, where one intermediate instruction word may comprise a group of fields to set up the MAC unit to execute in response to the one intermediate instruction word.03-03-2011
20110264836TECHNIQUES TO MANAGE CRITICAL REGION INTERRUPTS - Briefly, techniques to manage interrupts and swaps of threads operating in critical region.10-27-2011
20110029707APPARATUS AND METHOD FOR PLAYING MULTIMEDIA DATA - A multimedia data reproducing device is provided which includes: a codec converting digital data into an analog signal by a predetermined method and reproducing the analog signal; and a control unit including a core generating a reproduction block by decoding multimedia data and outputting the generated reproduction block to a main memory in an activated state and an interface transmitting the reproduction block stored in the main memory as the digital data to the codec and transmitting the multimedia data stored in an auxiliary memory to the core in an activated state. Accordingly, it is possible to efficiently reproduce multimedia data to reduce the power consumption of a battery by alternately turning on and off a power source of blocks other than the interface in the control unit periodically or depending on a predetermined situation.02-03-2011
20110138093INTEGRATED CIRCUIT PACKAGE WITH MULTIPLE DIES AND INTERRUPT PROCESSING - A package includes a first die and a second die. The dies are connected to each other through an interface. The package includes interrupt processing for detecting interrupt information and providing a packet in response to the interrupt information detection. The packet includes an address to which data in the packet is to be written. The interface is configured to transport the packet between the dies. A data store is provided to which the data is writable. An interrupt event is determined from data received in several packets.06-09-2011
20120210033REAL-TIME MESSAGING SYSTEM FOR AN IMAGE DISPLAY DEVICE - A real-time messaging system for an image display device is provided. One disclosed embodiment includes an image display device including a light source and an image-generation device configured to receive light from the light source, and in response, generate an image. The image display device may further include a projection lens configured to display the image on a viewing surface. The image display device may also include memory and a processor operatively coupled with the memory to receive a command message sent to a select group of image display devices in real-time via a network, and upon recognizing the command message, display an alert image.08-16-2012
20100161864Interrupt request and message signalled interrupt logic for passthru processing - Methods, systems, apparatuses and program products are disclosed for managing interrupt services in hypervisor and hypervisor-related environments in Message Signaled Interrupts are emulated as other type(s) of interrupt.06-24-2010
20100082866Providing a set aside mechanism for posted interrupt transactions - In one embodiment, a method includes receiving an incoming posted transaction in a processor complex from a peripheral device, determining if the transaction is an interrupt transaction, and if so routing it to a first queue, and otherwise routing it to a second queue. Other embodiments are described and claimed.04-01-2010
20110185096SYSTEMS AND METHODS FOR EMBEDDING INTERRUPTS INTO A SERIAL DATA STREAM - Systems and methods for transmitting and processing interrupts by embedding interrupt information into a serial data stream are disclosed. An event is detected and converted into an interrupt signal. The interrupt signal is converted into a special interrupt character or symbol sequence. The special interrupt character or symbol sequence is embedded into a serial data stream at the next available character or symbol boundary and transmitted to a receiving controller. The receiving controller strips the special interrupt character or symbol sequence from the serial data stream and raises a corresponding interrupt. The receiving controller processes the interrupt by interrupting normal processing to run an interrupt subroutine. Once the receiver has detected and raised an interrupt, it can return an acknowledgement character or symbol sequence by the same mechanism. The transmitter can repeat the interrupt embedding and transmission if it fails to receive the acknowledgement within a predetermined period of time.07-28-2011
20100057966Notifying Asynchronous Events To A Host Of A Data Storage System And Apparatus For The Same - A method of notifying asynchronous events to a host of a data storage system is presented. The method comprises the steps of: detecting an asynchronous event; generating an interrupt message in response to the detected asynchronous event; and communicating the generated interrupt message to the host.03-04-2010
20090300250System and Method for Virtualizing Processor and Interrupt Priorities - Dispatching of interrupts to a processor is conditionally suppressed, that is, only if an old priority value and a new priority value are either both less than or both greater than a maximum pending priority value. This conditional avoidance of dispatching is preferably implemented by a virtual priority module within a binary translator in a virtualized computer system and relates to interrupts directed to a virtualized processor by a virtualized local APIC.12-03-2009
20090300249SELECTIVE MISR DATA ACCUMULATION DURING EXCEPTION PROCESSING - A plurality of test points are located at predetermined circuit nodes in a processing system. Test code which includes a set of software-controllable interrupts is executed using a multiple input shift register (MISR) to generate a MISR signature. One or more selected software-controllable interrupt types are determined. During execution of the test code, the MISR is used to also accumulate data values from the plurality of test points during exception processing of one or more of the software-controllable interrupts within the set of software-controllable interrupts which are of the one or more selected software-controllable interrupt types to generate the MISR signature. A test control register has a plurality of fields, each for selecting or not selecting a corresponding software-controllable interrupt type.12-03-2009
20090292846METHOD OF INTERRUPT SCHEDULING - There is provided a method of interrupt scheduling. The method comprises: without allowing a target process woken up when an interrupt occurs to enter into a ready queue, directly comparing the priority of the woken-up target process with that of a current process performed before the occurrence of the interrupt, and executing a rescheduling in accordance with the compared result; and performing direct context switching with respect to the current process into the target process in accordance with whether or not the rescheduling is executed. Accordingly, in the method of interrupt scheduling, the preemption latency caused by the interrupt in the operating system of the computer system can be minimized by omitting the process of allowing the woken-up target process to enter into the ready queue and the process of selecting a process with the highest priority on the ready queue.11-26-2009
20120042107SYSTEM AND METHOD TO INTERRUPT A COMPONENT OF A MOBILE COMMUNICATION DEVICE RESPONSIVE TO A MUTE COMMAND - A system and method to interrupt a component of a mobile communication device based on a mute command and a monitored operating condition is disclosed. In another particular embodiment, the method includes receiving a mute command at a mobile communication device while the mobile communication device is performing audio content processing. The method also includes monitoring an operating condition of the mobile communication device in response to receiving the mute command. The method includes determining whether to interrupt a component used to perform the audio content processing based on the monitored operating condition.02-16-2012
20090172229METHODS FOR SELECTING CORES TO EXECUTE SYSTEM MANAGEMENT INTERRUPTS - A method includes directing a system management interrupt to a processor core from a plurality of processor cores of a computing device for handling based upon core load-sharing considerations. A machine readable medium includes a plurality of instruction, that in response to being executed, result in a computing device selecting a processor core of a plurality of processor cores to handle a system management interrupt and programming at least one system management register to direct the system management interrupt to the processor core selected from the plurality of processor cores for handling. An associated system is also disclosed.07-02-2009
20110307640CALL STACK SAMPLING WITH LIGHTWEIGHT THREAD MIGRATION PREVENTION - A sample is generated based on an event. Further, an interrupt handler captures information for an interrupted thread on a current processor. In addition, an affinity of the interrupted thread is set such that the interrupted thread runs only on the current processor without being able to migrate to a different processor. A sampler thread that runs on the current processor retrieves a call stack associated with the interrupted thread after the affinity of the interrupted thread has been set to the current processor. The affinity of the interrupted thread is restored after the call stack has been retrieved.12-15-2011
20090172228METHOD AND SYSTEM FOR HANDLING A MANAGEMENT INTERRUPT EVENT IN A MULTI-PROCESSOR COMPUTING DEVICE - A method and system for handling a management interrupt, such as a system management interrupt (SMI) and/or a platform management interrupt (PMI), includes sequestering two or more processor cores from a plurality of processor cores to form a group of sequestered processor cores for handling the management interrupt. Generated management interrupts are directed to the group of sequestered processor cores and not to non-sequestered processor cores. At least one of the sequestered processor cores handles the management interrupt without disrupting the current operation of the non-sequestered processor cores.07-02-2009
20090172227SERIAL ADVANCED TECHNOLOGY ATTACHMENT WRITE PROTECTION: MASS STORAGE DATA PROTECTION DEVICE - A mass storage device protection system may have a mass storage device, a processor configured to generate at least one serial write command signal to the mass storage device via a serial communication link, and a storage protector configured for communication with the processor and mass storage device, the storage protector configured to do the following: intercept the at least one serial write command signal, and determine whether the at least one serial write command signal comprises an authorized command signal or an unauthorized command signal.07-02-2009
20120047301DATA PROCESSOR AND CONTROL SYSTEM - Provided are a data processor, and a control system, in which an interrupt controller and an event link controller are adopted. The event link controller responds to a generated event signal to output a start control signal for controlling start of an operation of a circuit module. The circuit module is able to generate an event signal. The event link controller generates the start control signal according to the correspondences between event signals and start control signals which are defined by event control information. The links between the event signals and start control signals can be prescribed by the event control information. Therefore, operations of circuit modules prescribed by such links can be controlled sequentially. The control neither involves save and return processes by CPU as in the interrupt processing, nor needs priority level control as executed on competing interrupt requests.02-23-2012
20120047300WIRELESS TWO-WAY TRANSMISSION OF SERIAL DATA SIGNALS BETWEEN AN ELECTRONIC DEVICE AND A POWER METER - The invention relates to a bidirectional wireless transmission system for serial format data signals between a “master” electronic device (02-23-2012
20120210032TECHNIQUES FOR MANAGING POWER CONSUMPTION STATE OF A PROCESSOR - Techniques are described for determining a temporary latency tolerance report (tLTR) value. A processing unit has to respond to a device interrupt within a duration specified by tLTR to ensure no incoming data is lost due to device buffer overflow. The tLTR value can be used to prevent the processing unit from entering too deep a sleep state when a device driver anticipates multiple sequential interrupts for a transaction.08-16-2012
20120017018METHOD, SYSTEM, AND APPARATUS FOR COMMUNICATING USING MULTIPLE CONTROLLERS - Operating a control system includes repeatedly transmitting a first interrupt to at least one interface unit by a first controller of a plurality of controllers, wherein the first interrupt is transmitted at a first frequency. A first response is received at the first controller from the at least one interface unit responsive to the first interrupt, and a second response is received at a second controller of the plurality of controllers from the at least one interface unit, wherein the second response is aperiodic with respect to the first frequency.01-19-2012
20110066782PARTITION BUS - A method and system are provided for integrating partitions in a virtual machine environment. Specifically, a partition bus is provided, where the partition bus operatively connects partitions in such a way that it functions as a data transport mechanism allowing for data transfer and device sharing between partitions. The partition bus relies on virtualizing software in order to establish itself and to establish channels of communication between partitions and to inject interrupts to partitions where it is appropriate to do so. Furthermore, the partition bus employs such mechanisms ring buffers, transfer pages, and memory map changes to transfer information (requests and data). Furthermore, it uses policy agents to decide when information should be transferred or when devices should be shared among partitions. Lastly, it employs various mechanisms to ensure smooth integration between partitions, which includes remote services that have proxy devices and device versioning functionalities.03-17-2011
20120124264TECHNIQUE FOR COMMUNICATING INTERRUPTS IN A COMPUTER SYSTEM - A technique to enable efficient interrupt communication within a computer system. In one embodiment, an advanced programmable interrupt controller (APlC) is interfaced via a set of bits within an APIC interface register using various interface instructions or operations, without using memory-mapped input/output (MMIO).05-17-2012
20120166696Method, Apparatus and Computer Program Code Handling a User Input - For handling a user input, an indication of a current state is received from a processor. When a user input is detected, it is determined whether the user input matches a criterion that is defined for the current state. An interrupt request to the processor is generated if it is determined that the user input matches the criterion defined for the current state.06-28-2012
20100174841PROVIDING MULTIPLE VIRTUAL DEVICE CONTROLLERS BY REDIRECTING AN INTERRUPT FROM A PHYSICAL DEVICE CONTROLLER - Embodiments of apparatuses, methods, and systems for providing multiple virtual device controllers by redirecting an interrupt from a physical device controller are disclosed. In one embodiment, an apparatus includes a processor, a physical device controller, and virtualization logic. The virtualization logic is to receive a first interrupt from the physical device controller, and in response, send a second interrupt to the processor from one of a plurality of virtual device controllers.07-08-2010
20100299470INTERRUPT PROCESSING APPARATUS AND METHOD - An interrupt processing apparatus stores an elapsed detection time and an interrupt occurrence count for each interruption cause. The interrupt processing apparatus stores an interval of trouble determination for each interruption cause, and determines whether the elapsed detection time for each interruption cause reaches the interval of trouble determination. If the interrupt occurrence count exceeds the threshold value when the trouble determination interval is reached, the trouble state is determined.11-25-2010
20080215787Method and System for Processing Status Blocks Based on Interrupt Mapping - Certain aspects of a method and system for processing status blocks based on interrupt mapping may be disclosed. Exemplary aspects of the method may include determining whether a particular status block has been processed by at least one CPU based on comparing a value of a first register with a value of a second register, wherein the first register may comprise a running index value of at least one client segment within the particular status block and the second register may comprise a current running index value of at least one client segment. An interrupt may be generated, if the value of the first register is not equal to the value of the second register. The particular status block may be processed by at least one CPU based on the generated interrupt.09-04-2008
20100011142REQUEST CONTROLLER, PROCESSING UNIT, METHOD FOR CONTROLLING REQUESTS AND COMPUTER PROGRAM PRODUCT - A request controller for controlling processing of requests by one or more semiconductor data processing unit. The resource controller includes a controller input for receiving a request for the processing unit to switch a context of the processing unit or to switch the processing unit from a current an operation to another operation. The resource controller includes a resource budget memory in which one or more budget value can be stored. The budget value represents an amount of a resource of the processing unit. The resource controller further has a budget controller which includes a first budget controller input connected to the request controller input. A second budget controller input is connected to the memory. A comparator is connected to the first budget controller input and the second controller input, for comparing a consumption value associated with the request with the budget value. The comparator includes a comparator output for outputting a request grant signal when the comparison satisfies a predetermined grant criterion and outputting a request reject value when the comparison meets a predetermined reject criterion. A data controller is connected to the resource budget memory and the comparator output, for adjusting the budget value when the request grant signal is outputted.01-14-2010
20120185628Locking/Unlocking CPUs to Operate in Safety Mode or Performance Mode Without Rebooting - An embodiment of the invention provides a method for changing a multi-processor system from a performance mode to a safety mode while the system continues to run software. When an external event or exception occurs, context is switched from the performance mode to the safety mode. After context is switched, at least one pair of CPUs is synchronized to operate in the safety mode. In addition, a multi-processor system may be switched form the safety mode to the performance mode while the software continues to operate.07-19-2012
20090019203IMAGE FORMING APPARATUS AND CONTROL METHOD THEREOF - An image forming apparatus and a control method thereof. The image forming apparatus includes a plurality of image processors which process an image to be formed on a printing medium corresponding to a plurality of colors, a processor which executes an interrupt routine with respect to the plurality of image processors, and a controller which generates an interrupt signal and transmits the interrupt signal to the processor if at least two of the plurality of image processors generate interrupt requests so that the processor executes the interrupt routine.01-15-2009
20120233367Interrupt Latency Measurement - A system and method for setting a first indicator indicating that interrupts are virtually locked, receiving a first interrupt at a processor of a computing device, setting a second indicator indicating the receipt of the first interrupt and recording a first timestamp based on the receipt of the first interrupt. The system and method further adapted to virtually execute a routine for the first interrupt that includes determining if the second indicator is set, record a second timestamp based on the virtual execution of the routine and determine an interrupt latency based on the first and second timestamp.09-13-2012
20110004715METHOD AND SYSTEM FOR HANDLING A MANAGEMENT INTERRUPT EVENT IN A MULTI-PROCESSOR COMPUTING DEVICE - A method and system for handling a management interrupt, such as a system management interrupt (SMI) and/or a platform management interrupt (PMI), includes sequestering two or more processor cores from a plurality of processor cores to form a group of sequestered processor cores for handling the management interrupt. Generated management interrupts are directed to the group of sequestered processor cores and not to non-sequestered processor cores. At least one of the sequestered processor cores handles the management interrupt without disrupting the current operation of the non-sequestered processor cores.01-06-2011
20110047308Control Equipment with Communication Apparatus - A control equipment with a built-in communication apparatus is provided which realizes a delay required for communication without a software intervention while at the same time reducing a load of the communication processing. The control equipment with a communication apparatus includes: a communication device to communicate with a plurality of destinations; and a decision device to determine a mode requiring a reception completion interrupt and a mode not requiring the reception completion interrupt. If the decision device decides that the reception completion interrupt is not necessary, the communication device transmits data to one or more destinations and also virtually transmits data to a second destination different from the first intended destination.02-24-2011
20120271977EXCEPTION HANDLING IN A CONCURRENT COMPUTING PROCESS - A system initiates multiple instances of a concurrent computing process, establishes a communication channel among the multiple instances, initiates execution of a computational job on the multiple instances, detects an interrupt request on one of the multiple instances, and terminates execution of the computational job while maintaining communication among the multiple instances via the communication channel.10-25-2012
20120096205INTER-VIRTUAL MACHINE PROFILING - Disclosed is a virtual machine system where hardware timer interrupts are processed by a first virtual machine. The first virtual machine writes a timer value to a shared memory location while processing the hardware timer interrupt. The timer value may be based on a kernel timing parameter maintained by the operating system of the first virtual machine. A second virtual machine may read the shared timer value from the shared memory location in order to time inter-virtual machine processes such as I/O processing and I/O requests.04-19-2012
20110161541POSTING INTERRUPTS TO VIRTUAL PROCESSORS - Embodiments of systems, apparatuses, and methods for posting interrupts to virtual processors are disclosed. In one embodiment, an apparatus includes look-up logic and posting logic. The look-up logic is to look-up an entry associated with an interrupt request to a virtual processor in a data structure. The posting logic is to post the interrupt request in a data structure specified by information in the first data structure.06-30-2011
20080235424Method and apparatus for performing interrupt coalescing - In one embodiment, the invention includes a controller that interrupts a CPU based on a counter that uses a decrement step which may increase as high priority data packets are received by the controller.09-25-2008
20080222333Methods and Apparatus for Scalable Array Processor Interrupt Detection and Response - Hardware and software techniques for interrupt detection and response in a scalable pipelined array processor environment are described. Utilizing these techniques, a sequential program execution model with interrupts can be maintained in a highly parallel scalable pipelined array processing containing multiple processing elements and distributed memories and register files. When an interrupt occurs, interface signals are provided to all PEs to support independent interrupt operations in each PE dependent upon the local PE instruction sequence prior to the interrupt. Processing/element exception interrupts are supported and low latency interrupt processing is also provided for embedded systems where real time signal processing is required. Further, a hierarchical interrupt structure is used allowing a generalized debug approach using debut interrupts and a dynamic debut monitor mechanism.09-11-2008
20100287320Interprocessor Communication Architecture - Described embodiments provide interprocessor communication between at least two processors of an integrated circuit, each processor running at least one task. For each processor, a proxy task is generated corresponding to each task running on each other processor. A task identifier for each task, and a look-up table having each task identifier associated with each other processor running the task is also generated. When a message is sent from a source task to a destination task that is running on a different processor than the source task, the source task communicates with the proxy task of the destination task. The proxy task appends the task identifier for the destination task to the message and sends the message to an interprocessor communication interface. Based on the task identifier, the processor running the destination task is determined and the destination task retrieves the message.11-11-2010
20120284443VIRTUAL MULTI-PROCESSOR SYSTEM - A virtual multi-processor system includes a plurality of logic processors. Moreover, the virtual multi-processor system includes a logic processor controller configured to allocate a time slice to each of the logic processors to control the logic processors so that the logic processors sequentially run in a time-sharing manner. When a request for interrupt processing occurs, an external interrupt controller performs control so that a logic processor that has a time slice within which the interrupt processing is possible and that runs next executes the interrupt processing.11-08-2012
20120284442LOW LATENCY INTERRUPT COLLECTOR - This document provides apparatus and methods for providing low latency response from a processor to the interrupts collected from peripheral devices. In an example, an apparatus can collect interrupt requests from a plurality of peripheral devices, and can communicate interrupt information to a processor. Certain examples can reduce the quantity of processor general purpose inputs and outputs configured to receive the peripheral device interrupts in comparison to systems where the peripheral device interrupts are directly coupled to the processor.11-08-2012
20110314198Wireless Peripheral Chips, Host Devices and Multi-Interface Communication Apparatuses - A wireless peripheral chip operable to connect to a host device is provided. The wireless peripheral chip includes a first wireless communication module providing a first wireless communication service for the host device and a second wireless communication module providing a second wireless communication service for the host device. The first wireless communication module and the second wireless communication module share at least one interrupt signal for communicating with the host device.12-22-2011
20120030392System and Method for Automatic Hardware Interrupt Handling - A processing system is provided consisting of an interrupt pin, multiple registers, a stack pointer, and an automatic interrupt system. The multiple registers store a number of processor states values. When the system detects an interrupt on the interrupt pin the system prepares to enter an exception mode where the automatic interrupt system causes an interrupt vector to be fetched, the stack pointer to be updated, and the processor state values to be read in parallel from the registers and stored in memory locations based on the updated stack pointer, prior to the execution of an interrupt service routine. A method for automatic hardware interrupt handling is also presented02-02-2012

Patent applications in class INTERRUPT PROCESSING

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