| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 710240000 | ACCESS ARBITRATING | 72 |
| 20100005209 | ARBITRATION DEVICE FOR ARBITRATING AMONG A PLURALITY OF MASTER DEVICES, ARBITRATION METHOD, AND VIDEO PROCESSING DEVICE INCLUDING THE ARBITRATION DEVICE - An arbitration device arbitrates among master devices such that each master device is allowed to access a shared memory at a predetermined bandwidth, and the arbitration device permits an access request in a first period that a designer has set as desired if the access request has been made by a specific master device beyond a bandwidth that has been allocated in advance. The arbitration device masks an access request from the specific master device in a second period that follows the first period. | 01-07-2010 |
| 20080228977 | Method and Apparatus for Dynamic Hardware Arbitration - A method and apparatus for dynamically arbitrating, in hardware, requests for a resource shared among multiple clients. Multiple data streams or service requests require access to a shared resource, such as memory, communication bandwidth, etc. A hardware arbiter monitors the streams' traffic levels and determines when one or more of their arbitration weights should be adjusted. When a queue used by one of the streams is filled to a threshold level, the hardware reacts by quickly and dynamically modifying that queue's arbitration weight. Therefore, as the queue is filled or emptied to different thresholds, the queue's arbitration weight rapidly changes to accommodate the corresponding client's temporal behavior. The arbiter may also consider other factors, such as the client's type of traffic, a desired quality of service, available credits, available descriptors, etc. | 09-18-2008 |
| 20100115167 | Shared Resource Arbitration - Masters request access to a shared resource, such as a shared bus. Usage of the shared bus by each of the masters is monitored, a request to use the shared bus by one of the masters is received, and usage of the shared bus by the master is compared with a corresponding bandwidth threshold. The request is arbitrated if the usage of the shared bus by the master is below the bandwidth threshold, and the request to use the shared bus is granted to the master based on the arbitration. | 05-06-2010 |
| 20090265495 | ACCESS RIGHT MANAGING METHOD FOR ACCESSING MULTIPLE PROGRAMS - Provided is an access right managing method for a resource of a storage system, in which a management computer stores access right definition information of the resource, and resource correspondence information including information on a management program which manages another resource related to the resource managed by the management program. In case of which receiving an updating request of an access right of the resource, the management computer updates an access right based on the updating request of the access right, selects a management program of the resource whose access right is requested to be updated based on the resource correspondence information, transmits an updating request of an access right for a relative resource to a management computer which executes the selected management program, and in case of which the access right updating request of the related resource is received, updates the access right of the relative resource. | 10-22-2009 |
| 20090055565 | MEMORY INTERFACE AND METHOD OF INTERFACING BETWEEN FUNCTIONAL ENTITIES - A data and signal interface for controlling the transfer of data and signals between a memory array and macro function such as that of a digital signal processor (DSP) core. In one embodiment, the interface comprises a plurality of memory ports which interface with X/Y memory banks, a plurality of function ports, each with a function controller, which interface with DSP functions, a crossbar connecting the memory and function ports, and an arbitration unit for arbitrating memory access by the function ports. The memory interface advantageously allows multiple simultaneous accesses of memory banks via a plurality of macro functions, each access under the control of a parent processor instruction. A standardized protocol used for memory read/write operations is also disclosed. | 02-26-2009 |
| 20090319711 | SYSTEM AND METHOD FOR PROVISIONING A REMOTE LIBRARY FOR AN ELECTRONIC DEVICE - The disclosure provides a system and method of provisioning a resource to an electronic device. The method comprises: after a triggering event, receiving from a network a data transmission at the device, the data transmission containing access information relating to a resource in a library that is in a remote server from the device, the resource relating to an application operating on the device; extracting the access information from the data transmission at the device; presenting the access information for the resource in a graphical user interface (GUI) on a display of the device; and after a selection event is initiated on the device for the resource, initiating a second data transmission containing a copy of the resource to the device and integrating the resource into the application as an output generated by the application. | 12-24-2009 |
| 20080270659 | Governing access to a computing resource - Technologies are described herein for governing access to a computing resource. A proxy receives a request to access a computing resource. In response to the request, the proxy determines whether the request can be granted without consulting a governor for the computing resource. If the request cannot be granted without consulting the governor, the proxy transmits the request to a broker. The broker, in turn, transmits the request to a governor for the computing resource. The governor determines whether the requested access to the computing resource should be granted. The governor generates a response to the request and transmits the response to the broker. The broker, in turn, transmits the response to the proxy. The broker may also request notifications from the governor. | 10-30-2008 |
| 20100325327 | PROGRAMMABLE ARBITRATION DEVICE AND METHOD THEREFOR - A system includes a plurality of sources to provide information access requests. An arbiter includes an assignment module to associate a first access request from the first source to one of the plurality of arbitration slots based upon assignment information at a storage location, and a dispatch module to determine one request of a plurality of requests received at the plurality of sources to be dispatched to a resource, memory controller by a dispatch module. | 12-23-2010 |
| 20100332709 | PERFORMANCE OPTIMIZATION SYSTEM, METHOD AND PROGRAM - Provided is a performance optimization system that can identify a case where the impact on performance is large even when the number of cache misses is small. The performance optimization system includes: a required-period-of-time measurement unit that measures a required period of time concerning a to-be-observed access; a required-period-of-time table holding unit that holds a required-period-of-time table that consists of a plurality of table entries in which stored are measured values of the required period of time for each of classification regions produced by dividing a memory region for each of types based on the to-be-observed access to store a measured value of the required period of time; a table entry selection unit that makes a selection as to in which table entry, out of a plurality of table entries for each of the classification regions that make up the required-period-of-time table, the measured value of the required period of time is stored on the basis of the to-be-observed access; and a cache miss observation unit that detects the occurrence of a cache miss associated with the to-be-observed access. | 12-30-2010 |
| 20110055443 | MEMORY CONTROL APPARATUS AND INFORMATION PROCESSING APPARATUS INCLUDING THE SAME - Provided is a memory control apparatus including: a monitoring unit that monitors, for each of the masters, a usable bandwidth indicating an amount of memory access data to be accessed per unit time in response to a corresponding one of the access requests from the master; a holding unit that holds a predetermined request bandwidth for each of the masters; a bandwidth determining unit that determines whether or not the usable bandwidth has reached the predetermined request bandwidth for each of the masters; and a control unit that issues an advanced refresh command to the memory based on a result of the determination by the bandwidth determining unit for each of the masters, regardless of timing of a refresh cycle. | 03-03-2011 |
| 20110246695 | CONTROLLING BANDWIDTH RESERVATIONS METHOD AND APPARATUS - Disclosed is an apparatus which operates to substantially evenly distribute commands and/or data packets issued from a managed program or other entity over a given time period. The even distribution of these commands or data packets minimizes congestion in critical resources such as memory, I/O devices and/or the bus for transferring the data between source and destination. Any unmanaged commands or data packets are treated as in conventional technology. | 10-06-2011 |
| 20110119421 | MULTIPLE CONCURRENT ARBITERS - Plural arbiters arbitrate over a set of queues. The arbiters are constructed as a series of pipelined stages. Conflict detection logic detects conflicts among the arbiters in arbitrating across the queues, and, when a conflict is detected, the conflict detection logic alters processing related to conflicting queues in one arbiter when another arbiter has not passed a predetermined commit point in processing the queue. | 05-19-2011 |
| 20090172226 | Data processing system and method for interconnect arbitration - A data processing system comprising a plurality of processing units (Dv | 07-02-2009 |
| 20120124263 | ALLOCATING GRANT CHANNEL RESOURCES - Grant channel resources are allocated based on the number of access terminals that use different types of transmission time intervals (TTIs) for data transmissions. For example, if the number of access terminals using a first type of TTI exceeds the number of access terminals using a second type of TTI, more grant channel resources are allocated to the access terminals that use the first type of TTI. | 05-17-2012 |
| 20120271976 | Variable Length Arbitration - In one embodiment, a method determines a plurality of categories for requests for a shared resource being shared by a plurality of entities. A request for the resource is received from an entity in the plurality of entities. The method determines a category in the plurality of categories for the received request. If the received request is determined to be in a first category, the method dispatches the received request to a first arbitration scheme configured to determine an arbitration decision in a first time cycle. If the received request is determined to be in a second category, the method dispatches the received request to a second arbitration scheme configured to determine an arbitration decision in a second time cycle of a different length from the first time cycle. | 10-25-2012 |
| 20130013834 | MULTI-CORE PROCESSOR SYSTEM, ARBITER CIRCUIT CONTROL METHOD, AND COMPUTER PRODUCT - A multi-core processor system includes multiple cores; shared memory accessed by the cores; and an arbiter circuit that arbitrates contention of right to access the shared memory by the cores. Each of the cores is configured to acquire for the core, a measured speed of access to the shared memory; calculate for the core, a response performance based on the measured speed of access and a theoretical speed of access for the core; calculate for the cores and based on the response performance calculated for each of the cores, ratios of access rights to access the shared memory, the ratios being calculated such that a ratio of access rights for a given core is larger than a ratio of access rights for another core whose response performance is higher than that of the given core; and notify the arbiter circuit of the calculated ratios of access rights. | 01-10-2013 |
| 710241000 | Centralized arbitrating | 10 |
| 20090157934 | Data Processing Unit and Bus Arbitration Unit - An effective bus arbitration unit is described in which it is possible to reduce, as much as possible, the waiting time until a bus master obtain bus ownership and improve the rate of operating the bus while improving the throughput of data transfer. A bus master issues a size signal (for example, signal “CDSZ”) indicative of the size of data to be read or written. A state machine | 06-18-2009 |
| 20130073764 | CENTRAL BUS GUARDIAN (CBG) AND METHOD FOR OPERATING CBG - Central bus guardians (CBGs) and methods for operating a CBG are described. In one embodiment, a method for operating a CBG includes performing race arbitration among the buses connected to the CBG to select a winner bus for a time slot, and selectively forwarding data received at the CBG from the winner bus to a destination bus in the time slot based on whether the winner bus or the destination bus has a connection to an external network with respect to the application network and whether a communications device connected to the winner bus or the destination bus performs a critical function. Other embodiments are also described. | 03-21-2013 |
| 20120110230 | DEVICE FOR ARBITRATING BUS ACCESSES AND METHOD FOR CONTROLLING SAME - In an information-processing apparatus including a plurality of modules and a first arbiter which arbitrates bus-access requests of the plurality of modules, at least one of the plurality of modules includes a plurality of submodules and a second arbiter which arbitrates bus-access requests of the plurality of submodules and transmits at least one of the bus-access requests of the plurality of submodules to the first arbiter. | 05-03-2012 |
| 20080244135 | Memory Controller and Method For Controlling Access to a Memory, as Well as System Comprising a Memory Controller - In the method for controlling access of a plurality of requestors to a shared memory, the following steps are repeated for successive time-windows: receiving access requests from various requestors (S1), determining a type of access requested by the requests, comparing the requested access type with an access type authorized for a respective time-window according to a back-end schedule, generating a first selection of the incoming requests which have the prescribed access type for the relevant time-window, dynamically selecting one of the requests from the first selection. | 10-02-2008 |
| 20080215785 | ARBITRATION CIRCUIT - The present invention provides an arbitration circuit capable of stable operation regardless of timings for read and write requests. A latch signal of a predetermined pulse width is generated in accordance with a read request signal or a write request signal and supplied to latches. Flip-flops or FFs respectively fetch therein write and read requests produced within the time of the latch signal. The latches respectively output the fetched requests as signals at the same timing. Thus, since the timings for the signals coincide with each other even when the write request and the read request are made at close intervals while the latch signal is being outputted from a latch controller, a write control signal or a read control signal can be stably outputted in accordance with the order of priority defined in advance by a delay unit. | 09-04-2008 |
| 20110208887 | Method and apparatus for performing arbitration - An apparatus for performing arbitration increases the fairness of arbitrations, decreases system latency, increases system throughput, and is suitable for use in more complex systems. According to an exemplary embodiment, the apparatus includes a generator for generating a plurality of arbitration numbers corresponding to a plurality of agents, and circuitry for selecting one of the agents to access a resource shared by the agents based on the arbitration numbers. At least one of the arbitration numbers includes a plurality of fields corresponding to a plurality of parameters. | 08-25-2011 |
| 20100153603 | Share Resources and Increase Reliability in a Server Environment - Methods and systems for a low-cost high density compute environment with increased fail-over support through resource sharing and resources chaining. In one embodiment, one of a number of servers qualified to share resources is elected as a resource server. The shared resource can be firmware memory, hard-drive, co-processor, etc. The elected server responds to requests from individual requesters and provides the responses, such as firmware images. In one embodiment, all the blade servers on a rack use an image server for their firmware image so that these blade servers can automatically adopt a common personality across the entire rack. If the elected image server fails, a dynamic process elects an alternate image server. In one embodiment, among a set of qualified servers, only one is actively elected at a given time. | 06-17-2010 |
| 20090113099 | ARBITER MODULE PROVIDING LOW METASTABILITY FAILURE PROBABILITY - An arbiter module receives two or more closely occurring asynchronous requests and provides an output with a low metastability failure probability. The arbiter module includes a request resolving module that receives multiple asynchronous requests for providing a final output. The request resolving module includes one or more arbiter stages cascaded with each other and operatively coupled with logic units. | 04-30-2009 |
| 20110022757 | Method for Accessing Control Units Arranged in a Vehicle, Control Program and Communication Control Unit - For control unit access, a vehicle to be checked is identified using an identifier. Control and/or monitoring operations covered by the control unit access are selected. A communication link is set up over a selected vehicle communication interface. Communication devices covered by the selected vehicle communication interface are ascertained. Independent control and/or monitoring operations covered by the control unit access are ascertained, where these operations are associated with available communication means and are not dependent on a superordinate control and/or monitoring operation. A control and/or monitoring operation, which has the greatest number of subordinate dependent control and/or monitoring operations, is selected for execution. | 01-27-2011 |
| 20100131690 | Content reception apparatus and content reception method - Disclosed is a content reception apparatus capable of receiving a content distributed from a server apparatus via a first network and a second network, the content reception apparatus including a plurality of content reception apparatuses capable of being connected to the second network that is local and connected to the first network, the server apparatus being capable of distributing a content and capable of being connected to the first network. The content reception apparatus includes an arbitration condition storage unit to store an arbitration condition for an arbitration, an arbitration table storage unit to store an arbitration table, an input unit with which a content reception request is input, an arbitration start request transmission unit to generate and transmit an arbitration start request, and an arbitration unit to execute arbitration processings. | 05-27-2010 |
| 710242000 | Decentralized arbitrating | 1 |
| 20120017017 | Data transfer circuit and data transfer method - A port A request queue is configured with a port AQ | 01-19-2012 |
| 710243000 | Hierarchical or multilevel arbitrating | 4 |
| 20080215786 | Electronic Device And A Method For Arbitrating Shared Resources - An electronic device is provided comprising a plurality of first shared resources (SR | 09-04-2008 |
| 20080263248 | Multi-drop extension for a communication protocol - In one embodiment, the present invention includes an apparatus having an upstream component including a plurality of virtual bridges to control communication with a corresponding plurality of endpoint components coupled downstream of the upstream component and a shared port. The apparatus may further include a first endpoint component coupled to the upstream component via a first link and a second endpoint component coupled to the first endpoint component via a second link and to the upstream component via a third link, where the upstream component and the endpoint components are coupled in a daisy chain topology. Other embodiments are described and claimed. | 10-23-2008 |
| 20080320193 | INFORMATION PROCESSING APPARATUS - A bus of a SoC (system on chip) includes a system arbiter for controlling not only a command arbiter but also a read information arbiter, a write data control circuit, a write complete notice arbiter and the like. A sequential table containing a series of system operations including activation processing and application processing and an operation clock information circuit or the like that becomes effective when a SoC bus region is divided by an operation clock frequency are utilized in assignment of priority of buses of the system arbiter. Thus, the information transfer efficiency of the whole system bus and the information transfer efficiency of every transfer originator can be improved. | 12-25-2008 |
| 20090055566 | Arbitration - Embodiments related to arbitration are described and depicted. | 02-26-2009 |
| 710244000 | Access prioritizing | 41 |
| 20090193167 | ARBITRATION DEVICE AND METHOD - An arbitration device receives a plurality of requests from a plurality of circuits, and grants access to one of the plurality of circuits. The arbitration device includes a sorter and an arbitrator. The sorter receives position information of an image signal including a plurality of image layers and determines an access priority including a first group and a second group according to the position information. The arbitrator receives the access priority and at least one of the plurality of requests, and grants the access to one of the plurality of circuits according to the access priority and the at least one of the plurality of requests. In addition, each of the plurality of circuits generates data for each of the image layers correspondingly. | 07-30-2009 |
| 20100042766 | PCI-EXPRESS DATA LINK TRANSMITTER EMPLOYING A PLURALITY OF DYNAMICALLY SELECTABLE DATA TRANSMISSION PRIORITY RULES - A PCI-Express data link transmitter includes a plurality of arbiters, each employing a distinct priority rule to select one of multiple scheduled TLPs and DLLPs based on their distinct types. A selector selects one of the arbiters to select the one of the multiple scheduled TLPs and DLLPs for transmission. A programmable storage element provides a value to control the selector. In one embodiment, the distinct priority rule employed by at least a first of the arbiters prioritizes TLPs higher than Ack/Nak DLLPs, and the distinct priority rule employed by at least a second of the arbiters prioritizes Ack/Nak DLLPs higher than TLPs. In one embodiment, at least a first arbiter prioritizes TLPs higher than Ack/Nak DLLPs and UpdateFC DLLPs, at least a second arbiter prioritizes Ack/Nak DLLPs higher than TLPs and UpdateFC DLLPs, and at least a third arbiter prioritizes UpdateFC DLLPs higher than TLPs and Ack/Nak DLLPs. | 02-18-2010 |
| 20090043934 | Method of and a System for Controlling Access to a Shared Resource - A method and a system of controlling access of data items to a shared resource, wherein the data items each is assigned to one of a plurality of priorities, and wherein, when a predetermined number of data items of a priority have been transmitted to the shared resource, that priority will be awaiting, i.e. no further data items are transmitted with that priority , until all lower, non-awaiting priorities have had one or more data items transmitted to the shared resource. In this manner, guarantees services may be obtained for all priorities. | 02-12-2009 |
| 20130097350 | QOS BASED DYNAMIC EXECUTION ENGINE SELECTION - In one embodiment, a processor includes processing cores, and instruction stores storing instructions at least one instructions having a group number, each instruction store having a unique identifier. The processor also includes a group execution matrix having group execution masks and a store execution matrix having store execution masks. The processor further includes a core selection unit that, for each instruction, selects a store execution mask using the unique identifier as an index. The core selection unit for each instruction, selects at least one group execution mask using the group number as an index, and performs logic operations on the selected group execution mask and the store execution mask to create a core request mask. The processor also includes an arbitration unit that determines instruction priority, assigns an instruction for each available core, and signals the instruction store of the assigned instruction to send the assigned instruction to the available core. | 04-18-2013 |
| 20090006693 | Apparatus and Method for Fairness Arbitration for a Shared Pipeline in a Large SMP Computer System - A modification of rank priority arbitration for access to computer system resources through a shared pipeline that provides more equitable arbitration by allowing a higher ranked request access to the shared resource ahead of a lower ranked requester only one time. If multiple requests are active at the same time, the rank priority will first select the highest priority active request and grant it access to the resource. It will also set a ‘blocking latch’ to prevent that higher priority request from re-gaining access to the resource until the rest of the outstanding lower priority active requesters have had a chance to access the resource. | 01-01-2009 |
| 20090006692 | METHOD AND APPARATUS FOR A CHOOSE-TWO MULTI-QUEUE ARBITER - An apparatus and method for granting one or more requesting entities access to a resource in a predetermined time interval. The apparatus includes a first circuit receiving one or more request signals, and implementing logic for assigning a priority to the one or more request signals, and, generating a set of first_request signals based on the priorities assigned. One or more priority select circuits for receiving the set of first_request signals and generating corresponding one or more fixed grant signals representing one or more highest priority request signals when asserted during the predetermined time interval. A second circuit device receives the one or more fixed grant signals generates one or more grant signals associated with one or more highest priority request signals assigned, the grant signals for enabling one or more respective requesting entities access to the resource in the predetermined time interval, wherein the priority assigned to the one or more request signals changes each successive predetermined time interval. In one embodiment, the assigned priority is based on a numerical pattern, the first circuit changing the numerical pattern with respect to the first_request signals generated at each successive predetermined time interval. | 01-01-2009 |
| 20100088443 | Data processing apparatus and method for arbitrating access to a shared resource - A data processing apparatus and method are provided for arbitrating access to a shared resource. The data processing apparatus includes a plurality of requester elements sharing access to the shared resource, and arbitration circuitry which is responsive to requests asserted by one or more of the requester elements for access to the shared resource, to perform a priority determination operation to select one of the asserted requests as a winning request. Each of the asserted requests has a priority level associated therewith, and the apparatus further comprises relative priority ordering circuitry for attributing relative priorities to the plurality of requester elements. The arbitration circuitry is responsive to the asserted requests to perform the priority determination operation in order to select as the winning request the request asserted by the requester element with the highest relative priority whose asserted request has a priority level not exceeded by any other asserted request. This provides a very flexible mechanism for performing arbitration, whilst allowing priority levels to be set on a request-by-request basis, thereby facilitating use of the arbitration circuitry with various quality of service mechanisms. | 04-08-2010 |
| 20120290756 | Managing Bandwidth Allocation in a Processing Node Using Distributed Arbitration - Management of access to shared resources within a system comprising a plurality of requesters and a plurality of target resources is provided. A separate arbitration point is associated with each target resource. An access priority value is assigned to each requester. An arbitration contest is performed for access to a first target resource by requests from two or more of the requesters using a first arbitration point associated with the first target resource to determine a winning requester. The request from the winning requester is forwarded to a second target resource. A second arbitration contest is performed for access to the second target resource by the forwarded request from the winning requester and requests from one or more of the plurality of requesters using a second arbitration point associated with the second target resource. | 11-15-2012 |
| 20080307139 | Resource access manager for controlling access to a limited-access resource - Methods and devices utilizing operating system semaphores are described for managing access to limited-access resources by clients. | 12-11-2008 |
| 20100241775 | METHOD AND APPARATUS FOR ARBITRATION ON A FULL-DUPLEX BUS USING DUAL PHASES - A method and apparatus for arbitrating on a high performance serial bus is disclosed. The invention provides for a plurality of arbitration phases and an arbitration advancing means. | 09-23-2010 |
| 20090282178 | Bounded Starvation Checking of an Arbiter Using Formal Verification - A system for formal verification of bounded fairness properties of pseudo random number generators and arbiters that use random priority-based arbitration schemes. The formal verification system determines an upper bound of a request-to-grant delay of an arbiter in terms of a number of complete random sequences. The formal verification system also determines, in terms of a number of clock cycles, an upper bound and a lower bound of a length of a complete random sequence in the random number sequence generated by a random number generator used by the arbiter. The formal verification system then determines a worst case request-to-grant delay bounds of the arbiter system, in terms of a number of clock cycles, by combining the upper bound of the request-to-grant delay of the arbiter with the upper bound of the length of the complete random sequence and the lower bound of the length of the complete random sequence. | 11-12-2009 |
| 20100299469 | ACCESS CONTROL CIRCUIT - An access control circuit includes a status managing circuit. The status managing circuit accepts one or at least two access requests issued from a plurality of buffer circuits each of which has a priority different from each other. A decoder repeatedly determines whether or not the one or at least two access requests accepted by the status managing circuit include an urgent access request. When a determination result is negative, the decoder acknowledges an access request corresponding to a higher priority out of the one or at least two access requests accepted by the status managing circuit. On the other hand, when the determination result is affirmative, the decoder acknowledges the urgent access request. | 11-25-2010 |
| 20080313377 | DISPLAY CONTROL CIRCUIT AND DISPLAY DEVICE - A display control circuit capable of performing arbitration with the use of a simple configuration. The display control circuit exchanges, with a plurality of masters, attribute information defining conditions for displaying video on a display, and includes a memory for storing the attribute information, a plurality of channels associated with the respective masters for accepting, from the masters, access requests to access the memory, and an arbitration controller configured by hardware. The arbitration controller arbitrates the access requests accepted via the respective channels and permits a selected one of the access requests to access the memory. | 12-18-2008 |
| 20120079155 | Interleaved Memory Access from Multiple Requesters - A shared memory system having multiple banks is coupled to a set of requesters. Separate arbitration and control logic is provided for each bank, such that each bank can be accessed individually. The separate arbitration logics individually arbitrate transaction requests targeted to each bank of the memory. Access is granted to each bank on each access cycle to a highest priority request for each bank, such that more than one transaction request may be granted access to the memory on a same access cycle. A wide transaction request that has a transaction width that is wider than a width of one bank is divided into a plurality of divided requests. | 03-29-2012 |
| 20080263249 | Access Arbiter and Arbitrable Condition Verification Device - A priority control value, which is smaller as the priority of access by each of requesters is higher, decreases with the lapse of time when an access request is issued. When the access is completed, the priority control value increases by a priority decrease value (PERIOD). When there is no access request, the priority control value decreases to a reference priority value (TMIN) and is then maintained at the reference priority value. Access permission is given to the one of the requesters issuing requests which has the smallest priority control value. As a result, proper arbitration is performed at a high speed with a simple hardware configuration. | 10-23-2008 |
| 20090254688 | Microprocessor Device and Related Method for a Liquid Crystal Display Controller - To reduce production cost, the present invention provides a microprocessor device for an LCD controller, which includes a memory, a first processing unit, a second processing unit, a first arbiter and a second arbiter. The memory is utilized for storing data. The first processing unit is utilized for executing a first program. The second processing unit is utilized for executing a second program. The first arbiter is coupled to the first processing unit and the second processing unit and utilized for deciding an operation order for the first processing unit and the second processing unit. The second arbiter is coupled to the first processing unit, the second processing unit and the memory and utilized for deciding a memory accessing order for the first processing unit and the second processing unit. | 10-08-2009 |
| 20120096204 | Formal Verification of Random Priority-Based Arbiters Using Property Strengthening and Underapproximations - A mechanism is provide for formally verifying random priority-based arbiters. A determination is made as to whether a random priority-based arbiter is blocking one of a set of output ports or a set of input ports. Responsive to the first predetermined time period expiring before the processor determines whether the random priority-based arbiter is blocking, a determination is made as to whether the random priority-based arbiter is blocking one of the set of output ports or the set of input ports within a second predetermined time period using the random seed and at least one of property strengthening or underapproximation. Responsive to the processor determining that the random priority-based arbiter satisfies a non-blocking specification such that not one of the set of output ports or the set of input ports is blocked within the second predetermined time period, the random priority-based arbiter is validated as satisfying the non-blocking specification. | 04-19-2012 |
| 20090276553 | CONTROLLER, HARD DISK DRIVE AND CONTROL METHOD - A data transfer system includes: a shared resource accessed from one or more devices; a plurality of request generation units each configured to generate a request for the device to access the shared resource, and output a remaining time value indicating how much time remains until the request is accepted before affecting an operation of an apparatus including the controller; and an arbitration unit configured to compare the remaining time values when the plurality of requests and the remaining time values are inputted from the plurality of request generation units, and give an access right to access the shared resource to a request with less remaining time. | 11-05-2009 |
| 20100185801 | DISTRIBUTED EQUIPMENT ARBITRATION IN A PROCESS CONTROL SYSTEM - A distributed process control equipment ownership arbitration system and method for arbitrating equipment ownership conflicts are disclosed. Individual control modules representing various process control entities within a process control system define a plurality of lists or queues for storing equipment arbitration information. Requests by one process control entity to acquire ownership over another process control entity are represented by an arbitration token that represents the ownership relationship sought by the acquiring process control entity. Copies of the arbitration token are communicated between the respective control modules and stored in the various arbitration queues defined by the control modules, depending on the status of the acquisition request. Upon receiving an acquisition request from another process control entity, the control module associated with the targeted process control entity decides whether the targeted process control entity is available to be acquired by the requesting control entity based on arbitration rules that are embedded within the control module itself. Once the targeted process control entity has been acquired by another process control entity it may not be acquired by any other process control entity until it has been released by the acquiring process control entity. | 07-22-2010 |
| 20100199010 | DEVICE HAVING PRIORITY UPGRADE MECHANISM CAPABILITIES AND A METHOD FOR UPDATING PRIORITIES - A device having priority update capabilities and a method for updating priorities, the method includes: receiving a request to update to a requested priority, priorities of transaction requests stored within a first sequence of pipeline stages that precede an arbiter; updating a priority level of a transaction request stored in the first sequence to the requested priority if the transaction request is priority upgradeable and if the requested priority is higher that a current priority of the transaction request; and arbitrating between transaction requests in response to priority attributes associated with the transaction requests. | 08-05-2010 |
| 20110238877 | Arbitration in Multiprocessor Device - An integrated circuit device ( | 09-29-2011 |
| 20110055444 | Resource Controlling - The present application relates to a method for resource controlling comprising controlling the processing of requests of a first category having a first priority. The method comprises controlling the processing of requests of a second category having a second priority, wherein the first priority is set such that processing the requests of the first category has priority over processing the requests of the second category. The method comprises blocking requests of the first category by a mechanism that detects when a predefined condition regarding the service provided to the second category is met. | 03-03-2011 |
| 20110072178 | Data processing apparatus and a method for setting priority levels for transactions - A data processing apparatus and method for setting priority levels for transactions is provided. The data processing apparatus has a shared resource for processing transactions, and at least one master device for issuing the transactions to the shared resource. The at least one master device provides a plurality of sources of the transactions, and each of the transactions has a priority level associated therewith. Arbitration circuitry is used to apply an arbitration policy to select a transaction from amongst multiple transactions issued to the shared resource, the arbitration policy using the priority level associated with each of the multiple transactions when performing the selection. Adaptive priority circuitry is associated with at least one of the sources, the adaptive priority circuitry monitoring throughput indication data for previously issued transactions from the associated source, and for each new transaction from the associated source, setting the priority level to one of a plurality of predetermined priority levels dependent on the throughput indication data. Through such a mechanism, the adaptive priority circuitry sets the lowest priority level from amongst the plurality of predetermined priority levels that will enable a specified target throughput to be achieved. The adaptive priority circuitry hence uses a feedback mechanism to control the priority level assigned to each new transaction from a source in order to target a specified throughput for the source, and through this mechanism finds the lowest priority necessary to achieve the throughput objectives independent of the activity of other sources within the system. | 03-24-2011 |
| 20110072179 | PACKET PRIORITIZATION SYSTEMS AND METHODS USING ADDRESS ALIASES - A switch fabric includes input links, output links, and at least one switching element. The input links are configured to receive data items that include destination addresses. At least some of the data items have different priority levels. The output links are configured to output the data items. Each of the output links is assigned multiple ones of the destination addresses. Each of the destination addresses corresponds to one of the priority levels. The switching element(s) is/are configured to receive the data items from the input links and send the data items to ones of the output links without regard to the priority levels of the data items. | 03-24-2011 |
| 20110072177 | VIRTUAL CHANNELS FOR EFFECTIVE PACKET TRANSFER - The invention sets forth a crossbar unit that includes multiple virtual channels, each virtual channel being a logical flow of data within the crossbar unit. Arbitration logic coupled to source client subsystems is configured to select a virtual channel for transmitting a data request or a data packet to a destination client subsystem based on the type of the source client subsystem and/or the type of data request. Higher priority traffic is transmitted over virtual channels that are configured to transmit data without causing deadlocks and/or stalls. Lower priority traffic is transmitted over virtual channels that can be stalled. | 03-24-2011 |
| 20100122004 | MESSAGE SWITCHING SYSTEM - The message switching system comprises at least two inputs and at least one output, first arbitration means dedicated to said output, and management means designed to determine a relative order OR(i,j) of one input relative to the other, for any pair of separate inputs belonging to the system and having sent requests for the assignment of said output, and designed to assign said output. Said management means comprise storage means designed to store said relative orders OR(i,j), initialization means designed to initialize said relative orders OR(i,j) such that only one of said inputs takes priority on initialization, and updating means designed to update all of said relative orders when a new request arrives at said first arbitration means, or when said output is assigned to one of said inputs. | 05-13-2010 |
| 20100115168 | MULTI-PROCESSING SYSTEM AND A METHOD OF EXECUTING A PLURALITY OF DATA PROCESSING TASKS - A plurality of data processing tasks with processing elements ( | 05-06-2010 |
| 20080222332 | COMBINED ENGINE FOR VIDEO AND GRAPHICS PROCESSING - The system includes an arbiter, a combined engine, a frame buffer, and a display processing unit. The arbiter provides three input channels: a first channel for graphics, a second channel for video and a third channel for processor. The arbiter performs prioritization and arbitration between the video and graphics and processor requests sent to the system. The arbiter has three output ports coupled to the combined engine. The combined engine is a hardware engine capable of processing either video data or graphics data. The output of the combined engine is provided to the frame buffer for the storage of pixel data. The output of the frame buffer is coupled to a display processing unit that renders the pixel data for display. | 09-11-2008 |
| 20120311214 | ARBITRATION CIRCUIT AND ARBITRATION METHOD THEREOF - An arbitration circuit and an arbitration method thereof are provided to arbitrate requests from a plurality of data processing devices for access to a shared resource. The arbitration method has steps of generating a first data stream for respectively identifying whether the data processing devices are currently serviced, generating a second data stream for identifying whether the data processing devices issue any request for access the shared resource, and performing AND operations on the first and second data streams in parallel to generate a third data stream that is used for determining which of the requests may be granted. Because the requests are processed in parallel, the arbitration time can be reduced. | 12-06-2012 |
| 20110138092 | ARBITRATION DEVICE, ARBITRATION SYSTEM, ARBITRATION METHOD, SEMICONDUCTOR INTEGRATED CIRCUIT, AND IMAGE PROCESSING DEVICE - Provided is a hierarchical arbitration device wherein an arbitration device at each level of the hierarchy selects a resource use request having the highest priority and a resource use request having the second highest priority, outputting these two resource use requests to the arbitration device that is one level higher. After outputting the memory use request having the highest priority to a resource control unit as the top priority resource use request, when the arbitration device at the highest level of the hierarchy receives a signal from the memory control unit indicating receipt of the resource use request, the arbitration device then selects the resource use request having the second highest priority and outputs this resource request as the next top priority resource use request. | 06-09-2011 |
| 20120042106 | STREAM PRIORITY - A system, method and apparatus for prioritizing transactions is disclosed. I/O devices may generate transactions with a stream identifier. A transaction classifier may assign a priority to a transaction based upon a stream identifier of the transaction. An arbiter may select a transaction for processing based upon priorities assigned to the transaction. | 02-16-2012 |
| 20080256279 | RESOURCE ARBITER - An aspect of the present invention provides an arbiter which grants a request (to access a resource) in the same clock cycle as in which the requests from requesters is received. In one embodiment, such a feature may be provided in case of arbitration policies requiring state information from previous grants. In another embodiment, such a feature may be provided when the arbitration policy is programmable such that the same arbiter can be used for different arbitration policies. | 10-16-2008 |
| 20120047299 | Data transfer device, method of transferring data, and image forming apparatus - A data transfer device controls data transfer performed through a bus capable of separately processing a request and a response. The data transfer device include a plurality of access control units that produce a data transfer process according to the request; and an arbitration unit that performs arbitration between the requests issued by the plurality of access control units so as to determine a request to be accepted among those requests. The arbitration unit sets an arbitration prohibited period in which the arbitration is prohibited for a designated period and accepts only the request issued by a designated access control unit among the plurality of access control units during the arbitration prohibited period. | 02-23-2012 |
| 20120072631 | Multilayer Arbitration for Access to Multiple Destinations - An arbiter is provided for arbitrating for access to a shared resource by a plurality of requesters and by a background requester in a processing system. A priority value is assigned to each of the plurality of requestors. A multilayer arbitration contest is performed to resolve each conflict in transaction requests to the shared resource, however, a requester of the plurality of requesters having a highest priority value does not always win an arbitration contest. An arbitration contest will be overridden whenever the background requester initiates a transaction request, such that the background requester always wins the overridden arbitration contest. The shared resource is accessed by the winner of each arbitration contest. | 03-22-2012 |
| 20120317322 | HIGH FAIRNESS VARIABLE PRIORITY ARBITRATION METHOD - Multiprocessor systems often share access to a centralized memory and experience conflicting access requests. An arbitration unit mediates priorities of requestor preferably ensuring both priority and fairness. In this invention upon an access conflict the arbitrator grants access to one requestor having the highest priority level and stalls other conflicting requestors. If plural requestors have the same priority level, the arbiter grants access to one and stalls the others. The arbiter then adjusts the priority levels of the requestors. The priority of the requestor granted access is decreased by the number of stalled requestors. The stalled requestors have their priority levels increased by one. The arbitration decision is thus based on the stall history and the caused stall history of each requestor. | 12-13-2012 |
| 20080228978 | METHOD OF DETERMING REQUEST TRANSMISSION PRIORITY SUBJECT TO REQUEST CONTENT AND TRANSTTING REQUEST SUBJECT TO SUCH REQUEST TRANSMISSION PRIORITY IN APPLICATION OF FIELDBUS COMMUNICATION FRAMEWORK - A method of determining request transmission priority subject to request content and transmitting request subject to such request transmission priority in application of Fieldbus communication framework in which the communication device determines whether the received requests have the priority subject to the respective content, and also determines whether there is any logical operation condition established, and then the communication device transmits the received external requests to the connected slave device as an ordinary request or priority request, preventing the slave device from receiving an important external request sent by the main control end or manager at a late time. | 09-18-2008 |
| 20110004714 | Method and Device for Priority Generation in Multiprocessor Apparatus - A device for generating a priority value of a processor in a multiprocessor apparatus, the device comprising a counter, an interface for receiving signals from an arbiter, wherein the signals indicate decision of the arbiter about granting or denying access to a common resource in said multiprocessor apparatus. The counter is adapted to change its value in response to said signal and the changes of the counter go in opposite directions depending on the type of signal received from the arbiter. The device is also adapted to send the modified value of the counter as a new priority value to the arbiter. | 01-06-2011 |
| 20120290755 | Lookahead Priority Collection to Support Priority Elevation - A queuing requester for access to a memory system. Transaction requests received from two or more requestors access to the memory system. Each transaction request includes an associated priority value. A request queue is formed in the queuing requester. Each transaction request includes an associated priority value. A highest priority value of all pending transaction requests within the request queue is determined. An elevated priority value is selected when the highest priority value is higher than the priority value of an oldest transaction request in the request queue; otherwise the priority value of the oldest transaction request is selected. The oldest transaction request in the request queue with the selected priority value is then provided to the memory system. An arbitration contest with other requesters for access to the memory system uses the selected priority value. | 11-15-2012 |
| 20130013835 | MULTICORE PROCESSOR SYSTEM, COMPUTER PRODUCT, AND CONTROL METHOD - A multicore processor system includes a processor configured to detect any among a switching process and an assignment process of applications in a multicore processor; acquire upon detecting any among the switching process and the assignment process, a priority level concerning execution of each application assigned to each core of the multicore processor and number of accesses of a shared resource shared by the multicore processor; determine an access ratio of an application whose priority level is highest to each of application remaining after excluding the application whose priority level is highest, among the assigned applications, by comparing the number of accesses by each remaining application and the number of accesses by the application whose priority level is highest; notify an arbiter circuit of the determined access ratios; and arbitrate using the arbiter circuit, the access of the shared resource by the multicore processor, based on the access ratios. | 01-10-2013 |
| 20130019041 | BIT SLICE ROUND ROBIN ARBITERAANM Bays; Laurence E.AACI AllentownAAST PAAACO USAAGP Bays; Laurence E. Allentown PA USAANM Banerjee; BalloriAACI BangaloreAACO INAAGP Banerjee; Ballori Bangalore INAANM Vomero; James F.AACI OrefieldAAST PAAACO USAAGP Vomero; James F. Orefield PA US - The present disclosure describes systems and methods for arbitrating between a plurality of devices competing for a system resource. Operations of the system and method may include, but are not limited to: initializing two or more previous grant request states; generating an access grant signal according to the two or more requests for access to the shared resource, two or more token states and the two or more previous grant request states; and generating an access grant signal according to the two or more requests for access to the shared resource, two or more token states and the two or more previous grant request states. | 01-17-2013 |
| 20130024588 | MULTICORE PROCESSOR SYSTEM, COMPUTER PRODUCT, AND CONTROL METHOD - A multicore processor system includes a core configured to detect a change in a state of assignment of a multicore processor; obtain, upon detecting the change in the state of assignment, number of accesses of a common resource shared by the multicore processor by each of process that are assigned to cores of the multicore processor; calculate an access ratio based on the obtained number of accesses; and notify an arbitration circuit of the calculated access ratio, the arbitration circuit arbitrating accesses of the common resource by the multicore processor. | 01-24-2013 |
