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Path selecting switch

Subclass of:

710 - Electrical computers and digital data processing systems: input/output

710100000 - INTRASYSTEM CONNECTION (E.G., BUS AND BUS TRANSACTION PROCESSING)

710305000 - Bus interface architecture

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Class / Patent application numberDescriptionNumber of patent applications / Date published
710317000 Crossbar 42
Entries
DocumentTitleDate
20130086297UNIVERSAL SERIAL BUS (USB) TO DIGITAL VIDEO - This document discusses, among other things, a system and method for serializing a video signal and providing non-packet-based serialized video information to a physical Universal Serial Bus (USB) interface and, in certain examples, receiving the non-packet-based serialized video information from the physical USB interface, deserializing the received non-packet-based serialized video information, and providing a high definition output signal to a video port (e.g., an HD video port, such as HDMI, DisplayPort, etc.) using the deserialized video information.04-04-2013
20090193171Multiuser KVM switch - A multiuser KVM switch that is connected between a plurality of consoles used by respective users and a plurality of servers, including: a setting portion that sets lock of an operation right for each server; and a prohibition portion that, when at least one operation right of the servers is locked by the setting portion, prohibits the consoles used by other users from operating a server in which the operation right is locked.07-30-2009
20090193170INFORMATION PROCESSING APPARATUS - An information processing apparatus for communicating with an external apparatus via a predetermined communication interface including a data signal line and an insertion/removal signal line is provided. The information processing apparatus includes a processing unit for executing an application that a user desires, a communication controlling unit for controlling a communication operation using the predetermined communication interface, at least two communication connectors that comply with the predetermined communication interface, an analog switch for switching between each of the at least two communication connectors and the communication controlling unit, and an interface controlling unit for enabling the data signal line of one of the at least two communication connectors by switching connection to the data signal line using the analog switch so as to cause the communication controlling unit to perform communication with an external apparatus connected to the enabled communication connector.07-30-2009
20110197012COMPUTER MOTHERBOARD - A computer motherboard includes first and second peripheral interfaces, a switching interface, a switching card inserted into the switching card, and first and second central processing unit (CPU) sockets. The switching interface is placed between the first and second peripheral interfaces. The switching card includes first and second interface. Pins of the first interface of the switching card are interconnected, and pins of the second interface of the switching card are interconnected. Connection between the first and second peripheral sockets and the first and second CPU sockets is adjustable by selectively connecting one of the first and second interfaces of the switching card to the switching interface.08-11-2011
20110197011STORAGE APPARATUS AND INTERFACE EXPANSION AUTHENTICATION METHOD THEREFOR - Degradation of data transfer performance is restrained during data transfer for minoring between first and second controllers.08-11-2011
20130031290System and Method for Implementing a Secure Processor Data Bus - System and method for implementing a secure processor data bus are described. One embodiment is a circuit comprising a processor disposed in a processor partition, the circuit further comprising a first set of peripherals disposed in a first peripheral partition; a second set of peripherals disposed in a second peripheral partition physically isolated from the first peripheral partition; a first state control register for controlling access to the first set of peripherals by the processor; and a second state control register for controlling access to the second set of peripherals by the processor. When the first and second state control registers are in a first mode of operation, the processor has read and write access to the first set of peripherals and write only access to the second set of peripherals. When the first and second state control registers are in a second mode of operation, the processor has read and write access to the second set of peripherals and read only access to the first set of peripherals.01-31-2013
20120246378INFORMATION TRANSFER APPARATUS, INFORMATION TRANSFER SYSTEM AND INFORMATION TRANSFER METHOD - An information transfer apparatus of the present invention is an information transfer apparatus including a network interface connected to a server that distributes data, via a network, and a USB interface connected to an information presentation apparatus that presents the data, the information transfer apparatus transferring the data distributed from the server to the information presentation apparatus; and the information transfer apparatus includes: a switch that enables or disables connection with the information presentation apparatus via the USB interface; and a control section that judges whether or not the data distributed from the server has been updated, enables connection with the information presentation apparatus by the switch to transfer the data to the information presentation apparatus only upon judging that the data has been updated, and, after transferring the data, disables the connection with the information presentation apparatus by the switch.09-27-2012
20100077126USB Matrix Switch System - An USB matrix switch system provided for a plurality of USB devices shared with a plurality of hosts is disclosed. The system comprises: (1) a plurality of DP PHYs, respectively, corresponding to the USB devices so as to transfer those series signal received from the USB devices to parallel signals; (2) a plurality of UP PHYs, respectively, corresponding to the hosts for transferring signal received therefrom to parallel signals or doing the reversal operation; (3) a plurality of hubs, respectively, corresponding to the UP PHYs, each hub has a digital repeater, a TT, an up router, a down router, and a hub controllers; (4) a signal fetching monitor for fetching a control signal provided by a user; (5) a plurality of signal control switch modules having a down stream port controller, a disconnection emulator, provided for simulating a disconnection status while the down stream port controller is empty, and a select MUX provided for switching a selected USB device to a selected hub in accordance with content of the hot key.03-25-2010
20130080678CABLE REDUNDANCY AND FAILOVER FOR MULTI-LANE PCI EXPRESS IO INTERCONNECTIONS - Method and apparatus for providing failover operation for a connection between a first PCIE bridge and a first input/output (IO) device are provided. A first set of bussed bits is exchanged between the first PCIE bridge and the first IO device over a first link using a first set of lanes of the first PCIE bridge. In response to detecting the failure in the first link, the first set of bussed bits is exchanged between the first PCIE bridge and the first IO device using an unused portion of a second link connecting a second PCIE bridge and a second IO device.03-28-2013
20130080677Virtual General Purpose Input/Output for a Microcontroller - A microcontroller includes a general purpose input/output (GPIO) port having a plurality of bits coupled to a plurality of external pins; a first set of registers for providing at least one of first control and data input/output functionality of the GPIO port; a second set of registers for providing at least one of second control and data input/output functionality of the GPIO port; and a multiplexer and associated select register for controlling the multiplexer to control said GPIO port through either said first or second register set.03-28-2013
20100106884Switch providing external access to computer-system components - Embodiments of the present invention include a switch component, incorporated within a computer system, that receives switch commands from users and that controls internal switches to direct output to, and receive input from, either components of the computer system or one or more external-access ports. The switch component allows one or more external computers to access internal components of, or external peripherals attached to, a computer system that includes the switch component.04-29-2010
20090125666DYNAMICALLY SCALABLE QUEUES FOR PERFORMANCE DRIVEN PCI EXPRESS MEMORY TRAFFIC - A computer program product for implementing a method within a data processing system and a PCI Express protocol for enabling high performance IO data transfers for multiple, different IO configurations, which include variable packet sizes and/or variable/different numbers of transactions on the IO link. PCI Express protocol is enhanced to support utilization of counters and dynamically variable queue sizes. In addition to the standard queue entries, several (or a selected number of) dynamically changeable queue entries are provided/reserved and a dynamic queue modification (DQM) utility is provided within the enhanced PCI Express protocol to monitor ongoing, current data transfer and manage when the size(s) of the queue entries are modified (increased or decreased) based on current data traffic transmitting on the PCI Express IO link. The enhanced PCI Express protocol provides an equilibrium point at which many large data packets are transferred efficiently, while imposing a limit on the number of each size of packets outstanding.05-14-2009
20130046913MULTIMEDIA STORAGE CARD SYSTEM - A multimedia storage card system includes a memory card; a dynamic switch coupled electrically and communicatively to the memory card; a first accessor coupled electrically and communicatively to the dynamic switch for accessing to the memory card, thereby storing data into and retrieving data from the memory card; and a second accessor coupled electrically and communicatively to the dynamic switch. Upon receipt of a first access signal transmitted from the second accessor, the dynamic switch determines whether the first accessor is in an idle condition. Upon detecting the first accessor is in the idle condition, the dynamic switch is switched to and in communication link with the second accessor, thereby transmitting the first access signal to the memory card and enabling the second accessor to access the memory card in order to store data into and retrieving data from the memory card.02-21-2013
20130046914CONNECTOR ASSEMBLY - A connector assembly includes first to fourth groups of holes set on a motherboard, first and second peripheral component interconnection express (PCIe) slots, and a number of switches. When the second group of holes are connected to the fourth group of holes, the signals at the second group of holes are transmitted to the second group of pins of the second PCIe slot through the switches and the fourth group of holes.02-21-2013
20090119441Heterogeneous Parallel Bus Switch - A parallel bus switch has an input stage configured to convert a bus signal from a first bus having a first configuration to a second configuration, an internal standard bus configured to receive the bus signal in the second configuration and transport the bus signal to an output stage. The output stage is configured to convert the bus signal from the second configuration to a third configuration used by a data recipient and transmit the bus signal to a second bus corresponding to the data recipient.05-07-2009
20090327570Bidirectional control circuit - A bidirectional bus control circuit to which first and second direction signals instructing bus directions are input and which inputs and outputs a clock signal and data signal includes a first bidirectional buffer that switches an input or output direction of the clock signal in accordance with the second direction signal, a second bidirectional buffer that switches an input or output direction of the data signal in accordance with the second direction signal, and a data confirmation unit that confirms a data signal input to the second bidirectional buffer and invalidates the confirmation of the data signal in accordance with switching of the signal direction instructed by the first direction signal from the input direction to the output direction, the switching of the signal direction instructed by the first direction signal occurring before the switching of the signal direction instructed by the second direction.12-31-2009
20090307407REMOTE ACCESS TO AN INTERNAL STORAGE COMPONENT OF AN ELECTRONIC DEVICE VIA AN EXTERNAL PORT - A computing device allows remote access to internal storage component via a remote access interface, e.g., USB, port. The electronic device or computing device contains a motherboard with modified internal circuitry that allows access to the internal storage component via the remote access port. Bus arbitration circuitry, within the motherboard of the computing device, arbitrates between a host CPU and the remote access interface port. Power arbitration circuitry, within the motherboard of the computing device, arbitrates between an internal power supply and power available at the remote access port. The bus arbitration and power arbitration are based upon a predetermined rules as well as an intelligent adaptive set of rules. Internal storage component access is provided based on authorization rules. The internal storage component may be accessed by an external processing circuitry even when the electronic device or computing device is powered down or not in working condition.12-10-2009
20110016255COMPUTER STSTEM - A computer system includes a host computer and a monitor connected to the host computer via an integrated digital video interface (DVI-I) connection, and a signal switching circuit. The DVI-I supports both digital/analog signals and generating a hot plug detection signal to identify an/a analog or digital display mode of the monitor. The signal switching circuit is capable of connecting the DVI-I to analog system management bus (SMBUS) if the monitor is in the analog display mode, and connecting the DVI-I to digital SMBUS if the monitor is in the digital display mode.01-20-2011
20090094401System for Dynamically Balancing PCI-Express Bandwidth - In a dynamic mode, firmware sets a threshold of errors that may occur within a predetermined period of time. If the threshold is exceeded, the firmware queries the front-side bus performance counters to determine whether the front-side bus is operating at its maximum data rate. If the front-side bus is not running at the maximum data rate, then the firmware bumps the data rate settings for the endpoint that exceeds the threshold by one step. If the front-side bus is running at its maximum data rate, then the firmware queries all the endpoints to determine which endpoints are active. The firmware then determines whether there are any active endpoints that are lower priority than the complaining endpoint. The mechanism drops the lower priority endpoints by one step and raises the complaining endpoint by one step.04-09-2009
20130073777Switching System which Allows Primary USB Connection in Response to USB Signaling - System and method controlling connectivity within a device. A device may be coupled to a host device. In response to the coupling, low power logic (e.g., an embedded device) of the device may be coupled to the host device. The low power logic may perform enumeration with the host device using only power provided by the host device. The low power logic may also charge a battery of the device using power provided by the host device. Device circuitry of the device may provide a signal for coupling to the host device. In response, the device circuitry may be coupled to the host device and may perform device enumeration with the host device.03-21-2013
20130073776High Current Multi-Port USB Hub - A high-current Multi-Port USB hub has a microcontroller that selectively switches the hub between low current synchronizing state and high current charging state. During charging state in excess of two Amps of current can be provided to each device connected to the hub. Each USB port circuit includes a power FET to selectively provide current to the USB port according to the state of the hub. Current sensors on each of the USB ports detects an amount of current being drawn by a device connected to the USB port. Each USB port is provided with indicators to indicate the charged state of the device connected to that port. The charge state of the device is also provided to the microcontroller which provides a summary status indication of the set of devices connected to the USB hub.03-21-2013
20130073775SYSTEMS AND METHODS FOR IMAGE STREAM PROCESSING - Various embodiments relate to systems and methods for simultaneously switching input image streams to output devices, while providing optional image processing functions on the image streams. Certain embodiments may provide vision systems and methods suitable for use in vehicles, particularly windowless vehicles, such as armored ground vehicles, submerged watercraft, and spacecraft. Some embodiments may enable sharing of image streams (e.g., with one or more other vehicles), generation of panoramic views (e.g., from various camera feeds), intelligent encoding of image streams, and implementation of security features based on image streams.03-21-2013
20130073774ELECTRIC DEVICE WITH MULTIPLE DATA CONNECTION PORTS - An electric device with multiple data connection ports is provided. The electric device includes a body, a processing unit, and a detecting switch unit. The body includes M surfaces and N data connection ports disposed on the surfaces. The processing unit includes a first interface control unit and a second interface control unit. The detecting switch unit detects whether the data connection ports are connected. While detecting the i03-21-2013
20130060987System and Method to Correlate Errors to a Specific Downstream Device in a PCIe Switching Network - A Peripheral Component Interconnect-Express (PCIe) port includes a PCIe link, a pending transaction counter, and an error status register. The PCIe port operates to issue a transaction on the PCIe link, determine that an endpoint device has become uncoupled from the PCIe link after issuing the first transaction, determine that a value stored in the pending transaction counter is not equal to zero in response to determining that the endpoint device has become uncoupled, and set an error bit in the error status register in response to determining that the first value is not equal to zero.03-07-2013
20120311226COMPUTER APPARATUS, COMPUTER SYSTEM AND ADAPTER CARRY-OVER METHOD - To obtain a computer that can change over from the active system to the standby system without reconnecting the I/O adapters. The computer according to the present invention carries over the identifiers logically identifying connection paths between computer modules and I/O adapters from active computers to standby computers.12-06-2012
20090271558PROGRAMMABLE CHANNEL - A programmable channel circuit can include a control circuit having at least one bidirectional I/O terminal, at least one programming terminal, and one or more processing elements, and an interface circuit having first and second field terminals/The interface circuit is coupled to the control circuit via the processing elements. The control circuit can be operable to respond to a programming signal on the programming terminal for automatically selecting one of a plurality of communications modes. The selection couples the bidirectional I/O terminal to the first terminal via one of the processing elements associated with the selected communications mode.10-29-2009
20090031070Systems And Methods For Improving Performance Of A Routable Fabric - Systems and methods for improving performance of a rentable fabric are disclosed. In an exemplary embodiment a system may comprise a plurality of compute nodes, a routable fabric, and a plurality of chipsets connected by the routable fabric to the plurality of compute nodes. The chipsets have range registers dynamically directing traffic from any device to any of the plurality of compute nodes over the routable fabric.01-29-2009
20110022771SYSTEM AND METHOD FOR DISPLAYING ALARM NOTIFICATIONS ON AN ON-SCREEN DISPLAY - A Keyboard, Video, Mouse (KVM) switch that includes one or more input ports to receive events, notifications and/or alarms generated by an external device. The KVM switch receives the events, notification and/or alarms in the form of an external signal. The KVM switch processes the external signals and compares the received external signal to one or more reference signals to identify an event that corresponds to the received external signal. The KVM switch then generates an announcement for display on one or more displays associated at least one user station coupled to the KVM switch.01-27-2011
20090248945NOISE REDUCING METHODS AND CIRCUITS - In some embodiments, a circuit is provided with a transmitter to generate switching noise during clock events when no transition occurs to reduce data dependent switching noise.10-01-2009
20120233376CONTROL DEVICE FOR STORAGE - A control device for controlling a storage device in which data is stored, the control device includes a processor that sets protection condition of the storage device through a signal line coupled with the storage device and sets the protection condition of the storage device through a first transmission line coupled with the control device, and an exchange switch coupled with the control device and an arithmetic operation device through the first transmission line and a second transmission line, respectively, the exchange switch being configured to switch between the first transmission line and the second transmission line so as to communicably couple either one of the control device and the arithmetic operation device with the storage device.09-13-2012
20090013121USB COMPUTER SWITCHING DEVICE - The present invention describes a device and circuit for attaching at least two computers to a one or more computer peripheral such as a projector in a classroom situation. The peripheral can be switched easily between the computers without difficult toggling by means of a button which activates a relay between the two computers. A default position indicates the position the switch can start in.01-08-2009
20130166813MULTI-PROTOCOL I/O INTERCONNECT FLOW CONTROL - Described are embodiments of methods, apparatuses, and systems for multi-protocol tunneling across a multi-protocol I/O interconnect of computer apparatus. A method for managing flow across the multi-protocol I/O interconnect may include providing, by a first port of a switching fabric of a multi-protocol interconnect to a second port of the switching fabric, a first credit grant packet and a second credit grant packet as indications of unoccupied space of a buffer associated with a path between the first port and a second port, and simultaneously routing a first data packet of a first protocol and a second data packet of a second protocol, different from the first protocol, on the path from the second port to the first port based at least in part on receipt by the second port of the first and second credit grant packets. Other embodiments may be described and claimed.06-27-2013
20080294833Method and apparatus for automatic detection and healing of signal pair crossover on a high performance serial bus - An automatic crossover and healing process is disclosed for the P1394b standard. In particular, a crossover process is disclosed which comprises coupling the transmitting logic of a PHY to TPA, and coupling the receive logic of a PHY to TPB.11-27-2008
20080294832I/O Forwarding Technique For Multi-Interrupt Capable Devices - The method, apparatus and system of an I/O forwarding technique for multi-interrupt capable I/O devices are disclosed. In one embodiment, a method of transferring an I/O request in a cache-coherent non-uniform memory access (ccNUMA) computer system including multiple cells (e.g., each cell may include multiple processors) that are connected via a system interconnect, includes receiving an I/O request from one of the multiple processors associated with one of the multiple cells in the ccNUMA computer system, associating a processor, corresponding to a multi-interrupt capable I/O interface that is servicing the I/O request, located in the one of the multiple cells as a lead processor, and executing an I/O initiation path and a completion path associated with the received I/O request on the lead processor upon associating the lead processor corresponding to the multi-interrupt capable I/O interface.11-27-2008
20090204741READER BOARD ASSEMBLY CIRCUIT, SYSTEM, AND METHOD FOR IDENTIFYING A DIGITAL DEVICE AMONG MULTIPLE DIGITAL DEVICES - The present invention provides an electronic circuit for detecting, identifying, and/or activating a digital device, including a touch-and-hold connector configured to hold an object of interest, the digital device coupled to the touch-and-hold connector, for example, wherein the digital device has a unique digital registration number, a microcontroller that reads the unique digital registration number of the digital device, a storage receptacle configured to selectively receive the touch-and-hold connector, a light-emitting source coupled to the storage receptacle and associated with the touch-and-hold connector, and an electrical power source.08-13-2009
20090177832Parallel computer system and method for parallel processing of data - The invention relates to multi-computer systems, wherein each computer (07-09-2009
20110289254CONFIGURABLE DIGITAL AND ANALOG INPUT/OUTPUT INTERFACE IN A MEMORY DEVICE - Methods and memory devices are disclosed, for example a memory device that has both an analog path and a digital path that both share the same input/output pad. One of the two paths on each pad is selected in response to command signals that indicate the nature of the signal being either transmitted to the device or read from the device. Each digital path includes a latch for latching digital input data. Each analog path includes a sample/hold circuit for storing either analog data being read from or analog data being written to the memory device.11-24-2011
20120089763COMPUTER AND USB INTERFACE MODULE THEREOF - A computer for charging an electronic device includes a computer, a power supply module, a motherboard and a USB interface module. The power supply module outputs electrical power when the computer is powered down. The USB interface module includes a USB interface and a switch. The USB interface is connected to the power supply and the motherboard and capable of charging the electronic device. The switch is set between the USB interface and the motherboard and controls a communication between the motherboard and the electronic device.04-12-2012
20110296076HYBRID DATA TRANSMISSION EXCHANGER AND HYBRID DATA TRANSMISSION METHOD - The present invention discloses a hybrid data transmission exchanger and a hybrid data transmission method, whereby hosts can access storage units and share data. The hybrid data transmission exchanger comprises an embedded central processing unit, a virtual bridge/switch unit, an optical fiber network connection unit and an Ethernet connection unit. The embedded central processing unit is connected with the storage units and detects the virtual bridge/switch unit, optical fiber network connection unit and Ethernet connection unit to detect the connection states of a host. A host can directly access the storage units via the optical fiber network connection unit or the Ethernet connection unit. When a host is linked to the exchanger via a PCIe interface, the virtual bridge/switch unit converts an address area and a request identification code of the host to correspond to the embedded central processing unit, whereby the host can access storage units.12-01-2011
20110296075MOTHERBOARD USED IN SERVER COMPUTER - An exemplary motherboard includes a substrate, a first CPU socket provided on the substrate for receiving a first CPU, a second CPU socket provided on the substrate for receiving a second CPU, a switching circuit connected to the first CPU and the second CPU, at least one quick path interconnect (QPI) bus connecting the first CPU to the second CPU, a number of first peripheral component interconnect express (PCI-e) interfaces connected to the first CPU via a number of first wires, a number of second PCI-e interfaces connected to the second CPU via a number of second wires, and a activating chip connected to the first CPU and the second CPU via the switching circuit and configured for starting a peripheral device connected to the first PCI-e interfaces or the second PCI-e interfaces.12-01-2011
20090164695PCI LOAD CARD - A PCI load card includes a PCI interface, an operational amplifier, at least two switches, and a controller. A terminal of each switch is connected to an input terminal of the operational amplifier and connected to a standby power pin of the PCI interface via a first resistor. The other terminals of the at least two switches are respectively connected to ground via at least two resistors. The other input terminal of the operational amplifier is grounded. An output terminal of the operational amplifier is connected to a first terminal of the controller, a second terminal of the controller is connected to a system power pin of the PCI interface, a third terminal of the controller is grounded, the power of the controller is adjusted by controlling the at least two switches.06-25-2009
20100153614INFORMATION TRANSMISSION SYSTEM, INFORMATION SENDING DEVICE AND INFORMATION RECEIVING DEVICE - In an information transmission system, an information sending device includes a generating unit that generates instruction information that instructs switching between operation states of each of transmission paths and a sending unit that apportions information to be transmitted to transmission paths that have been set in an effective state and sends the instruction information a transmission path. An information receiving device includes a receiving unit that receives information transmitted through the transmission paths and a restoring unit that restores information to be transmitted based on the information transmitted by the transmission paths that have been set in the effective state in the instruction information received through the transmission path.06-17-2010
20090100211Verification-scenario generating apparatus, verification-scenario generating method, and computer product - Hardware blocks respectively of an arbitrary access origin and an arbitrary access destination that are mutually accessible are extracted from among a plurality of hardware blocks constituting a bus system to be verified, and a path reaching from the access-origin hardware block to the access-destination hardware block is searched for. For each path found, a verification scenario is generated to verify transactions of the access-origin hardware block for a case where access to an address range assigned to the access-destination hardware block occurs, and the verification scenario is output being correlated with the path that corresponds thereto.04-16-2009
20110219165PORTABLE COMPUTER - The portable computer includes a PCIe controller, a DisplayPort connector, and a combination switch. The DisplayPort connector includes a hot plug pin. The combination switch is connected between the PCIe controller and the DisplayPort connector. The combination switch includes a selecting pin electronically connected to the hot plug pin. When the DisplayPort connector is electronically coupled to a discrete graphics card using PCIe, the hot plug pin sends a hot plug voltage signal to the selecting pin, and the combination switch electronically connects the DisplayPort connector to the PCIe controller after receiving the signal.09-08-2011
20110167191ARCHITECTURE FOR AN OUTPUT BUFFERED SWITCH WITH INPUT GROUPS - Embodiments of the present invention provide a system that transfers data between the components in the computer system through a switch. In these embodiments, the switch includes multiple switch chips which are coupled together and are configured to collectively function as a switch. During operation, each switch chip, receives cells from the subset of the set of inputs and selectively transfers each of the cells to at least one output of the subset of the set of outputs coupled to the switch chip or of the subset of the set of outputs coupled to the other switch chips.07-07-2011
20100169535DATA STREAM MANAGEMENT - A method for packetizing and communicating data. Data payloads are allocated to data categories based on processing function. A dedicated communication channel is associated with each data category. A data processing header for each channel precedes the data payload in each data communication packet, includes particulars sufficient to support a data processing operation, and is size-independent of the data payload. The header includes a dominant header sized common to all headers and a subdominant header of size defined for each channel, but independent of the data payload. The dominant header includes an operation identifier explicating the purpose of the data payload followed by a payload-size indicator conveying the size the data payload. The data payload may be empty. Dedicated communication channels include a command channel for keyboard and mouse events, a video raster channel, and a mass storage media block channel.07-01-2010
20100169534MULTIPLE CONNECTIONS TO A SINGLE SERIAL INTERFACE - This invention relates to a method, a computer program product, an apparatus and a system for switching a first switching unit of an apparatus into a state out of a set of states, wherein said apparatus comprises a first serial interface and a second serial interface, each of this first and second serial interfaces comprises at least one data line and a power supply line, and wherein said first switching unit is coupled to the power supply line of both said first serial interface and said second serial interface, wherein said set of states comprises a first state for connecting the power supply of said first serial interface to the power supply of said second serial interface, and a second state for connecting the power supply of said first serial interface to a first further power supply line, said first further power supply line being configured to be connected to a first power supply.07-01-2010
20100115174PCI Express Load Sharing Network Interface Controller Cluster - Embodiments provide load balancing in a virtual computing environment comprising a plurality of PCI-Express switches (the PCIe switching cloud) coupled to a plurality of network interface devices (NICs). An NIC cluster is added between the PCIe switching cloud and the NICs. The NIC cluster is configured to hide NICs from system images and allow the system images to access functions across multiple NICs. The NIC cluster of an embodiment dynamically load balances network resources by performing a hashing function on a header field of received packets. The NIC cluster of an embodiment performs load balancing and state management in association with driver software, which is embedded in the system image. The driver software adds a tag for flow identification to downstream data packets. The NIC cluster distributes data packets based on information in the tag.05-06-2010
20120110235WIRE CONTROL DEVICE AND ELECTRONIC DEVICE USING THE SAME - A wire control device for wired remotely controlling an electronic device. The wire control device includes a USB connector and a control switch, and the control switch generates control signals. The electronic device includes a USB port and a process unit. When the USB port is connected to the USB connector of the wire control device, the process unit receives the control signals via the USB port and executes corresponding functions.05-03-2012
20120066430USE OF PCI EXPRESS FOR CPU-TO-CPU COMMUNICATION - CPUs that generate PCIe auxiliary signals and changing clock signals nevertheless communicate with each other using PCIe owing to PCIe switch assemblies that are disposed in the communication paths to isolate and terminate the auxiliary signals from reaching other CPUs and to isolate changing clock signals, communicating with each other using a fixed clock derived from one of the changing clock signals. Also, the CPUs directly access the memories of CPUs to which they wish to write data so that data is directly written from one CPU memory to another without store-and-forward operations being needed in the network.03-15-2012
20080270670Storage system and path switching method - A storage system is characterized by including: a host apparatus for sending various requests and backup-target data; a virtualization apparatus including a volume that stores the data sent from the host apparatus and a virtual volume that stores replicated data for the data; and a virtual disk library apparatus having a controller apparatus that includes an actual volume for the virtual volume and a tape library apparatus having a tape that stores the replicated data stored in the actual volume, and is characterized in that the controller apparatus has a path switching unit for conducting switching, for a plurality of paths for transferring the data, between a path that connects the controller apparatus to the tape library apparatus and a path that connects the controller apparatus to the virtualization apparatus according to a request from the host apparatus.10-30-2008
20090083471METHOD AND APPARATUS FOR PROVIDING ACCELERATOR SUPPORT IN A BUS PROTOCOL - The present invention provides a method and apparatus for processing a bus protocol packet in order to provide accelerator support. A component receives a bus protocol packet having a requester identifier. The component looks up an agent routing field. The component routes the bus protocol packet to an accelerator agent based on the agent routing field. It processes the bus protocol packet at the accelerator agent based on the agent routing field.03-26-2009
20100088456STORAGE-SHARING BUS SWITCH - The present invention discloses a storage-sharing bus switch, which comprises a bus exchange device, a controller and a plurality of non-transparent bridge devices. The bus used in the present invention is PCI or a like system bus. The bus exchange device connects with the controller and a plurality of storage devices and links to hosts via the non-transparent bridge devices. The storage-sharing bus switch executes data transmission between hosts and storage devices. The controller starts up and monitors the devices linking to the storage-sharing bus switch. The non-transparent bridge devices implement data transmission between hosts and the storage-sharing bus switch and separate the hosts from the devices linking to the storage-sharing bus switch lest operation errors damage the devices. The present invention enables a plurality of hosts to share data storage simultaneously.04-08-2010
20100088455Storage system provided with a plurality of storage modules - For a storage system provided with a plurality of storage modules including a first storage module and a second storage module, the first storage module is provided with a first switch circuit including a plurality of ports and a first circuit connected to any of the plurality of ports included in the first switch circuit via an internal path, and the second storage module is provided with a second circuit. A direct path that is a path for connecting the first switch circuit and the second circuit is connected to any of the plurality of ports included in the first switch circuit. The first circuit issues a packet addressed to the second circuit. The first switch circuit receives the packet addressed from the first circuit to the second circuit, and outputs the packet from a port connected to the direct path to the second circuit.04-08-2010
20090210609Wireless USB hub - A hub has a case with an up-stream Type A USB socket in a top surface and four down-stream Type A sockets in the side surfaces. The hub has internal circuitry interconnecting the ports. Unconventionally for a USB up-stream port, the power contacts of the Type A up-stream socket are provided with a voltage across them for powering the transceiver. However, this is switched off as follows to allow wired transfer of data from the computer, without voltage being passed back the computer.08-20-2009
20100082874COMPUTER SYSTEM AND METHOD FOR SHARING PCI DEVICES THEREOF - In order to provide an inexpensive way to share an I/O device loaded in an I/O drawer among a plurality of blades, in a server system including a plurality of servers, a PCI device, and a manager for initializing a PCI switch, the PCI device has a plurality of virtual functions (VFs). The PCI switch, which has VF allocation information which indicates association between the servers and the VFs, is configured to: receive a transaction from one of the servers or from the PCI device; when the received transaction is a transaction sent from the one of the servers, remove a server identifier with which a sender server is identified and transfer the received transaction to the PCI device; and when the received transaction is a transaction sent from the PCI device, attach a server identifier that is determined based on the VF allocation information.04-01-2010
20100082875TRANSFER DEVICE - A transfer device includes: a first input port operatively connected to a first apparatus; a second input port operatively connected to a second apparatus which is to run in parallel to the first apparatus; an output port operatively connected to a third apparatus; and a controller for controlling a data synchronization in accordance with a process including: receiving first and second data packets from the first and second apparatus, respectively, each of the first and second data packets including a check code; comparing one of the check codes in the first and second data packet with the other; and transferring at least the data of one of the first and second data packets upon determining coincidence of the check codes of the first and second data packets to the third apparatus via the output port.04-01-2010
20090094402PORTABLE COMPUTER HAVING AUXILIARY IO APPARATUS AND SYSTEM SETUP METHOD THEREOF - A portable computer including an auxiliary Input/Output (IO) apparatus, a main controller configured to control the portable computer, a peripheral module configured to perform an individual function of the portable computer, an auxiliary Input/Output (IO) apparatus including a control unit configured to selectively control the peripheral module and being driven by its own operating system (OS), and an embedded controller (EC) configured to sense an operation mode of the portable computer from a Basic Input/Output System (BIOS) and to determine whether the main controller or the control unit of the auxiliary IO apparatus is to control the peripheral apparatus based on the sensed operation mode the of the portable computer.04-09-2009
20090287872Host computer with shared storage device - A host computer formed of a motherboard, a power supply unit with a power switch, a data storage device and an external interface is disclosed to have a transfer switch switcheable between a first switch position and a second switch position, the transfer switch having three contacts in the first switch position for electrically connecting the motherboard to the power supply unit and the data storage device to the power supply unit and the motherboard to the external interface, and two contacts in the second switch position for electrically connecting the data storage device to the external interface through a data transmission interface and the data storage device to said power supply unit respectively. This design allows access to the data storage device, achieving the effect of sharing the data storage device without boosting the computer system.11-19-2009
20090300260SELECTIVE SWITCHING OF A MEMORY BUS - In a system, a memory bus has a first bus segment coupled to a memory controller that includes control logic and a first memory device, a second bus segment coupled to a second memory device, and a switch to selectively couple and decouple the first bus segment and the second bus segment in response to control information from the control logic. Note that the control logic may output control information to the switch to selectively decouple the first bus segment and the second bus segment to effect a change in an electrical length of the memory bus to enable data transfer with respect to the first memory device at a first data rate. Additionally, the control logic may output control information to the switch to selectively couple the first bus segment and the second bus segment to effect another change in the electrical length of the memory bus to enable data transfer with respect to the second memory device at a second data rate that is slower than the first data rate.12-03-2009
20120297108INTEGRATED ELECTRONIC SYSTEM MOUNTED ON AIRCRAFT - The present invention provides an electronic system mounted on an aircraft which can effectively reduce electronic devices and wires by integration of control systems. Specifically, a fuselage (11-22-2012
20080276032ARRANGEMENTS WHICH WRITE SAME DATA AS DATA STORED IN A FIRST CACHE MEMORY MODULE, TO A SECOND CACHE MEMORY MODULE - A storage device control apparatus including first and second systematic memory module groups, each of which is composed of a plurality of memory modules, a memory controller for controlling memory access to the memory modules belonging to each of the first systematic and second systematic memory module groups. When the memory controller detects failure in one of the other memory systems, the memory system performs memory access to the memory modules belonging to its own systematic memory module groups.11-06-2008
20080276034Design Structure for Transmitting Data in an Integrated Circuit - A design structure, which may be generated by a fabless design company, for transmitting data between cores residing in an integrated circuit. Data is transmitted by using hubs located between the cores and an arbiter. The arbiter maintains a table that contains all the valid combinations of routing paths between the cores.11-06-2008
20080276033MULTIPATH REDUNDANT STORAGE SYSTEM ARCHITECTURE AND METHOD - Disclosed is a storage system and method that provides multi-path bus and component interconnection and isolation in a data storage system. A plurality of data storage devices in a removable assembly are connected to a fabric that is configurable to connect some or all of the data storage devices (or “drives”) to a drive controller and configurable to isolate one or more data storage devices from the drive controller. Multiple controllers, fabrics, and interconnecting buses may be employed to provide redundancy in the event of a connector, bus, or controller failure. Computer program code operating in a host, interface controller, and/or drive controller configures the fabric to isolate failed devices and may be employed to optimize data transfer rates. Data storage devices may be multi-ported. The fabric may comprise any device or devices capable of configurably interconnecting data storage devices to one or more controllers and may comprise multiplexers, cross point switches, port bypass controllers. Fabrics may also provide translation or conversion of one bus or interface format to another format.11-06-2008
20090265502SIGNAL PROCESSING DEVICE AND CONTROL METHOD, SIGNAL PROCESSING METHOD, PROGRAM, AND SIGNAL PROCESSING SYSTEM - A signal processing device controls a plurality of signal processing units that process an input signal inputted via a signal line with wide bandwidth, via a control line with narrow bandwidth or the signal line, and includes: a storing unit configured to store correspondence information that associates instruction information indicating an instruction of control with respect to each of the signal processing units, with control information related to all of the plurality of signal processing units, among pieces of control information necessary for each of the signal processing units to execute content of control; and a transmitting unit configured to transmit the control information associated with the instruction information by the correspondence information, to the plurality of signal processing units via the signal line, when control is instructed with respect to the plurality of signal processing units.10-22-2009
20080235430Creation and Management of Routing Table for PCI Bus Address Based Routing with Integrated DID - A method is provided for creating and managing tables for routing packets through an environment that includes multiple hosts and shared PCI switches and adapters. A Destination Identification (DID) field in the PBA is appended to a transaction packet dispatched through the PCI switches, wherein a particular DID is associated with a particular host or system image, and thus identifies the physical or virtual end point of its packet. In one embodiment, packets are routed through PCI switches in a distributed computer system comprising multiple root nodes, wherein each root node includes one or more hosts. The embodiment includes the step of creating a table or like data structure in a specified one of the switches. When a particular host of one of the root nodes becomes connected to the specified switch, a PCI Configuration Master (PCM), residing in one of the root nodes, is operated to enter a destination identifier or DID into the table. The DID is then appended as an address component, to packets directed through the specified switch from the particular host to one of the adapters. The destination identifier is also used to determine that a PCI packet, routed through the specified switch from one of the adapters, is intended for the particular root node.09-25-2008
20100287326Circuit of on-chip network having four-node ring switch structure - A hierarchical ring architecture is constructed with on-chip networks. The on-chip network includes two type-0 ring nodes and two type-1 ring nodes. The present invention provides multiple data transfer in parallel between multiple processor cores or multiple function units and register banks with dynamic configuration. The present invention thus obtains a low control complexity, an optimized local bandwidth, an optimized remote node path, a low routing complexity and a simplified circuit.11-11-2010
20090313413 METHOD FOR WIRING ALLOCATION AND SWITCH CONFIGURATION IN A MULTIPROCESSOR ENVIRONMENT - A method for wiring allocation and switch configuration in a multiprocessor computer, the method including employing depth-first tree traversal to determine a plurality of paths among a plurality of processing elements allocated to a job along a plurality of switches and wires in a plurality of D-lines, and selecting one of the paths in accordance with at least one selection criterion.12-17-2009
20090119440SELF-CONFIGURING BUS FOR CONNECTING ELECTRONIC DEVICES - A design structure for an apparatus for connecting electronic devices having a flexible cable bus housing containing a plurality of same or different communication and power channels extending along a length thereof and a plurality of bus ports at different locations along the bus housing length. Each bus port is capable of being operatively connected to one of the communication or power channels. There is further included a plurality of device connectors adapted to connect to a bus port at one end thereof and to a discrete device at another end thereof. Each connector at the device end has a different plug conforming to one of the communication or power channels. There is preferably further included a switch for connecting each bus port to the communication or power channel conforming to the device end plug when a device connector is connected to the bus port on the bus housing.05-07-2009
20080282017Serial Peripheral Interface Switch - An SPI switch allows selection of a BIOS memory transparent to a Southbridge chipset component. The SPI switch provides address translation to a selected BIOS memory area under the control of a security module processor. The SPI switch also provides command filtering to prevent commands that represent a security risk such as bulk erase commands. Because the SPI switch allows transparent redirection between BIOS programs, booting in different operating modes may be supported without any changes to the basic computer architecture or major chipset components.11-13-2008
20090083472DESIGN STRUCTURE FOR A MEMORY SWITCHING DATA PROCESSING SYSTEM - A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a memory switching data processing system is provided. The memory switching data processing system includes one or more central processing units (‘CPUs’); random access memory organized in at least two banks of memory modules; one or more memory buses providing communications paths for data among the CPUs and the memory modules; and a flexibly configurable memory bus switch comprising a first configuration adapting the first CPU to a first bank of memory modules and a second CPU to a second bank of memory modules and a second configuration adapting the first CPU to both the first bank of memory modules and the second bank of memory modules.03-26-2009
20130219102Local Event Ring In An Island-Based Network Flow Processor - An island-based network flow processor (IB-NFP) integrated circuit includes islands organized in rows. A configurable mesh event bus extends through the islands and is configured to form a local event ring. The configurable mesh event bus is configured with configuration information received via a configurable mesh control bus. The local event ring provides a communication path along which an event packet is communicated to each rectangular island along the local event ring. The local event ring involves event ring circuits and event ring segments. Upon each transition of a clock signal, an event packet moves through the ring from event ring segment to event ring segment. Event information and not packet data travels through the ring. The local event ring functions as a source-release ring in that only the event ring circuit that inserted the event packet onto the ring can delete the event packet from the ring.08-22-2013
20090187694Computer system and management method thereof - Disclosed herewith is a composite type computer system that can assure that a PCI tree to be allocated to a computer is configured completely before the computer is powered. The composite type computer system includes a PCI switch that connects plural computers through PCI interfaces; plural PCI devices connected to the PCI switch; a system controller that controls the computers; and a PCI manager that controls allocation of the PCI devices to the computers. The system controller carries out processings in the steps of (a) powering an object computer to start up its OS; (b) acquiring the identifier of a PCI tree allocated by the system controller to the computer and PCI tree management information denoting the status of the PCI tree; (c) retrying the powering or canceling the powering of the computer if the acquired PCI tree management information denotes the status “not initialized”; and (d) carrying out the powering for the computer if the acquired PCI management information denotes the status “initialized”.07-23-2009
20090144479Computer switcher and method for matching with a plurality of servers - The present invention provides a switcher for managing a plurality of servers and controlling at least one peripheral device, comprising: a transceiver module for transmitting a query instruction to one of the plurality of servers and receiving identification information of the server; and a matching module for receiving the identification information and matching a connection port between the switcher and the server with the server based on the identification information. With the present invention, automatic matching between a KVM switcher and servers can be achieved thus avoiding errors and delay which may occur during manual operations. Further, automatic matching can be performed after the connections between the servers and the KVM have been changed, without the need for excessive manual intervention.06-04-2009
20090024783APPARATUS AND METHOD FOR NETWORK CONTROL - A network control apparatus and network control method is provided. The network control apparatus including: a content addressable memory receiving to store a plurality of addresses which are generated by at least one master intellectual property, determining whether data corresponding to each of the plurality of stored addresses is received, and generating a determination signal; and a packet decoder transmitting each of the plurality of stored addresses and the data corresponding to each of the plurality of stored addresses to a slave intellectual property according to the determination signal. Accordingly, a multiple address issue function can be supported.01-22-2009
20090198863TRANSPARENT PCI-BASED MULTI-HOST SWITCH - A transparent PCI-based multi-host switch. A switch is configured with multiple north facing ports to couple the switch to multiple hosts. The multi-host switch can be included in a variety of switch configurations, including configurations having one multi-host switch, configurations having multiple multi-host switches, and configurations including one or more multi-host switches and one or more single host switches. The switch is designed to include controls to accurately route a packet through the switch.08-06-2009
20090198862Method for switching I/O path in a computer system having an I/O switch - The physical server includes a hypervisor for managing an association between the virtual server and the I/O device allocated to the virtual server. The I/O switch includes: a setting register for retaining a request to inhibit a transaction from being issued from the I/O device to the virtual server; a Tx inhibition control module for performing an inhibition of the transaction from the I/O device to the virtual server, and guaranteeing a completion of a transaction from the I/O device issued before the inhibition; a virtualization assist module for converting an address of the virtual server into an address within a memory of the physical server; and a switch management module for managing a configuration of the I/O switch.08-06-2009
20120079163SKEW MANAGEMENT IN AN INTERCONNECTION SYSTEM - An interconnection system is described where data lanes may be exchanged between lines at intervals along a transmission path so that the differential time delay between bits on a plurality of the lines is reduced when determined at a receiving location. The data lanes may be bound to the lines through the operation of a configurable switch, or by a configurable switch in conjunction with predetermined manufactured connections, or a combination of the techniques. The wiring of a connectorized node module, which may include a memory device, may be configured so that the differential time delay between pairs of input lines of a node, as measured at the output of a node, is reduced.03-29-2012
20120079162TRANSPARENT REPEATER DEVICE FOR HANDLING DISPLAYPORT CONFIGURATION DATA (DPCD) - Consistent with an example embodiment a repeater device is provided for handling signal transmissions, in particular in a DisplayPort environment. The repeater is to be coupled with an upstream device and a downstream device, the repeater being adapted for transmitting signals received from the upstream device to the downstream device and for conditioning the signals before transmission. The repeater is configured to provide a transparent communication path between the upstream device and the downstream device for DPCD access transactions belonging to a second group of DPCD access transactions. For DPCD access transactions belonging to a first group of DPCD access transaction, the repeater is configured to process the DPCD access transactions by accessing one or more DPCD registers included in the repeater.03-29-2012
20090100210Assembly for Permitting Power Over Ethernet Connection - An assembly for permitting “Power-over-Ethernet” (PoE) connection between a PoE control device and the components of a cabling network includes a patch panel or conventional design. The patch panel includes on a front face thereof a plurality of first sockets that are each open on the front face such that a plug inserted into the first socket is connectable to a data cable via a data transmission path forming part of the patch panel. The assembly includes a distribution matrix that is securable onto the front side of the patch panel, the distribution matrix including a plurality of through-going apertures corresponding in number and location to the first sockets of the patch panel such that when the matrix member is secured on the patch panel a said aperture is functionally in register with each of the first sockets. The distribution matrix includes a power bus supported thereby. The assembly includes one or more connector devices, and the power bus is connectable to a PoE controller.04-16-2009
20090210608KVM switch and operation method thereof - A KVM switch and an operation method thereof can share at least one USB device to a plurality of computers, and the computers can directly communicate with the USB device through a switch module. The KVM switch further comprises a microprocessor and a USB controller. When switching in the KVM switch, by using the set information command in USB specification, the microprocessor can control the USB controller to interfere in setting the USB device to become receiving a signal sent by the computer which recognition data is representative. Then, the computers need not execute the enumeration process to recognize the USB device in every switching time. Hence, the KVM switch can improve the compatibility problem and increase switching efficiency.08-20-2009
20120036307COMPUTER ARCHITECTURE WITH SELF-CONTAINED MODULES - The invention relates to the structure, data links and the interconnection of the main logical sections of a computer. The computer architecture consists of N self-contained modules that are connected with the aid of switches to the bus of one or N terminals via a bus corresponding to each module, each module comprises a central processor, a main memory, drives, input-output devices, peripheral items, a bus and a software. The specific features of the other variants of a computer architecture are that the software to be loaded for execution in the main memory of the module is stored entirely or in part on drives which, during the operation of the module, are in a hardware “read-only” mode and in that the software is loaded in the core memory of the module either in advance prior to the operation of the module, or in the module core memory during the operation thereof or in part in the core memory of the module prior to the module operation and in part in the core memory of the module during the operation thereof. The technical result is the protection of the computer against viruses and unauthorized copying of the software.02-09-2012
20100274943LINE-CARD DISABLING FOR POWER MANAGEMENT - A power management apparatus is configured to manage a switch having line-cards with ports. The management apparatus includes a tracking module configured to track activity for each port in a line-card in the switch, and a control module configured to determine whether the line-card is to be disabled. The management apparatus also includes output module configured to initiate a deactivation process for the line-card if all the ports are inactive.10-28-2010
20090248947PCI-Express Function Proxy - Embodiments are described for executing embedded functions in endpoint devices by proxy in a shared PCI Express subsystem. The shared subsystem comprises a plurality of proxy devices coupled to a PCIe fabric, wherein each one of the proxy devices is associated with an endpoint device and coupled to a controlling server through a PCIe link. An associated proxy device comprises a copy of the configuration space of the target endpoint device. Embedded functions of an endpoint device can be accessed by controlling servers through the associated proxy devices. Devices in the shared subsystem use PCI protocol to communicate. The duplication of the endpoint configuration space in the proxy device is administrated by a proxy configuration manager. The proxy device translates destination addresses in upstream and downstream transactions. A proxy interrupt conveyance mechanism relays interrupt messages from an endpoint device to the controlling server via the associated proxy device.10-01-2009
20090248946Information Handling System Including Multiple Compute Element Processor With Primary And Secondary Interconnect Trunks - A symmetric multi-processing (SMP) processor includes a primary interconnect trunk for communication of information between multiple compute elements situated along the primary interconnect trunk. The processor also includes a secondary interconnected trunk that may be oriented perpendicular with respect to the primary interconnect trunk. The secondary interconnect trunk communicates information off-chip via a number of I/O interfaces at the perimeter of the processor chip. The I/O interfaces may be distributed uniformly along portions of the perimeter.10-01-2009
20090248944MODULAR SCALABLE PCI-EXPRESS IMPLEMENTATION - In some embodiments a functional PCI Express port includes first buffers and an idle PCI Express port includes second buffers. One or more of the second buffers are accessed by the functional PCI Express port. Other embodiments are described and claimed.10-01-2009
20090259791ADJUSTMENT NUMBER OF EXPANDERS IN STORAGE SYSTEM - A storage system for storing data includes: a plurality of storage devices; a controller device; a plurality of expanders; and a path adjusting unit. The path adjusting unit includes: a target specifying unit, a destination selecting unit; and a data migrating unit. The target specifying unit specifies target data to be targeted for adjustment in the plurality of storage devices. The destination selecting unit selects a storage device in which to store the specified target data to reduce the number of expanders on a data transfer pathway for the specified target data. The data migrating unit migrates the specified target data to the selected storage device.10-15-2009
20090259790ERGONOMIC SLIDER-BASED SELECTOR - A device connectable to a computer is disclosed. The device comprises a selector defining a pathway and a plurality of positions along the pathway, the selector having a terminal displaceable along the pathway and positionable at one of the plurality of positions, the pathway being substantially straight, each of the plurality of positions having a process associated therewith. The device further comprises a sensor being operable for generating instruction signals. More specifically, the instruction signals are communicable to the computing device for executing thereon the process associated with one of the plurality of positions along the pathway whereat the terminal is positioned.10-15-2009
20100153615COMPOUND COMPUTER SYSTEM AND METHOD FOR SHARING PCI DEVICES THEREOF - A resource management module of a management server for controlling a multi-root I/O manager connected to a PCI switch for connecting a plurality of I/O devices and a plurality of computers with each other includes: failure handling content information indicating, for each computer sharing a multi-root I/O device, a content of a failure handling at an occurrence of a failure in the multi-root I/O device; and failure handling availability status information indicating whether a hardware reset of the multi-root I/O device is possible and updates, upon reception of a notification of the occurrence of the failure in the multi-root I/O device, the failure handling availability status information, and instructs, based on the failure handling availability status information, the multi-root I/O manager to restrain or cancel the hardware reset of the multi-root I/O device.06-17-2010
20080307149Clustering System and Flexible Interconnection Architecture Thereof - An interconnection architecture is provided for flexibly connecting a primary host module or an added host module to a network switch in a clustering system. The interconnection architecture mainly includes plural first slots, a primary function module, an added function module and plural multifunctional buses. The first slots electrically connect the network switch with the primary and added host modules. The primary function module inserts in one of the first slots to electrically connect the primary host module with the network switch; and the added function module inserts in one of the first slots to electrically connect the added host module with the network switch. The multifunctional buses connect the network switch with the first slots and also connect the first slots with the primary host module and the added host module.12-11-2008
20080301352BUS ARCHITECTURE - A system and method for implementing a bus. In one embodiment, the system includes a bus switch operative to couple to a bus, and a plurality of trace segments coupled to the bus switch, where the trace segments have different lengths. The bus switch is operative to connect one of the trace segments to the bus based on at least one system requirement, and the selected trace segment cancels signal reflections on the bus.12-04-2008
20100161871Computer - An all-in-one computer has a switch button is exposed on the front of the housing for a KVM switch, that is a switch for switching manual input data and VDU data. The KVM switch has a keyboard data input connection, a mouse data input connection, and two VDU data input connections. It has two keyboard and two mouse data output connections and one VDU data output connection. It connects a keyboard and mouse to either of the all-in-one computer and an external, laptop computer and either of their VDU data signals to the all-in-one's VDU.06-24-2010
20090077299Method and System for Accessing Data - A method and system for accessing data are disclosed. Specifically, one embodiment of the present invention sets forth a method, which includes the steps of providing a first path for a computing device to direct a first request to access the storage device associated with the computing device, providing a second path for a master to direct a second request to access the storage device based on an operating mode associated with the computing device, and establishing a reliable communication link with the storage device prior to transmitting a command to the storage device.03-19-2009
20100250822Motherboard with Backup Chipset - A motherboard includes a first chipset, a second chipset, a central processing unit (CPU), a low-speed bus, a first switch circuit and a second switch circuit. In a normal setup, the first switch circuit is coupled to the first chipset and the CPU, and the second switch circuit is coupled to the first chipset and the low-speed bus. In a backup setup, the first switch circuit is coupled to the second chipset and the CPU, and the second switch circuit is coupled to the second chipset and the low-speed bus. The motherboard of the present invention further comprises a switch-circuit control unit or a driver configured for switching the first and second switch circuits to be in the backup setup when the first chipset is damaged in the normal setup.09-30-2010
20100250823PCI-EXPRESS COMMUNICATION SYSTEM AND PCI-EXPRESS COMMUNICATION METHOD - A PCI-Express communication system includes a first PCI-Express=PCI-Express bridge connected with an external route complex through a first PCI-Express switch, and configured to perform an address translation on a packet received from the first PCI-Express switch to assign a parameter indicating a first route to a target address of the packet; a second PCI-Express=PCI-Express bridge connected with the external route complex through a second PCI-Express switch, and configured to perform an address translation on a packet received from the second PCI-Express switch to assign a parameter indicating a second route to a target address of the packet; and an address filter configured to limit an address range for the packet received from one of the first PCI-Express=PCI-Express bridge and the second PCI-Express=PCI-Express bridge. A route complex is configured to receive the packet from the address filter.09-30-2010
20100211716COMMUNICATION DEVICE AND METHOD FOR SECURING DATA - A communication device and method for securing data include connecting a processor and at least one storage device via active pins of a switch in the communication device, and setting a secure command for securing data stored in the at least one storage device. The communication device and method further include invoking the secure command to delete the data in the at least one storage device, if text data of a received message matches the secure command, and switching the active pins to the inactive pins so as to disconnect the processor and the at least one storage device, thereby disabling the at least one storage device.08-19-2010
20100211717COMPUTER SYSTEM, METHOD OF MANAGING PCI SWITCH, AND MANAGEMENT SERVER - It is provided a computer system including computers, PCI switches each having first and second ports, a switch management module and a power control module. The switch management module includes an identifying module for identifying a first port coupled to the computer to be booted up, and notifying the PCI switch of the first port, an instruction module for instructing the power control module to boot up the computer, and an allocation management module for managing allocation of one of the I/O device to the computer and notifying the one of the PCI switches of the allocation after the computer is booted up. The PCI switches includes a preventing control module for preventing the computer from detecting a configuration of the first port, and a virtual switch generating module for generating a virtual switch that couples the first port and the second port based on the notification.08-19-2010
20100161872Software-based virtual PCI system - A means for extending a PCI System of a host computer via software-centric virtualization. A Root Complex is virtualized at the host computer, and physically separated with a portion located remotely at an Endpoint, such as at a Remote Bus Adapter. One aspect of the invention avoids the need for a Host Bus Adapter. The invention utilizes 1 Gbps-10 Gbps or greater connectivity via the host's existing standard LAN adapter along with unique software to form the virtualization solution. The invention works within a host's PCI Express topology, extending the topology by adding an entire virtual I/O hierarchy via virtualization. The invention enables I/O virtualization in those implementations where a specialized host bus may not be desirable or feasible. Some examples of this may be a laptop computer, an embedded design, a cost-sensitive design, or a blade host where expansion slots are not available or accessible.06-24-2010
20100199018DATA TRANSFER SYSTEM, DATA TRANSMITTING APPARATUS, DATA RECEIVING APPARATUS, AND DATA TRANSFER METHOD - A data transfer system transmitting and receiving data through a first transmission path and a second transmission path, the data transferring system includes a first apparatus that transmits data through the first transmission path and a second apparatus that receives the data from the first apparatus through the first transmission path, the second apparatus transmits error bit information about the bit position of an error, wherein when the first apparatus receives the error bit information from the second apparatus, the first apparatus transmits switching bit information concerning the bit position which is identified by the error bit information and the transmission path of which is switched to the second transmission path and the data on the bit position identified by the error bit information to the second apparatus through the second transmission path, and the second apparatus receives the data on the bit position identified by the switching bit information.08-05-2010
20090259792Remote operation system - A remote operation system has a server, a client to which a first keyboard is connected, and a KVM switch connected to the server, the client and a second keyboard, the KVM switch including: an acquisition portion that acquires a state of the second keyboard; and the client including: a reception portion that receives a state of the first keyboard, and the state of the second keyboard from the KVM switch; a determination portion that determines whether the state of the first keyboard is identical with the state of the second keyboard; and a transmission portion that transmits information which makes the state of the first keyboard identical with the state of the second keyboard, to the first keyboard when the state of the first keyboard is not identical with the state of the second keyboard.10-15-2009
20120144088ONLINE CALIBRATION METHOD AND DEVICE FOR UNIVERSAL SERIAL BUS SYSTEM - An online calibration method and device for a universal serial bus system is disclosed in the present invention. The method comprises following steps: providing a plurality of chirp JK pairs; detecting the plurality of chirp JK pairs, and loading a power on a terminal resistor of a USB device end of the universal serial bus and its coupled to a terminal resistor of a USB host end of the universal serial bus; detecting a voltage level variation of the chirp JK pair; and processing the online calibration according to the voltage level variation to maintain the voltage level within a preset range.06-07-2012
20120144087CABLE REDUNDANCY AND FAILOVER FOR MULTI-LANE PCI EXPRESS IO INTERCONNECTIONS - Method and apparatus for providing failover operation for a connection between a first PCIE bridge and a first input/output (IO) device are provided. A first set of bussed bits is exchanged between the first PCIE bridge and the first IO device over a first link using a first set of lanes of the first PCIE bridge. In response to detecting the failure in the first link, the first set of bussed bits is exchanged between the first PCIE bridge and the first IO device using an unused portion of a second link connecting a second PCIE bridge and a second IO device.06-07-2012
20080282018APPARATUS FOR DETECTING STATE OF STORAGE DEVICE - An apparatus for detecting the state of a storage device prevents occurrence of a leakage current. A low-level detection unit is provided for each of blocks of a battery pack. Control units are connected to the blocks of the battery pack by way of first switches and are started upon receipt of power supply. The control units and measurement units are connected to the blocks by way of second switches. The control units activate the second switches after being started as a result of activation of the first switches, to thus receive power supply, and commence measurement of block voltages by means of the measurement units. The high-level detection unit supplies a read signal and a synchronous signal to the low-level detection units by way of the first switches.11-13-2008
20100223417SWITCH FOR TRANSFERRING A FILE BETWEEN ASSOCIATED COMPUTERS - A switch for transferring a file between associated computers comprises a first port set coupled a first computer; a second port set coupled to a second computer; a third port set coupled to the first and second computer; a first hub coupled to the first port set; a second hub coupled to the second port set; a data transferring unit coupled between the first hub and the second hub; a driving unit coupled to the first hub and the second hub and stored driving programs; a switching unit coupled to the first hub, second hub and the third port set; a control port set coupled to the switching unit; and a set of a keyboard, a cursor control device and a display unit coupled to the control port set; wherein the switching unit switches the set of keyboard, the cursor control device and the display unit coupled from the first computer to the second computer; wherein the data transferring unit registers a file from the first computer through the first hub and then transfers the file to the second computer through the second hub.09-02-2010
20090106477ASYNCHRONOUS/SYNCHRONOUS KVMP SWITCH FOR CONSOLE DEVICES AND PERIPHERAL DEVICES - A signal switch for sharing a video monitor, a plurality of console devices compliant with an industry standard and one or more than one peripheral device in any of a plurality of computer systems, is provided comprising a CPU with a first memory for storing a management program for managing the signal switch; a hub switch module connected to the CPU and configured to communicate with any of the plurality of computer systems, and the one or more than one peripheral device; a device control module for emulating according to the industry standard the plurality of console devices, connected to the CPU and the hub switch module; a host control module connected to the CPU and configured to communicate with the plurality of console devices; and a video control module connected to the CPU and configured to communicate with a video monitor device.04-23-2009
20100274944SERIAL INTERFACE COMMUNICATION TEST APPARATUS AND TEST METHOD USING THE SAME - A test apparatus for testing quality of serial interface communication between two CPUs of a dual-mode handset includes a processor module and a switch module. The processor module includes two serial ports, each serial port includes an output connector and an input connector, and the two input connectors respectively connected to the two CPUs. The output connector of either serial port connected to either CPU via the switch module. The processor module controls the CPU connected to the output connector to work when the switch module is switched on, and checks data transmission between the two CPUs via the two input connectors when the switch module is switched off.10-28-2010
20120036306SWITCHING CIRCUIT, INFORMATION PROCESSING APPARATUS, AND SWITCHING CIRCUIT CONTROL METHOD - A switching circuit connected to an I/O device having a plurality of functions, the switching circuit comprising: a processing unit that includes tables, each of which corresponds to one of the function of the I/O device, when the processing unit receives a packet that instructs to add a function to the I/O device, configured to select the table that contains a bus number of a destination of the received packet, and configured to notify a number of the selected table; and a filter configured to change a function number of the destination of the received packet to the number of the table notified from the processing unit.02-09-2012
20090164694UNIVERSAL ROUTING IN PCI-EXPRESS FABRICS - A universal routing identifier (URID) is provided to extend the function space in PCI-Express fabrics. Methods and systems based on the URID are provided for configuring URID capable devices and upgrading PCI-Express bridges and switches having lookup tables with access control functionality. The lookup table entry contains URIDs of destination ports, backup ports, acceptance ports, and permitted ports for downstream and upstream filtering, routing and arbitrating of transaction packets. URID capable devices can be incrementally added to current PCI-Express bridges and switches. A configuration mechanism is added to the current PCI/PCI-Express enumeration software. The URID capabilities can be disabled to maintain system compatibility. A URID capable PCI-Express system is able to address ten of thousands single-function devices. A URID capability segment field is provided in the current PCI-Express configuration space. Each URID capable device contains the URID capability segment implemented in its own set of configuration space registers.06-25-2009
20130138861ADAPTER FOR ELECTRONIC DEVICES - An adapter for connecting an accessory to a portable electronic device includes a first connector compatible with a connector of the portable electronic device and a second connector compatible with a connector of the accessory. The connectors of the accessory and the portable electronic device are otherwise incompatible with each other. The adapter provides two levels of authentication. First, the adapter authenticates itself to the portable electronic device. If this first authentication is successful, then the adapter authenticates the accessory to the adapter.05-30-2013
20100325335DUAL MODEM DEVICE AND CONTROLLING METHOD THEREOF - A dual modem device includes a first processor to communicate with a first network and a second processor to communicate with a second network. The first processor includes a USB module to transceive a signal with a computer side using a universal serial bus (USB) interface, a first packet control block to determine a type of the signal transceived via the USB module and to decide a communication path, and a first function block to process a signal associated with the first network. The second processor includes a first control block to process a control signal for the first processor, a second control block to process a control signal for the second processor, and a second function block to process a signal associated with the second network.12-23-2010
20110040922INTERPOSING APPARATUS FOR HOT-PLUGGING DEVICE TESTING - An apparatus adapted to interpose a first device and a second device for selective connection between the first device and the second device, each of the first device and the second device including a connector having a plurality of contacts, the apparatus comprising: a first plurality of contacts for connecting to the plurality of contacts of the first device; a second plurality of contacts for connecting to the plurality of contacts of the second device; and sequential switching means adapted to sequentially connect the plurality of contacts of the first device to the plurality of contacts of the second device.02-17-2011
20110040921KVM SWITCH HAVING UNIVERSAL INPUT AND PROGRAMMABLE USB HUB - A KVM switch of universal input and programmable USB hub includes a main control unit (MCU) chip, having a MCU circuit for controlling functions of the KVM switch, complete reports of console input devices, reading and corresponding transmissions of descriptors; a console device interface chip connected to the MCU; a console port, connected to the console device interface chip; a computer interface chip, connected to the MCU; a re-assignment USB hub chip, connected to the computer interface chip; and a computer port, connected to the re-assignment USB hub chip. Console USB I/O interfaces become dynamic and universal, such that USB devices connected to the control end correspond to the computer port to provide full compatibility, and the console ports can be connected to various USB devices without any limitation of device types, and the devices can be replaced freely during their operation to provide convenient operations and applications.02-17-2011
20110040920SYSTEM AND METHOD FOR PROVIDING MULTI-PROCESS PROTECTION USING DIRECT MEMORY MAPPED CONTROL REGISTERS - A method and system for providing multi-process protection using direct memory mapped control registers is disclosed. According to one embodiment, a computer-implemented method provides a set of control registers for each execution unit of a plurality of execution units in a controller switch. The controller switch facilitates communication between a host system and one or more devices connected to a plurality of device ports of the controller switch. A device driver is provided to allow users' processes to access the controller switch and to grant exclusive access to each execution unit of the plurality of execution units. A first access request to access an execution unit of the plurality of execution units is received from a first process. A set of direct accessible addresses to the set of control registers of the execution unit is allocated, and the first process is granted to exclusive access the execution unit until the first process release the exclusive access to the execution unit. A second access request to access the execution unit received from a second process is denied by checking the assignment of the set of direct accessible addresses to the set of control registers of the execution unit while the first process retains exclusive access to the execution unit.02-17-2011
20110113179SEGMENTING BUS TOPOLOGY - One embodiment is a method that segments a bus topology to increase addressable devices that can attach to a bus. Switching occurs between different segments on the bus having multiple bus segments linked together.05-12-2011
20110213910Stackable Form-Factor Peripheral Component Interconnect Device and Assembly - A stackable form-factor Peripheral Component Interconnect (PCI) device can be configured as a host controller or a master/target for use on a PCI assembly. PCI device may comprise a multiple-input switch coupled to a PCI bus, a multiplexor coupled to the switch, and a reconfigurable device coupled to one of the switch and multiplexor. The PCI device is configured to support functionality from power-up, and either control function or add-in card function.09-01-2011
20110213909Programmable controlled computer switch - A programmable controlled computer switch is disclosed. Console devices and universal serial bus devices of the computer switch can be switched as having a controlling function or a hub function. The computer switch includes a console port interface having console ports for connecting console devices, which initially have a controlling function; a universal serial bus hub port interface having hub ports for connecting universal serial bus devices, which initially have a hub function; plural computer interfaces having a computer port respectively for connecting a computer device; a matrix switching circuit connected to the console port interface, the universal serial bus hub port interface and the plural computer interfaces; and a main controlling circuit connected between the matrix switching circuit and the plural computer interfaces.09-01-2011
20100223418STORAGE APPARATUS AND A DATA MANAGEMENT METHOD EMPLOYING THE STORAGE APPARATUS - A storage apparatus is provided that is capable of reducing data maintenance management costs with a performance that is both highly reliable and fast. The present invention is storage apparatus where an intermediary device is arranged between a controller and a plurality of disk devices of different performances arranged in a hierarchical manner. The controller unit carries out I/O accesses to and from the disk devices via the intermediary devices based on access requests sent from host apparatus. The intermediary device includes a power saving control function for the disk device and carries out operation control such as spin off and spin up of disk devices in accordance with conditions set in advance.09-02-2010
20100036995COMPUTER SYSTEM AND BUS ASSIGNMENT METHOD - To make it possible to take over an IO configuration that is assigned to logical partitions in reallocation of the logical partitions, and to make an IO access work normally. A computer system has a server having an IO bridge, a switch that has a first IO bridge for connecting with the IO bridge of the server through a bus and plural second IO bridges for connecting to plural IO devices through a bus, and bus number assignment management means for fixedly assigning mutually different PCI bus numbers to the plural second IO bridges.02-11-2010
20100036994FLEXIBLE AND EXPANDABLE MEMORY ARCHITECTURES - Memory system architectures, memory modules, processing systems and methods are disclosed. In various embodiments, a memory system architecture includes a source configured to communicate signals to a memory device. At least one memory cube may coupled to the source by a communications link having more than one communications path. The memory cube may include a memory device operably coupled to a routing switch that selectively communicates the signals between the source and the memory device.02-11-2010
20100057974Optimal Representation Of Information Of Communication Paths To I/O Pins During Testing Of An Integrated Circuit - In accordance with an aspect of the present invention, a corresponding list of muxes is maintained for each combination of a peripheral and a mux option. The list is then retrieved to program the required muxes to connect the communication paths from a peripheral on the corresponding mux option, based on which the list is retrieved. In an embodiment, the information is maintained in the form of a table, with each entry storing the data corresponding to a mux and mux option. The entries are linked by appropriate pointers to form the linked list.03-04-2010
20090216934Common storage in scalable computer systems - A computer system comprises a plurality of processing modules, each operable to provide a service to an external entity. Each processing module has a processor and a memory. A storage module is provided, operable to store information required by the processing modules to provide the service. A switching module is also provided, operable to provide a switching service between the processing module and storage module and between the processing module and an external entity.08-27-2009
20100070675BRIDGE, INFORMATION PROCESSING SYSTEM, AND ACCESS CONTROL METHOD - Transparency of resources is provided and ordering in an access is guaranteed between nodes on a computer network. In an information processing system in which a plurality of processor units are connected to each other by a switch, a global address space is introduced into which effective addresses of the processor units are mapped and which is shared by the plurality of processor units. In response to an access request packet issued by a processor unit and designating an effective address of a target node, a bridge for routing an input and output bus of a processor unit to an input and output bus of the switch converts the effective address of the target node into a global address by appending to the packet a node identification number identifying the target node, and outputs the access request packet designating the global address to the switch. After an access request packet for a write operation is output, the bridge confirms whether the write operation is completed in a target node.03-18-2010
20100064090CWUSB Interface - A CWUSB interface 03-11-2010
20110093642ELECTRONIC DEVICE, CONTROL METHOD THEREOF AND RECORDING MEDIUM - An electronic device is connectable to an external device. An interface substrate is detachably connected to a main substrate. A first interface is installed on the interface substrate, and the first interface which is connectable to the external device. A second interface is installed on the main substrate, and the second interface which is connectable to the external device. A selection unit selects one interface of the first interface on the interface substrate and the second interface on the main substrate. A communication unit communicates information with the external device through the interface selected by the selection unit. The selection unit selects an interface which is pre-designated or preferentially selects an interface which first receives a signal from the external device, between the first interface and the second interface.04-21-2011
20110252179APPARATUS AND METHOD FOR ROUTING DATA AMONG MULTIPLE CORES - An apparatus and method for routing data among multicores that is capable of reconfiguring the connection among the multicores are provided. The apparatus includes a configuration information generating unit and at least one switching unit. The configuration information generating unit is configured to generate configuration information that indicates a local network connection among the multicores based on a program counter received from each of the multicores. The at least one switching unit is configured to change a data transfer path among the multicores based on the configuration information.10-13-2011
20110078357MEDIUM VOLTAGE SWITCH UNIT - A medium voltage switch unit comprising an interruption unit and a disconnection unit, wherein the interruption unit comprises a first and a second interruption contact and a first drive unit which moves one of said interruption contacts between a first position in which they are in electrical connection and a second position in which they are spaced apart. The disconnection unit comprises a first and a second fixed disconnection contacts couplable and uncouplable with respective first and second movable disconnection contacts mounted on the interruption unit and electrically connected to the first interruption contact. The interruption unit is mechanically supported by a first fixed conductor and the second interruption contact is electrically connected to said first fixed conductor. The disconnection unit comprises a second drive unit which moves the interruption unit, relative to said first conductor, between: a first disconnector position in which the first movable disconnection contact and the first fixed disconnection contact are coupled while the second movable disconnection contact is isolated from said second fixed disconnection contact; a second disconnector position in which the first and second movable disconnection contacts are isolated from the first and second fixed disconnection contacts; and a third disconnector position in which the second movable disconnection contact and the second fixed disconnection contact are coupled while the first movable disconnection contact is isolated from said first fixed disconnection contact.03-31-2011
20130159594Negotiation Between Multiple Processing Units for Switch Mitigation - A method for maintaining data and clock line synchronization, which may include a clock line that may be driven high after a clock line falling edge to mitigate a clock error. Additionally, the clock error may be mitigated by maintaining a saturated state of a device. Furthermore, a register may be connected to a microcontroller and/or a graphical processing unit to negotiate control of a switch and a bus.06-20-2013
20110016258Routing Data Units Between Different Address Domains - Methods for routing data units and PCI Express switches are disclosed. A plurality of devices may be coupled to a corresponding plurality of physical interfaces, each physical interface having a respective configurable status and a respective address domain, wherein in a first status the interface is transparent, and in a second status the interface is non-transparent. The status of each of the plurality of physical interfaces may be set as transparent or non-transparent. Data units may be switched between the physical interfaces using mapped address input/output, switching data units including masking the address domain for the interfaces configured as non-transparent.01-20-2011
20110016256USB PORTABLE DEVICE - A USB portable device includes an activating USB peripheral, a storing USB peripheral, and a controlling USB peripheral. If the USB portable device is connected to a host apparatus, the activating USB peripheral is recognized as a readable device and a switching program in the recognized readable device is read in the host apparatus and is executed. Consequently, a switching instruction is received from the host apparatus, the readable device is unmounted, and the storing USB peripheral is recognized as the readable device.01-20-2011
20110252178EXPANDABLE HYBRID STORAGE DEVICE AND COMPUTER SYSTEM AND CONTROL METHOD - An expandable hybrid storage device for a computer system includes a first storage unit, an expanded storage device including a disk controller and a second storage coupled to the disk controller via a second data transmission interface, and a selection unit coupled to the first storage unit via a first data transmission interface for selectively connecting the first storage unit to a south bridge circuit of the computer system or the expanded storage device, wherein when the expanded storage device connects to the computer system, the selection unit switches the first storage unit to the expanded storage device so that the disk controller is capable of controlling access to the first storage unit or the second storage unit.10-13-2011
20100057975STORAGE DEVICE - A storage device includes a plurality of interfaces for connection to an external device, a storage unit that stores data, an effective interface setting unit, and a switching instruction receiving unit. The effective interface setting unit sets one of the plurality of interfaces as an effective interface that may access the storage unit. The switching instruction receiving unit receives an effective interface switching instruction during operation of the storage device. The effective interface setting unit switches the interface set as the effective interface based on the effective interface switching instruction.03-04-2010
20100005216DOUBLE NETWORK PHYSICAL ISOLATION CIRCUIT - A double network physical isolation circuit includes a north bridge chip, a bus switch circuit, a first memory, and a second memory. The bus switch circuit includes a first and a second bus switch chip. The first and second memories are connected to different networks. The north bridge chip is connected to the first and second memory. When the bus switch circuit receives a high level signal, the first input pin of the first bus switch chip is in electrical communication with the first output pin of the first bus switch chip, and the first memory is activated. The second memory is grounded through the second bus switch chip. When the bus switch circuit receives a low level signal, the second input pin is in electrical communication with the second output pin of the first bus switch chip, and the second memory is activated. The first memory is grounded through the second bus switch chip.01-07-2010
20090240865Dual-Mode Switch for Multi-Media Card/Secure Digital (MMC/SD) Controller Reading Power-On Boot Code from Integrated Flash Memory for User Storage - A Multi-Media Card/Secure Digital (MMC/SD) single-chip flash device contains a MMC/SD flash microcontroller and flash mass storage blocks containing flash memory arrays that are block-addressable rather than randomly-addressable. MMC/SD transactions from a host MMC/SD bus are read by a bus transceiver on the MMC/SD flash microcontroller. Various routines that execute on a CPU in the MMC/SD flash microcontroller are activated in response to commands in the MMC/SD transactions. A flash-memory controller in the MMC/SD flash microcontroller transfers data from the bus transceiver to the flash mass storage blocks for storage. Rather than boot from an internal ROM coupled to the CPU, a boot loader is transferred by DMA from the first page of the flash mass storage block to an internal RAM. The flash memory is automatically read from the first page at power-on. The CPU then executes the boot loader from the internal RAM to load the control program.09-24-2009
20090222611Digital input/output unit, controller, engineering system, programmer and display unit, especially for automation and plant engineering - A digital input/output unit has a series of terminal points and visual display devices assigned to the terminal points for the display of the respective switching state. It also has an interface for the exchange of process data with a controller and an electronic circuit connected between the interface and the respective terminal points for converting the process data into corresponding switching signals and vice versa. The electronic circuit has an evaluation device for terminal point related signaling data received from the interface in order to activate a respective selected visual display device regardless of the current switching state. Alternatively, or in addition, the electronic circuit can have an evaluation device for a common signaling datum, which can be received from the interface, relative to the complete input/output unit in order to be able to jointly activate all visual display devices regardless of the particular current switching state.09-03-2009
20110153907PATH MAINTENANCE MECHANISM - In the computer system including a host computer and a storage system, the storage system includes a physical disk and a disk controller, and provides a storage area of the physical disk as at least one logical unit. The processor obtains, at a first time point and a second time point different from the first time point, a relation between a logical path and a component through which the logical path passes, stores, as logical path connection information, the relations obtained at the first time point and the second time point, refers to the logical path connection information to compare the logical paths existing at the first time point and the logical paths existing at the second time point with each other, and specifies the logical path which does not exist at the second time point among the logical paths existing at the first time point.06-23-2011
20110153905METHOD AND APPARATUS FOR I/O PATH SWITCHING - A system for input/output path switching comprises a host; a network switch coupled to the host; and a plurality of storage systems which include a first storage system and a second storage system. For switching an I/O path, from a path between the host and the first storage system via the network switch to another path between the host and the second storage system via the network switch, one of the host or the network switch changes FCID (Fibre Channel Node port identifier) information therein, to migrate a WWPN (World Wide Port Name) from association with the first storage system network interface to association with the second storage system network interface. The FCID information includes address information of storage system network interfaces of the storage systems for connecting to the network switch.06-23-2011
20090138647BUS SWITCH, ELECTRONIC EQUIPMENT, AND DATA TRANSFER METHOD - A serial transfer interface bus switch provided between a memory control unit which controls reading and writing of data with the memory, and multiple process control units which process the data is disclosed. The bus switch includes one or more first data transmitting and receiving units provided for each of the process control units for controlling data transmitting and receiving with the process control units; a second transmitting and receiving unit which controls data transmitting and receiving with the memory control unit; and a switching unit which switches between a connection to the first data transmitting and receiving unit and a connection to the second data transmitting and receiving unit. The first data transmitting and receiving unit has a buffer of a size no less than an amount of data which can be transferred with the memory in one instruction from the process control units.05-28-2009
20080228987Storage system and method of storage system path control - The present invention uses memory resources effectively and connects each storage device by a plurality of paths in a switchable manner, thus improving reliability and ease of use, by virtualizing external memory resources as internal memory resources. External storage 09-18-2008
20100325336INPUT-OUTPUT CONTROLLING APPARATUS AND ELECTRONIC MUSICAL INSTRUMENT - An input-output I/F has a pull-up register 12-23-2010
20080256284Simulation Circuit of Pci Express Endpoint and Downstream Port for a Pci Express Switch - Single hardware subsystems that present two software views that appear to be two separate hardware subsystems attached in a hierarchy are implemented with PCI-type arrangements. According to an example embodiment of the present invention, a hardware arrangement is adapted to emulate two virtually separate hierarchical subsystems in a single hardware block. This emulation facilitates the coupling of devices to PCI Express-type communications links while addressing PCI-Express-type linking requirements for such devices.10-16-2008
20080256285Image processing controller and image processing device - A first interface receives image information and an output destination address from a first external device. A second interface transmits image information to a second external device at a lower communication speed than the first interface. A communication path connects the first interface and the second interface to exchange data, on which a first-in first-out memory is provided. Upon the first interface receiving the address, when the second interface is specified as a transmission destination based on the address, a transmitting unit transmits the image information to the second interface through the communication path and the first-in first-out memory.10-16-2008
20110055451CROSS-THREADED MEMORY SYSTEM - In a data processing system, a buffer integrated-circuit (IC) device includes multiple control interfaces, multiple memory interfaces and switching circuitry to couple each of the control interfaces concurrently to a respective one of the memory interfaces in accordance with a path selection value. A plurality of requestor IC devices are coupled respectively to the control interfaces, and a plurality of memory IC devices are coupled respectively to the memory interfaces.03-03-2011
20110010482Self-Healing Chip-to-Chip Interface - A method, apparatus, and computer instructions for managing a set of signal paths for a chip. A defective signal path within the set of signal paths for the chip is detected. Signals are re-routed through the set of signal paths such that the defective signal path is removed from the set of signal paths and sending signals using remaining data signal paths in the set of signal paths and using an extra signal path in response to detecting the defective signal path.01-13-2011
20110022772CONTROL MODULE WITH CONNECTION DEVICES FOR CONNECTION TO CONNECTION TERMINALS OF A LOAD FEEDER AND LOAD FEEDER - A control module with connection devices for connection to connection terminals of a load feeder is disclosed, wherein the load feeder with the control module is connected to a bus system. In at least one embodiment, the control module includes a device interface for at least one connection, interface being independent of the bus system, with a shut-off element able to be connected to the at least one connection device and with the load feeder able to be shut off by way of the shut-off element independently of the bus system. At least one embodiment of the present invention further relates to a load feeder for turning a load on and off and/or for monitoring thereof, including first connection devices for connecting the load feeder to a bus system, second connection devices for connecting the load and a control module, wherein the control module is plugged into connection terminals of the load feeder for connecting to the load feeder and wherein the control module includes a device interface for at least one connection device, the interface being independent of the bus system, with a shut-off element able to be connected to the at least one connection device and with the load feeder able to be shut off by way of the shut-off element independently of the bus system.01-27-2011
20100293316Migration of Switch in a Storage Area Network - A method, system and computer program product for migrating at least one switch in a storage area network is disclosed. The migration is done by analysing the I/O traffic to identify patterns in the I/O traffic of the switch; forecasting future I/O workload of the switch based on one or more identified patterns in the I/O traffic, determining appropriate timing for migration based on the identified patterns and administrator inputs; processing the storage area network configuration data to identify the storage network physical and logical access paths to the or each selected switch to create a first connectivity map; generating a second connectivity map based on the first connectivity map and administrator inputs; and migrating the or each switch migration based on the second connectivity map and the appropriate timing. The migration may comprise routing the I/O traffic from the switch to be migrated to the alternate switches in the storage area network. The migration may further comprising transforming zones on the switch to be migrated and deploying the transformed zones to the new switch11-18-2010
20120311225DEVICE DRIVER-LEVEL APPROACH FOR UTILIZING A SINGLE SET OF INTERFACE INPUT DEVICES FOR MULTIPLE COMPUTING DEVICES - A method for switching interface device input between computing devices can begin with connecting a primary computing device to a secondary computing device using a physical connector cable using the appropriate communications port of each computing device. An interface input control program can be configured to establish a unique interface trigger that defines a user-selected series of inputs that switches the primary computing device between a first input state and a second input state. Input from the interface input devices of the primary computing device can be interpreted by a device driver. In the first input state, the input can be directed to the operating system of the primary computing device. In the second input state, the input can be redirected to the secondary computing device via the physical connector cable, which can be recognized as having originated from local interface input devices.12-06-2012
20120311224EXPOSING EXPANDERS IN A DATA STORAGE FABRIC - A method of selectively exposing expanders in a data storage fabric is disclosed. The method includes generating a phy permission table in a switch expander. The phy permission table is configured for access by an initiator and includes data as to which enclosure expanders are discoverable by the initiator. A zone group of phys from the enclosure expanders assigned to the initiator is created. The phy permission table is updated to identify each phy coupled to the enclosure expanders in the zone group.12-06-2012
20100180064Method and device for implementing USB endpoint multiplexing - A method and device for implementing USB endpoint multiplexing are disclosed. The USB device of the present disclosure supports at least two USB functional devices, and the number of the USB functional devices that are supported by the USB device is larger than the number of data endpoints of the USB device. The method includes: receiving a request for switching over USB functional devices, where the request carries a function identifier of a USB functional device selected by a user; searching for the USB functional device corresponding to the function identifier according to the function identifier; and switching the USB device to the searched USB functional device. The devices include: a USB device and a host. By multiplexing the USB endpoints, the present disclosure achieves an object of using one USB device as a multi-functional device, and hence saves the cost and enhances the user's experience.07-15-2010
20100122011Method and Apparatus for Supporting Multiple High Bandwidth I/O Controllers on a Single Chip - An integrated processor design includes physical interface macros supporting heterogeneous electrical properties. The processor design comprises a plurality of processing cores and a plurality of physical interfaces to connect to a memory interface, a peripheral component interconnect express (PCI Express or PCIe) interface for input/output, an Ethernet interface for network communication, and/or a serial attached SCSI (SAS) interface for storage. Each physical interface may be programmatically connected to a selected interface controller, such as a memory controller, a PCI Express controller, or an Ethernet controller, for example. A plurality of such controllers may be connected to a switch within the processor design, with the switch also being connected to each physical interface macro. Thus, the physical interface macros may be programmatically connected to a subset of the plurality of controllers.05-13-2010
20100122010USB SHARING SWITCH WITH AUTOMATIC SWITCHING CAPABILITIES - A USB printer sharing switch device with automatic switching capabilities is provided for multiple computers to share a USB printer. The sharing switch device transfers USB data between the computers and the printer without changing the data format. The automatic switching function is performed by hardware and firmware of the sharing switch device in cooperation with driver software on the computers. In one implementation, the sharing switch device includes multiple USB device controllers corresponding to the multiple computers, and employs multiple switches and a USB hub so that each computer is connected to its corresponding controller and the computer that is currently connected to the printer can communicate with its controller while printing. The current computer transmits a spooling finished command to its controller when spooling is finished. After receiving the spooling finished command, the sharing switch device automatically switches the printer to another computer.05-13-2010
20110138097COMPUTER SYSTEM FOR CONTROLLING ALLOCATION OF PHYSICAL LINKS AND METHOD THEREOF - The computer system of the present invention has a plurality of SAS target devices, an SAS initiator device, and a service delivery subsystem that is connected to each SAS target device by means of a physical link that is physical wiring and connected to the SAS initiator device by means of a wide link constituted by a plurality of physical links. The SAS initiator device controls how many physical links in the wide link are allocated to a particular SAS target device, whereby access from the SAS initiator device to the SAS target device is made via a physical link that is allocated to the SAS target device and is not made via a physical link that is not allocated to the SAS target device.06-09-2011
20110093644Memory Controller With Ring Bus for Interconnecting Memory Clients to Memory Devices - Embodiments of a distributed memory controller system implemented on a single integrated circuit device are described. In one embodiment, a memory controller that provides an interconnection circuit between a first plurality of memory devices to a second plurality of memory clients includes a ring bus to route at least one of the memory request and data return signals between the memory clients and the memory devices. The ring bus is configured in a ring topography that is distributed across a portion of an integrated circuit device, resulting in a reduction in the maximum wiring density at the center of memory controller. The ring bus structure also reduces the overall number of interconnections as well as the number of storage elements, thus reducing the total area used by the memory controller. The ring bus couples memory clients that are physically located within the ring topography on the integrated circuit to external memory devices through memory device interface circuits located on the integrated circuit device. The memory controller also includes deadlock avoidance mechanisms that utilize virtual channels on the ring bus for one or more defined types of bus traffic.04-21-2011
20110093643ELECTRONIC DEVICE AND METHOD THEREOF FOR IDENTIFYING ELECTRONIC ACCESSORY - An electronic device includes a jack, a voltage processing unit, a measuring unit, a data transmission unit and a switching unit. The jack is adapted to receive a plug of an electronic accessory and has at least one first contact terminal and one second contact terminal. The voltage processing unit is adapted to detect whether a voltage is present at the second contact terminal when a second contact of the plug is in contact with the second contact terminal of the jack. The measuring unit is adapted to measure a parameter resulted from the contact of the first contact terminal of the jack with a first contact of the plug. The data transmission unit is adapted to transmit to or receive from the electronic accessory a data signal through the first contact terminal of the jack. The switching unit is adapted to selectively connect the first contact terminal of the jack electrically to the data transmission unit or the measuring unit according to whether the voltage is present or not.04-21-2011
20120210039SELECTIVE LINK AGGREGATION IN A VIRTUALIZED ENVIRONMENT - A method for selective link aggregation in a virtualized data processing environment is provided in the illustrative embodiments. A data packet is received at a switch. An identifier associated with the data packet is determined. The identifier corresponds to a logical partition in a logical partitioned data processing system. A lookup is performed in a data structure to determine a set of ports associated with the identifier. The set of ports is retrieved from the data structure. A port is selected from the set of ports and the data packet is transmitted from the port to the logical partition.08-16-2012
20090292856INTERSERVER COMMUNICATION MECHANISM AND COMPUTER SYSTEM - An interserver communication mechanism which can eliminate the need for preparing an external I/O device for each of physical servers for communication between the physical servers and can avoid generation of overhead caused by protocol conversion. A plurality of physical servers are connected to the interserver communication mechanism via I/O link and I/O switch. The interserver communication mechanism has a read instruction generator for issuing an instruction to access data of the physical servers and a write instruction generator for transmitting the read data to the other server. Data transfer between the physical servers is carried out in the interior of the interserver communication mechanism by reading out data from a data transmission originator, writing the read data to a transmission destination as it is, and directly turning back the data at the interserver communication mechanism.11-26-2009
20090292855HIGH-RADIX INTERPROCESSOR COMMUNICATIONS SYSTEM AND METHOD - A high-radix interprocessor communications system and method having a plurality of processor nodes, a plurality of first routers and a plurality of second routers. Each first router is connected to a processor node and to two or more second routers. Each first router includes input ports, output ports, row busses, columns channels and a plurality of subswitches arranged in a n×p matrix. Each row bus receives data from one of the plurality of input ports and distributes the data to two or more of the plurality of subswitches. Each column distributes data from one or more subswitches to one or more output ports. Each row bus includes a route selector, wherein the route selector includes a routing table which selects an output port for each packet and which routes the packet through one of the row busses to the selected output port.11-26-2009
20090204742Switching Device and Method of Manufacturing Same - In some embodiments, a switching device is configured to couple a first computer to a first peripheral device and one or more second peripheral devices. The switching device is further configured to couple a second computer to a third peripheral device and the one or more second peripheral devices. The switching device includes: (a) a switch configured to couple to the one or more second peripheral devices; (b) a first hub including: (1) a first upstream port configured to couple to the first computer; (2) a first downstream port configured to couple to the first peripheral device; and (3) at least one second downstream port coupled to the switch; (c) a second hub including: (1) a first upstream port configured to couple to the second computer; (2) a first downstream port configured to couple to the third peripheral device; and (3) at least one second downstream port coupled to the switch. Other embodiments are also disclosed herein.08-13-2009
20110191519SWITCHING DEVICE, SWITCH CONTROL METHOD, AND STORAGE SYSTEM - A queue number acquiring unit acquires a command queuing number that is the upper limit of the number of process-waiting instructions that can be stored in each of storages that make up a virtual disk for each storage. A minimum queue number selecting unit selects the minimum value of the command queuing numbers of the storages that make up the virtual disk as a minimum queue number. A queue number setting unit sets the selected minimum queue number as the command queuing number of the virtual disk that includes the storage device of which the command queuing number is selected as the minimum queue number for each virtual disk.08-04-2011
20100023670METHOD AND SYSTEM FOR ROUTING DATA IN A PARALLEL TURBO DECODER - Described herein are system(s) and method(s) for routing data in a parallel Turbo decoder. Aspects of the present invention address the need for reducing the physical circuit area, power consumption, and/or latency of parallel Turbo decoders. According to certain aspects of the present invention, address routing-networks may be eliminated, thereby reducing circuit area and power consumption. According to other aspects of the present invention, address generation may be moved from the processors to dedicated address generation modules, thereby decreasing connectivity overhead and latency.01-28-2010
20120042114APPARATUS AND METHODS FOR MANAGING EXPANDED CAPACITY OF VIRTUAL VOLUMES IN A STORAGE SYSTEM - Methods and apparatus for expanded capacity virtual volumes in a virtualized storage system. A storage controller of the storage system parses a SCSI command block as it is received to generate a tag value indicating a segment of a virtual volume to which the command block is directed. The tag value is used to select one of a plurality of mapping segment objects stored in a memory of the controller. Each mapping segment objects maps logical block addresses of a corresponding segment of a corresponding virtual volume to physical storage addresses on the physical storage devices that comprise the virtual volume. An I/O processing circuit of the controller then processes the SCSI command block in accordance with the mapping information in the selected mapping segment object. In one exemplary embodiment, each segment of a virtual volume comprises 2 terabytes of storage capacity of the virtual volume.02-16-2012
20110153906SWITCH AND NETWORK BRIDGE APPARATUS - A network system that is part of a main system includes: a first PCI express-network bridge with a first control unit and a first PCI express adapter terminating a first PCI express bus; and a second PCI express-network bridge connected to the first PCI express-network bridge through a network. The second PCI express-network bridge includes a second control unit and a second PCI express adapter terminating a second PCI express bus, wherein the first control unit detects a destination of a packet sent from the first PCI express adapter, searches a physical address of the destination from a packet encapsulating table, and encapsulates the packet in a frame so that the frame includes the physical address, and wherein the second control unit removes the encapsulation tagged to the packet, and transfers the packet to the destination through the second PCI express bus by referring to a PCI express configuration register.06-23-2011
20120005399DATA TRANSMISSION SYSTEM AND METHOD OF READING DATA - In a request issuing device, a specific read request unit generates a read requesting write packet including a predetermined address of a memory of a request receiving device as a write address and including, as a read address, the address of the memory in a payload. In the request receiving device, when data is written into the predetermined address of the memory, a specific read request responding unit detects reception of the read request, reads the data from the read address of the memory written into the predetermined address, and generates a read responding write packet including, in the payload, the data that has been read.01-05-2012
20120005398ELECTRONIC DEVICE AND CONTROL METHOD THEREOF - According to one embodiment, an electronic device forming a first communication path which couples a first interface of a high-rank unit and a second interface of a mid-rank unit and a second communication path which couples a third interface of the mid-rank unit and a fourth interface of a low-rank unit, while cutting off a third communication path which couples the first interface and the fourth interface, in an ordinary state. When data needs to be write from the high-rank unit to the low-rank unit, the electronic device forming the third communication path and cutting off the first communication path and the second communication path.01-05-2012
20120005397SENSE AMPLIFIER AND SEMICONDUCTOR APPARATUS INCLUDING THE SAME - A sense amplifier is configured to transfer data on a first data I/O line to a second data I/O line or to transfer data on the second data I/O line to the first data I/O line. The first data I/O line is substantially continuously coupled to the second data I/O line during an active operation.01-05-2012
20120005396DATA ACCESS AND MULTI-CHIP CONTROLLER - A single data bus to a memory device can be split up into a number of data bus portions, each of which is managed by a different respective controller chip of multiple controller chips. During a memory access to a respective memory device, each of the multiple controller chips controls a different corresponding portion of the data bus to retrieve data from or store data to the memory device depending on whether the access is a read or write. To perform the data access, a synchronizer circuit (internal and/or external to the memory controller chips) synchronizes the multiple memory controller chips such that one of the memory controller chips drives the address bus and/or control signals to the memory device. After setting the address to the memory device, the memory controller chips either read data from or write data to the memory device based on the address.01-05-2012
20120011297Isolation Switch for Fibre Channel Fabrics in Storage Area Networks - An isolation switch blade Fibre Channel switch presents F_ports to form a first Fibre Channel fabric and N_ports to a second Fibre Channel fabric to appear as node devices. The isolation switch blade may be used to connect a plurality of blade servers to a Fibre Channel fabric. Fabric events engendered by the insertion or removal of hot-pluggable devices are handled by the isolation switch blade and “event storms” on the Fibre Channel fabric are avoided. The isolation switch blade presents the blade servers to the FC fabric as a virtualized N_port.01-12-2012
20120011296Multi-Hardware-System Data Processing Device and Information Input Method Thereof - Provided are a multi-hardware-system data processing device and information input method thereof, the multi-hardware-system data processing device comprising a first hardware system, a second hardware system, a switcher and a shared device; wherein the second hardware system comprises a second control module for generating a message when the second hardware system requires a user to input the information to be inputted, and a second communication module for sending the message to the first hardware system; wherein the first hardware system is connected to the shared device via the switcher and comprises a first communication module for receiving the message, and a first user interaction module for obtaining an input interface to be used by the user to input the information to be inputted according to the message, obtaining the information inputted by the user in the input interface, and sending the inputted information to the second hardware system via the first communication module; the second control module processes the inputted information. By the invention, it is not necessary to conduct switch when the background hardware system needs information to be inputted.01-12-2012
20120117295MULTI-STAGE INTERCONNECTION NETWORKS HAVING FIXED MAPPINGS - In one embodiment, a multistage interconnection network (MIN) has two or more configurable stages, each stage having a plurality of switches. The network has one or more unused input terminals, each mapped using fixed switch connections to an unused output terminal. The network also has a set of used input terminals that are selectively mapped to a set of used output terminals based on values of control signals supplied to the stages. Each stage receives a different control signal, and each control signal is generated by cyclically shifting a control seed by a corresponding cyclic-shift value. Fixing the mappings of the unused terminals ensures that the used input terminals are not mapped to any unused output terminals. By storing only the control seed, memory requirements are reduced over networks that explicitly store individual control signals for all of the stages.05-10-2012
20120059969NON-INVASIVE DIRECT-MAPPING USB SWITCHING DEVICE - A non-invasive direct-mapping USB switching device includes a main-controlled microprocessing module connected to a high-impedance module, and the high-impedance module is provided for detecting and monitoring a functional instruction code of a USB device transmitted from a data transmission module, such that a USB connecting module can be used for transmitting the USB data and functional instruction code to detect and monitor the data transmission module when the USB device is connected to the USB switching device. If the data transmitted from the data transmission module is not the required functional code, the non-required functional code (such as the USB data) will be passed, so that the USB device can be connected and communicated with a plurality of computer devices through another USB connecting module and a switching module to achieve a plug-and-play function.03-08-2012
20120059970MEMORY CONTROLLER SUPPORTING CONCURRENT VOLATILE AND NONVOLATILE MEMORY MODULES IN A MEMORY BUS ARCHITECTURE - A memory/storage module is provided that implements a solid state drive compatible with Serial Advanced Technology Attachment (SATA) or Serial Attached SCSI (SAS) signaling on a double-data-rate compatible socket. A detachable daughter card may be coupled to the memory module for converting a memory bus voltage to a second voltage for memory devices on the memory module. Additionally, a hybrid memory bus on a host system is provided that supports either DDR-compatible memory modules and/or SATA/SAS-compatible memory modules. In one example, the memory/storage module couples to a first bus (DDR3 compatible socket) to obtain voltage and/or other signals, but uses a second bus for data transfers. In another example, the memory module may repurpose/reuse electrical paths that typically carry non-data signals for data traffic to/from the memory/storage module. Such data traffic for the memory/storage module permits concurrent data traffic for other memory modules on the same memory bus.03-08-2012
20120159036INTEGRATION CONNECTING APPARATUS IN MOBILE TERMINAL AND METHOD FOR OPERATING THE SAME - An apparatus and method for operating a connector of a mobile terminal are provided. The apparatus includes a connector including a plurality of pins, a plug of a peripheral device, a display unit for displaying a menu for setting a connector mode, an input unit for receiving selection of one connector mode from the menu for setting a connector mode, a main processor for connecting with a switch unit through a data line, a sound line, a microphone line, and a control line, for receiving connector mode selection information from the input unit, and for transferring switching information through the control line, and the switch unit for connecting with a subset of the pins of the connector, and selectively connecting the subset of the pins to at least one of the data line, the sound line, and the microphone line.06-21-2012
20120159035SYSTEM AND METHOD FOR SWITCHING USE OF SERIAL PORT - A baseboard management controller (BMC) of a server includes a general purpose input output (GPIO) pin. An voltage level of the GPIO level determines if a BIOS of the server or the BMC uses a serial port of the server. If the BMC wants to use the serial port and the voltage level of the GPIO pin is at a high level, the serial port can be used by the BMC. If the BMC wants to use the serial port but the voltage level of the GPIO pin is not at the high level , the serial port is be used by the BIOS. If the BIOS has been initialized, the voltage level of the GPIO pin is pulled up.06-21-2012
20110107004Network Switch - A system and method for electronically transferring data between servers in a Local Area Network (LAN) requires a Network switch. Essentially, the Network switch incorporates a PCI Express switch that is run by a Central Processing Unit (CPU). A plurality of connectors (i.e. one for each server in the system) is provided to directly connect the PCI Express capability of the respective server to the PCI Express switch. With these connections, the CPU is used to implement an Internet Protocol (IP) routing function in compliance with IP addresses provided by respective servers to route data through the system from one server to another.05-05-2011
20110099317INPUT-OUTPUT MODULE FOR OPERATION IN MEMORY MODULE SOCKET AND METHOD FOR EXTENDING A MEMORY INTERFACE FOR INPUT-OUTPUT OPERATIONS - An I/O module configured to operate in a memory module socket and method for extending a memory interface are generally described herein. The I/O module may include a serial-presence detection (SPD) device to indicate that the I/O module is an I/O device and to indicate one or more functions associated with the I/O module. The I/O module may also include a serial data controller to communicate serial data in accordance with a predetermined communication technique with a configurable switch of a host system over preselected system management (SM) bus address lines and unused system clock signal lines of the memory module socket. The predetermined communication technique may include a peripheral component interconnect express (PCIe), a Serial Advanced Technology Attachment (SATA), a Serial Attached Small Computer System Interface (SAS), a universal-serial bus (USB) or a switched-fabric (InfiniBand) communication technique.04-28-2011
20120124268CONTROL APPARATUS FOR PROCESS INPUT-OUTPUT DEVICE - A control apparatus for an input-output device includes a hardware part and a software part, in which a controller in the hardware part carries out a control operation in accordance with a signal from the input-output device, outputs a result of the control operation to a process, and has a timer unit to be excited at a constant period; and the software part has an information process part, a control process part, and an interrupt control unit to switch over the information process part and control process part one another, in which the interrupt control unit suspends an execution of the information process part to execute the control process part in priority and resume the information process part by switching over to the information process part from the control process part, when the execution of the control process part is terminated.05-17-2012
20120124267VIDEO GRAPHICS ARRAY INTERFACE SWITCH APPARATUS - A video graphics array (VGA) interface switch apparatus includes first to third VGA interfaces, a single-pole double-throw (SPDT) switch, a switch control chip, and first to sixth electronic switches. The first VGA interface is connected to the second and third VGA interfaces through the switch control chip and the electronic switches. The SPDT switch is used to control the first VGA interface to be selectively connected to the second or third VGA interface.05-17-2012
20120166702ELECTRONIC APPARATUS, METHOD FOR CONTROLLING ELECTRONIC APPARATUS, TRANSMISSION APPARATUS, AND RECEPTION APPARATUS - An electronic apparatus includes a first communication unit configured to perform I2C bidirectional communication with an external apparatus using two signal lines included in a transmission path as I2C communication lines, a second communication unit configured to perform bidirectional differential communication with the external apparatus using the two signal lines as high-speed data communication lines, a switching unit configured to select a first communication state in which the first communication unit is connected to the two signal lines or a second communication state in which the second communication unit is connected to the two signal lines, and a controller configured to control operation of the switching unit.06-28-2012
20120131256I/O CONTROL SYSTEMS AND METHODS - An input/output (“I/O”) port control system is provided. The system can include an I/O controller (05-24-2012
20120317330PERIPHERAL COMPONENT INTERCONNECT EXPRESS INTERFACE CARD - An exemplary Peripheral Component Interconnect Express (PCIE) interface card is electrically coupled to a CPU. The PCIE interface card includes a circuit board, a first PCIE interface module arranged on the circuit board, at least one second PCIE interface module arranged on the circuit board, and a PCIE switch arranged on the circuit board. The PCIE switch is electrically coupled to the first PCIE interface module and the at least one second PCIE interface module. The PCIE switch transmits data from the CPU to the first PCIE interface module, and exchanges data between the CPU and the at least one second PCIE interface module.12-13-2012
20120317329KEYBOARD EQUIPPED WITH SWITCHING INTERFACES - A keyboard equipped with switching interfaces includes a key set module, a circuit unit, a wired transmission interface, a wireless transmission interface and a switch unit. The key set module includes a plurality of keys depressible by users to trigger the circuit unit to generate a message signal. The circuit unit is electrically connected to the wired transmission interface and wireless transmission interface. The wired transmission interface is electrically connected to a transmission cable to output therethrough. The switch unit is electrically connected to the circuit unit and triggers the circuit unit to output the message signal to the wired transmission interface or wireless transmission interface according to user's actions.12-13-2012
20120215958Variable Impedance Control for Memory Devices - This document generally describes systems, devices, methods, and techniques for variably controlling impedance for a memory device where multiple NVM units (e.g., NVM dies) are accessible over a shared bus. Impedance can be varied using switches that are configured to switch between a NVM unit and an impedance terminal. Switches can be adjusted during operation of a memory device so that a memory controller is connected over a shared bus to a selected single NVM unit and one or more impedance terminals. Impedance terminals can be configured to provide a relatively small load (a smaller load than an NVM unit) that is impedance matched (alone or in combination with other impedance terminals and/or a NVM unit) with a source impedance on a shared bus that is provided by a memory controller.08-23-2012
20100049897Computer and method for sharing input device thereof - According to the present invention, a computer is provided, which comprises a host system, an embedded subsystem, a power source, an input device control module, a first transmission interface and a second transmission interface, the input device control module being connected to the embedded subsystem through the first transmission interface, wherein the input device control module is configured to establish, in response to receipt of a first switching instruction, communication with the embedded subsystem such that the embedded subsystem is enabled to process input data from an input device and to transmit the input data obtained from the input device to the first transmission interface; and the embedded subsystem is configured to receive the input data from the first transmission interface, process the input data and perform an operation corresponding to the input data. According to the present invention, one set of input devices can be shared between a computer and an embedded system through design and modification in software without any change in the existing hardware design for the computer.02-25-2010
20100274945AUTOMATIC SELF-ADDRESSING METHOD FOR WIRED NETWORK NODES - A method and system for addressing nodes in a multi-drop wired network are disclosed. In an embodiment nodes communicate via a two-way communication bus. Upon receipt of an address command, a first node assigns itself a first address, closes a switch to activate an output port of the first node to enable a second node to receive communications from the first node, and sends a second address onto the two-way communication bus. The second address is received by all previously addressed nodes, including a controller if used, as well as the second node, which is as yet unaddressed. Upon receipt of the second address, the second node repeats the process. If a node does not receive an acknowledgement that a subsequent node has addressed itself, that node deactivates its output port and terminates the network.10-28-2010
20120254495X2 10GBASE-T Transceiver with 1 Gigabit Side-Band Support - An apparatus includes a transceiver device mounted on a printed circuit board and configured to selectively transmit and receive signals at a first data rate or signals at a second data rate. An X2 form factor pluggable connector disposed at one end of the printed circuit board includes first and second pins that respectively convey signals at the first and second data rates between the transceiver device and a system device. A port device disposed at an opposite end of the printed circuit board conveys signals between the transceiver device and a network device. A management circuit determines which of the first and second data rates is selected based on transmissions between the system device and the network device and controls the transceiver device to transmit and receive signal at the first data rate via the first pins and at the second data rate via the second pins.10-04-2012
20120185635REDUNDANT DATA BUS SYSTEM - There are configured a first transmission path, along which data is transmitted/received between a controller and a first microcomputer through a first driver, and a second transmission path, along which data is transmitted/received between the controller and the first microcomputer through a second driver. The controller transmits an operation check signal to the first microcomputer through the first or second transmission path, and receives a response signal from the first microcomputer through the first or second transmission path.07-19-2012
20120185633ON-CHIP ROUTER AND MULTI-CORE SYSTEM USING THE SAME - A table for changing destination has a destination address in a shared memory and an identifier of a router directly connected to a destination core, in association with each other, and is set by a source core. A search unit performs a first search for searching whether the table has an effective entry having the same address as the destination address in the shared memory, and stored in a header of a write request packet received by the source core. A route calculation unit performs a route calculation with a destination that is a router of an identifier of the entry, if the effective entry is found as a result of the first search. A header generator stores the router identifier obtained by the route calculation in a hop router field of the header of the write request packet, and sets a rerouted flag representing a change in destination.07-19-2012
20120185634COMPUTER SYSTEM AND METHOD FOR INHERITING HBA IDENTIFIER OF PCI CARD - A PCI card's HBA identifier table held in an IODC in an IO slot expansion unit is read and recorded on a PCIe switch register of a PCIe switch. After a server blade is powered on so that an EFI is activated, the EFI reads the HBA identifier table recorded on the PCIe switch register and updates an HBA identifier of an HBA mounted in each PCI card. The HBA mounted in the PCI card operates with the updated HBA identifier of the PCI card. Thus, even when the PCI card is replaced by a new PCI card because of failure or the like, the new PCI card can operate with the same HBA identifier as that before the replacement. Therefore, a user does not have to register the HBA identifier of the PCI card newly in a device connected to the PCI card.07-19-2012
20090319716MEMORY SYSTEM AND BUS SWITCH - A memory system includes a nonvolatile memory having a plurality of nonvolatile memory chips incorporated therein, a control circuit that controls the nonvolatile memory, an MPU that controls the control circuit, and an interface circuit that communicates with a host, all of which are mounted on a board of the memory system, and the memory system further includes a bus switch that switches connection of a signal line between the control circuit and the nonvolatile memory chips.12-24-2009
20120084486SYSTEM AND METHOD FOR USING A MULTIPATH - In a path determination unit of a SAS expander connected to a SAS initiator and connected via first and second paths to a SAS target, an SSP controller receives an SSP command frame received from the SAS initiator; a requested-data-length manager stores a requested data length of the SSP command frame in a requested-data-length storage unit; and a data-transfer-amount manager selects one of the first and second paths having a smaller one of the data transfer amounts stored in a data-transfer-amount storage unit, and adds the requested data length to the data transfer amount of the selected path. The SSP command frame is transmitted to the SAS target via the selected path. Upon receipt of an SSP response frame responding thereto, the requested data length is deleted from the requested-data-length storage unit, and the requested data length is subtracted from the data transfer amount of the selected path.04-05-2012
20120233375ADJUSTMENT OF POST AND NON-POST PACKET TRANSMISSIONS IN A COMMUNICATION INTERCONNECT - In a communication interconnect such as PCIe which favors post transmissions such as write requests over non-post transmissions such as read requests and completions, methods and systems for shortening the delay for non-post transmissions while maintaining fairness among the post transmissions. Undispatched non-post transmission requests are monitored on a running basis; and when a running value of the undispatched non-post transmission requests exceeds a threshold; ones of the post transmission requests are randomly dropped.09-13-2012
20120265919INTERFACE DEVICE AND WIRING BOARD - In the case of mounting two serial communication interfaces such as PCI-e and USB 3.0 with standards different from each other, it is allowed to flexibly address a design change and the like, and reduce a board area. An interface device is provided with a PCI-e PHY I/F, a USB 3.0 PHY I/F with equivalent specifications of a PIPE I/F to that of the PCI-e PHY I/F, and a system controller for controlling the PCI-e PHY I/F and the USB 3.0 PHY I/F. The interface device includes a PIPE I/F bridge in which the PCI-e PHY I/F and the USB 3.0 PHY I/F are provided, and the PIPE I/F bridge selectively switches connection of the PCI-e PHY I/F or the USB 3.0 PHY I/F with the system controller.10-18-2012
20120265918INTERFACE DEVICE AND WIRING BOARD - In the case of mounting two serial communication interfaces such as PCI-e and USB 3.0 with standards different from each other, it is allowed to flexibly address a design change and the like, and reduce a board area. An interface device includes a PCI-e I/F, a USB 3.0 I/F with characteristic impedance and an electric characteristic which are equivalent to those of the PCI-e I/F, and a controller provided with the PCI-e I/F and the USB 3.0 I/F. The interface device is provided with a PHY bus switch for selectively switching between the PCI-e I/F and the USB 3.0 I/F, and in which wiring for connecting the PCI-e I/F and the PHY bus switch and wiring for connecting the USB 3.0 I/F and the PHY bus switch are shared therebetween.10-18-2012
20110016257DISK SUBSYSTEM - A protocol controller disposed between switches in a fiber channel fabric switch circuit and disk drive units for converting a protocol to enable one-to-one connectivity established between controllers and disk drive units.01-20-2011
20120271980TEST DEVICE AND METHOD FOR TESTING SERIAL PORTS OF COMPUTING DEVICE - A test device for testing serial ports of the computing device includes a multiplexer, a USB interface, a signal conversion unit, a switch unit, and multiple serial port interfaces. The USB interface is connected to a USB port of the computing device. Each of the serial port interfaces is connected to a serial port of the computing device. The signal conversion unit is connected to the USB interface of the test device, and connected to the serial port interfaces through the multiplexer. The signal conversion unit converts serial signals into USB signals, or converts USB signals into serial signals, to transmit testing signals between the USB port and the serial ports. The switch unit controls a serial port to be tested to connect to the signal conversion unit through the multiplexer, to form a test channel to test functions of the serial port.10-25-2012
20120278523DISK SUBSYSTEM - A protocol controller disposed between switches in a fiber channel fabric switch circuit and disk drive units for converting a protocol to enable one-to-one connectivity established between controllers and disk drive units.11-01-2012
20110320677DATA PROCESSING APPARATUS, DATA PROCESSING METHOD, AND STORAGE MEDIUM - A data processing apparatus comprising: a determination unit to determine whether data input from input/output module is data to be processed by a plurality of processing modules in a setting order; and a switching unit to switch a first data and second data processing path, so that when the determination unit determines that the data input from the input/output module is not data to be processed by the processing modules in the setting order, the communication modules circulate data via the first data processing path used to transfer the data in an order in which the communication modules are connected, and otherwise, the communication modules circulate data via the second data processing path used to control the communication modules to transfer the data in the setting order.12-29-2011
20110320676SHARING DEVICE WITH MULTI CONNECTING PORTS FOR COMPUTER PERIPHRY DEVICES - The present invention relates to a sharing device with multi connecting ports for computer periphery apparatus, capable of connecting to a plurality of hosts and computer periphery apparatus, so as to facilitate any one host of the plurality of hosts be able to communicate with and control the plurality of computer periphery apparatus without installing any high-price network sharing equipments, the sharing device comprises: a plurality of HUBs, which are parallel to each other; and a plurality of connecting ports.12-29-2011
20100199017Data Encoding Using Spare Channels in a Memory System - Implementations of encoding techniques are disclosed. The encoding technique, such as a Data bus Inversion (DBI) technique, is implementable in a vertically-stacked memory module, but is not limited thereto. The module can be a plurality of memory integrated circuits which are vertically stacked, and which communicate via a bus formed in one embodiment of channels comprising Through-Wafer Interconnects (TWIs), but again is not limited thereto. One such module includes spare channels that are normally used to reroute a data signal on the bus away from faulty data channels. In one disclosed technique, the status of a spare channel or channels is queried, and if one or more are unused, they can be used to carry a DBI bit, thus allowing at least a portion of the bus to be assessed in accordance with a DBI algorithm. Depending on the location and number of spare channels needed for rerouting, DBI can be apportioned across the bus in various manners. Implementations can also be used with other encoding techniques not comprising DBI.08-05-2010
20090037638Backend-connected storage system - A switch device is interposed between a controller and a storage device in a storage system. One or more physical ports among the plurality of physical ports that the switch device has are physical ports that are physically connected, without passing through a host, to one or more physical ports among the plurality of physical ports that another switch device in another storage system has.02-05-2009
20130013842CONTROLLER AND TRANSFER SPEED CONTROL METHOD - A USB 3 host controller according to the present invention includes a transfer speed switching unit besides a transfer data converting unit that mutually converts transfer data from a USB device and transfer data from a PCI Express bus. The transfer speed switching unit receives transfer information regarding data transfer from the USB device via a USB 3 interface when the USB device is connected, and identifies a transfer speed used by a PC side according to the transfer information or a result of analyzing the transfer information. Then, when a current transfer speed of the PC side is different from the identified transfer speed, the transfer speed switching unit transmits a speed switching signal indicating switch to the identified transfer speed to a PCI master via a PCI express interface.01-10-2013
20120151114TOUCH MODULE SWITCH CIRCUIT FOR ALL IN ONE COMPUTER - A touch module switch circuit includes a universal serial bus (USB) display circuit, a touch module, a first resistor, a second resistor, a first diode, a second diode, a USB switch chip, and a USB interface. The touch module selectively communicates with one of the USB display circuits and the USB interface by control of the USB switch chip together with the first resistor, the second resistor, the first diode, and the second diode.06-14-2012
20130019046DATA TRANSMITTING DEVICE AND SYSTEM FOR PORTABLE DEVICE AND METHOD THEREOFAANM SHIEH; Yeong-RueyAACI Hsinchu CityAACO TWAAGP SHIEH; Yeong-Ruey Hsinchu City TWAANM Cho; Shih-KengAACI Hsinchu CityAACO TWAAGP Cho; Shih-Keng Hsinchu City TWAANM Liu; Hsu-PinAACI Hsinchu CityAACO TWAAGP Liu; Hsu-Pin Hsinchu City TWAANM Hsu; Wei-ShuAACI Hsinchu CityAACO TWAAGP Hsu; Wei-Shu Hsinchu City TWAANM Lin; Chi-HanAACI Hsinchu CityAACO TWAAGP Lin; Chi-Han Hsinchu City TWAANM Wang; Yu-ShiangAACI Hsinchu CityAACO TWAAGP Wang; Yu-Shiang Hsinchu City TW - A data transmitting method for communicating one of a plurality of portable devices with a host computer via a data transmitting device having a plurality of USB connector is disclosed. In one embodiment of the present invention, the method includes the following steps: firstly, a switch circuit is configured in one of the portable devices. Then, the portable device having the switch circuit is coupled with the data transmitting device. Afterward, a data transmission path between the host computer and the portable device having the switch circuit is connected by the switch circuit to transmit data between the portable device having the switch circuit and the host computer, or the data transmission path between the USB connector, which is not connecting with the portable device having the switch circuit, and the host computer is connected by the switch circuit.01-17-2013
20110161547METHOD AND DEVICE FOR DISABLING A HIGHER VERSION OF A COMPUTER BUS AND INTERCONNECTION PROTOCOL FOR INTEROPERABILITY WITH A DEVICE COMPLIANT TO A LOWER VERSION OF THE COMPUTER BUS AND INTERCONNECTION PROTOCOL - A method and a device for disabling a lower version of a computer bus and interconnection protocol (e.g., Peripheral Component Interconnect Express (PCIe) 2.0 or higher) for interoperability with a receiver compliant to a lower version of the protocol are disclosed. The device detects a presence of a receiver, and starts link training. During the link training, the number of link training failures or the elapsed time is counted. The device transmits a training sequence including symbols set in accordance with a higher version of the protocol that the device supports on each lane that the receiver is detected as long as the number of link training failures or the elapsed time is below a predetermined threshold. If the number of link training failures or the elapsed time reaches a predetermined threshold, the device transmits a training sequence including symbols set in accordance with a lower version of the protocol.06-30-2011
20130173839SWITCH DISK ARRAY, STORAGE SYSTEM AND DATA STORAGE PATH SWITCHING METHOD - A disk array for a storage system that includes a dual controller disk array and a server includes a disk frame and two controller nodes. Each controller node includes a switch, where a port of the switch is connected to a port of a switch of a peer controller node. Each controller node is configured to detect whether the peer controller node is invalid through the port. When it has been detected that the peer controller node is invalid, a local controller node enables the peer controller node to send, through the port of the switch of the peer controller node, received data from the server to a port of a switch of the local controller node.07-04-2013
20080244150PROCESSOR CHIP ARCITECTURE HAVING INTEGRATED HIGH-SPEED PACKET SWITCHED SERIAL INTERFACE - A computing and communication chip architecture is provided wherein the interfaces of processor access to the memory chips are implemented as a high-speed packet switched serial interface as part of each chip. In one embodiment, the interface is accomplished through a gigabit Ethernet interface provided by protocol processor integrated as part of the chip. The protocol processor encapsulates the memory address and control information like Read, Write, number of successive bytes etc, as an Ethernet packet for communication among the processor and memory chips that are located on the same motherboard, or even on different circuit cards. In one embodiment, the communication over head of the Ethernet protocol is further reduced by using an enhanced Ethernet protocol with shortened data frames within a constrained neighborhood, and/or by utilizing a bit stream switch where direct connection paths can be established between elements that comprise the computing or communication architecture.10-02-2008
20080222341Method And Apparatus For Automatically Switching Between USB Host And Device - An apparatus and method for automatically switching between USB host and device is provided. In a device with a USB interface, the present invention automatically switches between a USB host and USB device by detecting the handshake protocol of the D+ and D− pins of the USB interface. The apparatus for automatically switching between USB host and device includes ah host mode element, a device mode element, a random auto-switcher, and a detection element. The random auto-switcher switches the connection to the host mode element or the device mode element at random time. The detection element monitors the handshake protocol of the D+ and D− pins of USB interface and the external USB-interface device to determine whether the host mode or the device mode is in use. When the present invention detects the external USB-interfaced device is a host, the present invention switches to become a USB device. Similarly, when the present invention detects the external USB-interfaced device is a USB device, the present invention switches to become a USB host.09-11-2008
20090006711Device, System and Method of Utilizing PCI Express Packets Having Modified Headers - Device, system, and method of utilizing PCI Express packets having modified headers. For example, an apparatus includes a credit-based flow control interconnect device to generate a credit-based flow control interconnect Transaction Layer Packet in which one or more bits of an ID field carry non-ID data.01-01-2009
20080215791Audio Signal Processing Device - In a digital mixer, a standard mode or a switched mode of an input patch is selectable. When shifting from the standard mode to the switched mode is selected, input port information in input patch data stored in a current memory is converted according to a port correspondence relation indicated by conversion data. When shifting from the switched mode to the standard mode is selected, the input port information in the input patch data stored in the current memory is reversely converted to original information according to the port correspondence relation indicated by the conversion data.09-04-2008
20130103881Multi-Processor Architecture Implementing A Serial Switch And Method Of Operating Same - A multi-processor architecture for a network device that includes a plurality of barrel cards, each including: a plurality of processors, a PCIe switch coupled to each of the plurality of processors, and packet processing logic coupled to the PCIe switch. The PCIe switch on each barrel card provides high speed flexible data paths for the transmission of incoming/outgoing packets to/from the processors on the barrel card. An external PCIe switch is commonly coupled to the PCIe switches on the barrel cards, as well as to a management processor, thereby providing high speed connections between processors on separate barrel cards, and between the management processor and the processors on the barrel cards.04-25-2013
20130103879LOAD CARD FOR TESTING PERIPHERAL COMPONENT INTERCONNECT SLOTS - A load card for testing different types of PCI slots is provided. The load card includes several gold fingers, and resistor selection circuits. Each gold finger corresponds to one PCI slot. Each resistor selection circuit includes a resistor to test at least one PCI slot working in one working voltage. When a PCI slot working at a working voltage is to be tested, the gold finger connects to the PCI slot, and the resistor selection circuit including the resistor to test the PCI slot working at the working voltage is enabled and others are disabled in response to an operation of the user.04-25-2013
20130103880METHODS AND SYSTEMS FOR HANDLING INTER-PROCESS AND INTER-MODULE COMMUNICATIONS IN SERVERS AND SERVER CLUSTERS - Pluggable modules communicate via a switch fabric dataplane accessible via a backplane. Various embodiments are comprised of varying numbers and arrangements of the pluggable modules in accordance with a system architecture that provides for provisioning virtual servers and clusters of servers from underlying hardware and software resources. The system architecture is a unifying solution for applications requiring a combination of computation and networking performance. Resources may be pooled, scaled, and reclaimed dynamically for new purposes as requirements change, using dynamic reconfiguration of virtual computing and communication hardware and software.04-25-2013
20130103878UNIVERSAL USB CHARGER - A universal USB charger connected to an electronic device stored with a set of preset voltage values has a power supply circuit, a USB interface having a V04-25-2013
20130124775COMPUTER SYSTEM AND BUS ASSIGNMENT METHOD - To make it possible to take over an IO configuration that is assigned to logical partitions in reallocation of the logical partitions, and to make an IO access work normally. A computer system has a server having an IO bridge, a switch that has a first IO bridge for connecting with the IO bridge of the server through a bus and plural second IO bridges for connecting to plural IO devices through a bus, and bus number assignment management means for fixedly assigning mutually different PCI bus numbers to the plural second IO bridges.05-16-2013
20130124774METHOD AND SYSTEM TO ENABLE PRE-BOOT EXECUTABLE ENVIRONMENT OPERATING SYSTEM INSTALL USING SWITCH IN SCALABLE DIRECT ATTACHED STORAGE ENVIRONMENT - Disclosed is a system for installing operating system files on logical unit numbers (LUNs). At a SAS switch, a command to initiate an operating system installation on a LUN)associated with a SAS host bus adapter (HBA) connected to said SAS switch is received. In response to the command, a PXE session with a PXE server is established. Using the PXE session, operating system files are transferred to the LUN via the SAS switch thereby installing the operating system on said LUN.05-16-2013
20130145072High availability and I/O aggregation for server environments - Methods and apparatus are provided for virtualizing port adapter resources such as network interface cards (NICs) used to connect servers to packet based networks. Resources are offloaded from individual servers onto a resource virtualization switch. Servers connected to the resource virtualization switch using an I/O bus connection share access to NICs. Redundancy can be provided using multipathing mechanisms implemented at individual servers or high availability mechanisms implemented at the resource virtualization switch. Switchover can occur between ports on the same port adapter, between ports on separate adapters, or between ports on separate resource virtualization switches.06-06-2013
20110219164I/O SYSTEM AND I/O CONTROL METHOD - Virtual Functions (VFs) 09-08-2011
20080201516Input device, electronic device having input device, and input method thereof - An input devices includes a switch unit for selecting one of a plurality of application modes, the switch unit outputting a first signal in response to a selection made by a user with respect to the application mode; at least one hotkey, each hotkey outputting a second signal in response to an activation of hotkey by the user; and a control unit for outputting a third signal in response to the first signal and the second signal to enable execution of the actuated hotkey under the selected application mode.08-21-2008
20120260018KVM SWITCHER WITH ABILITY TO EXTEND UNIVERSAL SERIAL BUS (USB) HOST INTERFACE VIA SERIAL PERIPHERIAL INTERFACE (SPI) - A multi-computer (KVM) switcher with ability to extend universal serial bus (USB) host interface via serial peripheral interface (SPI), characterized in that SPI master device interface of master control unit can switch the capability of controlling plural SPI slave devices via serial peripheral interface (SPI), and through installing SPI slave device interfaces on plural universal serial bus (USB) host interface control units to be extended, the object of extending peripheral device with USB interface via SPI interface is achieved.10-11-2012
20100312942Redundant and Fault Tolerant control of an I/O Enclosure by Multiple Hosts - An apparatus, system, and method are disclosed for reliably controlling an I/O enclosure. A bus module receives two or more Peripheral Component Interconnect Express (“PCIe”) sideband signals via one or more PCIe cables. The one or more PCIe cables are connected between one or more hosts and an I/O enclosure. A decode module determines an asserted value of each of the two or more PCIe sideband signals and combines the PCIe sideband signal asserted values to form a bus value. Each PCIe sideband signal represents a bit in the bus value, and the bus value specifies a command for controlling the I/O enclosure. An execution module executes the specified command to perform control actions on the I/O enclosure.12-09-2010
20100318717STATUS INFORMATION SAVING AMONG MULTIPLE COMPUTERS - Provided are techniques for status information saving among multiple computers. In one embodiment, a selected computer is operated using a plurality of input/output devices over switched input/output signal paths passing through a KVM (keyboard video mouse) switch positioned between the selected computer and the plurality of input/output devices. Status data is carried over signal paths passing through the KVM switch wherein the status data represents status information for a plurality of computers connected to the KVM switch. The status data passing through the KVM switch is stored in a memory coupled to the KVM switch. Other embodiments are described and claimed. Other embodiments are contemplated, depending upon the particular application.12-16-2010
20120284449KVM SWITCH WITH EMBEDDED BLUETOOTH MODULE - A switch device that allows a user to use the same non-Bluetooth user console (e.g., keyboard, mouse) to control both non-Bluetooth computers and Bluetooth master machines such as tablet computers, smart phones, etc. The switch device includes a console port for connecting to the console and one or more computer ports for connecting to one or more computers, as well as a Bluetooth module for communicating with Bluetooth master machines. A controller processes input device data received via the console port, and either sends the data to a selected Bluetooth master machine or a selected computer, or perform other functions such as switching, Bluetooth device pairing and disconnecting based on the input device data. The controller stores link information of the Bluetooth master machines already paired with the computer switch for quickly switching to a Bluetooth master machine. The switch device can be with or without video switching.11-08-2012
20130159593APPARATUS, SYSTEM, AND METHOD FOR ANALYZING AND MANAGING DATA FLOW OF INTERFACE APAPRATUSES - An apparatus, a system, and a method for analyzing and managing data flow of interface apparatuses are provided. The system includes a host and the interface apparatuses. In the host, a first controller provides data of a first channel and a second channel through a first interface port. Each interface apparatus has a second interface port, a second controller, a switch, and a third interface port. The second interface port serially connected to the first interface port receives data of the two channels and divides the same to be transmitted on a first transmission path and a second transmission path. The second controller processes data transmitted on the first transmission path. The switch switches data transmitted on the two transmission paths according to a control signal issued by the first controller. The third interface port is connected to the switch for outputting the switched data of the two channels.06-20-2013
20110314201METHOD AND DEVICE FOR IDENTIFYING UNIVERSAL SERIAL BUS (USB) INSERTION OR CHARGER INSERTION OF MOBILE TERMINAL - The present invention discloses a method to identify whether a USB or a charger is plugged into a mobile terminal and an identification device thereof. The identification device comprises a USB interface module connected with an external power supply device, an interface detection and control module, an electronic switch module, a charging switch module, an identification module and a baseband USB data transceiving module. With the method to identify whether a USB or a charger is plugged into a mobile terminal and an identification device thereof provided by the present invention, when an external power supply is plugged in, the identification device makes the terminal to preferentially enter a USB mode, while, according to the ultimately detected D−signal state, interrupt responses can be flexibly generated to accurately determine the presence of a USB or a charger. It can quickly and accurately identify the type of USB or charger plugged into the terminal. The technology plays a particular important role for a 3G mobile phone terminal.12-22-2011
20110314200BALANCED ON-DIE TERMINATION - Termination of a high-speed signaling link is effected by simultaneously engaging on-die termination structures within multiple integrated-circuit memory devices disposed on the same memory module, and/or within the same integrated-circuit package, and coupled to the high-speed signaling link.12-22-2011
20130205061SYSTEM AND METHOD FOR USING A MULTIPATH - In a path determination unit of a SAS expander connected to a SAS initiator and connected via first and second paths to a SAS target, an SSP controller receives an SSP command frame received from the SAS initiator; a requested-data-length manager stores a requested data length of the SSP command frame in a requested-data-length storage unit; and a data-transfer-amount manager selects one of the first and second paths having a smaller one of the data transfer amounts stored in a data-transfer-amount storage unit, and adds the requested data length to the data transfer amount of the selected path. The SSP command frame is transmitted to the SAS target via the selected path. Upon receipt of an SSP response frame responding thereto, the requested data length is deleted from the requested-data-length storage unit, and the requested data length is subtracted from the data transfer amount of the selected path.08-08-2013
20120096212USE OF COMPLETER KNOWLEDGE OF MEMORY REGION ORDERING REQUIREMENTS TO MODIFY TRANSACTION ATTRIBUTES - A method and system of relaxing the ordering of a read completion by setting an ordering attribute in the read completion. The relaxed ordering allows the read completion to bypass pending writes.04-19-2012

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