| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 710314000 | Common protocol (e.g., PCI to PCI) | 28 |
| 20130086296 | Providing Multiple Decode Options For A System-On-Chip (SoC) Fabric - In one embodiment, a system-on-chip (SoC) can be configured to receive a request from a master agent in a fabric coupled to the master agent, send a show command grant to the master agent responsive to selection of the request by the fabric, receive a command portion of a transaction corresponding to the request in the fabric and determine a target agent to receive the transaction based on the command portion, and thereafter send a transaction grant to the master agent for the transaction. Other embodiments are described and claimed. | 04-04-2013 |
| 20100106883 | Adaptable resource spoofing for an extended computer system - A spoofing module that mimics remote computer resources to optimize system responsiveness and avoid expiration of intentional and unintentional timeouts in extended computer systems. The invention is capable of appearing to the host system and selectively responding to the host system as if it were the actual hardware. The invention includes a throttling mechanism to prevent data over-run. | 04-29-2010 |
| 20100106882 | System data transfer optimization of extended computer systems - A solution for setup and optimization of a data transfer path in extended computer systems, where the I/O system is virtualized. The solution achieves advantageous results via a mechanism that automates the configuration of multiple data path components. The solution achieves initial optimization and then automates continual optimization of the data path through monitoring of changes and through dynamic adjustment of system resources and data transfer characteristics. | 04-29-2010 |
| 20090043941 | System and method for allowing coexistence of multiple PCI managers in a PCI express system - A system and method that allows a plurality of SR-PCIMs to operate within a PCIe fabric. The system and method describe a master SR-PCIM election process and transfer of mastership from a master SR-PCIM to a standby SR-PCIM under certain conditions. The system and method leverage the PCI configuration space and PCI messages so that SR-PCIMs from multiple vendors can potentially interoperate. | 02-12-2009 |
| 20130124773 | METHOD AND APPARATUS FOR PCI SIGNALING DESIGN - Apparatus and method for wireless communication in a wireless communication network includes mapping a PCI command to different symbols across a plurality of slots, allocating the PCI command to the plurality of slots, and transmitting the PCI command across the plurality of slots on an Fractional Transmit Precoding Information Channel (F-TPICH) from a network device to a user equipment (UE). | 05-16-2013 |
| 20100169533 | MULTI-PORT SYSTEM AND METHOD FOR ROUTING A DATA ELEMENT WITHIN AN INTERCONNECTION FABRIC - The present invention relates generally to a generic fabric interconnect system and method for providing a data path between and among nodes and processing elements within an interconnection fabric. More specifically, there is provided a device accessible by a host processor for expanding access over a first bus to a second bus, the first bus and the second bus each being adapted to separately connect to respective ones of a plurality of bus-compatible devices, each device which comprise a link, a first circuit adapted to couple between the first bus and the link, and a second circuit adapted to couple between the link and the second bus, the first circuit and the second circuit each being operated as a bridge and being operable to (a) send outgoing information serially through said link in a form different from that of the first bus and the second bus (b) approve an initial exchange between the first bus and the second bus in response to pending bus transactions having a characteristic signifying a destination across a device, and (c) allow the host processor, communicating through the first bus, to individually address different selectable ones of the bus-compatible devices on the second bus: (i) using on the first bus substantially the same type of addressing as is used to access devices on the first bus, and (ii) without first employing a second, intervening one of the bus-compatible devices on the second bus. | 07-01-2010 |
| 20080209099 | APPARATUS AND METHODS FOR CLUSTERING MULTIPLE INDEPENDENT PCI EXPRESS HIERARCHIES - Apparatus, systems and methods for clustering multiple PCI Express hierarchies to enable access of components in different hierarchies. Each PCI Express hierarchy includes a root device as well as a cluster port for coupling each hierarchy to each other hierarchy of a physical cluster through a PCI Express switched fabric. Memory addresses and transaction IDs are re-mapped by the cluster port of each hierarchy to partition the PCI Express space of the system of multiple hierarchies. A first portion of the partitioned space is reserved for access to local components within a hierarchy. A second portion of the space is used to access remote components of other hierarchies from within a different first hierarchy. The address and transaction ID values exchanged in such remote transactions are re-mapped and used by the cluster port of each hierarchy to route exchanges between hierarchies using standard PCIe root devices, endpoint devices, and switches. | 08-28-2008 |
| 20120198120 | EXPANDED PROTOCOL ADAPTER FOR IN-VEHICLE NETWORKS - A protocol adapter for transferring diagnostic signals between a vehicle network and a computer including a vehicle connector, a common connector plate, and a common electronics package. The vehicle connector is interfaced with the vehicle network. The common connector plate is interfaced with the vehicle connector. The common electronics package is interfaced with the common connector plate, and wirelessly transmits the diagnostic signals from the vehicle network to the computer. | 08-02-2012 |
| 20110225341 | COMMUNICATION APPARATUS, COMMUNICATION SYSTEM AND ADAPTER - A communication apparatus for carrying out communications to and from an external apparatus that includes a first interconnecting unit and a first non-transparent port and effects an interconnection for communications via the first non-transparent port is provided. The communication apparatus includes a second interconnecting unit that includes a second non-transparent port communicably connected to the first non-transparent port. The second interconnecting unit effects an interconnection for communications via the second non-transparent port. The second interconnecting unit performs, when the communication apparatus carries out communications to and from the external apparatus, address translation between an address for use by the communication apparatus and an address for use by the second non-transparent port. | 09-15-2011 |
| 20110145469 | APPARATUS FOR PROCESSING PERIPHERAL COMPONENT INTERCONNECT EXPRESS PROTOCOL - An apparatus for processing a PCI Express protocol, includes: a PCI Express transaction layer reception unit for transmitting status information, and performing a data writing operation; a PCI Express data link layer transmission unit for creating a flow control packet, transmitting the flow control packet to a PCI Express physical layer, and transmitting an integrity acknowledgement packet to the PCI Express physical layer; and a PCI Express physical layer for transmitting the flow control packet and the integrity acknowledgement packet to an upstream device, and transmitting the writing request packet to a PCI Express data link layer reception unit. Further, the apparatus includes a PCI Express data link layer reception unit for transmitting the writing request packet to the PCI Express transaction layer reception unit, and transmitting the integrity acknowledgement packet to the PCI Express data link layer transmission unit and a PCI Express transaction layer reception unit. | 06-16-2011 |
| 20110145470 | DATA INPUT/OUTPUT DEVICE FOR ADJUSTING CHARACTERISTIC OF INTERFACE - To adjusts protocol and analog characteristics of an interface automatically, there is provided a data input/output device coupled to a host computer for inputting and outputting data to and from the host computer, including: an interface coupled to an interface of the host computer; and a controller for controlling the interface of the data input/output device, wherein the controller is configured to: measure an analog characteristic of the interface of the host computer and a protocol characteristic of the interface of the host computer when the data input/output device is reset; and adjust an analog characteristic of the interface of the data input/output device to an optimum value based on a result of the measurement, and then adjust a protocol characteristic of the interface of the data input/output device to an optimum value. | 06-16-2011 |
| 20080263255 | Apparatus, System, and Method For Adapter Card Failover - An apparatus, system, and method are disclosed for adapter card failover. A switch module connects a first processor complex to an adapter card through a first port as an owner processor complex. The owner processor complex manages the adapter card except for a second port and receives error messages from the adapter card. The switch module further connects a second processor complex to the adapter card through the second port as a non-owner processor complex. The non-owner processor complex manages the second port. A detection module detects a failure of the first processor complex. A setup module modifies the switch module to logically connect the second processor complex to the adapter card as the owner processor complex and to logically disconnect the first processor complex from the adapter card in response to detecting the failure. | 10-23-2008 |
| 20090006708 | PROPORTIONAL CONTROL OF PCI EXPRESS PLATFORMS - A system may comprise M data lanes where M is an integer greater than 1, a plurality of PCIe devices, and a PCIe lane controller. Each device may be coupled to corresponding ones of a plurality of PCIe endpoints. The PCIe lane controller may automatically distribute N data lanes to a first of the plurality of PCIe endpoints, and may distribute M minus N data lanes to a remaining plurality of endpoints, where N is an integer. | 01-01-2009 |
| 20090077297 | Method and system for dynamically reconfiguring PCIe-cardbus controllers - A method for configuring a computer system. The method includes allocating a first plurality of default resources to a plurality of devices of the computer system. Then a PCIe-CardBus controller in the computer system is reconfigured with a plurality of allocable resources that are available to the PCIe-CardBus controller. The method further comprises enumerating the plurality of devices of the computer system by an Operating System (OS) of the computer system for detecting a plurality of un-configured devices in the computer system. According to the enumeration, the OS allocates a second plurality of default resources to the plurality of un-configured devices. | 03-19-2009 |
| 20100211715 | Method for transmitting data between two computer systems - A method for transmitting data between two storage virtualization controllers (SVCs) is disclosed in the present invention. The two SVCs comprising a first SVC and a second SVC, in which the first SVC comprises a first bus interface and a first memory, the second SVC comprises a second bus interface and a second memory, and an inter-controller communication channel (ICC) is established between the first bus interface and the second bus interface, the method comprising the steps of: transmitting, by the second SVC, a message via the ICC through the second bus interface to the first SVC, in which the message comprises a destination address of a block of the second memory, and the block is accessible; reading, by the first SVC, data in the first memory to be transmitted when the first SVC receives the message; transmitting, by the first SVC, the data to be transmitted and the destination address to the second SVC via the ICC through the first bus interface; and storing, by the second SVC, the transmitted data into the second memory according the destination address. | 08-19-2010 |
| 20100161870 | Virtualized PCI endpoint for extended systems - Virtualization of a PCI Endpoint via the Internet and LANs. The invention is a solution that allows the use of low-complexity, low-cost PCI Express Endpoint Type 0 cores or custom logic for relatively simple virtualization applications. The invention combines two physically separate assemblies in such a way that they appear to the host system as one local multifunctional PCI Express Endpoint device. | 06-24-2010 |
| 20100180062 | INTERNET CONNECTION SWITCH AND INTERNET CONNECTION SYSTEM | 07-15-2010 |
| 20110060859 | Host-to-host software-based virtual system - A means for extending the Input/Output System of a host computer via software-centric virtualization. Physical hardware I/O resources are virtualized via a software-centric solution utilizing two or more host systems. The invention advantageously eliminates the host bus adapter, remote bus adapter, and expansion chassis and replaces them with a software construct that virtualizes selectable hardware resources located on a geographically remote second host making them available to the first host. One aspect of the invention utilizes | 03-10-2011 |
| 20120066429 | Peripheral Device, Program and Methods for Responding to a Warm Reboot Condition - A computing system peripheral device compatible with the peripheral component interconnect express (PCI-E) protocol responds to a DL_DOWN command primitive by configuring a general-purpose input/output (GPIO) port into a known state without invoking a GPIO module reset. In addition, select resources are excluded from resources on the peripheral device that are issued a reset command. The select resources can include a GPIO module, a memory element and a PCI-E SERDES module. After the remaining reset resources have completed their individual initialization processes, the central processor core on the peripheral device is reset. The described response to the DL_DOWN command primitive avoids cache data loss, masks signal transitions on I/O ports and timing problems that prevent some peripheral devices from being recognized in a computer's basic input/output system (BIOS). | 03-15-2012 |
| 20100318716 | ORDERED QUEUE AND METHODS THEREFOR - A device receives a first request from a requesting device for first information that is stored at contiguous address locations beginning at a first address. A plurality of spawned requests are generated that each request a different portion of the first information. A table location is allocated to each one of the plurality of requests, wherein the relative location of each allocated table location is indicative of an order that the information from each spawned request is to be returned to the requesting device relative to the information from each other spawned request. | 12-16-2010 |
| 20120047309 | Method, apparatus, and system for manageability and secure routing and endpoint access - A solution is presented to securing endpoints without the need for a separate bus or communication path. The solution allows for controlling access to endpoints by utilizing a management protocol by overlapping with existing interconnect communication paths in a packet format and utilizing a PCI address BDF (Bus number, Device number, and Function number) for verification. | 02-23-2012 |
| 20120017026 | System and Method for Increased Efficiency PCI Express Transaction - A system and method using new PCI Express transaction layer packet headers so that unchanged header information within a burst of transactions does not need to be re-transmitted. After the first full packet header of a burst is sent, subsequent packet headers in the burst are smaller. Thus, more reduced headers can be transmitted over time with a resulting increased efficiency. Both sides of the PCI Express transaction must support this system and method for this approach to be enabled. Once enabled, both the PCI Express transmitter and receiver can use the regular full header PCI Express packets as well as the reduced header packets. | 01-19-2012 |
| 20120221764 | LOW LATENCY PRECEDENCE ORDERING IN A PCI EXPRESS MULTIPLE ROOT I/O VIRTUALIZATION ENVIRONMENT - An apparatus and method of low latency precedence ordering check in a PCI Express (PCIe) multiple root I/O virtualization (MR-IOV) environment. The precedence ordering check mechanism aids in enabling a port to comply with PCIe MR-IOV ordering rules. A posted information array mirrors a posted transaction queue, storing precedence order indicator and Virtual Hierarchy (VH) tag information for corresponding posted transaction entries stored in the posted transaction queue. The selector queries the posted information array periodically, such as each cycle, to determine whether the non-posted/completion transaction at the output of their respective queues have any preceding posted transactions of the same VH somewhere in the posted queue. | 08-30-2012 |
| 20100011146 | Conveying Information With a PCI Express Tag Field - A method for determining when all data has been sent for a given PCI Express bus command issued by a backend entity of a PCI Express bus device, by setting a PCI Express bus packet header tag field of a PCI Express bus packet to indicate a backend entity that originated the PCI Express bus command and whether the PCI Express bus packet is a last packet of the PCI Express bus command, and then inspecting the PCI Express bus packet header tag field of the PCI Express bus packet to determine whether the PCI Express bus packet is the last packet of the PCI Express bus command. | 01-14-2010 |
| 20080313382 | Method and Device for Mapping Signal Order at Multi-Line Bus Interfaces - The present invention provides methods and modules allowing for mapping of interface signals at for instance multi-line buses. A mapping of internal signal order schemes to external signal order schemes is enabled such that upon configuration any interface signals may carried on any lines of a multi-line bus. The configurability may obtained by the implementation of mapping logics and mapping algorithms, which associates external interface terminal to signal association to internal interface terminal to signal association in a configurable manner. | 12-18-2008 |
| 20110047313 | Memory area network for extended computer systems - A solution enabling the practical use of very large amounts of memory, external to a host computer system. With physical locality and confinement removed as an impediment, large quantities of memory, here before impractical to physically implement, now become practical. Memory chips and circuit cards no longer must be installed directly in a host system. Instead, the memory resources may be distributed or located centrally on a network, asconvenient, in much the same manner that mass storage is presently implemented. | 02-24-2011 |
| 20120096211 | PERFORMANCE AND POWER OPTIMIZED COMPUTER SYSTEM ARCHITECTURES AND METHODS LEVERAGING POWER OPTIMIZED TREE FABRIC INTERCONNECT - A performance and power optimized computer system architecture and method leveraging power optimized tree fabric interconnect are disclosed. One embodiment builds low power server clusters leveraging the fabric with tiled building blocks while another embodiment implements storage solutions or cooling solutions. Yet another embodiment uses the fabric to switch non-Ethernet packets, switch multiple protocols for network processors and other devices. | 04-19-2012 |
| 20110320674 | UPBOUND INPUT/OUTPUT EXPANSION REQUEST AND RESPONSE PROCESSING IN A PCIE ARCHITECTURE - A system for implementing non-standard I/O adapters in a standardized input/output (I/O) architecture, the system comprising an I/O adapter communicatively coupled to an I/O hub via an I/O bus, the I/O adapter communicating in a first protocol, the I/O bus communicating in a second protocol different than the first protocol, and the I/O adapter including logic for implementing a method comprising initiating a first request to perform an operation on a host system, the first request formatted for the first protocol and comprising data required to process the first request, and creating a second request responsive to the first request, the second request comprising a header and formatted according to the second protocol, the creating comprising storing the data required to process the first request in the header of the second request. The method further comprising sending the second request to the host system. | 12-29-2011 |
