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Direct memory access (e.g., DMA)

Subclass of:

710 - Electrical computers and digital data processing systems: input/output

710100000 - INTRASYSTEM CONNECTION (E.G., BUS AND BUS TRANSACTION PROCESSING)

710305000 - Bus interface architecture

710306000 - Bus bridge

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DocumentTitleDate
20110202701UNIFIED SYSTEM AREA NETWORK AND SWITCH - A network switch, based on the PCI Express protocol, is disclosed. The switch includes a processor, local memory and a plurality of non-transparent bridges. By configuring the non-transparent bridges appropriately, the network switch can facilitate a number of different communication mechanisms, including TCP/IP communication between servers, server clusters, and virtualized I/O device utilization. For example, the network switch may configure the non-transparent bridges so as to have access to the physical memory of every server attached to it. It can then move data from the memory of any server to the memory of any other server. In another embodiment, the network switch is connected to an I/O device, and multiple servers are given access to that I/O device via virtualized connections.08-18-2011
20130042043Method and Apparatus for Dynamic Channel Access and Loading in Multichannel DMA - An arbiter detects waiting states of N buffers holding direct memory access (DMA) requests, and detects an availability of R core channels of a core R-channel DMA memory. The arbiter, based on the detection, dynamically grants up to R of the N buffers access to the R core channels. An N-to-R controller communicates DMA requests from the N buffers to currently granted ones of the R core channels, and maintains a location record of different data from each of the N buffers being written into different ones of the R core channels.02-14-2013
20100106880MANAGING MISALIGNED DMA ADDRESSES - A system and method operable to manage misaligned direct memory access (DMA) data transfers is provided. This method involves determining a delta between N bytes of data to be copied from within a local side buffer (source location) to a remote buffer (destination location). After the delta is determined a tail of the same length is copied to temporary storage. Then the N bytes of data on the local side buffer minus the tail will be shifted to align the N bytes of data to be copied from within the local side buffer to the starting address of the destination location in the remote buffer. The pre-shifted N bytes of data within the local side buffer may be DMA transferred to the remote buffer. The tail transferred to temporary storage may then be copied from temporary storage to the remote buffer04-29-2010
20130073772SOLID-STATE DISK, AND USER SYSTEM COMPRISING SAME - The inventive concept relates to a user system including a solid state disk. The user system may include a main memory for storing data processed by a central processing unit; and a solid state disk for storing the selected data among data stored in the main memory. The main memory and the solid state disk form a single memory hierarchy. Thus, the user system of the inventive concept can rapidly process data.03-21-2013
20090271555ACCESSING DATA - A method of accessing data in a device comprising: a first integrated circuit having a processor, a memory connected to the processor and a direct memory access engine operatively coupled to the memory and to the microprocessor; a second integrated circuit comprising storage means for holding data values in respective locations, the second integrated circuit being connected to the first integrated circuit via a serial link, the method comprising: the processor generating a plurality of memory access requests independent from one another and supplying a bundle of said independent memory access requests to the direct memory access engine, each memory access request comprising an address of a storage location in the storage means; the direct memory access engine sequentially supplying the memory access requests via the serial link to the second integrated circuit; the second integrated circuit returning a data value responsive to each memory access request and appending to the data value said address of the location where the data value was stored in the storage means; and storing in the memory of the first integrated circuit the returned data value and its appended address.10-29-2009
20110022767DMA CONTROLLER WITH INTERRUPT CONTROL PROCESSOR - Provided is a direct memory access (DMA) controller having an interrupt control processor that can process DMA transmission-related interrupts according to a control program modifiable by a user. The DMA controller includes the interrupt control processor that can process a DMA transmission-related interrupt and a DMA request interrupt transmitted from peripheral devices and control the DMA channel through the control program that can be modified by the user, so that DMA channel control and relevant interrupt processing loads caused by a plurality of DMA data transmissions are reduced, and the flexibility of DMA channel control and interrupt processing in control of the DMA controller is provided to the user.01-27-2011
20120233372DATA TRANSFER CONTROL DEVICE, INTEGRATED CIRCUIT OF SAME, DATA TRANSFER CONTROL METHOD OF SAME, DATA TRANSFER COMPLETION NOTIFICATION DEVICE, INTEGRATED CIRCUIT OF SAME, DATA TRANSFER COMPLETION NOTIFICATION METHOD OF SAME, AND DATA TRANSFER CONTROL SYSTEM - A data transfer control device 09-13-2012
20130166810APPARATUS FOR PROCESSING REGISTER WINDOW OVERFLOW AND UNDERFLOW - An apparatus for processing a register window overflow and underflow includes register windows each configured to include local registers and incoming registers, dedicated internal memories configured to store contents of the local registers and the incoming registers for each word, dedicated data buses configured to connect the local registers and the incoming registers and the respective dedicated internal memories, a memory word counter configured to perform counting in order to determine whether or not there is a storage space of a word unit in the dedicated internal memories, and a logic block configured to control an operation of the dedicated data buses when one of a window overflow and a window underflow is generated based on the count value of the memory word counter.06-27-2013
20110283036Multi-Pass System and Method Supporting Multiple Streams of Video - Systems and methods are disclosed for performing multiple processing of data in a network. In one embodiment, the network comprises a first display pipeline that is formed in real time from a plurality of possible display pipelines and that performs at least a first processing step on received data. A buffer stores the processed data and a second display pipeline that is formed in real time from a plurality of possible display pipelines performs at least a second processing step on stored data.11-17-2011
20120290763Method and system of complete mutual access of multiple-processors - The present disclosure discloses a method of complete mutual access of multiple-processors. The method comprises: a separate boot memory and a separate address mapping module are allocated for each processor; the processors perform the mutual access in the multiple-processors through the address mapping module after the processors are booted. The present disclosure also discloses a system for enabling complete mutual access of the multiple-processors. The method and the system creates the advantage of allowing complete mutual access of the multiple-processors, thereby sharing address space in the multiple-processors, sharing the peripheral controller and memory, improving expansibility and performance of the system.11-15-2012
20120110232MULTI-DESTINATION DIRECT MEMORY ACCESS TRANSFER - An apparatus generally including an internal memory and a direct memory access controller is disclosed. The direct memory access controller may be configured to (i) read first information from an external memory across an external bus, (ii) generate second information by processing the first information, (iii) write the first information across an internal bus to a first location in the internal memory during a direct memory access transfer and (iv) write the second information across the internal bus to a second location in the internal memory during the direct memory access transfer. The second location may be different from the first location.05-03-2012
20100169532SYSTEM LSI HAVING PLURAL BUSES - A system LSI includes first and second memories, first and second buses, a bus bridge that performs signal transfer between the first and second buses, a first bus system connecting to the first bus and accessing the first or second memory, a second bus system connecting to the second bus and accessing the first or second memory, a memory access circuit having first and second bus-side input/output terminals that perform signal transfer to/from the first and second buses and first and second memory-side input/output terminals that perform signal transfer to/from the first and second memories.07-01-2010
20100115170CHIP COMBINED WITH PROCESSOR CORES AND DATA PROCESSING METHOD THEREOF - A chip having integrated multiple processor cores and a data processing method are disclosed. The processor chip includes an MP core (main processor core), an AP core (application processor core) which performs a processing function designated by a control of the MP core, a first SM controller which sets a path such that the MP core is coupled with a shared memory, and a second SM controller which sets a path such that the AP core is coupled with the shared memory. By virtue of the present invention, the number of chips installed can be minimized, to allow efficient utilization of PCB space and enable a compact size for a portable terminal.05-06-2010
20080215789Data transfer control device and electronic instrument - A data transfer control device includes a PATA I/F connected to a PATA bus, a SATA I/F connected to a SATA bus, and a sequence controller that controls a transfer sequence. The PATA I/F includes a task file register that is a pseudo register provided to implement a PATA/SATA bus bridge, and the SATA I/F includes a shadow task file register, a register value being transferred between the shadow task file register and the task file register.09-04-2008
20120036302DETERMINATION OF ONE OR MORE PARTITIONABLE ENDPOINTS AFFECTED BY AN I/O MESSAGE - A data processing system includes a processor core, a system memory including a first data structure including a plurality of entries mapping requester identifiers (IDs) to partitionable endpoint (PE) numbers, and an input/output (I/O) subsystem including a plurality of PEs each having an associated PE number, where each of the plurality of PEs including one or more requesters each having a respective requester ID. An I/O host bridge, responsive to receiving an I/O message including a requester ID and an address, determines a PE number by reference to a first entry from the first data structure, and responsive to determining the PE number, accesses a second entry of the second data structure utilizing the PE number as an index and validates the address by reference to the accessed entry in the second data structure. The I/O host bridge, responsive to successful validation, provides a service indicated by the I/O message.02-09-2012
20080270668Method to Hide or Reduce Access Latency of a Slow Peripheral in a Pipelined Direct Memory Access System - A bus bridge between a high speed DMA bus and a lower speed peripheral bus sets a threshold for minimum available buffer space to send a read request dependent upon a frequency ratio and the DMA read latency. Similarly, a threshold for minimum available data for a write request depends on the frequency ratio and the DMA write latency. The bus bridge can store programmable values for the DMA read latency and write latency.10-30-2008
20090300256SELF-SYNCHRONIZING DATA STREAMING BETWEEN ADDRESS-BASED PRODUCER AND CONSUMER CIRCUITS - A circuit arrangement and method facilitate the direct streaming of data between producer and consumer circuits (12-03-2009
20090287871UNIVERSAL SERIAL BUS HOST CONTROLLER AND CONTROL METHODS THEREOF - The present invention provides a USB host controller and control method thereof. The USB host controller comprises a first controller, a second controller and a first memory. The first controller controls first transfer between a host and a USB device. The second controller controls second transfer between the host and the USB device. The first memory is coupled to the first controller and the second controller and is configured to temporarily store data transferred between the host and the USB device. The first controller accesses the first memory during the first transfer, and the second controller accesses the first memory during the second transfer.11-19-2009
20080215790Memory systems for automated computing machinery - Design structures embodied in machine readable medium are provided. Embodiments of the design structure include a memory system comprising: a memory controller; a memory bus terminator; a high speed memory bus that interconnects the memory controller, the memory bus terminator, and at least one memory module; and the at least one memory module, the memory module comprising at least one memory hub device, high speed random access memory served by the memory hub device, two bus signal ports, and a segment of the high speed memory bus fabricated on the memory module so as to interconnect the bus signal ports and the memory hub device, the high speed memory bus connected to the memory hub device by a negligible electrical stub.09-04-2008
20090138646METHOD AND APPARATUS FOR SIGNALING BETWEEN DEVICES OF A MEMORY SYSTEM - A method and apparatus for signaling between devices of a memory system is provided. In accordance with an embodiment of the invention, one or more of several capabilities are implemented to provide heretofore unattainable levels of important system metrics, for example, high performance and/or low cost. These capabilities relate to timing adjustment capabilities, bit time adjustment capabilities, cycle time selection, use of differential and/or non-differential signaling for bus signals and/or clock signals, use of termination structures on a bus, including integrated termination structures, and active control circuitry to allow adjustment to different characteristic bus impedances and power-state control, including a calibration process to optimize the termination value, use of slew rate control circuitry and transfer characteristic control circuitry in the predriver and driver of transmitter blocks to allow adjustment to different characteristic bus impedances and to allow adjustment for other bus properties, including a calibration process to optimize the such circuitry, and/or provision of a memory component designed to prefetch (preaccess) words that are wider than the width of the data bus so that the memory access bandwidth approximately matches the transfer bandwidth, and memory component able to adjust the size of the prefetch (preaccess) word to accommodate connection to data buses of different width.05-28-2009
20120198118USING DMA FOR COPYING PERFORMANCE COUNTER DATA TO MEMORY - A device for copying performance counter data includes hardware path that connects a direct memory access (DMA) unit to a plurality of hardware performance counters and a memory device. Software prepares an injection packet for the DMA unit to perform copying, while the software can perform other tasks. In one aspect, the software that prepares the injection packet runs on a processing core other than the core that gathers the hardware performance counter data.08-02-2012
20090070513Method and Apparatus for Distributed Direct Memory Access for Systems on Chip - A distributed direct memory access (DMA) method, apparatus, and system is provided within a system on chip (SOC). DMA controller units are distributed to various functional modules desiring direct memory access. The functional modules interface to a systems bus over which the direct memory access occurs. A global buffer memory, to which the direct memory access is desired, is coupled to the system bus. Bus arbitrators are utilized to arbitrate which functional modules have access to the system bus to perform the direct memory access. Once a functional module is selected by the bus arbitrator to have access to the system bus, it can establish a DMA routine with the global buffer memory.03-12-2009
20080263253APPARATUS AND METHOD FOR A TEST AND MEASUREMENT INSTRUMENT - The apparatus for a test and measurement instrument consists of multiple integrated circuits with each integrated circuit being connected to its own memory controller. At least one of the integrated circuits is a specialized integrated circuit, which may be a graphics processing unit, a digital signal processor, or a field-programmable gate array. Each memory controller is connected to its own memory. The integrated circuits are connected in a circular arrangement by multiple high-speed interconnects. A bridge is connected to at least the first and last integrated circuits. A system bus connects the bridge to an acquisition module. The acquisition module has a signal bus interface with the system bus being connected to the acquisition module and having its own acquisition hardware. The acquisition hardware is a direct memory access machine that can transfer data to any portion of the memory. There is a signal source connected to the signal bus interface.10-23-2008
20090222610BRIDGE, INFORMATION PROCESSING DEVICE , AND ACCESS CONTROL METHOD - A downstream port 09-03-2009
20090265500Information Processing Apparatus, Information Processing Method, and Computer Program - An information processing apparatus including a plurality of nodes, each node connecting at least a memory and a processor to a system bus; an interconnection bus that interconnects the nodes; a device that is connected to a system bus on any of the plurality of nodes and performs data processing; and a memory selecting unit that selects a memory connected to the system bus to which the device is connected as a memory to be accessed by the device.10-22-2009
20090259789MULTI-PROCESSOR, DIRECT MEMORY ACCESS CONTROLLER, AND SERIAL DATA TRANSMITTING/RECEIVING APPARATUS10-15-2009
20090248941Peer-To-Peer Special Purpose Processor Architecture and Method - A peer-to-peer special purpose processor architecture and method is described. Embodiments include a plurality of special purpose processors coupled to a central processing unit via a host bridge bus, a direct bus directly coupling each of the plurality of special purpose processors to at least one other of the plurality of special purpose processors and a memory controller coupled to the plurality of special purpose processors, wherein the at least one memory controller determines whether to transmit data via the host bus or the direct bus, and whether to receive data via the host bus or the direct bus.10-01-2009
20090276557BUS SYSTEM FOR USE WITH INFORMATION PROCESSING APPARATUS - A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on t11-05-2009
20100174843SYSTEM AND METHOD FOR OPERATING A BUS SYSTEM - A bus system for the real-time communication of a superordinate unit with one or more subordinate units is used for exchanging address and data information via a bus. For the rapid exchange of messages, further fields are provided between the fields for the address and data information.07-08-2010
20100153610BUS ARBITER AND BUS SYSTEM - A bus interface unit receives first and second data sent out to a data bus and observes address values indicated on an address bus. The first and second data are written into first and second registers respectively. First and second address detection unit receive the address values observed by the bus interface respectively. The first address detection unit outputs a first detection signal when it detects an address value which corresponds with the value of the first data. The second address detection unit outputs a second detection signal, when it detects an address value having an increment from the first data, which corresponds with the value of the second data. A control unit raises the priority of one of the bus masters given a bus utilization right, during the period from a start of outputting the first detection signal to an end of outputting the second detection signal.06-17-2010
20120036303APPARATUS AND METHODS FOR OPTICALLY-COUPLED MEMORY SYSTEMS - Optically-coupled memory systems are disclosed. In one embodiment, a system memory includes a carrier substrate, and a controller attached to the carrier substrate and operable to transmit and receive optical signals, and first and second memory modules. The module substrate of the first memory module has an aperture formed therein, the aperture being operable to provide an optical path for optical signals between the controller and an optical transmitter/receiver unit of the second memory module.02-09-2012
20100049896PEER-TO-PEER NETWORK COMMUNICATIONS USING SATA/SAS TECHNOLOGY - A conventional serial communications protocol that is limited to supporting only host-to-slave communications, such as SATA or SAS, is extended to support peer-to-peer communications, e.g., by adding a memory-map layer into the conventional protocol stack between the link layer and the protocol layer. The addition of the memory-map layer enables two (or more) non-host devices (i.e., peer devices) to communicate with one another without using a host computer and without relying on conventional protocol-bridging techniques.02-25-2010
20100049895Providing a Connection Between a Memory Medium of a Mobile Device and an External Device - System and method for providing a high speed connection to a memory medium of a mobile device. The mobile device may be a mobile phone or other type of portable electronic device. The memory medium may be removable and/or may be flash memory, as desired. The mobile device may include a USB hub that provides a direct high speed connection between an external device and a memory medium of the mobile device. The USB hub may also provide a connection (possibly high speed) between the external device and the processor of the mobile device. The mobile device may also include a high speed connection between the processor of the mobile device and the memory medium.02-25-2010
20090319714SYSTEM AND METHOD FOR TRANSMITTING DATA PACKETS IN A COMPUTER SYSTEM HAVING A MEMORY HUB ARCHITECTURE - A system and method for transmitting data packets from a memory hub to a memory controller is disclosed. The system includes an upstream reception port coupled to an upstream link. The upstream reception port receives the data packets from downstream memory hubs. The system further includes a bypass bus coupled to the upstream reception port. The bypass bus transports the data packets from the upstream reception port. The system further includes a temporary storage coupled to the upstream reception port and configured to receive the data packets from the upstream reception port. The system further includes a bypass multiplexer for selectively coupling an upstream transmission port to either one of a core logic circuit, the temporary storage, or the bypass bus. The system further includes a breakpoint logic circuit coupled to the bypass multiplexer and configured to switch the bypass multiplexer to selectively connect the upstream transmission port to either one of the core logic circuit, the bypass bus, or the temporary storage. The system further includes a local memory coupled to the core logic circuit and operable to receive and send the data packets to the core logic circuit.12-24-2009
20090138645SOC SYSTEM - Provided is a System on Chip (SoC) system for a multimedia system enabling high-speed transfer of a large amount of multimedia data and a processor to rapidly control a peripheral device. The SoC system includes a processor; a plurality of peripheral devices; a plurality of physically divided memories; a control bus for transferring a control signal from the processor to the peripheral devices and the memories; a data bus for transferring data between the processor, the peripheral devices and the memories; a bridge for coupling the control bus and the data bus to the processor; a plurality of memory controllers coupled to the control bus and controlling each of the memories; a Direct Memory Access (DMA) controller coupled to the data bus and the control bus and controlling data transfer between the peripheral devices and the memories; and a matrix switch coupled between the DMA controller and the memory controllers and enabling simultaneous multiple memory access.05-28-2009
20100223415REMOTE MEMORY ACCESS USING REVERSIBLE HOST/CLIENT INTERFACE - Accessing memory on a first device from a second device is supported by reversible host/client interfacing between the devices. The reversible interfacing permits the first and second devices to be configured respectively as host and client, or respectively as client and host.09-02-2010
20100306438BUS SYSTEM FOR USE WITH INFORMATION PROCESSING APPARATUS - A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.12-02-2010
20120036301PROCESSOR SUPPORT FOR FILLING MEMORY REGIONS - Techniques are disclosed relating to distributing workloads between processors and/or processing elements. A computer system having at least first and second processing elements may cause a request to initialize one or more memory regions to be handled by the second processing element. Initialization may be accomplished by the second processing element directly accessing a memory that includes the specified memory region to be initialized. Thus, while the second processing element is causing the memory region to be initialized, the first processing element is free to perform other computational tasks. A cache associated with the first processing element may be undisturbed as a result of the second processing element performing the initialization, which may avoid displacement of data from the cache.02-09-2012
20100312940DMA TRANSFER CONTROL DEVICE - A DMA transfer control device comprises: a DMA arbiter that performs DMA transfer for each DMA channel formed by a combination of a memory and a plurality of input/output devices and DMA controller circuits that control the DMA arbiter; a judgment unit and a transfer time calculation unit that calculates a next DMA transfer scheduled time based on the DMA transfer size for a DMA transfer request and a judgment time. A timer counter that times the judgment time at a unit time interval, and a comparator that compares the judgment time at which a DMA transfer request arrives with the DMA transfer scheduled time are also provided, and the judgment unit sends the DMA transfer permission to the DMA arbiter when an output of the comparator indicates that the judgment time is not earlier than the DMA transfer scheduled time. The efficiency of data transfer by dynamically controlling DMA transfer is performed.12-09-2010
20100281201PROTOCOL TRANSLATION IN A DATA STORAGE SYSTEM - A data storage system includes an input/output server and a storage unit. The input/output server includes a processor, memory, and a host channel adapter. The storage unit includes a processor, memory, and a storage module. The storage module includes a storage controller, and an interface block for connecting the storage module to a corresponding memory-mapped interface. The storage unit further includes a host channel adaptor. The storage unit host channel adapter is connected to a corresponding memory-mapped interface. The storage unit host channel adapter is capable of remote direct memory access to the input/output server. Protocol translation logic is configured to intercept a memory access request from the storage controller, and initiate a corresponding remote direct memory access to the input/output server through the storage unit host channel adapter and the input/output server host channel adapter.11-04-2010
20100325334HARDWARE ASSISTED INTER-PROCESSOR COMMUNICATION - An external memory based FIFO (xFIFO) apparatus coupled to an external memory and a register bus is disclosed. The xFIFO apparatus includes an xFIFO engine, a wDMA engine, an rDMA engine, a first virtual FIFO, and a second virtual FIFO. The xFIFO engine receives a FIFO command from the register bus and generates a writing DMA command and a reading DMA command. The wDMA engine receives the writing DMA command from the xFIFO engine and forwards an incoming data to the external memory. The rDMA engine receives the reading DMA command from the xFIFO engine and pre-fetches a FIFO data from the external memory. The wDMA engine and the rDMA engine synchronize with each other via the first virtual FIFO and the second virtual FIFO.12-23-2010
20110125949Routing packet from first virtual machine to second virtual machine of a computing device - A networking packet is to be sent from a first virtual machine of a computing device to a second virtual machine of the computing device. A hardware network interface controller (NIC) of the computing device is to determine whether the networking packet is to be routed from the first virtual machine to the second virtual machine in accordance with a first approach or a second approach, based upon one or more considerations regarding a state of the computing device. The hardware NIC is then to control routing of the networking packet in accordance with the first approach or the second approach.05-26-2011
20090216932DATA PROCESSING APPARATUS - A data processing apparatus includes: a system bus; a processor connected to the system bus in slave connection, the processor having a command register configured to retain a DMA request command corresponding to a resource on the system bus and be accessed through the system bus; and a DMA controller connected to the system bus in bus-mastering connection, the DMA controller being configured to read out the DMA request command retained in the command register and control DMA transfer between the resource on the system bus and the processor based on the DMA request command.08-27-2009
20120303856SEMICONDUCTOR DEVICE AND METHOD OF CONTROLLING THE SAME - A microcomputer includes a CPU (Central Processing Unit), a DMA (Direct Memory Access) processing unit, and a control unit. The control unit controls a processing speed of the CPU to be faster as the number of holding transfers increases, in which the number of holding transfers is the number of DMA transfers held to the DMA processing unit.11-29-2012
20120303855IMPLEMENTING STORAGE ADAPTER PERFORMANCE OPTIMIZATION WITH HARDWARE ACCELERATORS OFFLOADING FIRMWARE FOR BUFFER ALLOCATION AND AUTOMATICALLY DMA - A method and controller for implementing storage adapter performance optimization with automatic chained hardware operations eliminating firmware operations, and a design structure on which the subject controller circuit resides are provided. The controller includes a plurality of hardware engines and a control store configured to store a plurality of control blocks. Each control block is designed to control a hardware operation in one of the plurality of hardware engines. A plurality of the control blocks is selectively arranged in a respective predefined chain to define sequences of hardware operations. An automatic hardware structure is configured to build the respective predefined chain controlling the hardware operations for a predefined hardware function. The predefined hardware function includes buffer allocation and automatic DMA data from a host system to the controller for write operations, eliminating firmware operations.11-29-2012
20110016250SYSTEM AND METHOD UTILIZING DISTRIBUTED BYTE-WISE BUFFERS ON A MEMORY MODULE - A memory system and method utilizing one or more memory modules is provided. The memory module includes a plurality of memory devices and a controller configured to receive control information from a system memory controller and to produce module control signals. The memory module further includes a plurality of circuits, for example byte-wise buffers, which are configured to selectively isolate the plurality of memory devices from the system memory controller. The circuits are operable, in response to the module control signals, to drive write data from the system memory controller to the plurality of memory devices and to merge read data from the plurality of memory devices to the system memory controller. The circuits are distributed at corresponding positions separate from one another.01-20-2011
20100005212PROVIDING A VARIABLE FRAME FORMAT PROTOCOL IN A CASCADE INTERCONNECTED MEMORY SYSTEM - Systems and methods for providing a variable frame format protocol in a cascade interconnected memory system. The systems include a memory hub device that utilizes a first bus interface to communicate on a high-speed bus. The hub device also includes frame decode logic for translating variable format frames received via the first bus interface into memory device commands and data. The translating includes identifying write data headers and associated write data for self-registering write to data buffer commands.01-07-2010
20080320201CENTRAL PROCESSING APPARATUS, CONTROL METHOD THEREFOR AND INFORMATION PROCESSING SYSTEM - A plurality of system controllers 12-25-2008
20110010480METHOD FOR EFFICIENT I/O CONTROLLER PROCESSOR INTERCONNECT COUPLING SUPPORTING PUSH-PULL DMA READ OPERATIONS - A system for I/O controller-processor interconnect coupling supporting a push-pull DMA read operation, in one aspect, may comprise a processor interconnect comprising a plurality of caches and memory subsystems and an I/O controller coupled with the processor interconnect. The I/O controller may comprise a plurality of DMA read request queues, a DMA read slot pool comprising a plurality of DMA read slots, and an expander logic determining a priority of requests in said request queues.01-13-2011
20110072184DATA PROCESSING DEVICE AND DATA PROCESSING SYSTEM - To provide a data processing device in which a plurality of CPUs can individually and independently communicate with different functions of a USB device using a single communication path. The data processing device is configured so that a USB host module to be coupled to a plurality of central processing units has a plurality of pipes to communicate with an arbitrary end point of a USB device coupled from the outside of the data processing device, the data processing device also includes an access control register to specify which central processing unit should have a right to control the pipe and specify to which extent a range of the content of setting of a function for the pipe should be allowed, and a USB host interface is controlled in accordance with the content of setting of the access control register.03-24-2011
20110191517SYSTEM AND METHOD FOR TRANSMITTING DATA PACKETS IN A COMPUTER SYSTEM HAVING A MEMORY HUB ARCHITECTURE - A system and method for transmitting data packets from a memory hub to a memory controller is disclosed. The system includes an upstream reception port coupled to an upstream link. The upstream reception port receives the data packets from downstream memory hubs. The system further includes a bypass bus coupled to the upstream reception port. The bypass bus transports the data packets from the upstream reception port. The system further includes a temporary storage coupled to the upstream reception port and configured to receive the data packets from the upstream reception port. The system further includes a bypass multiplexer for selectively coupling an upstream transmission port to either one of a core logic circuit, the temporary storage, or the bypass bus. The system further includes a breakpoint logic circuit coupled to the bypass multiplexer and configured to switch the bypass multiplexer to selectively connect the upstream transmission port to either one of the core logic circuit, the bypass bus, or the temporary storage. The system further includes a local memory coupled to the core logic circuit and operable to receive and send the data packets to the core logic circuit.08-04-2011
20090172238BRIDGE CIRCUIT - A bridge circuit includes a bus, a memory interface module, a memory control module, and an external storage control module. The memory interface module receives a memory address from a processor via a memory interface and outputs the memory address to the bus. The memory address corresponds to one of a plurality of address regions of an address space of the processor. The memory control module receives the memory address via the bus and communicates with a memory when the memory address corresponds to a first one of the plurality of address regions. The external storage control module receives the memory address via the bus and communicates with an external storage device when the memory address corresponds to a second one of the plurality of address regions.07-02-2009
20080228984Single-Chip Multi-Media Card/Secure Digital (MMC/SD) Controller Reading Power-On Boot Code from Integrated Flash Memory for User Storage - A Multi-Media Card/Secure Digital (MMC/SD) single-chip flash device contains a MMC/SD flash microcontroller and flash mass storage blocks containing flash memory arrays that are block-addressable rather than randomly-addressable. MMC/SD transactions from a host MMC/SD bus are read by a bus transceiver on the MMC/SD flash microcontroller. Various routines that execute on a CPU in the MMC/SD flash microcontroller are activated in response to commands in the MMC/SD transactions. A flash-memory controller in the MMC/SD flash microcontroller transfers data from the bus transceiver to the flash mass storage blocks for storage. Rather than boot from an internal ROM coupled to the CPU, a boot loader is transferred by DMA from the first page of the flash mass storage block to an internal RAM. The flash memory is automatically read from the first page at power-on. The CPU then executes the boot loader from the internal RAM to load the control program.09-18-2008
20110167189STORAGE APPARATUS AND ITS DATA TRANSFER METHOD - By writing a command for transferring data from a first cluster to a second cluster and the second cluster writing data that was requested from the first cluster based on the command into the first cluster, data can be transferred in real time from the second cluster to the first cluster without having to issue a read request from the first cluster to the second cluster.07-07-2011
20120011295METHOD AND APPARATUS FOR WIRELESS BROADBAND SYSTEMS DIRECT DATA TRANSFER - Apparatus and method for direct data transfer in a wireless broadband system having an operating system, the apparatus including a central processing unit (CPU), at least one dedicated Direct Memory Access unit (DMA) local to the CPU, coupled directly to the CPU, and a commands FIFO (First In First Out) receiving commands from the CPU and automatically transferring the commands in sequence to the DMA for implementation by the DMA, in the absence of intervention by the operating system.01-12-2012
20120023280Atomic Operations with Page Migration in PCIe - A method and data processing system enables scheduling of atomic operations within a Peripheral Component Interconnect Express (PCIe) architecture during page migration. In at least one embodiment, firmware detects the activation of a page migration operation. The firmware notifies the I/O host bridge, which responds by setting an atomic operation stall (AOS) bit to a pre-established value that indicates that there is an ongoing migration within the memory subsystem of a memory page that is mapped to that I/O host bridge. When the AOS bit is set to the pre-established value, the I/O host bridge prevents/stalls any received atomic operations from completing. The I/O host bridge responds to receipt of receipt of an atomic operation by preventing the atomic operation from being initiated within the memory subsystem, when the AOS bit is set to the pre-established value. The AOS bit is reset when the migration operation has completed.01-26-2012
20120072636POWER-OPTIMIZED FRAME SYNCHRONIZATION FOR MULTIPLE USB CONTROLLERS WITH NON-UNIFORM FRAME RATES - A method, apparatus, and system to synchronize multiple host controllers with non-uniform frame rates. The apparatus includes a first host controller, a second host controller, and logic. The first host controller is configured to access memory at a first frame rate. The second host controller is configured to access the memory at a second frame rate which is different from the first frame rate. The logic is coupled to the first and second host controllers to synchronize the memory accesses of the first and second host controllers at a common frame rate. Other embodiments are described.03-22-2012
20110107001Performing data operations using non-volatile third dimension memory - Performing data operations using non-volatile third dimension memory is described, including a storage system having a non-volatile third dimension memory array configured to store data, the data including an address indicating a file location on a disk drive, and a controller configured to process an access request associated with the disk drive, the access request being routed to the non-volatile third dimension memory array to perform a data operation, wherein data from the data operation is used to create a map of the disk drive. In some examples, an address in the non-volatile third dimension memory array provides an alias for another address in a disk drive.05-05-2011
20100095044MOTHERBOARD SYSTEM, STORAGE DEVICE FOR BOOTING UP THEREOF AND CONNECTOR - A motherboard system is provided. The motherboard system includes a central processing unit (CPU), a control unit and an interface connector. The control unit is electrically connected to the CPU. The interface connector is electrically connected to the control unit and has a boot loader interface unit and a peripheral storage device interface unit, wherein the boot loader interface unit is electrically connected to the control unit and is configured for electrically connecting a system read only memory. When the power of the motherboard system is turned on, the CPU sends a read only memory fetch cycle to the control unit and fetches a booting program from the system read only memory configured in an external device via the boot loader interface unit. Accordingly, the system read only memory can be conveniently updated and maintained.04-15-2010
20120166700SPECIALIZED UNIVERSAL SERIAL BUS CONTROLLER - An apparatus comprises a memory device to store a pre-generated Universal Serial Bus (USB) command before a USB peripheral device is coupled to a USB. The apparatus also includes a processing device to retrieve the pre-generated USB command from the memory device and transmit the pre-generated USB command to the USB peripheral device over the USB. A method comprises identifying a Universal Serial Bus (USB) peripheral device is coupled to a USB. The USB peripheral device is coupled to the universal serial bus after a pre-generated USB command is stored in a memory device. The method further includes transmitting the pre-generated USB command to the USB peripheral device over the USB in response to identifying the USB peripheral device is coupled to the USB.06-28-2012
20120131253PCIE NVRAM CARD BASED ON NVDIMM - A memory system controller includes one or more sockets for accommodating NVDIMM cards produced by different NVDIMM providers; a PCIe interface for coupling the memory system controller to a host; and a controller coupled to the PCIe interface over a PCIe-compliant connection and to the one or more sockets over respective DDR2 connections. The controller is configured to manage data transfers between the host and a specified one of the NVDIMM sockets in which an NVDIMM card is accommodated as DMA reads and writes, format data received from the PCIe interface for transmission to the specified NVDIMM socket over the corresponding one or more DDR2 interfaces, and initiate save and restore operations on the NVDIMM card accommodated within the specified NVDIMM socket in response to power failure and power restoration indications.05-24-2012
20120131252INTELLIGENT PCI-EXPRESS TRANSACTION TAGGING - Systems and methods of routing data units such as data packets or data frames that provide improved system performance and more efficient use of system resources. The disclosed systems and methods employ memory mapping approaches in conjunction with transaction ID tag fields from the respective data units to assign each tag value, or at least one range of tag values, to a specified address, or at least one range of specified addresses, for locations in internal memory that store corresponding transaction parameters. The disclosed systems and methods can also apply selected bits from the transaction ID tag fields to selector inputs of one or more multiplexor components for selecting corresponding transaction parameters at data inputs to the multiplexor components. The disclosed systems and methods may be employed in memory-read data transfer transactions to recover the transaction parameters necessary to determine destination addresses for memory locations where the memory-read data are to be transmitted.05-24-2012
20120317328SCALABLE DISTRIBUTED MEMORY AND I/O MULTIPROCESSOR SYSTEM - A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module. The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules. Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.12-13-2012
20120137040MULTI CHANNEL SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR DEVICE INCLUDING THE SAME - Disclosed is a semiconductor memory device that includes a plurality of channel memories mounted within a package and is capable of minimizing or reducing the number of through-silicon vias. With the semiconductor memory device, a row command or a row address on two or more channels is applied through a shared bus. The semiconductor memory device is capable of reducing an overhead of a die size by reducing the number of through-silicon vias. A method of driving a multi-channel semiconductor memory device including a plurality of memories, using a shared bus, is also provided.05-31-2012
20110185101SCALABLE DISTRIBUTED MEMORY AND I/O MULTIPROCESSOR SYSTEM - A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module. The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules. Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.07-28-2011
20120173786METHOD AND SYSTEM FOR PERFORMING DMA IN A MULTI-CORE SYSTEM-ON-CHIP USING DEADLINE-BASED SCHEDULING - A direct memory access (DMA) engine schedules data transfer requests of a data processing system according to both an assigned transfer priority and the deadline for completing a transfer.07-05-2012
20120185632IMPLEMENTING PCI-EXPRESS MEMORY DOMAINS FOR SINGLE ROOT VIRTUALIZED DEVICES - A method, system and computer program product are provided for implementing PCI-Express memory domains for single root virtualized devices. A PCI host bridge (PHB) includes a memory mapped IO (MMIO) domain descriptor (MDD) and an MMIO Domain Table (MDT) are used to associate MMIO domains with PCI memory VF BAR spaces. One MDD is provided for each unique VF BAR space size per bus segment connecting a single root IO virtualization (SRIOV) device to the PCI host bridge (PHB). The MDT used with the MDD includes having a number of entries limited to a predefined total number of SRIOV VFs to be configured. A VF BAR Stride, which may be further implemented as a VF BAR Stride Capability Structure, is provided to reduce the number of MDDs required to map SRIOV VF BAR spaces. A particular definition of the MDD is provided to reduce the number of MDDs required to at most one per SRIOV bus segment below a PHB.07-19-2012
20120084484SELECTIVELY COMBINING COMMANDS FOR A SYSTEM HAVING NON-VOLATILE MEMORY - Systems and methods are disclosed for selectively combining commands for a system having non-volatile memory (“NVM”). In some embodiments, a command dispatcher of a system can receive multiple commands to access a NVM for a period of time. After receiving the multiple commands, the command dispatcher can determine a set of commands that are naturally combinable. In some embodiments, the command dispatcher can select commands that are fairly distributed across different chip enables (“CEs”) and/or buses. After selecting the set of commands, the command dispatcher can combine the set of commands into a multi-access command. Finally, the command dispatcher can dispatch the multi-access command to the NVM.04-05-2012
20120260017COMPUTER, COMPUTER SYSTEM, AND DATA COMMUNICATION METHOD - A computer includes first and second processors, first and second I/O devices, a shared memory, and an interrupt controller. The first processor issues a control command for causing the first I/O device to read target data from the first apparatus and store the target data in the shared memory. The first I/O device reads the target data from the first apparatus and, transfers the target data to the shared memory, and generates an I/O complete interrupt. The interrupt controller delivers the generated I/O complete interrupt to the second processor. When the second processor receives the I/O complete interrupt, the second processor issues a control command for causing the second I/O device to read the target data from the shared memory and send the target data to the second apparatus. The second I/O device reads the target data from the shared memory and sends the target data to the second apparatus.10-11-2012
20090049225Information processing apparatus, information processing method, program for executing the information processing method, storage medium storing the program, DMA controller, DMA transfer method, program for executing the DMA transfer method, and storage medium storing the program - Disclosed herein is an information processing apparatus that transfers information, using direct memory access (DMA), between a first storage section in an information processing system and a second storage section in an information transfer system. The information processing system includes the first storage section for storing the information, and a control section. The information transfer system includes: the second storage section for storing descriptor information indicating the location at which the information is stored in the first storage section and the size of the information; and a DMA transfer section for DMA transferring the information between the first storage section and the second storage section based on the descriptor information. The DMA transfer section DMA transfers the descriptor information concerning the DMA transferred information from the second storage section to the first storage section. The control section loads the descriptor information from the first storage section.02-19-2009
20120265917DATA TRANSFERRING DEVICE - A data transfer device for transferring data on a platform, in particular for transferring simultaneous data between different components of the platform, is disclosed. In one aspect, the data transfer device is adapted for simultaneous transfer of data between at least 3 ports of which at least one is an input port and at least one is an output port. The data transfer device has at least two controllers for executing instructions that transfer data between an input port and an output port. The controllers are adapted for receiving a synchronization instruction for synchronizing between the controllers and/or a synchronization instruction for synchronizing input ports and output ports.10-18-2012
20120265916DYNAMIC ALLOCATION OF A DIRECT MEMORY ADDRESS WINDOW - A computer-implemented method may include determining that a slot coupled to a peripheral component interconnect host bridge is occupied by an input/output adapter. The computer-implemented method may include determining one or more characteristics of the input/output adapter and determining whether the input/output adapter is capable of using additional memory based on the one or more characteristics of the input/output adapter. The computer-implemented method may also include allocating the additional memory for the input/output adapter in response to determining that the input/output adapter is capable of using the additional memory.10-18-2012
20110131360Context Execution in a Media Controller Architecture - Described embodiments provide a media controller for processing one or more data transfer requests received from at least one host device. The media controller includes a buffer to receive data of a data transfer request from a communication link and a command parser to generate one or more contexts corresponding to the data transfer request. The one or more contexts are stored in the buffer. At least one queue of the media controller includes a regular context queue for queuing regular-priority contexts, and a high-priority context queue for queuing high-priority contexts. A context manager coordinates processing of regular-priority contexts and high-priority contexts of the at least one queue based on context boundaries, wherein, when a context is processed at a context boundary, data corresponding to the processed context is data is transferred between the communication link and at least one of the buffer and the at least one storage media.06-02-2011
20120239848MITIGATION OF EMBEDDED CONTROLLER STARVATION IN REAL-TIME SHARED SPI FLASH ARCHITECTURE - An embedded controller includes a microcontroller core, a first bus interface that does not support bus arbitration, a second bus interface and memory control circuitry. The first bus interface is configured to receive and transmit memory transactions from and to a Central Processing Unit (CPU) chipset. The second bus interface is configured to communicate with a memory and to transfer the memory transactions of the CPU chipset to and from the memory. The memory control circuitry is configured to evaluate a starvation condition that identifies an inability of the microcontroller core to access the memory via the second bus interface due to the memory transactions transferred between the CPU chipset and the memory via the first and second bus interfaces, and to invoke a predefined corrective action when the starvation condition is met.09-20-2012
20110047311MULTI-PORT MEMORY AND OPERATION - Multi-port memory having an additional control bus for passing commands between ports have individual ports that can be configured to respond to a command received from an external control bus or to a command received from the additional control bus. This facilitates various combinations of ports to vary the bandwidth or latency of the memory to facilitate tailoring performance characteristics to differing applications.02-24-2011
20120324138DISTRIBUTED TRACE USING CENTRAL PERFORMANCE COUNTER MEMORY - A plurality of processing cores, are central storage unit having at least memory connected in a daisy chain manner, forming a daisy chain ring layout on an integrated chip. At least one of the plurality of processing cores places trace data on the daisy chain connection for transmitting the trace data to the central storage unit, and the central storage unit detects the trace data and stores the trace data in the memory co-located in with the central storage unit.12-20-2012
20120278522USING DIRECT MEMORY ACCESS TO INITIALIZE A PROGRAMMABLE LOGIC DEVICE - An embodiment includes using direct memory access (DMA) to initialize a programmable logic device (PLD). An aspect of the invention includes manipulating a control line of the PLD to configure the PLD in a programming mode. PLD programming data is received at a PLD interface from a DMA control at a DMA speed. The PLD interface controls access of a processor and the DMA control to a programming port on the PLD. The PLD interface includes a data buffer and pacing logic. The PLD programming data is written to the data buffer and read from the data buffer. The PLD programming data transmitted to the programming port on the PLD at a PLD programming speed. The pacing logic of the PLD interface controls the data transmission at the PLD programming speed, and the DMA control is configured to transform the PLD programming data while the processor performs other processing tasks.11-01-2012
20110271028MODULAR INTEGRATED CIRCUIT WITH COMMON INTERFACE - A modular integrated circuit includes a hub module that is coupled to a plurality of spoke modules via a plurality of hub interfaces. The plurality of hub interfaces provide a plurality of signal interfaces between the hub module and each of the plurality of spoke modules, wherein each of the plurality of signal interfaces is isolated from each of the other signal interfaces of the plurality of signals interface, and wherein each of the plurality of signal interfaces operates in accordance with a common signaling format.11-03-2011
20110320672METHOD AND APPARATUS FOR DISTRIBUTED DIRECT MEMORY ACCESS FOR SYSTEMS ON CHIP - A distributed direct memory access (DMA) method, apparatus, and system is provided within a system on chip (SOC). DMA controller units are distributed to various functional modules desiring direct memory access. The functional modules interface to a systems bus over which the direct memory access occurs. A global buffer memory, to which the direct memory access is desired, is coupled to the system bus. Bus arbitrators are utilized to arbitrate which functional modules have access to the system bus to perform the direct memory access. Once a functional module is selected by the bus arbitrator to have access to the system bus, it can establish a DMA routine with the global buffer memory.12-29-2011
20100262746METHOD OF INTEGRATING A PERSONAL COMPUTING SYSTEM AND APPARATUS THEREOF - An integrated circuit also referred to as an integrated computing system has a single substrate that has either deposited thereon or etched thereon, a central processing unit, a north bridge, a south bridge, and a graphics controller. An internal bus is coupled between the north bridge and the central processing unit. The central processing unit and north bridge do not require interfaces to perform bus protocol conversions.10-14-2010
20130013840SINGLE PIPE NON-BLOCKING ARCHITECTURE - A method for processing an incoming command destined for a target is provided, comprising: determining if the incoming command is a data command or a management command; forwarding the incoming command to a storage management component of the target when the incoming command is a management command; when the incoming command is a data command: determining if a disk command queue on the target is full; sending the incoming command to the disk command queue when the disk command queue is not full; when the disk command queue is full: starting a timer, the timer having a predetermined length; sending the incoming command to the disk command queue when the disk command queue becomes not full prior to the expiration of the timer; and sending a rejection of the incoming command to the host only if, upon expiration of the timer, if the disk command queue is still full.01-10-2013
20100161868DATA TRANSFER APPARATUS AND DATA TRANSFER METHOD - A data transfer apparatus performing data communication by transmitting a bus use request to an arbiter between a plurality of nodes coupled in a tree shape through a bus is provided. The data transfer apparatus includes a request generation circuit which generates a highest priority request indicating that a priority level for using the bus is the highest, a determination circuit which determines the priority level of the highest priority request, and a priority level setting circuit which determines the highest priority request which takes priority based on a result of the determination circuit when a plurality of highest priority requests conflicts in a node.06-24-2010
20130024595PCI EXPRESS SWITCH WITH LOGICAL DEVICE CAPABILITY - A PCIe switch implements a logical device for use by connected host systems. The logical device is created by logical device enabling software running on a host management system. The logical device is able to consolidate one or more physical devices or may be entirely software-based. Commands from the connected host are processed in the command and response queues in the host and are also reflected in shadow queues stored in the management system. A DMA engine associated with the connected host is set up to automatically trigger on queues in the connected (local) host. Commands are sent to the physical devices to complete the work and a completion signal is sent to the management software and a response to the work is sent directly to the connected host, which is not aware that the logical device is non-existent and is implemented by software in the management system.01-24-2013
20130024594SEMICONDUCTOR STORAGE DEVICE-BASED DATA RESTORATION - Embodiments of the invention provide a device and method for warm booting whereby data restoration occurs at the powering-on of the host, and can therefore be performed by the boot disk. Specifically, when the system is powered on, a backup controller will send a notification to a DMA controller indicating the data restoration is needed. The backup controller will automatically resorts contents of a backup storage device to main memory. During the process, when the host requests data, the DMA controller reads the data from the backup storage unit and sends it to the host. Then, once data restoration is complete, normal operations can commence.01-24-2013
20130173834METHODS AND APPARATUS FOR INJECTING PCI EXPRESS TRAFFIC INTO HOST CACHE MEMORY USING A BIT MASK IN THE TRANSACTION LAYER STEERING TAG - Methods and apparatus are provided for implementing transaction layer processing (TLP) hint (TPH) protocols in the context of the peripheral component interconnect express (PCIe) base specification. The method allows an endpoint function associated with a PCI Express device to configure a steering tag header in the open systems interconnect (OSI) transaction layer to identify a particular processing resource that the requester desires to target, such as a specific processor or cache location within the execution core. A bit mask may be implemented by the hardware or operating system, for example, by embedding the bit mask in the steering tag header. The bit mask provides administrative oversight of the steering tag header configuration, to thereby mitigate unintended denial of service attacks or cache misses occasioned by aggressive steering tag configuration strategies employed by endpoint functions.07-04-2013
20130179620Administering Connection Identifiers For Collective Operations In A Parallel Computer - Administering connection identifiers for collective operations in a parallel computer, including prior to calling a collective operation, determining, by a first compute node of a communicator to receive an instruction to execute the collective operation, whether a value stored in a global connection identifier utilization buffer exceeds a predetermined threshold; if the value stored in the global ConnID utilization buffer does not exceed the predetermined threshold: calling the collective operation with a next available ConnID including retrieving, from an element of a ConnID buffer, the next available ConnID and locking the element of the ConnID buffer from access by other compute nodes; and if the value stored in the global ConnID utilization buffer exceeds the predetermined threshold: repeatedly determining whether the value stored in the global ConnID utilization buffer exceeds the predetermined threshold until the value stored in the global ConnID utilization buffer does not exceed the predetermined threshold.07-11-2013
20130091316MODULAR INTEGRATED CIRCUIT WITH COMMON INTERFACE - A modular integrated circuit includes a hub module that is coupled to a plurality of spoke modules via a plurality of hub interfaces. The plurality of hub interfaces provide a plurality of signal interfaces between the hub module and each of the plurality of spoke modules, wherein each of the plurality of signal interfaces is isolated from each of the other signal interfaces of the plurality of signals interface, and wherein each of the plurality of signal interfaces operates in accordance with a common signaling format.04-11-2013
20130132634ROUTING SWITCH APPARATUS, NETWORK SWITCH SYSTEM, AND ROUTING SWITCHING METHOD - The present disclosure relates to a routing switch apparatus, a network switch system, and a routing switch method. The routing switch apparatus includes one or more direct memory access modules and at least two protocol conversion interfaces. The direct memory access module is configured to generate a continuous access request of a cross network node, and control data transmission in the at least two protocol conversion interfaces; each protocol conversion interface is configured to convert a communication protocol of data transmitted inside and outside the routing switch apparatus and connect the routing switch module and an external network node. The routing switch apparatus may be introduced to replace a network switch, so that cross-node memory access and IO space access can be performed directly rather than through a proxy, thereby reducing delay of the cross-node memory access and IO space access and improving overall performance of a system.05-23-2013
20100318714METHOD AND APPARATUS TRANSFERRING DATA VIA UNIVERSAL SERIAL BUS - A method of communicating data between an external storage device and a USB host via a USB device is disclosed. The method includes receiving data from the USB host; and either (1) directly communicating the received data to the external storage device via an exclusive bus, or (2) indirectly communicating the received data to the external storage device via a USB bus, separate from the exclusive bus.12-16-2010
20100318713Flow Control Mechanisms for Avoidance of Retries and/or Deadlocks in an Interconnect - Flow control mechanisms avoid or eliminate retries of transactions in a coherency interconnect. A class of transaction (CoT) framework is defined whereby individual transactions are associated with CoT labels consistent with chains of dependencies that exist between transactions initiated by any of the cooperating devices that participate in a given operation. In general, coherency protocols create dependencies that, when mapped to physical resources, can result in cycles in a graph of dependencies and deadlock. To support architectural mechanisms for deadlock avoidance, CoT labels are applied to individual transactions consistent with a precedence order of those transactions both (i) with respect to the operations of which such transactions are constituent parts and (ii) as amongst the set of such operations supported in the coherency interconnect. CoT labels applied to respective transactions constitute a CoT framework that may be used by coherency managers to efficiently support concurrent in-flight transactions without retry.12-16-2010
20100318712SYSTEM AND METHOD FOR DISTRIBUTED PERSISTENT COMPUTING PLATFORM - Example embodiments of the invention are disclosed for an adaptive computing platform wherein a reader/writer device uses distributed, external memory resources as non-volatile memory blocks to provide distributed execution-in-place capability for the reader/writer device, such as a mobile phone, to enhance the processing power of the device. The execution architecture of the reader/writer device is scalable and adaptive to accommodate variations in the speed, size, and other characteristics of different external memory blocks it uses as it moves from one external memory block to another.12-16-2010
20100318711SIMULTANEOUS INTERMEDIATE PROXY DIRECT MEMORY ACCESS - Disclosed is a method that simultaneously transfers DMA data from a peripheral device to a hardware assist function and processor memory. A first DMA transfer is configured to transfer data from the peripheral to a peripheral DMA engine. While receiving the data, the DMA engine simultaneously transfers this data to processor memory. The DMA engine also transfers a copy of the data to a hardware assist function. The DMA engine may also simultaneously transfer data from processor memory to a peripheral device while transferring a copy to a hardware assist function.12-16-2010
20130159590LOW LATENCY, HIGH BANDWIDTH DATA COMMUNICATIONS BETWEEN COMPUTE NODES IN A PARALLEL COMPUTER - Methods, systems, and products are disclosed for data transfers between nodes in a parallel computer that include: receiving, by an origin DMA on an origin node, a buffer identifier for a buffer containing data for transfer to a target node; sending, by the origin DMA to the target node, a RTS message; transferring, by the origin DMA, a data portion to the target node using a memory FIFO operation that specifies one end of the buffer from which to begin transferring the data; receiving, by the origin DMA, an acknowledgement of the RTS message from the target node; and transferring, by the origin DMA in response to receiving the acknowledgement, any remaining data portion to the target node using a direct put operation that specifies the other end of the buffer from which to begin transferring the data, including initiating the direct put operation without invoking an origin processing core.06-20-2013
20110314199APPARATUS AND METHOD FOR DIRECT MEMORY ACCESS IN A HUB-BASED MEMORY SYSTEM - A memory hub for a memory module having a DMA engine for performing DMA operations in system memory. The memory hub includes a link interface for receiving memory requests for access at least one of the memory devices of the system memory, and further including a memory device interface for coupling to the memory devices, the memory device interface coupling memory requests to the memory devices for access to at least one of the memory devices. A switch for selectively coupling the link interface and the memory device interface is further included in the memory hub. Additionally, a direct memory access (DMA) engine is coupled through the switch to the memory device interface to generate memory requests for access to at least one of the memory devices to perform DMA operations.12-22-2011
20120030398Combination Non-Volatile Memory and Input-Output Card with Direct Memory Access - A removable electronic circuit card having both a memory module with a non-volatile mass storage memory and a separate input-output module so that data transfers may be made through the input-output module directly to and from the mass storage memory in a direct memory access (DMA) type transfer when the card is inserted into the host system but without having to pass the data through the host system. Once the host gives a DMA command, the data transfer is accomplished independently of the host system, except for the host supplying power and possibly a clock signal and other like support, during such a data transfer directly with card. The data for the transfer can be communicated between the input-output module and the exterior device through either wireless or an electrical connection means.02-02-2012
20120030397INFORMATION PROCESSING SYSTEM AND METHOD FOR CONTROLLING INFORMATION PROCESSING SYSTEM - An information processing system includes a memory, a controller that reads data from a device coupled thereto and writes the data on the memory, a bridge that couples a system bus and an input output bus, the system bus being coupled to the memory and the processor, the input output bus being coupled to the controller, a check code generator that generates a check code from the data read from the device, and a determining unit that determines whether a second check code generated from the data read from the memory corresponds with the first check code.02-02-2012
20120030396Decoupled Memory Modules: Building High-Bandwidth Memory Systems from Low-Speed Dynamic Random Access Memory Devices - Apparatus and methods related to exemplary memory system are disclosed. The exemplary memory systems use a synchronization device to increase channel bus data rates while using relatively-slower memory devices operating at device bus data rates that differ from channel bus data rates.02-02-2012
20130198433METHODS AND SYSTEMS FOR DEVICES WITH SELF-SELECTING BUS DECODER - Disclosed are methods and devices, among which is a device including a self-selecting bus decoder. In some embodiments, the device may be coupled to a microcontroller, and the self-selecting bus decoder may determine a response of the peripheral device to requests from the microcontroller. In another embodiment, the device may include a bus translator and a self-selecting bus decoder. The bus translator may be configured to translate between signals from a selected one of a plurality of different types of buses. A microcontroller may be coupled to a selected one of the plurality of different types of buses of the bus translator.08-01-2013

Patent applications in class Direct memory access (e.g., DMA)