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Bus access regulation

Subclass of:

710 - Electrical computers and digital data processing systems: input/output


Patent class list (only not empty are listed)

Deeper subclasses:

Class / Patent application numberDescriptionNumber of patent applications / Date published
710110000 Bus master/slave controlling 322
710113000 Centralized bus arbitration 94
710112000 Bus request queuing 15
710119000 Decentralized bus arbitration 12
710108000 Bus locking 12
710109000 Bus polling 7
710111000 Rotational prioritizing (i.e., round robin) 7
20090193164General Input/Output Architecture, Protocol and Related Methods to Implement Flow Control - An enhanced general input/output communication architecture, protocol and related methods are presented. In one embodiment, a method for an enhanced general input/output communication architecture includes initializing a flow control mechanism within an general input/output (GIO) interface associated with a virtual channel upon initialization of the virtual channel, and tracking receive buffer availability in a remote GIO interface coupled with the GIO interface by the virtual channel by monitoring an indication associated with an amount of content transmitted from the GIO interface to the remote GIO interface.07-30-2009
20120246366SERIAL PORT REMOTE CONTROL CIRCUIT - A serial port remote control circuit includes a first interface circuit, a control circuit, an output circuit, and a power circuit. The first interface circuit converts recommended standard 232 (RS232) level signals to transistor-transistor logic (TTL) level signals or vice versa. The control circuit is connected to the first interface circuit, to convert the TTL level signals to physical bus signal or vice versa. The output circuit is connected to the control circuit, to convert the received physical bus signals from the control circuit to network bus signals or vice versa. The power circuit outputs a first voltage and a second voltage converted from the first voltage to the control circuit, the first interface circuit, and the output circuit.09-27-2012
20090119428Method and Apparatus for Indirect Interface with Enhanced Programmable Direct Port - Device, apparatus and methods for implementing a direct address mode to directly access registers by passing an indirect interface includes a display controller. A plurality of direct access registers for bypassing indirect interface is defined within the display controller. The display controller includes a bus interface having a first pin that is configured to activate the direct address mode and a second pin that configured to identify one of the direct access registers. The first pin in conjunction with the second pin provides a direct address mode through which the non-direct access registers may be directly accessed bypassing the indirect interface so that register index cycle, when accessing memory, may be avoided.05-07-2009
20090327549MONITORING UNIT FOR MONITORING OR CONTROLLING USER ACCESS TO A DATA BUS AND USER HAVING SUCH A MONITORING UNIT - The present invention relates to a local monitoring unit, which is locally assigned to a bus controller of a user of a communication system, a central monitoring unit of a communication system for monitoring and/or controlling the access of multiple users to a data bus. An important feature of the provided monitoring concept is that the monitoring unit has a time basis of its own that is independent of a local time basis of a communication controller of the users and that is synchronized with a global time basis of the communication system. This separate local time basis is utilized in the monitoring unit to monitor and/or control the access authorization of the communication controller or of a bus driver to the data bus. In this way, sending conflicts of the users, in particular due to permanent disturbances in one or more users, may be reliably detected and prevented.12-31-2009
20130060982INFORMATION PROCESSING SYSTEM AND METHOD OF CONTROLLING HARDWARE OF THE INFORMATION PROCESSING SYSTEM - An information processing system has a plurality of processing devices and a plurality of system control devices which control hardware in the plurality of processing devices. Each of the system control devices shares the hardware control in the plurality of processing devices. One of system control devices determines shared processing amount of which each of system control devices charge from processing amount of hardware control in the plurality of processing devices and each of the system control devices executes the hardware control of the shared amount in the plurality of processing devices.03-07-2013
20130060981SYSTEMS AND METHODS FOR AN ENHANCED CONTROLLER ARCHITECTURE IN DATA STORAGE SYSTEMS - Disclosed herein is a controller architecture that pairs a controller with a NVM (non-volatile memory) storage system over a high-level, high speed interface such as PCIe. In one embodiment, the NVM storage system includes a bridge that communicates with the controller via the high-level interface, and controls the NVM via an interface (e.g., ONFI). The controller is provided a rich set of physical level of controls over individual elements of the NVM. In one embodiment, the controller is implemented in a higher powered processor that supports advanced functions such as mapping, garbage collection, wear leveling, etc. In one embodiment, the bridge is implemented in a lower powered processor and performs basic signal processing, channel management, basic error correction functions, etc. This labor division provides the controller physical control of the NVM over a fast, high-level interface, resulting in the controller managing the NVM at both the page and block level.03-07-2013
20120226836SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit capable of reducing unnecessary current consumption includes a plurality of bus drive circuits for receiving data input, a common bus coupled to the bus drive circuits, and a bus holder coupled to the common bus. One of the bus drive circuits is selected as the selected bus drive circuit. When a logical value corresponding to the data input to be output is the same as a logical value that has been held by the bus holder and output to the common bus, the selected bus drive circuit stops outputting the logical value corresponding to the data input to the common bus. With this configuration, it is possible to eliminate the unnecessary output of the selected bus drive circuit, and to reduce unnecessary current consumption compared to the conventional semiconductor integrated circuit.09-06-2012
20110022754BUS ENHANCED NETWORK ON CHIP - A system that includes multiple modules of an integrated circuit; a network on chip that is coupled to the multiple modules; a bus, coupled in parallel to the network on chip to the multiple modules; wherein a latency of the bus is lower and more predictable than an average latency of the network of chip.01-27-2011
20090013113Methods and systems for interprocessor message exchange between devices using only write bus transactions - Systems and methods for reducing or eliminating use of read transactions by a message consuming device coupled through a shared bus to a message producing device to transfer a message from the producing device to the consuming device. Features and aspects hereof provide for use of only write transactions on the bus issued by the devices to transfer messages directly into the data memory of the consuming device. A memory manager on the producing device may manage allocation and freeing of buffer space within the data memory of the consuming device. The producing device notifies the consuming device when a message transfer is completed.01-08-2009
20090006688BLACK-BOX HOST STACK LATENCY MEASUREMENT - A method comprises sniffing an input from a client device to a host device and an output from the host device to the client device; recording a first time parameter in response to a characteristic data unit being inserted into the input that is outputted from a host stack of a host device; recording a second time parameter in response to the output that comprises the characteristic data unit being received by the host stack; and measuring a latency based on the first time parameter, the second time parameter and arrival time of the input and the output at a sniffing point.01-01-2009
20130166799METHOD FOR ALLOCATING SUBSCRIBER ADDRESSES TO BUS SUBSCRIBERS OF A BUS-BASED CONTROL SYSTEM - A bus-based control system comprises a plurality of bus subscribers which are connected to one another by means of a communication medium. The bus subscribers are assigned logical subscriber addresses. Next, the assigned subscriber addresses are verified. For this purpose, the bus subscribers use a defined mathematical operation to calculate a common first check value which is compared with a second check value. The mathematical operation begins with a defined starting value and comprises a number of operation steps which use a number of defined operands. Each of the subscriber addresses to be verified forms a different operand, and each bus subscriber executes at least one operation step.06-27-2013
20130166800Method and device for transmitting data having a variable bit length - A method for serially transmitting data in a bus system having at least two bus users, which exchange data frames over the bus, the bus users deciding which data frames they receive, as a function of an identifier, the data frames having a logic structure according to the CAN standard, ISO 11898-1, the temporal bit length (L06-27-2013
20110167185METHOD AND APPARATUS FOR TRANSMITTING DATA - A semiconductor device comprising an interface logic module for transmitting data frames across an interface, and controller logic module arranged to control a rate at which the interface logic transmits data across the interface. Upon receipt of data frames to transmit across the interface, the controller logic module is arranged to determine a sequence of data rates with which to transmit sequential data frames across the interface, and to configure the transmission of the data frames across the interface according to the determined data rate sequence. The selection of these data rates will be dependent on specific critical RF frequencies where EMI impacts have to be minimized.07-07-2011
20110283030METHOD AND SYSTEM FOR MANAGING PULSE-WIDTH MODULATION - A host computer and a method for managing pulse-width modulation (PWM) include detecting a signal of a powerGD port. The management system further includes confirming a first state according to a first signal of the powerGD port. The management system further includes enabling the PWM port if the first state is in a power-on state, and disabling the PWM port if the first state is a power-off state.11-17-2011
20110283029IMPLEMENTING ELECTRONIC CHIP IDENTIFICATION (ECID) EXCHANGE FOR NETWORK SECURITY - A method and circuit for implementing electronic chip identification (ECID) exchange for network security in an interconnect system, and a design structure on which the subject circuit resides are provided. Each interconnect chip includes an ECID for the interconnect chip, each ECID is unique and is permanently stored on each interconnect chip. Each interconnect chip sends predefined exchange identification (EXID) messages including the ECID across links to other interconnect chips in the interconnect system. Each interconnect chip compares a received EXID with a system list for the interconnect system to verify validity of the sending interconnect chip.11-17-2011
20090150586Optimizing clock crossing and data path latency - In one embodiment, the present invention includes a method for transmitting a predetermined data pattern from a first agent to a second agent of an interface, receiving an indication of correct receipt of the predetermined data pattern in a buffer of the second agent, determining in a state machine of the first agent an updated load position within a window of the predetermined data pattern at which the buffer can realize the correct receipt, and transmitting the updated load position to the second agent to enable the second agent to capture incoming data from the first agent at the updated load position. Other embodiments are described and claimed.06-11-2009
20110302343SYSTEMS AND METHODS FOR PROVIDING INSTANT-ON FUNCTIONALITY ON AN EMBEDDED CONTROLLER - Systems and methods for providing instant-on functionality on an embedded controller are disclosed. A method of providing instant-on functionality on a controller comprises an initial state, an intermediate state and a final state. The initial state comprises installing a first responder code, enabling the first responder code and enabling a timer interrupt service routine. The intermediate state comprises registering the first responder code as a timer interrupt service routine. The timer interrupt service routine initiates periodic processing. The final state comprises registering a steady-state interrupt service routine.12-08-2011
20100005206AUTOMATIC READ DATA FLOW CONTROL IN A CASCADE INTERCONNECT MEMORY SYSTEM - Systems and methods for providing automatic read flow control in a cascade interconnect memory system. A hub device includes an interface to a channel in a cascade interconnect memory system for connecting the hub device to an upstream hub device or a memory controller. The channel includes an upstream bus and a downstream bus. The hub device also includes read data flow control logic for determining when to transmit data on the upstream bus. The determining is responsive to an order of commands received on the downstream bus and to current traffic on the upstream bus.01-07-2010
20100082862UNIVERSAL SERIAL BUS ENDPOINT CONTEXT CACHING - According to some embodiments, an apparatus may be capable of exchanging information with t potential universal serial bus endpoints, where t is an integer greater than 1. Moreover, x endpoint state machines may be established, where x is an integer greater than 1 and less than t. A first endpoint state machine may then be assigned to a first potential endpoint having a pending work item. Before the apparatus has completed the pending work item associated with the first potential endpoint, the first endpoint state machine may be flushed, and the first endpoint state machine may be re-assigned to a second potential endpoint.04-01-2010
20080209093Fine-grained bandwidth control arbiter and the method thereof - A fine-grained bandwidth control arbiter manages the shared bus usage of the requests of the masters which have real-time and/or bandwidth requirements, moreover, the masters are preset a ticket respectively. The arbiter consists of three components, a real-time handler, a bandwidth regulator, and a lottery manager with tuned weight. The real-time handler grants the most urgent request. The bandwidth regulator handles the bandwidth allocation and blocks the requests of masters that have met the bandwidth requirement. The lottery manager with tuned weight stochastically grants one of the contending masters according to the ticket assignment.08-28-2008
20090300246PACKET COMMUNICATION DEVICE AND PACKET COMMUNICATION METHOD - A packet communication device for switching packets to be transferred in packet communication which is time-managed in constant cycles, the packet communication device includes a changing section configured to change a portion of a first packet to be transmitted in each of the constant cycles.12-03-2009
20100146172Apparatus and Method for Controlling a Master/Slave System via Master Device Synchronization - A method of operating a master/slave system includes the step of identifying a master receive data phase value to coordinate the transfer of data from a slave device without phase alignment circuitry to a master device with a universal phase aligner. Data is transferred from the slave device to the master device in accordance with the master receive data phase value. The master device characterizes a master transmit data phase value to coordinate the transfer of data from the master device to the slave device. Subsequently, the master device routes data to the slave device in accordance with the master transmit data phase value.06-10-2010
20100293311DEVICE AND METHOD FOR MANIPULATING COMMUNICATION MESSAGES - A device for manipulating communication messages in a communication system is provided, which communication system includes a data bus, and a plurality of nodes connected thereto, and an arrangement for transmitting messages in message frames at fixedly predefined communication cycles. The device is connected in the data bus between at least one node for which the messages to be manipulated are intended and the other nodes of the communication system. The device has an arrangement for intercepting the messages before they reach the at least one node, an arrangement for manipulating the intercepted messages, and an arrangement for transmitting the manipulated messages to the at least one node.11-18-2010
20080244129MASTER DEVICE OF TWO-WIRE BUS PROVIDING RELEASE FUNCTION FOR CLOCK LINE AND METHOD THEREOF - Disclosed is a master device which is capable of communicating with a salve device via a two-wire bus having a clock line and a data line. The master device includes a data port, a clock port and an output port. The output port is also coupled to the clock line. When the clock is held by the slave device for exceeding a predetermined stretching period, the output port can transmit at least one clock pulse generated by the master device to the slave device through the clock line to prevent transmission failure or data corruption. The master device checks each time whether or not a response is received via the data port after the output port transmits the clock pulse generated by the master device. The response represents that releasing the clock is confirmed. Then, the data port transmits a stop pulse after releasing the clock.10-02-2008
20080250178Load Distribution in Storage Area Networks - A load balancing method and system for identifying an input/output (I/O) network path from a set off I/O network paths is provided by the invention. The set off I/O network paths connect a host system via a network to a storage subsystem. The host system comprises at least one host bus adapter (HBA) and the storage subsystem comprises at least one I/O device and the network comprises at least one network device. Each of the HBA, the I/O device and the network device comprise at least one I/O port. For each I/O port of each HBA, an HBA port limit is determined. Additionally the set of I/O network paths which connect the I/O port of each of the HBA via the I/O ports of the network device to the I/O port of the I/O device is identified. Then a fabric utilization limit is determined for each I/O network path and a HBA port utilization is determined for each I/O port of the at least one HBA. All network paths are discarded for which the HBA port utilization is greater than the HBA port limit. For each of the remaining paths a network path distance is determined. All I/O network paths for which the network path distance is greater than the path distance limit are discarded. Then for each of the remaining paths a fabric utilization is determined. All I/O network paths for which the fabric utilization is greater than the fabric utilization limit are discarded and the I/O network path is determined from the remaining network paths.10-09-2008
20130219094Commonality of Memory Island Interface and Structure - The functional circuitry of a network flow processor is partitioned into a number of rectangular islands. The islands are disposed in rows. A configurable mesh data bus extends through the islands. A first island includes a first memory and a first data bus interface. A second island includes a processor, a second memory, and a second data bus interface. The processor can issue a command for a target memory to do an action. If a field in the command has a first value then the target memory is the first memory, whereas if the field has a second value then the target memory is in the second memory. The command format is the same, regardless of whether the target memory is local or remote. If the target memory is remote, then a data bus bridge adds destination information before putting the command onto the global configurable mesh data bus.08-22-2013
20080263246System and Method for Balancing PCI-Express Bandwidth - A system and method for balancing bus bandwidth across a plurality of PCI-Express (PCIe) endpoints are provided. Firmware automatically operates in concert with established data structures to set operational parameters of the PCIe endpoints so as to maximize usage of the available bandwidth of a front-side bus while minimizing isochronous issues and the likelihood that the performance of the PCIe endpoints cannot be guaranteed. A first table data structure comprises various combinations of operational parameter settings for controlling bandwidth usage of each of the endpoints of the data processing system. A second table data structure contains a listing of the endpoints that the data processing system supports with their associated minimum data rates, priorities, and whether the endpoints have isochronous requirements. A setting of the desired bandwidth balancing level is used along with these data structures to determine how to adjust the operating parameters of the PCIe endpoints.10-23-2008
20090265493Efficient Architecture for Interfacing Redundant Devices to a Distributed Control System - A system and method for interfacing redundant devices to a distributed control system, includes a first and second redundant field bus modules communicably coupled to the distributed control system and to one another via Ethernet switches. A pair of redundant field devices are coupled to the Ethernet switches, one FD having a floating IP address. The FBMs adopt respective roles as master FBM and tracker FBM, so that the master FBM is configured to capture data from the one FD using the floating IP address, and to pass any data changes periodically to the tracker FBM, through the Ethernet switches. The master FBM is configured to point to the other field device in the event the other field device has assumed the floating IP address. The FBMs are configured to switch roles in the event communication is disrupted between the master FBM and the FD having the floating IP address.10-22-2009
20080282006Latency Hiding for a Memory Management Unit Page Table Lookup - In certain systems, local request's require corresponding associated information to be present in order to be serviced. A local memory stores some of the associated information. There is latency associated with retrieval of associated information that is not immediately available. Logic operates for each local request to access the local memory to ascertain whether the associated information corresponding to the local request, is present If the associated information is present, a request is placed in an output request queue to service the local request If the associated information is not present, a request is placed on a bypass path to retrieve the associated information. Requests issue from the bypass path with priority over requests from the output request queue. Useful work is thereby done during the latency of associated information retrieval. The arrangement is useful in a TLB in an MMU.11-13-2008
20080276021Data transfer control apparatus - A data transfer control apparatus has a plurality of bus slaves connected to a bus master via a bus interface unit for RAM connected to the bus master via a master bus, and a transfer bus which connects the first bus slave and plural second bus slaves in the plurality of bus slaves. When an instruction to execute data transfer via the transfer bus is given by a transfer instruction signal, data transfer between one second bus slave selected from the plural second bus slaves and the first bus slave via the transfer bus is carried out in response to a control signal contained in a control signal bus on a slave bus for RAM.11-06-2008
20110208885DATA BUS CONTROL METHOD AND APPARATUS - A method and apparatus to prevent I2C device from hanging the I2C data bus and thus stopping other devices in the system from transmitting or receiving data is presented. A logic transition detector detects a logic transition at the output data line of an I2C device and triggers a timer. The timer starts counting after it is triggered. A reset module resets the I2C interface module in the I2C device after the timer counts to a specified period of time. The timer is reset when the logic transition detector detects another logic transition at the output data line of the I2C device.08-25-2011
20090024775Dual core architecture of a control module of an engine - A control system for a control module of a vehicle includes a first integrated circuit (IC) core of a primary processor that generates a first control signal using a central processing unit (CPU). A second IC core of the primary processor generates a second control signal using a second CPU and generates a remedial control signal based on the first control signal and the second control signal.01-22-2009
20110225332Data transmission device and control method - The present invention provides a data transmission device with high speed serial transmission interfaces and control method thereof, and includes a control unit, at least one first storage device connected to the control unit and at least one second storage device, at least one switching device, which is used to switch data transmission lines; each of the switching devices being connected to the control unit, the second storage device and a computer. Accordingly, the switching devices enable the storage devices to connect to the computer to implement data transmission, or the switching devices switch connection to form an independently operable data transmission control system to enable implementing data transmission between the storage devices. Moreover, an automatic detection mode and a manual mode can be used to control connection to the computer or enable independent operation of the data transmission device.09-15-2011
20110145455Information processing apparatus and method for controlling information processing apparatus - According to an aspect of the embodiment, a system control apparatus includes a control signal transmitting unit which transmits a control signal to control circuits via first signal line. The control signal includes a command for performing a control setting on other control circuits other than own control circuit or to all control circuits. Each control circuit includes a signal receiving unit which receives the control signal transmitted from the control signal transmitting unit via the first signal line, a signal transfer unit which transfers the command included in the received control signal via second signal lines to the control circuit, and a control setting unit which performs the control setting on the own control circuit according to the command included in the received control signal or a command transferred from the other control circuits other than the own control circuit.06-16-2011
20110231587Masked Register Write Method and Apparatus - A hardware device register is written without transferring the register content from the hardware device to a host device over an interface bus for modification. The hardware device receives an address identifying the target register included in the hardware device and bit information associated with a write operation involving the target register from the host device over the interface bus. The address is stored in a first register included in the hardware device and dedicated for supporting write operations. The bit information is stored in a second register included in the hardware device and also dedicated for supporting write operations. The target register is accessed based on the address stored in the first register dedicated for supporting write operations and one or more bits of the target register are written based on the bit information without first transferring the register content to the host device over the interface bus.09-22-2011
20120079149METHOD FOR VEHICLE INTERNETWORKS - Vehicle internetworks provide for communications among diverse electronic devices within a vehicle, and for communications among these devices and networks external to the vehicle. The vehicle internetwork comprises specific devices, software, and protocols, and provides for security for essential vehicle functions and data communications, ease of integration of new devices and services to the vehicle internetwork, and ease of addition of services linking the vehicle to external networks such as the Internet.03-29-2012
20120079148REORDERING ARRANGEMENT - An embodiment of a network-on-chip is provided. The network-on-chip includes a plurality of sources of requests and a plurality of destinations for requests. The plurality of destinations are configured to provide respective responses to respective requests. The network-on-chip further includes an interconnect for routing said requests and respective responses to said requests to and from the plurality of sources and at least one transaction reordering arrangement. The transaction reordering arrangement is configured to reorder said responses such that said responses are provided to a respective source in an order which corresponds to an order in which the requests are issued by said respective source. A respective transaction reordering arrangement is associated with a respective source.03-29-2012
20120079147BUS CONTROL DEVICE - A bus controller includes: a data receiving section for receiving output status information from other bus controllers on transmission routes available; a route load detecting section for calculating uniformity of distribution index indicating the degree of non-uniformity in transmission flow rate between the routes based on the output status information; a routing section for determining transmission routes, of which the transmission flow rates have been adjusted by reference to the index; a packet assembling section for generating a packet; a data output section for outputting the packet through one of output ports; a header analyzing section for determining which output port is connected to a transmission route chosen by reference to information about the packet receiving end; and a data output section for outputting the packet through the output port.03-29-2012
20090254687ELECTRONIC DEVICE FOR CONTENTION DETECTION OF BIDIRECTIONAL BUS AND RELATED METHOD - An electronic device of detecting contention of a bidirectional bus for avoiding failing to drive a bidirectional bus due to bus contention includes: an output terminal, an input terminal and a data output unit, a timing comparing controller and a comparing unit. The output terminal is coupled to the bidirectional bus and used for outputting a data output signal to the bidirectional bus. The input terminal is coupled to the output terminal and the bidirectional bus and used for receiving a data reception signal from the bidirectional bus. The data output unit is used for providing the data output signal. The timing comparing controller is used for generating a timing comparison signal according to the data output signal. The comparing unit is used for comparing the data reception signal with the data output signal according to the timing comparison signal to determine a contention state of the bidirectional bus.10-08-2009
20090240857Method and device for controlling a bus system and a corresponding bus system - Method for controlling a bus system having at least two users, a first user repeatedly transmitting a reference message in at least one predeterminable time interval over the bus system, the reference message being triggered by time trigger information when the time information reaches a time mark assigned to the trigger information, wherein the time mark is altered at least once in such a way that when the time information reaches the altered time mark, time shifting of the trigger information occurs.09-24-2009
20090254686MEMORY SHARING THROUGH A PLURALITY OF ROUTES - A method for sharing a memory through a plurality of routes and a device thereof are disclosed. The digital processing apparatus in accordance with an embodiment of the present invention comprises a main processor, an application processor controlled by the main processor and coupled to the main processor through one connection bus and a memory having a plurality of ports, each of which is coupled to the application processor through an independent memory bus. With the present invention, the process time for processing a high-performance, high-resolution image can be minimized, and the loss in process efficiency of the application processor can be minimized.10-08-2009
20100185800COMMUNICATION PROTOCOL FOR SHARING MEMORY RESOURCES BETWEEN COMPONENTS OF A DEVICE - In a device, such as a cell phone, memory resource sharing is enabled between components, such as integrated circuits, each of which has memory resources. This may be accomplished by providing an interconnect between the components and constructing transaction units which are sent over the interconnect to initiate memory access operations. The approach may also be used to allow for a degree of communication between device components.07-22-2010
20100174838METHOD AND APPARATUS FOR EMPLOYING A SECOND BUS CONTROLLER ON A DATA BUS HAVING A FIRST BUS CONTROLLER - A method for employing a second bus controller on a data bus having a first bus controller including: (a) recording appearances of predetermined character groups on the data bus; (b) noting patterns of the appearances preceding a qualifying quiet period on the data bus; a qualifying quiet period being a time interval having a duration greater than a predetermined duration with no traffic on the data bus; (c) employing the patterns to determine probability of occurrence of a qualifying quiet period following at least one pattern; and (d) permitting the second bus controller to control operation of the data bus during a respective qualifying quiet period when the probability of occurrence for the respective qualifying quiet period is greater than a predetermined value.07-08-2010
20090089467BUS COMMUNICATION EMULATION - Provided are a method, system, and program for initializing a processor of a computer system, to enumerate a remote bus and remote devices coupled to the remote bus, as operating components of the computer system. In another embodiment, a controller stores a message containing a directive in a memory shared by a processor of a computer system and the controller which may be operated independently of the state of said processor and said operating system. The processor may read a message stored in the shared memory by the controller and process the message. In addition, the processor may store a message intended for the controller to provide, for example, status information to be forwarded to another computer system. Other embodiments are described and claimed.04-02-2009
20100146171MEMORY SYSTEM HAVING A PLURALITY OF TYPES OF MEMORY CHIPS AND A MEMORY CONTROLLER FOR CONTROLLING THE MEMORY CHIPS - A memory controller converts controller output signals output from a controller into memory input signals according to the operation specifications of memory chips to operate, and outputs the resultant to the memory chips through a common bus. The memory controller also receives memory output signals output from the memory chips through the common bus, and converts the received signals into controller input signals receivable to the controller. This allows the single memory controller to access the plurality of types of memory chips. As a result, the memory controller can be reduced in chip size, lowering the cost of the memory system.06-10-2010
20090113096HIGH BANDWIDTH SPLIT BUS - A system includes a first bus segment and a second bus segment. The first bus segment is operatively coupled to one or more first bus agents, where the first bus agents are configured for writing messages to the first bus segment and reading messages from the first bus segment and the second bus segment, which is separate from the first bus segment, is operatively coupled to one or more second bus agents. The first bus agents are configured for writing messages to the first bus segment and reading messages from the first bus segment. The system also includes first electrical circuitry operably coupled to the first bus segment and the second bus segment and configured to read messages written on the first bus segment and to write the messages onto the second bus segment and second electrical circuitry operably coupled to the first bus segment and the second bus segment and configured to read messages written on the second bus segment and to write the messages onto the first bus segment.04-30-2009
20110113170INTERFACE - An interface, for communication between an internal device and an external device, includes two bus lines of a bus for bidirectional data transfer and at least a first control line, by means of which a control signal can be transferred from the external device to the internal device.05-12-2011
20090049216Dynamically allocating lanes to a plurality of PCI express connectors - Method, apparatus, and computer program products for dynamically allocating lanes to a plurality of PCI Express connectors are disclosed that include identifying whether a PCI Express device is installed into each PCI Express connector, and assigning a portion of the lanes to each PCI Express connector having a PCI Express device installed into the PCI Express connector. Dynamically allocating lanes to a plurality of PCI Express connectors may also include identifying a device type for each PCI Express device installed into the plurality of PCI Express connectors. Dynamically allocating lanes to a plurality of PCI Express connectors may also include creating allocation rules that specify the allocation of lanes to the plurality of PCI Express connectors. Dynamically allocating lanes to a plurality of PCI Express connectors may also include receiving user allocation preferences that specify the allocation of lanes to the plurality of PCI Express connectors.02-19-2009
20080228974Design Structure for a Livelock Resolution Circuit - A design structure for a livelock resolution circuit is provided. When a bus unit detects a timeout condition, or potential timeout condition, the bus unit activates a livelock resolution request signal. A livelock resolution unit receives livelock resolution requests from the bus units and signals an attention to a control processor. The control processor performs actions to attempt to resolve the livelock condition. Once a bus unit that issued a livelock resolution request has managed to successfully issue its command, it deactivates its livelock resolution request. If all livelock resolution request signals are deactivated, then the control processor instructs the bus and all bus units to resume normal activity. On the other hand, if the control processor determines that a predetermined amount of time passes without any progress being made, it determines that a hang condition has occurred.09-18-2008
20090070505Method For Exchanging Information Between Devices Connected Via A Communication Link - A method for exchanging information between a first device and a second device connected via a communication link, the communication link supporting a query command and at least a further command, where each command includes a specific command code is described. The method comprises transmitting a query command code and data from the first device via the communication link, the data identifying a specific command, receiving the query command code and the data at the second device, transmitting reply data from the second device via the communication link, the reply data including at least a first segment and a second segment, and receiving the reply data at the first device, wherein the first segment includes information whether the specific command is supported, wherein, if the specific command is not supported, the second segment includes information identifying an alternative command to the specific command.03-12-2009
20100306430BUS CONTROL SYSTEM AND SEMICONDUCTOR INTEGRATED CIRCUIT - A bus control circuit includes a first bus to which a first circuit is connected, a second bus to which a second circuit is connected and a control circuit that transfers data between the first circuit and the second circuit, wherein the control circuit monitors completion of the processing of an access request that is resident in the control circuit.12-02-2010
20110035522Software-Defined Radio Using Multi-Core Processor - A radio control board passes a plurality of digital samples between a memory of a computing device and a radio frequency (RF) transceiver coupled to a system bus of the computing device. Processing of the digital samples is carried out one or more cores of a multi-core processor to implement a software-defined radio.02-10-2011
20100262734WIRELESS USB DEVICE FOR NETWORKING WITH MULTIPLE WIRELESS USB HOSTS AND METHOD THEREOF - Provided are a Wireless USB device for networking with multiple Wireless USB hosts and a method thereof. The Wireless USB device includes a selection unit for selecting a device management unit which corresponds to a Wireless USB host based on MAS location information in the MAS allocation list, and relaying MMC frames to the selected device management unit; device management units for each Wireless USB host for analyzing MMC frames relayed from the selection unit, and performing a command defined in the MMC frames; and a common information storage for storing common information maintained and managed commonly to all Wireless USB hosts.10-14-2010
20090216926APPARATUS TO IMPROVE BANDWIDTH FOR CIRCUITS HAVING MULTIPLE MEMORY CONTROLLERS - An apparatus for improving bandwidth for circuits having a plurality of memory controllers employing a first memory controller, a second memory controller, a first busy read output signal circuit, a first busy write output signal circuit, a second busy read output signal circuit, and a second busy write output signal circuit. The first busy read output signal indicates when the first memory controller releases the address bus for a next external access subsequent to a read access to the data bus by the first memory controller. The first busy write output signal indicates when the first memory controller releases the data bus for a next external access subsequent to a write access to the data bus by the first memory controller. The second busy read output signal indicates when the second memory controller releases the address bus for a next external access subsequent to a read access to the data bus by the second memory controller. The second busy write output signal indicates when the second memory controller releases the data bus for a next external access subsequent to a write access to the data bus by the second memory controller.08-27-2009
20110179206BUS CONTROLLER, BUS COMMUNICATION SYSTEM, AND BUS CONTROL METHOD - It is an object to prevent a command-issuing interval from being fixed and then avoid a situation where a target always returns a retry by varying a timing of a command-issuing request (i.e., a request signal) from each initiator, even if a plurality of initiators simultaneously or alternately make a plurality of command-issuing requests (i.e., send request signals). Based on predetermined priorities, a bus control unit 07-21-2011
20110016242DATA PROCESSING APPARATUS AND DATA PROCESSING METHOD - A data processing apparatus includes a data input unit configured to input data to a ring bus, a data output unit configured to output the data input by the input unit, a first communication processing unit configured to control input of the data by the data input unit to the ring bus and to control output of the data by the data output unit, a plurality of data processing units configured to perform data processing, a plurality of second communication processing units configured to control transmission and reception of the data between the plurality of data processing units and the ring bus, and a control unit configured to independently perform initialization on the plurality of second communication processing units or the plurality of data processing units.01-20-2011
20100005207INTEGRATED CIRCUIT DEVICE WITH MULTIPLE COMMUNICATION MODES AND OPERATING METHOD THEREOF - An integrated circuit device having multiple communication modes is provided. The integrated circuit device includes a transceiver coupled to first and second data lines. The integrated circuit device further includes a voltage control circuit. The voltage control circuit determines whether or not an external device is connected to the integrated circuit device. In the case where the external device is connected to the integrated circuit device, the voltage control circuit controls the voltage of the first data line so as to cause the external device to not recognize the integrated circuit device for a predetermined time.01-07-2010
20110153888CASCADE-ABLE SERIAL BUS DEVICE WITH CLOCK AND MANAGEMENT AND CASCADE METHODS USING THE SAME - A cascade-able serial bus device for coupling between a host device and another serial bus device is disclosed. The host device includes a serial bus interface. The serial bus device includes a first connection interface, a second connection interface and a bypassing module. The first connection interface is coupled to the serial bus interface of the host device. The second connection interface is coupled to the second serial bus device. The bypassing module is coupled to a chip select (CS) signal line of the serial bus interface and the second connection interface for selectively bypassing or non-bypassing the CS signal to the second serial bus device.06-23-2011
20090138640Data Processing System, Method and Interconnect Fabric Supporting Concurrent Operations of Varying Broadcast Scope - A data processing system includes a first processing node and a second processing node coupled by an interconnect fabric. The first processing node includes a plurality of first processing units coupled to each other for communication, and the second processing node includes a plurality of second processing units coupled to each other for communication. A first processing unit in the first processing node includes interconnect logic that processes a plurality of concurrently pending broadcast operations of differing broadcast scope. At least a first of the plurality of concurrently pending broadcast operations has a first scope limited to the first processing node, and at least a second of the plurality of concurrently pending broadcast operations has a second scope including the first processing node and the second processing node.05-28-2009
20120203945SYSTEM AND METHOD FOR INITIALIZING A MEMORY SYSTEM, AND MEMORY DEVICE AND PROCESSOR-BASED SYSTEM USING SAME - Systems, controllers, and methods are disclosed, such as an initialization system including a controller configured to receive patterns of read data coupled from a memory device through a plurality of read data lanes. The controller is operable to detect lane-to-lane skew in the patterns of read data. The controller then adjusts the manner in which the read data received through the read data lanes during normal operation are divided into frames. The controller can also couple patterns of command/address bits to the memory device through a plurality of command/address lanes. The memory device can send the received command/address bits back to the controller through the read data lanes. The controller is operable to detect any lane-to-lane skew in the patterns of command/address bits received through the read data lanes to adjust the manner in which the command/address bits coupled through the command/address lanes during normal operation are divided into frames.08-09-2012
20120203944Systems and Methods for Providing Access to Financial Trading Services - A system and method to allow service consumers to access financial services deployed using various integration technologies with optimal latency through a technique of data-driven bus arbitration and the use of on-demand delivered bus integration plug-in components.08-09-2012
20100332707Bi-directional handshake for advanced reliabilty availability and serviceability - In some embodiments a signal is sent from a Basic Input/Output System to a device to indicate that the Basic Input/Output System needs to obtain control of shared resources. A signal is sent from the device to the Basic Input/Output System that indicates that the Basic Input/Output System can now control the shared resources. Other embodiments are described and claimed.12-30-2010
20100293312Network Communications Processor Architecture - Described embodiments provide a system having a plurality of processor cores and common memory in direct communication with the cores. A source processing core communicates with a task destination core by generating a task message for the task destination core. The task source core transmits the task message directly to a receiving processing core adjacent to the task source core. If the receiving processing core is not the task destination core, the receiving processing core passes the task message unchanged to a processing core adjacent the receiving processing core. If the receiving processing core is the task destination core, the task destination core processes the message.11-18-2010
20110125944Synchronising activities of various components in a distributed system - An initiator device for issuing transaction requests to a recipient device via an interconnect is disclosed. The initiator device comprises: at least one port for receiving requests from and issuing requests to said interconnect; a barrier generator for generating barrier transaction requests, the barrier transaction requests indicating to the interconnect that an ordering of at least some transaction requests within a stream of transaction requests passing through the interconnect should be maintained by not allowing reordering of at least some of the transaction requests that occur before the barrier transaction request in the stream of transaction requests with respect to the barrier transaction request; wherein in response to receipt of a synchronise request querying progress of at least a subset of transaction requests, the initiator device is responsive to action any pending transaction requests within the at least a subset of transaction request and to generate a barrier transaction request at the barrier generator and to issue the barrier transaction request to the interconnect via the at least one port, and in response to receiving a response to the barrier transaction request to issue an acknowledge signal as a response to the synchronise request.05-26-2011
20100332708Information Processing Apparatus - According to one embodiment, an information processing apparatus including a suspension/resume function includes a bus controller which controls a bus capable of transmitting data at a first transmission speed or a second transmission speed lower than the first transmission speed, a storage module which stores setting information for limiting a data transmission speed of the bus to the second transmission speed, an initializing module which initializes the bus controller so as to limit the data transmission speed of the bus to the second transmission speed if the setting information is stored in the storage module when the apparatus is activated or returned from a suspended state, and a controller which stores the setting information into the storage module and makes the apparatus transit to the suspended state and return from the suspended state, when the transmission speed of the bus is limited to the second transmission speed.12-30-2010
20100180056BUS ACCESS CONTROL APPARATUS AND METHOD - An apparatus that controls access by multiple IP cores to a bus is provided. The apparatus includes a main controller and multiple sub controllers, each of the sub controllers being associated with each IP cores. The main controller switches connection between each of the IP cores and the bus according to a schedule predetermined based on predetermined time slices. Each of the sub controllers controls access by the IP core to the bus according to a schedule under the control of the main controller. Embodiments of the present invention provide method and apparatus to ensure real-time accessibility to a bus shared by multiple IP cores and improve bus use efficiency.07-15-2010
20110258352Inline PCI-IOV Adapter - A system for enabling input/out virtualization for a device is disclosed. In one embodiment, the system includes a plurality of host CPUs; a multi-root switch connected to each of the plurality of host CPUs via respective buses; and an inline PCI virtualizing device connected to the multi-root switch via a front-side bus and the device via a back-side bus, the inline PCI virtualizing device including a plurality sets of registers, each of the plurality sets of registers accessible by a corresponding host CPU of the plurality of host CPUs and implementing functionalities of the device.10-20-2011
20110138089DATA PROCESSING SYSTEM HAVING A CHANNEL ADAPTER SHARED BY MULTIPLE OPERATING SYSTEMS - A data processing system comprising a processing unit on which a control program runs, a plurality of operating systems (OS's) configured to run under control of said control program, a Peripheral Component Interchange (PCI) bus coupled to the processing unit, and a channel adaptor for data transmission/reception, wherein: the channel adaptor is coupled to the PCI bus on a PCI bus side of the channel adapter, and the channel adapter includes only one connecting port on an input/output (I/O) side of the channel adapter; an input/output process is executed between each OS and said channel adaptor by using input/output process control data specifying input/output (I/O) data each having an identifier; configuration information is provided, defining the identifier of said input/output process control data which is usable by each respective OS; said channel adaptor can process a plurality of input/output process control data; and each OS uses said input/output process control data corresponding to a usable identifier and defined in said configuration information, and thereby a plurality of OS's control input/output process control data having different identifiers relative to said channel adaptor to execute the input/output process.06-09-2011
20100023662BUS MASTERING METHOD - A mastering method of a bus includes the following steps: receiving a command; determining if the command is a bus master command to generate a determined result; outputting at least one break event to switch a processor from a non-snoop state into a snoop state according to the determined result; and outputting at least one bus master request to access the bus; wherein the break event is ahead of the bus master request that corresponds to the break event.01-28-2010
20100017551BUS ACCESS MODERATION SYSTEM - A method, programmed medium and system are provided in which system bus traffic is moderated with real-time data. The Operating System (OS) is enabled to get information from the firmware (FW) to determine if a resource threshold has been reached. This is accomplished by generating an interrupt to flag the OS when a bus request retry rate has reached a predetermined number. The system firmware plays an integral role in this mechanism, and should be interpreted as a general term which could also include a hypervisor technology. The system firmware will report the bus request retry rate to the operating system by way of, for example, a firmware-generated interrupt. The OS may have something similar to a kernel daemon/service running to intercept the interrupt notice. In the simplest case, the daemon/service will determine if the threshold has been met based on the feedback from the firmware. If so, it will generate a system call that will moderate traffic with an operating system tunable. In one example, the number of simultaneous multithreading (SMT) threads per core will be reduced using a system call. This effectively throttles back the amount of logical threads per core and effectively alleviates the bus request saturation.01-21-2010
20080320191SYSTEM AND METHOD FOR PROVIDING A CONFIGURABLE COMMAND SEQUENCE FOR A MEMORY INTERFACE DEVICE - A system and method for providing a configurable command sequence for a memory interface device (MID). The system includes a MID intended for use in a cascade interconnect system and in communication with one or more memory devices. The MID includes a first connection to a high speed bus operating at a first data rate, a second connection to the high speed bus, an alternate communication means and logic. The first connection to the high speed bus includes receiver circuitry operating at the first data rate. The alternate communication means operates at a second data rate that is slower than the first data rate. The logic facilitates receiving commands via the first connection from the high speed bus operating at the first data rate and using a first command sequence. The logic also facilitates receiving the commands via the alternate communication means using a second command sequence which differs from the first command sequence in the speed in which the commands are transferred. The logic further facilitates processing the commands if the commands are directed to the MID and redriving the commands via the second connection onto the high speed bus.12-25-2008
20090172225Method and apparatus for providing overlapping defer phase responses - A multiprocessor system in which a defer phase response method is utilized that allows for a deferring agent to interrupt the normal flow of bus transactions once it gains control of system interface bus. The deferring agent is allowed to look ahead to determine if a continuous stream of defer phase cycles are pending transfer. If pending, the deferring agent will not release control of the bus until the pending defer phase cycles have been depleted. The look ahead feature allows expedited return of higher priority defer data, while minimizing bus dead cycles caused by interleaving defer phase cycles with normal bus traffic.07-02-2009
20120151107MODIFYING SYSTEM ROUTING INFORMATION IN LINK BASED SYSTEMS - Methods and apparatus to improve modification of system routing information in link based systems are described. In one embodiment, entries in a first table (storing data corresponding to routing paths between a plurality of components prior to a hot-plug event) and a second table (storing data corresponding to routing paths between the plurality of components after a hot-plug event) may be compared to determine which corresponding routing registers are to be modified in response to the hot-plug event. Other embodiments are also disclosed.06-14-2012
20080209094Bus-based communication system - A communications bus operates using transition coding, for example NRZI coding, with transition-dominant signalling. That is, when the signal takes a first binary value, binary “1”, the component drives the bus line to its opposite state, and, when the signal takes a second binary value, binary “0”, the component does not actively drive the bus line. During arbitration, each arbitrating component writes a unique arbitrand onto the bus, and arbitration is lost by each component that writes a binary “0” when at least one other component writes a binary “1”. The components preferably do not use transition-dominant signalling when transmitting data payloads. For such traffic they actively drive the binary “0”s as well as binary “1”s.08-28-2008
20120047298INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, AND STORAGE MEDIUM - An information processing apparatus which circulates a packet in one way among a plurality of modules connected in a ring shape, and transmits/receives the packet, each of the plurality of modules comprising a determination unit to determine whether data contained in the packet is processing-data to be processed by a processing-module of the module or configuration data for changing settings of the processing-module by an internally contained command, a discrimination unit to discriminate, when the data is determined to be the configuration data, a command type indicating the type of command contained within the configuration data as a write-mode in which the configuration data is written in the module, a read-mode in which currently set configuration data held in the module is read out, or an exchange-mode in which the currently set configuration data is read out, and then the configuration data is written, a decision unit to decide a packet transmission interval based on the command type.02-23-2012
20120210028SERVICE SCHEDULING SYSTEM AND METHOD, AND CONTROL DEVICE - The disclosure discloses a service scheduling system, a service scheduling method, and a control device; the control device is added to the service scheduling system, and the control device obtains connection status information of each bus port in the service scheduling system respectively, updates a first corresponding relationship between transfer units in a service scheduling device and transfer units in service processing devices according to the obtained connection status information of the bus port when judging that changed connection status information is obtained, and sends the updated first corresponding relationship to the service scheduling device to enable the service scheduling device to schedule services to be scheduled according to the updated first corresponding relationship. By means of the technical solutions provided by the disclosure, the problem presenting in the prior art that modifying the software codes when the corresponding relationship among the transfer units is updated results in the poorer expansibility of the service scheduling system and the lower processing efficiency of the system can be solved.08-16-2012
20110167184ACCESS CONTROL APPARATUS, DATA PROCESSING APPARATUS, ACCESS CONTROL METHOD, AND PROGRAM - An access control apparatus includes: a determination section; and an update section.07-07-2011
20110167183Minimizing Interconnections In A Multi-Shelf Switching System - In certain embodiments, minimizing interconnections in a multi-shelf switching system includes receiving a map describing the switching system, where the switching system comprises shelves and input/output (I/O) points. The map is transformed to yield a graph comprising nodes and edges. A node represents an I/O point, and a node weight represents a number of interface cards of the I/O point represented by the node. An edge between a node pair represents traffic demand between the I/O points represented by the node pair, and an edge weight represents the amount of the traffic demand represented by the edge. The graph is partitioned to yield a groups that minimize interconnection traffic among the shelves, where each group represents a shelf of the multi-shelf switching system.07-07-2011
20120059961SYSTEM AND METHOD FOR SHARING MEMORY - A system and method for interfacing multiple SoCs (System on a Chip) to a single, shared memory device are provided. The system and method of the present disclosure provides for controlling the downloading of operating code to two or more SoC controller circuits sharing a memory containing the operating code and a common communications bus, where each controller is a master controller of the communications bus in normal operation. The system and method involves sequentially controlling access of each of the controller circuits to the communications bus to allow each device to separately download the common operating code. The system and method utilize a separate initializing circuit or device along with chaining the controllers together in a series such that each controller be held in a reset state to prevent communications bus access until the previous controller in the chain has completed its code download.03-08-2012
20120179847Method and System for Implementing Bus Operations with Precise Timing - The present disclosure describes a system and method for implementing bus operations with precise timing. The system includes a trigger descriptor register for a bus operation. The trigger descriptor register includes a bus definition field, which further includes data and address fields for providing data and address information for the bus operation. The trigger descriptor register may also include a holdoff time field to store a time value and includes an event select field to select a trigger for the bus operation. A processor configures the trigger descriptor register. A counter may count based on a time period such that at the end of the counting, the bus operation is performed based on the data and address fields. The time period is derived from one or more of the holdoff field or an external timer. The disclosed method and system employ hardware assist for maintaining precise timing while performing bus operations.07-12-2012
20110066779DATA PROCESSING SYSTEM, DATA PROCESSING METHOD, AND APPARATUS - A data processing system may include a first data path and a second data path. A set of components may include a system component and a partner component, each having a communication interface for communicating data. The components are operable in a synchronized mode and a non-synchronized mode with respect to each other. The set may further include a configuration control system connected to the system component and the partner component, for controlling the set to be in a synchronized mode configuration or a non-synchronized mode configuration. The configuration control system may include a first path selector module connecting the communication interface of the system component to the first data path and the second data path and a partner path selector module connecting the communication interface of the partner component to the first data path and the second data path. The path selector modules may be arranged to enable, depending on the configuration, communication of data to the respective component via one or more selected data path, selected from the first data path and the second data path, and to inhibit communication via the not selected data paths.03-17-2011
20120317321PROCESSOR BRIDGING IN HETEROGENEOUS COMPUTER SYSTEM - A bridge logic device for a heterogeneous computer system that has at least one performance processor, a processor supporting logic supporting the at least one performance processor to execute tasks of the software, and a hypervisor processor consuming less power than the at least one performance processor is disclosed. The bridge logic device comprises a hypervisor operation logic that maintains status of the system under the at least one performance processor; a processor language translator logic that translates between processor languages of the at least one performance and the hypervisor processors; and a high-speed bus switch that has first, second and third ports for relaying data across any two of the three ports bidirectionally. The switch is connected to the at least one performance processor, the hypervisor processor via the processor language translator logic, and to the processor supporting logic respectively at the first, second, and third port.12-13-2012
20120221753METHOD AND DEVICE FOR WAKING UP USERS IN A BUS SYSTEM AND CORRESPONDING USERS - An apparatus for waking up users of a CAN bus system, a sensing element being provided which senses at least one predefined signal property of the signals transmitted on the bus system and the further wakeup operation being initiated as a function of the behavior of the at least one sensed signal property, wherein at least two profiles, patterns, or sequences of one of the at least one signal property are defined, one profile or pattern or sequence being used for waking up a group of users, and a second profile or a second pattern or a second sequence being used for individually waking up a user.08-30-2012
20120173780MULTI-CORE DATA PROCESSOR - A multi-core LSI with improved stability of operation. The multi-core LSI includes a plurality of CPUs coupled to a first shared bus, one or more modules coupled to a second shared bus, a shared bus controller coupled between the first shared bus and the second shared bus for arbitrating access to the module(s) by the CPUs, and a system controller that monitors whether or not a response signal to an access request signal of the CPUs is output from a module to be accessed, wherein the system controller outputs a pseudo response signal to the first shared bus via the shared bus controller to terminate access by the CPU while accessing if the response signal is not output from the module to be accessed after the access request signal is output to the second shared bus from the shared bus controller and before a predetermined time elapses.07-05-2012
20100011138DESIGN STRUCTURE FOR AUTOMATED MEANS FOR DETERMINING INTERNET ACCESS ON A SYSTEM ON A CHIP - A method for determining Internet access by an autonomous electronic circuit on a system on a chip integrated circuit includes a system bus which is snooped to determine if Internet activity is occurring on the system bus. Local header information is collected when the snooping has determined that Internet activity is occurring on the system bus. A packet including the local header information is created. Internet access is requested with the created packet.01-14-2010
20090019201IDENTIFICATION OF EQUIPMENT LOCATION IN DATA CENTER - Techniques are disclosed for identifying the locations of equipment in computing environments such as data centers. For example, a method of identifying a location of at least one computing device in a computing environment, including a plurality of computing devices, includes the following steps. A first representation of temperature conditions associated with the plurality of computing devices is obtained while the at least one computing device is in a first mode. The at least one computing device is placed into a second mode. A second representation of temperature conditions associated with the plurality of computing devices is obtained while the at least one computing device is in the second mode. The location of the at least one computing system is determined using the first representation and the second representation. The first mode may be one of a normal operating mode and an idle mode, and the second mode may be the other of the normal operating mode and the idle mode.01-15-2009
20080301343DEVICE FOR CONTROLLING COMMUNICATION BETWEEN A MODULE AND A TRANSMISSION BUS - The invention relates to a device for controlling communication between a module (12-04-2008
20110004713INFORMATION TRANSMISSION SYSTEM, INFORMATION TRANSMISSION DEVICE, INFORMATION TRANSMISSION METHOD AND A COMPUTER READABLE MEDIUM STORING A PROGRAM FOR INFORMATION TRANSMISSION - The present invention provides an information transmission system including: a transmission path that transmits information in serial; a first information transmission device including, a transmitting section that transmits the information in the transmission path at a predetermined transmission speed, and a controller that controls the transmitting section to transmit predetermined first information in the transmission path when establishing communication, the first information including a same value in successive plurality of bits; and a second information transmission device including, a receiving section that receives the information transmitted via the transmission path, and a communication establishing section that establishes the communication based on the first information, when the receiving section receives the first information.01-06-2011
20120239840BUS CONTROL FOR A DOMESTIC APPLIANCE - A domestic appliance (09-20-2012
20110283028IMPLEMENTING NETWORK MANAGER QUARANTINE MODE - A method and circuit for implementing a network manager quarantine mode in an interconnect system, and a design structure on which the subject circuit resides are provided. A respective network manager on a source interconnect chip and a destination interconnect chip sends end-to-end (ETE) heartbeats on each path between the source and destination interconnect chips. Each network manager maintains a heartbeat table with counters to track each path to each destination interconnect chip. When a first network manager of a first interconnect chip detects a change from at least one valid path to no working paths for a second interconnect chip of the interconnect chips, the quarantine mode is established for a programmable quarantine time interval and all paths are prevented from advertising good heartbeats during the quarantine time interval.11-17-2011
20110289247Autonomous positional addressing in stacked multi-board systems - A method includes receiving a first address over an address bus at a first module, modifying the first address to generate a second address, and transmitting the second address over the address bus to a second module. The method also includes determining at the first module if at least one of the first and second addresses has a specified value. Modifying the first address could include incrementing or decrementing the first address to generate the second address. Determining if at least one of the first and second addresses has the specified value could include determining if the first address has a value of zero or a value of 211-24-2011
20110320657CONTROLLING DATA STREAM INTERRUPTIONS ON A SHARED INTERFACE - A mechanism for controlling data stream interruptions on a shared bus is provided. A first request is received to transfer data. High priority data components and low priority data components are determined for the first request. The high priority data components are transferred without interruptions. In response to receiving requests when transferring the high priority data components, the received requests are rejected.12-29-2011
20120102247Cabling Between Rack Drawers Using Proximity Connectors And Wiring Filter Masks - An approach is provided in which a number of inter-unit communication connections are detected between a rack-mounted system unit and adjacent rack-mounted system units. The connections are established by a set of electrical contacts selected from a set of available electrical contacts included on surfaces of the rack-mounted system unit. The set of electrical contacts is determined by physical masks inserted between the rack-mounted system unit and adjacent rack-mounted system units. A configuration of rack-mounted system units is identified including the rack-mounted system unit and the adjacent system units rack based on an arrangement of the inter-unit communication connections.04-26-2012
20100199006DATA TRANSFER DEVICE AND DATA TRANSFER METHOD - To provide inter-LSI data synchronized transfer with a transfer throughput satisfying a required performance without causing an operation timing difference of the entire system even when a wiring delay between LSIs varies on an evaluation board and an actual device. A master (LSI08-05-2010
20110161537METHOD FOR GENERATING ELECTROMAGNETIC WAVES USING SOFTWARE - Provided is a method of generating electromagnetic waves using software. The method includes setting electromagnetic wave pattern data in consideration of a number of a bus (06-30-2011
20130173831PROTECTING CIRCUIT FOR BASIC INPUT OUTPUT SYSTEM CHIP - A protecting circuit for a basic input output system (BIOS) chip of a computer includes a platform controller hub (PCH), an inverting circuit connected to the PCH, a BIOS socket to connect the BIOS chip, and a controlling circuit connected between the inverting circuit and the BIOS socket. The PCH outputs a first signal or a second signal, and a third signal. The inverting circuit outputs an inverted signal with a level contrary to the first or second signal. The controlling circuit receives the first or second signal and the inverted signal, to output a processing signal to the BIOS socket, thereby controlling write-protection states of the BIOS chip.07-04-2013
20120254490TOUCH SENSOR SYSTEM - A touch sensor system includes buses, a plurality of touch sensor devices disposed on the buses, and an information integrating device that is connected to all the buses and integrates information from the touch sensor device. The touch sensor device includes a sensor unit and a signal processing unit that transmits a sensor data signal generated by processing an analog sensor signal to the information integrating device through the bus. The signal processing unit includes a digital converting unit, a threshold evaluating unit that gives a start permission of the signal process when a sensor value exceeds a preset threshold, an ID adding unit that adds a transmitter identification number to the sensor signal, and a data transmitting unit that outputs the sensor data signal to a signal line of the bus. Fast responses are made possible without increasing the amount of data and host processing load while including many touch sensor elements.10-04-2012
20130103867Method And Apparatus For Reducing Power Consumption In A Memory Bus Interface By Selectively Disabling And Enabling Sense Amplifiers - A technique includes amplifying data signals from a memory bus interface. The amplified data signals are sampled, and the amplifier is selectively disabled in response to the absence of a predetermined operation occurring over the memory bus. In some embodiments of the invention, the amplification may be selectively enabled in response to the beginning of the predetermined operation over the memory bus.04-25-2013
20100287317Source Driver System Having an Integrated Data Bus for Displays - A source driver system includes a scan driver and a data driver. The data driver has a signal controller, a data bus, a connector and a plurality of data driver units. The signal controller is connected with the connector with via the data bus to form a first connection relationship such that the data bus is capable of transmitting control signals from the signal controller to the connector. The connector connects with the data driver units via the data bus to form a second connection relationship such that the data bus is capable of transmitting the control signals from the connector to the corresponding data driver units. In a preferred embodiment, the data bus is further arranged to form a third connection relationship among the data driver units such that the data bus is capable of communicating a serial connection signal among the data driver units.11-11-2010
20130097347SYSTEM AND METHOD OF TRANSMITTING DATA BETWEEN DEVICES CONNECTED VIA A BUS DEFINING A TIME SLOT DURING TRANSMISSION FOR RESPONSIVE OUTPUT INFORMATION FROM BUS DEVICES - Techniques and devices for transmitting data and information via a bus are provided. According to these techniques, data is transmitted in units or frames together with information that is required or useful for one or more of the transmission and the use of the data. If desired, at least some of the units or frames include a time slot within which freely selectable devices can output onto the bus data representing freely selectable information at freely selectable points in time.04-18-2013
20100318705DATA TRANSFER CIRCUIT - A data transfer circuit includes a fetcher which fetches data having L words (L: integer of 2 or more), each word of which has a first bit width. A first divider divides each data of preceding M words (M: integer of less than L), out of the data fetched by the fetcher, into partial data having a second bit width smaller than the first bit width. A holder temporarily holds data having N words (N: integer equivalent to L-M) succeeding to the M words, out of the data fetched by the fetcher. A second divider divides each data of the N words held by the holder, into partial data having the second bit width. An outputter outputs the partial data divided by the first divider and the partial data divided by the second divider in a time-division manner.12-16-2010
20130159574DATA TRANSFERRING APPARATUS AND DATA TRANSFERRING METHOD - A data transferring apparatus includes a receiving unit configured to receive a transfer request containing attribute information that indicates a type of data transfer, a buffer configured to store the transfer requests received by the receiving unit, a storing unit configured to associate the attribute information with a first identifier and store the attribute information, and a sending unit configured to preferentially transmit, out of the plurality of transfer requests stored in the buffer, a transfer request containing attribute information that corresponds to the attribute information stored in the storing unit, wherein the sending unit is configured to transmit the first identifier associated with the attribute information that corresponds to the attribute information contained in the transfer request in place of the attribute information of the transfer request.06-20-2013
20130198426HETEROGENEOUS PARALLEL SYSTEMS FOR ACCELERATING SIMULATIONS BASED ON DISCRETE GRID NUMERICAL METHODS - A system for executing a given scientific code using a suitable finite-volume or finite-element solver for a large dataset represented as a grid, comprising a plurality of equal computing nodes interconnected by node communication means and a parallel computing software package for distributing and controlling the execution in sub-grids among said computing nodes; each computing node comprising at least a CPU-based first processing means and a FPGA-based second processing means interconnected by a bus; said package being configured for the simultaneous execution of at least one first solver process (which is fully executed in a first processing means) and one second solver process (which is fully executed in a second processing means) in each computing node for one sub-grid of said grid and for managing the exchange of boundary data with the solver processes that solve neighbour sub-grids.08-01-2013
20120059960METHOD FOR CONTROLLING A DATA TRANSFER ON A SERIAL TRANSMISSION DATA TRANSFER BUS - Method for controlling a data transfer on a serial transmission data transfer bus by means of a central processing unit and associated system. The method includes various steps, including determining an available bandwidth for a data bus, determining an available computing capacity percentage of the central processing unit, and determining a maximum data rate that a data transfer can be performed on the data bus based on the available bandwidth and the available computing capacity percentage. Furthermore, the method provides that the data transfer rate is controlled to not exceed the maximum data rate.03-08-2012
20130205056APPARATUS AND METHOD FOR TRANSFERRING A DATA SIGNAL PROPAGATED ALONG A BIDIRECTIONAL COMMUNICATION PATH WITHIN A DATA PROCESSING APPARATUS - An apparatus including a first circuit and a second circuit connected in parallel to the bidirectional communication path, and one of the first and second circuits being an active circuit monitoring a value of the data signal on the bidirectional communication path whilst the other of the first and second circuits being a passive circuit that is not monitoring the value of the data signal. The active circuit initially starts in a low gain state, but on detection of a transition by transition detection circuitry, it enters a high gain state where the switch circuitry disconnects the transition detection circuitry from the bidirectional communication path, and the drive circuitry is activated in order to drive the data signal on the bidirectional communication path to the opposite value. Once the data signal has been driven to the opposite value, the active circuit and the passive circuits switch states.08-08-2013

Patent applications in class Bus access regulation

Patent applications in all subclasses Bus access regulation