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System configuring

Subclass of:

710 - Electrical computers and digital data processing systems: input/output

710100000 - INTRASYSTEM CONNECTION (E.G., BUS AND BUS TRANSACTION PROCESSING)

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DocumentTitleDate
20090193162COORDINATED ACTIONS OF KERNEL AND USERSPACE COMPONENTS - A system for and method of coordinating actions of components between userspace and kernel are described. The system comprises a processor; zero or more hardware components coupled with the processor; and a memory coupled with the processor and comprising a set of processor-executable instructions. The instructions comprise a component handling state machine responsive to at least one of a kernel component or a userspace component; and at least one component interface thread in communication with the component handling state machine and configured to interact with at least one of the zero of more hardware components responsive to a signal from the component handling state machine.07-30-2009
20100042765Dynamically Migrating Channels - In one embodiment, the present invention includes a method of determining a relative priority between a first agent and a second agent, and assigning the first agent to a first channel and the second agent to a second channel according to the relative priority. Depending on the currently programmed status of the channels, information stored in at least one of the channels may be dynamically migrated to another channel based on the assignments. Other embodiments are described and claimed.02-18-2010
20090157924METHOD AND APPARATUS FOR CONFIGURING ELECTRONIC DEVICES TO PERFORM SELECTABLE PREDEFINED FUNCTIONS USING DEVICE DRIVERS - A multifunctional mobile telephone handset is connected to a PC using a Universal Serial Bus. During bus enumeration, a device class descriptor is returned by the handset to the PC. The PC's operating system receives information relating to one of the functions of the handset and assigns an appropriate device driver.06-18-2009
20090157923Method and System for Managing Performance Data - The present invention is directed to a method and system for managing performance data. In accordance with a particular embodiment of the present invention, cache metrics are received. At least one of the cache metrics may be compared with a threshold value. A determination may be made as to whether one or more parameter adjustments are required based upon the comparison.06-18-2009
20120185625Method for operating a fieldbus interface - A method for operating a fieldbus interface (FI) connected to a fieldbus of process automation technology. The method includes the following: tapping data traffic on the fieldbus by the fieldbus interface; and registering tapped configuration information relative to cyclic data traffic on the fieldbus by the fieldbus interface.07-19-2012
20090125656Method and Arrangement for the Automatic Configuration of a Master-Slave Field Bus System - A field bus system (05-14-2009
20100095033PERFORMING A CONFIGURATION VIRTUAL TOPOLOGY CHANGE AND INSTRUCTION THEREFORE - In a logically partitioned host computer system comprising host processors (host CPUs) partitioned into a plurality of guest processors (guest CPUs) of a guest configuration, a perform topology function instruction is executed by a guest processor specifying a topology change of the guest configuration. The topology change preferably changes the polarization of guest CPUs, the polarization related to the amount of a host CPU resource is provided to a guest CPU.04-15-2010
20130046908SCALABLE METHOD AND APPARATUS TO CONFIGURE A LINK - Disclosed herein axe reconfigurable ports and methods for doing the same.02-21-2013
20090043931AUTOMATIC CONFIGURATION OF A COMMUNICATION PORT AS TRANSMITTER OR RECEIVER DEPENDING ON THE SENSED TRANSFER DIRECTION OF A CONNECTED DEVICE - A communications port is implemented for configuration in direction and arrangement. According to an example embodiment of the present invention, a communications link, such as a PCI Express type link, is configurable for communicating with devices having different directional and/or polarity configurations. The communications link is configured to match a communications port condition (e.g., a directional and/or polarity condition) of a device coupled to the communications link. In one instance, the communications link is directionally configurable for reassigning input lanes to output lanes and output lanes to input lanes. With this approach, the communications link can be used to communicate with a variety of devices having varied communication characteristics.02-12-2009
20120191885METHOD FOR CONFIGURING CHARGING PORTS AND CONTROLLER APPLYING THE SAME - A method for configuring charging ports and a controller applying the same are disclosed. The method includes recording a maximum permission value and a permitted value, and comparing the maximum permission value and the permitted value to determine whether the interface port can be used as a charging port when a device is connected to an interface port.07-26-2012
20090094396MODULE FOR REPRODUCING A TRANSMITTER SIGNAL - The invention relates to a module for reproducing a transmitter signal (x04-09-2009
20130073754APPARATUS AND METHOD FOR ESTABLISHING DEVICE IDENTIFIERS FOR SERIALLY INTERCONNECTED DEVICES - A method or apparatus operates a multitude of devices in a serial interconnection configuration to establish a device identifier (ID) for each device. An input signal is transmitted through a serial interconnection to a first device using inputs that are also used by the first device to input other information thereto (e.g., data, commands, control signals). A generating circuit generates a device ID in response to the input signal. A transfer circuit then transfers an output signal associated with the device ID to a second device through a serial output of the first device. The serial output is also used by the first device to output other information (e.g., signals, data) to another device in the serial interconnection configuration.03-21-2013
20130060979MULTIPLEXED SERIAL MEDIA INDEPENDENT INTERFACE - Systems, methods, and devices are provided for a multiplexed serial media independent interface (03-07-2013
20130060978INTEGRATED LINK CALIBRATION AND MULTI-PROCESSOR TOPOLOGY DISCOVERY - Integrating link calibration and dynamic topology discovery in a multi-processor system establishes a first of a plurality of processors in the multi-processor system as a director of integrated link calibration and dynamic topology discovery. A plurality of high speed interconnects connects the plurality of processors with each other. The director processor directs calibration of each of the plurality of high speed interconnects via a shared hardware resource. The shared hardware resource is shared among the plurality of processors. Topology of the multi-processor system is incrementally discovered as each of the plurality of high speed interconnects is calibrated based on a result of each of the plurality of high speed interconnects being calibrated.03-07-2013
20130067127METHOD AND APPARATUS FOR INTERLEAVING BURSTS OF HIGH-SPEED SERIAL INTERCONNECT LINK TRAINING WITH BUS DATA TRANSACTIONS - In an apparatus according to one embodiment of the present disclosure, a communications link comprises a first device and a second device communicating with each other via the communications link at a plurality of different speeds. However, prior to communicating via the communications link for the first time at a second speed, the first device and second device complete a first training cycle at the second speed. Further, during this first training cycle for the second speed, the first training cycle for the second speed will pause before the first training cycle at the second speed completes, and the first device and second device communicate at a first speed for a period of time before returning to the paused first training cycle at the second speed. When the paused first training cycle for the second speed continues, the first training cycle for the second speed will continue where it had paused.03-14-2013
20090234995MOTHERBOARD DETECTION OF COMPUTER CHASSIS TYPE - A computer motherboard detects the form factor type of the chassis in which it is installed to permit tailoring functionality accordingly.09-17-2009
20090006685Computer Server System and Computer Server for a Computer Server System - A computer server system comprises multiple computer server units, each computer server comprising a server processing system. Each computer server comprises a local subsystem access module which is standardized for the multiple computer servers and which provides virtual control function for a single instantiation of a hardware resource of the computer server system, wherein the hardware resource is shared between each of the computer servers.01-01-2009
20090006684Backplane - There is described a backplane with connections for connecting functional units. The backplane has hardware resources to handle software tasks, wherein the hardware resources are redundantly implemented or comprise essentially identical hardware modules, and wherein the hardware resources are organized in such that the software tasks are dynamically assigned to the hardware resources.01-01-2009
20110289245Memory Controller and Method Utilizing Equalization Co-Efficient Setting - A chip includes a transmitter circuit and a register provided to store a value representative of an equalization co-efficient setting. The transmitter circuit includes an output driver configured to adjust an output data signal based at least in part on the equalization co-efficient setting.11-24-2011
20100030934Bus Termination System and Method - A memory system includes a number of integrated circuit chips coupled to a bus. Each of the integrated circuit chips has an input/output node coupled to the bus, the input/output node having a programmable on-die termination resistor. The input/output node of one of the integrated circuit chips is accessed via the bus. The programmable on-die termination resistor of each of the integrated circuit chips is independently set to a termination resistance. The termination resistance is determined by a transaction type and which of the plurality memory devices is being accessed, which information can be transmitted over a separate transmission control bus.02-04-2010
20090276552MOTHERBOARD AND POWER MANAGING METHOD FOR GRAPHIC CARD INSTALLED THEREON - A motherboard and a power managing method for a graphic card installed thereon are provided. When the motherboard is switched to a second performance mode from a first performance mode, a microcontroller in the motherboard outputs a regulation signal to the graphic card through an exclusive connection interface, so as to correspondingly adjust an operation parameter of the graphic card, thus achieving better overall power saving and performance improving the effects of a computer.11-05-2009
20100268859Server - A server includes a motherboard, a central processing unit (CPU) and a riser card. The CPU is mounted on the motherboard. The riser card is inserted in the motherboard. The riser card includes a first circuit board extending parallel to the CPU, such that the CPU positioned between the motherboard and the first circuit board. At least one memory is inserted in the first circuit board.10-21-2010
20090282176COMPUTER SYSTEM AND METHOD FOR PROCESSING DATA SIGNAL OF MEMORY INTERFACE THEREOF - A computer system and a method for processing a data signal of a memory interface thereof are provided. The computer system includes a memory module, a memory controller, and a digital signal processor. The memory controller accesses data temporarily stored in the memory module through a data bus. The digital signal processor processes varied data on the bus according to a select code to recover the data.11-12-2009
20090172223Method and Apparatus for Distributing Configuration Files in a Distributed Control System - The invention described herein provides a system and method for distributing and applying a configuration file from a master device (07-02-2009
20120297099CONTROL OVER LOADING OF DEVICE DRIVERS FOR AN INDIVIDUAL INSTANCE OF A PCI DEVICE - A method identifies a plurality of PCI devices in a computer system by an associated PCI device handle, wherein each of the PCI devices is also associated with a default EFI device driver. The method further identifies a target PCI device to be disabled from within the plurality of PCI devices, provides a dummy driver that enables fewer functions for the target PCI device than would the default EFI device driver, and binds the dummy driver to the target PCI device instead of binding the default EFI device driver associated with the target PCI device. The dummy driver may be used to effectively disable the target PCI device so that the POST does not hang up or completes faster without loading the default EFI device driver.11-22-2012
20080244126METHOD AND APPARATUS FOR CHAINING MULTIPLE INDEPENDENT HARDWARE ACCELERATION OPERATIONS - Multiple hardware accelerators can be used to efficiently perform processes that would otherwise be performed by general purpose hardware running software. The software overhead and bus bandwidth associated with running multiple hardware acceleration processes can be reduced by chaining multiple independent hardware acceleration operations within a circuit card assembly. Multiple independent hardware accelerators can be configured on a single circuit card assembly that is coupled to a computing device. The computing device can generate a playlist of hardware acceleration operations identifying hardware accelerators and associated accelerator options. A task management unit on the circuit card assembly receives the playlist and schedules the hardware acceleration operations such that multiple acceleration operations may be successively chained together without intervening data exchanges with the computing device.10-02-2008
20080244125Method and Apparatus for Non-Disruptively Unassigning an Active Address in a Fabric - A non-disruptive unassignment of an address from a fabric responsive to a request from a channel adapter. A logout command requests the fabric to unassign an address. The status of the address is thereby changed from active to unassigned and an acknowledgment sent back to the channel adapter.10-02-2008
20130219093Electrically Configurable Option Board Interface - A Main Logic Board having an electrically configurable option board interface (ECOBI) to facilitate connection of option boards into apparatus for providing optional functions. Once connected to the host, an Option board provides identification (ID) data to the main logic board host processor. The host processor determines the interface configuration necessary to enable communication between the host and the option board based on the option board ID, then configures electrically configurable interface circuitry for operational compatibility. The option board may provide an interface driver directly to the host for configuration of the interface. The interface may comprise a standard interface protocol such as PCI or USB that the host configures through the same connection to the option board.08-22-2013
20130219092Global Event Chain In An Island-Based Network Flow Processor - An island-based network flow processor (IB-NFP) integrated circuit includes islands organized in rows. A configurable mesh event bus extends through the islands and is configured to form one or more local event rings and a global event chain. The configurable mesh event bus is configured with configuration information received via a configurable mesh control bus. Each local event ring involves event ring circuits and event ring segments. In one example, an event packet being communicated along a local event ring reaches an event ring circuit. The event ring circuit examines the event packet and determines whether it meets a programmable criterion. If the event packet meets the criterion, then the event packet is inserted into the global event chain. The global event chain communicates the event packet to a global event manager that logs events and maintains statistics and other information.08-22-2013
20090049214GRAPHICS CARD TEST METHOD - A method for testing graphics cards is provided. The method utilizes a principle that when an operating system operates under a kernel layer, a CPU of the computer has privileges to execute any instructions, thus, able to perform privileged functions of a graphics card, thereby testing hardware acceleration functions of the graphics card. Utilizing the above method can test self-owned brand graphics cards before the GPU manufactured provides a formal graphics card driver of the graphics cards, and avoids abnormal situations resulting in bad communication between a graphics card test program and an informal graphics card driver of the graphics cards.02-19-2009
20080288682Database Contention and Deadlock Detection and Reduction Within Application Servers - A method in a data processing system for detecting and reducing database contention and deadlock caused from within an application server. A determination is made as to whether a set of parameters in a statistical model indicates contention. If the set of parameters in the statistical model indicates contention, an application server administrator is notified of the contention and the number of threads in an application server pool is reduced. If the set of parameters in the statistical model indicates contention is reduced, the number of threads in the application server pool is increased.11-20-2008
20110271020Node Differentiation in Multi-Node Electronic Systems - A technique for differentiating nodes in a multi-node electronic system includes establishing an intended configuration for the system, the configuration including a number of nodes to be installed and a specification of intended node locations. A node ID for each of multiple nodes to be installed in the system is established, and the multiple nodes are installed. Using the node ID established for each of the multiple nodes, a determination is made whether the multiple nodes as installed comply, with the intended configuration.11-03-2011
20090182916SERVER, AND METHOD OF RECOVERY FROM LINK FAILURE IN SERVER - In a server composed of a server module having a processor in it, an I/O module having an I/O extension slot for accommodating an I/O extension adapter to expand the server's I/O capability, and a management module managing the entire server, the server module and the I/O extension slot (and through it, ultimately the I/O extension adapter) are interconnected using a PCI Express interface and the I/O module and the management module are interconnected using a special interface carrying detection information indicating whether an I/O extension adapter is actually mounted on the I/O extension slot. In the event of a link failure on the PCI Express interface, link recovery is attempted by grasping the status of the link based on the detection information obtained through the special interface.07-16-2009
20090164677TIMING ADJUSTMENT IN A RECONFIGURABLE SYSTEM - This disclosure provides a method for adjusting system timing in a reconfigurable memory system. In a Dynamic Point-to-Point (“DPP”) system, for example, manufacturer-supplied system timing parameters such as access latency and maximum clock speed typically reflect a worst-case configuration scenario. By in-situ detecting actual configuration (e.g., whether expansion boards have been inserted), and correspondingly configuring the system to operate in a mode geared to the specific configuration, worst-case or near worst-case scenarios may be ruled out and system timing parameters may be redefined for faster-than-conventionally-rated performance; this is especially the case in a DPP system where signal pathways typically become more direct as additional modules are added. Contrary to convention wisdom therefore, which might dictate that component expansion should slow down timing, clock speed can actually be increased in such a system, if supported by the configuration, for better performance.06-25-2009
20080320188Method And Apparatus For Backing Up TCP Connection - A method for backing up a TCP connection includes a data transmission process and a data receiving process. The data transmission process includes obtaining, by an AMB of a transmitting end, boundary information of data; and backing up the data and the boundary information of the data to a SMB of the transmitting end. The data receiving process includes backing up, by the SMB, data received from a peer side of the TCP connection and the boundary information of the data received by the peer side to the AMB; and deleting the data received by the peer side from the data backed up by the SMB during the transmission process according to the boundary information of the data received by the peer side. The disclosure also provides an apparatus for backing up a TCP connection.12-25-2008
20090063737Portable amplified stethoscope with recording capability - The present invention relates to an improved design for a stethoscope. The invention is a stethoscope with a built-in amplifier and a memory stick to digitally record sounds as well as patient information. The present invention will be able to digitally record the sounds from the stethoscope through the use of an electronic amplification system and a built in memory stick. This system will also have a USB Port that allows the invention to communicate with a computer system. The medical practitioner will also be able to digitally hear the patient sounds with a set of head-phones or through the use of a Bluetooth system.03-05-2009
20090083461Soft-reconfigurable massively parallel architecture and programming system - The present disclosure provides a methodology for reducing congestion of a processing unit, preferably by configuring a plurality of functional blocks to run in parallel or in series without the influence or input from the processing unit. In an embodiment, the present method chains a plurality of functional blocks together by software so that one functional block starts after the completion of another functional block. The configuration of the chain can be series, parallel, and any combination thereof, arranged to meet the circuit's objective. The chaining can be configured and re-configured, preferably by software input. The chaining can also be performed at design time or at run time. The chaining can also be modified, preferably at design time, but can also be modified at run time.03-26-2009
20090083460Re-configurable bus fabric for integrated circuits - The present invention relates to a flexible and reconfigurable bus fabric for microelectronic processing units, which can offer efficient memory data management, together with efficient data transfer and relieving data transfer congestion in an integrated circuit. In an embodiment, the present reconfigurable bus fabric comprises a multistate intersection between two data buses. Preferably, the multistate intersection comprises at least two states, a connecting state connecting the two data buses, and a disconnecting state disconnecting the two data buses. The multistate intersection provides a reconfigurable bus fabric, allowing different connection configuration for the data buses. This reconfigurable bus fabric offers soft-configurability and soft-reconfigurability, using software programming to arrange the circuits' interconnections. Other configurations are also disclosed in exemplary embodiments.03-26-2009
20090204736COMPUTING DEVICE WITH FLEXIBLY CONFIGURABLE EXPANSION SLOTS, AND METHOD OF OPERATION - A computing device that allows for a flexible allocation of bandwidth among peripheral devices using a peripheral bus is disclosed. The computing device includes a peripheral bus and at least two slots. The computing device may be used with a single peripheral card or multiple peripheral cards. In a multi-card configuration the invention allows the bandwidth on the peripheral bus to be shared by all the cards. In a single-card configuration, the computing device allows available bandwidth on the peripheral bus to be used by a single card. The device is particularly useful with PCI express compliant expansion cards, such as graphics adapters.08-13-2009
20090248926System for automating storage device swaps and/or replacements - A storage device manipulation system for implementing communications between a set of storage devices and a midplane is described. The storage device manipulation system may comprise a receiver and a communication system. The receiver may be configured to receive a command and generate a stimulus corresponding to the command. The communication system may be communicatively connected to the receiver and may be communicatively connectable to the set of storage devices and the midplane. The communication system may be configured to implement communication between the set of storage devices and the midplane based upon the stimulus by selectively providing power to the storage devices in the set of storage devices, selectively providing power to the ports on the midplane, and selectively establishing communication between the storage devices and the ports.10-01-2009
20120198110MAIN BOARD AND METHOD FOR DYNAMICALLY CONFIGURING PCIE PORTS THEREOF - A main board and a method for dynamically configuring PCIE ports thereof. The main board comprises a PCIE slot, a detecting circuit, an ROM, a chipset and a modifying circuit. The chipset comprises a Management Engine controller and several PCIE ports. The chipset has a Management Engine function or a similar function. The detecting circuit detects the PCIE slot to generate a current state parameter. The ROM stores a default configuration data. The modifying circuit coupled between the chipset and the ROM determines whether the default configuration data needs to be modified according to the current state parameter. When the default configuration data needs to be modified, the modifying circuit modifies the default configuration data according to the current state parameter, so that the Management Engine controller initially configures the PCIE ports according to the modified default configuration data. Thus, the dynamical configuration of the chipset PCIE ports is realized.08-02-2012
20090125655ENABLING SAS EXPANDER LOOPS FOR INCREASED FAIRNESS AND PERFORMANCE - The use of loops in SAS networks is enabled by designating ports connected to loop connections as table loop ports (TLPs). Under normal operating conditions, each TLP is blocked from receiving BCNs, appears to the expander to have nothing connected to it, and is made invisible to initiators. The loop connection and TLPs may be enabled and used to access devices when a problem is detected. In particular, the TLP will now appear in a list of destination ports within the expander to which a BCN should be propagated. In addition, during a subsequent self-configuration, the TLP is allowed to populate its route table with devices accessible through it, and the existence of the TLP is also reported back to initiators. After re-discovery is complete, communications between the initiator and a target can resume, with traffic re-routed through the TLPs as needed, bypassing the failure point.05-14-2009
20090259782APPARATUS AND METHOD FOR AUTOMATICALLY PERFORMING SYSTEM CONFIGURATION - An apparatus and a method for automatically performing system configuration are provided. The apparatus includes a motherboard and a peripheral backplane. The motherboard includes a data transmission interface and has a plurality of predetermined messages, and the peripheral backplane includes a sensor. The motherboard is coupled to the peripheral backplane through the data transmission interface. The sensor disposed on the peripheral backplane identifies the type of a system in which the apparatus is applied and generates an identification code corresponding to the system type. The motherboard then selects one of the predetermined messages as a configuration message according to the identification code and automatically performs system configuration to peripheral devices by using the configuration message.10-15-2009
20130219091Island-Based Network Flow Processor Integrated Circuit - A reconfigurable, scalable and flexible island-based network flow processor integrated circuit architecture includes a plurality of rectangular islands of identical shape and size. The islands are disposed in rows, and a configurable mesh command/push/pull data bus extends through all the islands. The integrated circuit includes first SerDes I/O blocks, an ingress MAC island that converts incoming symbols into packets, an ingress NBI island that analyzes packets and generates ingress packet descriptors, a microengine (ME) island that receives ingress packet descriptors and headers from the ingress NBI and analyzes the headers, a memory unit (MU) island that receives payloads from the ingress NBI and performs lookup operations and stores payloads, an egress NBI island that receives the header portions and the payload portions and egress descriptors and performs egress scheduling, and an egress MAC island that outputs packets to second SerDes I/O blocks.08-22-2013
20100185798Method and communications system for the configuration of a communications module containing a logic component - The invention relates to a method according to which a cycle-oriented control program generated for a programmable logic controller (07-22-2010
20100169523Scalable method and apparatus to configure a link - Disclosed herein are reconfigurable ports and methods for doing the same.07-01-2010
20100191881System and Method for Reserving and Provisioning IT Resources - A method for reserving and provisioning IT resources comprises receiving, from a user, a request to reserve a desired configuration of IT resources. The desired configuration comprises one or more desired technical specifications and a desired reservation time having a start time and an end time. The method further comprises accessing an IT resource database to determine one or more of a plurality of resource pools that the user has access to. The one or more resource pools are consulted to determine if one or more IT resources matching the desired configuration are available. If the one or more IT resources matching the desired configuration are available, the one or more IT resources are reserved for the user and provided to the user at the start time.07-29-2010
20100161858ADDRESS CONVERSION SYSTEM AND METHOD - An address conversion system is applied for a numerical control device and connected between a software inner address unit and a hardware contact point address unit. The address conversion system includes an address editing unit and an address conversion unit. The address editing unit includes an address display module and an address editing module. The address display module is configured for displaying hardware device startup addresses stored in the software inner address unit via an address display interface. The address editing module is configured for displaying contact point addresses stored in the hardware contact point address unit via an address editing interface. The contact point addresses are capable of being amended in the address editing interface. The address conversion unit is configured for matching the hardware device startup addresses with the corresponding contact point address.06-24-2010
20100146168System and method of inter-connection between components using software bus - A method for inter-connection between components using a software bus, which may analyze whether a port in which at least one component is connected with each other is a data transmission port or a function interface calling port in accordance with an application of the port, determine an execution attribute of the port based on an analyzed result, and control the port in accordance with the execution attribute of the port. The function interface calling port may be divided into any one of a thread generation-connection port for each request using an attribute of an on-demand function calling port, or a recursive server connection port using an attribute of an on load function calling port in accordance with a type of the called port.06-10-2010
20100223408APPARATUS FOR NON-DISRUPTIVELY DISCONNECTING A PERIPHERAL DEVICE - An electronic device includes a communication bus having a physical layer for interacting with a peripheral device. The physical layer is configured to be adjacent to a link layer on the peripheral device. The electronic device further includes a connector at a junction of the physical layer and the link layer. Communication through the communication bus is maintained through the physical layer when the link layer of the peripheral device is disconnected from the physical layer at the connector.09-02-2010
20100235554RECONFIGURABLE POINT-TO-POINT MEMORY INTERFACE - Embodiments of an apparatus are described. An interface circuit in this apparatus receives or transmits digital signals on a bus and is configured to alternatively operate as either a data-bus interface circuit or a control-bus interface circuit in dependence upon a mode setting stored in a register. For example, the interface circuit may be pre-configured to interpret a line of an external bus as either a data line or a control line in accordance with the stored mode setting. Moreover, the stored mode setting may be dynamically configured (e.g., reprogrammed) during operation of the interface circuit so that subsequent digital signals are subsequently handled in accordance with a new mode setting.09-16-2010
20090327541ADAPTABLE DATAPATH FOR A DIGITAL PROCESSING SYSTEM - The present invention includes an adaptable high-performance node (RXN) with several features that enable it to provide high performance along with adaptability. A preferred embodiment of the RXN includes a run-time configurable data path and control path. The RXN supports multi-precision arithmetic including 8, 16, 24, and 32 bit codes. Data flow can be reconfigured to minimize register accesses for different operations. For example, multiply-accumulate operations can be performed with minimal, or no, register stores by reconfiguration of the data path. Predetermined kernels can be configured during a setup phase so that the RXN can efficiently execute, e.g., Discrete Cosine Transform (DCT), Fast-Fourier Transform (FFT) and other operations. Other features are provided.12-31-2009
20090327539Multiple Die System Status Communication System - Suitably arranged circuits located on a die surface are operatively connected via a shared link which is configured for carrying data information content between the suitably arranged circuits. A suitably arranged and configured system status signal is transferred between a first of the suitably arranged circuits and a second of the suitably arranged circuits via the shared link for mirroring a system status of the first of the suitably arranged circuits in the second of the suitably arranged circuits.12-31-2009
20090006683STATIC POWER REDUCTION FOR MIDPOINT-TERMINATED BUSSES - A memory system is disclosed which is comprised of a memory controller and addressable memory devices such as DRAMs. The invention provides a programmable register to control the high vs. low drive state of each bit of a memory system address and control bus during periods of bus inactivity. In this way, termination voltage supply current can be minimized, while permitting selected bus bits to be driven to a required state. This minimizes termination power dissipation while not affecting memory system performance. The technique can be extended to work for other high-speed busses as well.01-01-2009
20090150583Video data processing module furnished with a configurable video processing unit with a single input bus - According to the invention, the video data to be processed and the configuration data are transferred to the module via one and the same data bus. These modules are advantageously chained in series on a common bus which transfers to each module both the configuration data and the video data to be processed. Preferably, dead time or “blanking” periods between two picture frames transmitted on this bus are used in order to insert the configuration data.06-11-2009
20090113095COMPUTER WITH COMPOUND AUDIO INTERFACE - An exemplary computer with compound audio interface includes a chassis, a USB interface arranged in the chassis, an audio interface arranged in the chassis, and a switch arranged in the chassis. The USB interface includes two signal terminals and a ground terminal. The audio interface includes two audio signal terminals and a ground terminal, wherein the audio signal terminals and the ground terminal of the audio interface are connected to the signal terminals and the ground terminal of the USB interface via the switch respectively. The audio signals received by the USB interface can be transmitted to an audio system in the chassis via the audio interface.04-30-2009
20080228971Device modeling in a multi-core environment - A method and apparatus for modeling devices in a multi-core environment is herein described. A hardware offload engine or add-in device is modeled by offload engine code or device model code stored in memory. An event agent in a hypervisor traps accesses to the offload engine or add-in device and routes them to at least one core of a multi-core processor to be serviced. The core of the multi-core processor executes the offload engine code or device model code to emulate the physical hardware offload engine or add-in device to service the access. Therefore, virtual devices may be provided by providing virtual device code, allowing upgrade of a computer system without adding physical hardware.09-18-2008
20080228970EMBEDDED SYSTEM DESIGN THROUGH SIMPLIFIED ADD-ON CARD CONFIGURATION - Methods for configuring an embedded system are described. One method includes connecting a plurality of add-on cards to a circuit board having a programmable processor. The programmable processor is configured to communicate with the plurality of add-on cards. At least one add-on card connects to a circuit board utilizing two or more connectors. The method also includes determining an identifier of each of the plurality of add-on cards, where the identifier of each of the plurality of add-on cards is used to generate a configuration image. Further included is configuring the programmable processor to communicate with the plurality of add-on cards by obtaining the configuration image. In some examples, the programmable processor is an FPGA.09-18-2008
20110022751METHODS AND APPARATUS FOR AN IMPROVED MOTOR CONTROL CENTER - Methods, apparatus, and systems are provided for operating a motor control center. The invention includes determining a hardware configuration of functional modules within a motor control center; downloading the hardware configuration to a programmable logic controller; configuring a program to run on the programmable logic controller based on the hardware configuration; and executing the program. Numerous additional aspects are disclosed.01-27-2011
20100131685HARDWARE CONFIGURATION INFORMATION SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT - A method for determining configuration information to be reported comprises accessing a table corresponding to a configuration resource associated with the configuration information, wherein the table comprises an entry for each hardware configuration definition to be built for the configuration resource, identifying a seed value in the table corresponding to the configuration resource, and modifying the seed value based on a result of processing each entry indicated by the table.05-27-2010
20100131684SHARING RESOURCES IN MULTI-DICE STACKS - Apparatus, systems, and methods for configuring a plurality of stacked semiconductor dice with unique identifiers and identifying a die in the stack using the unique identifier are provided. Additional apparatus and methods are disclosed.05-27-2010
20090049213Computers having USB buses, methods of operation thereof and programs and information for use therewith - A computer has a USB bus with at least two USB connectors for removable USB devices. When a removable USB device is connected to at least one of the connectors, conventional standard actions are auto-launched. However, when a removable USB device is connected to at least one special USB connector, no action is auto-launched, or some non-standard action is auto-launched. The special USB connector is designated as such by a configuration file stored by the computer, because neither the USB address and port number of the hub for the special connector, nor the USB address allocated to the removable USB device can simply be used for this purpose.02-19-2009
20090307398Method for Manufacturing Memory Modules - In a method for manufacturing memory modules MM, first a support board SB is populated with memory components MC. After the populating process, individual memory components MC are programmed via a bus system BS provided on the support board. After programming, the support board SB is separated into individual memory modules MM.12-10-2009
20110252167PHYSICAL TO HIERARCHICAL BUS TRANSLATION - In an embodiment, a translation of a physical bus number to a hierarchical bus number is written to a south chip. The south chip receives a configuration write command that comprises a physical bus number. The south chip sends the configuration write command to a device via the bus identified by the physical bus number, and the device stores the physical bus number in the device. In response to a received message from a device that comprises the physical bus number, the south chip replaces the physical bus number in the message with the hierarchical bus number. The south chip sends the message to a north chip via a point-to-point serial link. Both the physical bus number and the hierarchical bus number identify a bus with which the device connects to a bridge in the south chip.10-13-2011
20100036983PROCESSING MODULE, INTERFACE, AND INFORMATION HANDLING SYSTEM - A processing module, interface, and information handling system are disclosed. According to an aspect, a processing module can include a plurality of components coupled to a circuit card operable to be coupled to a host processing system. The processing module can also include a processing module interface configured to be coupled to a host interface of the host processing system. According to an aspect, the processing module interface can include a plurality of contacts operable to couple a plurality of signals configured to be coupled between the host processing and the circuit card to enable or disable use of resources of the circuit card during a reduced operating state of the host processor.02-11-2010
20090216924Interconnection system - An interconnection system, apparatus and method is described for arranging elements in a network, which may be a data memory system, computing system or communications system where the data paths are arranged and operated so as to control the power consumption and data skew properties of the system. A configurable switching element may be used to form the interconnections at nodes, where a control signal and other information is used to manage the power status of other aspects of the configurable switching element. Time delay skew of data being transmitted between nodes of the network may be altered by exchanging the logical and physical line assignments of the data at one or more nodes of the network. A method of laying out an interconnecting motherboard is disclosed which reduces the complexity of the trace routing.08-27-2009
20100057957RECONFIGURABLE FADEC FOR GAS TURBINE ENGINE - A reconfigurable FADEC includes a reconfigurable CPU configured for performing digital computing functions. A reconfigurable MSPD communicates with the CPU and is configured for performing analog I/O functions. A data bus is coupled to the CPU and the MSPD. The data bus is configured for connecting the CPU and the MSPD to an external connector.03-04-2010
20110060854FUNCTIONAL CONFIGURATION WIZARD - Described herein are methods and systems for configuration of complex applications. The configuration is performed by invoking from a repository of an executable checklist. The repository includes executable checklists to be used for different configuration scenarios. An executable checklist consists of all the necessary activities for a particular configuration setting.03-10-2011
20100005204Power optimized dynamic port association - A method, device, system, and computer readable medium are disclosed. In one embodiment the method includes dynamically associating a newly active port in a computer system with a first host controller. The first association happens when a total number of currently active ports in the computer system is less than a maximum capacity number of ports for the first host controller. The method also includes dynamically associating the newly active port in the computer system with a second host controller. The second association happens when the total number of currently active ports in the computer system is greater than or equal to the maximum capacity number of ports for the first host controller. In this method, each port, the first host controller, and second host controller all utilize the same protocol.01-07-2010
20090240853Method and apparatus for configuring a bus network in an asset management system - A method and system for managing assets includes a controller area network bus having a first end and a second end. One or more sensor systems are connected to the network bus. The sensor systems are connected to one or more assets to obtain at least one of operational data and condition data for the one or more assets. A self-healing bridge is connected to the first end and the second end of the network bus and is adapted to minimize a loss of connectivity in the network bus.09-24-2009
20090240854Multiple Removable Non-Volatile Memory Cards Serially Communicating With a Host - Two or more very small encapsulated electronic circuit cards to which data are read and written are removably inserted into two or more sockets of a host system that is wired to the sockets. According to one aspect of the disclosure, command and response signals are normally communicated between the host and the cards by a single circuit commonly connected between the host and all of the sockets but during initialization of the system a unique relative card address is confirmed to have been written into each card inserted into the sockets by connecting the command and status circuit to each socket one at a time in sequence. This is a fast and relatively simple way of setting card addresses upon initialization of such a system. According to a second aspect of the disclosure, the host adapts to transferring data between it and different cards of the system over at least two different number of the data lines commonly connected between the host and all of one or more sockets, each card permanently storing a host readable indication of the number of parallel data lines the card is capable of using. This allows increasing the rate of data transfer when the need justifies an increased card circuit complexity. According to a third aspect of the disclosure, a serial stream of data is sent over a number of data lines from one to many by alternately connecting bits of the stream to a particular number of individual lines.09-24-2009
20080288681Devices with multiple functions, and methods for switching functions thereof - Devices with multiple functions and methods for switching functions thereof are provided. The device comprises a plurality of hardware components, a plurality of functional modules, an input device, and a processing module. Each functional module corresponds to one of the functional connecting configurations for the hardware components. The processing module executes one of the functional modules and drives the hardware components according to the functional connecting configuration corresponding to the executed functional module. The processing module determines whether to generate a switch command according to an input command received by the input device. When the switch command is generated, the processing module directly terminates the functional module being currently executed and adjusts to execute another functional module, and drives the hardware components according to the functional connecting configuration corresponding to the functional module to be executed.11-20-2008
20120278518NON-PORTED GENERIC DEVICE (SOFTWARE MANAGED GENERIC DEVICE) - Techniques are disclosed for utilizing a non-ported generic device (NGD) or other non-ported hardware to couple processing device(s) to access components on a serial data bus without the need for integrated manager hardware. Using the NGD, a processing device(s) can utilize available unused bandwidth on the serial data bus to communicate with components coupled with the serial data bus, including a processing device having the manager hardware. Various alterations and embodiments are disclosed.11-01-2012
20110264834RE-CONFIGURABLE MULTIPURPOSE DIGITAL INTERFACE - Systems and apparatus are provided for a reconfigurable, multi-purpose input/output (I/O) interface. The system comprises a comparator coupled to a means for signal generation. The system further comprises a switch fabric configured to reconfigure the I/O circuit in real time to perform a variety of signal processing, signal generation and built-in-test functions.10-27-2011
20110093631ADAPTERS FOR EVENT PROCESSING SYSTEMS - Methods, systems, and computer-readable media are disclosed for implementing adapters for event processing systems. A particular system includes an input adapter configured to store event objects received from a source at an input queue. The system also includes a query engine configured to remove event objects from the input queue, to perform a query with respect to the removed event objects to generate result objects, and to insert result objects into an output queue. The system also includes an output adapter configured to remove result objects from the output queue and to transmit the result objects to a sink.04-21-2011
20110125939Function expansion apparatus, information processing apparatus, and control method - A disclosed function expansion apparatus for expanding a function of an information processing apparatus by connecting the information processing apparatus to an external storage apparatus via a first interface includes a first storage unit that stores first setup information used for connecting the information processing apparatus to the external storage apparatus, a connection module unit that is operated based on the first setup information and connects the information processing apparatus to the external storage apparatus via the first interface, a control unit that is connected to the first storage unit, and the connection module unit or a second storage unit, and stores second setup information stored in the second storage unit into the first storage unit, wherein the second storage unit is exchangeable with the connection module unit and stores the second setup information in connecting to the connection module unit.05-26-2011
20100017549MECHANISM TO FLEXIBLY SUPPORT MULTIPLE DEVICE NUMBERS ON POINT-TO-POINT INTERCONNECT UPSTREAM PORTS - A method and apparatus for supporting multiple device numbers on point-to-point interconnect upstream ports. In one embodiment, the method includes a downstream component (DC) that performs discovery of internal device components of the DC during initialization of the DC. Subsequent to the discovery of internal devices of the DC, the DC may issue a multiple device number (MDN) request to an upstream component (UC) of the DC. In one embodiment, the MDN request may include an indication that the DC supports a “multiple device number capability,” as well as a quantity of the internal device components of the DC. The DC may receive an acknowledgement MDN from the UC to indicate a quantity of device numbers allocated to the DC. Subsequently, the DC may assign device numbers to the internal device components of the DC according to configuration requests received from the UC. Other embodiments are described and claimed.01-21-2010
20090182915Performing a Configuration Virtual Topology Change and Instruction Therefore - In a logically partitioned host computer system comprising host processors (host CPUs) partitioned into a plurality of guest processors (guest CPUs) of a guest configuration, a perform topology function instruction is executed by a guest processor specifying a topology change of the guest configuration. The topology change preferably changes the polarization of guest CPUs, the polarization related to the amount of a host CPU resource is provided to a guest CPU.07-16-2009
20120072626Automatic Addressing Protocol for a Shared Bus - An automatic addressing protocol for a shared bus is described. In an embodiment, devices connected in a chain by a shared bus are also connected by an independent electrical connection between each pair of neighboring devices. A protocol is used over the independent electrical connections which is independent of that used on the shared bus. Devices in the chain receive at least one device ID from an upstream neighbor via the independent electrical connection and either use this received ID as their ID or use the received ID to compute their ID. Where the device has a downstream neighbor, a device then transmits at least one device ID to the downstream neighbor via the independent electrical connection and this transmitted ID may be their ID or an ID generated based on their ID, for example, by incrementing the ID by one. The process is repeated by devices along the chain.03-22-2012
20120059959Method for Assigning Addresses to Nodes of a Bus System, and Installation - A method for assigning addresses to nodes of a bus system, and installation,03-08-2012
20120159023Method and System for Inter-PCB Communications with Wireline Control - Aspects of a method and system for inter-PCB communications with wireline control may include setting up a microwave communication link between a first PCB and a second PCB via a wireline communication bus. The initialization may comprise adjusting beamforming parameters of a first antenna array communicatively coupled to the first PCB, and of a second antenna array communicatively coupled to the second PCB. The first PCB and the second PCB may communicate data via the microwave communication link. The microwave communication link may be routed via one or more relay PCBs, when the first PCB and the second PCB cannot directly communicate satisfactorily. Control data may be transferred between the first PCB, the second PCB, and/or the one or more relay PCBs, which may comprise one or more antennas. The relay PCBs may be dedicated relay PCBs or multi-purpose transmitter/receivers.06-21-2012
20120159022INTEGRATION OF FIELD DEVICES IN A DISTRIBUTED SYSTEM - Exemplary embodiments are directed to a system and method for integrating field devices in an automation system having a plurality of field devices connectable via at least one bus system. A respective field device is connected to the bus system of the automation system, and is automatically addressed by a superordinate controller using a predefined default address. The device addressed using the default address then registers in the system with its device address, and a fixed address which is provided from a multiplicity of unassigned addresses from an address memory is automatically allocated to the device registered in the system. An individually assigned identification (TAG) provided from the predetermined configuration of the automation system is allocated to the allocated fixed address, and, after the automatically allocated fixed address has been transmitted to the field device, the field device is changed to a suitable state for communication with the superordinate controller.06-21-2012
20090132741COMMUNICATION CHANNEL CALIBRATION USING FEEDBACK - A method for calibrating a communication channel coupling first and second components includes transmitting a data signal from the first component to the second component on the communication channel, and sensing a characteristic, such as phase, of the data signal on the second component. Information about the sensed characteristic is fed back to the first component using an auxiliary channel. An adjustable parameter, such as phase, for the transmitter is adjusted on the first component in response to the information. Also, a characteristic of a data signal received from the transmitter on the second component is sensed and used to adjust an adjustable parameter for the receiver on the first component.05-21-2009
20120124255Priority Logic Module - In a nuclear process control system, a priority logic module (PLM) is provided. The priority logic module comprises a plurality of input ports, each input port associated with one of a plurality of priorities, a plurality of output ports, and a test mode select port associated with a test mode select signal. The test mode select signal selects one of a normal mode or test mode, each mode being associated with matching signals received by the input ports to signals sent by the output ports. The priority logic module further comprises a configurable priority logic circuit, wherein the priority logic circuit maps one of the input ports to one of the output ports.05-17-2012
20120166690MULTI-ROOT SHARING OF SINGLE-ROOT INPUT/OUTPUT VIRTUALIZATION - In a first embodiment of the present invention, a method for multi-root sharing of a plurality of single root input/output virtualization (SR-IOV) endpoints is provided, the method comprising: CSR redirection to a management processor which either acts as a proxy to execute the CSR request on behalf of the host or filters it and performs an alternate action, downstream routing of memory mapped I/O request packets through the switch in the host's address space and address translation with VF BAR granularity, upstream routing of requests originated by I/O devices by table lookup indexed by Requester ID, and requester ID translation using a fixed local-global RID offset.06-28-2012
20120215954Resetting A Hypertransport Link In A Blade Server - Methods, apparatus, and computer program products are described for resetting a HyperTransport link in a blade server, including reassigning, by a blade management module, a gate signal from enabling a transceiver to signaling a HyperTransport link reset; sending, by the blade management module to a reset sync module on an out-of-band bus, the gate signal; and in response to the gate signal, sending, by the reset sync module to the blade processor, HyperTransport reset signals. The HyperTransport link includes a bidirectional, serial/parallel, high-bandwidth, low-latency, point to point data communications link. The blade server includes the blade processor, the reset sync module, and the baseboard management controller. The blade server is installed in the blade center. The blade center includes the blade management module. The blade management module is coupled to the baseboard management controller by the blade communication bus.08-23-2012
20100299465SCALING ENERGY USE IN A VIRTUALIZED ENVIRONMENT - A method, system, and computer usable program product for scaling energy use in a virtualized data processing environment are provided in the illustrative embodiments. A set of PIOAs is configured such that each PIOAs in the set of PIOAs is a functional equivalent of another PIOAs in the set of PIOAs. A utilization of each PIOA in the set of PIOAs is measured. A number of PIOAs needed to service a workload is determined. A first subset of PIOAs from the set of PIOAs is powered down if the number of PIOAs needed to service the workload is smaller than a number of operational PIOAs. The I/O operations associated with the first subset of PIOAs are transferred to a second subset of PIOAs remaining operational in the set of PIOAs.11-25-2010
20120254489BUS CONTROL FOR A DOMESTIC APPLIANCE - A domestic appliance (10-04-2012
20120185624Automated Cabling Process for a Complex Environment - A method is provided for cabling a plurality of hardware components. A chassis controller establishes a wireless connection to a wireless device. The chassis controller, via a wireless interface, transmits a chassis map to the wireless device over the wireless connection. The chassis controller, via the wireless interface, transmits to the wireless device, an indication of a first port to be cabled over the wireless connection, the first port. The first port is of a first hardware component of the plurality of hardware components. The chassis controller tests the first port to determine whether cabling of the first port has been performed correctly.07-19-2012
20090327540System and Method for Determining a Bus Address for a Controller Within a Network - A system and a method for determining a bus address for a controller within a network are provided. The method includes coupling a first set of pins of a wire harness connector to a second set of pins of a PCB connector of the controller. The method further includes sampling voltages of a portion of the first set of pins of the PCB connector to determine a wire harness ID utilizing a microprocessor. The method further includes accessing a look-up table from a memory device to select the bus address for the controller using the wire harness ID utilizing the microprocessor. The look-up table includes a plurality of bus addresses correspondingly associated with a plurality of wire harness IDs. The method further includes storing the selected bus address in the memory device utilizing the microprocessor.12-31-2009
20120084472PROGRAMMABLE MULTIMEDIA CONTROLLER WITH FLEXIBLE USER ACCESS AND SHARED DEVICE CONFIGURATIONS - A system which includes a programmable multimedia controller is provided in which flexible user access is provided through a combination of user profiles and usernames/pas swords. A configuration for a given device which may form part of the system or may interoperate with the system may be shared by multiple similar devices. A sharable device configuration is stored by a master device and can be shared by other devices of the same type as the master device.04-05-2012
20120084471USB TRANSACTION TRANSLATOR AND A MICRO-FRAME SYNCHRONIZATION METHOD - The present invention is directed to a universal serial bus (USB) transaction translator and a micro-frame synchronization method. A device interface is coupled to a device via a device bus, and a host interface is coupled to a host via a host bus, wherein the host USB version is higher than the device USB version. At least two buffers configured to store data are disposed between the device interface and the host interface. A controller stores the data in the buffers alternately. A start-of-frame (SOF) counter is used to count the SOF packets, wherein the counting value of the SOF counter is compared to a predefined value. Specifically, the controller resets a SOF timer for sending the SOF packet when the counting value achieves the predefined value or is greater than the predefined value, such that the SOF packet and an isochronous timestamp packet (ITP) from the host are sent at the same time. Further, the controller delays the sending of the SOF packet for a period of time according to the ITP from the host.04-05-2012
20100332703COMPUTER UNIT, COMPUTER PROCESSING METHOD, AND COMPUTER PROGRAM PRODUCT - Improves ease of operation by making it easier for the operator to view and select storage media devices connected to a computer unit. Provides a computer unit with a USB root hub and running an operating system that has the function of managing a storage media device connected to the root hub directly or indirectly via a hub. The unit includes a topology configuration portion that, when the hub is connected to a port of the root hub and the storage media device is connected to the hub, configures the hub as a virtual drive and sets up a connection whereby a folder corresponding to the storage media device is placed in the virtual drive; and a display controller that displays on a display device a directory list DP of the connections that were configured by the topology configuration portion.12-30-2010
20120239837RELATIONAL ADMINISTRATION OF SAS DOMAIN MANAGEMENT DATA - Disclosed is a process that is performed by a management application for automatically mapping the topology of one domain to another domain. In addition, if a device in a domain fails, the domain application can automatically associate replacement devices with predecessor management objects.09-20-2012
20110047307DATA TRANSFER METHOD AND DATA TRANSFER APPARATUS - A data transfer method for transferring data between a source device and a sink device includes receiving a query about a channel number included in connection plug information from the sink device and notifying the sink device of information of an unused connection plug when a channel corresponding to the channel number is unused.02-24-2011
20120278519UPDATING INTERFACE SETTINGS FOR AN INTERFACE - A computer system includes a processor, and the processor includes at least one interface for communicating with an electronic component. Each of the at least one interface has a set of interface settings. The computer system further includes a memory containing machine executable instructions. Execution of the instructions causes the processor to: monitor communications traffic on the at least one interface; store, eye distribution data acquired during the monitoring of the communications traffic in a database; compare the eye distribution data to a set of predetermined criteria; and generate a set of updated interface settings if the eye distribution does not satisfy the set of predetermined criteria.11-01-2012
20130013829MECHANISM TO FLEXIBLY SUPPORT MULTIPLE DEVICE NUMBERS ON POINT-TO-POINT INTERCONNECT UPSTREAM PORTS - A method and apparatus for supporting multiple device numbers on point-to-point interconnect upstream ports. In one embodiment, the method includes a downstream component (DC) that performs discovery of internal device components of the DC during initialization of the DC. Subsequent to the discovery of internal devices of the DC, the DC may issue a multiple device number (MDN) request to an upstream component (UC) of the DC. In one embodiment, the MDN request may include an indication that the DC supports a “multiple device number capability,” as well as a quantity of the internal device components of the DC. The DC may receive an acknowledgement MDN from the UC to indicate a quantity of device numbers allocated to the DC. Subsequently, the DC may assign device numbers to the internal device components of the DC according to configuration requests received from the UC. Other embodiments are described and claimed.01-10-2013
20130019036Expanded Electronic Bus Communication Capacity - In an embodiment, an apparatus comprises a bus network having a set of lines, and a number of communication system devices associated with a number of electronics equipment connected to the bus in which each communication system device configures the electronics equipment to send and receive a plurality of signals on a line of the set of lines in a noise region of the set of lines.01-17-2013
20110161535ADAPTABLE DATAPATH FOR A DIGITAL PROCESSING SYSTEM - The present invention includes an adaptable high-performance node (RXN) with several features that enable it to provide high performance along with adaptability. A preferred embodiment of the RXN includes a run-time configurable data path and control path. The RXN supports multi-precision arithmetic including 8, 16, 24, and 32 bit codes. Data flow can be reconfigured to minimize register accesses for different operations. For example, multiply-accumulate operations can be performed with minimal, or no, register stores by reconfiguration of the data path. Predetermined kernels can be configured during a setup phase so that the RXN can efficiently execute, e.g., Discrete Cosine Transform (DCT), Fast-Fourier Transform (FFT) and other operations. Other features are provided.06-30-2011
20110161534Control Architectures for RF Transceivers - Described herein are devices and methods for implementing a transceiver with independently controlled components. The components may include a programmable digital portion, a dedicated digital portion, and an analog portion. Each independently controlled component includes a programmable controller that resides in the programmable digital portion of the component that controls components in the dedicated digital or analog portions using state transition information. The programmable controller is configured to accommodate a broad spectrum of state transition information and is capable of emulating a plurality of hardwired finite state machines06-30-2011
20130024586VERIFICATION OF HARDWARE CONFIGURATION - A method for verifying an input/output (I/O) hardware configuration is provided. Data from an input/output data set (IOCDS) is extracted for building a verification command. The IOCDS contains hardware requirements that define at least software devices associated with a logical control unit (LCU). The verification command is processed. The verification command includes a software device address range associated with a logical control unit (LCU) of the I/O hardware. The LCU utilizes a first logical path. The software device address range utilizing the first logical path is compared with an existing software device address range utilizing at least one additional logical path. The verification command is accepted if the software device address range and the existing software device address range match.01-24-2013
20110246691METHOD AND APPARATUS FOR COHERENT DEVICE INITIALIZATION AND ACCESS - A method and apparatus for enabling usage of an accelerator device in a processor socket is herein described. A set of inter-processor messages is utilized to initialize a configuration/memory space of the accelerator device. As an example, a first set of inter-processor interrupts (IPIs) is sent to indicate a base address of a memory space and a second set of IPIs is sent to indicate a size of the memory space. Furthermore, similar methods and apparatus' are herein described for dynamic reconfiguration of an accelerator device in a processor socket.10-06-2011
20130145062UNIVERSAL SERIAL BUS PRE-DETERMINING CIRCUIT - A universal serial bus pre-determining circuit for determining whether a universal serial bus is connected to a host or a device includes an input unit, a detection unit, a processing unit, and a switch unit. The input unit is connected to the host or the device. Once the input unit is connected to the host, the detection unit will enable the host, allowing the host to generate and send a synchronous signal to the input unit. Once the input unit is connected to the device, no synchronous signal will be generated. The processing unit determines accurately whether the universal serial bus is connected to the host or the device by judging the synchronous signal.06-06-2013
20130138845INTEGRATED CIRCUIT NETWORK NODE CONFIGURATION - An electronic device for transmitting and/or receiving data through an electronic networking bus-system having a network topology includes an analog input connector for receiving an analog input signal representative for a network location in a network topology, and a processing unit for handling network data traffic transmitted through an electronic networking bus-system having said network topology, wherein the processing unit is further adapted for determining at least one network configuration parameter for the handling of network data traffic taking into account said input signal or digitized version thereof.05-30-2013
20080215778APPARATUS AND METHOD FOR IDENTIFYING DEVICE TYPE OF SERIALLY INTERCONNECTED DEVICES - A memory controller is unaware of device types of a plurality of memory devices in a serial interconnection configuration. Possible device types include, e.g., random access memories (DRAM, SRAM, MRAM) and NAND-, NOR- and AND-type Flash memories. Each device has device type information on its device type. Each device is capable of performing a “+1” to an input search number. First, the memory controller sends a specific device type (“don't care”) and an initial search number. Each device performs the “+1” calculation. The last device provides the memory controller with an Nד+1” search number from which the memory controller can recognize the total number of devices in the serial interconnection configuration. Thereafter, the memory controller sends a pre-determined device number for device type matching. Each device performs device type match determination of “previous match”, “present match” and “don't care match” and based on the match determination, the input search number is or is not modified and propagated through the devices. From the propagated search number, the memory controller can identify the device type of each device.09-04-2008
20080201507Bus system and methods of operation thereof - A bus system and methods for initialization and communication in a bus system are presented.08-21-2008
20130138846ENHANCED DATA STORAGE DEVICE - A data storage device includes one or more data paths through electrical contacts of the data storage device. The data paths are operably connected to allow bits to be transferred into and out of the data storage device. The data storage device stores an indication of a number of the one or more data paths in a configuration register. A method includes performing, while the data storage device is operatively coupled to a host device, receiving a command of the host device to read the configuration register and providing the indication via at least one of the one or more data paths. Providing the indication enables indicating to the host device the number of the one or more data paths.05-30-2013
20130097345ADDRESS LEARNING AND AGING FOR NETWORK BRIDGING IN A NETWORK PROCESSOR - Described embodiments process data packets received that include a source address and at least one destination address. If the destination address is stored in a memory of an I/O adapter, the received data packet is processed in accordance with bridging rules associated with each destination address stored in the I/O adapter memory. If the destination address is not stored in the I/O adapter memory, the I/O adapter sends a task message to a processor to determine whether the destination address is stored in an address table stored in a shared memory of the network processor. The I/O adapter memory has lower access latency than the address table. If the destination address is stored in the address table, the received data packet is processed in accordance with bridging rules stored in the address table and the bridging rules stored in the I/O adapter memory are updated.04-18-2013
20100318701LOCATION ENABLED BOOKMARK AND PROFILE - Location based profiles are used to modify the configuration of a computing device based on a detected location. The location based profiles allow features such as cameras to be enabled and disabled. Physical and logical data storage partitions can also be mounted and unmounted, and the home screen displayed by a device can be modified. Location bookmarks can be used to further customize the appearance and function of a computing device.12-16-2010
20120284439COMPUTING SYSTEM WITH HARDWARE BUS MANAGEMENT AND METHOD OF OPERATION THEREOF - A method of operation of a computing system includes: providing reconfigurable hardware devices having a first application fragment and a second application fragment; configuring a virtual bus module having a virtual bus for coupling the reconfigurable hardware devices; allocating a physical port in the virtual bus, based on availability, for communicatively coupling the first application fragment and the second application fragment through the virtual bus; and implementing an application through the virtual bus including transferring application data between the first application fragment and the second application fragment.11-08-2012
20120284438COMPUTING SYSTEM WITH DATA AND CONTROL PLANES AND METHOD OF OPERATION THEREOF - A method of operation of an computing system includes: providing a microkernel; controlling a reconfigurable hardware device by the microkernel; configuring an event scoreboard module for monitoring the reconfigurable hardware device; and implementing an application configured in the reconfigurable hardware device including receiving a machine identifier for the reconfigurable hardware device.11-08-2012
20120284437PCI EXPRESS SR-IOV/MR-IOV VIRTUAL FUNCTION CLUSTERS - An apparatus, including a first multiple of virtual function clusters positioned on a Peripheral Component Interconnect Express (PCIe) configuration space, each of the clusters comprising at least one virtual function, and a second multiple of physical functions positioned on the PCIe configuration space. The apparatus also includes an extended virtual function shell positioned on the PCIe configuration space and configured to select one of the physical functions, to select one of the available virtual function clusters and to associate the selected virtual function cluster with the selected the physical function.11-08-2012
20130159572MANAGING CONFIGURATION AND SYSTEM OPERATIONS OF A NON-SHARED VIRTUALIZED INPUT/OUTPUT ADAPTER AS VIRTUAL PERIPHERAL COMPONENT INTERCONNECT ROOT TO MULTI-FUNCTION HIERARCHIES - A computer system includes an adapter, a processor, and a memory storing program code, the program code executable by the processor to determine the adapter is single root input/output virtualization (SR-IOV) capable, to determine that an operating system is capable of using the adapter in SR-IOV mode, to configure the adapter in SR-IOV mode by generating an SR-IOV function associated with the adapter, and to assign control of the SR-IOV function to the operating system.06-20-2013
20110314194METHOD AND APPARATUS FOR USING A SINGLE MULTI-FUNCTION ADAPTER WITH DIFFERENT OPERATING SYSTEMS - A flexible arrangement allows a single arrangement of Ethernet channel adapter (ECA) hardware functions to appear as needed to conform to various operating system deployment models. A PCI interface presents a logical model of virtual devices appropriate to the relevant operating system. Mapping parameters and values are associated with the packet streams to allow the packet streams to be properly processed according to the presented logical model and needed operations. Mapping occurs at both the host side and at the network side to allow the multiple operations of the ECA to be performed while still allowing proper delivery at each interface.12-22-2011
20130191566Overcoming Limited Common-Mode Range for USB Systems - An intelligent level shifter may be added to adjust the voltage level on the data lines (D+ and D−) used for communications in USB systems, to address the issue of missing negative common-mode range as defined by the USB specification. The level shifter may be part of a port power controller that allows adaptive shifting of the signal level in accordance with the current levels drawn on the supply line by a device, for example during charging. The port power controller may be operated in systems enabled for battery charging, and may combine overcurrent sensing (current meter for VBus) and the routing of the D+ and D− lines (used for the battery charging protocol) into a single package. By varying the voltage levels on the D+ and D− data lines according to the drawn current levels, the performance of USB Hosts ports and USB Hub ports may be greatly increased.07-25-2013
20120030387MECHANISM TO FLEXIBLY SUPPORT MULTIPLE DEVICE NUMBERS ON POINT-TO-POINT INTERCONNECT UPSTREAM PORTS - A method and apparatus for supporting multiple device numbers on point-to-point interconnect upstream ports. In one embodiment, the method includes a downstream component (DC) that performs discovery of internal device components of the DC during initialization of the DC. Subsequent to the discovery of internal devices of the DC, the DC may issue a multiple device number (MDN) request to an upstream component (UC) of the DC. In one embodiment, the MDN request may include an indication that the DC supports a “multiple device number capability,” as well as a quantity of the internal device components of the DC. The DC may receive an acknowledgement MDN from the UC to indicate a quantity of device numbers allocated to the DC. Subsequently, the DC may assign device numbers to the internal device components of the DC according to configuration requests received from the UC. Other embodiments are described and claimed.02-02-2012
20120030386Configurable Interface Controller - A flexible input/output controller logic interfaces with existing input/output controllers (IOC's) in order to configure the amount of data sent to and received from the IOC's. The flexible I/O interface receives data from a component at a rate determined by the particular component. The flexible I/O interface then feeds the received data to a traditional I/O controller at a rate suitable for the I/O controller. Thus, the interface to the individual I/O controllers is maintained. The flexible I/O logic balances bandwidth between a plurality of individual I/O controllers in order to better utilize the overall system I/O bandwidth. In one embodiment, the I/O configuration managed by the flexible I/O logic is determined during system-build, while in another embodiment, the I/O configuration is set during system initialization.02-02-2012
20120072627DYNAMIC CREATION AND DESTRUCTION OF IO RESOURCES BASED ON ACTUAL LOAD AND RESOURCE AVAILABILITY - A method for binding input/output (I/O) objects to nodes. The method includes binding an I/O object group to a NUMA node of a plurality of NUMA nodes on a system, obtaining an I/O object group size of the I/O object group, and determining an I/O object group target size based on an I/O object group aggregate load of the I/O object group. The method further includes comparing, by the NUMA I/O Framework, the I/O object group target size and the I/O object group aggregate load, determining, by the NUMA I/O Framework, that a difference between the I/O object group target size and the I/O object group aggregate load exceeds a threshold, and instructing, by the NUMA I/O Framework, an I/O Subsystem associated with the I/O object group to change the I/O object group size, wherein the I/O Subsystem changes, in response to the instruction, the I/O object group size.03-22-2012
20120303847SENSOR INTERFACE ENGINEERING - A method for communication between function modules in drive engineering is described, wherein a first function module has a first sensor interface, wherein a second function module has a second sensor interface, wherein the first sensor interface is functionally assigned to the second sensor interface, wherein the first function module is assigned to a first automation component, wherein the second function module is assigned to a second automation component, wherein an address, in particular a logical address, for the transfer of sensor data is automatically specified.11-29-2012
20130212308MEMORY MAPPED INPUT/OUTPUT BUS ADDRESS RANGE TRANSLATION - In an embodiment, a north chip receives a secondary bus identifier that identifies a bus that is immediately downstream from a bridge in a south chip, a subordinate bus identifier that identifies a highest bus identifier of all of buses reachable downstream of the bridge, and an MMIO bus address range that comprises a memory base and a memory limit. The north chip writes a translation of a bridge identifier and a south chip identifier to the secondary bus identifier, the subordinate bus identifier, and the MMIO bus address range. The north chip sends the secondary bus identifier, the subordinate bus identifier, the memory base, and the memory limit to the bridge. The bridge stores the secondary bus identifier, the subordinate bus identifier, the memory base, and the memory limit in the bridge.08-15-2013

Patent applications in class System configuring