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INTRASYSTEM CONNECTION (E.G., BUS AND BUS TRANSACTION PROCESSING)

Subclass of:

710 - Electrical computers and digital data processing systems: input/output

Patent class list (only not empty are listed)

Deeper subclasses:

Class / Patent application numberDescriptionNumber of patent applications / Date published
710305000 Bus interface architecture 1036
710107000 Bus access regulation 575
710300000 Bus expansion or extension 455
710105000 Protocol 320
710104000 System configuring 120
Entries
DocumentTitleDate
20090228624DERIVATIVE LOGICAL OUTPUT - Embodiments of the invention are related to methods, systems, and articles of manufacture for transferring data between two devices using an interconnect bus. On each conductive line of the bus, a bit representing a first logic state is transferred if a current bit is the same as an immediately previously transmitted bit. If the current bit is different from the immediately previously transmitted bit, then a bit representing a second logic state is transferred.09-10-2009
20120246364DATA PROCESSING APPARATUS AND DATA PROCESSING METHOD - A data processing apparatus may include a data conversion unit that arranges the input data in each transfer data in the conversion unit using one transfer data as one transfer unit and a predetermined number of transfer units as one conversion unit when converting a plurality of input data input sequentially into transfer data having a bit number identical to a predetermined bit number of a data bus and sequentially transferring the converted transfer data. The data conversion unit may include a data generation unit and a first data arrangement changing unit. The first data arrangement changing unit may include a bit change number calculating unit, a bit change number analysis unit, a first data sorting unit, and a data coupling unit.09-27-2012
20100106872DATA PROCESSOR FOR PROCESSING A DECORATED STORAGE NOTIFY - A data processing system having a processor and a target device processes decorated instructions (i.e. an instruction having a decoration value). A device of the data processing system such as the processor sends transactions to the target device over a system interconnect. A decorated storage notify (DSN) transaction includes an indication of an instruction operation, an address associated with the instruction operation, and a decoration value (i.e. a command to the target device to perform a function in addition to a store or a load). The transaction on the system interconnect includes an address phase and no data phase, thereby improving system bandwidth. In one form the target device (e.g. a memory with functionality in addition to storage functionality) performs a read-modify-write operation using information at a storage location of the target device.04-29-2010
20100095032USE OF COMPLETER KNOWLEDGE OF MEMORY REGION ORDERING REQUIREMENTS TO MODIFY TRANSACTION ATTRIBUTES - A method and system of relaxing the ordering of a read completion by setting an ordering attribute in the read completion. The relaxed ordering allows the read completion to bypass pending writes.04-15-2010
20090070503CAPACITIVE MULTIDROP BUS COMPENSATION - The signal integrity of a high speed heavily loaded multidrop memory bus is often degraded due the numerous impedance mismatches. The impedance mismatches causes the bus to exhibit a nonlinear frequency response, which diminishes signal integrity and limits the bandwidth of the bus. A compensating element, such as a capacitor which ties the bus to a reference plane (e.g., a ground potential), or an inductor wired in series with the bus, is located approximately midway between the memory controller and the memory slots. The use of the compensating element equalizes signal amplitudes and minimizes phase errors of signals in an interested frequency range and diminishes the amplitudes of high frequency signals which exhibit high degrees of phase error. The resulting bus structure has increased desirable harmonic content with low phase error, thereby permitting the bus to exhibit better rise time performance and permitting a higher data transfer rate.03-12-2009
20110022750Interface for Bridging Out-Of-Band Information from a Downstream Communication Link to an Upstream Communication Link - A device includes a first interface to receive a signal from a first communication link, wherein the receive signal includes out-of-band (OOB) information. A detector coupled to the first interface detects the OOB information. An encoder coupled to the detector encodes the OOB information into one or more symbols (e.g., control characters). A second interface is coupled to the encoder and a second communication link (e.g., a serial transport path). The second interface transmits the symbols on the second communication link. The device also includes mechanisms for preventing false presence detection of terminating devices.01-27-2011
20090006682METHOD OF ADAPTING AN EXPRESSCARD SLOT FOR SMALLER FORM FACTOR MEMORY COMPATIBILITY - An adapter assembly is disclosed that enables a memory card having a smaller length than a standard ExpressCard to be compatible with the standard ExpressCard slot. The adapter assembly includes an adapter having side rails configured to disable the ExpressCard slot ejector mechanisms. The adapter assembly further includes a tongue provided for rigidly connecting the adapter to a finger grip, which gets positioned outside of the opening of the ExpressCard slot upon insertion of the adapter assembly into the slot. The adapter allows a memory card having the approximate size, look and feel of a conventional CompactFlash card to be used in a conventional ExpressCard slot.01-01-2009
20080294817DATA TRANSMITTING APPARATUS - Interface circuits are tested flexibly. Interface circuits 11-27-2008
20080320187IC CARD, TERMINAL WITH IC CARD AND INITIALIZING METHOD THEREOF - An IC card and a terminal mounted with an IC card are disclosed. In one embodiment, the IC card includes i) a memory, ii) a plurality of contacts including a pair of RF contacts and at least one communication contact, a micro processor, selecting any one of a low speed communication protocol and a high speed communication protocol, processing data written in the memory by a command inputted through any one of the RF contact and the communication contact determined by the selected communication protocol, and outputting a corresponding response, iii) a high speed interface, communicating the command and the response through the communication contact by use of the high speed communication protocol, iv) a low speed interface, communicating the command and the response through the communication contact by use of the low speed communication protocol and v) a contact allotting unit, connecting the communication contact determined by the selected communication protocol to any one of the low speed interface and the high speed interface.12-25-2008
20080282004HOLOGRAPHIC ENTERPRISE NETWORK - A system, method, program product and service for implementing a holographic enterprise network. A system for providing an interface between an operations center and a three dimensional (3D) virtual simulator system capable of rendering holographic images of the operations center is disclosed. Included is a holographic enterprise interface having a translation system for translating standard enterprise data associated with the operations center and 3D holographic data. Also enclosed is a communications manager for managing parallel communications between the holographic enterprise interface and a 3D data processing infrastructure having a holographic bus.11-13-2008
20100115163METHOD, APPARATUS AND SYSTEM FOR SERIAL ATTACHED SCSI (SAS) ZONING MANAGEMENT OF A DOMAIN USING CONNECTOR GROUPING - Embodiments of the invention include a method, apparatus and system for managing SAS zoning, using connector grouping. A connector grouping management application is configured to allow connectors on the edge of the ZPSDS to be grouped into defined zones. The defined zones are used to create a minimal number of zone groups and to configure the respective permissions of the zone groups. The connector grouping application then compares all existing zone groups for phys common to more than one zone group. The connector grouping application removes all phys common to more than one zone group from the respective zone groups and moves the common phys to a new zone group. The zone groups are processed in this manner until no zone groups have common phys. Once all zone groups have been processed accordingly, information associated with the resulting zone groups and their respective permissions are transferred to the zone manager.05-06-2010
20090319705COMMUNICATION BETWEEN PROCESSOR CORE PARTITIONS - In an embodiment, a method is provided that may include providing a first address space exclusively and coherently accessible by a first processor core partition in a platform. A second address space may be provided in this embodiment that is exclusively and coherently accessible by a second processor core partition in the platform. Also in this embodiment, a third address space in the platform may be provided that is accessible, at least in part, by both the first and second processor core partitions and may be to permit communication between the first and second processor core partitions of at least one packet and at least one descriptor associated with the at least one packet. The at least one descriptor may indicate, at least in part, one or more locations in the third address space to store, at least in part, the at least one packet. Of course, many alternatives, modifications, and variations are possible without departing from this embodiment.12-24-2009
20100169522METHOD AND APPARATUS TO DEFER USB TRANSACTIONS - An apparatus and method are provided that include providing a transaction data structure, and monitoring the transaction data structure for a predetermined amount of time. A link between a bus device and a host controller may be provided into a low power state in response to the monitored transaction data structure.07-01-2010
20100115164Mobile Device Combining Business Card with Chip - A mobile device combining a business card with at least one chip comprises: a chip sensing device; a data transforming device connected to the chip sensing device; a microprocessor connected to the data transforming device; a display interface connected to the microprocessor for showing the data of the chip; an operation interface able to change the property of the data of the chip and connected to the microprocessor; a memory for the microprocessor storing the data of the chip; and a power supply system for the mobile device; wherein the chip sensing device is disposed in the mobile device and has two modes for receiving data, to keep a certain distance between the business card with the chip and the mobile device is to let the mobile device sense the data of the chip of the business card through the chip sensing device.05-06-2010
20090150582Hardware assisted endpoint idleness detection for USB host controllers - In some embodiments, an electronic apparatus comprises at least one memory module, and a universal serial bus (USB) host controller coupled to the memory, wherein the USB host controller implements hardware assisted idleness endpoint detection.06-11-2009
20080294818Semiconductor chip - In a chip, a transfer unit is provided between a physical layer processing unit and a link unit so that multiple lanes of data processed by the physical layer processing unit are transferred to the link unit. The transfer unit includes: multiple transfer unit input terminals inputting the multiple lanes of data processed by the physical layer processing unit; multiple transfer unit output terminals respectively connected to multiple input terminals of the link unit so as to output data input from one of the multiple transfer unit input terminals to each of the multiple input terminals of the link unit; and a switching unit switching the data, which is input from any one of the transfer unit input terminals, to be output from each of the transfer unit output terminals in response to a control signal from a control signal terminal.11-27-2008
20100100654Coupling a Specialty System, Such as a Metering System, to Multiple Control Systems - A metering system configured to couple to multiple specialty systems, such as a control system. At least some of the illustrative embodiments are processing units comprising a processor, a memory coupled to the processor, and a communication port configured to coupled to a backbone communication network of a control system. The memory stores a program that causes the processor to selectively participate (over the communication port) as a processing unit of a control system of a first manufacturer (the control system implements a first proprietary communication protocol between processing units), and to participate (over the communication port) as a processing unit of a control system of a second manufacturer different than the first manufacturer (the control system of the second manufacturer implements a second proprietary communication protocol between the processing units).04-22-2010
20090089466PROXIMITY COMMUNICATION PACKAGE FOR PROCESSOR, CACHE AND MEMORY - A “sombrero” bridge transports signal communication between a processor and one or more cache memories. The bridge surrounds the processor's perimeter, and includes an aperture opposite the processor through which power and data can be provided to the processor from another device. The bridge exchanges signals with the cache memories via capacitively coupled proximity connections. The bridge communicates with the processor via conductive (e.g. wire) connections and optionally proximity connections. Spacing between opposing pads of the proximity connection(s) between the bridge and the cache memories can be provided by recesses in a surface of the cache memory, corresponding recesses in an opposing surface of the bridge, and a ball for each matching pair of corresponding cache memory and bridge recesses. The ball fits in and between the recesses of the matching pair. The recess depths and ball diameter(s) constrain a minimum distance between opposing pads of the proximity connection(s).04-02-2009
20080244124Bus system for use with information processing apparatus - A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on t10-02-2008
20080250175CABLE ASSEMBLY HAVING AN ADAPTIVE TWO-WIRE BUS - Techniques for improving the quality or fidelity of a digital signal transmitted via a two-wire bus interconnect utilizing an open-terminal configuration at one or both end devices of the bus interconnect are disclosed. An intermediate two-wire bus is used to connect two open-terminal-based two-wire busses. A bus adapter device is utilized at each end of the intermediate two-wire bus, whereby the bus adapter device communicates signaling on the corresponding open-terminal-based two-wire bus using open-terminal ports and communicates signaling on the intermediate two-wire bus using push-pull ports. The bus adapter device can utilize control logic to implement a state machine or other function to control the interactions between the different two-wire buses. The bus adapter devices may be implemented as interchangeable integrated circuit devices that can change configuration based on connection, thereby permitting their implementation at either end of a bus transmission system.10-09-2008
20090055561Bus Module for Connection to a Bus System and Use of Such a Bus Module in an AS-I Bus System - Disclosed is a bus module that can be connected to a bus system and comprises means for outputting safety-relevant signals in the form of repeated unambiguous code sequences. The bus module further comprises a first and second arithmetic unit with means for executing software programs. A code generator program of the first arithmetic unit generates a first partial code sequence of the code sequence while a code generator program of the second arithmetic unit generates the remaining portion of the code sequence as a second partial code sequence. Advantageously, a proper code sequence is output at the output of the bus module only when both arithmetic units function properly. A deviation in the code sequence that is output can then be detected by a monitor or actuator.02-26-2009
20090265492Data transmission device - The invention relates to a data transmission device for transmitting data between a first bus system and a second bus system with a copy table (10-22-2009
20100005203Method of Merging and Incremantal Construction of Minimal Finite State Machines - A method of merging at least two state machines includes: mapping a first node from a first state machine to a second node of a second state machine to generate an input pair; performing a depth-first recursive analysis of transitions and nodes in the first state machine and the second state machine based on the input pair to construct an output node; and mapping the output node to a third state machine.01-07-2010
20080288680COMMUNICATION ARRANGEMENT - The disclosure relates to an arrangement and method for communication between modular devices for measurement, closed-loop and open-loop control which are connected to one another via a backplane. It is proposed that two modules of the device in each case be connected to one another via a serial point-to-point connection. Modules with a coupling element are connected to a plurality of other modules.11-20-2008
20080270648SYSTEM AND METHOD FOR MULTI-PORT READ AND WRITE OPERATIONS - A computer (10-30-2008
20100146166METHODS AND APPARATUSES FOR IMPROVING SATA TARGET DEVICE DETECTION - Methods and apparatuses for improving detection of a Serial Advanced Technology Attachment (“SATA”) target device by a storage initiator over a link. The storage initiator receives a Frame Information Structure (“FIS”) and determines whether the FIS is valid. In direct response to a determination that the FIS is invalid, the storage initiator immediately resets the link to the SATA target device.06-10-2010
20100146167Control and/or data-transmission module - The invention relates to a control and/or data-transmission system comprising a number of I/O modules connected in series one adjacent to the other and a control and/or data-transmission module, as well as a control and/or data-transmission module for controlling I/O modules for such a control and data-transmission system. The invention proposes a control and data-transmission system that comprises a number of I/O modules connected in series one adjacent to each other, wherein each I/O module comprises at least one I/O signal channel and also at least one first signal terminal for connecting the I/O signal channel to a data bus and at least one second signal terminal for connecting a bus subscriber to the I/O signal channel, and wherein the system comprises a control and/or data-transmission module that comprises control electronics for the selective control of the number of I/O modules and that forms a detachable unit.06-10-2010
20090182914Semiconductor memory device and data processing system including the semiconductor memory device - A semiconductor device that includes a plurality of memory cell arrays, a plurality of ports, a plurality of internal address generating circuits, and a controller. The plurality of internal address generating circuits may generate first and second internal addresses of first and second memory cell arrays of the plurality of memory cell arrays. The first internal address may designate a first area of the first memory cell array. The second internal address may designate a second area of the second memory cell array. The controller reads a series of data from the first area sequentially and writes the series of read data into the second area sequentially without transferring the series of read data to the plurality of ports.07-16-2009
20090164676Method For Transfer/Transmission Of Field Bus Data And Field Bus Communication System - Methods for the transfer/transmission of field bus data between at least two members of a field bus communication system, each member including at least one field bus interface and a memory device. At least one common memory device is provided for the at least two members, wherein field bus data is written onto the at least one common memory device by the first member, and the field bus data is read out of the at least one common memory device by the second member. A field bus communication system includes at least one member, where each member includes a field bus interface and a memory device. The field bus communication system further includes at least one common memory device writeable from and readable to the members of the field bus communication system.06-25-2009
20110225331GENERIC INTERFACE - A system and process for ensuring the smooth flow of electronic ink is described. Dynamic rendering is given priority over other event handlers. Priority may be the use of one or more queues to order when events occur and may be performing dynamic rendering prior to other steps.09-15-2011
20090100205MANAGMENT SYSTEM FOR RE-DISPLAYING CHARACTERS ON TERMINAL AND METHOD THEREOF - A management system for re-displaying characters on the terminal and re-displaying method thereof are disclosed. The management system includes a buffer having first buffer and a second buffer, a first switch, a second switch, and a control unit. The first buffer stores a plurality of characters constituting an image shown on a display of the terminal if the terminal is switched from the first computing device to the second computing device or if the second switch selects one of a first buffer set and a second buffer set. The second buffer stores a plurality of attributes constituting the image shown on the display of the terminal if the terminal is switched from the first computing device to the second computing device, or if the second switch selects one of a first buffer set and a second buffer set. The first switch couples one of the first computing device and the second computing device to the first buffer and the second buffer. The control unit is capable of controlling the switching procedure between the first computing device and the second computing device.04-16-2009
20110029702METHOD AND APPARATUS PERTAINING TO PORTABLE TRANSACTION-ENABLEMENT PLATFORM-BASED SECURE TRANSACTIONS - A portable transaction-enablement platform carries out certain actions to improve the protection of sensitive information. This can comprise detecting when a user of the portable transaction-enablement platform prepares to use the portable transaction-enablement platform to facilitate a sensitive transaction and then responding in a corresponding manner. This can comprise, for example, automatically pre-enabling transaction-enablement platform functionality as pertains to the sensitive transaction while also limiting transaction-enablement platform functionality that does not support the sensitive transaction and that poses a risk to the sensitive transaction.02-03-2011
20110145453CAPACITIVE MULTIDROP BUS COMPENSATION - The signal integrity of a high speed heavily loaded multidrop memory bus is often degraded due the numerous impedance mismatches. The impedance mismatches causes the bus to exhibit a nonlinear frequency response, which diminishes signal integrity and limits the bandwidth of the bus. A compensating element, such as a capacitor which ties the bus to a reference plane (e.g., a ground potential), or an inductor wired in series with the bus, is located approximately midway between the memory controller and the memory slots. The use of the compensating element equalizes signal amplitudes and minimizes phase errors of signals in an interested frequency range and diminishes the amplitudes of high frequency signals which exhibit high degrees of phase error. The resulting bus structure has increased desirable harmonic content with low phase error, thereby permitting the bus to exhibit better rise time performance and permitting a higher data transfer rate.06-16-2011
20090216923MANAGING RECOVERY OF A LINK VIA LOSS OF LINK - A computer program product, apparatus and method for managing recovery of a link in a multi-tasking multi-processor environment. An exemplary embodiment includes shutting off timers for a failed channel associated with the communications link, storing a loss of link condition in a data structure, disabling communications on the failed channel and sending an external notification of the loss of link condition.08-27-2009
20090031062MODULARIZED MOTHERBOARD - A modularized motherboard is provided. The modularized motherboard includes a first circuit board, a second circuit board and a connecting device. The first circuit board includes a north bridge chip, a central processing unit (CPU) slot and a first connecting port. The CPU slot is coupled to the north bridge chip and is used for installing a CPU. The second circuit board is independent of the first circuit board. The second circuit board includes a second connecting port and a south bridge chip. The south bridge chip is coupled to the north bridge chip via the second connecting port the first connecting port. The connecting device is coupled between the first connecting port and the second connecting port.01-29-2009
20090077287METHOD AND DEVICE FOR EXCHANGING DATA BETWEEN AT LEAST TWO STATIONS CONNECTED TO A BUS SYSTEM - A method and a device for exchanging data in messages between at least two stations connected by a bus system. The messages contain the data being transmitted by the stations over the bus system. Each message contains an identifier characterizing the data contained therein. Each station decides on the basis of the identifier whether to receive the message. The messages are controlled in time by a first station. The first station repeatedly transmits a reference message over the bus in at least one specifiable time interval. The time interval is subdivided into time windows of a specifiable length, the messages being transmitted in the time windows.03-19-2009
20100250802Data processing apparatus and method for performing hazard detection - A data processing apparatus and method are provided for performing hazard detection in respect of a series of access requests issued by processing circuitry for handling by one or more slave devices. The series of access requests include one or more write access requests, each write access request specifying a write operation to be performed by an addressed slave device, and each issued write access request being a pending write access request until the write operation has been completed by the addressed slave device. Hazard detection circuitry comprises a pending write access history storage having at least one buffer and at least one counter for keeping a record of each pending write access request. Update circuitry is responsive to receipt of a write access request to be issued by the processing circuitry, to perform an update process to identify that write access request as a pending write access request in one of the buffers, and if the identity of another pending write access request is overwritten by that update process, to increment a count value in one of the counters. On completion of each write access request by the addressed slave device, the update circuitry performs a further update process to remove the record of that completed write access request from the pending write access history storage. Hazard checking circuitry is then responsive to at least a subset of the access requests to be issued by the processing circuitry, to reference the pending write access history storage in order to determine whether a hazard condition occurs. The manner in which the update circuitry uses a combination of buffers and counters to keep a record of each pending write access request provides improved performance with respect to known prior art techniques, without the hardware cost that would be associated with increasing the number of buffers.09-30-2010
20090113094System for performing a serial communication between a central control block and satellite components - The various embodiments described herein relate to a system for performing a serial communication between a central control block and a plurality of satellite components within a semiconductor chip. The system comprises at least one logical ring that serially connects the satellite components to the central control block. The system further comprises a centralized timer. The satellite components aid the system in obeying protocols and performing direct accesses to and/or from registers. The logical ring comprises at least one data channel that is provided for transmitting data packets and address packets. Single-envelope transactions are implemented. Errors of the satellite components associated with the single-envelope transactions are reported to the central control block as additional acknowledgement information.04-30-2009
20080270649Multi-channel memory connection system and method - A multi-channel memory connection system comprises a circuit board comprising a plurality of memory connectors, at least one of the plurality of memory connectors configured to receive either a memory module or a memory riser, the at least one memory connector having at least two memory channels connected thereto through the circuit board.10-30-2008
20090070502Data Modification Module - The present invention relates to a microcontroller including a central processing unit, a storage location, a bus coupling the storage location to the central processing unit, and a data modification module for modifying data in the storage location. The data modification module includes a first interface being coupled to the bus for transferring data to the storage location over the bus, and a second interface being adapted to be coupled to an external device for receiving the data, wherein the data modification module is adapted to operate as a bus master and to transfer data received from the external device over the bus to the storage location.03-12-2009
20100191880MEMORY MODULE CAPABLE OF IMPROVING THE INTEGRITY OF SIGNALS TRANSMITTED THROUGH A DATA BUS AND A COMMAND/ADDRESS BUS, AND A MEMORY SYSTEM INCLUDING THE SAME - A memory module and a related memory system are disclosed. The memory module comprises a semiconductor memory having a data output buffer, a data input buffer, a command/address input buffer and a first termination resistor unit connected to a data bus. The memory module further comprises a second termination resistor unit connected to an internal command/address bus. First and second termination resistor units are preferably of different resistive value and/or type.07-29-2010
20110040911DUAL INTERFACE COHERENT AND NON-COHERENT NETWORK INTERFACE CONTROLLER ARCHITECTURE - A dual interface coherent and non-coherent network interface controller architecture is generally presented. In this regard, a network interface controller is introduced including a non-coherent bus interface to communicatively couple with devices of a system through a non-coherent protocol, the non-coherent bus interface to facilitate discovery of the network interface controller by an operating system, a coherent bus interface to communicatively couple with devices of the system through a coherent protocol, and a coherency engine to perform coherent transactions over the coherent interface including to snoop for writes on system memory. Other embodiments are also disclosed and claimed.02-17-2011
20110153883DUAL FIELD INSTRUMENT - A dual field instrument may include a first microprocessor that includes a first address bus and a first data bus and performs a first operation process, a second microprocessor that includes a second address bus and a second data bus performs a second operation process that is the same with the first operation process, a first code analysis unit that compresses and encodes histories of data on at least one of the first address bus and the first data bus to generate a first code, a second code analysis unit that compresses and encodes histories of data on at least one of the second address bus and the second data bus to generate a second code, and a first collating unit that collates the first code with the second code so as to determine whether or not the first code corresponds with the second code.06-23-2011
20090187689NON-VOLATILE MEMORY WITH LPDRAM - Memory, systems and devices are disclosed where a non-volatile memory device (such as a Flash memory device) is paired with a LPDRAM memory device or array and configures the LPDRAM by utilizing routines stored in the non-volatile memory executing on a controller or state machine of the either the LPDRAM or non-volatile memory. This allows the configuration of the LPDRAM to be self contained and occur under local control of the controller or state machine of the non-volatile memory (or LPDRAM) utilizing these pre-stored LPDRAM configuration routines, eliminating the need for the system designer to have to account for and configure the LPDRAM and its specific configuration and/or routines with the system processor or operating system.07-23-2009
20090177818DISCOVERY OF ELECTRONIC DEVICES UTILIZING A CONTROL BUS - Discovery of electronic devices utilizing a control bus. An embodiment of a method includes connecting a receiving device to a cable, where the cable includes a control bus. If the receiving device is in a disconnect state and a signal from a transmitting device is detected on the control bus, the device is transferred to a state for a first type of transmitting device. If the receiving device is in either the disconnect state or the state for the first type of transmitting device and a predetermined voltage signal is received from the transmitting device, then the receiving device is transferred to a state for a second type of transmitting device.07-09-2009
20090037626Multi-drop bus system - A multi-drop bus system and a method for operating such a system. The system includes a multi-drop bus having at least one bus line, each bus line being made up of a multiple of line segments. Each of the line segments terminates at a drop point and each drop point is coupled to a load impedance. The characteristic impedance of a line segment is matched to the equivalent impedance presented by the load impedance in combination with the characteristic impedance of a following segment, or is matched to the load impedance if there is no following segment.02-05-2009
20090077286DATA BUS INVERSION DETECTION MECHANISM - A bus inversion apparatus includes exclusive-OR gates and an inversion detector. The exclusive-OR gates are coupled to an instant data bus and a last data bus. The data buses have a corresponding plurality of bits, where the exclusive-OR gates perform a bitwise comparison of the data buses, and provide an exclusive-OR bus. The states of the exclusive-OR bus indicate whether corresponding bits of the data buses are different. The inversion detector counts the number of the corresponding bits that are different, and indicates that the instant data bus should be inverted. The inversion detector has a plurality of left shift circuits, each configured to perform a logical left shift of input bits as directed by the states of shift bits, where outputs of the each of the plurality of left shift circuits indicate a number of a subgroup of the corresponding bits that are different.03-19-2009
20110099308SPLIT TRANSACTION PROTOCOL FOR A BUS SYSTEM - A method of and apparatus for communicating between a host and an agent. The method includes the step of performing a first transaction between a host controller and a hub. The hub is operable to perform a single transaction with an agent based on the first transaction. The method then includes the step of performing a second transaction between the host controller and the hub. The second transaction is based on the single transaction.04-28-2011
20090327538DATA TRANSFER APPARATUS, INFORMATION PROCESSING APPARATUS, AND DATA TRANSFER METHOD - Provided is a data transfer apparatus having a system bus interface 12-31-2009
20090019199SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus includes a first memory cell region including a plurality memory cells; a second memory cell region including a plurality memory cells, the second memory cell region positioned adjacent to the first memory cell region; a sub-local data bus coupled with some of the plurality of memory cells in each of the first and second memory cell regions, the sub-local data bus configured to execute data I/O operations of the first and second memory cell regions; a data bus region disposed between the first and second memory cell regions; a first local data bus disposed within the data bus region and configured to execute data I/O operations in conjunction with the sub-local data bus and a first data I/O sense amplifier; and a second local data bus also disposed within the data bus region and also configured to execute data I/O operations in conjunction with the sub-local data bus and a second data I/O sense amplifier.01-15-2009
20100153599SIGNAL PROCESSING SYSTEM AND METHOD, SIGNAL PROCESSING APPARATUS AND METHOD, RECORDING MEDIUM, AND PROGRAM - According to one aspect of the invention, when an algorithm bay is connected to a signal processing apparatus according to a first connection mode, a selector of the algorithm bay selects and sets a first function provided by a first function provider as the signal processing function of the signal processing apparatus. When the algorithm bay is connected to the signal processing apparatus according to a second connection mode, the selector of the algorithm bay selects and sets a second function provided by a second function provider as the signal processing function of the signal processing apparatus. According to another aspect of the invention, a first information provider of an algorithm bay supplies a signal indicating first information to be used in the signal processing of a signal processor of a signal processing apparatus to the signal processor via a wired interface of the algorithm bay, wired connection, and a wired interface of the signal processing apparatus. A second information provider of the algorithm bay supplies a signal indicating second information of changing the signal processing function of the signal processor to the signal processor via a wireless interface of the algorithm bay, wireless connection, and a wireless interface of the signal processing apparatus.06-17-2010
20080256275Multi-Chip Module With Third Dimension Interconnect - A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network.10-16-2008
20080222329I/O and memory bus system for DFPs and units with two- or multi-dimensional programmable cell architectures - A general bus system is provided which combines a number of internal lines and leads them as a bundle to the terminals. The bus system control is predefined and does not require any influence by the programmer. Any number of memories, peripherals or other units can be connected to the bus system (for cascading).09-11-2008
20080222328Semiconductor memory module and memory system, and method of communicating therein - Example embodiments relate to a semiconductor memory module and memory system, and a method of communicating therein. According to an example embodiment, a semiconductor memory system may include a memory controller, M interconnected memory elements, and/or N data buses, where N is a natural number and M is a divisor of N. The N data buses may connect the M memory elements to the memory controller. Each memory element may use N/M of the N number of data buses.09-11-2008
20080201506Switch device for connection port access control - A switch device for connection port access control is applicable to a PS/2 connection port for converting a USB transmission specification to a PS/2 transmission specification. The switch device includes a universal serial bus (USB) expansion unit, which provides a plurality sets of USB transmission line, each set of USB transmission line having a USB connection port signal line and a first power supply control line; a USB-PS/2 conversion unit for converting the USB connection port signal line of a set of USB transmission line to a PS/2 connection port signal line; a logic unit having a first input end, a second input end, and an output end, the logic unit processing signals received by the first and second input ends and outputting the processed signal through the output end to form the output end into a second power supply control line; and a PS/2 connection port.08-21-2008
20120066421NETWORK SYSTEM AND NODE - A connector unit includes a communication line connecting a receiving port of a physical layer unit of a node to one adjacent node, and a communication line connecting a transmitting port of the physical layer unit to the one adjacent node via a capacitor, and a connector unit includes a communication line for connecting a receiving port of a physical layer unit of the node to the other adjacent node, and a communication line for connecting a transmitting port of the physical layer unit to the other adjacent node via a capacitor, wherein the connector unit is connected to a connector unit of the one adjacent node, so that the communication line of the node is connected to the communication line of the one adjacent node, and the communication line of the node is connected to the communication line of the one adjacent node.03-15-2012

Patent applications in class INTRASYSTEM CONNECTION (E.G., BUS AND BUS TRANSACTION PROCESSING)

Patent applications in all subclasses INTRASYSTEM CONNECTION (E.G., BUS AND BUS TRANSACTION PROCESSING)