Class / Patent application number | Description | Number of patent applications / Date published |
710066000 | Width conversion | 10 |
20080228968 | IMAGE FORMING APPARATUS, IMAGE PROCESSING DEVICE, CONTROL DEVICE, AND CONNECTION DEVICE - A disclosed image forming apparatus includes an image processing device including plural image processing units; a control device configured to control the plural image processing units; and a connection unit configured to connect the image processing device to the control device. Each of the plural image processing units is connected to the control device by one of plural channels; the image processing device is connected to the control device by a first bus including the channels; and the connection unit is provided on the first bus so that the image processing device is connected to the control device by a single connection unit. | 09-18-2008 |
20080282001 | PEAK POWER REDUCTION USING FIXED BIT INVERSION - A semiconductor device includes a first circuit block, a second circuit block, and a data bus. The data bus is coupled between the first and second circuit blocks. A first data inverter on the data bus inverts a selected segment of data that is transferred onto the data bus. A second data inverter at an end of the data bus re-inverts the selected segment of data before the data is transferred off the data bus. The data that is transferred onto the data is not analyzed in order to determine the selected segment of data that is inverted. | 11-13-2008 |
20090006678 | Data input-output control apparatus - A system controller is presented that controls an output format of data according to a data congestion status of the data and then outputs the data over an output bus. Specifically, if there is data congestion, the system controller changes the format of the data to a format that matches a bus width of the output bus before outputting the data over the output bus. To give a specific example, the system controller changes the format of the data input over an input bus in an input format of 4 B to an output format of 5 B before outputting the data over the output bus. If there is no data congestion, the system controller outputs the data over the output bus without changing the input format. | 01-01-2009 |
20090043930 | SERIAL COMMUNICATION SYSTEM AND MONITOR DEVICE - A serial communication system includes a first and second communication devices for transmitting first signals in a first standard with each other; a convertor for receiving and converting the first signals into second signals in a second standard; a controller for generating third signals in the second standard according to the second signals; and a processing unit for receiving the third signals and generating data corresponding to the first signals in responding the received third signals. A related monitor device is also provided. | 02-12-2009 |
20090094392 | System and Method for Data Operations in Memory - A system and method for receiving, by a memory device, data in a first format, transforming, by the memory device, the data from the first format to a second format and outputting the data in the second format. An integrated circuit having at least one data segment and a logic circuit receiving and transforming data from a first format to a second format. | 04-09-2009 |
20100115158 | Methods and Systems to Accomplish Variable Width Data Input - Disclosed are methods and systems for variable width data input to a pattern-recognition processor. A variable width data input method may include receiving bytes over a data bus having a first width and receiving one or more signals indicating the validity of each of the one or more bytes The valid bytes may be sequentially provided to a pattern-recognition processor in an 8-bit wide data stream. In an embodiment, a system may include one or more address lines configured to provide the one or more signals indicating the validity of the bytes transferred over the data bus. The system may include a buffer and control logic to sequentially process the valid bytes. | 05-06-2010 |
20100293309 | Production Tool For Low-Level Format Of A Storage Device - A production tool for low-level format of a storage device is disclosed. The production tool includes an input connector connectable and an output connector, both of which conform to an interface standard. At least a redundant pin of the input connector is unconnected with a corresponding redundant pin of the output connector, and the redundant pin of the output connector is electrically connected to receive a provided predetermined signal, the presence of which indicating a low-level format mode. | 11-18-2010 |
20110113168 | Methods of Communicating Data Using Inversion and Related Systems - A method may be provided to communicate a plurality of groups of output data bits representing a respective plurality of groups of input data bits over a data bus with each group of output data bits and each group of input data bits have an equal data width. Each of the plurality of groups of input data bits at may be received at a data register. For each group of input data bits received at the data register, if a number of data bits of the group of input data bits having a first logic level is greater than half of the data width, the group of input data bits are inverted, the inverted group of input data bits are transmitted as a respective group of output data bits in parallel over the data bus, and an inversion flag associated with the respective group of output data bits is transmitted. For each group of input data bits received at the data register, if a number of data bits of the group of input data bits having a second logic level different than the first logic level is greater than half of the data width, the group of input data bits is transmitted without inversion as a respective group of output data bits in parallel over the data bus, and a non-inversion flag associated with the respective group of output data bits is transmitted. Related systems are also discussed. | 05-12-2011 |
20120324130 | Methods and Systems to Accomplish Variable Width Data Input - Disclosed are methods and systems for variable width data input to a pattern-recognition processor. A variable width data input method may include receiving bytes over a data bus having a first width and receiving one or more signals indicating the validity of each of the one or more bytes. The valid bytes may be sequentially provided to a pattern-recognition processor in an 8-bit wide data stream. In an embodiment, a system may include one or more address lines configured to provide the one or more signals indicating the validity of the bytes transferred over the data bus. The system may include a buffer and control logic to sequentially process the valid bytes. | 12-20-2012 |
20140223044 | METHODS AND SYSTEMS TO ACCOMPLISH VARIABLE WIDTH DATA INPUT - Disclosed are methods and systems for variable width data input to a pattern-recognition processor. A variable width data input method may include receiving bytes over a data bus having a first width and receiving one or more signals indicating the validity of each of the one or more bytes. The valid bytes may be sequentially provided to a pattern-recognition processor in an 8-bit wide data stream. In an embodiment, a system may include one or more address lines configured to provide the one or more signals indicating the validity of the bytes transferred over the data bus. The system may include a buffer and control logic to sequentially process the valid bytes. | 08-07-2014 |