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Input/Output process timing

Subclass of:

710 - Electrical computers and digital data processing systems: input/output

710001000 - INPUT/OUTPUT DATA PROCESSING

Patent class list (only not empty are listed)

Deeper subclasses:

Class / Patent application numberDescriptionNumber of patent applications / Date published
710061000 Synchronous data transfer 44
710060000 Transfer rate regulation 23
710059000 Processing suspension 4
20130166795SYSTEM AND METHOD FOR STREAMING DATA IN FLASH MEMORY APPLICATIONS - Systems and methods for streaming data are disclosed. In various implementations, the system comprises a hardware device and input streaming interface operably connected to the hardware device. The input streaming interface is configured to inform a data source, based on a determination that a receiving device will accept data transmitted by the hardware device, that the input streaming interface is ready to receive data, and then receive, in response to the detecting the activation of a source signal and a data initiation signal associated with the data source, source data transmitted by the data source over a data bus, and forward the source data to the hardware device.06-27-2013
20090019198Method and Apparatus for Effecting Database File Performance by Allowing Delayed Query Language Trigger Firing - Embodiments of the invention provide techniques for processing database triggers having delay attributes. In general, delay attributes may selectively introduce a delay between the firing of a trigger and the execution of the triggered action. The delay may be based on waiting for a specified time interval, waiting until a specified time, or reaching a predetermined threshold of a measure of system performance. The use of delay attributes may enable greater control over the timing of the execution of the triggered action, resulting in reduced impact on the performance of an underlying system.01-15-2009
20100023658SYSTEM AND METHOD FOR ENABLING LEGACY MEDIUM ACCESS CONTROL TO DO ENERGY EFFICENT ETHERNET - A system and method for enabling legacy media access control (MAC) to do energy efficient Ethernet (EEE). A backpressure mechanism is included in an EEE enhanced PHY that is responsive to a detected need to transition between various power modes of the EEE enhanced PHY. Through the backpressure mechanism, the EEE enhanced PHY can indicate to the legacy MAC that transmission of data is to be deferred due to a power savings initiative in the EEE enhanced PHY.01-28-2010
20110246689Content transmission apparatus, content playback system, content transmission method, and program - There is provided a content transmission apparatus including a reception unit for performing a receiving process for receiving, from a content output apparatus, a transmission instruction that is based on an output order of pieces of content data, a transmission unit for starting transmission of content data to the content output apparatus in response to the transmission instruction, and a control unit for controlling a time interval for causing the reception unit to perform the receiving process, according to wait information indicating a status of wait until transmission of the content data to the content output apparatus is to be started.10-06-2011
Entries
DocumentTitleDate
20090265485RING-BASED CACHE COHERENT BUS - Managing data traffic among three or more bus agents configured in a topological ring can include numbering each bus agent sequentially and injecting messages from the bus agents into the ring during cycles of bus agent activity, where the messages include a binary polarity value and a queue entry value. Messages are received from the ring into two or more receive buffers of a receiving bus agent. The value of the binary polarity value is changed after succeeding N cycles of bus ring activity, where N is the number of bus agents connected to the ring. The received messages are ordered for processing by the receiving bus agent based on at least in part on the polarity value of the messages and the queue entry value of the messages.10-22-2009
20090006673DETECTING A PRESENCE OF A DEVICE - Methods and systems are disclosed for detecting a presence of a device that includes providing a clock driver having a pair of differential clock signal lines capable of connection to a device, providing a presence detection signal for transmission through the pair of differential clock signal lines, determining whether the presence detection signal is received through the pair of differential clock signal lines, and identifying the presence of the device if the presence detection signal is received through the pair of differential clock signal lines.01-01-2009
20110302340SYSTEM AND METHOD DETECTING CABLE PLUG STATUS IN DISPLAY DEVICE - A timing controller provides a cable plug status detection function by receiving a reference lock signal from a graphics system connected via a constituent cable and comparing the reference lock signal to one or more reference time periods to determine the cable plug status.12-08-2011
20090287862Host device and scheduling method - In order to achieve an improved efficiency for a system in which a host device specifies a time slot for data transfer from a device to the host device, a scheduling unit of the host device performs scheduling and allocates, to the device, a time slot having a length of a shortest time period which is necessary for the device to perform the data transfer to the host device normally. When errors have occurred continuously in receiving data transferred from the device, the scheduling unit temporarily extends a slot length which is to be specified for the device.11-19-2009
20090187683ADAPTIVE LINK WIDTH CONTROL - A communications apparatus uses at least one logical communications link that comprises a plurality of lanes within a computerized hardware device. A data transfer monitor is connected to the logical communications link and measures the real-time data transfer bandwidth of the logical communications link. In addition, a link management unit or link width control unit (comparator) is connected to the lanes and to the data transfer monitor and continually compares the real-time data transfer bandwidth to a predetermined data transfer bandwidth standard. If the real-time data transfer bandwidth is below the predetermined data transfer bandwidth standard, the link management unit is adapted to perform up-configuring of the logical communications link by activating additional lanes up to a maximum number of lanes making up the logical communications link. Conversely, if the real-time data transfer bandwidth is above the predetermined data transfer bandwidth standard, the link management unit is adapted to perform down-configuring the logical communications link by deactivating lanes within the logical communications link. The lanes consume less power when the lanes are deactivated relative to when the lanes are activated, thus the down-configuring reduces power consumption.07-23-2009
20110173354Hardware Based Connection State Machine With Built In Timers - The present invention provides a hardware implemented connection monitoring system. A timer array establishes an input timer and an output timer for each connection between the processor and each I/O connection. A state machine periodically steps through the timer array to update the accumulated values of the timers and to monitor if any of the timers has reached a preset, timer done value. If a timer reaches the timer done value, the state machine loads the timer status into an event buffer and generates an interrupt for the processor. The processor reads the event buffer, identifies whether the expired timer was an input timer or an output timer, and takes action accordingly.07-14-2011
20090177811I/O DEVICE, NETWORK SYSTEM WITH I/O DEVICE AND COMMUNICATION METHOD IN NETWORK SYSTEM WITH I/O DEVICE - An I/O device is provided to accurately synchronize clocks between nodes to have a device driving signal directly made out from the clocks, so that operation timing can be synchronized between the nodes regardless of a processing flicker on a host computer and a delay in a communication channel, and so that sending and receiving of a communication frame between the nodes, updating of contents of the communication frame, etc. can be efficiently performed. The I/O device comprises receiving means for receiving information including at least contents instructing an input and output time to a device, time tag generating means for generating a time tag indicative of the input and output time included in the received signal to output the same to device control means, and clock means for generating a clock signal indicative of the present time, wherein the device control means compares the input and output time indicated by the time tag output from the time tag generating means with the present time indicated by the clock signal output from the clock means to output designated data to a device or input data from the device at the input and output time.07-09-2009
20110225328METHOD AND APPARATUS FOR ENHANCING UNIVERSAL SERIAL BUS APPLICATIONS - A system for enhancing universal serial bus (USB) applications comprises an upstream processor, a downstream processor and a main controller. The upstream processor accepts standard USB signals from a USB host and independently provides responses required by USB specification within the required time frame. The upstream processor also contains storage for descriptors for a device associated with this upstream processor. The main controller obtains the descriptors by commanding the downstream processor, and passes them to the upstream processor. The downstream processor connectable to USB-compliant devices accepts the USB signals from the USB-compliant devices and provides responses required by USB specification within the required time frame. The main controller interconnects the upstream and downstream processors, and provides timing independence between upstream and downstream timing. The main controller also commands the downstream processor to obtain device descriptors independent of the USB host.09-15-2011
20110225327SYSTEMS AND METHODS FOR CONTROLLING AN ELECTRONIC DEVICE - Systems and methods (09-15-2011
20080263240Transfer apparatus, transfer system, program, and transfer method - Disclosed herein is a transfer apparatus including, a connection status detection block, a storage status detection block, a no-operation status detection block, and a transfer block.10-23-2008
20090077278INFORMATION PROCESSING AND DEVICE INFORMATION MANAGEMENT APPARATUS AND METHOD - An information processing apparatus includes a receiving unit configured to receive device information sent by a peripheral device based on timing information, a setting unit configured to set timing information based on device information, and a transmission unit configured to transmit timing information set by the setting unit to a peripheral device.03-19-2009
20110055440METHOD FOR EXPRESSING EMOTION IN A TEXT MESSAGE - In one embodiment of the present invention, while composing a textual message, a portion of the textual message is dynamically indicated as having heightened emotional value. In one embodiment, this is indicated by depressing a key on a keyboard for a period longer than a typical debounce interval. While the key remains depressed, a plurality of text parameters for the character associated with the depressed key are accessed and one of the text parameters is chosen. Animation processing is then performed upon the textual message and the indicated portion of the textual message is visually emphasized in the animated text message.03-03-2011
20110087809Reduced latency barrier transaction requests in interconnects - Interconnect circuitry for a data processing apparatus is disclosed. The interconnect circuitry is configured to provide data routes via which at least one initiator device may access at least one recipient device, the interconnect circuitry comprising: at least one input for receiving transaction requests from the at least one initiator device; at least one output for outputting transaction requests to the at least one recipient device; at least one path for transmitting the transaction requests between the at least one input and the at least one output; control circuitry for routing said received transaction requests from said at least one input to said at least one output; wherein said control circuitry is configured to respond to a barrier transaction request to maintain an ordering of at least some transaction requests with respect to said barrier transaction request within a stream of transaction requests passing along one of said at least one paths, by not allowing reordering of at least some of said transactions requests that occur before said barrier transaction request in said stream of transaction requests with respect to at least some of said transaction requests that occur after said barrier transaction request in said stream of transaction requests; wherein said control circuitry comprises a response signal generator, said response signal generator being responsive to receipt of said barrier transaction request to issue a response signal, said response signal indicating to upstream blocking circuitry that any transaction requests delayed in response to said barrier transaction request can be transmitted further.04-14-2011
20100131682ELECTRONIC DEVICE AND METHOD FOR AUTOMATICALLY CONTROLLING OPERATION OF THE ELECTRONIC DEVICE - An electronic device is adapted to be connected to a plurality of peripheral devices, and includes a storage unit and a control circuit. The storage unit records a preset time and a control list. The control list lists at least a selected one of the electronic device and the peripheral devices, and an operation mode therefor. The control circuit detects whether the preset time matches a reference time, and if so, controls operation of the selected one of the electronic device and the peripheral devices according to settings in the control list.05-27-2010
20110264832SYSTEMS, METHODS, AND APPARATUS FOR FACILITATING COMMUNICATIONS BETWEEN AN EXTERNAL CONTROLLER AND FIELDBUS DEVICES - Systems, methods, and apparatus for facilitating communications between an external controller and Fieldbus devices are described. A primary linking device in communication with the controller and one or more Fieldbus devices may be configured to direct the communication of a timing message to the controller and determine whether a response to the timing message has been received from the controller. Based upon the determination, the primary linking device may direct a switching of communications control to a secondary linking device.10-27-2011
20110082953DATA TRANSMISSION METHOD FOR USE WITH WIRELESS MOUSE - A data transmission method for use with a wireless mouse includes the following steps. Firstly, a mouse displacement data including a horizontal displacement and a vertical displacement is periodically transmitted from a wireless signal emitter to a wireless signal receiver in every wireless transmission time interval T04-07-2011
20120151106PAIRING AND STORAGE ACCESS SCHEME BETWEEN A HANDHELD DEVICE AND A COMPUTING SYSTEM - A method is described that involves detecting the presence of a pairing partner. Prior to establishing a paired relationship with the pairing partner, a user is prompted to verify himself/herself. In response to the user properly verifying himself/herself, the paring partner is paired with. The pairing includes invoking a remote storage protocol that contemplates a network between the partners to establish on a first of the partners access to non volatile storage resources for general use. The non volatile storage resources are located on a second of the partners. The second of the partners is a handheld device that provides wireless cell phone service, wireless Internet service and music playback service.06-14-2012
20120159019PARALLEL COMPUTING SYSTEM, SYNCHRONIZATION DEVICE, AND CONTROL METHOD OF PARALLEL COMPUTING SYSTEM - A synchronization device includes a receiver that receives data from at least two synchronization devices establishing synchronization, and extracts synchronization information and register selection information from the received data, a transmitter that transmits data to each of the at least two synchronization devices establishing synchronization among a plurality of synchronization devices, a first and a second receiving state register that each stores the extracted synchronization information, a second receiving state register that stores the extracted synchronization information, and a controller that stores the extracted synchronization information into the first receiving state register and the second receiving state register alternately based on the register selection information, and controls the transmitter to transmit data including the register selection information to each of the at least two synchronization devices when the extracted synchronization information is completed in one of the first and the second receiving state register.06-21-2012
20110099306ENABLING CONSECUTIVE COMMAND MESSAGE TRANSMISSION TO DIFFERENT DEVICES - In one embodiment, the present invention includes a method for transmitting a frame information structure (FIS) message from a host controller or receiving a FIS message at the host controller, transmitting a synchronization signal from the host controller to a port multiplier coupled to the host controller via a link and sustaining a transmit ready signal from the host controller to the port multiplier to thereby lock the link between the host controller and the port multiplier after sending the synchronization signal, and transmitting multiple command FIS messages from the host controller to the port multiplier in a back-to-back manner, where the back-to-back command FIS messages are directed to different devices. Other embodiments are described and claimed.04-28-2011
20100174836USING USB SUSPEND/RESUME TO COMMUNICATE INFORMATION THROUGH A USB DEVICE - Methods and systems for communicating information through a USB device using suspend/resume states are presented. A USB host stops transmitting Start-of-Frame (SOF) packets to a USB device, causing the USB device to enter a sleep/suspend state. The USB host then restarts the transmission of SOF packets to trigger the USB device back into a normal/resume state. The USB host repeats this process in a temporal pattern corresponding to a message, such that a circuit monitoring the USB device can determine the message.07-08-2010
20120096197Management of a USB Host Device - A host device is managed that communicates with a peripheral device via an interface on the basis of a high frequency clock; the host device is in a suspended state in which the high frequency clock is deactivated. At the host device, an activation state of the peripheral device is detected (04-19-2012
20080244119Information processing apparatus, information processing method, and information processing program - An information processing apparatus includes a communication unit that transmits/receives data to and from an external device; a detection unit that detects communication connection with the external device by the communication unit; an operation input unit that accepts an operation input; a command allocation unit that, when the detection unit detects communication connection with the external device, allocates a data transmission command with respect to a one-click operation to a symbol corresponding to a data storage place to be displayed on a display unit, which is accepted by the operation input unit; and a control unit that, when the operation input unit accepts the one-click operation to the symbol, in case the data transmission command is allocated with respect to the one-click operation, controls so that the communication unit transmits data stored in the data storage place corresponding to the symbol to the external device.10-02-2008
20130145060SIGNAL COLLECTION SYSTEM AND METHOD WITH SIGNAL DELAY - An exemplary signal collection system includes a signal transmitting module, a computer, and a data collection card. The signal transmitting module includes a signal source and a delay chip. The delay chip receives a first path high-speed signal output from the signal source and transmits the first path high-speed signal to the data collection card in real time. The computer sends a delay command to the data collection card and the data collection card transfers the delay command to the delay chip. The delay chip generates a second path high-speed signal by delaying the first path high-speed signal in response to the delay command and transmits the second path high-speed signal to the data collection card. The data collection card transmits the high-speed signals output from the delay chip to the computer. A signal collection method based upon the signal collection system is also provided.06-06-2013

Patent applications in class Input/Output process timing

Patent applications in all subclasses Input/Output process timing