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Input/Output data buffering

Subclass of:

710 - Electrical computers and digital data processing systems: input/output

710001000 - INPUT/OUTPUT DATA PROCESSING

Patent class list (only not empty are listed)

Deeper subclasses:

Class / Patent application numberDescriptionNumber of patent applications / Date published
710056000 Buffer space allocation or deallocation 47
710057000 Fullness indication 32
710053000 Alternately filling or emptying buffers 30
710054000 Queue content modification 20
710055000 Contents validation 7
Entries
DocumentTitleDate
20100057953DATA PROCESSING SYSTEM - There is provided a data processing system comprising at least one processing module having at least one processor processing data and a data input/output unit that classifies and buffers input data received from an external medium, applies the input data to a processing module capable of processing the input data among the at least one processing module such that the input data is processed, classifies and buffers output data processed by the at least one processing module and outputs the output data to an external device. Accordingly, a processing module can be easily added or changed, and thus integration and variableness of processing resources can be improved to code with an increase in the quantity of input/output data, costs required to support a new service and upgrade the data processing system can be minimized, difficulty in maintaining processing can be alleviated and capability of coping with trouble in the data processing system.03-04-2010
20080307125HIGH-SPEED SEQUENTIAL SAMPLING OF I/O DATA FOR INDUSTRIAL CONTROL - An I/O module samples an industrial process to acquire data indicative of performance of the industrial process. The I/O module has an internal memory in which the data from multiple samples is stored until readout by, or produced to, an industrial controller. The I/O module assigns a time-stamp identifier to the stored samples thereby providing time information to the industrial controller for the stored data when read out by the industrial controller.12-11-2008
20130042032Dynamic resource allocation for transaction requests issued by initiator devices to recipient devices - Initiator devices for generating transaction requests and recipient devices for receiving them are disclosed. The recipient devices accept transaction requests where there is available buffer storage for the transaction request. If there is no storage space available an acknowledgement signal generator generates and outputs a reject acknowledgement signal indicating a request has been received but has not been accepted by the recipient device. A credit generator can reserve at least one available storage location in the buffer and generate a credit grant for an initiator device that sent one of the transaction requests that was not accepted by the recipient device. The credit grant indicates to the initiator device that there is at least one reserved storage location, such that a subsequent transaction request from the initiator device will be accepted by the recipient device. Thus, the initiator device may not transmit the transaction request again until it has received the credit grant, whereupon it may transmit it along with a credit grant indicator such that it is sure that it will be accepted.02-14-2013
20100095029TAPE DRIVE, TAPE DRIVE RECORDING SYSTEM, AND METHOD FOR SELECTING IMPROVED TAPE SPEED IN RESPONSE TO INTERMITTENT READ REQUESTS - A tape drive, tape drive recording system, and method are provided for improving tape speed selection during data transfer. The tape drive comprises a buffer, a tape for recording the data to be temporarily stored in the buffer, and a read head. The tape drive further comprises a reading controller that initially sets a tape speed such that a drive transfer rate matches a host transfer rate as closely as possible and that drives the tape at the tape speed. To address backhitching caused by one or more host transfer halts, the reading controller subsequently adjusts the tape speed such that the drive transfer rate is lower than the host transfer rate by recalculating the host transfer rate in consideration of the host transfer and the host transfer halt and setting the tape speed such that the drive transfer rate matches the recalculated host transfer rate as closely as possible.04-15-2010
20090119424METHOD FOR STORING DATA - A method for storing data is disclosed. The method is used for storing data into a program memory used for storing program codes. The program memory is divided into a first buffer storage area and a second buffer storage area. By alternate accessing of the first buffer storage area and the second buffer storage area, instantly accessible data can be stored in the program memory, such that the conventional data memory can be replaced by the program memory of the present invention and the cost of the product can be reduced.05-07-2009
20130060975Assistive Buffer Usage Techniques - Assistive buffer usage techniques are described. In one or more implementations, audio generated through text-to-speech conversion is output, the audio corresponding to text portioned in one of a plurality of buffers from an item of content. An input is received to rewind or fast forward the output of the audio. Responsive to the input, additional audio is output that was generated through text-to-speech conversion from text portioned in another one of the plurality of buffers.03-07-2013
20110022746METHOD OF DISPATCHING AND TRANSMITTING DATA STREAMS, MEMORY CONTROLLER AND MEMORY STORAGE APPARATUS - A method of dispatching and transmitting data stream, which is used for a memory storage apparatus having a non-volatile memory module and a smart card chip, is provided. The method includes configuring a plurality of logical block addresses, and a plurality of specific logical block addresses are used for storing a specific file. The method also includes receiving a response data unit from the smart card chip and storing the response data unit in a buffer memory. The method also includes, when a logical block address corresponding to a read command from a host system belongs to one of the specific logical block addresses and the buffer memory stores a response data unit, transmitting the response data unit stored in the buffer memory to the host system. Accordingly, the method can make the host system to correctly receive the response data unit from the smart card chip.01-27-2011
20090234988APPARATUS AND METHOD FOR INITIALIZING AN ELASTIC BUFFER - An apparatus and method for initializing an elastic buffer are provided. The elastic buffer, a FIFO buffer, outputs and writes data according to a reading index and a writing index, respectively. First, a random number is generated. Then, the writing index is determined according to the random number and the reading index. Finally, the elastic buffer is initialized according to the writing index and the reading index.09-17-2009
20090055558Method for transmitting telegrams between a control device and a peripheral element via an intermediate device - For the transmission of a telegram from the control device to the peripheral element an intermediate device receives the telegram from the control device and forwards it without amendment to the peripheral element. For the transmission of a telegram from the peripheral element to the control device the intermediate device receives the telegram from the peripheral element and forwards it without amendment to the control device. The telegrams are safety telegrams, so that telegrams forwarded to the control device or to the peripheral element from the respective receiving unit can be checked for freedom from errors.02-26-2009
20090013106FLEXIBLE AND ERROR RESISTANT DATA BUFFERING AND CONNECTIVITY - One embodiment of the invention includes a method of buffering data between an upstream system sending data to a buffer and a downstream system obtaining data from the buffer. This method may include receiving a data record containing a status flag and a position identifier, reading the status flag and the position identifier of the received data record, and searching an existing buffer location associated with the received position identifier. In some instances, when the existing buffer location associated with the received position identifier has an existing record associated with the received position identifier, the condition of a processing flag associated with the existing record and buffering the received data at the buffer location may be reviewed and subsequent updates to a processing flag may be made.01-08-2009
20080320184Buffer device, buffer arrangement method, and information processing apparatus - A buffer device that transfers data and is shared by a plurality of CPU cores arranged in a symmetrically inverted manner about a predetermined reference line, each CPU core breaking up a data block into a plurality of data lines and outputting the data lines via a plurality of ports, includes a plurality of line buffers that correspond to the data lines and are connected to the ports in the CPU cores, wherein the line buffers are paired into line buffer groups, and the line buffers in each buffer group are arranged symmetrically about the reference line.12-25-2008
20080294811SYSTEM AND METHOD FOR MIRRORING POWER OVER ETHERNET REGISTERS IN A PHYSICAL LAYER DEVICE OVER A SINGLE ISOLATION BOUNDARY - A system and method for mirroring power over Ethernet (PoE) registers in physical layer devices (PHYs) over a single isolation boundary. PHYs in a PoE system can be arranged in a master/slave configuration. In this configuration, a master PHY can be designed to communicate with the power source equipment controllers via a single isolation device.11-27-2008
20120203941SERIAL COMMUNICATION DEVICE AND SERIAL COMMUNICATION METHOD - A serial communication device has: a MAC (Media Access Control), a mask circuit and a buffer. The MAC conforms to Serial Media Independent Interface specification and outputs an identical segment data for plural times within a unit period. The mask circuit is configured to mask a predetermined segment data out of the plurality of identical segment data and to output the other segment data out of the plurality of identical segment data. The buffer is configured to receive the segment data output from the mask circuit and to output the received segment data to a physical layer device in synchronization with a clock signal.08-09-2012
20110302339DATA TRANSFER APPARATUS AND DATA TRANSFER METHOD - A data transfer apparatus includes a plurality of input ports, a plurality of output ports and a switch unit between the plurality of input ports and the plurality of output ports. Each input port includes an input buffer configured to store input data including destination information indicating destinations of respective pieces of the input data, a first buffer monitoring unit configured to monitor a first usage rate of the input buffer, and a first frequency control unit configured to control a first operating frequency of the input buffer on the basis of the first usage rate. Each output port includes an output buffer configured to store output data, a second buffer monitoring unit configured to monitor a second usage rate of the output buffer, and a second frequency control unit configured to control a second operating frequency of the output buffer on the basis of the second usage rate.12-08-2011
20100281193DATA BUFFER DEVICE - A data buffer device includes: a tag value generation circuit that generates a tag value; a first buffer that stores first priority data; a second buffer that stores second priority data; and a data output circuit that outputs the first priority data or the second priority data, wherein the tag value generation circuit sets a tag value for the following second input data to a second tag value which differs from a first tag value for second preceding input data, and sets a tag value of the following first input data to a fourth tag value that is the same as a third tag value for the first preceding input data, and wherein the data output circuit outputs the first priority data or the second priority data in a first mode based on the tag values and outputs the first priority data earlier in a second mode.11-04-2010
20090063734BUS CONTROLLER - A bus controller capable of shortening the time required before a flush is completed so as not to degrade the performance of a processor. A bus controller includes: a FIFO for temporarily holding, on a first-in first-out basis, data to be stored from a processor into a memory; a flush pointer for holding a pointer which indicates end data held by the FIFO at a time when a trigger signal is received; a memory control unit for writing a portion of the data held by the FIFO into the memory according to the trigger signal so as to partially flush the FIFO, the portion ranging from start data through end data indicated by the flush pointer; and a wait circuit for generating a wait signal for a specific access instruction, which is executed by the processor, until the memory control unit completes the partial flush.03-05-2009
20120110222APPARATUS AND METHOD FOR DYNAMICALLY ENABLING AND DISABLING WRITE XFR_RDY - A method for dynamically enabling and disabling use of XFR_RDY is disclosed herein. In one embodiment of the invention, such a method includes receiving a write command at a target and determining whether XFR_RDY is enabled or disabled for the write command. In the event XFR_RDY is disabled, the method determines whether one or more buffers are available at the target. If at least one buffer is available, the method processes the write command by writing data associated with the write command to the one or more buffers. The method then returns information indicating the number of buffers that are still available at the target after completing the write command. A corresponding apparatus and computer program product are also disclosed and claimed herein.05-03-2012
20100088438APPARATUS AND METHODS FOR TRANSLATION OF DATA FORMATS BETWEEN MULTIPLE INTERFACE TYPES - Apparatus and methods for translation of data formats between multiple interface types. Translation logic is interposed between a producer circuit and a consumer circuit to translate data formats of data signals generated by the producer for application to the consumer. The translation logic may include multiple translators to provide translations between any of multiple producer data formats and any of multiple consumer data formats. One or more producer circuits may thus be selectively coupled with one or more consumer circuits through the translation logic circuit.04-08-2010
20100082858METHOD TO IMPROVE OPERATING PERFORMANCE OF A COMPUTING DEVICE - The system includes a microprocessor, a first buffer, a second buffer, and a control circuit. The control circuit includes a memory and an interface. The control circuit is configured to determine a first buffer value and compare the first buffer value to a predetermined value to obtain a result. The control circuit is further configured to control a read issue rate of the first buffer based on the result. The memory is configured to store at least one of the first buffer value, the result, the read issue rate, and the TAG.04-01-2010
20100281192APPARATUS AND METHOD FOR TRANSFERRING DATA WITHIN A DATA PROCESSING SYSTEM - An apparatus for transferring data between buffers within a data processing architecture includes first and second memory devices. The apparatus further includes a first connection manager associated with a first buffer in the first memory device, and a second connection manager associated with a second buffer in the second memory device. The first and second connection managers manage data transfers between the first and second buffers. The first connection manager is configured to receive a token from the second connection manager in order to trigger data transfer between the first buffer and the second buffer. The first connection manager is further configured to initiate a data transfer between the first and second buffers in response to receiving the token. This token-based method for initiating data transfers between the connection managers requires little or no CPU intervention.11-04-2010
20090138634SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE WHICH EXECUTES DATA TRANSFER BETWEEN A PLURALITY OF DEVICES CONNECTED OVER NETWORK, AND DATA TRANSFER METHOD - A semiconductor integrated circuit device includes a first semiconductor device and a second semiconductor device, first and second buffer circuits, a data bus, and a control circuit. The semiconductor integrated circuit device executes data transmission/reception between the first and second semiconductor devices. The first and second buffer circuits store data. The data bus transmits the data between the first and second buffer circuits. The first semiconductor device reads out the transfer data into the first buffer circuit. The control circuit transfers the transfer data, which is stored in the first buffer circuit, to the second buffer circuit via the data bus. The control circuit acquires a right of use of the data bus after the first semiconductor device writes the transfer data into the first buffer circuit, and disclaims the right of use of the data bus after the transfer data is transferred to the second buffer circuit.05-28-2009
20080313367REPRODUCING DEVICE OF INFORMATION STORAGE MEDIUM REPRODUCING METHOD THEREOF - According to one embodiment, a reproducing device of an information storage medium sufficiently reproduces resource data of advanced contents as much as possible. The device uses a ring buffer to temporarily store packets of resource data of a video stream. Packets read out from the buffer are basically transferred to a file cache in response to a playlist. If a storage area in the cache cannot be secured, a packet list storage unit stores a packet list to be stored in the buffer. The packet list includes a pointer on the buffer of packets composing the resource data. When the cache makes it possible to store the packets therein, the buffer can transfer the packets to the cache at a high speed.12-18-2008
20100146162Apparatus and Method to Maximize Buffer Utilization in an I/O Controller - An apparatus and method for maximizing buffer utilization in an I/O controller using credit management logic contained within the I/O controller. The credit management logic keeps track of the number of memory credits available in the I/O controller and communicates to a chipset connected to the I/O controller the amount of available memory credits. The chipset may then send an amount of data to the I/O controller equivalent to or less than the communicated available amount of memory credits to reduce the occurrence of a “retry” event. The amount of available memory credits is determined by comparing the available memory in each buffer within the I/O controller and designating that the “available” amount of memory for the I/O controller is an amount equivalent to the amount of memory contained in the buffer with the least amount of available memory. This “available” amount of I/O controller memory may then be converted into memory credits and communicated to the chipset.06-10-2010
20090019194STORAGE DEVICE - When a control unit (01-15-2009
20090019192USB TRANSMISSION SYSTEM AND RELATED METHOD FOR ACCESSING DATA IN A FIRST USB SPECIFICATION WITH A SPEED OF A SECOND USB SPECIFICATION - A USB transmission system includes a transferring device for outputting connecting packet when the transferring device is electrically connected to a USB storage device for storing data in a first USB specification, and a server for receiving the connecting packet and accordingly outputting a request packet to the transferring device. The transferring device receives the request packet and accordingly outputs a first response packet in indicative of a second USB specification to the server. The first response packet indicates a device descriptor, and a configuration descriptor, of which the USB version defined in the device descriptor is set as the second USB specification, and the maximum packet size defined in the configuration descriptor is set as the speed of the second USB specification. The first USB specification complies with USB 1.1 specification, while the second USB specification complies with USB 2.0 specification.01-15-2009
20090083456INFORMATION INPUT SYSTEM, CONTROL METHOD THEREOF, AND STORAGE MEDIUM - This invention has as its object to provide an information input system which can flexibly select the storage location of information input from an input apparatus. To achieve this object, in an information input system which comprises an input apparatus for inputting information, and an information processing apparatus which is connected to the input apparatus and processes information transferred from the input apparatus, the input apparatus has a storage unit for storing input information, a connection detection device for detecting whether or not the information processing apparatus is connected to the input apparatus, and a controller for controlling to transfer the input information to the information processing apparatus without storing the information in the storage unit, when the connection detection device detects that the information processing apparatus is connected to the input apparatus.03-26-2009
20110145450TRANSACTION ID FILTERING FOR BUFFERED PROGRAMMED INPUT/OUTPUT (PIO) WRITE ACKNOWLEDGEMENTS - A PIO transaction unit includes an input buffer, a response buffer, and a control unit. The input buffer may receive and store PIO write operations sent by one or more transactions sources. Each PIO write operation may include a source identifier that identifies the transaction source. The response buffer may store response operations corresponding to respective PIO write operations that are to be transmitted to the transaction source identified by the source identifier. The control unit may store a particular response operation corresponding to the given PIO write operation in the response buffer prior to the given PIO write operation being sent from the input buffer. The control unit may store the particular response operation within the response buffer if the given PIO write operation is bufferable and there is no non-bufferable PIO write operation having a same source identifier stored in the input buffer.06-16-2011
20120131239DYNAMIC RESOURCE ALLOCATION FOR DISTRIBUTED CLUSTER-STORAGE NETWORK - Various embodiments for operating a distributed cluster storage network having a host computer system and a storage subsystem are provided. In one embodiment, by way of example only, at a first of a plurality of storage control nodes a request is received to write data to storage from the host computer system. The data is forwarded by a forwarding layer at the first of the plurality of storage control nodes to a second of the plurality of storage control nodes. Buffer resource are allocated for the data to be written to the storage by a buffer control component at each of the plurality of storage control nodes. The constrained status indicator of the buffer resource is communicated to the forwarding layer. Additional system and computer program product embodiments are disclosed and provide related advantages.05-24-2012
20090248920Off-Line Task List Architecture - A flexible and reconfigurable digital system (for example, a wireless modem) includes a set of sub-circuits. Each sub-circuit includes a task manager and an amount of configurable hardware circuitry for performing a type of operation on a data stream. The task manager of a sub-circuit can configure and control the configurable hardware of the sub-circuit. A central processor configures and orchestrates operation of the sub-circuits by maintaining a set of task lists in a tightly coupled memory. Each task list includes task instructions for a corresponding sub-circuit. The task manager of a sub-circuit reads task instructions from its task list and controls its associated hardware circuitry as directed by the instructions. A timestamp task instruction and a push task instruction and the task list architecture allow modem sub-circuits to be easily reconfigured to operate in accordance with either a first air interface standard or a second air interface standard.10-01-2009
20090248919METHOD FOR EXTERNAL FIFO ACCELERATION - Disclosed is a pre-fetch system in which data blocks are transferred between a RAM 10-01-2009
20080307126SYSTEM AND METHOD FOR SERIAL-PERIPHERAL-INTERFACE DATA TRANSMISSION - The invention provides a method for Serial-Peripheral-Interface (SPI) data transmission. First, data stored in a first buffer of an SPI controller is transmitted to a second buffer of an SPI slave. A clock signal according to which the SPI slave operates is halted after data stored in the first buffer is completely transmitted. The first buffer is then refreshed with data newly received by the SPI controller while the clock signal is halted. The clock signal is then restarted to operate the SPI slave after the first buffer is refreshed. Refreshed data stored in the first buffer is then transmitted to the second buffer while the clock signal is oscillating. Halting of the clock signal, refreshing of the first buffer, restarting of the clock signal, and transmitting of refreshed data are repeated until the second buffer is full. The buffer size of the second buffer greatly exceeds that of the first buffer.12-11-2008
20090094390Data transfer control device and electronic instrument - A data transfer control device including: a link controller which analyzes a packet received through a serial bus; a packet detection circuit which detects completion or start of packet reception based on analysis result of the received packet; first and second packet buffers into which the packet received through the serial bus is written; and a switch circuit which switches a write destination of the received packet. When a Kth packet has been written into one of the first and second packet buffers and completion of reception of the Kth packet or start of reception of a (K+1)th packet subsequent to the Kth packet has been detected, the switch circuit switching the write destination of the (K+1)th packet to the other of the first and second packet buffers.04-09-2009
20100223405CASCADABLE HIGH-PERFORMANCE INSTANT-FALL-THROUGH SYNCHRONOUS FIRST-IN-FIRST-OUT (FIFO) BUFFER - An apparatus and method of operating a cascadable, instant-fall-through First In, First Out (FIFO) buffer is provided. The method comprises receiving a first data element at an input of a FIFO buffer which includes a plurality of buffer slices including an output buffer slice wherein each of the plurality of buffer slices comprise a data register and a control bit register. A buffer slice is identified which is indicated for storing a data element based on a control bit register for the buffer slice and a control bit register of an adjacent buffer slice on an output side. When data is read from an output buffer slice the FIFO buffer, all data in other buffer slices are shifted down one slice closer to the output side of the FIFO buffer.09-02-2010
20100250798HIERARCHICAL MEMORY ARCHITECTURE WITH AN INTERFACE TO DIFFERING MEMORY FORMATS - A hierarchical memory storage using a concentrator device that is located between a processor and memory storage devices to provide an interface to accommodate different memory formats.09-30-2010
20100241770METHOD AND APPARATUS FOR EFFICIENT SYNCHRONIZATION REQUEST RESPONSE - A data writing apparatus includes a tape drive, a buffer and non-volatile memory. When a synchronization request is received from a device sending data to be written to a tape, the apparatus is operable to copy data corresponding to the synchronization request from the buffer to the non-volatile memory. The data may be stored in the non-volatile memory until at least the time when the data which it is a copy of is written to the tape from the buffer.09-23-2010
20100241771PERIPHERAL CIRCUIT WITH HOST LOAD ADJUSTING FUNCTION - A peripheral circuit with a host load adjusting function which is capable of readily carrying out control so that the amounts of data processed by the peripheral circuit and a host CPU are balanced by limiting interrupts made by the peripheral circuit, usage of a memory bus bandwidth, and a processing throughput of data. A typical embodiment of the present invention has an adjustment limitation setting unit setting a minimum value of an interval of interrupt requests generated by the peripheral circuit with the host load adjusting function, and a cycle counter counting generation timing of the interrupt requests, and compares a value of the cycle counter with the interval set in the adjustment limitation setting unit, thereby suppressing the interrupt requests generated at an interval shorter than the set interval.09-23-2010
20100211707METHOD AND APPARATUS FOR LOWERING I/O POWER OF A COMPUTER SYSTEM AND COMPUTER SYSTEM - The present invention provides a method and an apparatus for lowering I/O power of a computer system and a computer system. According to an aspect of the present invention, there is provided a method for lowering I/O power of a computer system, comprising: buffering a plurality of ways of data to be sent to a bus; encoding each of the plurality of ways of data buffered from n bits to n+m bits based on an encoding rule, wherein n and m are both an integer larger than or equal to 1, the encoding rule is used to lower code switching frequency; and sending the plurality of ways of data encoded to the bus.08-19-2010
20100211706BUFFER CONTROL DEVICE, BUFFER CONTROL METHOD, AND PROGRAM - A buffer control device includes a reference time generation unit configured to generate a reference time based on time information included in a data stream input, a buffer configured to receive an encoded data extracted from the data stream, store the encoded data, and output the encoded data at a decoding time or a reproducing time of the encoded data, and a control unit configured to control an input of the encoded data to the buffer based on a relativity between the decoding time or the reproducing time of the encoded data and the reference time.08-19-2010
20090327535ADJUSTABLE READ LATENCY FOR MEMORY DEVICE IN PAGE-MODE ACCESS - A read process in a memory device is optimized. Sub-pages of a page of data are read from storage elements by an internal controller of the memory device at a read speed of the internal controller. At a specific time, the controller sets a READY signal to inform an external host to start reading out data from the buffer in a continuous burst, at the associated read speed of the host, which can differ from the controller's read speed, and asynchronous to the internal controller. The READY signal is set so that the host can complete its burst before the buffer runs out of data, while overall read time is minimized. The controller can also be configured for use with hosts having different read speeds. A host may communicate an identifier to the controller for use in determining an optimum time to set the READY signal.12-31-2009
20090259776TIME-SHIFTING FOR PUSH TO TALK VOICE COMMUNICATION SYSTEMS - A network communication device located on a Push To Talk (PTT) communication network and configured to provide time-shifting capabilities to a user of a PTT communication device. The network communication device includes a receiver configured to progressively receive time-based media. The network communication device also includes a time-shifting buffer for progressively storing the received time based media as the time-based media is received and a time-shifting buffer controller configured to control the rendering of the time-based media at the PTT device. In response to a control signal received from the PTT device of the user, the time-based media is rendered at the PTT communication device either (i) in a near real-time mode as the time-based media is progressively received at the network communication device and progressively transmitted to the PTT device or (ii) at an arbitrary later time after the storage of the time-based media in the time-shifting buffer by retrieving the time-based media from the time-shifting buffer at the arbitrary later time and transmitting the retrieved time-based media to the PTT communication device.10-15-2009
20090138633Computer, external storage and method for processing data information in external storage - The present invention provides a computer, comprising: a processor for processing data; a system bus connected to the processor; a management unit connected to the system bus; and an external storage connected to the system bus through the management unit, wherein the external storage comprises: a buffer for buffering data; and storage areas connected to the buffer for storing data, and wherein the management unit is adapted to: receive an instruction sent by the processor from the system bus, said instruction corresponding to operations; read data information from the storage areas to the buffer; and execute at least one of the operations on the data information. Furthermore, the present invention provides an external storage and a method for processing data information in an external storage. According to the present invention, it is possible to scan the external storage with a large capacity in a short time.05-28-2009
20090319703STACKED SEMICONDUCTOR MEMORY DEVICE WITH COMPOUND READ BUFFER - A stacked memory apparatus operating with a compound read buffer is disclosed. The stacked memory apparatus includes an interface device having a main buffer and a plurality of memory devices each having a device read buffer. Systems incorporating one or more stacked memory apparatuses and related method of performing a read operation are also disclosed.12-24-2009
20100299460BUFFER MANAGER AND BUFFER MANAGEMENT METHOD BASED ON ADDRESS POINTER LINKED LIST - Embodiments of the present invention provide a buffer manager and a buffer management method based on an address pointer linked list. In the embodiments, address pointers of all buffer blocks in a buffer are divided into several groups, lower bits of address pointers in each group are used to record a linked list between the address pointers in the same group, and an address pointer which is pointed by one predetermined address pointer of each group and is in a different group is further recorded to upbuild a linked list between the groups. Thereby, an address linked list can still be stored without a RAM with a width equal to a pointer depth and with a depth equal to the total number of buffer blocks in the buffer as required by the conventional art, which greatly reduces hardware resources required.11-25-2010
20090138632SYSTEMS AND METHODS FOR READ DATA BUFFERING - Methods for controlling read data buffering are disclosed. In one of the methods core operations are performed in response to a receipt of a read command from a master controller and an internal or external communication buffer of a data storage node is selected to forward information to the master controller. The data storage node is selected based upon constraints and contents of one or more communication buffers. Information is forwarded from the selected internal or external communication buffer to the master controller.05-28-2009
20110035518Digital Phase Relationship Lock Loop - In one embodiment, an apparatus comprises a first clocked storage device operable in a first clock domain corresponding to a first clock signal. The first clocked storage device has an input coupled to receive one or more bits transmitted on the input from a second clock domain corresponding to a second clock signal. The apparatus further comprises control circuitry configured to ensure that a change in a value of the one or more bits transmitted on the input meets setup and hold time requirements of the first clocked storage device. The control circuitry is responsive to a sample history of one of the first clock signal or the second clock signal to detect a phase relationship between the first clock signal and the second clock signal on each clock cycle to ensure the change meets the setup and hold time requirements.02-10-2011
20110035517METHOD AND APPARATUS FOR RECEIVING, STORING, AND PRESENTING MULTIMEDIA PROGRAMMING WITHOUT INDEXING PRIOR TO STORAGE - A method and apparatus for improved digital recording and presentation of broadcast information is disclosed. Received broadcast data, which may include video, audio, private, or other data, relating to one or more particular content programs, is presented from an input section to a buffer and recorded directly onto a storage device without any intelligent parsing, such as indexing, and without any manipulation by intermediate hardware or software functions. Upon normal presentation, statistics may be generated to determine the ideal number of frames to skip, the number of bytes to seek, and the size of data files to read from the storage device during time-shifted presentation. Algorithms and processes are provided to dynamically optimize time-shifted presentation. In this way, data may be captured to the storage device more efficiently and economically, and the time-shifted presentation operations may be performed in a smoother, more nuanced manner with the application of appropriate probabilistic algorithms.02-10-2011
20100228897METHOD AND SYSTEM FOR CONTROLLING THE ADMISSION OF A STORAGE MEANS TO A PERPHERAL BUS OF A DATA REPRODUCTION SYSTEM - It is an object of the invention to ensure the reliable and flawless operation of a storage means that is connected to a data reproduction system. This object will be met by a method for controlling the admission of a storage means to a peripheral bus of a data reproduction system, wherein a storage means is connected to the peripheral bus of a data reproduction system, the read latency of the storage means is determined, and it is decided based on the determined read latency whether the storage means is admitted to the peripheral bus or rejected. The latency for read requests from the storage means, for instance a USB mass storage device, will be analyzed on first insertion and the results of this analysis will be used to carry out a compatibility check of the storage means with the data reproduction system, for example a car audio system.09-09-2010
20090313402FIFO device and method of storing data in FIFO buffer - A FIFO device includes: a FIFO buffer that holds a transfer request transferred from a bus and including a write address, a data size, and write data, and outputs the transfer request to a bus; and a transfer request generation unit that receives, from the bus, a first transfer request and a second transfer request subsequent to the first transfer request, to determine whether the second transfer request can be combined with the first transfer request based on a write address and a data size of the first transfer request and a write address and a data size of the second transfer request, and when determining that the transfer requests can be combined together, holds a combined transfer request obtained by combining the first transfer request and the second transfer request together, to store the combined transfer request in the FIFO buffer.12-17-2009
20110252165Retry Mechanism - An interface unit may comprise a buffer configured to store requests that are to be transmitted on an interconnect and a control unit coupled to the buffer. In one embodiment, the control unit is coupled to receive a retry response from the interconnect during a response phase of a first transaction for a first request stored in the buffer. The control unit is configured to record an identifier supplied on the interconnect with the retry response that identifies a second transaction that is in progress on the interconnect. The control unit is configured to inhibit reinitiation of the first transaction at least until detecting a second transmission of the identifier. In another embodiment, the control unit is configured to assert a retry response during a response phase of a first transaction responsive to a snoop hit of the first transaction on a first request stored in the buffer for which a second transaction is in progress on the interconnect. The control unit is further configured to provide an identifier of the second transaction with the retry response.10-13-2011
20110099305Universal Serial Bus Host Control Methods and Universal Serial Bus Host Controllers - A USB host control method is provided for a USB host controller. The USB host controller includes a USB device and a buffer, the USB device includes one or more endpoints. The USB host control method includes the steps of: storing first output data to be sent to a first endpoint into one or more buffer units used for the first endpoint; sending the first output data to the first endpoint; and when a first predetermined response from the first endpoint is received, configuring fake releasing labels and information tags corresponding to the first endpoint in the one or more buffer units, and not releasing the one or more buffer units.04-28-2011
20110072172INPUT/OUTPUT DEVICE INCLUDING A MECHANISM FOR TRANSACTION LAYER PACKET PROCESSING IN MULTIPLE PROCESSOR SYSTEMS - An I/O device includes a host interface coupled to a plurality of hardware resources. The host interface includes a transaction layer packet (TLP) processing unit that may receive and process a plurality of transaction layer packets sent by a plurality of processing units. Each processing unit may correspond to a respective root complex. The TLP processing unit may identify a transaction type and a processing unit corresponding to each transaction layer packet and store each transaction layer packet within a storage according to the transaction type and the processing unit. The TLP processing unit may select one or more transaction layer packets from the storage for process scheduling based upon a set of fairness criteria using an arbitration scheme. The TLP processing unit may further select and dispatch transaction layer packets for processing by downstream application hardware based upon additional criteria.03-24-2011
20120303844CONTROLLER AND CONTROLLING METHOD THEREOF - A controller includes a first input port, a first buffering unit, a timer, and a package processing unit. When a first byte from the first input device is received by the first buffering unit, the timer starts counting time. If a second byte from the first input device is received by the first buffering unit during a preset time interval, the timer re-counts time. Whereas, if no second byte from the first input device is received by the first buffering unit during the preset time interval, the timer issues a time out signal. In response to the time out signal, all bytes in the first buffering unit are packed into a first packet by the package processing unit and an interrupt request is issues to a controlling circuit.11-29-2012
20120303843VARIABLE DEPTH BUFFER - A variable depth buffer includes: a set of buffer units to receive input data in a First in First Out (FIFO) manner, with links between the buffer units such that the input data can be transferred sequentially from a first buffer unit that initially receives the input data to each subsequent buffer unit in the set; and a multiplexer, inputs of the multiplexer being connected to outputs of the respective buffer units and an output of the multiplexer to output data such that a depth of the buffer varies depending on which buffer unit output is selected by the multiplexer.11-29-2012
20110072173Processing Host Transfer Requests for Direct Block Access Storage Devices - Described embodiments provide a host subsystem that generates a host context corresponding to a received host data transfer request. A programmable sequencer generates one or more sequencer contexts based on the host context. Each of the sequencer contexts corresponds to at least part of the host data transfer request. The sequencer contexts are provided to a buffer subsystem of the media controller. For host read requests, the buffer subsystem retrieves the data associated with the sequencer contexts of the read request from a corresponding buffer or a storage media and transmits the data associated with the sequencer contexts to the host device. For host write requests, the buffer subsystem receives the data associated with the host context from the host device and stores the data associated with the sequencer contexts of the write request to a corresponding buffer or the storage media.03-24-2011
20110252164MEMORY CHAIN - A memory system having a plurality of memory devices and a memory controller. The memory devices are coupled to one another in a chain. The memory controller is coupled to the chain and configured to output a memory access command that is received by each of the memory devices in the chain and that selects a set of two or more of the memory devices to be accessed.10-13-2011
20100057954ALIGNMENT OF INSTRUCTIONS AND REPLIES ACROSS MULTIPLE DEVICES IN A CASCADED SYSTEM, USING BUFFERS OF PROGRAMMABLE DEPTHS - Buffers of programmable depths are used in the instruction and reply paths of cascaded devices to account for possible differences in latencies between the devices. The buffers may be enabled or bypassed such that the alignment of instruction and result may be performed at the boundaries between separate groups of devices having different instruction latencies.03-04-2010
20110131351Coalescing Multiple Contexts into a Single Data Transfer in a Media Controller Architecture - Described embodiments provide for transferring data between a host device and a storage media. A host data transfer request is received and a total size of the data transfer is determined. One or more contexts corresponding to the total size of the requested transfer are generated and are associated with transfers of data. If the data transfer is a write operation, one or more data segments from the host device are transferred into a buffer. The combined size of the data segments corresponds to the total size of the data transfer. In accordance with the contexts, the one or more data segments are transferred from the buffer to the storage media. If the requested data transfer is a read operation, in accordance with the contexts, data from the storage media is retrieved into a buffer and grouped into one or more segments, which are transmitted to the host device.06-02-2011
20110131350ASYNCHRONOUS UPSIZING CIRCUIT IN DATA PROCESSING SYSTEM - An asynchronous upsizing circuit in a data processing system. The asynchronous upsizing circuit includes an asynchronous packer and an asynchronous unpacker. The asynchronous packer includes a write buffer commonly used for an asynchronous bridge and for upsizing and for buffering a write channel data; and first and second asynchronous packing controllers controlling channel compaction according to first and second clocks, respectively, regarding the write channel data inputted/outputted to/from the write buffer during a burst write operation. The asynchronous unpacker includes a read buffer commonly used for an asynchronous bridge and for upsizing and for buffering a read channel data; and first and second asynchronous unpacking controllers controlling channel compaction according to the first and second clocks, respectively, regarding the read channel data inputted/outputted to/from the read buffer during a burst read operation.06-02-2011
20090210586Communication control device, information processing device and computer program product - A communication control device includes a plurality of receive buffers each storing therein received information that corresponds to all or a part of a received message or an argument of a receive function, a hash-value generating unit that generates a hash value from a receive key contained in the received message in accordance with a hash-value generation rule, a storing unit that stores the received information in a selected one of the receive buffers corresponding to the hash value, and an output unit that outputs the received information from one of the receive buffers corresponding to the hash value in response to a transmission request from a receiving unit that performs a receiving operation by determining a matching based on a receive key specified by the receive function.08-20-2009
20080320183Method, Computer Program Product and Apparatus for Receiving Recording Recommendations - Methods, computer program products, and apparatuses for receiving recording recommendations through a data network are provided. The recommendations originate from sources selected by the user. Each source may send a recommendation from his or her set top box or other computing device connected to the data network. The user may establish and send recommendation instructions used to filter and prioritize the recommendations based on the source of the recommendation. The user may send the recommendation instructions from his or her set top box or another computing device connected to the data network. Based at least partially by the recommendation instructions, the set top box of the user may receive a recommendation from a source and record at least one media program subject to the recommendation.12-25-2008
20080228966SYSTEM, APPARATUS, COMPUTER PROGRAM PRODUCT FOR PERFORMING OPERATIONAL VALIDATION WITH LIMITED CPU USE OF A COMMUNICATIONS NETWORK - A system, apparatus, computer program product and method of performing operational validation on a system are provided. The system may include a CPU with a cache, a communications network, and a plurality of devices exchanging data during a test. When the test is ready to be performed, the CPU may set up a pool of buffers in the cache. The pool of buffers may generally have a set of locations corresponding to locations in an actual destination buffer and a set of locations corresponding to locations in an actual source buffer. During the performance of the test, data is exchanged over the communications network to and from the source and destination buffers. Snooping logic in the cache may snoop data on the communications network. The data snooped may be entered in appropriate locations in the pool of buffers. This allows the CPU to perform operational validation by using cached data instead of data that is in the actual source and destination buffers.09-18-2008
20080228965SYSTEM, APPARATUS AND COMPUTER PROGRAM PRODUCT FOR PERFOMING FUNCTIONAL VALIDATION TESTING - A system, apparatus, computer program product and method of performing functional validation testing in a system are provided. Generally, functional validation testing includes data acquisition and data validation testing. During the functional validation testing two devices may be exchanging data. The exchange of data by the two devices may be referred to as data acquisition. The data from one device and the data from the other device may be compared to each other. This may be referred to as data validation. When data is exchanged during data acquisition, it is also stored in appropriate locations in a pool of buffers in memory. During the data acquisition, checks are made to determine if the system is entering an idle cycle. If so, the data validation test is performed by using the data in the pool of buffers in memory.09-18-2008
20100325320VERIFICATION OF DATA READ IN MEMORY - A method and a circuit for checking data transferred between a circuit and a processing unit, in which: the data originating from the circuit transit through a first buffer element having a size which is a multiple of the size of data to be subsequently delivered over a bus of the processing unit; an address provided by the processing unit for the circuit is temporarily stored in a second element; and the content of the first element is compared with current data originating from the circuit, at least when they correspond to an address of data already present in this first element.12-23-2010
20080256271Methods and apparatus for reducing storage usage in devices - Transmission buffer apparatus and methods configured to minimize the storage requirements for transmission/retransmission of data by allocating retransmission data to two or more types of storage. In one embodiment, RAM usage in a RAM-limited embedded device is minimized by storing only a reference or pointer to ROM- or Flash-sourced within the retransmission buffer (e.g., RAM), thereby reducing the storage burden on the buffer. For example, web pages having largely non-volatile components can be stored in ROM or Flash, while only the dynamic or volatile portions are stored in RAM. Apparatus and methods for implementing an exemplary serial-to-Ethernet interface are disclosed, as well as use of Flash or ROM to store configuration data in the form of e.g., a web page image. A circular buffer approach implementing the aforementioned methodologies is also described.10-16-2008
20110072174APPARATUS AND METHOD FOR TRANSMITTING AND RECEIVING DATA IN ONE-TO-ONE COMMUNICATION - An apparatus and method for transmitting and receiving data in one-to-one communication are provided. A first buffer for temporarily storing file data and a second buffer for temporarily storing message data are connected to a data transmitter for transmitting data and a data receiver for receiving data, respectively or vice versa, according to a request for data transmission or reception. The buffer for storing file data and the buffer for storing message data are differently constructed, thereby reducing the waste of memories of the buffers and achieving the miniaturization and high-speed data transmission of a portable terminal device.03-24-2011
20100293308METHOD, SYSTEM, AND INTEGRATED CHIP FOR SERIAL DATA TRANSMISSION - The invention provides a method for serial data transmission. First, a chip select signal is enabled to a device for serial data transmission. Data stored in a first buffer of a controller is then transmitted to a second buffer of the device. A clock signal is then halted after data stored in the first buffer is completely transmitted. The first buffer is then refreshed with data newly received by the controller while the clock signal is halted. The clock signal is the restarted to operate the device after the first buffer is refreshed. Refreshed data stored in the first buffer is then transmitted to the second buffer while the clock signal is oscillating.11-18-2010
20120311201PARTITIONING OF A VARIABLE LENGTH SCATTER GATHER LIST - Partitioning of a variable length scatter gather list including a processor for performing a method that includes requesting data from an I/O device comprising an I/O buffer. The requesting includes initiating a subchannel. The method further includes determining whether the subchannel supports data divisions by requesting SSQD data from the I/O device and inspecting at least one bit in the SSQD data. A determination is made whether the requested data includes a metadata block in response to determining that the subchannel support data divisions. Also, the subchannel is notified that the requested data includes the metadata block in response to determining that the requested data includes the metadata block. A location of storage is identified in an SBAL in response to notifying the subchannel.12-06-2012
20110138087STACKED SEMICONDUCTOR MEMORY DEVICE WITH COMPOUND READ BUFFER - A stacked memory apparatus operating with a compound read buffer is disclosed. The stacked memory apparatus includes an interface device having a main buffer and a plurality of memory devices each having a device read buffer. Systems incorporating one or more stacked memory apparatuses and related method of performing a read operation are also disclosed.06-09-2011
20110082952MULTI-READER MULTI-WRITER CIRCULAR BUFFER MEMORY - A system for managing a circular buffer memory includes a number of data writers, a number of data readers, a circular buffer memory; and logic configured to form a number of counters, form a number of temporary variables from the counters, and allow the data writers and the data readers to simultaneously access locations in the circular buffer memory determined by the temporary variables.04-07-2011
20090292838Simplified data transfer using intermediary - In certain embodiments consistent with the present invention, a method of transferring data from a source device to a destination device, using an intermediate device having pre-segmented storage involves receiving a user input associating a file type with a segment of the pre-segmented storage device; receiving a user input selecting a source port of the intermediate device; receiving a user input selecting a destination port of the intermediate device; receiving a user input selecting a segment of the pre-segmented storage device; determining a file type from the association of the selected segment of the pre-segmented storage device; and transferring the files of the determined file type from the source device to the destination device, wherein only files of the determined file type are transferred. This abstract is not to be considered limiting, since other embodiments may deviate from the features described in this abstract.11-26-2009
20100064073Input/output completion system and method for a data processing platform - A mechanism is disclosed for performing I/O operations using queue banks within a data processing system that supports multiple processing partitions. A queue bank is a re-useable area of memory allocated for performing I/O operations. All memory locking and address-translation functions are generally performed only once for a queue bank to reduce system overhead. After a queue bank has been used to perform an I/O operation, some processing is performed to make it available for re-use. This processing determines whether the queue bank contains memory that is being removed from a current processing partition. If so, a delay is imposed so that the queue bank is not made available for immediate re-use. This creates a window of time wherein all queue banks that contain the affected memory are inactive, thereby allowing the affected memory to be removed from the partition without halting on-going I/O activity.03-11-2010
20120011289FIFO SYSTEM AND OPERATING METHOD THEREOF - FIFO systems and operating method thereof are provided to transfer data between a first device and a second device. In the FIFO system, a memory controller serves as an interface to access a memory device for storage of the data, and a CPU processes instructions to control the data transfer. Two data FIFOs serve as data buffers for data transactions to and from the first and second devices, and two status FIFOs serve as an instruction buffers for status transactions between the first, second devices and the CPU. A data controller connects the memory controller and the two data FIFOs for direct data delivery therebetween.01-12-2012
20120023274INCREASED SPEED OF PROCESSING OF DATA RECEIVED OVER A COMMUNICATIONS LINK - A method and apparatus for processing data samples utilizes a channel map populated by device descriptor, or by an application program interface. Packet processing code loops through all of the samples contained in a packet while incrementing through a channel map and steering table without having to look up a table to determine in what audio buffer the sample is to be stored or read. Additionally, the present invention utilizes a stride map, so the audio subsystem knows how many samples to skip in order to reach the next sample frame. The present invention can be used for handling received packets as well as forming packets to send over a bus.01-26-2012
20120023273COMMAND MANAGEMENT DEVICE CONFIGURED TO STORE AND MANAGE RECEIVED COMMANDS AND STORAGE APPARATUS WITH THE SAME - According to one embodiment, a command management device includes a command buffer, a free address register and a FIFO unit with entries. The command buffer stores commands received from a host. The entries include address sections configured to store addresses of the areas in the command buffer in which the respective commands are stored. The address sections are connected together like a ring. Each of the address sections includes a substitute module configured to substitute either the free address held in the free address register or a second address stored in the address section preceding the each of the address sections for a first address stored in the each of the address sections.01-26-2012
20120072625DATA PROCESSING APPARATUS CAPABLE OF COMMUNICATING WITH EXTERNAL DEVICE VIA A PLURALITY OF LOGICAL LINE, DATA PROCESSING SYSTEM, DATA PROCESSING DEVICE STORING DATA PROCESSING PROGRAM, AND DEVICE DRIVER - A data processing apparatus includes a data processing unit, a communication unit communicating with an external device via at least two logical lines including a first logical line and a second logical line having priority higher than the first logical line, a storage unit including a first buffer area storing data received by the communication unit via the first logical line and a second buffer area storing data received by the communication unit via the second logical line, and a control unit determining if the second buffer area stores data. According to determination that the second buffer area stores data, the control unit reads data from the second buffer area and controls the data processing unit to process the data read from the second buffer area, and according to determination that the second buffer area stores no data, the control unit determines if the first buffer area stores data.03-22-2012
20110099304Controller and a Method for Controlling the Communication Between a Processor and an External Peripheral Device - The present invention relates to a data processing system based on a multithreaded operating system. The data processing system comprises at least one processor (PROC) for processing data based on multiple threads, at least one controller unit (CU) for controlling the communication between said at least one processor (PROC) and an external peripheral device (PD) connected to said at least one controller unit (CU). Said at least one controller unit (CU) comprises at least one buffer memory (BM) for buffering data from said peripheral device (PD) connected to said at least one controller unit (CU), and at least one memory managing unit (MMU) for managing the access to said at least one buffer memory (BM) by mapping said at least one buffer memory (BM) into N banks (C04-28-2011
20090132735METHOD FOR EXCHANGING INFORMATION WITH PHYSICAL LAYER COMPONENT REGISTERS - A device and a method for exchanging information with registers of a physical layer component. The method includes allocating at least one receive buffer for receiving the status information; associating at least one receive buffer descriptor with the at least one receive buffer; sending to a physical layer component a request to read status information stored in a selected status register of the physical layer component; and writing the status information to the at least one receive buffer descriptor.05-21-2009
20120124254ESTIMATING PROCESSOR LOAD USING PERIPHERAL ADAPTER QUEUE BEHAVIOR - Techniques for estimating processor load by using queue depth information of a peripheral adapter provides processor loading information that can be used to adapt interrupt latency to improve performance in a processing system. A mathematical function of the depth of one or more queues of the adapter is compared to its historical value in order to provide an estimate of processor load. The estimated processor load can then be used to set a parameter that controls the frequency of an interrupt generator. The mathematical function may be the ratio of the transmit queue depth to the receive queue depth and the historical value may be predetermined, user-settable, obtained during a calibration interval or obtained by taking a long-term average of the mathematical function of the queue depths.05-17-2012
20110185089Method and System for Supporting Hardware Acceleration for iSCSI Read and Write Operations and iSCSI Chimney - Certain aspects of a method and system for supporting hardware acceleration for iSCSI read and write operations via a TCP offload engine may comprise pre-registering at least one buffer with hardware. An iSCSI command may be received from an initiator. An initiator test tag value, a data sequence value and/or a buffer offset value of an iSCSI buffer may be compared with the pre-registered buffer. Data may be fetched from the pre-registered buffer based on comparing the initiator test tag value, the data sequence value and/or the buffer offset value of the iSCSI buffer with the pre-registered buffer. The fetched data may be zero copied from the pre-registered buffer to the initiator.07-28-2011
20100049887DEVICE AND METHOD FOR TRANSFERRING DATA BETWEEN DEVICES - A device and method for transferring data is disclosed that facilitates data transfers between devices having different clock domains. The data transfer from one device to another occurs through a First In First Out memory (FIFO). The relative number of FIFO access cycles to the FIFO is controlled to maintain a desired FIFO fullness. Setting the desired FIFO fullness to a desired value allows control of data transfer latency between devices.02-25-2010
20100049886STORAGE SYSTEM DISPOSED WITH PLURAL INTEGRATED CIRCUITS - To provide a transceiving technology that controls the mounting area of a circuit pertaining to transmission and/or reception and where the utilization efficiency of a buffer is improved. In a transmission side circuit, there are disposed a transmission side first circuit component that generates a first packet that follows a request and a transmission side second circuit component that is a lower-level circuit component of the transmission side first circuit component, includes a transmission buffer and temporarily stores in the transmission buffer, and transmits, a second packet that includes the first packet. The second packet includes a second header portion and a second data portion. In the second data portion that the second packet that is transmitted from the transmission side second circuit component includes, there is included the first packet, and in the second header portion, there is included a predetermined value as a parameter value that represents the type of the second packet. The predetermined value is a value that represents a predetermined one second packet type of plural second packet types.02-25-2010
20120185620BUFFERING APPARATUS FOR BUFFERING MULTI-PARTITION VIDEO/IMAGE BITSTREAM AND RELATED METHOD THEREOF - An exemplary buffering apparatus for buffering a multi-partition video/image bitstream which transmits a plurality of compressed frames each having a plurality of partitions includes a first bitstream buffer and a second bitstream buffer. The first bitstream buffer is arranged to buffer data of a first partition of the partitions of a specific compressed frame. The second bitstream buffer is arranged to buffer data of a second partition of the partitions of the specific compressed frame.07-19-2012
20090019193Buffer circuit - Systems, devices, and methods, including logic and/or executable instructions are described in connection with a buffer circuit. One buffer circuit includes a flip-flop based first-in first-out (FIFO) buffer having an input and an output, selection logic coupled in series with the FIFO buffer input, and a random access memory (RAM) FIFO coupled in parallel with the selection logic. The selection logic diverts incoming data to the RAM FIFO after the FIFO buffer is filled to a first capacity level, and reloads the FIFO buffer using data from the RAM FIFO until the RAM FIFO is emptied to a second capacity level. Data is extracted without read data latency from the output of the FIFO buffer as an output of the buffer circuit.01-15-2009
20120260010Storage control system and storage control method - A storage control system, for controlling data transmission between a computer and an external device, includes a USB interface connected to the computer, an external interface connected to the external device and a control module connected between the USB interface and the external interface. The control module includes a data transmission submodule transmitting data with the computer, a microcontroller controlling a work flow of the control module, a ROM connected to the microcontroller, a protocol resolution submodule resolving data, a protocol timing sequencer connected to the external interface for transforming protocols and a buffer connected between the protocol resolution submodule and the protocol timing sequencer for storing data. The ROM changes its code according to different external devices. The microcontroller controls a work flow of the control module according to the code of the ROM to realize functions of different external devices. The invention further provides a storage control method.10-11-2012
20120260009DATA STORAGE SYSTEM WITH COMPRESSION/DECOMPRESSION - A data storage system includes a host interface configured to be coupled to a host device, to receive data from the host device, and to send data to the host device and a memory. The data storage system further includes a primary compression engine coupled to the host interface and to the memory, wherein the primary compression engine is configured to compress data received from the host device via the host interface and to store the compressed data in the memory, and wherein the primary compression engine is further configured to decompress compressed data stored in the memory prior to the decompressed data being sent to the host device via the host interface. The data storage system further includes a secondary compression engine coupled to the memory, wherein the secondary compression engine is configured to compress data stored in the memory and to store the compressed data back in the memory, and wherein the secondary compression engine is further configured to decompress compressed data stored in the memory and to store the decompressed data back in the memory. The data storage system further includes a non-volatile storage medium and a processor configured to transfer compressed data from the memory to the non-volatile storage medium in response to a write command received from the host device and to transfer compressed data from the non-volatile storage medium to the memory in response to a read command received from the host device.10-11-2012
20080301334DISK CONTROL APPARATUS, DISK CONTROL METHOD, REMOTE DISK CONTROL APPARATUS, AND REMOTE DISK CONTROL METHOD - A disk control apparatus formats each track of a storage disk device in a short time. The disk control apparatus (12-04-2008
20120239833BUFFER MANAGEMENT DEVICE, BUFFER MANAGEMENT METHOD, AND STORAGE DEVICE - According to one embodiment, a buffer management device includes a buffer memory, a current-credit retaining module, a reserved-credit retaining module, a transfer controller, and a subtractor. The buffer memory manages a storage area in a credit unit representing a predetermined data size and temporarily stores data transferred from an external device. The current-credit retaining module retains the number of credits currently available for the buffer memory as a current credit value. The transfer controller registers the number of credits necessary to temporarily store the data in the reserved-credit retaining module as a reserved credit value prior to the transfer of the data from the external device to the buffer memory. The subtractor subtracts the reserved credit value registered in the reserved-credit retaining module from the current credit value retained by the current-credit retaining module and outputs a subtraction result as an available credit value.09-20-2012
20120324129CONFIGURABLE BUFFER ALLOCATION FOR MULTI-FORMAT VIDEO PROCESSING - Systems and methods are described including dynamically configuring a shared buffer to support processing of at least two video read streams associated with different video codec formats. The methods may include determining a buffer write address within the shared buffer in response to a memory request associated with one read stream, and determining a different buffer write address within the shared buffer in response to a memory request associated with the other read stream.12-20-2012
20120278516Addressable FIFO11-01-2012
20110276731DUAL-PORT FUNCTIONALITY FOR A SINGLE-PORT CELL MEMORY DEVICE - A network node (11-10-2011
20110276730PACKET BASED DATA TRANSFER SYSTEM AND METHOD FOR HOST-SLAVE INTERFACE - In a host-slave data transfer system, the slave device receives packet based data from an external device and stores the packet content in a buffer as data segments. The slave merges a plurality of data segments into data streams and transmits the data streams to the host. The host uses direct memory access (DMA) to unpack the data stream from the slave into individual data segments without memory copy. To enable the host to set up DMA, the slave transmits information regarding sizes of the data segments to the host beforehand via an outband channel, e.g. by transmitting the size information in headers and/or tailers inserted into previous data streams. The host utilizes the data segment size information to program descriptor tables, such that each descriptor in the descriptor tables causes one data segment in the data stream to be stored in the system memory of the host.11-10-2011
20110320650ANALYSIS PREPROCESSING SYSTEM, ANALYSIS PREPROCESSING METHOD AND ANALYSIS PREPROCESSING PROGRAM - An analysis preprocessing system is provided which is capable of rapidly passing data to means for analyzing data while preventing the data from overflowing, even if large amounts of data are transmitted from a large number of data generation sources. Data acquisition means 12-29-2011
20130013824PARALLEL AGGREGATION SYSTEM - A parallel aggregation system includes a data analysis module to determine a unique key value of a record to be forwarded to a destination. A pre-processing module may determine existence of the record in a buffer and priority of the record in a priority queue. Based on the existence and priority, the pre-processing module may absorb the record in the buffer and selectively forward another record in the buffer to the destination.01-10-2013
20080250169REAL-TIME NOTIFICATION OF DEVICE EVENTS - Real-time notification is provided of an event which has occurred in a computer-related device. Upon the occurrence of an event, a record of the event is stored in a buffer, such as a Really Simple Syndication buffer, associated with the device. The buffer is updated based on indications and other events noted by a CIM agent in the device. One of a series of regular requests is received from an open browser window on a user computer, the request inquiring about any record of the event stored in the buffer. In response to the request, the record of the event is transmitted to an HTML event element in a page of the browser window whereby the record of the event is inserted into the HTML element and displayed in the browser window.10-09-2008
20080222324SYSTEM METHOD STRUCTURE IN NETWORK PROCESSOR THAT INDICATES LAST DATA BUFFER OF FRAME PACKET BY LAST FLAG BIT THAT IS EITHER IN FIRST OR SECOND POSITION - A method and structure for determining when a frame of information comprised of one or more buffers of data being transmitted in a network processor has completed transmission is provided. The network processor includes several control blocks, one for each data buffer, each containing control information linking one buffer to another. Each control block has a last bit feature which is a single bit settable to “one or “zero” and indicates the transmission of when the data buffer having the last bit. The last bit is in a first position when an additional data buffer is to be chained to a previous data buffer indicating an additional data buffer is to be transmitted and a second position when no additional data buffer is to be chained to a previous data buffer. The position of the last bit is communicated to the network processor indicating the ending of a particular frame.09-11-2008
20080222323MULTIMEDIA ADAPTING APPARATUS - The present invention discloses a multimedia adapting apparatus. The multimedia adapting apparatus includes a communicating module, a buffer, a primary controller, a command register, a status register, a secondary controller, a media hardware engine, and a memory unit. The buffer stores the audiovisual content from the multimedia player. The primary controller handles the operation of audiovisual content between the multimedia player and the portable multimedia devices. The status register stores a plurality of statuses associated with the portable multimedia devices. The command register stores a command set associated the operation of audiovisual content between the multimedia player and the portable multimedia devices according to the statuses of the status register. The communicating module couples the buffer and the primary controller, respectively, to the multimedia player, for communicating with the multimedia player based on a plurality of control signals associated with the command set.09-11-2008
20130145059DATA STORAGE SYSTEM WITH PRIMARY AND SECONDARY COMPRESSION ENGINES - Aspects of the subject technology relate to a data storage system controller including a host interface configured to be coupled to a host device, to receive data from the host device, and to send data to the host device. In certain aspects, the data storage system includes a primary compression engine configured to compress data received from the host device via the host interface, and a secondary compression engine configured to decompress and compress data associated with operations internal to the data storage system. In some implementations, the data storage systems can further include a processor configured to transfer data between the host interface and the primary compression engine, between the primary compression engine and a non-volatile storage medium, between a memory and the secondary compression engine, and between the secondary compression engine and the memory. A data storage system is also provided.06-06-2013
20110271016Method and system for a universal serial bus image capturing with two isochronous transfers - A system for universal serial bus (USB) image capturing with two isochronous transfers includes a USB image capturing device and a host. The USB image capturing device has two endpoints for transferring a video stream through a USB. The host has a driver for receiving the video stream through the USB. The driver receives the video stream, and creates a read extension data structure for the endpoints. The driver manages and dispatches the packets of the endpoints, and copies data of the packets into a first buffer and a second buffer, respectively. When a first end frame flag in a packet of the first endpoint is set and a second end frame flag in a packet of the second endpoint is set, the driver combines data of the first and the second buffers into a frame and sends the frame to the host.11-03-2011
20130103863ALIGNMENT OF INSTRUCTIONS AND REPLIES ACROSS MULTIPLE DEVICES IN A CASCADED SYSTEM, USING BUFFERS OF PROGRAMMABLE DEPTHS - Buffers of programmable depths are used in the instruction and reply paths of cascaded devices to account for possible differences in latencies between the devices. The buffers may be enabled or bypassed such that the alignment of instruction and result may be performed at the boundaries between separate groups of devices having different instruction latencies.04-25-2013
20130132619METHOD FOR REDUCING TRANSMISSION LATENCY AND CONTROL MODULE THEREOF - A method for reducing transmission latency and a control module thereof are operated inside a host and at an external USB device. The method includes following steps: when the host receives an NRDY packet, storing a first data segment to be transferred by the host at the buffer storage unit inside the host; when the host receives an ERDY packet, capturing the first data segment stored at the buffer storage unit; and transferring the first data segment to the external USB device.05-23-2013
20130159567Method and System for Buffer State Based Low Power Operation in a MoCA Network - A first device of a Multimedia Over Coax Alliance (MoCA) network may communicate with a second device of the MoCA network to control power-save operation of the second MoCA device. The first device may control the power-save operation of the second MoCA device based on an amount of data stored in a buffer, wherein the data stored in the buffer is destined for the second device. The buffer may be in a third device which sends the data to the second device, and/or the buffer may be in the first device. The first device may be operable to buffer data destined for the second device while the second device is in a power-saving state.06-20-2013
20110314190FIFO BUFFER SYSTEM - As a FIFO buffer system, a rewind function is realized without reducing a data transfer rate. Input data is written in a write FIFO buffer, and is packetized by a packetizing FIFO buffer to be written in a buffer memory area formed in a save memory. A multiplexer selects, in a first mode, an output of the write FIFO buffer, and in a second mode, packet data read from the buffer memory area. The multiplexer continuously selects the first mode until the read FIFO buffer becomes full.12-22-2011
20110314189TRANSACTION ID FILTERING FOR BUFFERED PROGRAMMED INPUT/OUTPUT (PIO) WRITE ACKNOWLEDGEMENTS - A PIO transaction unit includes an input buffer, a response buffer, and a control unit. The input buffer may receive and store PIO write operations sent by one or more transactions sources. Each PIO write operation may include a source identifier that identifies the transaction source. The response buffer may store response operations corresponding to respective PIO write operations that are to be transmitted to the transaction source identified by the source identifier. The control unit may store a particular response operation corresponding to the given PIO write operation in the response buffer prior to the given PIO write operation being sent from the input buffer. The control unit may store the particular response operation within the response buffer if the given PIO write operation is bufferable and there is no non-bufferable PIO write operation having a same source identifier stored in the input buffer.12-22-2011
20110314188HUB APPARATUS WITH OTG FUNCTION - A hub apparatus provided by the present invention comprises an OTG (on-the-go) control module and at least one USB port and a linking module. The OTG control module has a buffer and be coupled to the USB port and the linking module. When the host apparatus and the peripheral apparatus link with the hub apparatus, the OTG control module captures a data, which is asserted by a user through the host apparatus, from the peripheral apparatus via the USB port, and saves the captured data into the buffer, so as to move the data saved into the buffer to the host apparatus via a data transmission for responding a data capturing requirement from the host apparatus.12-22-2011
20130191558CONTINUOUS READ BURST SUPPORT AT HIGH CLOCK RATES - A memory device includes a memory array, an output buffer, an initial latency register, and an output signal. Often times a host device that interfaces with the memory device is clocked at high rate such that data extraction rates of the memory device are not adequate to support a gapless data transfer. The output signal is operable to stall a transmission between the memory device and the host device when data extraction rates from the memory array are not adequate to support output rates of the output buffer.07-25-2013
20120023275DATA TRANSFERRING METHOD - A first device (01-26-2012
20120030385BUFFER MANAGEMENT DEVICE WHICH MANAGES BUFFER TRANSFER, STORAGE APPARATUS COMPRISING THE SAME DEVICE, AND BUFFER MANAGEMENT METHOD - According to one embodiment, a table holds buffer transfer information for managing data transfer, specified by each data transfer command, between a transmission FIFO and a buffer or between a reception FIFO and the buffer via a intermediate FIFO. A first sequencer activates buffer transfer for data transfer specified by a data transfer command from the host in units of at least one frame on the basis of corresponding buffer transfer information held in the table. The buffer transfer includes data transfer in sectors between the buffer and the intermediate FIFO. A second sequencer transfers data in frames between the transmission FIFO and the intermediate FIFO or between the reception FIFO and the intermediate FIFO in accordance with the activation of the buffer transfer. A third sequencer transfers data in sectors between the intermediate FIFO and the buffer in accordance with the activation of the buffer transfer.02-02-2012
20130198418TRACE PROTOCOL EFFICIENCY - This invention controls data transmission from a data source to a sink. The data source buffers the data. T he data source signaling to transmit data upon storing a burst amount of data. The data source may include a plurality of data sources. A merge unit merges data by receiving and retransmitting data from each data source which signals to transmit and inserting a source identity block each time the merged data is received from a different source.08-01-2013

Patent applications in class Input/Output data buffering

Patent applications in all subclasses Input/Output data buffering