Class / Patent application number | Description | Number of patent applications / Date published |
710035000 | Burst data transfer | 29 |
20080201499 | Asynchronous Data Buffer - The present invention relates to an asynchronous data buffer for transferring m data elements of a burst-transfer between two asynchronous systems. The asynchronous data buffer comprises a data memory for storing m data elements of a data burst and a valid bit memory for storing m input valid bits corresponding to the m data elements. Input control logic circuitry generates the m input valid bits and controls storage of the same and the m data elements. After storage of the m input valid bits an input control signal is provided for inverting the input valid bits of a following data burst. Therefore, after each burst-transfer of m data elements the input valid bit is inverted, automatically rendering all data elements of a previous burst-transfer invalid. | 08-21-2008 |
20080222320 | COMMUNICATION NODE APPARATUS, NETWORK SYSTEM HAVING THE COMMUNICATION NODE APPARATUS, AND DATA TRANSMITTING SYSTEM - Disclosed is a data transmission system in which a set of asymmetrical serial buses are formed by a set of multiplexed unidirectional buses and a reverse-direction sole serial bus. A synchronization signal is superimposed on the signal transmitted over each of the multiplexed unidirectional buses. The multiplexed unidirectional buses are used mainly for data transfer, and the reverse-direction sole serial bus is used for transmitting the control information, such as ACK response, to the data transfer. | 09-11-2008 |
20080228962 | VIRTUAL PIPE FOR WIRE ADAPTER COMMUNICATIONS - A wire adapter in a Wireless Universal Serial Bus configuration includes endpoints bound to communication constructs for communicating with discrete identified endpoints of downstream devices. A Virtual Pipe system is provided for the wire adapter to manage the communications pathways between a host and a downstream device connected to the wire adapter. The system provides for establishing data pathways through previously unused endpoints in the wire adapter. | 09-18-2008 |
20080270643 | TRANSFER SYSTEM, INITIATOR DEVICE, AND DATA TRANSFER METHOD - An object of the invention is to provide a transfer system, initiator device, and data transfer method that can improve data transfer-related performance by fully utilizing a high-speed interface even when transferring data between devices that execute data processing at different speed. | 10-30-2008 |
20090006669 | DMA TRANSFER CONTROL DEVICE AND METHOD OF DMA TRANSFER - A DMA transfer control device for controlling a DMA transfer between a source and a destination is provided. The DMA transfer control device has: a buffer in which a transfer data is stored; and a bus cycle generation unit performing a burst transfer of the transfer data between the buffer and the source or the destination. The bus cycle generation unit performs an undefined-length burst transfer until an access address reaches a burst address boundary in the source or the destination. The bus cycle generation unit performs a fixed-length burst transfer after the undefined-length burst transfer until transfer of the transfer data is completed. | 01-01-2009 |
20090063729 | System for Supporting Partial Cache Line Read Operations to a Memory Module to Reduce Read Data Traffic on a Memory Channel - A memory system is provided that supports partial cache line read operations to a memory module to reduce read data traffic on a memory channel. The memory system comprises a memory hub device integrated in the memory module and a set of memory devices coupled to the memory hub device. The memory hub comprises burst logic integrated in the memory hub device. The burst logic determines an amount of read data to be transmitted from the set of memory devices and generates a burst length field corresponding to the amount of read data. The memory hub also comprises a memory hub controller integrated in the memory hub device. The memory hub controller controls the amount of read data that is transmitted using the burst length field. The memory hub device transmits the amount of read data that is equal to or less than a conventional data burst amount of data. | 03-05-2009 |
20090063730 | System for Supporting Partial Cache Line Write Operations to a Memory Module to Reduce Write Data Traffic on a Memory Channel - A memory system is provided that supports partial cache line write operations to a memory module to reduce write data traffic on a memory channel. The memory system comprises a memory hub device integrated in the memory module and a set of memory devices coupled to the memory hub device. The memory hub device comprises burst logic integrated in the memory hub device. The burst logic determines an amount of write data to be transmitted to the set of memory devices and generates a burst length field corresponding to the amount of write data. The memory hub also comprises a memory hub controller integrated in the memory hub device. The memory hub controller controls the amount of write data that is transmitted using the burst length field. The memory hub device transmits the amount of write data that is equal to or less than a conventional data burst amount. | 03-05-2009 |
20090063731 | Method for Supporting Partial Cache Line Read and Write Operations to a Memory Module to Reduce Read and Write Data Traffic on a Memory Channel - A method is provided that supports partial cache line read and write operations to a memory module to reduce read and write data traffic on a memory channel. In a memory hub controller integrated in the memory module determines an amount of data to be transmitted to or from a set of memory devices of the memory module, in responsive to an access request. The memory hub controller generates a burst length field corresponding to the amount of data. The memory controller controls the amount of data that is transmitted to or from the memory devices using the burst length field. The amount of data is equal to or less than a standard data burst amount of data for the set of memory devices. | 03-05-2009 |
20090119423 | Transfer control device, LSI, and LSI package - A transfer control device is arranged between a bus and a bus interface. The transfer control device includes a bus connecting unit that is connected to plural signal lines of the bus, an interface connecting unit that is connected to plural signal lines of the bus interface, and a connection control unit that connects, when a defective signal line exists in the plural signal lines of the bus, a signal line corresponding to the defective signal line out of the plural signal lines of the bus interface and a signal line other than the defective signal line out of the plural signal lines of the bus. | 05-07-2009 |
20090172216 | METHOD AND APPARATUS FOR TRANSMITTING DATA IN A FLEXRAY NODE - A method of transmitting data to a recipient comprising the steps of dividing the data into a plurality of groups, providing a synchronising means for each of the groups, using the synchronising means to synchronise the data in each group, and transmitting the data to a recipient characterised in that the data is divided in accordance with its synchronisation requirements with the recipient. | 07-02-2009 |
20090193159 | BUS ENCODING/DECODING METHOD AND BUS ENCODER/DECODER - An encoding method and an encoder for encoding data transmitted in a manner of bursts via a parallel bus and a decoding method and a decoder. The encoding method includes organizing data of the bursts into matrixes, determining for each of the matrixes whether a transform mode capable of decreasing the bus transition number exists, determining that the matrix needs to be transformed, determining a transform mode for transforming the matrix, and replacing the initial matrix with the transformed matrix. Then, forming a new matrix to be transmitted from matrixes which do not need to be transformed and matrixes which have been transformed. Thereafter, first generating a transform information word indicating transform states of the respective matrixes and then attaching the transform information word to the matrix to be transmitted to form an encoded matrix for actual transmission. | 07-30-2009 |
20090276548 | DYNAMICALLY SETTING BURST TYPE OF A DOUBLE DATA RATE MEMORY DEVICE - One or more external control pins and/or addressing pins on a memory device are used to set one or both of a burst length and burst type of the memory device. | 11-05-2009 |
20100017547 | PCI Bus Burst Transfer Sizing - Various apparatuses, methods and systems for specifying memory transaction sizes on a PCI bus are disclosed herein. For example, some embodiments of the present invention provide apparatuses for transferring data including a PCI bus, a memory map for memory transactions performed on the PCI bus, and at least one set of control registers adapted to establish at least one window within the memory map. The set of control registers contains an address range for the at least one window within the memory map and a burst transfer size for memory transactions taking place on the PCI bus that are addressed within the address range. | 01-21-2010 |
20100042759 | VARIOUS METHODS AND APPARATUS FOR ADDRESS TILING AND CHANNEL INTERLEAVING THROUGHOUT THE INTEGRATED SYSTEM - Various methods and apparatus are described for a target with multiple channels. Address decoding logic is configured to implement a distribution of requests from individual burst requests to two or more memory channels making up an aggregate target. The address decoding logic implements a channel-selection hash function to allow requests from each individual burst request to be distributed amongst the two or more channels in a non-linear sequential pattern in channel round order that make up the aggregate target. | 02-18-2010 |
20100057952 | MEMORY CONTROLLER AND MEMORY CONTROL METHOD - A memory controller has a control unit receiving a transfer data from a transmission circuit and executing a burst transfer of the transfer data to a reception circuit. The transmission circuit transmits a first data of a first bit length for a first burst times by a burst transmission. The amount of the transfer data is equal to a product of the first bit length and the first burst times. The reception circuit receives a second data of a second bit length for a second burst times by a burst reception. When the amount of the first data received by the control unit becomes equal to or more than a product of the second bit length and the second burst times, the control unit transfers the received first data as the second data to the reception circuit, regardless of the number of the first data received by the control unit. | 03-04-2010 |
20100088436 | COMMUNICATION METHOD AND INTERFACE BETWEEN A COMPANION CHIP AND A MICROCONTROLLER - The invention relates to a communication method and interface between a companion chip (CC) and a microcontroller (MC), a communication protocol being transmitted, having a first group of data ( | 04-08-2010 |
20100146161 | Burst termination control circuit and semiconductor memory device using the same cross-references to related application - A burst termination control circuit includes: a pull-up unit for pulling up a first node in response to a burst termination signal, a latch unit for latching a signal of the first node, a buffer for generating a first termination control signal for stopping data output operation by buffering an output signal of the latch unit, and a logic unit for generating a second termination control signal for stopping burst operation and generation of an output enable signal in response to an output signal of the latch unit. | 06-10-2010 |
20100318691 | MEMORY CONTROL DEVICE, DATA PROCESSOR, AND DATA READ METHOD - Even after reading data from a memory in response to a read request received from a bus master and burst transferring the read data, the memory interface | 12-16-2010 |
20100325319 | SYSTEMS FOR IMPLEMENTING SDRAM CONTROLLERS, AND BUSES ADAPTED TO INCLUDE ADVANCED HIGH PERFORMANCE BUS FEATURES - A memory controller including an address incrementer and a page crossing detect logic. The address incrementer may be configured to generate a next address in a burst from a current address in the burst. The page crossing detect logic may be configured to determine whether the burst will cross a memory page boundary based on the current address and the next address. The memory controller may be configured to automatically split bursts crossing page boundaries. | 12-23-2010 |
20110219152 | DATA TRANSFER CONTROL APPARATUS - In a data transfer control apparatus, a transfer start address and a transfer size are acquired from a peripheral circuit. A command is issued in response to an activation signal from the peripheral circuit. When data transfer is performed between the main memory unit and the peripheral circuit, completion of issuance of all of commands corresponding to the transfer start address and transfer size is detected. The transfer size is retained until the end of data transfer. A next command is issued prior to completion of data transfer for one command, and a next activation signal is received upon detection of completion of issuance of all of the commands corresponding to the one transfer start address and transfer size. Next transfer start address and transfer size are acquired upon detection of completion of issuance of all of the commands corresponding to the one transfer start address and transfer size. | 09-08-2011 |
20110238870 | Memory System With Command Filtering - A memory system includes a memory controller coupled to at least one memory device via high-speed data and request links. The timing and voltage margins of the links are periodically calibrated to reduce bit error. The high-speed request links complicate calibration because commands issued over the uncalibrated request links can be erroneously interpreted by the memory device. Misinterpreted commands can disrupt the calibration procedure (e.g., a write command might be misinterpreted as a power-down command). The memory controller addresses this problem using a separate, low-speed control interface to issue a filter command that instructs the memory device to decline potentially disruptive requests when in a calibration mode. | 09-29-2011 |
20110246687 | STORAGE CONTROL APPARATUS, STORAGE SYSTEM AND METHOD - A storage control apparatus for transmitting data to and receiving data from a plurality of storage devices connected to the same interface, the storage control apparatus includes a memory configured to store a management table registering a burst transfer length of each of the plurality of storage devices, the plurality of storage devices including a first storage device having a first burst transfer length that is a minimum in the management table and a second device having a second burst transfer length; an adjusting controller configured to adjust the second burst transfer length in input and/or output processing if the second burst transfer length registered in the management table is different from the first burst transfer length; and a data transfer controller configured to issue a command for a data transfer to the second storage device on the basis of the adjusted second burst transfer length. | 10-06-2011 |
20110276727 | QUANTUM BURST ARBITER AND MEMORY CONTROLLER - An apparatus comprising an arbiter circuit, a protocol engine circuit and a channel router circuit. The arbiter circuit may be configured to determine a winning channel from a plurality of channel requests based on a first criteria. Each of the plurality of channel requests may represent a burst of data having a fixed length aligned to an address boundary of a memory. The protocol engine circuit may be configured to receive a signal from the arbiter circuit indicating the winning channel. The protocol engine circuit may also be configured to perform a memory protocol at a granularity equal to the burst of data. The channel router circuit may be configured to present the plurality of channel requests to the arbiter circuit and the protocol engine circuit. | 11-10-2011 |
20110289243 | COMMUNICATION CONTROL DEVICE, DATA COMMUNICATION METHOD AND PROGRAM - A communication control device includes reception controllers capable of receiving data in a burst transfer mode in which packets are continuously transferred as one burst. There are dedicated buffers having a capacity of one packet for each of a plurality of endpoints and common buffers shared by the endpoints; a first packet of a burst transfer is stored in the dedicated buffer; and a common buffer is secured at the same time. The dedicated buffers and common buffers are controlled according to a transfer status. | 11-24-2011 |
20110302336 | Resolving Contention Between Data Bursts - In an embedded system, there are a plurality of data requesting devices, a plurality of data sources and a bus fabric interconnecting the data requesting devices and the data sources, wherein the bus fabric comprises a plurality of bus components. Some or all of the data sources and arbitration devices associated with the bus components resolve contentions between data bursts by selecting a first one of the contending data bursts; determining a length of a critical section of the first selected data burst; and processing the critical section of the selected data burst. Then, a second one of the contending data bursts is selected, a length of a critical section of the second selected data burst is determined, and the critical section of the second selected data burst is processed before a non-critical section of the selected data burst. | 12-08-2011 |
20120221750 | DATA TRANSFER CIRCUIT AND MEMORY DEVICE HAVING THE SAME - A data transfer circuit includes a serial-to-parallel converter configured to convert multi-bit data inputted in series into parallel data by controlling the number of bits of the parallel data and a conversion timing based on an operation mode, and a data transmission unit configured to transfer the parallel data to a first data path or a second data path based on the operation mode. | 08-30-2012 |
20130060974 | DATA TRANSFERRING APPARATUS AND DATA TRANSFERRING METHOD - A memory stores data generated by a processor and a transferring unit burst transfers the data from the memory unit to a processing unit. Based on an access capability of the processor when accessing the memory, a prescribed value for a burst width and information concerning the time that the processing unit consumes to process the data are set in advance at the data transferring apparatus. When the transferring unit performs data transfer, the time allowed for data transfer is calculated based on the information concerning the time that the processing unit consumes to process the data, and the burst width is determined as a value greater than or equal to the prescribed value for the burst width and is as close as possible to the prescribed value for the burst width within a range in which data transfer can be finished within the allowed time. | 03-07-2013 |
20140201397 | EXPANDABLE WIRELESS STORAGE DEVICE FOR STREAMING A MUJLTI-MEDIA FILE - An expandable wireless storage device is provided that includes an interface slot, internal memory, a wireless interface and an aggregated file system view providing component. An external memory, which stores a first subset of multi-media files, can be physically coupled with the expandable wireless storage device using the interface slot. A second subset of multi-media files can be stored on the internal memory. A multi-media file of the multi-media files can be streamed to a playing device using the wireless interface. The internal memory is used as a buffer when the multi-media file resides on the external memory. An aggregated file system view providing component provides an aggregated file system view of the multi-media files. | 07-17-2014 |
20150370733 | UNIVERSAL SERIAL BUS (USB) COMMUNICATION SYSTEMS AND METHODS - Universal serial bus (USB) communication systems and methods are disclosed. In particular, aspects of the present disclosure optimize polling and scheduling of bulk data transfers from bulk endpoints connected through a USB connection. By reducing the amount of polling, and by favoring endpoints that are known to have data to transfer, unnecessary signaling is avoided. Reduction in signaling allows more data to be transferred in a shorter amount of time. Reducing the time required for a data transfer may allow for low power modes to be used, which in turn further saves power. | 12-24-2015 |