Class / Patent application number | Description | Number of patent applications / Date published |
710024000 | By command chaining | 28 |
20080228960 | INFORMATION PROCESSING APPARATUS AND COMMAND MULTIPLICITY CONTROL METHOD - Provided are an information processing apparatus and a command multiplicity control method that enable easy and proper control of command multiplicity assigned to each host. The information processing apparatus, which executes processing in accordance with a command sent from each of plural hosts, dynamically determines each host's command multiplicity with respect to the information processing apparatus in accordance with command issue frequency of each host, and sets the determined multiplicity for the host. Accordingly, an information processing apparatus that enables easy and proper control of the command multiplicity assigned to each host can be realized. | 09-18-2008 |
20080244114 | Runtime integrity chain verification - A runtime integrity check may be implemented for a chain or execution path. When the chain or execution path calls other functions, the correctness of an entity called from the execution path is verified. As a result, attacks by malicious software that attempt to circumvent interrupt handlers can be combated. | 10-02-2008 |
20080313363 | Method and Device for Exchanging Data Using a Virtual Fifo Data Structure - A method and a device for exchanging data. The method includes: requesting the processor, by the data transfer controller, to initiate a transfer of multiple data chunks from the second memory unit to the Virtual FIFO data structure, in response to a status of the virtual FIFO data structure; sending the data transfer controller, by the processor a request acknowledgment and an indication about a size of a group of data chunks to be transferred to the virtual FIFO data structure; updating the state of the virtual FIFO data structure; transferring, by the second level DMA controller, the group of data chunks from the second memory unit to the virtual FIFO data structure; sending, by the processor a DMA completion acknowledgment indicating that the group of data chunks was written to the virtual FIFO data structure; and transferring, by a first level DMA controller, a data chunk from the virtual FIFO data structure to the hardware FIFO memory unit. | 12-18-2008 |
20080320179 | DATA COMMUNICATION APPARATUS AND METHOD, DATA COMMUNICATION SYSTEM, INFORMATION-PROCESSING APPARATUS AND METHOD, RECORDING MEDIUM, AND PROGRAM - In an AV-data transfer system, AV data stored in a RAID embedded in an AV server is supplied to a client personal computer connected to a network such as the Internet or an intranet by way of the network, and AV data output by the client personal computer is transmitted to the AV server through the network to be stored in the RAID. The AV server makes accesses to the RAID to write and read out data into and from the RAID. In addition to the AV server, the AV-data transfer system also includes another personal computer for exchanging AV data with the client personal computer and receiving a variety of commands from the client personal computer by way of the network in accordance with an FTP (File Transfer Protocol). As a result, it is possible to fast handle access requests made by a larger number of client personal computers. | 12-25-2008 |
20090006667 | Secure digital host sector application flag compression - A memory apparatus and method of operation therefore includes control by a memory controller which, in one embodiment, is configured to configure a host sector application flag table in the memory array, the flag table associating each flag value with an address in the memory array where information associated with that flag value is stored. In a second embodiment the controller is configured to (a) write at least one page of information to the memory, each page having a plurality of sectors, each of the at least one pages including a page header having a flag value associated with information written to the page, and (b) configure an exception block in memory, the exception block including exception entries, each exception entry having at least an exception flag value and address information identifying an address range in the memory array to which the exception flag value applies. | 01-01-2009 |
20090019189 | Data transfer system, data transfer method, host apparatus and image forming apparatus - A system capable of efficiently transferring a command set for controlling an image forming apparatus to the image forming apparatus from a host apparatus. A command separate/storage unit separates an image forming command set into a context command set and an object command set, and allocates both command sets in a main memory device. A command read instruction transmission unit transmits a command read instruction having a transfer size and a storage address of each of the allocated context command set and object command set, to the memory access controller. The memory access controller compares the storage address of the context command set included in the received command read instruction with a previous storage address, and reads the context command set from the main memory device only when both storage addresses differ from each other. | 01-15-2009 |
20090031055 | Chaining Direct Memory Access Data Transfer Operations for Compute Nodes in a Parallel Computer - Methods, systems, and products are disclosed for chaining DMA data transfer operations for compute nodes in a parallel computer that include: receiving, by an origin DMA engine on an origin node in an origin injection FIFO buffer for the origin DMA engine, a RGET data descriptor specifying a DMA transfer operation data descriptor on the origin node and a second RGET data descriptor on the origin node, the second RGET data descriptor specifying a target RGET data descriptor on the target node, the target RGET data descriptor specifying an additional DMA transfer operation data descriptor on the origin node; creating, by the origin DMA engine, an RGET packet in dependence upon the RGET data descriptor, the RGET packet containing the DMA transfer operation data descriptor and the second RGET data descriptor; and transferring, by the origin DMA engine to a target DMA engine on the target node, the RGET packet. | 01-29-2009 |
20090094388 | DMA Completion Mechanism - An apparatus and a computer program product are provided for completing a plurality of (direct memory access) DMA commands in a computer system. It is determined whether the DMA commands are chained together as a list DMA command. Upon a determination that the DMA commands are chained together as a list DMA command, it is also determined whether a current list element of the list DMA command is fenced. Upon a determination that the current list element is not fenced, a next list element is fetched and processed before the current list element has been completed. | 04-09-2009 |
20090138627 | APPARATUS AND METHOD FOR HIGH PERFORMANCE VOLATILE DISK DRIVE MEMORY ACCESS USING AN INTEGRATED DMA ENGINE - A method and apparatus for high performance volatile disk drive (VDD) memory access using an integrated direct memory access (DMA) engine. In one embodiment, the method includes the detection of a data access request to VDD memory implemented within volatile system memory. Once a data access request is detected, a VDD driver may issue a DMA data request to perform the data access request from the VDD. Accordingly, in one embodiment, the job of transferring data to/from a VDD memory implemented within an allocated portion of volatile system memory is offloaded to a DMA engine, such as, for example, an integrated DMA engine within a memory controller hub (MCH). Other embodiments are described and claimed. | 05-28-2009 |
20100036977 | CKD PARTIAL RECORD HANDLING - A method for combining partial records into a single direct memory access (DMA) operation for a count key data (CKD) protocol in a computer environment is provided. In an initiator processor of the computer environment, a number of the partial records to be prefetched is determined by gathering a plurality of descriptor information for a command according to a predetermined algorithm having a plurality of assumptions for the command. The number of partial records is prefetched. At least one of record headers and record keys of the number of partial records are concatenated into the single DMA operation. The DMA operation is forwarded to a receiver process to be completed. | 02-11-2010 |
20100036978 | EMBEDDED LOCATE RECORDS FOR DEVICE COMMAND WORD PROCESSING - A method of packaging locate record commands for device command word (DCW) processing is provided. A first locate record command is packaged into DCW prefix parameter data. The first locate record command includes first search and first seek arguments, a first intent count argument, a first transfer length factor argument, and a plurality of remaining arguments. A plurality of truncated locate record commands is embedded in the DCW prefix parameter data as concatenations to the first locate record command. Each of the plurality of truncated locate record commands include a unique search argument, intent count argument, and transfer length factor argument. Seek argument parameters for each of the plurality of truncated locate record commands are calculated by taking an offset from the first seek argument and the first search argument, applying the offset to each of the plurality of truncated locate record commands. The plurality of remaining arguments is shared. | 02-11-2010 |
20100191874 | HOST CONTROLLER - The present disclosure includes methods, devices, and systems for controlling a memory device. One method for controlling a memory device embodiment includes storing device class dependent information and a command in one or more of host system memory and host controller memory, setting a pointer to the command in a register in a host controller, directing access to the one or more of host system memory and host controller memory with the memory device via the host controller; and executing the command with the memory device. | 07-29-2010 |
20100268853 | APPARATUS AND METHOD FOR COMMUNICATING WITH SEMICONDUCTOR DEVICES OF A SERIAL INTERCONNECTION - A system controller communicates with devices in a serial interconnection. The system controller sends a read command, a device address identifying a target device in the serial interconnection and a memory location. The target device responds to the read command to read data in the location identified by the memory location. Read data is provided as an output signal that is transmitted from a last device in the serial interconnection to a data receiver of the controller. The data receiver establishes acquisition instants relating to clocks in consideration of a total flow-through latency in the serial interconnection. Where each device has a clock synchronizer, a propagated clock signal through the serial interconnection is used for establishing the acquisition instants. The read data is latched in response to the established acquisition instants in consideration of the flow-through latency, valid data is latched in the data receiver. | 10-21-2010 |
20110010472 | GRAPHIC ACCELERATOR AND GRAPHIC ACCELERATING METHOD - A graphic accelerator including a frame memory and the same interface as a memory of a processor and a graphic accelerating method are provided. The graphic accelerator includes: a frame memory; an accelerator controller having the same interface as a memory of the processor on an input side and recording data, which should be transmitted from the processor to the display device, in the frame memory; and a display DMA (Direct Memory Access) transmitting the data recorded in the frame memory to the display device in a DMA manner. A memory bandwidth of the processor is not reduced even by continuous reading operations based on DMA transmission of the display device, by recording data corresponding to the frame memory in the graphic accelerator disposed outside the processor. | 01-13-2011 |
20110219150 | DMA ENGINE CAPABLE OF CONCURRENT DATA MANIPULATION - Disclosed is a method and device for concurrently performing a plurality of data manipulation operations on data being transferred via a Direct Memory Access (DMA) channel managed by a DMA controller/engine. A Control Data Block (CDB) that controls where the data is retrieved from, delivered to, and how the plurality of data manipulation operations are performed may be fetched by the DMA controller. A CDB processor operating within the DMA controller may read the CDB and set up the data reads, data manipulation operations, and data writes in accord with the contents of the CDB. Data may be provided from one or more sources and data/modified data may be delivered to one or more destinations. While data is being channeled through the DMA controller, the DMA controller may concurrently perform a plurality of data manipulation operations on the data, such as, but not limited to: hashing, HMAC, fill pattern, LFSR, EEDP check, EEDP generation, XOR, encryption, and decryption. The data modification engines that perform the data manipulation operations may be implemented on the DMA controller such that the use of memory during data manipulation operations uses local RAM so as to avoid a need to access external memory during data manipulation operations. | 09-08-2011 |
20120023271 | FULLY ASYNCHRONOUS DIRECT MEMORY ACCESS CONTROLLER AND PROCESSOR WORK - An apparatus generally having a processor and a direct memory access controller is disclosed. The processor may be configured to increment a task counter to indicate that a new one of a plurality of tasks is scheduled. The direct memory access controller may be configured to (i) execute the new task to transfer data between a plurality of memory locations in response to the task counter being incremented and (ii) decrement the task counter in response to the executing of the new task. | 01-26-2012 |
20120072618 | MEMORY SYSTEM HAVING HIGH DATA TRANSFER EFFICIENCY AND HOST CONTROLLER - According to one embodiment, the host controller includes a register set to issue command, and a direct memory access (DMA) unit and accesses a system memory and a device. First, second, third and fourth descriptors are stored in the system memory. The first descriptor includes a set of a plurality of pointers indicating a plurality of second descriptors. Each of the second descriptors comprises the third descriptor and fourth descriptor. The third descriptor includes a command number, etc. The fourth descriptor includes information indicating addresses and sizes of a plurality of data arranged in the system memory. The DMA unit sets, in the register set, the contents of the third descriptor forming the second descriptor, from the head of the first descriptor as a start point, and transfers data between the system memory and the host controller in accordance with the contents of the fourth descriptor. | 03-22-2012 |
20130013822 | HOST CONTROLLER - The present disclosure includes methods, devices, and systems for controlling a memory device. One method for controlling a memory device embodiment includes storing device class dependent information and a command in one or more of host system memory and host controller memory, setting a pointer to the command in a register in a host controller, directing access to the one or more of host system memory and host controller memory with the memory device via the host controller; and executing the command with the memory device. | 01-10-2013 |
20130159563 | System and Method for Transmitting Graphics Rendered on a Primary Computer to a Secondary Computer - One embodiment of the present invention sets forth a method for transmitting data rendered on a primary computer to a secondary computer. The method includes transmitting to GPU graphics processing commands received from a graphics application, where the graphics processing commands are configured to cause the GPU to render a first set of graphics data, determining that graphics data should be collected for transmission to the secondary computer, conveying to the GPU that the first set of graphics data should be stored in a first buffer within a frame buffer memory, transmitting to the GPU graphics processing commands received from a process application executing on the primary computer, where the graphics processing commands are configured to cause the GPU to perform operations on the first set of graphics data to generate a second set of graphics data, and transmitting the second set of graphics data to the secondary computer. | 06-20-2013 |
20140068115 | INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, COMPUTER-READABLE RECORDING MEDIUM HAVING STORED THEREIN PROGRAM - A first computing device includes a data transmission processing unit transmitting data to be transferred to another computing device to a first storage area among the plurality of storage areas, and an interrupt generating unit generating an interrupt corresponding to transmission of data by the data transmission processing unit with respect to a transmission destination of the data together with identification information specifying the storage area, and a second computing device includes an interrupt processing unit specifying from which computing device the interrupt is requested based on the identification information received together with the interrupt when receiving the interrupt, and a data receiving unit reading out data from the first storage area corresponding to the computing device specified by the interrupt processing unit among the plurality of storage areas to efficiently communicate among computing devices in an information processing apparatus including a plurality of computing devices. | 03-06-2014 |
20140089537 | AUTOMATING DIGITAL DISPLAY - A device comprises a central processing unit (CPU), a display controller configured for controlling a digital display and a memory configured for storing data corresponding to the digital display. The device includes a direct memory access (DMA) controller configured for autonomously transferring the data from the memory directly to the display controller without CPU intervention. | 03-27-2014 |
20140108678 | HOST CONTROLLER - The present disclosure includes methods, devices, and systems for controlling a memory device. One method for controlling a memory device embodiment includes storing device class dependent information and a command in one or more of host system memory and host controller memory, setting a pointer to the command in a register in a host controller, directing access to the one or more of host system memory and host controller memory with the memory device via the host controller; and executing the command with the memory device. | 04-17-2014 |
20140223040 | MEMORY DATA TRANSFER METHOD AND SYSTEM - A method and apparatus are disclosed for providing a DMA process. Accordingly, a DMA process is initiated for moving data from contiguous first locations to contiguous second locations and to a third location or third locations. Within the DMA process the data from each of the contiguous first locations is retrieved and stored in a corresponding one of the contiguous second locations and in the third location or corresponding one of the third locations. The DMA process is performed absent retrieving the same data a second other time prior to storing of same within the corresponding one of the contiguous second locations and in the third location or corresponding one of the third locations. | 08-07-2014 |
20150012674 | SEMICONDUCTOR MEMORY DEVICES AND SEMICONDUCTOR SYSTEMS INCLUDING THE SAME - Semiconductor systems are provided. The semiconductor system includes a controller and a semiconductor memory device. The controller generates a first command signal and receives a foreground data to generate a foreground control signal for controlling a drivability of the foreground data and to generate a second command signal. The semiconductor memory device receives the first command signal to output a pattern data as the foreground data through a foreground input/output (I/O) line, stores the foreground control signal therein in response to the second command signal, and controls the drivability of the foreground data according to the foreground control signal. | 01-08-2015 |
20150032913 | STORAGE SYSTEM FOR CHANGING A DATA TRANSFER SPEED AND A METHOD OF CHANGING THE DATA TRANSFER SPEED THEREOF - A storage device of a storage system includes a device Direct Memory Access (DMA) configured to calculate a data transfer amount based on size information of data provided to a DMA queue; a command manager configured to receive the data transfer amount from the device DMA and to calculate a transfer speed using a speed mode table; and a device interface configured to transfer the transfer speed to a host. | 01-29-2015 |
20150067200 | Memory Management for Finite Automata Processing - Matching at least one regular expression pattern in an input stream may be optimized by initializing a search context in a run stack based on (i) partial match results determined from walking segments of a payload of a flow through a first finite automation and (ii) a historical search context associated with the flow. The search context may be modified via push or pop operations to direct at least one processor to walk segments of the payload through the at least one second finite automation. The search context may be maintained in a manner that obviates overflow of the search context and obviating stalling of the push or pop operations to increase match performance. | 03-05-2015 |
20160085690 | HOST AND COMPUTER SYSTEM HAVING THE SAME - A host includes a cache including a plurality of cache lines, a command descriptor list configured to store a command transmitted from one of the plurality of cache lines, a host controller including a direct memory access (DMA) device that accesses the command descriptor list, and a processor configured to determine a size of the command descriptor list based on a size of the one of the plurality of cache lines. | 03-24-2016 |
20160253278 | Dynamic Boot Image Streaming | 09-01-2016 |