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Direct Memory Accessing (DMA)

Subclass of:

710 - Electrical computers and digital data processing systems: input/output

710001000 - INPUT/OUTPUT DATA PROCESSING

Patent class list (only not empty are listed)

Deeper subclasses:

Class / Patent application numberDescriptionNumber of patent applications / Date published
710026000 Using addressing 35
710023000 Programmed control memory accessing 30
710024000 By command chaining 19
710025000 Timing 18
710028000 With access regulating 17
710027000 Via separate bus 4
20130073753SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device includes: a plurality of memory cell arrays; a plurality of bidirectional data buses provided in correspondence with respective ones of the plurality of memory cell arrays; a plurality of bidirectional buffer circuits, which are provided in correspondence with respective ones of the memory cell arrays, capable of connecting adjacent bidirectional data buses serially so as to relay data in the bidirectional data buses; and a control circuit for controlling activation of the bidirectional buffer circuits. The bidirectional buffer circuit is arranged so as to invert logic and the bidirectional buffer circuit is arranged so as not to invert logic.03-21-2013
20090138628MULTI-BUS ARCHITECTURE FOR MASS STORAGE SYSTEM-ON-CHIP CONTROLLERS - Systems and methods that can facilitate an expedient and efficient transfer of data between memory components (e.g., flash memory) and host components (e.g., multimedia cards, secure digital cards, etc.) are presented. A memory controller component can be employed to facilitate transferring between the memory components and host components by utilizing a multi-bus architecture. A controller first bus can be utilized for code that can be executed by a controller processor while a controller second bus can be designated for the transfer of data to the mass storage devices. By architecting the memory controller component with two buses, this innovation can provide a higher data throughput than conventional memory controllers.05-28-2009
20080301329Data Transfer Apparatus and Data Transfer Method - A data transfer apparatus includes a processor, a main memory, and a DMAC connected to the main memory via a plurality of buses. The DMAC transfers data to the main memory by bypassing the processor, writes flag data “1” indicating completion of the data transfer processing in a completion status storage area of the main memory, and finally outputs an interrupt signal to the processor. In response to the interrupt signal, an interrupt handler refers to the completion status storage area, and when the flag data is written, reads the data in the main memory and erases the flag data in the completion status storage area.12-04-2008
20100318689Device for real-time streaming of two or more streams in parallel to a solid state memory device array - Device for real-time streaming to an array of solid state memory device sets, said device comprising receiving means for receiving data from data streams of individual data rate in parallel, an input cache for buffering received data, a bus system for transferring data from the input buffer to the solid state memory device sets, and a controller adapted for using a page-receiving-time t_r, a page-writing-time wrt_tm, the data amount p and the individual data rates for dynamically controlling the bus system such that data received from the first data stream is transferred to solid state memory device sets comprised in a first subset of said array of solid state memory device sets, only, and data received from the at least a second data stream is transferred to solid state memory device sets comprised in a different second subset of said array of solid state memory device sets, only.12-16-2010
Entries
DocumentTitleDate
20110179197METHOD AND SYSTEM FOR STORING MEMORY COMPRESSED DATA ONTO MEMORY COMPRESSED DISKS - A method of transmitting compressed data from a main memory to an input/output adaptor (IOA)/input/output processor (IOP), includes sending compressed memory directory information to the IOA/IOP and copying a content of the memory to the IOA/IOP using a direct memory access (DMA) operation, without decompressing the data.07-21-2011
20090125647Device And Method For Executing A DMA Task - A method for executing a DMA task, the method includes receiving a request to execute a DMA task; the method characterized by including: defining inter-buffer jumping points at substantially an end of one or more dimensions of each multidimensional buffer out of a plurality of multidimensional buffers; and executing multiple DMA sub-tasks, wherein the executing includes jumping between buffers at the inter-buffer jumping points. A device hat includes at least one memory unit and a DMA controller adapted to access the memory unit; the device is characterized by being adapted to implement multidimensional buffers within the at least one memory unit; wherein the DMA controller is adapted to execute multiple DMA sub-tasks, wherein the execution comprises jumping between buffers at inter-buffer jumping points; and wherein the inter-buffer jumping points are defined at substantially an end of one or more dimensions of each multidimensional buffer out of a plurality of multidimensional buffers.05-14-2009
20130185465Fencing Direct Memory Access Data Transfers In A Parallel Active Messaging Interface Of A Parallel Computer - Fencing direct memory access (‘DMA’) data transfers in a parallel active messaging interface (‘PAMI’) of a parallel computer, the PAMI including data communications endpoints, each endpoint including specifications of a client, a context, and a task, the endpoints coupled for data communications through the PAMI and through DMA controllers operatively coupled to segments of shared random access memory through which the DMA controllers deliver data communications deterministically, including initiating execution through the PAMI of an ordered sequence of active DMA instructions for DMA data transfers between two endpoints, effecting deterministic DMA data transfers through a DMA controller and a segment of shared memory; and executing through the PAMI, with no FENCE accounting for DMA data transfers, an active FENCE instruction, the FENCE instruction completing execution only after completion of all DMA instructions initiated prior to execution of the FENCE instruction for DMA data transfers between the two endpoints.07-18-2013
20110196994DMA CONTROL DEVICE AND DATA TRANSFER METHOD - A DMA control device and a data transfer method, which make it possible to use a DMA channel independent of an operation mode of a processor and realize the protection of DMA control parameters during DMA operation (during a data transfer), while reducing the number of shift of an operating mode of the processor as small as possible, are provided. In requesting a DMA start by locking an access to a ch-08-11-2011
20110202695METHOD AND SYSTEM FOR PADDING IN A VIDEO PROCESSING SYSTEM - A method and system for padding an array of data on-the-fly in a direct memory access (DMA) controller. The method includes receiving the array of data in the DMA controller. The method also includes identifying edge groups of pixels at edges of the array of data and creating a padded region of data words along a periphery of the array of data. Each data word includes pixels of a corresponding edge group. The data words are then stored in a memory along with received array of data. Further, the method includes sending a request for padded data at a location in the memory, the padded data defining the array of data and the padded region of data words. Further, the method also includes translating the location of the padded data to addresses of one of, the data words and the array of data in the memory and retrieving the padded data at the addresses in the memory.08-18-2011
20120246353AUDIO DEVICE AND METHOD OF OPERATING THE SAME - An audio device and a method of operating the same are provided. The audio device includes a storage unit, a first memory and a second memory, a hardware decoder, a software decoder, a first direct memory access (DMA) block, a second DMA block, and a controller. The controller converts the audio device from an ultra low power mode in which the first PCM information is transmitted to an audio interface buffer through the first memory, the hardware decoder, and the first DMA block or a low power mode in which the second PCM information is transmitted to the audio interface buffer through the second memory, the software decoder, and the first DMA block to a normal mode in which the second PCM information is transmitted to the audio interface buffer through the second memory, the software decoder, and the second DMA block.09-27-2012
20100077110Low Latency Real-Time Audio Streaming - Systems and methods for audio streaming in a computing device are described. In one aspect an interface to an adapter driver is provided. The adapter driver is associated with an audio device. The adapter driver and a wave real-time (WaveRT) port driver associated with the computing device use the interface to configure direct access by a client of the computing device and by the audio device to a cyclic buffer. The direct access is for rendering and/or capturing an audio stream. The direct access is independent of any copying by a port driver on the computer system of the audio stream to any buffer03-25-2010
20130036243HOST-DAUGHTERCARD CONFIGURATION WITH DOUBLE DATA RATE BUS - A double data rate bus system includes a host-network interface card configuration wherein the host is configured to recognize the network interface card to establish a double data rate bus between the host and the network interface card. The host is configured to generate a plurality of generic data frame queues. Each of the generic data frame queues is configured to receive and to transmit generic data frames via the double data rate bus. The network interface card is configured to transmit a plurality of dynamic memory access read requests to the host via the double data rate bus. The host is configured to allow each of the plurality of dynamic memory access read requests to remain pending prior to responding to anyone of the plurality of dynamic memory access read requests.02-07-2013
20100042755METHODS AND SYSTEMS FOR DEADLOCK-FREE ALLOCATION OF MEMORY - Methods and systems for memory management. A method for memory management includes: maintaining a reference count for at least one first process associated with a portion of memory; maintaining a shared reference count for at least one second process associated with the portion of memory; and freeing the portion of memory when the shared reference count is decremented to zero.02-18-2010
20090157913Method for Toggling Non-Adjacent Channel Identifiers During DMA Double Buffering Operations - Disclosed are a method, a system and a computer program product for managing direct memory access (DMA) operations in a double buffering system. During direct memory access operations in a computer system, data is transferred from a source memory location to a destination memory location with minimal use of the computer's processing unit. Double buffering utilizes two separate memory buffers to perform simultaneous DMA operations. Prior to processing a DMA request each buffer in a double buffering system is assigned a channel identification (ID), or tag. When reading, writing, or polling status of data in a buffer, the tag identifies the buffer. A toggle factor is utilized to conveniently switch between each buffer in the double buffering system. Utilizing a toggle factor decreases latencies in DMA operations.06-18-2009
20100106865DMA TRANSFER DEVICE AND METHOD - To provide a DMA transfer apparatus and a DMA transfer method capable of reducing traffic on a bus between an external shared memory and DMA controller with less additional hardware to effectively use a memory.04-29-2010
20090313396SYSTEM, CONTROLLER AND METHOD THEREOF FOR TRANSMITTING AND DISTRIBUTING DATA STREAM - A system, a controller, and a method for transmitting and distributing a data stream from a host to a storage device having a non-volatile memory and a chip are provided. A specific mark is added into a data stream which is transmitted from the host to the storage device, such that the data stream can be dispatched to the chip by transmitting a write command. The, a response message generated by the chip can be received inerrably by executing a plurality of read commands.12-17-2009
20120191882DMA CONTROLLER - The DMA controller includes a peripheral device read unit to read states of peripheral devices, a state comparator, a transfer unit, a register, and a peripheral device write unit to write data in the peripheral devices according to the contents in the register when the DMA transfer is executed, an interrupt select unit selects one of plural interrupt signals to determine whether the peripheral device read unit, the state comparator and the transfer unit are at a timing to execute operations. Based on these operations the state comparator determines whether to start the DMA transfer, and the transfer unit executes data transfer between the peripheral devices.07-26-2012
20130073751FENCING NETWORK DIRECT MEMORY ACCESS DATA TRANSFERS IN A PARALLEL ACTIVE MESSAGING INTERFACE OF A PARALLEL COMPUTER - Fencing direct memory access (‘DMA’) data transfers in a parallel active messaging interface (‘PAMI’) of a parallel computer, the PAMI including data communications endpoints, each endpoint including specifications of a client, a context, and a task, the endpoints coupled for data communications through the PAMI and through DMA controllers operatively coupled to a deterministic data communications network through which the DMA controllers deliver data communications deterministically, including initiating execution through the PAMI of an ordered sequence of active DMA instructions for DMA data transfers between two endpoints, effecting deterministic DMA data transfers through a DMA controller and the deterministic data communications network; and executing through the PAMI, with no FENCE accounting for DMA data transfers, an active FENCE instruction, the FENCE instruction completing execution only after completion of all DMA instructions initiated prior to execution of the FENCE instruction for DMA data transfers between the two endpoints.03-21-2013
20090031053SEMICONDUCTOR INTEGRATED CIRCUIT AND SEMICONDUCTOR DEVICE WITH THE SAME - An interconnect configuration technology of making an access from an IP mounted on a semiconductor chip to an IP mounted on another semiconductor chip by transmitting and receiving a packet transferred through an interconnect built in a semiconductor chip among the chips using the 3D coupling technology. The device according to the technology has an initiator for transmitting an access request, a target for receiving the access request and transmitting an access response, a router for relaying the access request and the access response, and a 3D coupling circuit (three-dimensional transceiver) for performing communication with the outside, wherein the 3D coupling circuit is disposed adjacent to the router.01-29-2009
20130067123METHODS AND STRUCTURE FOR IMPROVED I/O SHIPPING IN A CLUSTERED STORAGE SYSTEM - Methods and structure for improved shipping of I/O requests among multiple storage controllers of a clustered storage system. Minimal processing of a received I/O request is performed in a first controller to determine whether the I/O request is directed to a logical volume that is owned by the first controller or to a logical volume owned by another controller. For requests to logical volumes owned by another controller, the original I/O request is modified to indicate the target device address of the other controller. The first controller then ships the request to the other controller and configures DMA capabilities of the first controller to exchange data associated with the shipped request between the other controller and memory of the host system.03-14-2013
20130067122Guest Partition High CPU Usage Mitigation When Performing Data Transfers in a Guest Partition - An invention is disclosed for offloading operations, such data transfers, of a guest partition to a host partition. A guest operating system is presented with virtualized resources rather than physical resources—e.g. a guest virtualized processor, guest virtualized memory space, and a guest virtualized direct memory access (DMA) controller. The guest partition can detect the guest operation system attempt to initiate a data transfer, and can instruct the host partition to perform the data transfer. The guest partition need not perform the data transfer using the guest virtual resources. The host partition can perform the data transfer to a remote computing as instructed by the guest partition without copying the data to the host virtualized memory space. The host partition can provide a message to the guest partition indicative of a status of the data transfer.03-14-2013
20090006665Modified Memory Architecture for CODECS With Multiple CPUs - The solution proposed in this invention is a nearest neighborhood access protocol, where not every processor is given access to every other memory block. It is shown by analyzing the pipeline that it is adequate to have no more than two masters (CPU's) in particular and 3 CPU's in general. In the case of the 2 CPU approach one of these CPU's is a producer, and the other CPU is a consumer. In the 3 CPU case the third owner may be a DMA channel.01-01-2009
20090006663Direct Memory Access ('DMA') Engine Assisted Local Reduction - Methods, compute nodes, and computer program products are provided for DMA engine assisted local reduction. Embodiments include receiving, by a DMA engine, one or more data descriptors, each descriptor identifying a buffer containing an array for reduction; selecting, in dependence upon the arrays in the buffers and local hardware functional units available to the DMA engine, at least one local hardware functional unit; and reducing one or more arrays in the buffers identified by the data descriptors with the selected local hardware functional unit.01-01-2009
20090006662OPTIMIZED COLLECTIVES USING A DMA ON A PARALLEL COMPUTER - Optimizing collective operations using direct memory access controller on a parallel computer, in one aspect, may comprise establishing a byte counter associated with a direct memory access controller for each submessage in a message. The byte counter includes at least a base address of memory and a byte count associated with a submessage. A byte counter associated with a submessage is monitored to determine whether at least a block of data of the submessage has been received. The block of data has a predetermined size, for example, a number of bytes. The block is processed when the block has been fully received, for example, when the byte count indicates all bytes of the block have been received. The monitoring and processing may continue for all blocks in all submessages in the message.01-01-2009
20130166792IMAGE PROCESSING METHOD, IMAGE PROCESSING APPARATUS, AND CONTROL PROGRAM - An image processing method includes: dividing received data into a header and a body; and writing the data in at least one buffer through a direct memory access (DMA) transfer.06-27-2013
20100088433Direct memory access (DMA) system - A direct memory access (DMA) system includes a memory unit, a memory control unit electrically connected to the memory unit to control the memory unit for data import or data export, a memory bus is electrically connected to the memory unit, an intermediate control unit electrically connected to the memory bus to receive data of the memory unit through the memory bus, and a plurality of DMA units, each of which includes a DMA controller electrically connected to the intermediate control unit and the memory control unit and a data in/out unit electrically connected to the DMA controller and the intermediate control unit. The DMA controllers control the data in/out units to receive data from the intermediate control unit. The present invention may reduce the load on bandwidth of the memory bus 04-08-2010
20080294806PROGRAMMABLE SYSTEM-ON-CHIP HUB - A Programmable System on a Chip Hub (PHUB) is configured to enable master processing elements within the PHUB to simultaneously access peripherals on different busses. The master processing elements include a Central Processing Unit (CPU) interface configured to decode addresses received from a CPU and configure the PHUB to connect signaling from the CPU to one of the multiple busses associated with the address. A second one of the master processing elements is a Direct Memory Access Controller (DMAC) source engine configured to conduct Direct Memory Access (DMA) reads. A third one of the master processing elements is a DMAC destination engine configured to conduct DMA writes independently of the CPU interface.11-27-2008
20100042754DATA TRANSMITTING DEVICE AND DATA TRANSMITTING METHOD - A data transfer device includes: a plurality of storage devices (02-18-2010
20090187679Universal DMA (Direct Memory Access) Architecture - A universal DMA (Direct Memory Access) engine can be dynamically configured to function in either a receive or transmit mode. DMAs are logically assembled and bound as needed, without limitation to a fixed, pre-determined number of receive engines and transmit engines. Because a DMA engine may be dynamically assembled to support the flow of data in either direction, varied usage models are enabled, and components used to assemble a receive DMA engine for one application may be subsequently used to assemble a transmit engine for a different application. An application may request a specific number of each type of engine, depending on the nature of its input/output traffic. The number of receive or transmit engines can be dynamically increased or decreased without suspending or rebooting the host. A universal DMA architecture provides a unified software framework, thereby decreasing the complexity of the software and the hardware gate count cost.07-23-2009
20110302333Methods and Apparatus for Providing Bit-Reversal and Multicast Functions Utilizing DMA Controller - Techniques for providing improved data distribution to and collection from multiple memories are described. Such memories are often associated with and local to processing elements (PEs) within an array processor. Improved data transfer control within a data processing system provides support for radix 2, 4 and 8 fast Fourier transform (FFT) algorithms through data reordering or bit-reversed addressing across multiple PEs, carried out concurrently with FFT computation on a digital signal processor (DSP) array by a DMA unit. Parallel data distribution and collection through forms of multicast and packet-gather operations are also supported.12-08-2011
20110289242MANAGING INTERRUPTS IN A VIRTUALIZED INPUT/OUTPUT DEVICE SUPPORTING MULTIPLE HOSTS AND FUNCTIONS - Methods and apparatus are provided for managing interrupts within a virtualizable communication device. Through virtualization, one port of the device may be able to support multiple hosts (e.g., computers) and multiple functions operating on each host. Any number of interrupt resources may be allocated to the supported functions, and may include receive/transmit DMAs, receive/transmit mailboxes, errors, and so on. Resources may migrate from one function to another, such as when a function requests additional resources. Each function's set of allocated resources is isolated from other functions' resources so that their interrupts may be managed and reported in a non-blocking manner. If an interrupt cannot be immediately reported to a destination host/function, the interrupt may be delayed, retried, cancelled or otherwise handled in a way that avoids blocking interrupts to other hosts and functions.11-24-2011
20080215768Variable coherency support when mapping a computer program to a data processing apparatus - A computer implemented tool is provided for assisting in the mapping of a computer program to a data processing apparatus 09-04-2008
20110296062STORAGE APPARATUS AND METHOD FOR CONTROLLING STORAGE APPARATUS - An object is to efficiently and securely process a data I/O request received from an external apparatus by a storage apparatus. A storage apparatus 12-01-2011
20090006664Linked DMA Transfers in Video CODECS - A new mechanism submits multiple DMA requests that are becoming more common in the newer video codec standards. This feature improves system performance and allows bus accesses to be more efficient. An artificial burst is created by aggregating multiple requests which normally would be distributed to be more localized in time, thus creating a burst of traffic.01-01-2009
20100005200APPARATUS AND METHOD FOR PROCESSING HIGH SPEED DATA USING HYBRID DMA - An apparatus and a method for processing high speed data using hybrid Direct Memory Access (DMA) are provided. The method includes determining a size of data to be transmitted, determining a memory access method of the data by comparing the determined size of the data with a first threshold, and determining an I/O bus access method of the data by comparing the determined size of the data with a second threshold.01-07-2010
20090031054DATA PROCESSING APPARATUS AND DATA TRANSFER METHOD - A data processing apparatus which can copy necessary data without imposing a burden on a CPU when broadcasting specific data is realized. A data processing apparatus includes a reception FIFO memory which temporarily stores received data sequentially; a buffer management unit which reads out the received data stored in the reception FIFO memory, discriminates whether or not a plurality of the same data are required for transferring the received data, and searches a plurality of buffer memory areas that are different from each other when the plurality of the same data are required; and a DMA (Direct Memory Access) control circuit which writes the received data read from the reception FIFO memory into each of buffer memory areas designated by the buffer management unit.01-29-2009
20100057950DMA ASSISTED DATA BACKUP AND RESTORE - An integrated circuit includes a DMA controller for performing conventional DMA transfers and for backing-up and restoring data during low power events. The integrated circuit includes one or more processor components, one or more peripheral components, a power management circuit and the DMA controller. The power management circuit manages power control within the integrated circuit. The DMA controller includes a DMA engine for executing DMA transfers between different ones of the components and memory based on configuration parameters provided to the DMA engine. A detection circuit configured determines if the power management circuit initiates a power state change. The DMA controller also has circuitry for providing a first set of configuration parameters to the DMA engine if no change in power state is detected and overriding the first set of configuration parameters with a second set of configuration parameters if a change in power state is detected.03-04-2010
20100115152Sending large command descriptor block (CDB)Structures in serial attached SCSI(SAS) controller - A system for sending large Command Descriptor Block (CDB) structures in a serial attached SCSI (SAS) controller includes a CDB Transmit Block, a CDB Memory, a Context Memory, a Direct Memory Access (DMA) Queue, a Transmit DMA Engine, and a SAS Interface. The CDB Transmit Block receives one or more Message Frames. If the CDB is small (32 bytes or less), the CDB Transmit Block reads data from the Message Frame and transmits a SAS Command Frame over the SAS interface. If the CDB is large (33 bytes or more), the CDB Transmit Block places a large CDB entry into the DMA Queue. The Transmit DMA Engine receives the large CDB entry from the DMA queue, utilizes an address pointer from the Message Frame to the CDB Memory to fetch large CDB information into a DMA buffer, and transmits a SAS Command Frame over the SAS interface.05-06-2010
20100115153ADAPTIVE MULTI-CHANNEL CONTROLLER AND METHOD FOR STORAGE DEVICE - An adaptive multi-channel controller and its method for a storage device are provided for data transmission between a host and the storage device. The storage device is configured to have multiple channels. A channel use amount is determined based on a data access amount of the host. Then, activated channels are selected among the channels according to the channel use amount. The data transmission is then carried out through the selected channels.05-06-2010
20120066414NETWORK STORAGE SYSTEM AND NETWORK STORAGE METHOD - The present invention provides a network storage system for increasing data writing efficiency of a net storage service and a network storage method for increasing data writing efficiency of the net storage service. The network storage system comprises: a first module, a first data buffer, a second module, and a third module. The present invention can omit the standard process of the traditional operation system processing files when writing data, and the network storage system and the network storage method of the present invention can use a new file processing procedure in the second module and the third module. In this way, the present invention can shorten the file processing flow in the traditional network storage system, so as to increase data writing efficiency of the net storage service over 50%.03-15-2012
20100082848INCREASING AVAILABLE FIFO SPACE TO PREVENT MESSAGING QUEUE DEADLOCKS IN A DMA ENVIRONMENT - Embodiments of the invention may be used to manage message queues in a parallel computing environment to prevent message queue deadlock. A direct memory access controller of a compute node may determine when a messaging queue is full. In response, the DMA may generate an interrupt. An interrupt handler may stop the DMA and swap all descriptors from the full messaging queue into a larger queue (or enlarge the original queue). The interrupt handler then restarts the DMA. Alternatively, the interrupt handler stops the DMA, allocates a memory block to hold queue data, and then moves descriptors from the full messaging queue into the allocated memory block. The interrupt handler then restarts the DMA. During a normal messaging advance cycle, a messaging manager attempts to inject the descriptors in the memory block into other messaging queues until the descriptors have all been processed.04-01-2010
20120271973DATA TRANSFER SYSTEM AND DATA TRANSFER METHOD - A data transfer system includes: a processor; a main memory that is connected to the processor; a peripheral controller that is connected to the processor; and a peripheral device that is connected to the peripheral controller and includes a register set, wherein the peripheral device transfers data stored in the register set to a predetermined memory region of the main memory or the processor by a DMA (Data Memory Access) transfer, and the processor reads out the data transferred to the memory region by the DMA transfer without accessing to the peripheral device.10-25-2012
20100100648ADDRESS WINDOW SUPPORT FOR DIRECT MEMORY ACCESS TRANSLATION - A apparatus is disclosed. The apparatus includes a remapping circuit to facilitate access of one or more I/O devices to a memory device for direct memory access (DMA) transactions. The remapping circuit includes a translation mechanism to perform memory address translations for I/O DMA transactions via address window-based translations.04-22-2010
20090063724System core for transferring data between an external device and memory - Details of a highly cost effective and efficient implementation of a manifold array (ManArray) architecture and instruction syntax for use therewith are described herein. Various aspects of this approach include the regularity of the syntax, the relative ease with which the instruction set can be represented in database form, the ready ability with which tools can be created, the ready generation of self-checking codes and parameterized test cases. Parameterizations can be fairly easily mapped and system maintenance is significantly simplified.03-05-2009
20090287858DMA CONTROL SYSTEM, PRINTING APPARATUS, TRANSFER INSTRUCTION METHOD AND COMPUTER READABLE MEDIUM - A DMA control system includes: a plurality of DMA control units that are controlled in a manner that, while one of the plurality of DMA control units use a transmission path, the other DMA control units other than the one of the plurality of DMA control unit are prevented from using the transmission path; and a transfer instruction unit that defines transfer amounts of DMA transfers for the respective DMA control units and gives transfer instructions thereto. The transfer instruction unit, when the transfer instruction unit gives a transfer instruction to a first DMA control unit of the plurality of the DMA control units, defines a transfer amount for the first DMA control unit and gives the transfer instruction thereto in accordance with a state of utilizing a second DMA control units of the plurality of the DMA control units.11-19-2009
20080209084Hardware-Based Concurrent Direct Memory Access (DMA) Engines On Serial Rapid Input/Output SRIO Interface - A serial buffer includes queues configured to store data packets received from a host. A direct memory access (DMA) engine receives data packets from the highest priority queue having a water level that reaches a corresponding watermark. The DMA engine is configured in response to a DMA register set, which is selected from a plurality of DMA register sets. The DMA register set used to configure the DMA engine can be selected in response to information in the header of the read data packet, or in response to the queue from which the data packet is read. Each DMA register set defines a corresponding buffer in system memory, to which the data packet is transferred. Each DMA register set also defines whether the corresponding buffer is accessed in a wrap mode or a stop mode, and whether doorbell signals are generated in response to transfers to the last address in the corresponding buffer.08-28-2008
20080209085SEMICONDUCTOR DEVICE AND DMA TRANSFER METHOD - A semiconductor device includes a plurality of resources for performing DMA transfer and a DMA controller, wherein the plurality of resources each include a transfer setting register08-28-2008
20090287859DMA Engine - A circuit and corresponding method for transferring data. The circuit comprises: a CPU; a plurality of addressable devices; and a DMA engine coupled to the CPU and to those devices, the DMA engine comprising a plurality of DMA contexts each having fetch circuitry for fetching a DMA descriptor indicated by the CPU and transfer circuitry for transferring data from one to another of the devices based on a fetched descriptor. The DMA engine further comprises switching means operable to control a group of the contexts to alternate in a complementary sequence between fetching and performing a transfer, such that alternately one or more contexts in the group fetch whilst one or more others perform a transfer.11-19-2009
20120297095DMA CONTROL DEVICE AND IMAGE FORMING APPARATUS - Provided is efficiently performing DMA transfer of data without causing heavy overhead to occur. A data transfer detecting portion detects data transfer from an external device to a predetermined memory area in a memory; and a DMA execution instructing portion instructs, when the data transfer to the memory area is detected by the data transfer detecting portion, an image processing DMA controller to start execution of the direct memory access transfer of data from the above memory area to an image processing dedicated memory.11-22-2012
20120297096Data Flow Control Within and Between DMA Channels - In one embodiment, a direct memory access (DMA) controller comprises a transmit circuit and a data flow control circuit coupled to the transmit circuit. The transmit circuit is configured to perform DMA transfers, each DMA transfer described by a DMA descriptor stored in a data structure in memory. There is a data structure for each DMA channel that is in use. The data flow control circuit is configured to control the transmit circuit's processing of DMA descriptors for each DMA channel responsive to data flow control data in the DMA descriptors in the corresponding data structure.11-22-2012
20120297097UNIFIED DMA - In one embodiment, an apparatus comprises a first interface circuit, a direct memory access (DMA) controller coupled to the first interface circuit, and a host coupled to the DMA controller. The first interface circuit is configured to communicate on an interface according to a protocol. The host comprises at least one address space mapped, at least in part, to a plurality of memory locations in a memory system of the host. The DMA controller is configured to perform DMA transfers between the first interface circuit and the address space, and the DMA controller is further configured to perform DMA transfers between a first plurality of the plurality of memory locations and a second plurality of the plurality of memory locations.11-22-2012
20090037614Offloading input/output (I/O) virtualization operations to a processor - In one embodiment, the present invention includes a method for receiving a request for a direct memory access (DMA) operation in an input/output (I/O) hub, where the request includes a device virtual address (DVA) associated with the DMA operation, determining in the I/O hub whether to perform an address translation to translate the DVA into a physical address (PA), and sending the request with the DVA from the I/O hub to a processor coupled to the I/O hub if the I/O hub determines not to perform the address translation. Other embodiments are described and claimed.02-05-2009
20110271015INFORMATION PROCESSING APPARATUS AND INFORMATION PROCESSING METHOD - An information processing apparatus includes a communication processing unit configured to communicate with an external communication device and a data processing unit configured to communicate with the communication processing unit via a wired data communication path. The data processing unit is configured to interpret address information received from the external communication device. The communication processing unit includes a memory where data transmitted and received between the external communication device and the data processing unit is temporarily stored. The communication processing unit further includes a control unit configured to control data writing in and data reading from the memory, perform an error check process by a code included in a received data from the external communication device, and transmit the address information received from the external communication device to the data processing unit without interpreting the address information.11-03-2011
20080244110PROCESSING WIRELESS AND BROADBAND SIGNALS USING RESOURCE SHARING - Methods and structures are described for processing signals formatted according to a plurality of different wireless and broadband standards. In some embodiments, network resources are shared to enable energy efficient, pseudo-simultaneous processing. In some embodiments, a timestamp is prepended to input data to remove jitter associated with time division multiplexed processing using shared resources. Systems according to embodiments of the invention are also disclosed.10-02-2008
20080244111Information Processing Terminal, Data Transfer Method, and Program - There is provided an information processing terminal that is provided with an IC chip that is capable of non-contact communication with a reader/writer. The information processing terminal includes a first storage portion, a second storage portion, and a data transfer portion. The first storage portion is provided within the IC chip and is capable of storing at least one type of data item that is used by the IC chip. The second storage portion is disposed outside the IC chip. The data transfer portion transfers the data item between the first storage portion and the second storage portion in accordance with a user input.10-02-2008
20090265483DIRECT MEMORY ACCESS FOR ADVANCED HIGH SPEED BUS - A memory system for use with a master-slave type bus such as an AHB bus has a memory, a bus interface to allow memory access from the bus, and a direct memory access interface to allow memory access from a DMA controller without occupying the bus. The system can reduce occupancy of the bus, it can allow dedicated DMA access protocols faster than the bus protocol to be used, and can remove or reduce the need for bus arbitration and associated circuitry and delays. An arbiter can arbitrate between the memory accesses and give priority to DMA accesses.10-22-2009
20080281997Low Latency, High Bandwidth Data Communications Between Compute Nodes in a Parallel Computer - Methods, parallel computers, and computer program products are disclosed for low latency, high bandwidth data communications between compute nodes in a parallel computer. Embodiments include receiving, by an origin direct memory access (‘DMA’) engine of an origin compute node, data for transfer to a target compute node; sending, by the origin DMA engine of the origin compute node to a target DMA engine on the target compute node, a request to send (‘RTS’) message; transferring, by the origin DMA engine, a predetermined portion of the data to the target compute node using memory FIFO operation; determining, by the origin DMA engine whether an acknowledgement of the RTS message has been received from the target DMA engine; if the an acknowledgement of the RTS message has not been received, transferring, by the origin DMA engine, another predetermined portion of the data to the target compute node using a memory FIFO operation; and if the acknowledgement of the RTS message has been received by the origin DMA engine, transferring, by the origin DMA engine, any remaining portion of the data to the target compute node using a direct put operation.11-13-2008
20080281998Direct Memory Access Transfer Completion Notification - DMA transfer completion notification includes: inserting, by an origin DMA engine on an origin node in an injection first-in-first-out (‘FIFO’) buffer, a data descriptor for an application message to be transferred to a target node on behalf of an application on the origin node; inserting, by the origin DMA engine, a completion notification descriptor in the injection FIFO buffer after the data descriptor for the message, the completion notification descriptor specifying a packet header for a completion notification packet; transferring, by the origin DMA engine to the target node, the message in dependence upon the data descriptor; sending, by the origin DMA engine, the completion notification packet to a local reception FIFO buffer using a local memory FIFO transfer operation; and notifying, by the origin DMA engine, the application that transfer of the message is complete in response to receiving the completion notification packet in the local reception FIFO buffer.11-13-2008
20100005199DIRECT MEMORY ACCESS (DMA) DATA TRANSFERS WITH REDUCED OVERHEAD - A digital processing system, in which a single interrupt to a processor is used in transferring multiple messages in the form of corresponding packets. In an embodiment, a processor continues to write messages to a transmit first-in-first-out (FIFO) along with a length of the message in a header of a packet. A direct memory access (DMA) controller compares the length indicated in the header with the unread data in the transmit FIFO to determine whether a complete message is stored in the transmit FIFO. DMA controller starts transmission of only complete messages thereafter. A single interrupt is generated when no complete message is determined to be present in the transmit FIFO. Similar features may be used to reduce interrupts to the processors, when transmitting data to the processor.01-07-2010
20080235409Multiple Phase Buffer Enlargement for Rdma Data Transfer Related Applications - Methods of provisioning remote direct memory access (RDMA) buffers are disclosed. In one aspect, a method may include determining that a pre-registered RDMA buffer has insufficient size to transfer a particular data. A larger RDMA buffer, which is larger than the pre-registered RDMA buffer, may then be provisioned. Then, the data may be transferred to a potentially remote node over a network using the provisioned larger RDMA buffer. Other methods, including methods of receiving data, are also disclosed. Apparatus and system to implement such methods are also disclosed.09-25-2008
20100146158DATA PROCESSING CIRCUIT - A CPU decodes MP3 data, stores it in a buffer memory, and issues a transfer instruction. A predetermined time period is required for the CPU to issue a first transfer instruction after turning-on of power supply. A DMA controller transfers data stored in the buffer memory in response to the transfer instruction. A power supply control unit turns off power supply to a first area when a time period for completing transfer of current data awaiting transfer reaches a first time period longer than the predetermined time period, according to an amount of data awaiting transfer in the buffer memory, and then turns on the power supply to the first area when the time period for completing the transfer of the current data awaiting transfer reaches a second time period which is equal to or longer than the predetermined time period and is shorter than the first time period.06-10-2010
20090164672Computer Memory Subsystem For Enhancing Signal Quality - Computer memory subsystems are disclosed for enhancing signal quality that include: one or more memory modules; a memory bus; and a memory controller connected to the memory modules through the memory bus, the memory controller including a reception buffer connected to the memory bus, the reception buffer capable of receiving an input signal from one of the memory modules, the memory controller including a reception characteristics table capable of storing reception characteristics for each of the memory modules connected to the memory controller, the memory controller including an equalizer connected to the reception buffer and the reception characteristics table, the equalizer capable of equalizing the received input signal in dependence upon the reception characteristics for the memory module from which the input signal was received, and the memory controller including memory controller logic connected to the equalizer, the memory controller logic capable of processing the equalized input signal.06-25-2009
20090138624STORAGE SYSTEM AND METHOD - Efficient and convenient storage systems and methods are presented. In one embodiment a storage system includes a plurality of storage nodes and a master controller. The storage nodes store information. The storage node includes an upstream communication buffer which is locally controlled at the storage node to facilitate resolution of conflicts in upstream communications. The master controller controlls the flow of traffic to the node based upon constraints of the upstream communication buffer. In one embodiment, communication between the master controller and the node has a determined maximum latency. The storage node can be coupled to the master controller in accordance with a chain memory configuration.05-28-2009
20090287857Virtual Memory Direct Access (DMA) Channel Technique with Multiple Engines for DMA Controller - A virtual DMA channel technique in which a generally larger number of DMA channels are mapped to a generally smaller number of DMA engines can provide a configuration in which switches amongst DMA engines (and therefore amongst a current working set of DMA channels currently mapped thereto) can be accomplished without context switch latency. Accordingly, as long as contents of the current working set can be appropriately managed, many changes (whether or nor priority based) between a current active DMA channel and a next runnable DMA channel can be accomplished without incurring a context switch latency such as normally associated with loading/restoring and/or saving DMA context information. In some embodiments, a working set or replacement strategy that seeks to cache a most frequently (or most recently) used subset of virtual DMA channels is employed. In some embodiments, a set- or frame-oriented variants of such strategies may be employed.11-19-2009
20090327532APPARATUS AND METHOD FOR DIRECT MEMORY ACCESS IN A HUB-BASED MEMORY SYSTEM - A memory hub for a memory module having a DMA engine for performing DMA operations in system memory. The memory hub includes a link interface for receiving memory requests for access at least one of the memory devices of the system memory, and further including a memory device interface for coupling to the memory devices, the memory device interface coupling memory requests to the memory devices for access to at least one of the memory devices. A switch for selectively coupling the link interface and the memory device interface is further included in the memory hub. Additionally, a direct memory access (DMA) engine is coupled through the switch to the memory device interface to generate memory requests for access to at least one of the memory devices to perform DMA operations.12-31-2009
20090063726IMPLEMENTING BUFFERLESS DIRECT MEMORY ACCESS (DMA) CONTROLLERS USING SPLIT TRANSACTIONS - According to one embodiment a method for implementing bufferless DMA controllers using split transaction functionality is presented. One embodiment of the method comprises, generating a write command from a disk controller directed to a destination unit, the write command including an identifier, generating a read command from the disk controller directed to a source unit, the read command including an identifier which matches the identifier in the write command, the source unit transmitting read data on a split transaction bus, the read data including the identifier of the read command, and receiving the read data at the destination unit via the split transaction bus if the identifier of the read data matches the identifier of the write command.03-05-2009
20090144461METHOD AND SYSTEM FOR CONFIGURATION OF A HARDWARE PERIPHERAL - The present disclosure relates to a method for re-configuration of a hardware peripheral, and a system that includes the hardware peripheral. Processing of large amounts of data in a multifunctional environment in a processor system is enabled in a flexible way by employing a re-configurable and autonomous operating hardware peripheral, which receives and, if necessary, sends data independently of a processor by use of DMA channels. Furthermore, the re-configuration method enables flexible assembling and storing of at least one set of configuration parameters used for the re-configuration of the hardware peripheral. The present disclosure provides the advantage of a flexible and fast way of handling large amounts of temporary data independently of a processor.06-04-2009
20090210577DIRECT MEMORY ACCESS SYSTEM AND METHOD USING THE SAME - The invention discloses a DMA system capable of being adapted to various interfaces. The DMA system includes the following advantages: 1) the software porting effort can be reduced when different interfaces are integrated into a SoC; 2) a flexible DMA that could provide protocol transparency and could be ported into different interfaces easily; 3) a scalable DMA that can support unlimited TX/RX scattering/gathering data segments; 4) a reusable DMA that provides user defined TX information (or RX information) and TX message (or RX message) field; and 5) a high performance DMA that support unaligned segment data pointers and unlimited scattering/gathering data segments, so as to reduce extra memory copies by CPU.08-20-2009
20090204732Single-Chip Multi-Media Card/Secure Digital (MMC/SD) Controller Reading Power-On Boot Code from Integrated Flash Memory for User Storage - A Multi-Media Card/Secure Digital (MMC/SD) single-chip flash device contains a MMC/SD flash microcontroller and flash mass storage blocks containing flash memory arrays that are block-addressable rather than randomly-addressable. MMC/SD transactions from a host MMC/SD bus are read by a bus transceiver on the MMC/SD flash microcontroller. Various routines that execute on a CPU in the MMC/SD flash microcontroller are activated in response to commands in the MMC/SD transactions. A flash-memory controller in the MMC/SD flash microcontroller transfers data from the bus transceiver to the flash mass storage blocks for storage. Rather than boot from an internal ROM coupled to the CPU, a boot loader is transferred by DMA from the first page of the flash mass storage block to an internal RAM. The flash memory is automatically read from the first page at power-on. The CPU then executes the boot loader from the internal RAM to load the control program.08-13-2009
20090063725Direct memory access system - A direct memory access (DMA) system is disclosed herein. The DMA system includes a controller and an interrupt processing unit. The controller is coupled to a first module and a second module for controlling transferring data between the first module and the second module. The data is modulated into a plurality of data blocks. The interrupt processing unit is coupled to the controller for receiving an interrupt from the first module indicative of transferring a data block of the plurality of data blocks, and for generating a drive signal to the controller indicative of transferring the data block of the plurality of data blocks. The plurality of data blocks are transferred between the first module and the second module in sequence according to a parameter value stored in the controller.03-05-2009
20080263236DATA TRANSFER SYSTEM - A data transfer system is provided, in which divided data generated by data generation terminals are randomly transmitted to data transfer apparatuses by a host terminal, a parameter list controlling the order of transfer of divided data is generated by a parameter list generation part, and a transfer processing part transfers divided data transferred in a DMA mode to an electron beam drawing apparatus according to the parameter list through a general-purpose high-speed data transfer bus by bypassing a CPU.10-23-2008
20080263235Device-to-Device Sharing of Digital Media Assets - Apparatus, a method, or an electronic device may be provided. Media and a data structure encoded on the media are each provided, to hold one or more digital media assets (DMAs). One or more share tools may be provided, which are configured to provide at least a target device of plural separate communication devices share access to a given DMA to which another source device of plural separate communication devices has access. The share access may be provided in response to a single share event at one of the source and target devices.10-23-2008
20090210578Apparatus of TCP/IP offload engine and method for transferring packet using the same - A TOE apparatus and a method for transferring a packet applying the TOE have developed. the device comprises that an embedded processor for receiving information on an address and size of physical memory and generating a prototype header according to contents of the received information; and Gigabit Ethernet for generating header information of a packet using the prototype header, receiving data according to the address and size of the physical memory included in the information received from a host device through a main PCI bus, a PCI-to-PCI bridge, and a sub PCI bus, and adding the header information to the data, so as to transmit the data to a network.08-20-2009
20090248910CENTRAL DMA WITH ARBITRARY PROCESSING FUNCTIONS - A method and system is disclosed for transforming of data by a DMA controller without first saving the transmitted data on an intermediate medium. The method includes the DMA controller accessing data for transfer between an origination location in the system and a destination location in the system. The accessed data is passed through the DMA controller before being sent to the destination location. While the data is being passed through the DMA controller, it is transformed into a modified state. This transformation may include encryption or decryption of the data. The transformation may also include adding error correction bits to the data through an encoding process or decoding previously encoded data. Upon completion of the transformation, the data is sent directly to a prescribed destination location, typically either a memory circuit or an I/O device. Also disclosed is a DMA controller capable of performing the data transformation.10-01-2009
20120036286DATA TRANSFER SYSTEM AND DATA TRANSFER METHOD - An efficient transfer of data including a plurality of data sections is achieved. In a data transfer system including a first DMA 02-09-2012
20120131235USING A TABLE TO DETERMINE IF USER BUFFER IS MARKED COPY-ON-WRITE - A method, system and computer program product for determining if a buffer is marked copy-on-write. A user applications selects a buffer in user space to store data involved in a write/read operation. The user application searches a table storing addresses of buffers in user space that are marked copy-on-write to determine if the address of the selected buffer is listed in the table. If the address is listed in the table, then the selected buffer is marked copy-on-write. If the address is not listed in the table, then the selected buffer is not marked copy-on-write. By having a table store a list of addresses of buffers in user space that are marked copy-on-write by the kernel, the user application is now able to know whether the buffer in user space is marked copy-on-write.05-24-2012
20100161843Accelerating internet small computer system interface (iSCSI) proxy input/output (I/O) - The present invention is a method for accelerating proxy Input/Output (proxy I/O). The method includes the step of receiving a command at a primary target storage system. The primary target storage system may be part of a clustered storage array. The command may be a command which was transmitted by an initiator system via a storage area network, and may include a request for data. The method further includes the step of forwarding the command to a session layer of the primary target storage system. Further, when a virtualization layer of the primary target storage system determines that a portion of the data requested in the data request is not stored by the primary target storage system, but is stored by a proxy target storage system included in the plurality of storage systems, the method further includes providing a proxyIO request to a proxy initiator of the primary target storage system. Further, the method may further include, based on the proxyIO request, generating a proxyDataIn request and providing the proxyDataIn request to an I/O controller for the primary target storage system.06-24-2010
20100161845METHOD AND SYSTEM FOR IMPROVING DIRECT MEMORY ACCESS OFFLOAD - A system for improving direct memory access (DMA) offload. The system includes a processor, a data DMA engine and memory components. The processor selects an executable command comprising subcommands. The DDMA engine executes DMA operations related to a subcommand to perform memory transfer operations. The memory components store the plurality of subcommands and status data resulting from DMA operations. Each of the memory components has a corresponding token associated therewith. Possession of a token allocates its associated memory component to the processor or the DDMA engine possessing the token, making it inaccessible to the other. A first memory component and a second memory component of the plurality of memory components are used by the processor and the DDMA engine respectively and simultaneously. Tokens, e.g., the first and/or the second, are exchanged between the DDMA engine and the processor when the DDMA engine and/or the microcontroller complete accessing associated memory components.06-24-2010
20080307121Direct Memory Access Transfer Completion Notification - Methods, compute nodes, and computer program products are provided for direct memory access (‘DMA’) transfer completion notification. Embodiments include determining, by an origin DMA engine on an origin compute node, whether a data descriptor for an application message to be sent to a target compute node is currently in an injection first-in-first-out (‘FIFO’) buffer in dependence upon a sequence number previously associated with the data descriptor, the total number of descriptors currently in the injection FIFO buffer, and the current sequence number for the newest data descriptor stored in the injection FIFO buffer; and notifying a processor core on the origin DMA engine that the message has been sent if the data descriptor for the message is not currently in the injection FIFO buffer.12-11-2008
20090077272DISK CONTROLLER - A disk controller has a channel adapter having a connection interface to a host computer or a disk drive; a memory adapter for temporarily storing data to be transferred between the host computer and disk drive; a processor adapter for controlling operations of the channel adapter and memory adapter; and a switch adapter for configuring an inner network by interconnecting the channel adapter, memory adapter and processor adapter, wherein the channel adapter, memory adapter, processor adapter and switch adapter each include a DMA controller for performing a communication protocol control of the inner network; and packet multiplex communication is performed among the DMA controllers provided in the adapters. The disk controller can realize a high transfer efficiency and a low cost while retaining a high reliability.03-19-2009
20100161844DMA compliance by remapping in virtualization - Methods, systems, apparatuses and program products are disclosed for managing DMA compliance by remapping in hypervisor and hypervisor-related environments.06-24-2010
20100161846Multithreaded Programmable Direct Memory Access Engine - A mechanism programming a direct memory access engine operating as a multithreaded processor is provided. A plurality of programs is received from a host processor in a local memory associated with the direct memory access engine. A request is received in the direct memory access engine from the host processor indicating that the plurality of programs located in the local memory is to be executed. The direct memory access engine executes two or more of the plurality of programs without intervention by a host processor. As each of the two or more of the plurality of programs completes execution, the direct memory access engine sends a completion notification to the host processor that indicates that the program has completed execution.06-24-2010
20100185789DMA Engine - Disclosed herein is a method of accessing a slave device from a circuit including a central processing unit, a data transfer engine, and an interface to the slave device. In one embodiment, the method includes: executing code on the central processing unit to set up the data transfer engine to access the slave device; and based on the set-up, operating the data transfer engine to supply a read request word to a transmit buffer of the interface for transmission to the slave device, and, after return of a corresponding response word to a first-in-first-out receive buffer of the interface, to disable the first-in-first-out receive buffer from receiving any further data such that the last word therein is assured to be the response word. The method further includes using an underflow mechanism of the first-in-first-out receive buffer to determine the last word therein and hence determine the response word.07-22-2010
20100262727Enhanced Memory Migration Descriptor Format and Method - An enhanced migration descriptor migrates a plurality of source sub-pages in a large source page accessible by direct memory access devices. A splitter and selector are integrated into a configuration of a computer. Responsive to a request to migrate a large page containing the plurality of source sub-pages in the source page, the splitter divides a plurality of high order page numbers from a plurality of low order page numbers. The selector selects the high order page number of the large page and creates an enhanced migration descriptor comprising the high order page number and a size of the large page. The selector, by the enhanced migration descriptor, combines the low order page number for a sub-page with the destination address and size of the enhanced migration descriptor to migrate the large page and each of the plurality of sub-pages.10-14-2010
20100250792OPPORTUNISTIC IMPROVEMENT OF MMIO REQUEST HANDLING BASED ON TARGET REPORTING OF SPACE REQUIREMENTS - Methods and apparatus for opportunistic improvement of Memory Mapped Input/Output (MMIO) request handling (e.g., based on target reporting of space requirements) are described. In one embodiment, logic in a processor may detect one or more bits in a message that is to be transmitted from an input/output (I/O) device. The one or more bits may indicate memory mapped I/O (MMIO) information corresponding to one or more attributes of the I/O device. Other embodiments are also disclosed.09-30-2010
20100161847VIRTUALISED INTERFACE FUNCTIONS - Roughly described, a data processing system comprises a memory addressable by a range of physical memory addresses; a plurality of non-privileged software domains each having a virtual memory address space; a privileged software domain; a memory management unit operable to perform virtual address translation of a virtual memory address into a physical memory address; and an I/O device supporting virtualised interfaces each associated with a respective non-privileged software domain, the I/O device comprising an operation management unit operable to perform virtual address translation in one or more of the virtual memory address spaces; wherein, for I/O operations requested by a virtualised interface, the I/O device invokes the operation management unit to perform virtual address translation for those I/O operations meeting first criteria and to invoke the memory management unit to perform virtual address translation for those I/O operations which do not meet the first criteria.06-24-2010
20100146157MULTI-RADIO INTERFACING AND DIRECT MEMORY ACCESS BASED DATA TRANSFERRING METHODS AND SINK NODE FOR PERFORMING THE SAME IN WIRELESS SENSOR NETWORK - Provided are a method of mediating a plurality of radio frequency (RF) transceivers, which is performed in a sink node in order to perform multi-radio interfacing between the sink node and a plurality of sensor nodes in a wireless sensor network (WSN), and a direct memory access (DMA) based data transfer method.06-10-2010
20100153590DMA (DIRECT MEMORY ACCESS) COALESCING - In general, in one aspect, a method includes determining a repeated, periodic DMA (Direct Memory Access) coalescing interval based, at least in part, on a power sleep state of a host platform. The method also includes buffering data received at the device in a FIFO (First-In-First-Out) queue during the interval and DMA-ing the data enqueued in the FIFO to a memory external to the device after expiration of the repeated, periodic DMA coalescing interval.06-17-2010
20100211703Storage Apparatus and Data Integrity Assurance Method - A channel control unit of a storage apparatus is provided with: a variable-length DMA (Direct Memory Access) that performs data transfer of variable-length data sent to or received from the host computer in accordance with an I/O request; a fixed-length DMA that performs data transfer of fixed-length data to and from the cache memory; and a buffer intervening between the variable-length DMA and the fixed-length DMA. In performing the data transfer of the fixed-length data to the cache memory, the fixed-length DMA divides the variable-length data into multiple sets of the fixed-length data each having a data size equivalent to a unit size of data managed in the cache memory, and adds a first integrity code to the last fixed-length data set of the fixed-length data sets generated by the division, the first integrity code being generated based on the entire variable-length data.08-19-2010
20100198997Direct Memory Access In A Hybrid Computing Environment - Direct memory access (‘DMA’) in a hybrid computing environment that includes a host computer, an accelerator, the host computer and the accelerator adapted to one another for data communications by a system level message passing module, where DMA includes identifying, by the system level message passing module, a buffer of data to be transferred from the host computer to the accelerator according to a DMA protocol; segmenting, by the system level message passing module, the buffer of data into a predefined number of memory segments; pinning, by the system level message passing module, the memory segments against paging; and asynchronously with respect to pinning the memory segments, effecting, by the system level message passing module, DMA transfers of the pinned memory segments from the host computer to the accelerator.08-05-2010
20100268852Replenishing Data Descriptors in a DMA Injection FIFO Buffer - Methods, apparatus, and products are disclosed for replenishing data descriptors in a Direct Memory Access (‘DMA’) injection first-in-first-out (‘FIFO’) buffer that include: determining, by a messaging module on an origin compute node, whether a number of data descriptors in a DMA injection FIFO buffer exceeds a predetermined threshold, each data descriptor specifying an application message for transmission to a target compute node; queuing, by the messaging module, a plurality of new data descriptors in a pending descriptor queue if the number of the data descriptors in the DMA injection FIFO buffer exceeds the predetermined threshold; establishing, by the messaging module, interrupt criteria that specify when to replenish the injection FIFO buffer with the plurality of new data descriptors in the pending descriptor queue; and injecting, by the messaging module, the plurality of new data descriptors into the injection FIFO buffer in dependence upon the interrupt criteria.10-21-2010
20100306421DMA TRANSFER DEVICE - A source address setting detector acquires a DMA source address from a transfer start address setting for a DMA source area of a plurality of register settings for a DMAC which are made by a master. A read-ahead processor reads ahead data in a resource which is specified by the DMA source address before the DMAC starts DMA transfer, and further, increments the DMA source address to repeat read-ahead operation. The DMAC starts DMA transfer if the master completes the register settings, reads data in the DMA source area which has already been read ahead in the read-ahead processor, and transfers the data to a DMA destination area in the resource.12-02-2010
20100306420FAST PATH SCSI IO - A hardware automated IO path, comprising a message transport unit for transporting an IO request to a local memory via a DMA operation and determining a LMID for associating with a request descriptor of the IO request; a fastpath engine for validating the request descriptor and creating a fastpath descriptor based on the request descriptor; a data access module for performing an IO operation based on the fastpath descriptor and posting a completion message into the fastpath completion queue upon a successful completion of the IO operation. The fastpath engine is further configured for: receiving the completion message, releasing the IO request stored in the local memory, and providing a reply message based on the completion message. The message transport unit is further configured for providing the reply message in response to the IO request.12-02-2010
20100312924Network processor, reception controller and data reception processing method performing direct memory access transfer - A network processor is connected to an external memory which includes storage areas for storing received data, and stores descriptors specifying locations of the storage areas, respectively. The network processor includes a descriptor storage circuit for storing a plurality of descriptors out of the descriptors; a DMA control circuit configured to transfer the plurality of descriptors from the external memory to the descriptor storage circuit through DMA transfer, transfer the received data to the storage areas in the external memory through DMA transfer on a basis of the plurality of descriptors stored in the descriptor storage circuit upon receipt of the received data, and generate a reception status indicating a condition of the received data each time the received data is transferred to the external memory through DMA transfer, a reception status storage circuit for storing the reception status; and a reception status combination control circuit for combining the reception statuses which are stored in the reception status storage circuit. The DMA control circuit transfers the combined reception statuses to the external memory through DMA transfer.12-09-2010
20110010471Recording A Communication Pattern and Replaying Messages in a Parallel Computing System - A parallel computer system includes a plurality of compute nodes. Each of the compute nodes includes at least one processor, at least one memory, and a direct memory address engine coupled to the at least one processor and the at least one memory. The system also includes a network interconnecting the plurality of compute nodes. The network operates a global message-passing application for performing communications across the network. Local instances of the global message-passing application operate at each of the compute nodes to carry out local processing operations independent of processing operations carried out at another one of the compute nodes. The direct memory address engines are configured to interact with the local instances of the global message-passing application via injection FIFO metadata describing an injection FIFO in a corresponding one of the memories. The local instances of the global message passing application are configured to record, in the injection FIFO in the corresponding one of the memories, message descriptors associated with messages of an arbitrary communication pattern in an iteration of an executing application program. The local instances of the global message passing application are configured to replay the message descriptors during a subsequent iteration of the executing application program.01-13-2011
20120246352DATA PROCESSING SYSTEMS FOR AUDIO SIGNALS AND METHODS OF OPERATING SAME - A data processing system includes an audio processor with a main memory for storing data, first and second buffers for temporarily storing the data to input/output an audio signal, and a data input/output (I/O) unit for outputting the stored data. A direct memory access (DMA) controller is provided for transmitting data between the main memory and the first and second buffers according to a DMA transmission process. If transmission of the data stored in the first buffer ends and an interrupt signal is thus generated, the DMA controller increases sizes of the first and second buffers during transmission of the data stored in the second buffer.09-27-2012
20090024772OVERLAYED SEPARATE DMA MAPPING OF ADAPTERS - DMA mapping for adapters configured to communicated with respect to a computer processor memory structure via DMA and configured to have DMA mapping space for control information and data. The adapters are separated into groups. The control information DMA mapping of the adapters is separated into at least three types: type “H” mapping, type “D” mapping, and shared mapping. The type “H” mapping and the shared mapping are applied to one group of adapters for the DMA mapping space for control information, such as host adapters, and the type “D” mapping and the shared mapping are applied to another group, such as device adapters, and the type “H” mapping of the one group and the type “D” mapping of another group are overlayed in the DMA mapping space for control information for the respective adapters.01-22-2009
20100332693DIRECT MEMORY ACCESS IN A COMPUTING ENVIRONMENT - A method of address translation in a computing system providing direct memory access (DMA) by way of one or more remote memory management units (MMUs) is provided. The method comprises intercepting a request for a first DMA operation forwarded by a first device to a second device; and translating a guest address included in the request to a first address according to a mapping referencing a memory frame in a memory of the second device. A local MMU increments a first reference count indicating number of active DMA operations directed to the memory frame and a second reference count indicating number of remote MMUs that have mapped the memory frame.12-30-2010
20090222596APPARATUS, SYSTEM, AND METHOD FOR COORDINATING STORAGE REQUESTS IN A MULTI-PROCESSOR/MULTI-THREAD ENVIRONMENT - An apparatus, system, and method are disclosed for coordinating storage requests in a multi-processor/multi-thread environment. A append/invalidate module generates a first append data storage command from a first storage request and a second append data storage command from a second storage request. The storage requests overwrite existing data with first and second data including where the first and second data have at least a portion of overlapping data. The second storage request is received after the first storage request. The append/invalidate module updates an index by marking data being overwritten as invalid. A restructure module updates the index based on the first data and updates the index based on the second data. The updated index is organized to indicate that the second data is more current than the first data regardless of processing order. The modules prevent access to the index until the modules have completed updating the index.09-03-2009
20110055435DATA PROCESSOR - The data processor provides an access protection with higher reliability during data transfer control according to a transfer condition set by CPU. The data processor has: CPU; a memory management section operable to control data transfer by CPU; and a transfer controller operable to control data transfer. The transfer controller holds identification information which the memory management section uses for access protection. When producing an address for transfer according to the setting of CPU, the transfer controller starts data transfer on condition that the identification information corresponding to the address for transfer matches the identification information of CPU at the setting of a transfer condition, etc.03-03-2011
20110125935DIRECT MEMORY DOWNLOAD IN A VOICE DATA AND RF INTEGRATED CIRCUIT AND METHOD FOR USE THEREWITH - A voice data and RF integrated circuit (IC) includes an RF transceiver module that produces received data based on a received RF signal and that produces a transmitted RF signal based on transmit data. A memory module includes a first read only memory (ROM) segment for storing a first plurality of operational instructions, and a first random access memory (RAM) segment for storing a second plurality of operational instructions. A first processing module executes the plurality of operational instructions that include baseband processing to generate input data from the received data, and to produce the transmit data from input data. A first memory interface provides direct downloading of the second plurality of operational instructions from the external memory to the first RAM segment.05-26-2011
20090313398METHOD AND SYSTEM FOR STORING MEMORY COMPRESSED DATA ONTO MEMORY COMPRESSED DISKS - A method (and system) of storing information, includes storing main memory compressed information onto a memory compressed disk, where pages are stored and retrieved individually, without decompressing the main memory compressed information.12-17-2009
20120036288SYSTEMS AND METHODS FOR USING A SHARED BUFFER CONSTRUCT IN PERFORMANCE OF CONCURRENT DATA-DRIVEN TASKS - Disclosed herein are techniques to execute tasks with a computing device. A first task is initiated to perform an operation of the first task. A buffer construct that represents a region of memory accessible to the operation of the first task is created. A second task is initiated to perform of an operation of the second task that is configured to be timed to initiate in response to the buffer construct being communicated to the second task from the first task.02-09-2012
20110078342System and Method for Direct Memory Access Using Offsets - A DMA device may include an offset determination unit configured to determine a first offset for a DMA transfer and a data transfer unit. The data transfer unit may be configured to receive a first buffer starting address identifying a starting location of a first buffer allocated in memory for the DMA transfer and to generate a first buffer offset address by applying the first offset to the first buffer starting address. The data transfer unit may be further configured to use the first buffer offset address as a starting location in the first buffer for data transferred in the DMA transfer. By applying various offsets, such DMA devices may spread memory access workload across multiple memory controllers, thereby achieving better workload balance and performance in the memory system.03-31-2011
20100185790DATA TRANSFER DEVICE AND DATA TRANSFER METHOD - There are provided a transfer request module 07-22-2010
20090313397Methods and Systems for Protecting Data in USB Systems - The various embodiments described below are directed to providing authenticated and confidential messaging from software executing on a host (e.g. a secure software application or security kernel) to and from I/O devices operating on a USB bus. The embodiments can protect against attacks that are levied by software executing on a host computer. In some embodiments, a secure functional component or module is provided and can use encryption techniques to provide protection against observation and manipulation of USB data. In other embodiments, USB data can be protected through techniques that do not utilized (or are not required to utilize) encryption techniques. In accordance with these embodiments, USB devices can be designated as “secure” and, hence, data sent over the USB to and from such designated devices can be provided into protected memory. Memory indirection techniques can be utilized to ensure that data to and from secure devices is protected.12-17-2009
20100036976DEVICE AND METHOD FOR TESTING A DIRECT MEMORY ACCESS CONTROLLER - A device and a method for testing a DMA controller. The device includes: (i) a DMA controller that includes a first data transfer path and a second data transfer path, wherein the first data transfer path and the second data transfer path are mutually independent; (ii) a test unit, connected to the first and second data transfer paths, that is adapted to control a transfer of data between the first data transfer path and the second data transfer path during a test mode, while masking from a first memory unit coupled to the DMA controller, at least one control signal associated with the transfer of data.02-11-2010
20100057949CIRCUITS, SYSTEMS, AND METHODS TO INTEGRATE STORAGE VIRTUALIZATION IN A STORAGE CONTROLLER - Methods and systems for improved performance in virtualized storage systems. Features and aspects hereof provide for a virtualization circuit integrated in each storage controller of a storage system. The virtualization circuit is operable to determine whether a request received from an attached host system will be processed locally by the receiving storage controller or will be processed by another storage controller of the storage system. If another storage controller is to process the request, the virtualization circuit is operable to transfer the request to the appropriate other storage controller. The virtualization circuit then receives result information from the other storage controller and returns such result information to the requesting host system. Integration of the virtualization circuit at below level of request processing of storage controllers improves performance of virtualization as compared to prior techniques.03-04-2010
20090216916METHOD AND APPARATUS FOR INPUTTING/OUTPUTTING DATA USING VIRTUALIZATION TECHNIQUE - A method and apparatus for inputting and outputting data by using a virtualization technique are provided. The method includes generating a virtual operating system (OS) for the external device, which is connected to a host, based on OS information stored in the external device, setting a partial area of a storage of the host as virtual storage for the external device, and storing the data in the virtual storage or a memory of the external device in response to a request for inputting and outputting the data from the virtual OS.08-27-2009
20090216915METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR MERGING DATA - A method for merging data including receiving a request from an input/output device to merge a data, wherein a merge of the data includes a manipulation of the data, determining if the data exists in a local cache memory that is in local communication with the input/output device, fetching the data to the local cache memory from a remote cache memory or a main memory if the data does not exist in the local cache memory, merging the data according to the request to obtain a merged data, and storing the merged data in the local cache, wherein the merging of the data is performed without using a memory controller within a control flow or a data flow of the merging of the data. A corresponding system and computer program product.08-27-2009
20090216914Information Processing Apparatus and Information Processing Method - The present invention relates to an information processing apparatus capable of accurately controlling DMA transfer of a plurality of pieces of data present in a memory with a simple hardware configuration, and an information processing method for use therewith. A memory 08-27-2009
20100064070DATA TRANSFER UNIT FOR COMPUTER - In order to improve throughput by suppressing contention of hardware resources in a computer to which a data transfer unit is coupled, a control unit for transferring data between a first interface coupled to the computer and a second interface coupled to a memory transaction issuing unit for issuing, when one of the first interface and the second interface receives an access request to a memory of the computer, a memory transaction for the main memory to the first interface, the first interface includes a plurality of interfaces coupled in parallel to the computer, and the control unit further includes a memory transaction distribution unit for extracting an address of the main memory, which is contained in the memory transaction issued by the memory transaction issuing unit, and selecting an interface having address designation information set therein, which corresponds to the extracted address to transmit the memory transaction.03-11-2010
20110153875OPPORTUNISTIC DMA HEADER INSERTION - In a first embodiment of the present invention, a method for operating an I/O interconnect midpoint device is presented, wherein the midpoint device has a direct memory access (DMA) controller and a plurality of ports, the method comprising: generating, using the DMA controller, a DMA read request; sending, using the DMA controller, the DMA read request to a first device connected to a first of the plurality of ports; receiving data responsive to the DMA read request from the first device; generating, using the DMA controller, a DMA write request including the received data; and sending, using the DMA controller, the DMA write request to a second device connected to the second of the plurality of ports.06-23-2011
20110153876HIGH-PERFORMANCE DIGITAL IMAGE MEMORY ALLOCATION AND CONTROL SYSTEM - Systems and methods are described that facilitate mitigating processor overload and reducing memory waste during image compression. Clients requesting memory allocation are assigned a direct memory access (DMA) channel to which DMA memory blocks are allocated for use during image compression. As each DMA block is used by its channel, the DMA block generates an interrupt message that is counted by a DMA counter and may be optionally processed by the CPU. If the number of interrupts being processed exceeds a first threshold, then memory block size is increased to reduce processor load. If the number of interrupts is below a second, lower threshold, then block size is decreased to reduce and amount of unused but allocated memory in the final block allocated to the channel a compressed image file. Fixed DMA block size may also be used and any DMA block may be programmed to generate an interrupt indicating a memory usage threshold has been crossed and that additional DMA memory blocks should be allocated to continue compression beyond the number of DMA blocks initially allocated.06-23-2011
20110072170Systems and Methods for Transferring Data to Maintain Preferred Slot Positions in a Bi-endian Processor - A bi-endian multiprocessor system having multiple processing elements, each of which includes a processor core, a local memory and a memory flow controller. The memory flow controller transfers data between the local memory and data sources external to the processing element. If the processing element and the data source implement data representations having the same endian-ness, each multi-word line of data is stored in the local memory in the same word order as in the data source. If the processing element and the data source implement data representations having different endian-ness, the words of each multi-word line of data are transposed when data is transferred between local memory and the data source. The processing element may incorporate circuitry to add doublewords, wherein the circuitry can alternately carry bits from a first word to a second word or vice versa, depending upon whether the words in lines of data are transposed.03-24-2011
20120303842SELECTING DIRECT MEMORY ACCESS ENGINES IN AN ADAPTOR FOR PROCESSING INPUT/OUTPUT (I/O) REQUESTS RECEIVED AT THE ADAPTOR - Provided are a computer program product, system, and method for selecting Direct Memory Access (DMA) engines in an adaptor for processing Input/Output requests received at the adaptor. A determination is made of an assignment of a plurality of processors to the DMA engines, wherein each processor is assigned to use one of the DMA engines. I/O request related work for a received I/O request directed to the storage is processed by determining the DMA engine assigned to the processor processing the I/O request related work and accessing the determined DMA engine to perform the I/O related work.11-29-2012
20120303841PROCESS TO GENERATE VARIOUS LENGTH PARAMETERS IN A NUMBER OF SGLS BASED UPON THE LENGTH FIELDS OF ANOTHER SGL - A method of generating length parameters, comprising the steps of reading a data stream from a host, detecting a particular field of the data stream, and calculating a variable based on a length parameter of a first list to be transferred. The data stream may comprise a plurality of definitions. The method may also comprise the step of selecting one of the list definitions. One of the list definitions may be used to generate a length parameter used in a second list in response to (i) the particular field of the data stream and (ii) the length parameter of the first list.11-29-2012
20120303840DMA DATA TRANSFER MECHANISM TO REDUCE SYSTEM LATENCIES AND IMPROVE PERFORMANCE - A method of implementing a data transfer mechanism to reduce latencies and improve performance comprising the steps of reading a first data element, storing the first data element, and writing the first data element. The first data element may be read from a host. The first data element may be stored in a storage portion of a controller. The first data element may be written to a first destination device. The first data element may also be written to a second destination device prior to deleting the first data element from the storage portion.11-29-2012
20110060853SYSTEM, METHOD, AND DEVICE FOR ROUTING CALLS USING A DISTRIBUTED MOBILE ARCHITECTURE - Methods and devices for routing communications between distributed mobile architecture (DMA) servers using DMA gateways are disclosed. Communications information is received at a first DMA gateway of a DMA gateway communications network. The communications information is associated with a communications network that is accessible by a second DMA gateway of the DMA gateway communications network. The communications information is stored at a memory of the first DMA gateway. The first DMA gateway receives a communication that is associated with a destination device indicated by the communications information to be served by the second DMA gateway. The communication is routed from the first DMA gateway to the destination device by relaying the communication from the first DMA gateway to the second DMA gateway via the DMA gateway communications network.03-10-2011
20110072171DMA AND GRAPHICS INTERVACE EMULATION - An emulator schedules emulation threads for DMA emulation and other emulation functions in a time-multiplexed manner. Emulation threads are selected for execution according to a load balancing scheme. Non-DMA emulation threads are executed until their execution time period expires or they stall. DMA emulation thread execution is allowed to execute indefinitely until the DMA emulation thread stalls. The DMA emulation thread prefetches additional adjacent data in response to target computer system DMA requests. Upon receiving a target computer system DMA request, the DMA emulation thread first checks to the prefetched data to see if this data matches the request. If so, the request is fulfilled using the prefetched data. If the prefetched data does not match the target computer system DMA request, the DMA emulation thread fetches and stores the requested data and additional adjacent data for potential future use.03-24-2011
20110060852COMPUTER SYSTEM AND DATA TRANSFER METHOD THEREIN - A DMA transfer technique which can be adapted to “hardware in the loop simulation” (HILS) and which requires less overhead. In a computer system having a data transfer device, a continuous DMA mechanism successively and repeatedly outputs a data transfer request in response to an enable process. A simulation system for HILS places data as a result of the simulation in a predetermined area in a memory and transfers the data from the memory to the continuous DMA mechanism together with generation ID data. The continuous DMA mechanism stores the transferred generation ID as a received ID, and receives the transferred data in response to the event that the transferred generation ID differs from the received ID being stored. The continuous DMA mechanism successively repeats the data transfer request until it is disabled.03-10-2011
20110060851Deep Packet Inspection (DPI) Using A DPI Core - Illustrated is a system for performing Deep Packet Inspection (DPI) that includes a core to prepare a data packet for transmission. Further, the system includes a memory controller to direct the data packet to a DPI core. Additionally, the system includes a Network Interface Card to receive the data packet for transmission after DPI is performed on the data packet by the DPI core. The system includes a Direct Memory Management module to update a descriptor that references a received data packet stored in an Operating System buffer. Moreover, the system includes an Input/Output Memory Management Unit to direct the descriptor to be stored in a DPI memory. Additionally, the system includes an interrupt controller to transmit an interrupt to the DPI core to such that the DPI core retrieves the descriptor from the DPI memory and performs DPI on the data packet stored in the OS buffer.03-10-2011
20100325317Controlling complex non-linear data transfers - A direct memory access controller for controlling data transfer between a plurality of data sources and a plurality of data destinations is disclosed. The plurality of data sources and data destinations communicate with the direct memory access controller via a plurality of channels, the direct memory access controller further communicates with a memory and a processor. The memory stores two sets of control data for each of the plurality of channels and for the processor. The direct memory access controller is responsive to a data transfer request received from one of said plurality of channels or from said processor to access one set of said corresponding control data stored in said memory, said direct memory access performing at least a portion of said data transfer requested in dependence upon said accessed control data.12-23-2010
20100064069DEVICE AND METHOD FOR CONTROLLING MULTIPLE DMA TASKS - A method for controlling multiple DMA tasks, the method includes receiving multiple DMA task requests; the method is characterized by defining multiple buffer descriptors for each of a plurality of DMA channel; wherein at least two buffer descriptors comprise timing information that controls an execution of cyclic time based DMA tasks; selecting a DMA task request out of the multiple DMA task requests; executing a DMA task or a DMA task iteration and updating the buffer descriptor associated with the selected DMA task request to reflect the execution; and jumping to the stage of selecting. A device that includes a memory unit; the device is characterized by including a DMA controller that is adapted to: (i) access at least one buffer descriptor out of multiple buffer descriptors defined for each of a plurality of DMA channel, wherein at least two buffer descriptors comprise timing information that controls an execution of cyclic time based DMA tasks; (ii) receive multiple DMA task requests, (iii) select a DMA task request out of the multiple DMA task requests, and (iv) execute a DMA task or a DMA task iteration and update a buffer descriptor associated with the selected DMA task request to reflect the execution.03-11-2010
20090240847High Speed Memory Access in an Embedded System - Data is processed in an embedded system by writing data read from a peripheral device in response to an event to memory external to the embedded system. The data or a portion of the data is copied to memory internal to the embedded system. Which portion of the data is stored in both the external memory and the internal memory is tracked. The copied data is retrieved from the internal memory by a processor included in the embedded system. The processor has one or more caches logically and physically separated from the internal memory. The processor uses the copied data it retrieved to begin servicing the event.09-24-2009
20110131346Context Processing for Multiple Active Write Commands in a Media Controller Architecture - Described embodiments provide a method of transferring data from host devices to a media controller. The media controller generates a transfer context for each write request received from a host device. Receive-data threads corresponding to data transfer contexts for each transfer context are generated, each receive-data thread corresponding to a data transfer between a host device and the media controller. Buffer threads corresponding to data transfer contexts for each transfer context are generated, each buffer thread corresponding to a data transfer between the receive data path and a buffer subsystem. The receive-data and buffer threads are tracked for each transfer context. For each tracked transfer context, data from the receive datapath is iteratively transferred to the buffer subsystem for a previous data transfer context of the buffer thread while data from the host device is transferred to the receive datapath for a subsequent data transfer context of the receive-data thread.06-02-2011
20080320178DMA transfer apparatus - A DMA transfer apparatus 12-25-2008
20080228958Direct Memory Access Engine for Data Transfers - A system and method of transferring data of unknown length in a computer system includes providing an embedded device having a processing apparatus and a DMA engine, the processing apparatus processing the data and the DMA engine transferring the data from the embedded device to a component in the computer system, determining whether information from the embedded device is an address value or a data value, programming the DMA engine with the address value if the information is the address value, and transferring the data value to the address value in the component if the information is the data value.09-18-2008
20120203939INJECTION OF I/O MESSAGES - A data processing system includes a processor core, a system memory coupled to the processor core, an input/output adapter (IOA), and an input/output (I/O) host bridge coupled to the processor core and to the IOA. The I/O host bridge includes a register coupled to receive I/O messages from the processor core, a buffer coupled to receive I/O messages from the IOA, and logic coupled to the register and to the buffer that services I/O messages received from the register and from the buffer.08-09-2012
20120173772DIRECT MEMORY ACCESS CONTROLLER, CORRESPONDING METHOD AND COMPUTER PROGRAM - The invention relates to an access controller which comprises a module (07-05-2012
20110264830Measuring Direct Memory Access Throughput - Methods and systems for measuring available direct memory access (DMA) throughput are disclosed, including providing a plurality of DMA channels, the DMA channels comprising a measuring DMA channel and other DMA channels, the measuring DMA channel having a lowest data rate priority, and determining an available DMA throughput by measuring a current data rate at which the measuring DMA channel is serviced in response to initiating a data transfer on the measuring DMA channel.10-27-2011
20110179198STORAGE DEVICE OF SERIAL ATTACHED SMALL COMPUTER SYSTEM INTERFACE/SERIAL ADVANCED TECHNOLOGY ATTACHMENT TYPE - Provided is a storage device of a serial attached small computer system interface/serial advanced technology attachment (SAS/SATA) type, which provides data storage/reading services through an SAS/SATA interface. The SAS/SATA type storage device includes: a memory disk unit which includes a plurality of memory disks provided with a plurality of volatile semiconductor memories; an SAS/SATA host interface unit which interfaces between the memory disk unit and a host; and a controller unit which adjusts synchronization of a data signal transmitted/received between the SAS/SATA host interface unit and the memory disk unit to control a data transmission/reception speed between the SAS/SATA host interface unit and the memory disk unit. The storage device can support a low-speed data processing speed for the host and simultaneously support a high-speed data processing speed for the memory disk unit, so that there are advantages in that the performance of the memory disk can be fully utilized to enable high-speed data processing in an existing interface environment.07-21-2011
20110125934APPARATUSES AND METHODS FOR TRANSFERRING DATA - An apparatus includes a socket, a computer-readable medium, and a controller. The socket is capable of interfacing with different types of storage medium. The computer-readable medium is operable for storing a computer-executable universal driver associated with a first operation mode and compatible with each of the types of storage medium, and for storing a computer-executable dedicated driver associated with a second operation mode and compatible with only a subset of the types of storage medium. The controller is operable for selecting a selected driver from the universal driver and the dedicated driver if a storage medium is inserted into the socket and for operating in a corresponding operation mode to exchange data information with the storage medium according to the selected driver. The selected driver includes the dedicated driver if the storage medium is a member of the subset and otherwise the selected driver includes the universal driver.05-26-2011
20120311198FIBRE CHANNEL INPUT/OUTPUT DATA ROUTING SYSTEM AND METHOD - A computer program product is provided for performing a method including: obtaining information relating to an I/O operation at a channel subsystem in a host computer system; generating at least one address control word (ACW) in the local channel memory specifying one or more host memory locations for transfer of data between the host and a control unit and including at least one ACW error checking field; generating an address control structure specifying a location in the local channel memory of a corresponding ACW and including at least one address control structure error checking field; receiving a data transfer request from the network interface that includes the addressing information; comparing the at least one ACW error checking field to the at least one address control structure error checking field; and, responsive to the fields matching, routing the data transfer request to the host memory location specified in the corresponding ACW.12-06-2012
20120311197APPARATUS INCLUDING MEMORY SYSTEM CONTROLLERS AND RELATED METHODS - Memory system controllers can include hardware masters, first buffers, and a switch coupled to the hardware masters and to the first buffers. The switch can include second buffers and a buffer allocation management (BAM) circuit. The BAM circuit can include a buffer tag pool. The buffer tag pool can include tags, each identifying a respective first buffer or a respective second buffer. The BAM circuit can be configured to allocate a tag to a hardware master in response to an allocation request from the hardware masters. The BAM circuit can be configured to prioritize allocation of a tag identifying a second buffer over a tag identifying a first buffer.12-06-2012
20100180053DIRECT MEMORY ACCESS CONTROLLER - A direct memory access controller is provided, in which an internal storage section storing control setting information; and a control section loading the control setting information from an external storage section to the internal storage section when a transfer request signal does not belong to a first group, and not loading the control setting information from the external storage section to the internal storage section when the transfer request signal belongs to the first group; are included, and a data transfer by a direct memory access is performed in accordance with the control setting information within the internal storage section.07-15-2010
20090300229Methods and Apparatus for Providing Data Transfer Control - A variety of advantageous mechanisms for improved data transfer control within a data processing system are described. A DMA controller is described which is implemented as a multiprocessing transfer engine supporting multiple transfer controllers which may work independently or in cooperation to carry out data transfers, with each transfer controller acting as an autonomous processor, fetching and dispatching DMA instructions to multiple execution units. In particular, mechanisms for initiating and controlling the sequence of data transfers are provided, as are processes for autonomously fetching DMA instructions which are decoded sequentially but executed in parallel. Dual transfer execution units within each transfer controller, together with independent transfer counters, are employed to allow decoupling of source and destination address generation and to allow multiple transfer instructions in one transfer execution unit to operate in parallel with a single transfer instruction in the other transfer unit. Improved flow control of data between a source and destination is provided through the use of special semaphore operations, signals and message synchronization which may be invoked explicitly using SIGNAL and WAIT type instructions or implicitly through the use of special “event-action” registers. Transfer controllers are also described which can cooperate to perform “DMA-to-DMA” transfers. Message-level synchronization can be used by transfer controllers to synchronize with each other.12-03-2009
20110191506VIRTUALIZATION OF AN INPUT/OUTPUT DEVICE FOR SUPPORTING MULTIPLE HOSTS AND FUNCTIONS - Methods and apparatus are provided for simultaneously supporting multiple hosts with a single communication port; each host may host multiple functions. The input/output device comprises multiple buffers; each buffer stores packets for one host, but can be dynamically reallocated to a different host. Multiple buffers may simultaneously support the same host and all of its functions. After a packet is received and classified, it is stored in at least one buffer, along with control information for processing the packet upon egress from the buffer. Egress managers for each buffer extract packets and transfer them to destination host/functions, by speculatively moving the packets forward even while DMA engines perform their processing to facilitate their transfer.08-04-2011
20100017544DIRECT MEMORY ACCESS CONTROLLER AND DATA TRANSMITTING METHOD OF DIRECT MEMORY ACCESS CHANNEL - Provided is a direct memory access (DMA) controller. The DMA controller includes a plurality of channel groups and a channel group controller. Each of the channel groups has a plurality of DMA channels, and the channel group controller controls enablement of the DMA channels in units of channel groups. Herein, the channel group controller enables the DMA channels of at least one of the channel groups in data transmission.01-21-2010
20120042100SYSTEMS AND METHODS FOR MANAGING MEMORY USING MULTI-STATE BUFFER REPRESENTATIONS - Disclosed herein are techniques to manage access to a memory using a buffer construct that includes state information associated with a region of the memory. The disclosed techniques facilitate access to the region of memory through a direct memory access operation while the state information of the buffer construct is in a first state. The state information can be transitioned to a second state in response to a first instruction. The disclosed techniques also facilitate access to the region of memory through a cache operation while the state information of the buffer construct is in the second state is disclosed. The state information can be transitioned to the first state in response to a second instruction.02-16-2012
20080301327Direct Memory Access Transfer Completion Notification - Methods, apparatus, and products are disclosed for DMA transfer completion notification that include: inserting, by an origin DMA engine on an origin compute node in an injection FIFO buffer, a data descriptor for an application message to be transferred to a target compute node on behalf of an application on the origin compute node; inserting, by the origin DMA engine, a completion notification descriptor in the injection FIFO buffer after the data descriptor for the message, the completion notification descriptor specifying an address of a completion notification field in application storage for the application; transferring, by the origin DMA engine to the target compute node, the message in dependence upon the data descriptor; and notifying, by the origin DMA engine, the application that the transfer of the message is complete, including performing a local direct put operation to store predesignated notification data at the address of the completion notification field.12-04-2008
20080228959METHOD AND APPARATUS FOR OPERATING STORAGE CONTROLLER SYSTEM IN ELEVATED TEMPERATURE ENVIRONMENT - A storage controller that operates under elevated temperature conditions includes a memory, a memory controller, and a CPU that detects a temperature of the memory controller has exceeded a threshold while operating at a first frequency and responsively places the memory into self-refresh mode, reduces the memory controller frequency to a second frequency, and then takes the memory out of self-refresh mode. The clock frequency of a bus bridge or communications link circuit may also be reduced when their temperatures exceed a threshold. The bus bridge may deny access to requestors of access to the memory while the frequency is being reduced. Message transfers on a communications link between redundant storage controllers in a system may be suspended while the link frequency is being reduced. Finally, the system may fail over to one controller while the other controller reduces the frequencies and then fail back.09-18-2008
20110320644RESIZING ADDRESS SPACES CONCURRENT TO ACCESSING THE ADDRESS SPACES - Address spaces are resized concurrent to accessing those address spaces. The size of an address space can be increased or decreased concurrent to performing read or write operations on the address space. Further, cache entries associated with an address space being decreased in size are purged.12-29-2011
20120210024DATA TRANSFER DEVICE AND STORAGE DEVICE - A data transfer device includes a transmitter, a receiver, and a monitor. The transmitter transmits data by non-handshake communication, and the receiver receives the data transmitted from the transmitter. Further, the monitor is provided separately from the receiver, and monitors a size of data received by the receiver to notify the transmitter of a result of monitoring.08-16-2012
20080294807Method and Apparatus for Invalidating Cache Lines During Direct Memory Access (DMA) Write Operations - A method and apparatus for invalidating cache lines during direct memory access (DMA) write operations are disclosed. Initially, a multi-cache line DMA request is issued by a peripheral device. The multi-cache line DMA request is snooped by a cache memory. A determination is then made as to whether or not the cache memory includes a copy of data stored in the system memory locations to which the multi-cache line DMA request are directed. In response to a determination that the cache memory includes a copy of data stored in the system memory locations to which the multi-cache line DMA request are directed, multiple cache lines within the cache memory are consecutively invalidated.11-27-2008
20130013820METHOD FOR INITIALIZING REGISTERS OF PERIPHERALS IN A MICROCONTROLLER - Embodiments described in the present disclosure relate to a method for initializing registers of peripherals of a microcontroller, including acts of: accessing initialization data in a non-volatile memory connected by a main bus to a processing unit of the microcontroller and to the peripherals, activating a peripheral including registers to be initialized, and transferring the data read into the registers of the activated peripheral, the initialization data being accessed in the memory by an initialization circuit distinct from the processing unit, the initialization data accessed being sent to the peripherals by an initialization bus distinct from the main bus.01-10-2013
20120023270COMPUTER SYSTEM AND METHOD OF PROCESSING COMPUTER SYSTEM - A computer system has a master device having a first register for storing a first process ID associated with a software process number. The master device transmits the first process ID onto a system bus when it generates a transaction. The computer system has a slave device holding a second process ID for permitting access. The slave device accepts the transaction when the first process ID and the second process ID meet a predetermined condition.01-26-2012
20120117282DATA FILTERING USING CENTRAL DMA MECHANISM - A method and system is disclosed for passing data processed by a DMA controller through a transmission filter. The method includes the DMA controller accessing data for transfer between an origination location in the system and a destination location in the system. The accessed data is passed through the DMA controller before being sent to the destination location. While the data is being passed through the DMA controller, it is passed through a transmission filter for processing. This processing may include the addition or removal of transmission protocol headers and footers, and determination of the destination of the data. This processing may also include hash-based packet classification and checksum generation and checking. Upon completion of the processing, the data is sent directly to a prescribed destination location, typically either a memory circuit or an I/O device.05-10-2012
20120117281Fencing Direct Memory Access Data Transfers In A Parallel Active Messaging Interface Of A Parallel Computer - Fencing direct memory access (‘DMA’) data transfers in a parallel active messaging interface (‘PAMI’) of a parallel computer, the PAMI including data communications endpoints, each endpoint including specifications of a client, a context, and a task, the endpoints coupled for data communications through the PAMI and through DMA controllers operatively coupled to segments of shared random access memory through which the DMA controllers deliver data communications deterministically, including initiating execution through the PAMI of an ordered sequence of active DMA instructions for DMA data transfers between two endpoints, effecting deterministic DMA data transfers through a DMA controller and a segment of shared memory; and executing through the PAMI, with no FENCE accounting for DMA data transfers, an active FENCE instruction, the FENCE instruction completing execution only after completion of all DMA instructions initiated prior to execution of the FENCE instruction for DMA data transfers between the two endpoints.05-10-2012
20120059956DIRECT MEMORY ACCESS (DMA) TRANSFER OF NETWORK INTERFACE STATISTICS - In general, in one aspect, the disclosure describes a method that includes maintaining statistics, at a network interface, metering operation of the network interface. The statistics are transferred by direct memory access from the network interface to a memory accessed by at least one processor.03-08-2012
20120159013METHOD OF TRANSFERRING DATA, A METHOD OF PROCESSING DATA, AN ACCELERATOR, A COMPUTER SYSTEM AND A COMPUTER PROGRAM - The invention provides a method of transferring data from a data array within a main memory of a computer to an accelerator for processing, the embodiment of the method comprising: at the accelerator, requesting data from the main memory and generating a data stream between the main memory and the accelerator, the generated data stream including data from the data array; and, using an offset to determine the scheduling of array elements within the generated data stream.06-21-2012
20120159014METHOD OF TRANSFERRING DATA, A METHOD OF PROCESSING DATA, AN ACCELERATOR, A COMPUTER SYSTEM AND A COMPUTER PROGRAM - The invention provides a method of transferring data from a data array within a main memory of a computer to an accelerator for processing, the embodiment of the method comprising: at the accelerator, requesting data from the main memory and generating a data stream between the main memory and the accelerator, the generated data stream including data from the data array; and, using an offset to determine the scheduling of array elements within the generated data stream.06-21-2012
20110066769Multithreaded Programmable Direct Memory Access Engine - A mechanism programming a direct memory access engine operating as a multithreaded processor is provided. A plurality of programs is received from a host processor in a local memory associated with the direct memory access engine. A request is received in the direct memory access engine from the host processor indicating that the plurality of programs located in the local memory is to be executed. The direct memory access engine executes two or more of the plurality of programs without intervention by a host processor. As each of the two or more of the plurality of programs completes execution, the direct memory access engine sends a completion notification to the host processor that indicates that the program has completed execution.03-17-2011
20110099301Using Central Direct Memory Access (CDMA) Controller to Test Integrated Circuit - In an embodiment, an integrated circuit includes a direct memory access (DMA) controller configured to perform DMA operations between peripheral components of the integrated circuit and/or a memory to which the integrated circuit is configured to be coupled. Combinations of memory-to-memory, memory-to-peripheral, and peripheral-to-memory operations may be used. The DMA controller may be programmed to perform a number of DMA operations concurrently. The DMA operations may be programmed and performed as part of testing the integrated circuit during design and/or manufacture of the integrated circuit. The DMA operations may cause many of the components in the integrated circuit to be busy performing various operations. In some embodiments, programmed input/output (PIO) operations may also be performed while the DMA operations are in progress. In some embodiments, various parameters of the DMA operations and/or PIO operations may be randomized.04-28-2011
20120124249Method Of Data Communications With Reduced Latency - Data communications with reduced latency, including: writing, by a producer, a descriptor and message data into at least two descriptor slots of a descriptor buffer, the descriptor buffer comprising allocated computer memory segmented into descriptor slots, each descriptor slot having a fixed size, the descriptor buffer having a header pointer that identifies a next descriptor slot to be processed by a DMA controller, the descriptor buffer having a tail pointer that identifies a descriptor slot for entry of a next descriptor in the descriptor buffer; recording, by the producer, in the descriptor a value signifying that message data has been written into descriptor slots; and setting, by the producer, in dependence upon the recorded value, a tail pointer to point to a next open descriptor slot.05-17-2012
20120124248PROCESSOR WITH TIGHTLY COUPLED SMART MEMORY UNIT - An information processor includes a central processing unit core and a tightly coupled smart memory unit, the central processing unit core having a direct memory access unit. The tightly coupled smart memory unit having a memory unit coupled to the central processing unit core and a control register, and status register coupled to the central processing unit core and a local processing unit that processes data stored in the memory unit.05-17-2012
20120166683Memory Data Transfer Method and System - A method and apparatus are disclosed for providing a DMA process. Accordingly, a DMA process is initiated for moving data from contiguous first locations to contiguous second locations and to a third location or third locations. Within the DMA process the data from each of the contiguous first locations is retrieved and stored in a corresponding one of the contiguous second locations and in the third location or corresponding one of the third locations. The DMA process is performed absent retrieving the same data a second other time prior to storing of same within the corresponding one of the contiguous second locations and in the third location or corresponding one of the third locations.06-28-2012
20120166682MEMORY MAPPING APPARATUS AND MULTIPROCESSOR SYSTEM ON CHIP PLATFORM INCLUDING THE SAME - A memory mapping apparatus includes a core/memory selector adapted to select a core from among a plurality of cores, and select a memory from among a plurality of memories, a transfer path allocator adapted to allocate a data transfer path between the core and memory which are selected by the core/memory selector, and a DMA control signal setter adapted to set a signal to be controlled to a DMA Controller which controls a plurality of DMAs corresponding to data transfer paths between the cores and the memories.06-28-2012
20100082849Data filtering using central DMA mechanism - A method and system is disclosed for passing data processed by a DMA controller through a transmission filter. The method includes the DMA controller accessing data for transfer between an origination location in the system and a destination location in the system. The accessed data is passed through the DMA controller before being sent to the destination location. While the data is being passed through the DMA controller, it is passed through a transmission filter for processing. This processing may include the addition or removal of transmission protocol headers and footers, and determination of the destination of the data. This processing may also include hash-based packet classification and checksum generation and checking. Upon completion of the processing, the data is sent directly to a prescribed destination location, typically either a memory circuit or an I/O device.04-01-2010
20110179196SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR PORTABLE MULTIMEDIA CONTENT DISPLAY - A system, method and computer program product for performing a method for presenting multimedia data are disclosed. The method includes but is not limited to detecting insertion of a portable storage device into a first end user device; automatically launching transfer of multimedia data and Meta data describing the multimedia data from the first end user device to the portable storage device; transferring the multimedia data from the first end user device to the portable storage device; detecting insertion of the portable storage device into a second end user device; automatically launching transfer of multimedia data and Meta data describing the multimedia data from the portable storage device to the second end user device; and transferring the multimedia data from the portable storage device to the second end user device.07-21-2011
20120137029DMA (DIRECT MEMORY ACCESS) COALESCING - In general, in one aspect, a method includes determining a repeated, periodic DMA (Direct Memory Access) coalescing interval based, at least in part, on a power sleep state of a host platform. The method also includes buffering data received at the device in a FIFO (First-In-First-Out) queue during the interval and DMA-ing the data enqueued in the FIFO to a memory external to the device after expiration of the repeated, periodic DMA coalescing interval.05-31-2012
20100049883METHOD AND SYSTEM FOR MEMORY ADDRESS TRANSLATION AND PINNING - A method and system for memory address translation and pinning are provided. The method includes attaching a memory address space identifier to a direct memory access (DMA) request, the DMA request is sent by a consumer and using a virtual address in a given address space. The method further includes looking up for the memory address space identifier to find a translation of the virtual address in the given address space used in the DMA request to a physical page frame. Provided that the physical page frame is found, pinning the physical page frame as long as the DMA request is in progress to prevent an unmapping operation of said virtual address in said given address space, and completing the DMA request, wherein the steps of attaching, looking up and pinning are centrally controlled by a host gateway.02-25-2010
20100274933Method and apparatus for reducing memory size and bandwidth - A solid state disk drive is provided. The solid state disk drive includes a memory device and a controller. The memory device includes memory cells for storing data bits. The controller is coupled to the memory device, accesses the memory device according to a clock signal, estimates a work load of the memory device, and adjusts a frequency of the clock signal in accordance with the estimated work load.10-28-2010
20100131678DIRECT MEMORY APPARATUS AND DIRECT MEMORY ACCESS METHOD - There is provided a direct memory access apparatus and a direct memory access method.05-27-2010
20100011136Functional DMA - In one embodiment, a direct memory access (DMA) controller comprises a transmit control circuit, an offload engine, and a receive control circuit. The transmit control circuit is configured to read first DMA data from an address space in a host. Coupled to receive the first DMA data from the transmit control circuit, the offload engine is configured to perform at least a first operation on the first DMA data to produce a result. The offload engine is configured to at least start performing the first operation during a DMA transfer that provides the first DMA data to the offload engine. Coupled to the offload engine to receive the result, the receive control circuit is configured to write the result to the address space in the host according to a DMA descriptor data structure that describes the DMA transfer.01-14-2010
20120254480FACILITATING, AT LEAST IN PART, BY CIRCUITRY, ACCESSING OF AT LEAST ONE CONTROLLER COMMAND INTERFACE - An embodiment may include circuitry to facilitate, at least in part, a first network interface controller (NIC) in a client to be capable of accessing, via a second NIC in a server that is remote from the client and in a manner that is independent of an operating system environment in the server, at least one command interface of another controller of the server. The command interface may include at least one controller command queue. Such accessing may include writing at least one queue element to the at least one command queue to command the another controller to perform at least one operation associated with the another controller. The another controller may perform the at least one operation in response, at least in part, to the at least one queue element. Many alternatives, variations, and modifications are possible.10-04-2012
20120226830MEMORY SYSTEM HAVING HIGH DATA TRANSFER EFFICIENCY AND HOST CONTROLLER - According to one embodiment, the host controller includes a register set to issue command, and a direct memory access (DMA) unit and accesses a system memory and a device. First, second, third and fourth descriptors are stored in the system memory. The first descriptor includes a set of a plurality of pointers indicating a plurality of second descriptors. Each of the second descriptors comprises the third descriptor and fourth descriptor. The third descriptor includes a command number, etc. The fourth descriptor includes information indicating addresses and sizes of a plurality of data arranged in the system memory. The DMA unit sets, in the register set, the contents of the third descriptor forming the second descriptor, from the head of the first descriptor as a start point, and transfers data between the system memory and the host controller in accordance with the contents of the fourth descriptor.09-06-2012
20120260005CONTROLLER FOR DIRECT ACCESS TO A MEMORY FOR THE DIRECT TRANSFER OF DATA BETWEEN MEMORIES OF SEVERAL PERIPHERAL DEVICES, METHOD AND COMPUTER PROGRAM ENABLING THE IMPLEMENTATION OF SUCH A CONTROLLER - The subject of the invention is in particular the direct transfer of data between first and second peripherals connected via a communication bus. For this purpose, the first peripheral comprises a controller for direct access to a memory having means (10-11-2012
20120265906DEMAND-BASED DMA ISSUANCE FOR EXECUTION OVERLAP - A method, apparatus, and program product retrieve data for a task utilizing demand-based direct memory access (“DMA”) requests. The method comprises, prior to the execution thereof, analyzing a first portion of a task to determine whether data required for execution thereby is stored in a local memory, and, in response to determining that the data required for execution by the first portion of the task is not stored in the local memory, proactively issuing a first DMA request for the data required for execution by the first portion of the task. The method further comprises, in response to determining that the first DMA request is not complete, determining whether to proactively analyze a second portion of the task prior to the execution thereof for a determination whether data required for execution thereby is stored in the local memory.10-18-2012
20110131347DIRECT MEMORY ACCESS CONTROLLER WITH MULTIPLE TRANSACTION FUNCTIONALITY - A direct memory access controller is set forth. The direct memory access controller includes first and second registers storing various values that are used to set the parameters of DMA transfers that take place during a single data transaction. The first register stores a start address location value used to define a start address at which direct memory access transfers for the transaction are to begin. The second register stores a value used to end data transfers of the data transaction. The DMA controller also includes transfer control circuitry for executing the data transaction. The transfer control circuitry is adapted to automatically execute multiple, consecutive data transactions using the values stored in the first and second registers.06-02-2011
20110047302PROGRAMMED I/O ETHERNET ADAPTER WITH EARLY INTERRUPTS FOR ACCELERATING DATA TRANSFER - In a Local Area Network (LAN) system, an Ethernet adapter exchanges data with a host through programmed I/O (PIO) and FIFO buffers. The receive PIO employs a DMA ring buffer backup so incoming packets can be copied directly into host memory when the PIO FIFO buffer is full. The adapter may be programmed to generate early receive interrupts when only a portion of a packet has been received from the network, so as to decrease latency. The adapter may also be programmed to generate a second early interrupt so that the copying of a large packet to the host may overlap reception of the packet end. The adapter to begin packet transmission before the packet is completely transferred from the host to the adapter, which further reduces latency. The minimal latency of the adapter allows it to employ receive and transmit FIFO buffers which are small enough to be contained within RAM internal to an Application Specific Integrated Circuit (ASIC) containing the transceiver, ethernet controller, FIFO control circuitry and the host interface as well.02-24-2011
20120331185Methods and Apparatus for Providing Bit-Reversal and Multicast Functions Utilizing DMA Controller - Techniques for providing improved data distribution to and collection from multiple memories are described. Such memories are often associated with and local to processing elements (PEs) within an array processor. Improved data transfer control within a data processing system provides support for radix 2, 4 and 8 fast Fourier transform (FFT) algorithms through data reordering or bit-reversed addressing across multiple PEs, carried out concurrently with FFT computation on a digital signal processor (DSP) array by a DMA unit. Parallel data distribution and collection through forms of multicast and packet-gather operations are also supported.12-27-2012
20120278510USING DIRECT MEMORY ACCESS TO INITIALIZE A PROGRAMMABLE LOGIC DEVICE - An embodiment includes an integrated circuit (IC) for using direct memory access (DMA) to initialize a programmable logic device (PLD), the IC operably coupled to the PLD. The IC includes an input/output (I/O) interface and a PLD interface. The I/O interface converts a signal format between the IC and the PLD. The PLD interface includes a configuration and status register, a data buffer, and pacing logic. The configuration and status register is adapted to manipulate a control line of the PLD to configure the PLD in a programming mode via the I/O interface. The data buffer temporarily holds PLD programming data received from a DMA control at a DMA speed. The pacing logic controls the speed of transmitting the PLD programming data to a programming port on the PLD via the I/O interface at a PLD programming speed.11-01-2012
20120331186DMA CONTROLLER - The DMA controller includes a peripheral device read unit to read states of peripheral devices, a state comparator, a transfer unit, a register, and a peripheral device write unit to write data in the peripheral devices according to the contents in the register when the DMA transfer is executed, an interrupt select unit selects one of plural interrupt signals to determine whether the peripheral device read unit, the state comparator and the transfer unit are at a timing to execute operations. Based on these operations the state comparator determines whether to start the DMA transfer, and the transfer unit executes data transfer between the peripheral devices.12-27-2012
20120331184POLLING OF A TARGET REGISTER WITHIN A PERIPHERAL DEVICE - In a disclosed example of a method, a requested value of a target register may be specified as a precondition to performing a requested read or write operation. The requested read or write operation may be generated by a requesting device, such as a processor, and sent over a bus to a peripheral device containing the target register. The target register may be polled internally to the peripheral device without generating additional bus traffic between the requesting device and the peripheral device. A ring topology may be used to internally poll the target register and to perform the requested read or write operation when the polled value of the target register equals the requested value.12-27-2012
20110320647SKIP BASED CONTROL LOGIC FOR FIRST IN FIRST OUT BUFFER - Skip based control logic for first in first out buffer is disclosed. In one embodiment, an isochronous data packet placed in an isochronous receive first in first out (IRFIFO) buffer coupled to an isochronous receive direct memory access (IRDMA) is detected. Further, a header of the isochronous data packet is read. Furthermore, a validity of the isochronous data packet is determined. Also, a read operation of remaining data of the isochronous data packet is skipped if the isochronous data packet is determined as invalid.12-29-2011
20110320646SKIP BASED CONTROL LOGIC FOR FIRST IN FIRST OUT BUFFER - Skip based control logic for first in first out buffer is disclosed. In one embodiment, a host controller interface (HCI) device includes an isochronous receive first in first out (IRFIFO) buffer. The IRFIFO buffer includes a storage for storing an isochronous data packet received from a guest device. Further, the IRFIFO buffer includes a write pointer for pointing to a write address of the storage for a write operation. Furthermore, the IRFIFO buffer includes a read pointer for pointing to a read address of the storage for a read operation. In addition, the IRFIFO includes a control logic for incrementing the read pointer by a value of a skip parameter of a skip register if the isochronous data packet is not valid for the read operation.12-29-2011
20110320645METHOD, APPARATUS AND SYSTEM FOR REDUCED CHANNEL STARVATION IN A DMA ENGINE - Techniques for generating information identifying a next direct memory access (DMA) task to be serviced. In an embodiment, arbitration logic provides a sequence of masking logic to determine, according to a hierarchy of rules, a next task to be serviced by a DMA engine. In certain embodiments, masking logic includes logic to mask information representing pending tasks to be serviced, the masking based on identification of a channel as being a suspended channel and/or a victim channel.12-29-2011
20120290745DMA TRANSFER CONTROL DEVICE - A DMA transfer control device comprises: a DMA arbiter performing DMA transfer for each DMA channel formed by a combination of a memory and a plurality of input/output devices and DMA controller circuits controlling the DMA arbiter; a judgment unit and a transfer time calculation unit calculating a next DMA transfer scheduled time based on the DMA transfer size for a DMA transfer request and a judgment time. A timer counter timing the judgment time at a unit time interval, and a comparator comparing the judgment time where a DMA transfer request arrives with the DMA transfer scheduled time are also provided, and the judgment unit sends the DMA transfer permission to the DMA arbiter upon an output of the comparator indicating the judgment time is not earlier than the DMA transfer scheduled time. Data is efficiently transferred by dynamically controlling DMA transfer.11-15-2012
20130013821DATA TRANSFER CONTROL DEVICE AND DATA TRANSFER CONTROL METHOD - A data transfer control device that selects one of a plurality of DMA channels and transfers data to or from memory includes a request holding section configured to hold a certain number of data transfer requests of the plurality of DMA channels and a request rearranging section configured to select and rearrange the data transfer requests that are held in a basic transfer order so that the data transfer requests of each of the plurality of DMA channels are successively outputted for a number of successive transfers set in advance.01-10-2013
20120151103High Speed Memory Access in an Embedded System - Data is processed in an embedded system by writing data read from a peripheral device in response to an event to memory external to the embedded system. The data or a portion of the data is copied to memory internal to the embedded system. Which portion of the data is stored in both the external memory and the internal memory is tracked. The copied data is retrieved from the internal memory by a processor included in the embedded system. The processor has one or more caches logically and physically separated from the internal memory. The processor uses the copied data it retrieved to begin servicing the event.06-14-2012
20130019032APPARATUS AND METHOD FOR GENERATING INTERRUPT SIGNAL THAT SUPPORTS MULTI-PROCESSORAANM HAN; Dong-KuAACI Suwon-siAACO KRAAGP HAN; Dong-Ku Suwon-si KRAANM LEE; Kang-MinAACI Suwon-siAACO KRAAGP LEE; Kang-Min Suwon-si KRAANM LEE; Kyung-HaAACI Yongin-siAACO KRAAGP LEE; Kyung-Ha Yongin-si KR - A method for generating an interrupt signal in a memory controller and supporting a multi-processor is provided. Whether an access for a determined memory region occurs is determined. When the access for the determined memory region occurs, whether the access for the determined memory region has a right is determined. When the access for the determined memory region has the right, a core that will generate an interrupt signal is determined. The determined core is requested to generate the interrupt signal.01-17-2013
20080244112HANDLING DMA REQUESTS IN A VIRTUAL MEMORY ENVIRONMENT - An apparatus includes a virtual memory manager that moves data from a first block to second block in memory. When the virtual memory manager is ready to transfer data from the first block to the second block, a third, temporary block of memory is defined. The translation table in a DMA controller is changed to point DMA transfers that target the first block to instead target the temporary block. The virtual memory manager then transfers data from the first block to the second block. When the transfer is complete, a check is made to see if the DMA transferred data to the temporary block while the data from the first block was being written to the second block. If so, the data written to the temporary block is written to the second block. A hardware register is preferably used to efficiently detect changes to the temporary block.10-02-2008
20110246686APPARATUS AND SYSTEM HAVING PCI ROOT PORT AND DIRECT MEMORY ACCESS DEVICE FUNCTIONALITY - An apparatus and system having both PCI Root Port (RP) device and Direct Memory Access (DMA) End Point device functionality is disclosed. The apparatus is for use in an input/output (I/O) system interconnect module (IOSIM) device. A DMA/RP module includes a RP portion and one or more DMA/RP portions. The RP portion has one or more queue pipes and is configured to function as a standard PCIe Root Port device. Each of the DMA/RP portions includes DMA engines and DMA input and output channels, and is configured to behave more like an End Point device. The DMA/RP module also includes one or more PCIe hard core portions, an ICAM (I/O Caching Agent Module), and at least one PCIe service block (PSB). *The hard core portion couples the DMA/RP module and IOSIM device to an I/O device via a PCIe link, and the ICAM transitions data to a host memory device operating system.10-06-2011
20080222317Data Flow Control Within and Between DMA Channels - In one embodiment, a direct memory access (DMA) controller comprises a transmit circuit and a data flow control circuit coupled to the transmit circuit. The transmit circuit is configured to perform DMA transfers, each DMA transfer described by a DMA descriptor stored in a data structure in memory. There is a data structure for each DMA channel that is in use. The data flow control circuit is configured to control the transmit circuit's processing of DMA descriptors for each DMA channel responsive to data flow control data in the DMA descriptors in the corresponding data structure.09-11-2008
20120254481SYSTEMS AND METHODS FOR USING A SHARED BUFFER CONSTRUCT IN PERFORMANCE OF CONCURRENT DATA-DRIVEN TASKS - Disclosed herein are techniques to execute tasks with a computing device. A first task is initiated to perform an operation of the first task. A buffer construct that represents a region of memory accessible to the operation of the first task is created. A second task is initiated to perform of an operation of the second task that is configured to be timed to initiate in response to the buffer construct being communicated to the second task from the first task.10-04-2012
20110271014DIRECT I/O DEVICE ACCESS BY A VIRTUAL MACHINE WITH MEMORY MANAGED USING MEMORY DISAGGREGATION - Illustrated is a system and method for identifying a memory page that is accessible via a common physical address, the common physical address simultaneously accessed by a hypervisor remapping the physical address to a machine address, and the physical address used as part of a DMA operation generated by an I/O device that is programmed by a VM. It also includes transmitting data associated with the memory page as part of a memory disaggregation regime, the memory disaggregation regime to include an allocation of an additional memory page, on a remote memory device, to which the data will be written. It further includes updating a P2M translation table associated with the hypervisor, and an IOMMU translation table associated with the I/O device, to reflect a mapping from the physical address to a machine address associated with the remote memory device and used to identify the additional memory page.11-03-2011
20130138840Efficient Memory and Resource Management - The present system enables passing a pointer, associated with accessing data in a memory, to an input/output (I/O) device via an input/output memory management unit (IOMMU). The I/O device accesses the data in the memory via the IOMMU without copying the data into a local I/O device memory. The I/O device can perform an operation on the data in the memory based on the pointer, such that I/O device accesses the memory without expensive copies.05-30-2013
20130103862SD/SDIO HOST CONTROLLER - An SD/SDIO host controller is disclosed, which includes a control register and interrupt generation module, an internal DMA module, an SD/SDIO command interface module, an SD/SDIO data interface module, and a frequency divider and trigger/sampling enable signal generation module which is connected to an output end of the control register and interrupt generation module; the frequency divider and trigger/sampling enable signal generation module employs a frequency divider to perform frequency division on a local high-speed clock so as to obtain the operating clock of the SD/SDIO card, and simultaneously generates a trigger/sampling enable signal by the frequency divider and enables the position of the enable signal to be adjustable with respect to the operating clock of the SD/SDIO card. The present invention is capable of solving the setup/hold time issues caused by delay in digital signals.04-25-2013
20080201495HANDLING DMA OPERATIONS DURING A PAGE COPY - A memory controller provides page copy logic that assures data coherency when a DMA operation to a page occurs during the copying of the page by the memory controller. The page copy logic compares the page index of the DMA operation to a copy address pointer that indicates the location currently being copied. If the page index of the DMA operation is less than the copy address pointer, the portion of the page that would be written to by the DMA operation has already been copied, so the DMA operation is performed to the physical address of the new page. If the page index of the DMA operation is greater than the copy address pointer, the portion of the page that would be written to by the DMA operation has not yet been copied, so the DMA operation is performed to the physical address of the old page.08-21-2008
20080201494Controlling complex non-linear data transfers - A direct memory access controller for controlling data transfer between a plurality of data sources and a plurality of data destinations is disclosed. The plurality of data sources and data destinations communicate with the direct memory access controller via a plurality of channels, the direct memory access controller further communicates with a memory and a processor. The memory stores two sets of control data for each of the plurality of channels and for the processor. The direct memory access controller is responsive to a data transfer request received from one of said plurality of channels or from said processor to access one set of said corresponding control data stored in said memory, said direct memory access performing at least a portion of said data transfer requested in dependence upon said accessed control data.08-21-2008
20120284434METHODS AND APPARATUS FOR TRANSPORTING DATA THROUGH NETWORK TUNNELS - Methods and apparatus for efficiently transporting data through network tunnels. In one embodiment, a tunneled device advertises certain capabilities to peer devices of a network, and discovers capabilities of peer devices of the network. In a second embodiment, each device of a tunneled network derives a network parameter from a transit protocol parameter for use in data networking.11-08-2012
20130159562STORAGE SYSTEM, CONTROL DEVICE, AND STORAGE SYSTEM CONTROL METHOD OF CONTROLLING STORAGE SYSTEM - A storage system includes a disk and a CM. The CM includes a main control unit and a sub control unit that distribute and execute processing in the CM. Further the CM includes a plurality of CAs that receive commands related to the input and the output of the data stored in the disk from a host computer. The main control unit requests the sub control unit to copy dump data of a first CA among the plurality of CAs when detecting abnormality of the first CA while copying dump data of a second CA among the plurality of CAs according to abnormality of the second CA.06-20-2013
20110314185MEDIA PROCESSING METHOD AND DEVICE - A media processing system and device with improved power usage characteristics, improved audio functionality and improved media security is provided. Embodiments of the media processing system include an audio processing subsystem that operates independently of the host processor for long periods of time, allowing the host processor to enter a low power state while the audio data is being processed. Other aspects of the media processing system provide for enhanced audio effects such as mixing stored audio samples into real-time telephone audio. Still other aspects of the media processing system provide for improved media security due to the isolation of decrypted audio data from the host processor.12-22-2011
20120030382DIRECT MEMORY ACCESS DEVICE FOR MULTI-CORE SYSTEM AND OPERATING METHOD OF THE SAME - A Direct Memory Access (DMA) device for a multi-core system, and an operating method of the DMA device are provided. The DMA device includes a channel state determining unit to determine whether at least one channel among a source channel and a destination channel is available, the source channel being formed between a source core and the DMA device, and the destination channel being formed between a destination core and the DMA device, and a data transmission processing unit to process data of the source core to be transmitted to the destination core, when both the source channel and the destination channel are determined to be available.02-02-2012
20120036287STORAGE DEVICES WITH BI-DIRECTIONAL COMMUNICATION TECHNIQUES AND METHOD OF FORMING BI-DIRECTIONAL COMMUNICATION LAYER BETWEEN THEM - A storage device includes a storage media storing an information structure for establishing a bidirectional communication layer and a controller configured to send the information structure to an external device according to an information structure read/write command. A layer for a bidirectional communication between the storage device and the external device is formed according to the information structure.02-09-2012

Patent applications in class Direct Memory Accessing (DMA)

Patent applications in all subclasses Direct Memory Accessing (DMA)