# Multiplication

## Subclass of:

## 708 - Electrical computers: arithmetic processing and calculating

## 708100000 - ELECTRICAL DIGITAL CALCULATING COMPUTER

## 708200000 - Particular function performed

## 708490000 - Arithmetical operation

### Patent class list (only not empty are listed)

#### Deeper subclasses:

Class / Patent application number | Description | Number of patent applications / Date published |
---|---|---|

708620000 | Multiplication | 43 |

20110231468 | HIGH-RADIX MULTIPLIER-DIVIDER - The high-radix multiplier-divider provides a system and method utilizing an SRT digit recurrence algorithm that provides for simultaneous multiplication and division using a single recurrence relation. When A, B, D and Q are fractions (e.g., Q=0· | 09-22-2011 |

20090164546 | METHOD AND APPARATUS FOR EFFICIENT PROGRAMMABLE CYCLIC REDUNDANCY CHECK (CRC) - A method and apparatus to optimize each of the plurality of reduction stages in a Cyclic Redundancy Check (CRC) circuit to produce a residue for a block of data decreases area used to perform the reduction while maintaining the same delay through the plurality of stages of the reduction logic. A hybrid mix of Karatsuba algorithm, classical multiplications and serial division in various stages in the CRC reduction circuit results in about a twenty percent reduction in area on the average with no decrease in critical path delay. | 06-25-2009 |

20090157790 | METHOD AND APPARATUS FOR MULTIPLYING POLYNOMIALS WITH A PRIME NUMBER OF TERMS - An efficient method and apparatus to compute a product of polynomials of degree n−1 where n is an arbitrary prime is provided. The total number of multiply operations and Arithmetic Logical Unit (ALU) operations to compute the product is minimized through the judicious use of polynomial evaluations at few points to decrease the number of multiplications while using only simple ALU operations. | 06-18-2009 |

20080275932 | Integer Division In A Manner That Counters A Power Analysis Attack - In the course of performing an Elliptic Curve Scalar Multiplication operation by Additive Splitting Using Division, a main loop of an integer division operation may be performed. The integer division has a dividend and a divisor. By storing both the divisor and the negative value of the divisor, susceptibility to a Simple Power Analysis Side Channel attack is minimized. A carry bit from a previous iteration of the main loop determines which of the divisor or the negative of the divisor to use. The order of an addition operation and a shift left operations in the main loop is interchanged compared to a known integer division method and there are no negation operations in the main loop. | 11-06-2008 |

20140095572 | Multiply and Accumulate Feedback - A method and apparatus may be used to evaluate a polynomial by initializing a multiply and accumulate feedback apparatus ( | 04-03-2014 |

20140006469 | VECTOR MULTIPLICATION WITH OPERAND BASE SYSTEM CONVERSION AND RE-CONVERSION | 01-02-2014 |

20150339101 | BIT-MATRIX MULTIPLICATION USING EXPLICIT REGISTER - The invention relates to a processor comprising, in its instruction set, a bit matrix multiplication instruction (sbmm) having a first double precision operand (A) representing a first matrix to multiply, a second operand (B) explicitly designating any two single precision registers whose joint contents represent a second matrix to multiply, and a destination parameter (C) explicitly designating any two single precision registers for jointly containing a matrix representing the result of the multiplication. | 11-26-2015 |

20130346463 | METHOD AND APPARATUS FOR MULTIPLY INSTRUCTIONS IN DATA PROCESSORS - The disclosed embodiments relate to apparatus for accurately, efficiently and quickly executing a multiplication instruction. The disclosed embodiments can provide a multiplier module having an optimized layout that can help speed up computation of a result during a multiply operation so that cycle delay can be reduced and so that power consumption can be reduced. | 12-26-2013 |

20130166616 | System and Method for Implementing a Multiplication - The present system and method relate to a system for performing a multiplication. The system is arranged for receiving a first data value, and comprises means for calculating at run time a set of instructions for performing a multiplication using the first data value, storage means for storing the set of instructions calculated at run time, multiplication means arranged for receiving a second data value and at least one instruction from the stored set of instructions and arranged for performing multiplication of the first and the second data values using the at least one instruction. | 06-27-2013 |

20140067896 | Universe has an End - The “Big Bung!” was not at the beginning of Universe! | 03-06-2014 |

20120239721 | ARITHMETIC DEVICE, METHOD, AND PROGRAM PRODUCT - An arithmetic device includes an input unit inputting data that are elements of a group; a converting unit is configured, when the input data are in a second representation, to convert the input data into a first representation and to perform arithmetic operation on the converted first representation using an operand in the first representation in which at least one subcomponent is a zero element to convert the converted first representation into first converted data expressed in the first representation, and when the input data are in the first representation, to perform arithmetic operation on the input data using the operand in the first representation in which at least one subcomponent is a zero element to convert the input data into second converted data expressed in the first representation; and an operating unit that performs arithmetic processing on the first or the second converted data using secret information. | 09-20-2012 |

20090157789 | Multiplicative Group Counter - Systems and methods are provided for efficiently counting detected events via a multiplicative group counter. An equivalent class polynomial congruent with a first of a plurality of elements comprising a multiplicative group is represented as a series of binary values. The represented polynomial is subjected to a state transition function as each event is detected, such that the series of binary values is altered to represent a new equivalent class polynomial congruent with a second of the plurality of elements of a multiplicative group. The series of binary values is decoded to determine a number of detected events recorded by the counter. | 06-18-2009 |

20090125576 | Pade approximation convert circuit of direct digital frequency synthesizer - This invention relates to Pade approximation convert circuit of the direct digital frequency synthesizer in which a multiplier receives and multiplies a first input signal and a variable signal so as to produce a multiplication signal; a divider receives and divides a second input signal and a variable signal so as to produce a division signal; an adder receives and adds the multiplication signal and the division signal so as to generate an output signal, that is then returned back to the divider. A quarter period of a sinusoidal wave signal is completed by the proceeding of direct calculation two times such that the time for the calculation of a complete sinusoidal wave can be saved and the area of the calculation circuit can be reduced. | 05-14-2009 |

20100125621 | ARITHMETIC PROCESSING DEVICE AND METHODS THEREOF - An arithmetic processing unit is disclosed that can perform multiply operations, addition operations, or a combination thereof. The arithmetic processing unit can operate in two modes. The first mode supports one single, double, or extended-precision computation, and the second mode supports two simultaneous single-precision computations using the same exponent and mantissa datapaths. | 05-20-2010 |

20130144926 | MINIMUM MEAN SQUARE ERROR PROCESSING - A first systolic array receives an input set of time division multiplexed matrices from a plurality of channel matrices. In a first mode, the first systolic array performs triangularization on the input matrices, producing a first set of matrices, and in a second mode performs back-substitution on the first set, producing a second set of matrices. In a first mode, a second systolic array performs left multiplication on the second set of matrices with the input set of matrices, producing a third set of matrices. In a second mode, the second systolic array performs cross diagonal transposition on the third set of matrices, producing a fourth set of matrices, and performs right multiplication on the second set of matrices with the fourth set of matrices. The first systolic array switches from the first mode to the second mode after the triangularization, and the second systolic array switches from the first mode to the second mode after the left multiplication. | 06-06-2013 |

20140244705 | Phase Aligned Interleaved Sampling of Multiple Data Channels - Provided is a method for processing data samples from a plurality of data channels. The method may include obtaining a plurality of data samples from the plurality of data channels. Obtaining the plurality of data samples may involve successively obtaining a data sample from each data channel of the plurality of data channels. Successively obtaining a data sample from each data channel may be performed a plurality of times during a specified time period. Each data sample of the plurality of data samples may be associated with a respective sample time, and each respective sample time may be relative to a single specified reference point in time. The method may further include, for each data sample of the plurality of data samples, determining a time-dependent coefficient value that may correspond to the sample time associated with the data sample, and applying the determined time-dependent coefficient value to the data sample. | 08-28-2014 |

20120226731 | LOW DEPTH COMBINATIONAL FINITE FIELD MULTIPLIER - A method for generating a design of a multiplier is disclosed. The method generally includes steps (A) to (C). Step (A) may generate a first circuit comprising a plurality of polynomial results of a particular multiplier scheme based on a plurality of parameters of the multiplier. The first circuit is generally configured to multiply a plurality of polynomials. Step (B) may generate a second circuit comprising a plurality of polynomial evaluators based on the parameters. The second circuit may be (i) connected to the first circuit and (ii) configured to evaluate a polynomial modulo operation. Step (C) may generate the design of the multiplier in combinational logic by optimizing a depth of a plurality of logic gates through the first circuit and the second circuit. A product of the polynomials generally resides in a finite field. | 09-06-2012 |

20140046996 | UNIFIED COMPUTATION SYSTEMS AND METHODS FOR ITERATIVE MULTIPLICATION AND DIVISION, EFFICIENT OVERFLOW DETECTION SYSTEMS AND METHODS FOR INTEGER DIVISION, AND TREE-BASED ADDITION SYSTEMS AND METHODS FOR SINGLE-CYCLE MULTIPLICATION - A unified computation unit for iterative multiplication and division may include an architecture having a unified integer iterative multiplication and division circuit. A method may include a device receiving a dividend and a divisor for a division operation, separating the dividend into two parts based on the determining, and evaluating whether an overflow situation exists based on the two parts. A single-cycle multiplication unit may include a multi-operand addition schema for partial products compression that implements tree-based addition methods for single-cycle multiplication operations. | 02-13-2014 |

20130144925 | SYSTEMS AND METHODS FOR SOLVING COMPUTATIONAL PROBLEMS - Solving computational problems may include generating a logic circuit representation of the computational problem, encoding the logic circuit representation as a discrete optimization problem, and solving the discrete optimization problem using a quantum processor. Output(s) of the logic circuit representation may be clamped such that the solving involves effectively executing the logic circuit representation in reverse to determine input(s) that corresponds to the clamped output(s). The representation may be of a multiplication circuit. The discrete optimization problem may be composed of a set of miniature optimization problems, where each miniature optimization problem encodes a respective logic gate from the logic circuit representation. A multiplication circuit may employ binary representations of factors, and these binary representations may be decomposed to reduce the total number of variables required to represent the multiplication circuit. | 06-06-2013 |

708622000 | Complex number format | 3 |

20120166511 | SYSTEM, APPARATUS, AND METHOD FOR IMPROVED EFFICIENCY OF EXECUTION IN SIGNAL PROCESSING ALGORITHMS - Embodiments of systems, apparatuses, and methods for performing a complex multiplication instruction in a computer processor are described. In some embodiments, the execution of such instruction causes a real and an imaginary component resulting from the multiplication of data of first and second complex data source operands to be generated and stored. | 06-28-2012 |

20140032626 | MULTIPLY ACCUMULATE UNIT ARCHITECTURE OPTIMIZED FOR BOTH REAL AND COMPLEX MULTIPLICATION OPERATIONS AND SINGLE INSTRUCTION, MULTIPLE DATA PROCESSING UNIT INCORPORATING THE SAME - A multiply-accumulate unit (MAU) configurable to perform both real and complex multiplication operations, a method of performing a mac operation and a processing unit incorporating the MAU or the method. In one embodiment, the MAU includes: (1) a first multiplier having a first vector input and a first scalar input and configured to multiply a first vector by a first scalar to yield a first product, (2) a second multiplier having a second vector input and a second scalar input and configured to multiply a second vector by a second scalar to yield a second product and (3) an accumulator coupled to the first multiplier and the second multiplier and configured to receive the first and second products. | 01-30-2014 |

20100017453 | PROGRAMMABLE SIGNAL PROCESSING CIRCUIT AND METHOD OF DEMODULATING - A programmable signal processing circuit has an instruction processing circuit ( | 01-21-2010 |

708623000 | Decimal | 3 |

20090132629 | Method for Providing a Decimal Multiply Algorithm Using a Double Adder - A method for performing decimal multiplication including storing a multiplier and a multiplicand in operand registers, the multiplier including one or more digits. A running sum is stored in a shifter and initialized to zero. The method includes performing for each of the digits in the multiplier in order from least significant digit to most significant digit: creating a partial product of the digit and the multiplicand and adding the partial product to the running sum. The running sum is output as the result of multiplying the multiplier and the multiplicand. The performing and outputting are implemented by a mechanism that includes one or more two cycle adders connected to the operand registers, multiplicand multiples circuitry connected to the operand registers, and a result digits register connected to the two cycle adders. | 05-21-2009 |

20120117136 | Data verification algorithm for RF receivers - Sending a set of two data, having actual data and calculated data by using the actual data, to a communication device using RF signal works as a virtual check sum function. | 05-10-2012 |

20120089658 | MODULO OPERATION METHOD AND APPARATUS FOR SAME - The present invention provides a modulo operation method. The modulo operation method, in a case where the square of a divisor N is greater than or equal to a dividend C, includes: determining the number of computation stages n satisfying 2 | 04-12-2012 |

708624000 | Coded decimal | 2 |

20100146030 | Combined Binary/Decimal Fixed-Point Multiplier and Method - A combined binary/decimal fixed-point multiplier that uses BCD-4221 recoding for the decimal digits. This allows the use of binary carry-save hardware to perform decimal addition with a small correction. The described designs provide an improved reduction tree organization to reduce the area and delay of the multiplier and improved reduction tree components that leverage the redundant decimal encodings to help reduce delay. A split reduction tree architecture is also introduced that reduces the delay of the binary product with only a small increase in total area. Area and delay estimates are presented that show that the proposed designs have significant area improvements over separate binary and decimal multipliers while still maintaining similar latencies for both decimal and binary operations. | 06-10-2010 |

20110131266 | Decimal Floating Point Multiplier and Design Structure - Several implementations and a design structure for decimal multiplication that uses a BCD 4221 encoding scheme, separate accumulation of partial products, accumulation of the partial products into a final product and conversion from and to a BCD 8421 coding scheme. | 06-02-2011 |

708625000 | Binary | 16 |

20160034257 | GENERATING A HASH USING S-BOX NONLINEARIZING OF A REMAINDER INPUT - A processor includes a hash register and a hash generating circuit. The hash generating circuit includes a novel programmable nonlinearizing function circuit as well as a modulo-2 multiplier, a first modulo-2 summer, a modulor-2 divider, and a second modulo-2 summer. The nonlinearizing function circuit receives a hash value from the hash register and performs a programmable nonlinearizing function, thereby generating a modified version of the hash value. In one example, the nonlinearizing function circuit includes a plurality of separately enableable S-box circuits. The multiplier multiplies the input data by a programmable multiplier value, thereby generating a product value. The first summer sums a first portion of the product value with the modified hash value. The divider divides the resulting sum by a fixed divisor value, thereby generating a remainder value. The second summer sums the remainder value and the second portion of the input data, thereby generating a hash result. | 02-04-2016 |

20130304787 | DIGITAL SERIAL MULTIPLIER - A multiplier of a binary number A by a binary number B may be configured to add each term A | 11-14-2013 |

20090132630 | METHOD AND APPARATUS FOR MULTIPLYING BINARY OPERANDS - Method and apparatus for multiplying a signed first operand na bits and a signed second operand nb bits, wherein na and nb are different positive integer numbers, the method comprising generating single bit products of pairs of a single bit from the signed first operand and a single bit from the signed second operand with a logical AND function to produce na times nb single bit products, selectively inverting for the signed first operand and the signed second operands the single bit products of the first operand bit na- | 05-21-2009 |

20090083360 | Shift-add based parallel multiplication - A system for performing parallel multiplication on a plurality of factors. In a binary processor, a first and a second memory have pluralities of bit-positions. The first memory holds a first value as a multiplier that will commonly serve as multiple of the factors, and the second memory holds a second value that is representative of multiple multiplicands that are other of the factors. A multiplier bit-count is determined of the significant bits in the multiplier. And a +* operation is performed with the first value and said second value a quantity of times equaling the multiplier bit-count. | 03-26-2009 |

20080256164 | METHODS AND APPARATUS FOR CARRY GENERATION IN A BINARY LOOK AHEAD SYSTEM - Methods and apparatus provide for a carry generation tree for a carry look-ahead binary adder, which includes N stages of operators, reducers, and/or repeaters, wherein: a first of the stages receives binary outputs from a series of binary adders; a last of the stages produces a carry out signal representing the carry state of the series of binary adders; and any operator in a given stage does not receive signals from more than one operator in a preceding stage. | 10-16-2008 |

20100325188 | PROCESSOR AND METHOD FOR IMPLEMENTING INSTRUCTION SUPPORT FOR MULTIPLICATION OF LARGE OPERANDS - A processor including instruction support for implementing large-operand multiplication may issue, for execution, programmer-selectable instructions from a defined instruction set architecture (ISA). The processor may include an instruction execution unit comprising a hardware multiplier datapath circuit, where the hardware multiplier datapath circuit is configured to multiply operands having a maximum number of bits M. In response to receiving a single instance of a large-operand multiplication instruction defined within the ISA, wherein at least one of the operands of the large-operand multiplication instruction includes more than the maximum number of bits M, the instruction execution unit is configured to multiply operands of the large-operand multiplication instruction within the hardware multiplier datapath circuit to determine a result of the large-operand multiplication instruction without execution of programmer-selected instructions within the ISA other than the large-operand multiplication instruction. | 12-23-2010 |

20140067897 | FORMAL VERIFICATION OF BOOTH MULTIPLIERS - Disclosed below are representative embodiments of methods, apparatus, and systems for performing formal verification. For example, certain embodiments can be used to formally verify a Booth multiplier. For instance, in one example embodiment, a specification of a Booth multiplier circuit is received; an initial model checking operation is performed for a smaller version of the Booth multiplier circuit; a series of subsequent model checking operations are performed for versions of the Booth multiplier circuit that are incrementally larger than the smaller version of the Booth multiplier circuit, wherein, for each incrementally larger Booth multiplier circuit, two or more model checking operations are performed, the two or more model checking operations representing decomposed proof obligations for showing; and a verification result of the Booth multiplier circuit is output. | 03-06-2014 |

20140136588 | METHOD AND APPARATUS FOR MULTIPLYING BINARY OPERANDS - Method and apparatus for multiplying a signed first operand na bits and a signed second operand nb bits, wherein na and nb are different positive integer numbers, the method comprising generating single bit products of pairs of a single bit from the signed first operand and a single bit from the signed second operand with a logical AND function to produce na times nb single bit products, selectively inverting for the signed first operand and the signed second operands the single bit products of the first operand bit na−1 multiplied with the second operand bits 0 to nb−2, selectively inverting the single bit products of the signed second operand bits 0 to na−2 multiplied with the signed second operand bit nb−1, after the step of inverting adding the single bit products in accordance with their respective order for producing an intermediate product, and adding a ‘1’ bit value at bit positions nb−1, na−1 and na+nb−1 for receiving a final product. | 05-15-2014 |

20130144927 | METHOD AND APPARATUS FOR PERFORMING MULTIPLICATION IN A PROCESSOR - A method and apparatus are described for performing multiplication in a processor to generate a product. In one embodiment, a 64-bit multiplier and a 64-bit multiplicand may be multiplied together over four cycles by merging different partial product (PP) subsets, generated by a Booth encoder and a PP generator, with feedback sum and carry results. The logic inputs of a plurality of multiplexers may be selected on a cyclical basis to efficiently compress (i.e., merge) each PP subset with feedback sum and carry results. A pair of preliminary sum results stored during one cycle may be outputted during a subsequent cycle and processed by a logic gate (e.g., an XOR gate) to generate a feedback sum result that is merged with a feedback carry result and a PP subset. Final sum and carry results may be added to generate the product of the multiplier and the multiplicand. | 06-06-2013 |

20150317126 | Approximating Functions - A binary logic circuit for approximating a mathematical function over a predefined range as a series of linear segments, each linear segment having one of a predetermined set of fixed gradients and a corresponding base value, the binary logic circuit comprising: an input for receiving an input variable in the predefined range; a plurality of logic chains each comprising: a binary multiplier adapted to perform multiplication by a respective one of the set of fixed gradients using h−1 binary adders, where h is the extended Hamming weight; and a binary adder adapted to add a base value to the input or output of the binary multiplier; and selection logic configured to select one of the logic chains in dependence on the input variable so as to provide, for the received input variable, an approximate value of the mathematical function. | 11-05-2015 |

20150095396 | MULTIPLYING VARYING FIXED-POINT BINARY NUMBERS - Methods and systems for multiplying varying cast numbers are described herein. By using information related to the inputs to be multiplied, a single multiplier module may be used to multiply many different type cast numbers. These systems and methods may reduce hardware costs and complexity, reduce size of the circuitry, and/or reduce the complexity of the logic, among many other benefits. These systems and methods may be used with in industrial controllers in and industrial environment. | 04-02-2015 |

708626000 | Sum of cross products | 1 |

20090198758 | METHOD FOR SIGN-EXTENSION IN A MULTI-PRECISION MULTIPLIER - A method for implementing sign extension within a multi-precision multiplier is described. The method includes receiving a first input within a multiplier core of the multiplier, receiving a second input within the multiplier core, and creating partial products in the multiplier core using the first and second inputs. The method also includes summing up the partial products in a partial product reduction tree in the multiplier core. The method also includes performing sign extension within the partial product reduction tree of the multiplier core by adding a value to a partial product of the partial product reduction tree. The method further includes computing an output from the partial product reduction tree, the output including a final product of the first and second inputs signed extended to a desired width. | 08-06-2009 |

708627000 | Repeated addition | 4 |

708628000 | Multiple digit | 4 |

20090083361 | Shift-add based multiplication - A system for multiplication of multi-bit first and second values. A processor is provided that has first and second memories with bit-positions that can all be zero or one and where the first memory has a low bit (LB). The first value is arranged in the first memory so its LSB is in the first memory LB, and the remaining bit-positions in the first memory are set to zero. The second value is arranged in the second memory such that its LSB is in the bit-position of the second memory that is next higher in order than the MSB of the first value in the first memory, and the remaining bit-positions in the second memory are set to zero. A +* operation is then performed a quantity of times equaling the number of significant bits in the first value, inclusive, thus obtaining the product of the first and second values. | 03-26-2009 |

708629000 | Carry-save adders (i.e., CSAs) | 1 |

20130031154 | SELF-TIMED MULTIPLIER - A self-timed multiplier unit includes a multiplier and a clock generator. The multiplier has a first set of semiconductor circuits in a critical path. The clock generator has a second set of semiconductor circuits configured to control a clock period of said clock generator selected to set a clock period longer than the propagation delay through the critical path of the multiplier. The clock generator may include a delay circuit having a delay to set the clock period longer than the propagation delay through the critical path of said multiplier. The clock generator uses circuit with identical logical design including the same standard cells, the same logic design or the same floor plan. Close matching of these circuit causes the multiplier and the clock generator to experience the same PVT speed variations. | 01-31-2013 |

708630000 | Array adders | 1 |

20090013022 | Multiplier Engine Apparatus and Method - A multiplier engine that reduces the size of the circuitry used to provide the multiplier engine, as well as increases the speed at which the multiplication algorithm is performed, are provided. The illustrative embodiments may comprise a M*8 multiplication engine having one or more 4:2 compressors that comprise only two full adders, as opposed to the three full adders in the known 5:2 compressor based architecture. The 4:2 compressors are able to achieve the same operation as the known 5:2 compressor based architecture by virtue of using the unused bits in a least significant portion of the partial product inputs to store the negate bit values. Moreover, a negate bit value that is not fused with the partial product inputs may be input to the 4:2 compressors for a bit | 01-08-2009 |

708631000 | Pipeline | 1 |

20110106872 | Method and apparatus for providing an area-efficient large unsigned integer multiplier - An area efficient multiplier having high performance at modest clock speeds is presented. The performance of the multiplier is based on optimal choice of a number of levels of Karatsuba decomposition. The multiplier may be used to perform efficient modular reduction of large numbers greater than the size of the multiplier. | 05-05-2011 |