Class / Patent application number | Description | Number of patent applications / Date published |
708606000 | Evaluation of powers | 9 |
20090112962 | MODULAR SQUARING IN BINARY FIELD ARITHMETIC - After squaring an element of a binary field, the squaring result may be reduced modulo the field-defining polynomial g bits at a time. To this end, a lookup table may be employed, where the lookup table stores entries corresponding to reducing g-bit-long polynomials modulo the field-defining polynomial. Such a reducing strategy may be shown to be more efficient than a bit-by-bit reducing strategy. | 04-30-2009 |
20090157788 | MODULAR SQUARING IN BINARY FIELD ARITHMETIC - After squaring an element of a binary field, the squaring result may be reduced modulo the field-defining polynomial g bits at a time. To this end, a lookup table may be employed, where the lookup table stores entries corresponding to reducing g-bit-long polynomials modulo the field-defining polynomial. Such a reducing strategy may be shown to be more efficient than a bit-by-bit reducing strategy. | 06-18-2009 |
20090172068 | METHOD AND APPARATUS FOR EFFICIENTLY IMPLEMENTING THE ADVANCED ENCRYPTION STANDARD - Implementations of Advanced Encryption Standard (AES) encryption and decryption processes are disclosed. In one embodiment of S-box processing, a block of 16 byte values is converted, each byte value being converted from a polynomial representation in GF(256) to a polynomial representation in GF((2 | 07-02-2009 |
20100106763 | RMS Metering Devices and Methods - Embodiments of the present invention provide systems, devices and methods for efficiently calculating a true RMS values (either voltage or current) of an AC signal. The RMS value is generated from both high and low frequency components of the AC signal without a high speed ADC being integrated within the system. The high frequency component is processed by calculating an average current waveform of the high frequency component and approximating a corresponding RMS value using a waveform factor. The waveform factor is effectively a scalar that relates the average current waveform of the high frequency component to an appropriate RMS value. | 04-29-2010 |
20110087719 | MULTIMETER WITH FILTERED MEASUREMENT MODE - A multimeter with filtered measurement mode is disclosed. The multimeter includes a signal conditioning circuit, a low-pass filter, a microprocessor, a measurement circuit, a root-mean-square (RMS) converter, a display unit, and an external rotary switch. The signal conditioning circuit receives a control signal to select an operation mode of the multimeter. The low-pass filter is electrically connected to the signal conditioning circuit. The microprocessor is electrically connected to the signal conditioning circuit. The measurement circuit is electrically connected to the microprocessor and the RMS converter to measure a signal outputted from the RMS converter. The display unit is electrically connected to the microprocessor and the measurement circuit. Also, the external rotary switch is optionally connected to the microprocessor. Whereby rotating the external rotary switch to generate the control signal and perform a low-pass filtering mode to communicate the low-pass filter with the RMS converter. | 04-14-2011 |
20110289131 | MACHINE DIVISION - Techniques are generally described that include methods, devices, systems and/or apparatus for dividing a numerator by a denominator. Some example methods may include selecting a first numerical factor stored in an electronic storage media. The first numerical factor may be multiplied by a numerator at least in part using a first logic circuit configured to perform multiplication. The first numerical factor may also be multiplied by a denominator. A second numerical factor may be calculated based, at least in part, on an approximation of a square of the difference between unity and the product of the first numerical factor and the denominator. The second numerical factor may be multiplied by the product of the numerator and the first numerical factor at least in part using the first logic circuit, to generate an approximation of a quotient of the numerator and the denominator. | 11-24-2011 |
20140129604 | Cryptographic method comprising a modular exponentiation operation - The present invention relates to a method for performing an iterative calculation of exponentiation of a large datum, the method being implemented in an electronic device (DV1) and comprising calculations of squaring and multiplying large variables performed in parallel, by squaring (SB1) and multiplication (SM1) blocks, the method comprising steps of: while a temporary storage buffer memory is not full of unused squares, triggering a calculation by the squaring block for a bit of the exponent, when the squaring block is inactive, storing each square provided by the squaring block in the buffer memory, if the bit of the corresponding exponent is on 1, and while the buffer memory contains an unused square, triggering a calculation by the multiplication block concerning the unused square, when the multiplication block is inactive. | 05-08-2014 |
20140337403 | COMPUTING DEVICE, COMPUTING METHOD, AND COMPUTER PROGRAM PRODUCT - According to an embodiment, a computing device includes an input unit and a power computing unit. The input unit is configured to input, in a form of vector representation, an element of an algebraic torus selected from elements of an M-th (M is an integer of 2 or greater) degree extension field obtained by extending a finite filed by an M-th order polynomial. The power computing unit is configured to compute an N-th (N is an integer of 2 or greater) power of the input element of the algebraic torus, computing the N-th power being performed on the basis of an arithmetic expression for computing the N-th power of an element of the M-th degree extension field expressed in the form of vector representation, and the arithmetic expression being satisfied when the element of the M-th degree extension field satisfies a condition for an element of the algebraic torus. | 11-13-2014 |
20140372496 | METHOD FOR PERFORMING AND VALIDATING NAVIGATION BIT SYNCHRONIZATION - A method for determining bit boundary of a navigation bit of a satellite signal received by a receiver is disclosed. The method includes dividing an assumed navigation bit equally into a plurality of power units, calculating unit powers of each of the plurality of power units, and determining a plurality of phases. Each of the plurality of phases is associated with an estimated bit boundary. The method further includes adding unit powers of the plurality of power units to obtain a plurality of bit powers. Each of the plurality of bit powers corresponds to the estimated bit boundary associated with one of the plurality of phases. The bit boundary of the navigation bit is determined based on the plurality of bit powers. | 12-18-2014 |