| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 708520000 | Matrix array | 17 |
| 20090157787 | ROW-VECTOR NORM COMPARISON METHOD AND ROW-VECTOR NORM COMPARISON APPARATUS FOR INVERSE MATRIX - Disclosed are a row-vector norm comparison method and a row-vector norm comparison apparatus for an inverse matrix. A row-vector norm comparison apparatus includes: an input matrix processing module that receives and combines constituent elements of a matrix; a cofactor operation module that multiplexes the combination result of the constituent elements to calculate factors constituting an adjoint matrix; a square calculation module that squares the calculated factors; a summation module that selects a predetermined number of factors among the squared factors and sums the selected factors to calculate the norms of row vectors in an inverse matrix; and a norm comparison module that outputs a comparison result of the calculated norms of the row vectors. A row-vector norm comparison method includes: combining constituent elements of a matrix to generates a plurality of combination results of the constituent elements; multiplexing the combination results to calculate factors constituting an adjoint matrix of the matrix; squaring the calculated factors and selectively summing the squared factors; and calculating the norms of row vectors in an inverse matrix and comparing the calculated norms of the row vectors. With this configuration, row-vector norm comparison for an inverse matrix can be performed with a design structure. Therefore, it is not necessary to use an existing complex operation method. In addition, low power consumption of the multiple antenna system can be achieved, and efficiency of the design structure can be improved. | 06-18-2009 |
| 20090292755 | METHODS AND APPARATUS FOR SIGNATURE PREDICTION AND FEATURE LEVEL FUSION - A system for signature prediction and feature-level fusion of a target according to various aspects of the present invention includes a first sensing modality for providing a measured data set. The system further includes a processor receiving the measured data set and generating a first k-orthogonal spanning tree constructed from k orthogonal minimal spanning trees having no edge shared between the k minimal spanning trees to define a first data manifold. | 11-26-2009 |
| 20090006518 | Simple MIMO precoding codebook design for a MIMO wireless communications system - The present invention relates to methods and apparatus for establishing a precoding codebook for a Multiple Input Multiple Output (MIMO) wireless communication system. The precoding codebook includes a plurality of codebook entries. Each codebook entry includes four sets of vectors for four respective corresponding transmission ranks. The vectors may be predetermined, or generated from source unitary matrices. In addition, the codebook is fully nested. | 01-01-2009 |
| 20100082724 | Method For Solving Reservoir Simulation Matrix Equation Using Parallel Multi-Level Incomplete Factorizations - A parallel-computing iterative solver is provided that employs a preconditioner that is processed using parallel-computing for solving linear systems of equations. Thus, a preconditioning algorithm is employed for parallel iterative solution of a large sparse system of linear system of equations (e.g., algebraic equations, matrix equations, etc.), such as the linear system of equations that commonly arise in computer-based 3D modeling of real-world systems (e.g., 3D modeling of oil or gas reservoirs, etc.). A novel technique is proposed for application of a multi-level preconditioning strategy to an original matrix that is partitioned and transformed to block bordered diagonal form. An approach for deriving a preconditioner for use in parallel iterative solution of a linear system of equations is provided. In particular, a parallel-computing iterative solver may derive and/or apply such a preconditioner for use in solving, through parallel processing, a linear system of equations. | 04-01-2010 |
| 20090106343 | METHOD AND STRUCTURE FOR PRODUCING HIGH PERFORMANCE LINEAR ALGEBRA ROUTINES USING COMPOSITE BLOCKING BASED ON L1 CACHE SIZE - A method (and structure) for performing a matrix subroutine, includes storing data for a matrix subroutine call in a computer memory in an increment block size that is based on a cache size. | 04-23-2009 |
| 20120296950 | METHOD AND APPARATUS FOR QR-FACTORIZING MATRIX ON A MULTIPROCESSOR SYSTEM - A method and apparatus for QR-factorizing matrix on a multiprocessor system, wherein the multiprocessor system comprises at least one core processor and a plurality of accelerators, comprises the steps of: iteratively factorizing each panel in the matrix until the whole matrix is factorized; wherein in each iteration, the method comprises: partitioning an unprocessed matrix part in the matrix into a plurality of blocks according to a predetermined block size; partitioning a current processed panel in the unprocessed matrix part into at least two sub panels, wherein the current processed panel is composed of a plurality of blocks; and performing QR factorization one by one on the at least two sub panels with the plurality of accelerators, and updating the data of the sub panel(s) on which no QR factorization has been performed among the at least two sub panels by using the factorization result. | 11-22-2012 |
| 20090063607 | METHOD AND STRUCTURE FOR FAST IN-PLACE TRANSFORMATION OF STANDARD FULL AND PACKED MATRIX DATA FORMATS - A method and structure for an in-place transformation of matrix data. For a matrix A stored in one of a standard full format or a packed format and a transformation T having a compact representation, blocking parameters MB and NB are chosen, based on a cache size. A sub-matrix A | 03-05-2009 |
| 20090248778 | SYSTEMS AND METHODS FOR A COMBINED MATRIX-VECTOR AND MATRIX TRANSPOSE VECTOR MULTIPLY FOR A BLOCK-SPARSE MATRIX - Systems and methods for combined matrix-vector and matrix-transpose vector multiply for block sparse matrices. Exemplary embodiments include a method of updating a simulation of physical objects in an interactive computer, including generating a set of representations of objects in the interactive computer environment, partitioning the set of representations into a plurality of subsets such that objects in any given set interact only with other objects in that set, generating a vector b describing an expected position of each object at the end of a time interval h, applying a biconjugate gradient algorithm to solve A*Δv=b for the vector Δv of position and velocity changes to be applied to each object wherein the q=Ap and qt=A | 10-01-2009 |
| 20090063608 | Full Vector Width Cross Product Using Recirculation for Area Optimization - Embodiments of the invention are generally related to the field of image processing, and more specifically to vector units for supporting image processing. A vector unit may comprise a plurality of operand multiplexers associated with each vector processing lane of the vector unit. The operand multiplexers may select vector operands from one or more register files for performing a cross product operation. A first multiply operation may be performed in a first pipeline stage by multiplying a first set of operands in a multiplier. In a second pipeline stage, a second multiply operation may be performed by multiplying a second set of operands. The results of the first multiply operation and the second multiply operation may be transferred to an adder to complete the cross product instruction. | 03-05-2009 |
| 20100241683 | METHOD AND APPARATUS FOR ARITHMETIC OPERATION BY SIMULTANEOUS LINEAR EQUATIONS OF SPARSE SYMMETRIC POSITIVE DEFINITE MATRIX - An arithmetic operation apparatus includes: a branch node set detection unit to detect a set of branch nodes for each parallel level; a subtree memory storage area allocation unit to allocate an arithmetic result of a column vector to a memory storage area selected on a basis of a predetermined selection rule from a plurality of memory storage areas; and a node memory storage area allocation unit to allocate an arithmetic result of a column vector to a memory storage area selected on a basis of a predetermined selecting rule from a plurality of memory storage areas. | 09-23-2010 |
| 20090077153 | Reconfigurable arithmetic unit - A reconfigurable arithmetic circuit including a plurality of logical AND gates arranged in logical columns and rows, a plurality of conductors each connected to furnish input to the AND gates of a row, an array of memory cells each connected to furnish input to one of the AND gates, and a plurality of reconfigurable counting circuits, each counting circuit connected to receive the output of each of the AND gates in a column, each counting circuit being configurable to provide a count of parity of the outputs furnished by the AND gates of the column. | 03-19-2009 |
| 20100306300 | Sparse Matrix Padding - Zero elements are added to respective lines (e.g., rows/columns) of a sparse matrix. The added zero elements increase the number of elements in the respective lines to be a multiple of a predetermined even number “n” (e.g., 2, 4, 8, etc.), based upon an n-fold unrolling loop, where n=2, 4, 8, etc. By forming a sparse matrix having lines (e.g., rows or columns) that are multiples of the predetermined number “n”, the n-fold unrolling loop thereby acts upon a predetermined number of elements in respective iterations, avoiding unnecessarily costly operations (e.g., additional loop unrolling code) on remainder non-zero elements (e.g. remainder row/column elements not within an n-fold unrolling loop) left in a row or column after unrolling. This improves the efficiency of sparse matrix linear algebra solvers and key sparse linear algebra kernels (e.g., SPMV) thereby improving the overall performance of a computer (e.g., running an application). | 12-02-2010 |
| 20110010411 | VIEW PROJECTION - A first derived matrix of transport coefficients and a second derived matrix of transport coefficients are derived from a primary matrix of transport coefficients Each of the transport coefficients describes transport of a respective image forming element from a first position onto one or more image forming elements at a second position. An approximate inverse of the first derived matrix is ascertained. A modified version of a projection image is determined from the projection image, the approximated inverse of the first derived matrix, and the second derived matrix. The modified version of the projection image is rendered from the first position onto a physical medium at the second position. | 01-13-2011 |
| 20110191401 | CIRCUIT AND METHOD FOR CHOLESKY BASED DATA PROCESSING - A method for Cholesky based processing of data includes receiving a first matrix that equals a product of a first lower triangular matrix and a first upper triangular matrix, where the first upper triangular matrix is a complex conjugate transpose of the first lower triangular matrix, and applying, by a processing unit that has a set of P processors, a loopless Cholesky factorization process on each equally sized block of multiple equally sized blocks of the first matrix to provide the first lower triangular matrix. Each equally sized block has E elements, where E is a integer multiple of P. | 08-04-2011 |
| 20080250094 | EFFICIENT IMPLEMENTATIONS OF KERNEL COMPUTATIONS - A method and apparatus for efficiently performing digital signal processing is provided. In one embodiment, kernel matrix computations are simplified by grouping similar kernel coefficients together. Each coefficient group contains only coefficients having the same value. At least one of the coefficient groups has at least two coefficients. Techniques are disclosed herein to efficiently apply successive first order difference operations to a data signal. The techniques allow for a low gate count. In particular, the techniques allow for a reduction of the number of multipliers without increasing clock frequency, in an embodiment. The techniques update pixels of a data signal at a rate of two clock cycles per each pixel, in an embodiment. The techniques allow hardware that is used to process a first pixel to be re-used to start the processing of a second pixel while the first pixel is still being processed. | 10-09-2008 |
| 20130138712 | MINIMUM MEAN SQUARE ERROR PROCESSING - A first systolic array receives an input set of time division multiplexed matrices from a plurality of channel matrices. In a first mode, the first systolic array performs triangularization on the input matrices, producing a first set of matrices, and in a second mode performs back-substitution on the first set, producing a second set of matrices. In a first mode, a second systolic array performs left multiplication on the second set of matrices with the input set of matrices, producing a third set of matrices. In a second mode, the second systolic array performs cross diagonal transposition on the third set of matrices, producing a fourth set of matrices, and performs right multiplication on the second set of matrices with the fourth set of matrices. The first systolic array switches from the first mode to the second mode after the triangularization, and the second systolic array switches from the first mode to the second mode after the left multiplication. | 05-30-2013 |
| 20130124593 | QUANTIFYING MEHTOD FOR INTRINSIC DATA TRANSFER RATE OF ALGORITHMS - The quantifying method for intrinsic data transfer rate of algorithms is provided. The provided quantifying method for an intrinsic data transfer rate includes steps of: detecting whether or not a datum is used; providing a dataflow graph G including n vertices and m edges, and a Laplacian matrix L having ixj elements L(i,j) when the datum is not reused, wherein each of the vertices represents one of an operation and a datum, each of the edges represents a data transfer, and vi is the ith vertex; and using the Laplacian matrix L to estimate a maximum quantity of the intrinsic data transfer rate. | 05-16-2013 |
