Class / Patent application number | Description | Number of patent applications / Date published |
708503000 | Multiplication | 10 |
20080228846 | PROCESSING APPARATUS AND CONTROL METHOD THEREOF - A processing apparatus comprising a register that stores operand data, a register data reading section that reads operand data stored in the register, a coefficient table set storage section that stores a coefficient table storing Taylor series operation coefficient data, a coefficient data reading section that reads the Taylor series coefficient data from the coefficient table set storage section using the degree information of the Taylor series and the coefficient table identification information and a floating point multiply-adder that executes the Taylor series operation using the coefficient data read by the coefficient data reading section, data read from the register. | 09-18-2008 |
20080307029 | Arithmetic device and arithmetic method - An FMA arithmetic unit has a timing control circuit. The timing control circuit controls bypass selectors to bypass intermediate resisters on performing floating point addition/subtraction, controls another bypass selector to bypass another intermediate register on performing floating point multiplication, and controls still another bypass selectors to bypass a register file/other arithmetic unit result register and operand registers on performing successive FMA arithmetic operations. | 12-11-2008 |
20090164544 | Dynamic range enhancement for arithmetic calculations in real-time control systems using fixed point hardware - A digital processing system and method are described that encodes a fixed point number into a mantissa by removing redundant sign bits by shifting the significant bits to the left. The number of bits shifted is recorded as the exponent. In one embodiment the mantissa and exponent are combined into a single word of memory for the system which allows efficient loading of the value from memory. The mantissa and exponent can be used in multiplication calculations with a second fixed point number to achieve increased dynamic range. When the mantissa is multiplied by the fixed point number, the initial result is larger by a factor of 2 | 06-25-2009 |
20120059866 | METHOD AND APPARATUS FOR PERFORMING FLOATING-POINT DIVISION - A method and apparatus provides for performing floating-point division using input check/output correction floating-point division logic and a floating-point division fix-up instruction (e.g., an instruction, command, signal or other indicator). In one example, the apparatus includes a processor having a floating-point arithmetic logic unit (ALU) that includes the input check/output correction floating-point division logic. The input check/output correction floating-point division logic is responsive to the floating-point division fix-up instruction executable by the floating-point ALU that causes the input check/output correction floating-point division logic to examine a first input representing a numerator and a second input representing a denominator to determine whether a special case of floating-point division occurs. The floating-point division fix-up instruction also causes the input check/output correction floating-point division logic to provide an output representing a floating-point division result based on the determined special case of floating-point division and a third input representing a candidate quotient. | 03-08-2012 |
20120259904 | FLOATING POINT FORMAT CONVERTER - A computer program product for converting from a first floating point format to a second floating point format, each floating point format having an associated base value and being represented by a significand value and a exponent value, comprising an executable algorithm to perform the steps of: determining the second exponent value by multiplying the first exponent value by a predefined constant and taking the integer portion of the result, the predefined constant being substantially equivalent to the logarithm of the first base value divided by the logarithm of the second base value; determining a bias value substantially equivalent to the second base value raised to the second exponent value divided by the first base value raised to the first exponent value; and determining the second significand value by multiplying the first significand value by the bias value. | 10-11-2012 |
20130138711 | SHARED INTEGER, FLOATING POINT, POLYNOMIAL, AND VECTOR MULTIPLIER - A multiplier for performing multiple types of multiplication including integer, floating point, vector, and polynomial multiplication. The multiplier includes a modified booth encoder within the multiplier and unified circuitry to perform the various types of multiplication. A carry save adder tree is modified to route sum outputs to one part of the tree and to route carry outputs to another part of the tree. The carry save adder tree is also organized into multiple carry save adder trees to perform vector multiplication. | 05-30-2013 |
20140089371 | MIXED PRECISION FUSED MULTIPLY-ADD OPERATOR - A circuit for calculating the fused sum of an addend and product of two multiplicands, the addend and multiplicands being binary floating-point numbers represented in a standardized format as a mantissa and an exponent is provided. The multiplicands are in a lower precision format than the addend, with q>2p, where p and q are respectively the mantissa size of the multiplicand precision format and the addend precision format. The circuit includes a p-bit multiplier receiving the mantissas of the multiplicands; a shift circuit that aligns the mantissa of the addend with the product output by the multiplier based on the exponent values of the addend and multiplicands; and an adder that processes q-bit mantissas, receiving the aligned mantissa of the addend and the product, the input lines of the adder corresponding to the product being completed to the right by lines at 0 to form a q-bit mantissa. | 03-27-2014 |
20160110163 | SMALL MULTIPLIER AFTER INITIAL APPROXIMATION FOR OPERATIONS WITH INCREASING PRECISION - In an aspect, a processor includes circuitry for iterative refinement approaches, e.g., Newton-Raphson, to evaluating functions, such as square root, reciprocal, and for division. The circuitry includes circuitry for producing an initial approximation; which can include a LookUp Table (LUT). LUT may produce an output that (with implementation-dependent processing) forms an initial approximation of a value, with a number of bits of precision. A limited-precision multiplier multiplies that initial approximation with another value; an output of the limited precision multiplier goes to a full precision multiplier circuit that performs remaining multiplications required for iteration(s) in the particular refinement process being implemented. For example, in division, the output being calculated is for a reciprocal of the divisor. The full-precision multiplier circuit requires a first number of clock cycles to complete, and both the small multiplier and the initial approximation circuitry complete within the first number of clock cycles. | 04-21-2016 |
20160179467 | Processing with Compact Arithmetic Processing Element | 06-23-2016 |
20170237440 | Processor Comprising Three-Dimensional Memory (3D-M) Array | 08-17-2017 |