Class / Patent application number | Description | Number of patent applications / Date published |
708492000 | Galois field | 20 |
20080215658 | GENERIC IMPLEMENTATIONS OF ELLIPTIC CURVE CRYPTOGRAPHY USING PARTIAL REDUCTION - A reduction operation is utilized in an arithmetic operation on two binary polynomials X(t) and Y(t) over GF(2), where an irreducible polynomial M | 09-04-2008 |
20080270505 | EFFICIENT HARDWARE IMPLEMENTATION OF TWEAKABLE BLOCK CIPHER - A combination of an infrequently-called tiny multiplication unit and a “differential” unit that quickly computes T | 10-30-2008 |
20090006517 | UNIFIED INTEGER/GALOIS FIELD (2m) MULTIPLIER ARCHITECTURE FOR ELLIPTIC-CURVE CRYTPOGRAPHY - A unified integer/Galois-Field 2 | 01-01-2009 |
20090063606 | Methods and Apparatus for Single Stage Galois Field Operations - Techniques for single function stage Galois field (GF) computations are described. The new single function stage GF multiplication requires only m-bits per internal logic stage, a savings of m−1 bits per logic stage that do not have to be accounted for as compared with a previous two function stage approach. Also, a common design CF multiplication cell is described that may be suitably used to construct an m-by-m GF multiplication array for the calculation of GF[2 | 03-05-2009 |
20090287756 | Computing Modular Polynomials Modulo Large Primes - Systems and methods for computing modular polynomials modulo large primes are described. In one aspect, the systems and methods generate l-isogenous elliptic curves. A modular polynomial modulo a large prime p is then computed as a function of l-isogenous elliptic curves modulo p. | 11-19-2009 |
20100023572 | RANDOMIZED MODULAR POLYNOMIAL REDUCTION METHOD AND HARDWARE THEREFOR - A cryptographically secure, computer hardware-implemented binary finite-field polynomial modular reduction method estimates and randomizes a polynomial quotient used for computation of a polynomial remainder. The randomizing error injected into the approximate polynomial quotient is limited to a few bits, e.g. less than half a word. The computed polynomial remainder is congruent with but a small random multiple of the residue, which can be found by a final strict binary field reduction by the modulus. In addition to a computational unit and operations sequencer, the computing hardware also includes a random or pseudo-random number generator for producing the random polynomial error. The modular reduction method thus resists hardware cryptoanalysis attacks, such as timing and power analysis attacks. | 01-28-2010 |
20100057823 | Alternate galois field advanced encryption standard round - An apparatus having a first circuit and a second circuit is disclosed. The first circuit may be configured to (i) generate second Galois Field elements by performing a first Galois Field inversion on first Galois Field elements, the first Galois Field inversion being different from a second Galois Field inversion defined by an Advanced Encryption Standard and (ii) generate third Galois Field elements by multiplying the second Galois Field elements by an inverse of a predetermined matrix. The second circuit may be configured to (i) generate fourth Galois Field elements by processing the third Galois Field elements in a current encryption round while in a non-skip mode, (ii) generate fifth Galois Field elements by multiplying the fourth Galois Field elements by the predetermined matrix and (iii) present the fifth Galois Field elements as updated versions of the first Galois Field elements in advance of a next encryption round. | 03-04-2010 |
20100063986 | COMPUTING DEVICE, METHOD, AND COMPUTER PROGRAM PRODUCT - In a computing device that calculates a square of an element in a finite field, a vector representation of the element in the finite field is accepted. The vector representation includes a plurality of elements. The computing device performs a multiplication operation on a base field using the accepted elements, and obtains a multiplication value. The multiplication operation is determined by a condition under which the element in the finite field is placed in an algebraic torus. The computing device performs an addition and subtraction operation using the obtained multiplication value and the accepted elements, and obtains a calculation result of the square of the element. The addition and subtraction operation is determined by the condition. The computing device then outputs the calculation result. | 03-11-2010 |
20100082723 | Method, Apparatus and Media for Performing GF(2) Polynomial Operations - Methods, apparatus and media for performing polynomial arithmetic operations over a Galois field having characteristic 2 and size 1 are disclosed. Such methods, apparatus and media include generating a binary representation of a polynomial over a Galois field having characteristic 2 and size 1, generating a plurality of right shifted binary representations of the first polynomial, and generating a binary representation of the polynomial reciprocal based upon a bitwise exclusive-OR of the binary representation of the polynomial and one or more right shifted binary representations selected from the plurality of right shifted binary representations. | 04-01-2010 |
20100115017 | Semi-Sequential Galois Field Multiplier And The Method For Performing The Same - Disclosed are a semi-sequential Galois field GF(2 | 05-06-2010 |
20100306299 | Circuits and Methods for Performing Exponentiation and Inversion of Finite Field Elements - An exponentiation circuit for computing an exponential power of a finite field element includes combinatory logic circuits that map input digits of a multi-digit field element P to output digits of an output multi-digit field element β | 12-02-2010 |
20110202587 | SYSTEM AND METHOD FOR PROCESSING DATA USING A MATRIX OF PROCESSING UNITS - A system and method for processing data utilizes a matrix of processing units using an array of commands stored in memory to process input data words to generate output data words, which can be used in various applications. | 08-18-2011 |
20110246548 | SEQUENTIAL GALOIS FIELD MULTIPLICATION ARCHITECTURE AND METHOD - A sequential Galois field (GF) multiplication architecture based on Mastrovito's multiplication and composite field has a two-tier architecture for performing GF(2 | 10-06-2011 |
20120239718 | CONNECTION INFORMATION GENERATING APPARATUS AND CONTROLLING METHOD - A connection information generating apparatus that generates connection information that indicates connections between a plurality of first transferring devices and a plurality of second transferring devices. The connection information generating apparatus includes a creating unit that creates an addition table and a multiplication table in a Galois field that has a characteristic of a value based on a number of the second transferring devices that are connected to each of the first transferring devices. The connection information generating apparatus includes a generating unit that generates connection information defining groups of first transferring devices to be connected to each of the second transferring devices, in accordance with the multiplication table and the addition table created by the creating unit. | 09-20-2012 |
20120311007 | SQUARING BINARY FINITE FIELD ELEMENTS - Methods and systems for squaring a binary finite field element are described. In some aspects, a data processing apparatus includes registers and processor logic. A first register stores a sequence of binary values that define a binary finite field element input. The processor logic accesses input components from the first register according to intervals in the sequence. Each input component includes a binary value from each interval in the sequence. In some cases, the intervals are periodic and the binary finite field element corresponds to a sum of phase-shifted input components. The processor logic generates output components based on the input components. The processor logic generates a square of the binary finite field element in the second register based on the output components. The number of input components can be selected, for example, to balance costs of additional processing time against benefits associated with reduced processing hardware. | 12-06-2012 |
20140012889 | Construction Methods for Finite Fields with Split-optimal Multipliers - Improved multiplier construction methods facilitate efficient multiplication in finite fields. Implementations include digital logic circuits and user scaleable software. Lower logical circuit complexity is achieved by improved resource sharing with subfield multipliers. Split-optimal multipliers meet a lower bound measuring complexity. Multiplier construction methods are applied repeatedly to build efficient multipliers for large finite fields from small subfield components. | 01-09-2014 |
20140149479 | METHOD OF PERFORMING MULTIPLICATION OPERATION IN BINARY EXTENSION FINITE FIELD - In a method of performing a multiplication operation in a binary extension finite field, a polynomial defined by | 05-29-2014 |
20140280423 | METHOD AND SYSTEM OF IMPROVED REED-SOLOMON DECODING - Embodiments of an improved Galois multiplication route are described. In some embodiments, the Galois multiplication routine looks up and retrieves a first value corresponding to an address in the Galois table, exclusive ORs the retrieved value with a data value from a data set to generate an intermediate address for the Galois table, wherein the data value is at a location associated with an index, and looks up and retrieves a second value in the Galois table by the intermediate address. | 09-18-2014 |
20150067011 | FINITE FIELD INVERTER - A finite field inverter is disclosed, wherein the finite field inverter includes an input port, an output port and a search tree inverse circuit configured to perform an inverse operation of the operand α(x) in the finite field GF (2 | 03-05-2015 |
20160147504 | CUBIC ROOT OF A GALOIS FIELD ELEMENT - A method includes receiving a first element of a Galois Field of order q | 05-26-2016 |