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# Arithmetical operation

## Subclass of:

## 708 - Electrical computers: arithmetic processing and calculating

## 708100000 - ELECTRICAL DIGITAL CALCULATING COMPUTER

## 708200000 - Particular function performed

### Patent class list (only not empty are listed)

#### Deeper subclasses:

Class / Patent application number | Description | Number of patent applications / Date published |
---|---|---|

708495000 | Floating point | 84 |

708670000 | Addition/subtraction | 41 |

708491000 | Residue number | 34 |

708620000 | Multiplication | 29 |

708650000 | Division | 23 |

708520000 | Matrix array | 19 |

708607000 | Multiplication of matrices | 17 |

708492000 | Galois field | 15 |

708523000 | Multiplication followed by addition (i.e., x*y+z) | 14 |

708550000 | Compensation for finite word length | 8 |

708530000 | Error detection or correction | 8 |

708524000 | Multiple parallel operations | 8 |

708606000 | Evaluation of powers | 6 |

708517000 | Logarithmic format | 5 |

20130080494 | ARITHMETIC DEVICE AND DATABASE - An arithmetic device includes a database that stores a first indicator representing a base unit included in a unit system being assigned with a prime number other than a prime factor of a prefix, and a second indicator derived by combining the base units, in a form of a simple fraction; a conversion section that obtains a plurality of physical quantities each including a quantity, a prefix, and possibly a unit, to derive a third indicator by converting the unit into the first indicator and multiplying the converted first indicator by the prefix, or when the unit belongs to the derived unit, by converting the unit into the second indicator and multiplying the converted second indicator by the prefix; and an arithmetic section that performs calculation between the quantities of the plurality of physical quantities and between the third indicators. | 03-28-2013 |

20090164545 | Electronic Circuitry and Method for Determination of Amplitudes of Received Signals - A method and a calculating circuit for generating an output signal representing an actual amplitude of a received digitized signal having a magnitude of the actual amplitude equal or greater than a value of a saturation level of a dynamic range of a receiver. For the determination of the actual amplitude, firstly, a predetermined time interval is selected. Then, a total number of samples of the received digitized signal within the predetermined time interval is calculated. Further, a number of samples of the received digitized signal within the predetermined time interval with the amplitude equal to the saturation level is calculated. Thereafter, a ratio between the number of the samples with the amplitude value equal to the saturation level and the total number of the samples is calculated. For calculation of the magnitude of the actual amplitude a predetermined relationship between the magnitude of the amplitude and the ratio is applied and the output signal representing the actual amplitude is provided. | 06-25-2009 |

20120203814 | COMPUTER FOR AMDAHL-COMPLIANT ALGORITHMS LIKE MATRIX INVERSION - A family of computers is disclosed and claimed that supports simultaneous processes from the single core up to multi-chip Program Execution Systems (PES). The instruction processing of the instructed resources is local, dispensing with the need for large VLIW memories. The cores through the PES have maximum performance for Amdahl-compliant algorithms like matrix inversion, because the multiplications do not stall and the other circuitry keeps up. Cores with log based multiplication generators improve this performance by a factor of two for sine and cosine calculations in single precision floating point and have even greater performance for log | 08-09-2012 |

20080208946 | Method Of Data Analysis - A method of analysis of incomplete data sets to detect fraudulent data is disclosed. The method comprises computing constant values for various leading digit sequence lengths, computing artificial Benford frequencies for the digit sequence lengths, computing a standard deviation for each of the sequence lengths, and flagging any digit sequences in the data set that deviate more than an upper bound number of standard deviations from the artificial Benford frequencies, the upper bound used to determine if the observed data deviates enough to be considered anomalous and potentially indicative of fraud or abuse. | 08-28-2008 |

20120011186 | METHOD FOR QUANTIFYING AND ANALYZING INTRINSIC PARALLELISM OF AN ALGORITHM - A method for quantifying and analyzing intrinsic parallelism of an algorithm is adapted to be implemented by a computer, and includes the steps of: configuring the computer to represent the algorithm by means of a plurality of operation sets; configuring the computer to obtain a Laplacian matrix according to the operation sets; configuring the computer to compute eigenvalues and eigenvectors of the Laplacian matrix; and configuring the computer to obtain a set of information related to intrinsic parallelism of the algorithm according to the eigenvalues and the eigenvectors of the Laplacian matrix. | 01-12-2012 |

708521000 | Pipeline | 4 |

20090037508 | METHOD FOR IMPLEMENTING MONTGOMERY MODULAR MULTIPLICATION AND DEVICE THEREFORE - Device for implementing modular multiplication, characterized in that it comprises at least one computation cell comprising a multiplier-adder comprising p pipelined logic-register pairs, receiving several digits to be added together and multiplied, at least two outputs corresponding to the low order and to the high order, an adder receiving the two outputs of the multiplier-adder, the number p being chosen in such a way that the maximum frequency of the multiplier-adder is greater than or equal to the maximum frequency of the adder. | 02-05-2009 |

20100121899 | Methods and apparatus for efficient complex long multiplication and covariance matrix implementation - Efficient computation of complex long multiplication results and an efficient calculation of a covariance matrix are described. A parallel array VLIW digital signal processor is employed along with specialized complex long multiplication instructions and communication operations between the processing elements which are overlapped with computation to provide very high performance operation. Successive iterations of a loop of tightly packed VLIWs may be used allowing the complex multiplication pipeline hardware to be efficiently used. | 05-13-2010 |

20120233234 | SYSTEM AND METHOD OF BYPASSING UNROUNDED RESULTS IN A MULTIPLY-ADD PIPELINE UNIT - A processing unit, system, and method for performing a multiply operation in a multiply-add pipeline. To reduce the pipeline latency, the unrounded result of a multiply-add operation is bypassed to the inputs of the multiply-add pipeline for use in a subsequent operation. If it is determined that rounding is required for the prior operation, then the rounding will occur during the subsequent operation. During the subsequent operation, a Booth encoder not utilized by the multiply operation will output a rounding correction factor as a selection input to a Booth multiplexer not utilized by the multiply operation. When the Booth multiplexer receives the rounding correction factor, the Booth multiplexer will output a rounding correction value to a carry save adder (CSA) tree, and the CSA tree will generate the correct sum from the rounding correction value and the other partial products. | 09-13-2012 |

20090132628 | Method for Performing Decimal Division - A method for performing decimal division including receiving a scaled divisor and a scaled dividend into input registers. A subset of multiples of the scaled divisor is stored in a plurality of multiples registers. Quotient digits are calculated in response to the scaled divisor and the scaled dividend. Each quotient digit is calculated in three clock cycles by a pipeline mechanism. The calculating includes selecting a new quotient digit, and calculating a new remainder. Input to the calculating a new remainder includes data from one or more of the multiples registers. | 05-21-2009 |

708603000 | Sum of products generation | 3 |

20080307031 | Fast Modular Zero Sum and Ones Sum Determination - In one embodiment, a state determiner comprises a plurality of logic circuits and a second logic circuit. Each logic circuit corresponds to a respective bit position of a result of an adder. A first logic circuit corresponds to a least significant bit of the result and is coupled to receive a least significant bit of each operand of the adder and a carry-in input to the adder. Each remaining logic circuit is coupled to receive a respective bit from the respective bit position of each operand and a less significant bit adjacent to the respective bit of each operand. Each logic circuit is configured to generate an output signal indicative of whether or not a specific result occurs in the respective bit position of the result responsive only to inputs that the logic circuit is coupled to receive as stated previously. Coupled to receive the output signals from the logic circuits, the second logic circuit is configured to generate a sum signal indicative, when asserted, that the specific result occurs in each bit position of the result of the adder. | 12-11-2008 |

20110106871 | Apparatus and method for performing multiply-accumulate operations - A data processing apparatus and method for performing multiply-accumulate operations is provided. The data processing apparatus includes data processing circuitry responsive to control signals to perform data processing operations on at least one input data element. Instruction decoder circuitry is responsive to a predicated multiply-accumulate instruction specifying as input operands a first input data element, a second input data element, and a predicate value, to generate control signals to control the data processing circuitry to perform a multiply-accumulate operation by: multiplying said first input data element and said second input data element to produce a multiplication data element; if the predicate value has a first value, producing a result accumulate data element by adding the multiplication data element to an initial accumulate data element; and if the predicate value has a second value, producing the result accumulate data element by subtracting the multiplication data element from the initial accumulate data element. Such an approach provides a particularly efficient mechanism for performing complex sequences of multiply-add and multiply-subtract operations, facilitating improvements in performance, energy consumption and code density when compared with known prior art techniques. | 05-05-2011 |

20120278375 | Exponentiation System - A method for computation, including defining a sequence of n bits that encodes an exponent d, such that no more than a specified number of successive bits in the sequence are the same, initializing first and second registers using a value of a base x that is to be exponentiated, whereby the first and second registers hold respective first and second values, which are successively updated during the computation, successively, for each bit in the sequence computing a product of the first and second values, depending on whether the bit is one or zero, selecting one of the first and second registers, and storing the product in the selected one of the registers, whereby the first and second registers hold respective first and second final values upon completion of the sequence, and returning x | 11-01-2012 |

708605000 | Evaluation of root | 3 |

20090083359 | APPARATUS FOR CALCULATING SQUARE ROOT - Provided is a square root calculation apparatus. The apparatus includes a section judgment unit, a coefficient storing unit, and an adder. The section judgment unit stores information regarding a plurality of sections obtained by dividing an entire range of an input value into predetermined intervals, and judges one of the sections to which the input value belongs when the input value is input. The coefficient storing unit stores, in advance, first-order term coefficients and constant terms of first-order approximate equations obtained by approximating square root curves for respective sections, multiplies a first-order term coefficient of the first-order approximate equation in the section to which the input value belongs, by the input value to output a first-order term, and outputs a constant term in the section to which the input value belongs. The adder adds the first-order term and the constant term output from the coefficient storing unit to calculate an approximated square root value. | 03-26-2009 |

20100198902 | COMPUTING MINIMAL POLYNOMIALS OF RADICAL EXPRESSIONS - Described is a technology, such as implemented in a computational software program, by which a minimal polynomial is efficiently determined for a radical expression based upon its structure of the radical expression. An annihilation polynomial is found based upon levels of the radical to obtain roots of the radical. A numerical method performs a zero test or multiple zero tests to find the minimal polynomial. In one implementation, the set of roots corresponding to a radical expression is found. The annihilation polynomial is computed by grouping roots of the set according to their conjugation relationship and multiplying factor polynomials level by level. A selection mechanism selects the minimal polynomial based upon the annihilation polynomial's factors. | 08-05-2010 |

20120066282 | Whole 1 number method of integer factorization - Disclosed is a method for factoring integers by squaring computation time. The present invention uses binary numbers to process invert function of multiplication as factorization. Inverse method of integer factorization uses a diamond expansion form to arrange the digit positions of 1-numbers and 0-numbers subtracted from the product number P and its complement number No. The complement number N | 03-15-2012 |

708604000 | All four basic functions | 2 |

20130218939 | EXPONENTIATION CALCULATION APPARATUS AND METHOD FOR CALCULATING SQUARE ROOT IN FINITE EXTENSION FIELD - In a computing device that calculates a square of an element in a finite field, a vector representation of the element in the finite field is accepted. The vector representation includes a plurality of elements. The computing device performs a multiplication operation on a base field using the accepted elements, and obtains a multiplication value. The multiplication operation is determined by a condition under which the element in the finite field is placed in an algebraic torus. The computing device performs an addition and subtraction operation using the obtained multiplication value and the accepted elements, and obtains a calculation result of the square of the element. The addition and subtraction operation is determined by the condition. The computing device then outputs the calculation result. | 08-22-2013 |

20110153708 | COMMUNICATION DEVICE, RECEPTION DATA LENGTH DETERMINATION METHOD, MULTIPLE DETERMINATION CIRCUIT, AND RECORDING MEDIUM - A communication device includes a storage unit to store quotients and remainders associated with multiplication values obtained by multiplying a specified integer number, which is expressed in a form of (2 | 06-23-2011 |

708522000 | Systolic | 2 |

20090204658 | DECIMAL COMPUTING APPARATUS, ELECTRONIC DEVICE CONNECTABLE DECIMAL COMPUTING APPARATUS, ARITHMETIC OPERATION APPARATUS, ARITHMETIC OPERATION CONTROL APPARATUS, AND PROGRAM-RECORDED RECORDING MEDIUM - A decimal calculation apparatus, which performs multidigit decimal calculation with the number of calculation digits set in a calculation instruction, includes a multidigit memory section which stores values with greater numbers of digits than the number of digits of a predetermined digit unit in a plurality of memory areas, a calculation-instruction memory section which stores the calculation instruction having the number of calculation digits and a type of calculation set therein, and a decimal calculation section which performs decimal calculation of sequentially calculating numerical values of corresponding digit units respectively stored in the plurality of memory areas of the multidigit memory section, digit unit by digit unit in the number of calculation digits set in the calculation instruction stored in calculation-instruction memory section, in decimal calculation according to type of calculation set in the calculation instruction stored in calculation-instruction memory section, and sequentially writing calculation results in the plurality of memory areas of the multidigit memory section digit unit by digit unit. | 08-13-2009 |

20100250640 | SYSTOLIC ARRAY AND CALCULATION METHOD - A linear systolic array is added to the lower side of a trapezoid systolic array created by combining a triangular systolic array and a square systolic array. In order to make the connection among the cells fixed, the intermediate result output from each row of the trapezoid systolic array to a lower row is shifted in phase with respect to the intermediate result of the complex MFA algorithm, the phase shift is absorbed by the next row, and the phase shift in the intermediate result output from the last row of the trapezoid systolic array is corrected by the linear systolic array. Each cell is implemented by a CORDIC circuit that processes vector angle computation, vector rotation, division, and multiply-and-accumulate with a constant delay. | 09-30-2010 |

708525000 | Status condition/flag generation or use | 1 |

20100030834 | Performing A Binary Coded Decimal (BCD) Calculation - To perform a binary-coded decimal (BCD) calculation, a processor receives values on which the BCD calculation is to be performed. A carry resulting from the BCD calculation is stored in a flag register of the processor, and the carry stored in the flag register is used to compute a result of the BCD calculation. | 02-04-2010 |

708493000 | Multi-valued | 1 |

20090030962 | QUANTUM COMPUTING METHOD AND QUANTUM COMPUTER - An (N+1) number of physical systems each having five energy levels |0>, |1>, |2>, |3>, and |4>, a qubit being expressed by |0> and |1>, are provided in an optical cavity having a cavity mode resonant with |2>-|3>, such that an N number of control systems and a target system are prepared. The target system is irradiated with light pulses resonant with |0>-|4>, |1>-|4>, and |2>-|4> to change a superposed state |c> to |2>. All of the physical systems are irradiated with light pulses resonant with |0>-|3> and |1>-|3>, and a phase of the light pulse resonant with the target system is shifted by a specific value dependent on a unitary transformation U. The target system is irradiated with light pulses resonant with |0>-|4>, |1>-|4>, and |2>-|4>, with a phase difference between them being set to a specific value dependent on the unitary transformation U, to return |2> to |c>. | 01-29-2009 |

Entries | ||

Document | Title | Date |
---|---|---|

20100281092 | STANDARD CELL FOR ARITHMETIC LOGIC UNIT AND CHIP CARD CONTROLLER - A masked ALU cell for a certain bit position p is provided. The cell comprises a base unit operable to generate a masked inverted carry out bit co*_n and an inverted masked sum bit s*_n based on a first masked output a*, a second masked output b*, and a re-masked carry bit input ci*; a transformation unit coupled to the base unit, the transformation unit having a first masked input bit a | 11-04-2010 |

20080281896 | INDUSTRIAL CONTROLLER - A first arithmetic operator ( | 11-13-2008 |

20100191793 | Symbolic Computation Using Tree-Structured Mathematical Expressions - A method for performing symbolic computations on a mathematical expression. The mathematical expression may be converted to a tree structure having one or more parent nodes and one or more child nodes. Each parent node may be a mathematical operation. Each child node may be a mathematical expression on which the mathematical operation is performed in a specified order. Each child node may be in a hierarchical relationship to one of the parent nodes. The parent nodes, the child nodes or both may be manipulated to perform a first symbolic computation on the mathematical expression. | 07-29-2010 |

20120254275 | RELIABLE AND EFFICIENT COMPUTATION OF MODAL INTERVAL ARITHMETIC OPERATIONS - A computer executable method of performing a modal interval operation, and system for performing same is provided. The method includes providing representations of first and second modal interval operands. Each modal interval operand of the operands is delimited by first and second marks of a digital scale, each mark of the marks comprises a bit-pattern. Each bit-pattern of the bit-patterns of the marks of each of the modal interval operands are examined, and conditions of a set of status flags corresponding to each bit-pattern of the bit-patterns of the marks are set. A bit-mask is computed wherein the mask is based upon the set condition of the status flag sets and a presence/absence of an exceptional arithmetic condition, and a presence/absence of an indefinite operand are each represented by a bit of said bits of said bit mask. | 10-04-2012 |

20130091189 | Single datapath floating point implementation of RCP, SQRT, EXP and LOG functions and a low latency RCP based on the same techniques - Methods and apparatus is provided for computing mathematical functions comprising a single pipeline for performing a polynomial approximation (e.g. a quadratic polynomial approximation, or the like); and one or more data tables corresponding to at least one of the RCP, SQRT, EXP or LOG functions operable to be coupled to the single pipeline according to one or more opcodes; wherein the single pipeline is operable for computing at least one of RCP, SQRT, EXP or LOG functions according to the one or more opcodes. | 04-11-2013 |

20130144924 | METHOD AND APPARATUS FOR DISTRIBUTING OBJECTS - A method and apparatus for distributing objects. In one embodiment, the method comprises computing a modulus operand based on a number of objects to be distributed and a number of objects pertaining to a first category; computing a modulus operation based on a number of distributed objects and the modulus operand; and distributing a first object or a second object based on a result of computing the modulus operation. | 06-06-2013 |

20130159371 | Arithmetic Logic Unit Architecture - Embodiments of the present invention include an apparatus, method, and system for acoustic modeling. In an embodiment, an arithmetic logic unit for computing a one-dimensional score between a feature vector and a Gaussian probability distribution vector is provided. The arithmetic logic unit includes a computational logic unit configured to compute a first value based on a mean value and a variance value associated with a dimension of the Gaussian probability distribution vector and a dimension of a feature vector, a look up table module configured to output a second value based on the variance value, and a combination module configured to combine the first value and the second value to generate the one-dimensional score. | 06-20-2013 |