| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 708322000 | Adaptive | 23 |
| 20130036148 | SYSTEM AND METHOD FOR STATISTICALLY SEPARATING AND CHARACTERIZING NOISE WHICH IS ADDED TO A SIGNAL OF A MACHINE OR A SYSTEM - Methods for determining variance properties of a noise component of a raw signal of a machine or a system. An example method includes recording a signal using a noise estimation unit, numerically differentiating the signal using a first module of the noise estimation unit to obtain a differentiated signal, identifying, using a second module of the noise estimation unit, a histogram which corresponds to the differentiated signal, and determining using the histogram, a variance property of the noise component of the signal. | 02-07-2013 |
| 20090070397 | METHOD FOR ACTIVE NOISE REDUCTION AND AN APPARATUS FOR CARRYING OUT THE METHOD - In active noise reduction, at least one input signal ( | 03-12-2009 |
| 20090172060 | FILTER ADAPTIVE FREQUENCY RESOLUTION - In signal processing using digital filtering the representation of a filter is adapted depending on the filter characteristics. If e.g. a digital filter is represented by filter coefficients for transform bands Nos. 0, 1, . . . , K in the frequency domain, a reduced digital filter having coefficients for combined transform bands, i.e. subsets of the transformed bands, Nos. 0, 1, . . . , L, is formed and only these coefficients are stored. When the actual filtering in the digital filter is to be performed, an actual digital filter is obtained by expanding the coefficients of the reduced digital filter according to a mapping table and then used instead of the original digital filter. | 07-02-2009 |
| 20120078988 | MODIFIED GRAM-SCHMIDT CORE IMPLEMENTED IN A SINGLE FIELD PROGRAMMABLE GATE ARRAY ARCHITECTURE - A modified Gram-Schmidt QR decomposition core implemented in a single field programmable gate array (FPGA) comprises a converter configured to convert a complex fixed point input to a complex floating point input, dual port memory to hold complex entries of an input matrix, normalizer programmable logic module (PLM) to compute a normalization of a column vector. A second PLM performs complex, floating point multiplication on two input matrix columns. A scheduler diverts control of the QRD processing to the normalizer PLM or the second PLM. A top level state machine communicates with scheduler and monitors processing in normalizer PLM and second PLM and communicates the completion of operations to scheduler. A complex divider computes final column for output matrix Q using floating point arithmetic. Multiplexer outputs computed values as elements of output matrix Q or R. Complex floating point operations are performed in a parallel pipelined implementation reducing latencies. | 03-29-2012 |
| 20100262641 | Method and System for Estimating and Applying a Step Size Value for LMS Echo Cancellers - Disclosed is an improved method and apparatus for estimating and applying a step size value for a least mean squares echo canceller. A power estimate of an excitation signal is compared to a reference power level to determine a shift adjustment. The shift adjustment is added to a reference shift amount to determine a shift amount. The product of an excitation signal and an error signal is then calculated and the product is stored in a memory register comprising a plurality of bits. The bits stored in the memory register are shifted either left or right based upon the shift amount. The shift adjustment may be based in part upon the ratio of the excitation signal power estimate and the reference power level. | 10-14-2010 |
| 20100228810 | METHOD AND SYSTEM FOR UNCONSTRAINED FREQUENCY DOMAIN ADAPTIVE FILTERING - Aspects of a method and system for unconstrained frequency domain adaptive filtering include one or more circuits that are operable to select one or more time domain coefficients in a current filter partition. A value may be computed for each of the selected one or more time domain coefficients based on a corresponding plurality of frequency domain coefficients. The corresponding plurality of frequency domain coefficients may be adjusted based on the computed values. A subsequent plurality of frequency domain coefficients in a subsequent filter partition may be adjusted based on the computed values. Input signals may be processed in the current filter partition based on the adjusted corresponding plurality of frequency domain coefficients. A time-adjusted version of the input signals may be processed in a subsequent filter partition based on the adjusted subsequent plurality of frequency domain coefficients. | 09-09-2010 |
| 20100223311 | PARTICULAR SIGNAL CANCEL METHOD, PARTICULAR SIGNAL CANCEL DEVICE, ADAPTIVE FILTER COEFFICIENT UPDATE METHOD, ADAPTIVE FILTER COEFFICIENT UPDATE DEVICE, AND COMPUTER PROGRAM - By using the adaptive filter, the reference input signal is processed so as to identify a pseudo-signal of a particular signal to be deleted. The pseudo-signal is subtracted from the mixture containing a target signal inputted from a microphone, the particular signal to be deleted, and a noise so as to obtain an error signal. A stationary noise is estimated to obtain a stationary noise estimated value. A non-stationary noise is estimated to obtain a non-stationary noise estimated value. The stationary noise estimated value is mixed with the non-stationary estimated value to obtain a mixed noise estimated value. An update amount is calculated according to a correlation value between the error signal and the reference input signal, and the mixed noise estimated value. According to the update amount, a coefficient of the adaptive filter is updated. | 09-02-2010 |
| 20080222229 | DETERMINATION OF INCREMENTAL VALUE IN SERVER PROCESSED DATA - The accumulated change in values representative of actions taken by a processor, such as the number of email messages processed by an email server, in a given time period is determined. Actions are represented as data points on a plot. Look-ahead intervals are defined for each point. Candidate pairs of points are determined for each look-ahead interval by comparing the first value in the look-ahead interval with other values in the look-ahead interval. A candidate pair comprises the first point and another point having a lesser value. If a candidate pair has a value therebetween, the candidate pair is discarded. If, however, a candidate pair has no value therebetween, the first value of the candidate pair is a peak value for the look-ahead interval. The accumulated change is determined by calculating the sum of the peak values, plus the final value, minus the initial value, for the given time period. | 09-11-2008 |
| 20110264722 | SYSTEMS AND METHODS FOR AN ADJUSTABLE FILTER ENGINE - Systems and methods are provided for an adjustable filter engine. In particular, an electronic system is provided that can include a focus module, memory, and control circuitry. In some embodiments, the focus module can include an adjustable filter engine and a motor. By using the adjustable filter engine to generate a filter with a large number of filter coefficients, the control circuitry can accommodate a variety of system characteristics. For example, by generating a set of cumulative coefficients and re-arranging the order of the cumulative coefficients, the control circuitry can reduce the bit-width requirements of the adjustable filter engine hardware. For instance, the control circuitry can reduce the number of multipliers required to perform a convolution between an updated filter and one or more input signals. In some embodiments, the updated filter can be generated to reduce oscillations of the motor movement due to a new position request. | 10-27-2011 |
| 20120011183 | METHOD AND APPARATUS OF ADAPTIVELY CANCELING A FUNDAMENTAL FREQUENCY OF AN ANALOG SIGNAL - A system includes a first powered apparatus having a first analog signal with a fundamental frequency; and a second apparatus providing load diagnostics or power quality assessment of the first apparatus from a second digital signal. The second apparatus includes an input of the first analog signal, an output of the second digital signal, a processor, an adaptive filter executed by the processor, a digital-to-analog converter, and an analog-to-digital converter. The adaptive filter routine outputs a third digital signal as a function of the second digital signal and plural adaptive weights. The digital-to-analog converter inputs the third digital signal and outputs a fourth analog signal representative of an estimate of a fundamental frequency component of the first analog signal. The analog-to-digital converter inputs a difference between the first and fourth analog signals, and outputs the second digital signal representative of the first analog signal with the fundamental frequency component removed. | 01-12-2012 |
| 20120016921 | Method and Apparatus for Compressive Domain Filtering and Interference Cancellation - A method for compressive domain filtering and interference cancelation processes compressive measurements to eliminate or attenuate interference while preserving the information or geometry of the set of possible signals of interest. A signal processing apparatus assumes that the interfering signal lives in or near a known subspace that is partially or substantially orthogonal to the signal of interest, and then projects the compressive measurements into an orthogonal subspace and thus eliminate or attenuate the interference. This apparatus yields a modified set of measurements that can provide a stable embedding of the set of signals of interest, in which case it is guaranteed that the processed measurements retain sufficient information to enable the direct recovery of this signal of interest, or alternatively to enable the use of efficient compressive-domain algorithms for further processing. The method and apparatus operate directly on the compressive measurements to remove or attenuate unwanted signal components. | 01-19-2012 |
| 20120158810 | Systems and Methods for Reducing Filter Sensitivities - Various embodiments of the present invention provide systems and methods for reducing filter sensitivities. As an example, reduced sensitivity filter circuits are discussed that include a digital filter and a filter tap adaptation circuit. The digital filter is operable to filter a received input based at least in part on a plurality of filter taps, and to provide a filtered output. The filter tap adaptation circuit is operable to receive an error value and a weighting control value, and to adaptively calculate at least one of the filter taps using the error value and the weighting control value. | 06-21-2012 |
| 20120124118 | Systems and Methods for Variance Dependent Normalization for Branch Metric Calculation - Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes: a noise predictive filter circuit, a scaling factor adaptation circuit, and a scaling factor application circuit. The noise predictive filter circuit is operable to perform a noise predictive filtering process on a data input based on a filter tap to yield a noise filtered output. The scaling factor adaptation circuit is operable to calculate a scaling factor based at least in part on a derivative of the noise filtered output. The scaling factor application circuit is operable to apply the scaling factor to scale the noise filtered output. | 05-17-2012 |
| 20120131080 | Multi-Input IIR Filter with Error Feedback - Methods and systems for multi-input IIR filters with error feedback are disclosed. By using multiple-inputs to generate multiple outputs during each iteration, a multi-input IIR filter in accordance with the present invention has greatly increased throughput. Furthermore, the addition of a multi-variable error feedback unit in accordance with the present invention in a multiple-input IIR filter can greatly increase the accuracy of the multi-variable IIR Filter. | 05-24-2012 |
| 20100299381 | Algorithm for the Adaptive Infinite Impulse Response Filter - A new method to adjust the parameters of an adaptive Infinite Impulse Response (IIR) filter is suggested. The method adjusts the set of parameters of the pole polynomial of the filter. The parameters of the zero polynomial are calculated from the parameters of the pole polynomial. For efficiency, the pole polynomial is factored into a product of polynomials with at most quadratic order. To guarantee that the global minimum is achieved all the time, the algorithm ascertains that the new set of pole parameters gives smaller variance of the error than the set of pole parameters of the last adaptation time and the algorithm starts with the set of parameters that gives the global minimum. | 11-25-2010 |
| 20080301211 | SYSTEMS, METHODS AND APPARATUS FOR D-DIMENSIONAL FORMULATION AND IMPLEMENTATION OF RECURSIVE HIERARCHICAL SEGMENTATION - Systems, methods and apparatus are provided through which in some embodiments of recursive hierarchical segmentation of data with any number of spatial dimensions. Some embodiments of the recursive hierarchical segmentation include computationally efficient parallel implementations and other embodiments of the recursive hierarchical segmentation include computationally efficient serial implementations. | 12-04-2008 |
| 20120290633 | SPECTRUM AGILE RADIO - A spectrum agile radio having one or more variable digital filters is described. To quickly, yet accurately, retune the digital filter(s) a windowing function is applied to an ideal filter characteristic for each of one or more desired frequency bands to generate filter coefficients. Transitioning between coefficients of a previous filter and a current filter is handled to avoid problems associated with discontinuities in the signal processing. | 11-15-2012 |
| 20100198899 | METHOD AND DEVICE FOR LOW DELAY PROCESSING - Adaptive processing of an input signal is achieved by offline analysis, with inline processing comprising an adaptive filter. The method comprises passing the input signal through an adaptive time domain filter to produce an output signal. The input signal and/or output signal is used as an offline analysis signal. The analysis signal is transformed into a transform domain (eg frequency domain) to produce a transformed analysis signal. The transformed analysis signal is analyzed, for example by ADRO, to produce a plurality of desired gains each corresponding to a respective transform domain sub-band. A time domain filter characteristic is synthesized to at least approach the desired gains. The adaptive filter is updated with the synthesized filter characteristic. Minimum phase adaptive filter techniques are found to possess particular benefits in this scheme. | 08-05-2010 |
| 708323000 | Equalizer | 5 |
| 20090265406 | DECISION FEEDBACK EQUALIZER HAVING PARALLEL PROCESSING ARCHITECTURE - An integrated circuit includes a decision feedback equalizer (DFE) including a first and second digital equalizer logic including circuitry to compensate first and second bits in a received stream and to provide first and second sign bits. The second equalizer logic can run concurrently and can be connected in parallel relative to the first equalizer logic. The second equalizer logic can include a low and high sign bit pipelines providing first and second conditional sign bits by assuming a low and high sign bits, respectively, for a first bits being concurrently processed by the first equalizer logic and a sign bit selection element to select between the first and second conditional sign bits based on the sign bit outcome of the first equalizer logic. The first and second pipelines compensate bits using compensation weights chosen using most recent first and second conditional sign bits and sign bit outcome. | 10-22-2009 |
| 20120124119 | Systems and Methods for Self Tuning Target Adaptation - Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes an equalizer circuit, a noise predictive filter circuit, a data detector circuit, a data reconstruction circuit, and an adaptation circuit. The equalizer circuit is operable to receive a data input and to provide an equalized output based at least in part on an equalizer coefficient. The noise predictive filter circuit is operable to receive the equalized output and to provide a noise whitened output based at least in part on a noise predictive filter coefficient. The data detector circuit is operable to apply a data detection algorithm to the noise whitened output to yield a detected output. The data reconstruction circuit is operable to receive the detected output and to provide a reconstructed output corresponding to the equalized output based at least in part on a target polynomial. The adaptation circuit is operable to adaptively calculate the equalizer coefficient, the noise predictive filter coefficient and the target polynomial. | 05-17-2012 |
| 20120084336 | Systems and Methods for Retry Sync Mark Detection - Various embodiments of the present invention provide systems and methods for sync mark detection. As an example, a sync mark detection circuit is discussed that includes a storage circuit, a plurality of noise predictive filter circuits, and a controller circuit. The storage circuit is operable to store a data input as a stored input. The plurality of noise predictive filters are operable to receive a processing input. At least one of the noise predictive filters is selectably modifiable to either increase the probability of finding a sync mark in the processing input or to maintain a baseline probability of finding the sync mark in the processing input. The controller circuit is operable to determine an operational mode that may be a standard operational mode, a bit flipping mode, or a filter modification mode. | 04-05-2012 |
| 20120089657 | Systems and Methods for Partially Conditioned Noise Predictive Equalization - Various embodiments of the present invention provide systems and methods for equalization. As an example, a circuit for data equalization is described that includes a 2N state detector circuit that provides a series of detected bits based upon a conditioned input, and a noise predictive filter having a plurality of taps and operable to provide at least a portion of the conditioned input. At least a first of the plurality of taps uses a first subset of the series of detected bits, and a second of the plurality of taps uses a second subset of the series of detected bits. The first subset of the detected bits includes one more bit than the second subset of the detected bits. | 04-12-2012 |
| 20120102082 | RECEPTION APPARATUS, RECEPTION METHOD AND PROGRAM - Disclosed herein is a reception apparatus, including a first equalization section, a second equalization section, and an arithmetic operation section. The first equalization section is adapted to carry out equalization of a signal which represents data transmitted by a transmission method which uses a single carrier. The second equalization section is adapted to carry out equalization of a signal which represents data transmitted by a transmission method which uses multi carriers. The arithmetic operation section is adapted to carry out arithmetic operation for determining information to be used for the equalization by the first equalization section and arithmetic operation for determining information to be used for the equalization by the second equalization section. | 04-26-2012 |
