Class / Patent application number | Description | Number of patent applications / Date published |
708320000 | Recursive | 7 |
20090030961 | Microprocessor performing IIR filter operation with registers - A filter operation circuit of a microprocessor executes an IIR filter operation by using data provided from registers R | 01-29-2009 |
20090083354 | METHODS AND SYSTEMS FOR COMPRESSION, STORAGE, AND GENERATION OF DIGITAL FILTER COEFFICIENTS - A method and system for compressing coefficients of a digital filter is provided. In one approach, the method comprises providing a digital filter having a plurality of consecutive filter coefficients including a first filter coefficient, determining consecutive difference values between each of the consecutive filter coefficients, and storing the first filter coefficient and the consecutive difference values in a memory. The consecutive filter coefficients are generated by retrieving the first filter coefficient, and adding a first difference value to the first filter coefficient to generate a consecutive second filter coefficient. The first difference value corresponds to a difference between the first filter coefficient and the second filter coefficient. A consecutive next difference value is then added to the second filter coefficient to generate a consecutive next filter coefficient. The consecutive next difference value corresponds to a difference between the second filter coefficient and the consecutive next filter coefficient. | 03-26-2009 |
20090300089 | FINITE IMPULSE RESPONSE FILTER AND METHOD - An N-order finite impulse response (FIR) filter with a symmetric coefficient set is provided. An input device receives a serial of input signals according to a sampling frequency and stores the received data into the first and second memories by turns. A first calculating device reads the N successively received data from the first and second memories according to an operation frequency and generates a plurality of first calculation values, wherein each of the read data corresponds to a coefficient of the symmetric coefficient set and the first calculation value is generated by summing the read data corresponding to the same coefficient. A second calculating device generates a plurality of second calculation values, wherein the second calculation value is generated by multiplying the first calculation value and the corresponding coefficient. A third calculating device accumulates the second calculation values to generate an output signal. | 12-03-2009 |
20090300090 | APPARATUS AND METHOD FOR DETERMINING RESOLVER ANGLE - The invention concerns a method and apparatus ( | 12-03-2009 |
20100268752 | APPARATUS AND METHOD FOR ESTIMATING HIGH-INTEGRATION, HIGH-SPEED AND PIPELINED RECURSIVE LEAST SQUARES - Provided is an apparatus and method for estimating high-integration, high-speed and pipelined RLSs. Pipeline characteristics are given to an RLS algorithm to provide a high-speed HIP-RLS estimation apparatus. The HIP-RLS estimation apparatus has higher integration level than a conventional CORDIC-based RLS estimation apparatus. Thus, the use of the HIP-RLS estimation apparatus can reduce a chip size, thereby making it possible to fabricate more chips using the same wafer. Also, the HIP-RLS estimation apparatus is suitable for high-speed wireless communication because it has a high signal processing speed. | 10-21-2010 |
20100281090 | METHODS OR STRUCTURES FOR RECONSTRUCTION OF SUBSTANTIALLY UNIFORM SAMPLES FROM SUBSTANTIALLY NONUNIFORM SAMPLES - Briefly, embodiments of methods or structures for reconstruction of uniform digital signal sample values from nonuniform digital signal sample values are disclosed | 11-04-2010 |
20130318140 | Digital Filter - A digital filter for reducing a sampling rate for an input signal includes a parallelizing block for splitting the input signal into at least two parallel raw signals, an integration block for converting the parallel raw signals into an intermediate signal, and a differentiation block for generating an output signal by differentiating the intermediate signal. The integration block includes a logic block that is designed for generating two parallel sum signals from the parallel raw signals using summation operations, and a recursion block that is designed for generating the intermediate signal recursively from the parallel sum signals. | 11-28-2013 |