# Oscillator controlled

## Subclass of:

## 708 - Electrical computers: arithmetic processing and calculating

## 708100000 - ELECTRICAL DIGITAL CALCULATING COMPUTER

## 708200000 - Particular function performed

## 708250000 - Random number generation

### Patent class list (only not empty are listed)

#### Deeper subclasses:

Class / Patent application number | Description | Number of patent applications / Date published |
---|---|---|

708251000 | Oscillator controlled | 52 |

20150106415 | TRUE RANDOM NUMBER GENERATOR WITH REPEATEDLY ACTIVATED OSCILLATOR - A true random number generator (RNG) has one or more oscillators and an output register for storing a random number output. Each of the oscillators is activated, successively, in a free-running oscillation phase, and a capture phase during which the oscillator is quiescent. The output register latches during the capture phase of each oscillator an end state of that oscillator at or close to the end of its oscillation phase. The random number output is derived from the latched end states. | 04-16-2015 |

20120221616 | RANDOM NUMBER GENERATION CIRCUIT - According to one embodiment, a random number generation circuit includes an oscillation circuit and a holding circuit. The oscillation circuit has an amplifier array and a high-noise circuit. Amplifiers are connected in series in the amplifier array, and the amplifier array has a terminal between neighboring amplifiers. The high-noise circuit is inserted between other neighboring amplifiers in the amplifier array, and the high-noise circuit generates noise required to generate jitter in an oscillation signal from the amplifier array. The holding circuit outputs, as a random number, the oscillation signal held according to a clock signal. | 08-30-2012 |

20120265795 | SYSTEM AND METHOD FOR RANDOM NUMBER GENERATION USING ASYNCHRONOUS BOUNDARIES AND PHASE LOCKED LOOPS - Disclosed herein are systems, methods, and non-transitory computer-readable storage media for generating random data at an early stage in a boot process. A system practicing the method performs, by a processor based on a first clock, a group of reads of a counter running on a second clock to yield entropy words. In order to produce words with entropy, the system introduces a progressively increasing delay between each of the group of reads of the counter. The system generates entropy words by filling the buffer with successive reads of the least significant bit of the counter and then generates random data by applying a hash algorithm to the entropy words stored in the buffer. | 10-18-2012 |

20140250160 | RANDOM NUMBER GENERATOR - A random number generator includes a first oscillator configured to output a first oscillating signal having a first frequency. A second oscillator is configured to output a second oscillating signal having a second frequency different from the first frequency. A sampling unit is configured to receive the first and second oscillating signals. The sampling unit is configured to generate at least one entropy source by combining the received first and second oscillating signals. The sampling unit is configured to generate a random bit corresponding to the generated entropy source using a third oscillating signal. A third oscillator & control unit is configured to control the first and second oscillators and to generate the third oscillating signal. A frequency of the third oscillating signal is lower than the first and second frequencies. | 09-04-2014 |

20100106757 | Active Test and Alteration of Sample Times For a Ring Based Random Number Generator - An apparatus includes: a plurality of bit producing circuits; a controller setting a sample frequency at which bits from the bit producing circuits are sampled; and a plurality of test circuits determining if bits sampled from each of the bit producing circuits are random, wherein the controller adjusts the sample frequency if the test circuits determine that the sampled bits are not random. A method performed by the apparatus is also included. | 04-29-2010 |

20090248771 | TRUE RANDOM NUMBER GENERATOR - True random number generation circuitry utilizes a pair of oscillators driving a pair of linear feedback shift registers, with their output being combined to generate random numbers. At least one of the oscillators is programmable with a variable frequency. One embodiment controls the variable frequency of oscillators with output from one or more sets of oscillators and linear feedback shift registers. In other embodiments, linear feedback shift register output is captured and used to control the frequency of oscillators. | 10-01-2009 |

20130346459 | METHOD FOR GENERATING RANDOM NUMBERS - A method and an assemblage for generating random numbers. In the method, at a ring oscillator that comprises an odd number of inverting elements, values are picked off at at least two sampling points, an odd number of inverting elements being present in each case between at least two directly successive sampling points. | 12-26-2013 |

20130346458 | METHOD FOR MONITORING THE OUTPUT OF A RANDOM GENERATOR - An assemblage for monitoring an output of a random generator is provided, which assemblage compares chronologically successive sample values at a sampling point with one another in order to detect a relationship of the compared sample values with one another. | 12-26-2013 |

20140351305 | System And Method For Dynamic Tuning Feedback Control For Random Number Generator - A random number generator includes a first circuit producing a random sequence of values, the first circuit having an adjustable input that changes the entropy of the random sequence of numbers; a second circuit receiving the random sequence of values from the first circuit and producing an output indicative of the degree of entropy of the random sequence of values, and a third circuit that adjusts the adjustable input of the first circuit in response to the output of the second circuit. | 11-27-2014 |

20140351304 | RANDOM NUMBER GENERATING DEVICE - A random number generating device is provided. The random number generating device includes a first frequency generating circuit, a second frequency generating circuit and a flip-flop. The first frequency generating circuit generates a first frequency signal according to a signal inputted via an input end, and outputs the first frequency signal via an output end. The second frequency generation circuit generates and outputs a clock signal. The flip-flop includes a data input end, a clock input end and a data output end. The data input end and the clock input end are electrically connected to the first frequency generating circuit and the second frequency generating circuit respectively. The flip-flop outputs a random signal via the data output end according to the first frequency signal and the clock signal, and feedbacks the random signal to the first frequency generating circuit to change frequency of the first frequency signal. | 11-27-2014 |

20100332574 | Digital random number generator - A hardware-based digital random number generator is provided. The digital random number generator is a randomly behaving random number generator based on a set of nondeterministic behaviors. The nondeterministic behaviors include temporal asynchrony between subunits, entropy source “extra” bits, entropy measurement, autonomous deterministic random bit generator reseeding and consumption from a shared resource. | 12-30-2010 |

20110302232 | APPARATUS FOR GENERATING RANDOM NUMBER - An apparatus for generating a random number has high entropy. The apparatus includes a plurality of random number generators, each of which generates a metastability signal and generates a random number by using the generated metastability signal in a first mode, and in a second mode, the plurality of random number generators are connected to one another to operate as a ring oscillator. | 12-08-2011 |

20080313249 | RANDOM NUMBER GENERATOR WITH RING OSCILLATION CIRCUIT - A random number generator includes a ring oscillator having an EX-OR gate and four inverters together forming a loop. This loop enters stable state for a start signal having the low level and oscillates for the start signal having the high level. When the start signal has a pulse of a width shorter than the loop's delay time, output nodes responsively, sequentially enter metastable state hovering between the high and low levels. The metastable waveform becomes smaller with time and finally disappears. As metastable state cannot be controlled in longevity, it disappears at any random number node. A counter thus outputs a signal serving as true random number data depending on the longevity of the metastable state. A random number generator miniaturized and having reduced power consumption, and of high performance can thus be implemented. | 12-18-2008 |

20110066669 | PHYSICAL RANDOM NUMBER GENERATION DEVICE - A physical random number generation device includes a physical random number generation source which generates a white noise, an AD conversion module which inputs the white noise for conversion to a physical prime random number as digital data, a physical prime random number sequence generation module which inputs two or more physical prime random numbers to generate a physical prime random number sequence, a white noise array generation module for inputting the physical prime random number sequence and for generating a white noise array, a white noise composition module for generating multiple physical random numbers from the input white noise array, and an interface for externally outputting the generated physical random numbers as physical random number data. With this arrangement, multiple physical random numbers are generated at high speeds from the physical prime random number(s) taken out of the physical random number generation source as digital data. | 03-17-2011 |

20090177725 | RANDOM NUMBER GENERATION DEVICE - It is made possible to provide a random number generation device which generates a physical random number with as little power dissipation as possible. A random number generation device includes: a ring oscillator having at least one set, each set comprising a current noise source and a Schmitt inverter configured to receive an output of the current noise source; and a conversion circuit configured to convert output frequency fluctuation of the ring oscillator to a random number and output the random number. | 07-09-2009 |

20090157782 | RANDOM NUMBER GENERATOR AND RANDOM NUMBER GENERATING METHOD THEREOF - A random number generator and a random number generating method thereof are provided. The random number generator includes a signal generating unit and a sampling unit. The signal generating unit is adapted for memorizing a status of a noise generated during a transient of an output signal of an output buffer, and accordingly generating a frequency conversion signal which changes according to time and ambient factors. The sampling unit is coupled to the signal generating unit for receiving the frequency conversion signal, and sampling the frequency conversion signal according to a sampling clock pulse, so as to obtain a plurality of sets of unpredictable random number codes. | 06-18-2009 |

20100146025 | METHOD AND HARDWARE FOR GENERATING RANDOM NUMBERS USING DUAL OSCILLATOR ARCHITECTURE AND CONTINUOUS-TIME CHAOS - Novel random number generation methods and novel random number generators based on continuous-time chaotic oscillators with dual oscillator architecture are presented. Numerical and experimental results not only verify the feasibility of the proposed circuits, but also encourage their use as a high-performance IC TRNG. In comparison with RNG's based on discrete-time chaotic maps, amplification of a noise source and jittered oscillator sampling, which are advantageous in the sense that true random behavior can be mathematically proven thanks to an analytical model that has been developed, it is seen that RNG's based on continuous-time' chaotic oscillators can offer much higher and constant data rated without post-processing. The proposed innovation increases the throughput, maximizes the statistical quality of the output sequence and is robust against against external interference, parameter variations and attacks aimed to force throughout. The proposed circuits can be integrated on today process at GHz range. | 06-10-2010 |

20100005129 | METHOD AND APPARATUS FOR GENERATING A RANDOM BIT STREAM - Presently disclosed is method and apparatus for generating a random bit stream by generating a random bit according to a polynomial expression, providing a modification function operative on the polynomial expression, and modifying the polynomial expression by modifying the modification function. | 01-07-2010 |

20100005128 | RANDOM NUMBERS GENERATION USING CONTINUOUS-TIME CHAOS - Novel random number generation methods and random number generators (RNG)s based on continuous-time chaotic oscillators are presented. Offset and frequency compensation loops are added to maximize the statistical quality of the output sequence and to be robust against parameter variations and attacks. We have verified both numerically and experimentally that, when the one-dimensional section was divided into regions according to distribution, the generated bit streams passed the tests used in both the FIPS-140-2 and the NIST 800-22 statistical test suites without post processing. Numerical and experimental results presented in this innovation not only verify the feasibility of the proposed circuits, but also encourage their use as the core of a high-performance IC RNG as well. In comparison with RNGs based on discrete-time chaotic maps, amplification of a noise source and jittered oscillator sampling, it is seen that RNGs based on continuous-time chaotic oscillators can offer much higher and constant data rates without post-processing. In conclusion, we can deduce that the proposed circuits can be realized in integrated circuits and the use of continuous-time chaos with the proposed innovations is very promising in generating random numbers with very high throughput. | 01-07-2010 |

20080270501 | Seed generating circuit, random number generating circuit, semiconductor integrated circuit, IC card, and information terminal equipment - A random number generating circuit comprises: the seed generating circuit which generates a seed; and a pseudo random number circuit which generates pseudo random numbers based on the seed generated by the seed generating circuit. The seed generating circuit has: an oscillating circuit which oscillates continuously or intermittently, and which outputs a digital data sequence; a smoothing circuit which outputs time series data by controlling appearance frequencies of “0” and “1” in the digital data sequence outputted from the oscillating circuit; and a postprocessing circuit which generates one-bit seed by a computation using a plurality of bits included in the time series data. | 10-30-2008 |

20090077147 | Multi-Bit Sampling Of Oscillator Jitter For Random Number Generation - An apparatus includes an oscillator, a counter for counting pulses, and a latch for latching a count from the counter in response to changes in a logic level of an output of the oscillator. The apparatus can further include an edge detector for producing a latching signal in response to changes in the logic level of the output of the oscillator. | 03-19-2009 |

20100211624 | DEVICE AND METHOD FOR GENERATING A RANDOM BIT SEQUENCE - A device generates a random bit sequence with a digital ring oscillator circuit comprising logic components. The circuit has an input node and an output node, wherein the digital ring oscillator circuit is designed such that oscillation occurs during a change of state of a logic start signal coupled on the input node, said oscillation having a fixed point, and wherein on the output node a random signal can be tapped having an arbitrary level curve. | 08-19-2010 |

20090327380 | Circuit and method of generating a random number using a phass-locked-loop circuit - A circuit that generates a random number includes a phase-locked loop circuit and a sampling circuit. The phase-locked loop circuit generates an internal clock signal that is synchronized with a reference signal in which the internal clock has a random noise. The sampling circuit samples the reference signal in response to the internal clock signal to generate a random data bit. The circuit of generating a random number is capable of generating a random number with high randomness and is capable of operating at a relatively low frequency. | 12-31-2009 |

20140280413 | METHOD FOR DETECTING A CORRELATION - A method for detecting a correlation of a first ring oscillator with a second ring oscillator and a system for carrying out the method are provided. In the method, combinations of concatenations are compared to chronologically preceding concatenations. | 09-18-2014 |

20110040817 | CIRCUIT AND METHOD FOR GENERATING A TRUE, CIRCUIT-SPECIFIC AND TIME-INVARIANT RANDOM NUMBER - The invention relates to a circuit for generating a true, circuit-specific and time-invariant random binary number, having: a matrix of K−L delay elements that can be connected to each other by means of L−1 single or double commutation circuits into chains of delay elements of length L, a single or double demultiplexer connected before the matrix, a single or double multiplexer connection after the matrix, and a run time or number comparator, wherein the setting of the commutation circuits, the demultiplexer, and the multiplexer can be prescribed by a control signal, wherein the circuit comprises a channel code encoder whereby code words of a channel code can be generated and a transcriber, whereby code words of the channel code can be transcribed into the control signal of the L−1 single or double commutation circuits, and a method for generating a true, circuit-specific and time-invariant random number by means of a matrix of L−K delay elements, L−1 single or double commutation circuits, a single or double demultiplexer connected before the matrix, a single or double multiplexer connection after the matrix, and a run time or number comparator, comprising at least the steps a) generating a code word of a channel code, b) transcribing a code word of a channel code to a selection code, c) generating chains of L delay elements by setting a setting corresponding to the code word of the selection code for the L−1 single or double commutation circuits, the single or double demultiplexer, and the single or double multiplexer, d) pairwise comparing of two variables determined by the delay times of two chains defined by the setting of the L−1 commutation circuits corresponding to the code word of the channel code, by means of a number or delay comparator for generating a bit of the true, circuit-specific and time-invariant random number. | 02-17-2011 |

20100036899 | BIT GENERATOR - A system comprising a feedback shift-register having L serially connected stages, and a non-linear feedback sub-system to receive input from stage n and 2n+1, and including a first AND gate having a first and second input operationally connected to the output of stage n and 2n+1, respectively, the sub-system having an output based on a value of an output of the first AND gate, a bit generator operative to generate bits, and an XOR gate having a first and second input, an output of the bit generator being operationally connected to the first input of the XOR gate, the output of the sub-system being operationally connected to the second input of the XOR gate, the output of the XOR gate being operationally connected to the input of the first stage of the shift-register. Related apparatus and methods are also described. | 02-11-2010 |

20090222502 | RANDOM NUMBER GENERATOR - A random number generator includes: a variable frequency oscillator that includes: a selection circuit having multiple input terminals and an output terminal; a parallel circuit having an input terminal and multiple output terminals that are respectively connected to the input terminals of the selection circuit, the parallel circuit including one or more buffer circuits to be selected by the selection circuit; and an inverter circuit having a control terminal, the inverter circuit being connected to the input terminal of the parallel circuit and to the output terminal of the selection circuit; and a latch circuit connected to the variable frequency oscillator. | 09-03-2009 |

20080256153 | RANDOM NUMBER SIGNAL GENERATOR USING PULSE OSCILLATOR - A random number signal generator using pulse oscillators, the generator including: a first pulse oscillator oscillating a first pulse at high speed; a second pulse oscillator oscillating a second pulse; a sampler receiving an output pulse of the first oscillator as data, receiving an output pulse of the second pulse oscillator as a clock signal, and outputting a plurality of output signals; and a digital processor generating a random number signal with a desired size by using the output signals of the sampler. | 10-16-2008 |

20110131263 | Random Number Generators Having Metastable Seed Signal Generators Therein - A random number generator includes a signal generator and a sampling unit. The signal generator is configured to generate an alternating sequence of metastable seed signals and oscillating signals during respective first and second half-periods of a clock signal. The oscillating signals having respective phases determined by corresponding ones of the metastable seed signals in the alternating sequence. The sampling unit is configured to detect a logic value of each consecutive oscillating signal during a portion of a respective half-period of the clock signal. The signal generator may be responsive to the clock signal and the sampling unit may be responsive to a delayed version of the clock signal. | 06-02-2011 |

20090172055 | Random Number Generator - The invention concerns a random number generator comprising a n-bit LSFR at least one oscillator having at least one delay element introducing a variable delay in the counter feedback loop, and at least one sampling/holding device having at least one input coupled to an output of the oscillator, and at least one output coupled to a input of the LSFR, and a clock input receiving a sampling clock signal at a much lower frequency than the oscillator frequency. Said generator is for example configured to vary the delay introduced by the oscillator delay based on a number q of feedback bits among the n bits of the LSFR output, where q is a an integer such that 1≦q≦n. | 07-02-2009 |

20090106338 | Pseudorandom Number Generation - A system and method of for obtaining a pseudorandom number generator are disclosed. A set of state modules, each with a limit value, may be provided. In an embodiment, each of the limit values may be relatively prime to the other limit values. In response to one or more events, the values of the state modules are incremented. At some frequency that may be statistically independent from the occurrence of the one or more events, the values of the state modules are obtained and combined to form a random number. The values may be combined as desired and, if desired, may be combined modulo 2 | 04-23-2009 |

20090106339 | Random number generator - Provided is a random number generator including: a clock generator outputting first and second control signals; a ring oscillator (RO) block receiving a meta stable voltage and performing an oscillation operation using the meta stable voltage in response to the first control signal; and a sampling unit sampling an output signal according to the oscillation operation in response to the second control signal. | 04-23-2009 |

20120233233 | APPARATUS AND METHOD FOR GENERATING A RANDOM NUMBER - An apparatus and method for generating a random number are provided, the apparatus having at least one generator circuit, each generator circuit being configured to provide a first operating mode and a second operating mode, in the first operating mode each generator circuit operating as an oscillator, and in the second operating mode each generator circuit operating as a state retention element. A control signal generator then generates a control signal for input to each generator circuit. Each generator circuit is responsive to the input control signal being at a set level to operate in the first operating mode, and is responsive to the input control signal being at a clear level to operate in the second operating mode. On a transition of the input control signal from the set level to the clear level, each generator circuit is configured to capture within the state retention element a current value of the oscillator, and to output that current value to form at least part of the random number. Such an approach provides a particularly simple, efficient and low area apparatus for generating a random number. | 09-13-2012 |

20120233232 | Variable Architecture for Random Number Generators - A variable architecture for random number generators is disclosed. In some implementations, the architecture of a random number generator may be varied based on microcontroller-specific data stored on the microcontroller. For example, a random number generator module may be embedded in a microcontroller circuit. The random number generator module may be designed to receive input from data sources in the circuit that contain microcontroller-specific data (e.g., a unique chip identifier, data carried in fuse bits). In some implementations, the architecture of the random number generator module may be adjusted or varied based on the microcontroller-specific data. | 09-13-2012 |

20120278372 | Cryptographic Random Number Generator Using Finite Field Operations - An apparatus and method are provided in various illustrative embodiments for an integrated circuit chip that provides a fast, compact, and cryptographically strong random number generator. In one illustrative embodiment, an apparatus includes an initial random source, and a post-processing block in communicative connection with the initial random source. The post-processing block is configured to receive signals from the initial random source, to apply one or more finite field operations to the signals to generate an output, and to provide an output signal based on the output via an output channel, in this illustrative embodiment. | 11-01-2012 |

20090077146 | On-Line Randomness Test For Restart Random Number Generators - An apparatus includes a first counter for counting successive bits representative of a logic 1, and a second counter for counting successive bits representative of a logic 0, wherein a first predetermined count on the first counter or a second predetermined count on the second counter indicates a randomness failure. A method for testing randomness performed by the apparatus is also included. | 03-19-2009 |

20080320066 | Cryptographic random number generator using finite field operations - An apparatus and method are provided in various illustrative embodiments for an integrated circuit chip that provides a fast, compact, and cryptographically strong random number generator. In one illustrative embodiment, an apparatus includes an initial random source, and a post-processing block in communicative connection with the initial random source. The post-processing block is configured to receive signals from the initial random source, to apply one or more finite field operations to the signals to generate an output, and to provide an output signal based on the output via an output channel, in this illustrative embodiment. | 12-25-2008 |

20130013657 | RANDOM NUMBER GENERATOR - A system is described for generating random numbers. The system may include a plurality of information sources and one or more sampling devices coupled to each of the information sources. Each information source may have a characteristic which may differ from the characteristic of any other information source. The sampling devices may sample the information sources at some sampling interval. A sample value may be captured from each of the information sources by the sampling devices coupled thereto at the sampling interval. An output representative of a substantially random number may be derived from the sample values captured at the sampling interval. | 01-10-2013 |

20080243978 | RANDOM NUMBER GENERATOR - A random number generator includes an amplifier to amplify a difference between a noise signal and a reference signal to generate an amplified signal, a plurality of binarization circuits configured to binarize the amplified signal by using different inherent threshold values to obtain a plurality of binarized signals, and an exclusive OR circuit to perform an exclusive OR operation on the a plurality of binarized signals to generate random number sequence. | 10-02-2008 |

20100281088 | Integrated true random number generator - A true random number generator (TRNG) in an integrated circuit comprises a plurality of independent ring oscillators with multiple output taps combined into enhanced outputs, a plurality of delay lines, a combiner-sampler and a source of a clock signal. Some embodiments provide a TRNG that is resettable, allowing one or more independent random numbers to be generated in response to a trigger signal. | 11-04-2010 |

20150074157 | RANDOM NUMBER GENERATOR USING AN INCREMENTING FUNCTION - A random number generator uses a looped circuit that produces pulses dependent on manufacturing variations and noise, and fed into a counting circuit. In certain embodiments, the technology can be merged with a Physical Unclonable Function (PUF) such that a single circuit provides both 1) bits that are unique to each chip that remain fairly similar each time they are queried on the same chip; as well as 2) bits that are random, i.e., different each time the randomness is queried, even on the same device. | 03-12-2015 |

20150088950 | STORING AN ENTROPY SIGNAL FROM A SELF-TIMED LOGIC BIT STREAM GENERATOR IN AN ENTROPY STORAGE RING - A Self-Timed Logic Entropy Bit Stream Generator (STLEBSG) outputs a bit stream having non-deterministic entropy. The bit stream is supplied onto an input of a signal storage ring so that entropy of the bit stream is then stored in the ring as the bit stream circulates in the ring. Depending on the configuration of the ring, the bit stream as it circulates undergoes permutations, but the signal storage ring nonetheless stores the entropy of the injected bit stream. In one example, the STLEBSG is disabled and the bit stream is no longer supplied to the ring, but the ring continues to circulate and stores entropy of the original bit stream. With the STLEBSG disabled, a signal output from the ring is used to generate one or more random numbers. | 03-26-2015 |

20150088949 | SELF-TIMED LOGIC BIT STREAM GENERATOR WITH COMMAND TO RUN FOR A NUMBER OF STATE TRANSITIONS - A bit stream having non-deterministic entropy is generated by a Self-Timed Logic Entropy Bit Stream Generator (STLEBSG). The STLEBSG includes an incrementer and a linear feedback shift register (LFSR), both implemented in self-timed logic as parts of an asynchronous state machine. In response to a command, the incrementer asynchronously increments a number of times and then stops, where the number of times is determined by command. For each increment of the incrementer, the LFSR undergoes a state transition. As the incrementer increments, the LFSR outputs the bit stream. If the command is a run repeatedly command, then after the incrementer stops the incrementer is reinitialized and then again increments the number of times. This incrementing, stopping, reinitializing, and incrementing process is repeated indefinitely. Another command causes the incrementer to be loaded. Another command causes the LFSR to be loaded. | 03-26-2015 |

20150019606 | Method for evaluating an output of a random generator - A method and an assemblage for checking an output of a random generator are presented. In the method, signatures that are respectively created from a sequence of sampled values are compared with one another. | 01-15-2015 |

20130024490 | RANDOM NUMBER GENERATOR - A device includes a plurality of linear feedback shift registers, a counter having a counter value of a bit length, and a comparator to compare the counter value and an update value including bit values of bit positions of a first linear feedback shift register. The number of bit positions equal to the bit length of the counter value. A second linear feedback shift register to update based on the comparison. | 01-24-2013 |

20120303690 | RANDOM NUMBER GENERATOR WITH RING OSCILLATION CIRCUIT - A random number generator includes a ring oscillator having an EX-OR gate and four inverters together forming a loop. This loop enters stable state for a start signal having the low level and oscillates for the start signal having the high level. When the start signal has a pulse of a width shorter than the loop's delay time, output nodes responsively, sequentially enter metastable state hovering between the high and low levels. The metastable waveform becomes smaller with time and finally disappears. As metastable state cannot be controlled in longevity, it disappears at any random number node. A counter thus outputs a signal serving as true random number data depending on the longevity of the metastable state. A random number generator miniaturized and having reduced power consumption, and of high performance can thus be implemented. | 11-29-2012 |

20140143292 | RANDOM NUMBER GENERATING CIRCUIT - According to one embodiment, a random number generating circuit includes first to N-th oscillating circuits (N is a natural number equal to 2 or greater), first to N-th latch circuits that latch outputs of the first to N-th oscillating circuits by a first clock having a first frequency, first to N-th exclusive OR circuits, (N+1)-th to (2×N)-th latch circuits that latch outputs of the first to N-th exclusive OR circuits by the first clock, an (N+1)-th exclusive OR circuit that outputs an exclusive OR of outputs of the (N+1)-th to (2×N)-th latch circuits, and an M-bit shift register that converts serial data output from the (N+1)-th exclusive OR circuit into M-bit parallel data (M is a natural number equal to 2 or greater) by a second clock having a second frequency. | 05-22-2014 |

20130212140 | RANDOM NUMBER GENERATION USING STARTUP VARIANCES - Random numbers are generated according to a variety of solutions. A particular solution relates to method for generating the random number. A common start signal is provided to each of a plurality of inverter components of a ring oscillator circuit. This causes the ring oscillator circuit to enter a metastable mode. At least a first bit and a second bit of a random number are both generated in parallel. The parallel generation of the bits involves the generation of the first bit from entropic properties of a signal of a first one of the plurality of inverter components and the generation of the second bit from entropic properties of a signal of a second one inverter components. | 08-15-2013 |

20130124591 | RANDOM NUMBER GENERATION USING SWITCHING REGULATORS - Random numbers are generated using entropic properties associated with circuit hardware. Consistent with one method, a switching voltage regulator circuit is used to generate a random number. Data that is responsive to switching states of the switching voltage regulator circuit is generated. A multi-bit random number is then generated from the generated data. | 05-16-2013 |

20130191428 | RANDOM NUMBER GENERATING DEVICE - A random number generating device includes: a microcomputer; a first oscillator circuit that has a predetermined temperature characteristic and generates a clock serving as a basis of a behavior of the microcomputer; and an electronic circuit that has a temperature characteristic being different from the predetermined temperature characteristic of the first oscillator circuit and operates in accordance with a command from the microcomputer. The microcomputer measures an operating time of the electronic circuit based upon the clock generated by the first oscillator circuit and generates a random number based upon a result of the measurement. | 07-25-2013 |

20130318139 | RANDOM NUMBER GENERATION METHOD AND APPARATUS USING LOW-POWER MICROPROCESSOR - A random number generation method and apparatus using a low-power microprocessor is provided. In the random number generation method, a low-power microprocessor determines whether external power is supplied to a random number generator. The low-power microprocessor updates an internal state of the random number generator based on a first scheme if it is determined that the external power is supplied to the random number generator. The low-power microprocessor updates the internal state of the random number generator based on a second scheme different from the first scheme if it is determined that the external power is not supplied to the random number generator. | 11-28-2013 |

20140244702 | RANDOM NUMBER GENERATOR - A random number generator includes oscillating units configured to generate entropy sources and amplify the generated entropy sources, an entropy source combination unit configured to receive the entropy sources output from the oscillating units and combine the entropy sources to increase entropy, a sampling unit configured to sample a signal output from the entropy source combination unit in response to a sampling clock, and a clock generator and control unit configured to control the oscillating units and generate the sampling clock. | 08-28-2014 |