Class / Patent application number | Description | Number of patent applications / Date published |
708210000 | Determining number of like-valued bits in word | 9 |
20090019100 | POPULATION COUNT APPROXIMATION CIRCUIT AND METHOD THEREOF - A circuit and method provides an estimate of a population count (popcount) of a plurality of input bit values. In one form the input bit values represent respective nodes of an integrated circuit. An approximation circuit uses an approximation input stage which receives a plurality of data inputs and has a plurality of logic circuits. Each logic circuit provides a single bit output. The approximation circuit provides monotonic accuracy. A reduction tree receives the single bit outputs of the plurality of logic circuits and provides an approximate count of how many of the plurality of data inputs are asserted. Size and speed are improved by providing the estimate as opposed to an exact value. | 01-15-2009 |
20090055454 | Half Width Counting Leading Zero Circuit - A circuit and method are provided for storing a data word in a latch and determining the number of consecutive equal value bits within the data word. The data word consists of bits stored in unique bit positions and having a least significant bit position and a most significant bit position. The data word is examined to determine the number of consecutive bits having the same numeric value. The invention first corrects for any single bit anomaly within the consecutive equal value sequence, counts the number of consecutive bits having this equal value using logic that examines only every other bit position of the stored data word and provides a numeric value representing this number of consecutive equal value bits. | 02-26-2009 |
20090106336 | Digital Signal Processing Apparatus - Register includes flip-flop circuits each constructed to retain data of n bit in synchronism with a clock pulse, the register retaining a multiplication result of a multiplier dividedly by the flip-flop circuits, n bit per flip-flop circuit. For each of a first and second numeric value data to be multiplied by the multiplier, a control circuit detects the number of consecutive zeros from the lowest-order bit of the data and performs control, on the basis of the detected number of the consecutive zeros and for each flip-flop circuit, as to whether or not the clock pulse should be supplied to the flip-flop circuit. The control circuit obtains an integral quotient value x by dividing by the number n the sum between the detected numbers for the first and second numeric value data, to stop the clock pulse supply to a particular number x of flip-flop circuit counted from the lowest-order. | 04-23-2009 |
20090259704 | Generating a Number based on Mask and Range Constraints - Generating a number based on mask and range constraints. For example, a method of generating a pseudo random number satisfying a range constraint and a mask constraint may include determining a number of possible solutions satisfying the range constraint and the mask constraint; selecting an index representing a solution of the possible solutions; and generating the pseudo random number based on the index. Other embodiments are described and claimed. | 10-15-2009 |
20100082718 | COMBINED SET BIT COUNT AND DETECTOR LOGIC - A merged datapath for PopCount and BitScan is described. A hardware circuit includes a compressor tree utilized for a PopCount function, which is reused by a BitScan function (e.g., bit scan forward (BSF) or bit scan reverse (BSR)). Selector logic enables the compressor tree to operate on an input word for the PopCount or BitScan operation, based on a microprocessor instruction. The input word is encoded if a BitScan operation is selected. The compressor tree receives the input word, operates on the bits as though all bits have same level of significance (e.g., for an N-bit input word, the input word is treated as N one-bit inputs). The result of the compressor tree circuit is a binary value representing a number related to the operation performed (the number of set bits for PopCount, or the bit position of the first set bit encountered by scanning the input word). | 04-01-2010 |
20110238717 | Linear Bit Counting Implementations - Counting the number of set and unset bits in an n-bit data word or stream of data is most efficient in applications where the data can be characterized as sparsely populated (bits mostly or all unset/0) and/or heavily populated (bits mostly or all set/1). In these populations, processing can be linearly proportional to the smaller number of differing bit values resulting in compute time and resource savings. In any population, the operations of the bit counting methods, systems, apparata and computer program products described are bounded by the number of bits counted in the data word/stream. The described operations can be used for determining whether further processing of the data stream is required as well as the extent of that processing. | 09-29-2011 |
20110289128 | Method of performing discrete cosine transform - The present invention provides method and apparatus of a fast DCT implementation. DCT calculation is combined with quantization scales by a procedure of pre-processing. During DCT coefficient calculation, only non-zero coefficients are calculated. If pixel variance range is smaller than a first predetermined threshold, a predetermined lookup table is compared to decide the DCT coefficients. When a pixel variance range of a block pixels is within the second threshold, coupled with the quantization scales, the pre-processing determines the amount of non-zero DCT coefficients need to be calculated. Only a limited amount of LSB bits within a block is applied in the calculation of DCT coefficients. A previously saved pixel with equal or closest pixel value is used to replace the operation of current pixel's multiplication. | 11-24-2011 |
20140019501 | IDENTIFIER SELECTION - A data processing apparatus is provided which is configured to select 2 | 01-16-2014 |
20150032786 | IDENTIFICATION OF THE BIT POSITION OF A SELECTED INSTANCE OF A PARTICULAR BIT VALUE IN A BINARY BIT STRING - A circuit for identifying one or more bit positions of instances of a selected bit value in an N-bit input bit string includes a plurality of adders that compute, in parallel, sums of bits in each of P input substrings comprising the input bit string. A plurality of zero position detectors detect, for each of the P input substrings for which a corresponding sum differs from a threshold sum, one or more bit positions of the selected bit value. Correction logic generates adjustment indications indicative of a number of detected instances of the selected bit value. A plurality of output substring adjusters that, based on the detected bit positions and the adjustment indications, collectively output one or more output vectors identifying a bit position of at least an Mth instance of the selected bit value in the input bit string. | 01-29-2015 |