Entries |
Document | Title | Date |
20080270495 | INSERT/EXTRACT BIASED EXPONENT OF DECIMAL FLOATING POINT DATA - A decimal floating point finite number in a decimal floating point format is composed from the number in a different format. A decimal floating point format includes fields to hold information relating to the sign, exponent and significand of the decimal floating point finite number. Other decimal floating point data, including infinities and NaNs (not a number), are also composed. Decimal floating point data are also decomposed from the decimal floating point format to a different format. For composition and decomposition, one or more instructions may be employed, including an insert biased exponent or extract biased exponent instruction. | 10-30-2008 |
20080270496 | COMPOSITION/DECOMPOSITION OF DECIMAL FLOATING POINT DATA - A decimal floating point finite number in a decimal floating point format is composed from the number in a different format. A decimal floating point format includes fields to hold information relating to the sign, exponent and significand of the decimal floating point finite number. Other decimal floating point data, including infinities and NaNs (not a number), are also composed. Decimal floating point data are also decomposed from the decimal floating point format to a different format. | 10-30-2008 |
20080270497 | CONVERT SIGNIFICAND OF DECIMAL FLOATING POINT DATA TO/FROM PACKED DECIMAL FORMAT - A decimal floating point finite number in a decimal floating point format is composed from the number in a different format. A decimal floating point format includes fields to hold information relating to the sign, exponent and significand of the decimal floating point finite number. Other decimal floating point data, including infinities and NaNs (not a number), are also composed. Decimal floating point data are also decomposed from the decimal floating point format to a different format. For composition and decomposition, one or more instructions may be employed, including one or more convert instructions. | 10-30-2008 |
20080270498 | CONVERT SIGNIFICAND OF DECIMAL FLOATING POINT DATA TO PACKED DECIMAL FORMAT - A decimal floating point finite number in a decimal floating point format is composed from the number in a different format. A decimal floating point format includes fields to hold information relating to the sign, exponent and significand of the decimal floating point finite number. Other decimal floating point data, including infinities and NaNs (not a number), are also composed. Decimal floating point data are also decomposed from the decimal floating point format to a different format. For composition and decomposition, one or more instructions may be employed, including one or more convert instructions. | 10-30-2008 |
20080270499 | DECOMPOSITION OF DECIMAL FLOATING POINT DATA - A decimal floating point finite number in a decimal floating point format is composed from the number in a different format. A decimal floating point format includes fields to hold information relating to the sign, exponent and significand of the decimal floating point finite number. Other decimal floating point data, including infinities and NaNs (not a number), are also composed. Decimal floating point data are also decomposed from the decimal floating point format to a different format. | 10-30-2008 |
20080281890 | FAST CORRECTLY-ROUNDING FLOATING-POINT CONVERSION - A system and method for converting bases of floating point numbers using fixed-point computation includes tables having different related spacings of exponent indices. The tables are adapted to cross-reference conversion ratios between exponent bases. The tables are characterized by bi-uniform spacings of source and target exponents and including near-unity table entries representing the conversion ratios. A source number is converted into a target number in a different radix by a sequence of reduction operations using a sequence of the tables. The reduction operations include reducing a source number exponent magnitude and accumulating a target exponent and multiplying a source number mantissa by a selected conversion ratio including a near-unity ratio of powers. A final mantissa is normalized and rounded to produce the target number in a new radix. | 11-13-2008 |
20080307022 | Mixed Radix Conversion with a Priori Defined Statistical Artifacts - A method is presided for masking a process used in generating a random number sequence. The method includes generating a random number sequence. This step involves selectively generating the random number sequence utilizing a ring structure which has been punctured. The method also includes performing a mixed radix conversion to convert the random number sequence from a first number base to a second number base. The method further includes puncturing the ring structure by removing at least one element therefrom to eliminate a statistical artifact in the random number sequence expressed in the second number base. The first number base and second number base are selected so that they are respectively defined by a first Galois field characteristic and a second Galois field characteristic. | 12-11-2008 |
20090089346 | Method For Performing A Division Operation In A System - A method for performing a division operation in a system includes a) determining an approximate quotient of a numerator value and a denominator value; b) determining an initial error of the approximate quotient; c) determining a quotient adjustment value based on the initial error; d) determining whether to apply the quotient adjustment value to the approximate quotient; e) if the determination at d) is YES, then applying the quotient adjustment value to the approximate quotient; f) determining an iterative error of the approximate quotient; g) updating the quotient adjustment value based on the iterative error; h) repeating acts d) through g) until the determination at d) is NO, thereby determining a final value for the approximate quotient; i) generating an integer quotient based on the final value of the approximate quotient; and j) using the integer quotient with regard to at least one aspect of the system. | 04-02-2009 |
20090198752 | ASCII to Binary Decimal Integer Conversion in a Vector Processor - A system, method, and apparatus for the constant time, branchless conversion of decimal integers of varying size in ASCII format to a decimal integer in binary decimal format in a vector processor. | 08-06-2009 |
20090210467 | ASCII to Binary Floating Point Conversion of Decimal Real Numbers on a Vector Processor - The present invention provides a system, method, and apparatus for converting a decimal real number in ASCII format to a decimal real number in floating point binary decimal format in a vector processor. | 08-20-2009 |
20090319589 | USING FRACTIONAL EXPONENTS TO REDUCE THE COMPUTATIONAL COMPLEXITY OF NUMERICAL OPERATIONS - Technologies are described herein for using efficient log-linear transformations to reduce the complexity of numerical computations. Efficient transforms can convert between linear fixed point values and log space values in about ten processor cycles per sample. A fractional exponent and an integer exponent may be combined together into a log domain variable representation. Log domain arithmetic operations may be performed on the combined variable as a whole. A fractional exponent representation of log domain numerical values can support automatic bit carries from the fractional exponent into the integer exponent. If an intermediate result of a calculation in the log domain causes the fractional portion of the exponent to exceed one, a bit carry can occur over to the integer component of the exponent. This carry can occur automatically due to the conjoined placement of the integer and fractional components of the exponent in the log domain combined variable. | 12-24-2009 |
20100049777 | REPRESENTATION CONVERTING APPARATUS, ARITHMETIC APPARATUS, REPRESENTATION CONVERTING METHOD, AND COMPUTER PROGRAM PRODUCT - When converting an affine representation representing a 2r-th degree algebraic torus T | 02-25-2010 |
20100169396 | EFFICIENT COMPUTATION FOR EIGENVALUE DECOMPOSITION AND SINGULAR VALUE DECOMPOSITION OF MATRICES - For eigenvalue decomposition, a first set of at least one variable is derived based on a first matrix being decomposed and using Coordinate Rotational Digital Computer (CORDIC) computation. A second set of at least one variable is derived based on the first matrix and using a look-up table. A second matrix of eigenvectors of the first matrix is then derived based on the first and second variable sets. To derive the first variable set, CORDIC computation is performed on an element of the first matrix to determine the magnitude and phase of this element, and CORDIC computation is performed on the phase to determine the sine and cosine of this element. To derive the second variable set, intermediate quantities are derived based on the first matrix and used to access the look-up table. | 07-01-2010 |
20100306289 | SORTABLE FLOATING POINT NUMBERS - The invention comprises methods for manipulating floating point numbers on a microprocessor where the numbers are sortable. That is, the numbers obey lexicographical ordering. Hence, the numbers may be quickly compared using bit-wise comparison functions such as memcmp( ). Conversion may result in a sortable floating point number in the form of a sign, leading bits of the exponent, and sets of digit triples in the form of declets (sets of 10 bits). In a variable-length version, numbers may be compressed by storing the number of trailing zero declets in lieu of storing the zero declets themselves. | 12-02-2010 |
20110106867 | Method, Apparatus and Instructions for Parallel Data Conversions - Method, apparatus, and program means for performing a conversion. In one embodiment, a disclosed apparatus includes a destination storage location corresponding to a first architectural register. A functional unit operates responsive to a control signal, to convert a first packed first format value selected from a set of packed first format values into a plurality of second format values. Each of the first format values has a plurality of sub elements having a first number of bits. The second format values have a greater number of bits. The functional unit stores the plurality of second format values into an architectural register. | 05-05-2011 |
20110145308 | SYSTEM TO IMPROVE NUMEREICAL CONVERSIONS AND ASSOCIATED METHODS - A system to improve numerical conversion may include a data processor and a controller configured to convert a floating-point number from the data processor to more than one different floating-point type number. The conversion may enable the selection of the more than one different floating-point type number that satisfies the requirements of an executing application and/or is closest to the original number. | 06-16-2011 |
20110202585 | GENERATING PARTIAL SUMS - A method for generating partial sums from at least four multiple-digit sequences in a computing device includes partitioning the multiple-digit sequences into at least a first set of multiple-digit sequences and a second set of multiple-digit sequences. The method also includes generating at least one auxiliary set of multiple-digit sequences. The auxiliary set includes digits copied from respective digit positions of multiple-digit sequences in the first and second sets. The method further includes replacing the copied digits in the first and second sets by zeros to obtain a first altered set and a second altered set, respectively, of multiple-digit sequences each comprising multiple segments separated by the replaced zeros. The method also includes generating at least a first partial sum by adding the multiple-digit sequences in at least one auxiliary set and generating at least a second and third partial sums by adding the multiple-digit sequences in the first altered set and second altered set, respectively. | 08-18-2011 |
20110264719 | HIGH RADIX DIGITAL MULTIPLIER - The present invention relates to power and hardware efficient digital multipliers configured to multiply an N-bit multiplicand with an M-bit multiplier. The digital multipliers comprise efficient partial product generation through sharing of at least one partial product result. | 10-27-2011 |
20110270901 | Method and System for Bit Stacked Fast Fourier Transform - An FFT algorithm that splits a large bit width waveform into two parts, making it possible to conduct the FFT with much lower logic resource consumption is disclosed. The waveform is split into its most significant bits and its least significant bits through division in the form of a bit shift. Each partial signal is then put through an FFT algorithm. The MSB FFT output is then right bit shifted. The two partial FFT's are summed to create a single output that is largely equivalent to an FFT of the original waveform. Rounding distortion is reduced by overlapping the MSB and LSB partial signals. | 11-03-2011 |
20110270902 | Efficient Multipliers Based on Multiple-Radix Representations - Methods and apparatus for multiplying integers using a double-base numbering system are presented. In one embodiment, a method includes splitting a first integer into a plurality of binary blocks. The method may also include encoding the plurality of binary blocks into a plurality of encoded blocks in a double-base numbering system. Additionally, the method may include producing a plurality of multiples of a second integer. The method may also include producing a plurality partial results. The method may include selectively shifting the plurality of partial results to generate a plurality of shifted partial results, and adding the plurality of partial results and the shifted partial results to create the product of a plurality of integers. | 11-03-2011 |
20110320511 | NAF CONVERSION APPARATUS - According to one embodiment, a NAF conversion apparatus which converts a binary representation of an integer into a w-NAF redundant binary representation includes an acceptance device, a storage device, a shift register, and an update device. The acceptance device accepts the binary representation of the integer for every bit from lower bits. The storage device stores a state value expressed by 1 bit. The shift register stores a state value expressed by (w-1) bits. The update device determines a state of the storage device and a state of the (w−1)-bit shift register at next time, and determines a w-bit parallel output at current time by referring to a 1-bit value accepted by the acceptance device, the state value in the storage device, and the state value in the (w−1)-bit shift register. | 12-29-2011 |
20120005247 | PROCESSING OF LINEAR SYSTEMS OF EQUATIONS - Apparatus and computer programs are provided for generating n high-precision data elements corresponding to an n×1 vector x satisfying Ax=b where A is a symmetric, positive-definite n×n matrix corresponding to n×n predefined high-precision data elements and b is an n×1 vector corresponding to n predefined high-precision data elements. The apparatus ( | 01-05-2012 |
20120011181 | DECIMAL FLOATING-POINT FUSED MULTIPLY-ADD UNIT - A decimal floating-point Fused-Multiply-Add (FMA) unit that performs the operation of ±(A×B)±C on decimal floating-point operands. The decimal floating-point FMA unit executes the multiplication and addition operations compliant with the IEEE 754-2008 standard. Specifically, the decimal floating-point FMA includes a parallel multiplier and injects the addend after required alignment as an additional partial product in the reduction tree used in the parallel multiplier. The decimal floating-point FMA unit may be configured to perform addition-subtraction operations or multiplication operations as standalone operations. | 01-12-2012 |
20120023149 | BIT-WIDTH ALLOCATION FOR SCIENTIFIC COMPUTATIONS - Methods and devices for automatically determining a suitable bit-width for data types to be used in computer resource intensive computations. Methods for range refinement for intermediate variables and for determining suitable bit-widths for data to be used in vector operations are also presented. The invention may be applied to various computing devices such as CPUs, GPUs, FPGAs, etc. | 01-26-2012 |
20120047190 | Composition of Decimal Floating Point Data - A decimal floating point finite number in a decimal floating point format is composed from the number in a different format. A decimal floating point format includes fields to hold information relating to the sign, exponent and significand of the decimal floating point finite number. Other decimal floating point data, including infinities and NaNs (not a number), are also composed. Decimal floating point data are also decomposed from the decimal floating point format to a different format. | 02-23-2012 |
20120084335 | METHOD AND APPARATUS OF PROCESSING FLOATING POINT NUMBER - A method and apparatus of processing floating point number(s) is provided. The method which processes a plurality of first floating point numbers each having a mantissa and an exponent includes: normalizing exponents of the first floating point numbers according to a minimum value of the exponents to generate normalized exponents of the first floating point numbers; generating a plurality of second floating point numbers respectively corresponding to the first floating point numbers according to mantissas and the normalized exponents of the first floating point numbers; utilizing a processor to perform a specific computation on the second floating point numbers to generate a plurality of third floating point numbers; and de-normalizing each of the normalized exponents to accordingly generate a de-normalization result and adjusting the third floating point numbers according to the de-normalization result. | 04-05-2012 |
20120089653 | Data Converting Method and a Device Therefor - A data converting method and device therefor are disclosed by the invention, relating to data converting algorithm field, solving the problem of complicate data converting method in prior art. Steps of the invention are obtaining offset from the predetermined byte of the data string to be converted; obtaining the predetermined bits of data from the data string to be converted according to the offset; converting the obtained bits to decimal number; determining whether size of the decimal number is smaller than the first predetermined length, if so, keeping adding 0 to the upper digit of the decimal number till the first predetermined length is reached, and taking the data with added 0 as the converted data; otherwise keeping obtaining data from low bit of the decimal number, till the first predetermined length is reached, and taking the obtained data as the converted data. The method of the invention is mainly used for devices and methods requiring data converting, e.g. one time password generating method and device therefor. | 04-12-2012 |
20120089654 | METHOD FOR DEQUANTIZATION OF 1-D LUT CORRECTION CURVES - A method is described to combine two integer lookup tables to realize a single integer lookup table. The method converts each lookup table to a set of floating point values. The conversion process generates a set of floating point values that are as close as possible to the underlying analytic or smooth function that generated the tables in the first place. A system to implement the method is also described. | 04-12-2012 |
20120089655 | System and Method of Dynamic Precision Operations - In an embodiment, a method performs computer operations using a first fractional precision and a second fractional precision. A computer program has a source variable, a destination variable, and an operation. The source variable has a first dynamic fractional precision, the destination variable has a second dynamic fractional precision that differs from the first dynamic fractional precision, and the operation is related to the source variable and the destination variable. The source variable is aligned to a format of the destination variable, according to the first dynamic fractional precision and the second dynamic fractional precision. The operation is performed using the destination variable and the source variable. A value is assigned to the destination variable according to the operation. In this manner, a single codebase may be written that operates on various hardware that each have different bit precision capabilities, without requiring additional development and verification effort. | 04-12-2012 |
20120117134 | FLOATING POINT ENCODING SYSTEMS AND METHODS - Systems and methods for encoding floating point numbers. A system can include encoding logic which encodes invalid floating point representations as valid data. Decoding logic can be used to recognize the invalid floating point representations and map can provide the invalid floating point representations to valid data values. The decoding logic then can provide the valid data values so that operations on the valid data values can be performed in accordance with instructions received from an associated program. | 05-10-2012 |
20120124115 | METHODS AND APPARATUSES FOR CONVERTING FLOATING POINT REPRESENTATIONS - A method and an apparatus that determine an addend in a first floating point format from a first representation of a number in the first floating point format are described. An arithmetic processing unit may be instructed to perform a floating point add operation to generate a sum in the first floating point format from the addend and the first representation. A second representation of the number in a second floating point format may be extracted directly from the sum. The first floating point format and the second floating point format may be based on different precisions for the first and second representation of the number. | 05-17-2012 |
20120124116 | APPARATUS AND METHOD FOR CONVERTING DATA BETWEEN A FLOATING-POINT NUMBER AND AN INTEGER - An apparatus and method for converting data between a floating-point number and an integer is provided. The apparatus includes a data converter configured to determine a sign of input binary data and an output format to which to convert the input binary data and convert the input binary data into a one's complement number based on the sign and the output format of the input binary data, a bias value generator configured to determine whether the input binary data has been rounded up based on a rounding mode of the input binary data and generate a bias value accordingly; and an adder configured to convert the input binary data into a two's complement number by adding the one's complement number and the bias value. | 05-17-2012 |
20120131078 | ARITHMETIC DEVICE - According to one embodiment, a first shift amount calculation unit counts the number of continuous zeros from a less significant bit toward a more significant bit of an intermediate result of a computation of Montgomery multiplication result z and calculates a first shift amount. A second shift amount calculation unit counts the number of continuous zeros from a less significant bit toward a more significant bit of redundant-binary-represented integer x and calculates a second shift amount. An addition/subtraction unit calculates the intermediate result by adding/subtracting, with respect to the intermediate result which has been bit-shifted by the first shift amount, the integer p, and the integer y which has been bit-shifted by the second shift amount. An output unit outputs, as the Montgomery multiplication result z, the intermediate result when the sum of the first shift amounts is equal to the number of bits of the integer p. | 05-24-2012 |
20120136909 | CLOUD ANOMALY DETECTION USING NORMALIZATION, BINNING AND ENTROPY DETERMINATION - Illustrated is a system and method for anomaly detection in data centers and across utility clouds using an Entropy-based Anomaly Testing (EbAT), the system and method including normalizing sample data through transforming the sample data into a normalized value that is based, in part, on an identified average value for the sample data. Further, the system and method includes binning the normalized value through transforming the normalized value into a binned value that is based, in part, on a predefined value range for a bin such that a bin value, within the predefined value range, exists for the sample data. Additionally, the system and method includes identifying at least one vector value from the binned value. The system and method also includes generating an entropy time series through transforming the at least one vector value into an entropy value to be displayed as part of a look-back window. | 05-31-2012 |
20120158807 | MATCHING DATA BASED ON NUMERIC DIFFERENCE - Systems and methods for matching data based on numeric difference are described herein. Input data elements are parsed to identify a first number and a second number. A difference between the first number and the second number is calculated based on a predefined formula. Based on the difference, a matching score between the input data elements is evaluated. The matching score is proportional to a base matching score corresponding to a threshold difference, and a maximum score corresponding to a match between the first number and the second number. A similarity between the input data elements is reported based on the evaluated matching score. | 06-21-2012 |
20120197953 | MONTGOMERY INVERSE CALCULATION DEVICE AND METHOD OF CALCULATING MONTGOMERY INVERSE USING THE SAME - A Montgomery inverse calculation device includes a plurality of registers each storing a value of a variable, a modulus register storing a modulus, a multiplier performing multiplication on the modulus. A comparator compares the value of the variable stored in each of the registers with an output value of the multiplier and generates a plurality of control signals. A plurality of shifters shifts bits of a value of a variable stored in a corresponding register among the registers in response to at least one first control signal, and a quotient generation block calculates a quotient of mod 2m with respect to values output from some of the shifters in response to a second control signal. A calculation block calculates an updated value of an output value of each of the shifters using the quotient in response to at least one third control signal. | 08-02-2012 |
20120215822 | Number format pre-conversion instructions - Apparatus for processing data includes processing circuitry | 08-23-2012 |
20120226724 | FULLY DIGITAL CHAOTIC DIFFERENTIAL EQUATION-BASED SYSTEMS AND METHODS - Various embodiments are provided for fully digital chaotic differential equation-based systems and methods. In one embodiment, among others, a digital circuit includes digital state registers and one or more digital logic modules configured to obtain a first value from two or more of the digital state registers; determine a second value based upon the obtained first values and a chaotic differential equation; and provide the second value to set a state of one of the plurality of digital state registers. In another embodiment, a digital circuit includes digital state registers, digital logic modules configured to obtain outputs from a subset of the digital shift registers and to provide the input based upon a chaotic differential equation for setting a state of at least one of the subset of digital shift registers, and a digital clock configured to provide a clock signal for operating the digital shift registers. | 09-06-2012 |
20120271871 | DOUBLE PRECISION APPROXIMATION OF A SINGLE PRECISION OPERATION - A method for double precision approximation of a single precision operation is disclosed. The method may include steps (A) to (B). Step (A) may store an input value in a processor. The processor generally implements a plurality of first operations in hardware. Each first operation may receive a first variable as an argument. The first variable may be implemented in a fixed point format at a single precision. The input value may be implemented in the fixed point format at a double precision. Step (B) may generate an output value by emulating a selected one of the first operations using the input value as the argument. The emulation may utilize the selected first operation in hardware. The output value may be implemented in the fixed point format at the double precision. The emulation is generally performed by a plurality of instructions executed by the processor. | 10-25-2012 |
20130046804 | METHOD FOR IMPLEMENTING 32 BIT COMPLEX MULTIPLICATION BY USING 16-BIT COMPLEX MULTIPLIERS - An apparatus including a first circuit and a second circuit. The first circuit may be configured to receive a first 2N-bit complex number and a second 2N-bit complex number, each having a first format, and to reformat the first and the second 2N-bit complex numbers to a second format such that a lower portion of each real and imaginary part of each 2N-bit complex number is positive. The second circuit may be configured to multiply the first and the second 2N-bit complex numbers using at least one N-bit signed complex multiplier, where N is an integer. | 02-21-2013 |
20130066932 | CONSTANT GEOMETRY SPLIT RADIX FFT - An apparatus for performing a Fast Fourier Transform (FFT) is provided. The apparatus comprises a reorder matrix, symmetrical butterflies, and a memory. The reorder matrix is configured to have a constant geometry, and the butterflies are coupled in parallel to the reorder matrix. The memory is also coupled to the reorder matrix and each butterfly. The reorder matrix, the butterflies, and the memory can then execute a split radix algorithm. | 03-14-2013 |
20130132452 | Method and Apparatus for Fast Computation of Integral and Fractional Parts of a High Precision Floating Point Multiplication Using Integer Arithmetic - A system and method which multiplies the bits using integer multiplication is set forth. More specifically, performing a floating point operation using integer multiplication includes performing a high precision multiplication of an input ‘x’ having a first bit width using a plurality of integer multiplication operations of a second bit width, the second bit width being smaller than the first bit width, the plurality of integer multiplication operations each generating a result corresponding the first bit width. | 05-23-2013 |
20130212139 | MIXED PRECISION ESTIMATE INSTRUCTION COMPUTING NARROW PRECISION RESULT FOR WIDE PRECISION INPUTS - A technique is provided for performing a mixed precision estimate. A processing circuit receives an input of a first precision having a wide precision value. The processing circuit computes an output in an output exponent range corresponding to a narrow precision value based on the input having the wide precision value. | 08-15-2013 |
20130218936 | Method, Apparatus and Instructions for Parallel Data Conversions - Method, apparatus, and program means for performing a conversion. In one embodiment, a disclosed apparatus includes a destination storage location corresponding to a first architectural register. A functional unit operates responsive to a control signal, to convert a first packed first format value selected from a set of packed first format values into a plurality of second format values. Each of the first format values has a plurality of sub elements having a first number of bits. The second format values have a greater number of bits. The functional unit stores the plurality of second format values into an architectural register. | 08-22-2013 |
20130246490 | CONVERTING BINARY VALUES INTO BINARY-CODED-CENTIMAL VALUES - The disclosed embodiments facilitate converting binary values into the BCC format. One technique facilitates the direct conversion of binary numbers into BCC. A second variation first converts a binary number into an intermediate BCD value, and then converts that BCD value into a BCC value. Look-ahead comparators can further improve conversion performance by decreasing the latency of the conversion operation. By speeding up the conversion of binary values to decimal-format values, the disclosed techniques facilitate leveraging dedicated binary-format hardware for decimal-format operations, and thus improve the performance of decimal-format operations. | 09-19-2013 |
20130246491 | SOFTWARE-HARDWARE ADDER - A data processing system, method and computer program product to receive general-purpose code for iterative summation of an aggregate number of addends, wherein each addend has a precision. The data processing system operates an arithmetic hardware unit to set a first set of input registers to be a target of memory mapped registers and uses a broad-based adder to generate an adder result, wherein the broad-based adder has a broad-based adder size of inputs, and the broad-based adder size is less than the aggregate number of addends and greater than two, wherein each input register of the first set of input registers is connected to each input. Further, the data processing system may write the adder result to a storage array in memory, wherein the adder result is the sum of the inputs, and the adder result is placed in the storage array as indexed by a storage array index. | 09-19-2013 |
20130262539 | CONVERSION AND COMPRESSION OF FLOATING-POINT AND INTEGER DATA - Compression and decompression of numerical data can apply to floating-point or integer samples. Floating-point samples are converted to integer samples and the integer samples are compressed and encoded to produce compressed data for compressed data packets. For decompression, the compressed data retrieved from compressed data packets are decompressed to produce decompressed integer samples. The decompressed integer samples may be converted to reconstruct floating-point samples. Adaptive architectures can be applied for integer compression and decompression using one or two FIFO buffers and one or two configurable adder/subtractors. Various parameters can adapt the operations of adaptive architectures as appropriate for different data characteristics. The parameters can be encoded for the compressed data packet. This abstract does not limit the scope of the invention as described in the claims. | 10-03-2013 |
20130282778 | System and Method for Signal Processing in Digital Signal Processors - An embodiment of a method and a related apparatus for digital computation of a floating point complex multiply-add is provided. The method includes receiving an input addend, a first product, and a second product. The input addend, the first product and the second product each respectively has a mantissa and an exponent. The method includes shifting the mantissas of the two with smaller exponents of the input addend, the first product, and the second product to align together with the mantissa of the one with largest exponent of the input addend, the first product and the second product, and adding the aligned input addend, the aligned first product and the aligned second product. | 10-24-2013 |
20140101215 | DPD/BCD TO BID CONVERTERS - A method and system for binary coded decimal (BCD) to binary conversion. The conversion includes obtaining a BCD significand corresponding to multiple decimal digits; generating, by a BCD/binary hardware converter and based on the BCD significand, multiple binary vectors corresponding to the multiple decimal digits; and calculating, by the BCD/binary hardware converter, a binary output by summing the multiple binary vectors. | 04-10-2014 |
20140101216 | MIXED PRECISION ESTIMATE INSTRUCTION COMPUTING NARROW PRECISION RESULT FOR WIDE PRECISION INPUTS - A technique is provided for performing a mixed precision estimate. A processing circuit receives an input of a first precision having a wide precision value. The processing circuit computes an output in an output exponent range corresponding to a narrow precision value based on the input having the wide precision value. | 04-10-2014 |
20140115022 | PROGRAM FOR CORRECTING DATA MEASURED BY PS-OCT AND PS-OCT SYSTEM EQUIPPED WITH THE PROGRAM - Data measured by PS-OCT is corrected in a non-linear manner to enhance the quantitative analysis capability of PS-OCT and permit accurate quantitative diagnosis, including diagnosis of disease stage of lesions, as a useful means for computer diagnosis. Even when retardation per PS-OCT | 04-24-2014 |
20140129601 | CONVERSION APPARATUS FOR A RESIDUE NUMBER ARITHMETIC LOGIC UNIT - Methods and systems for conversion of binary data to residue data, and for conversion of residue data to binary data, allow fully extensible operation with related methods and systems for residue number based ALUs, processors and other hardware. In one or more embodiments, a residue to binary data converter apparatus comprises a mixed radix to fixed radix conversion apparatus. In one or more embodiments, a mixed radix converter apparatus assists internal processing of a related residue number based ALU, processor or other hardware. | 05-08-2014 |
20140188962 | Executing Perform Floating Point Operation Instructions - A perform floating-point operation instruction is executed specifying a Test (T) bit of general register 0, if the T bit is ‘1’ the execution sets a condition code value indicating whether a specified conversion function is installed, if the T bit is ‘0’ the execution stores a result of a specified floating-point conversion function in general register 0 and sets a condition code value. | 07-03-2014 |
20140237010 | DATA PROCESSING APPARATUS, DATA PROCESSING METHOD, AND COMPUTER PRODUCT - A data processing apparatus includes a computing unit that performs a matrix computation between data streams whose unit data is of a matrix format; a determining unit that for each matrix obtained by the matrix computation by the computing unit, determines based on the value of each element included in the matrix, an exponent value for expressing each element included in the matrix as a floating decimal point value; a converting unit that converts the value of each element into a significand value of the element, according to the exponent value determined by the determining unit; and an output unit that correlates and outputs the exponent value and each matrix after conversion in which the value of each element in the matrix has been converted by the converting unit. | 08-21-2014 |
20140280408 | METHOD AND SYSTEM OF IMPROVED GALOIS MULTIPLICATION - Embodiments of the invention include an apparatus for performing Galois multiplication using an enhanced Galois table. Galois multiplication may include converting a first and second multiplicand to exponential forms using a Galois table, adding the exponential forms of the first and second multiplicands, and converting the added exponential forms of the first and second multiplicands to a decimal equivalent binary form using the Galois table to decimal equivalent binary result of the Galois multiplication. | 09-18-2014 |
20140289294 | COMPLETE MAPPING OF FRACTAL POTENTIAL AND FIELD LINES - Faster methods for topological categorization and field line calculations are developed by using decomposition regions together with the self-winding techniques first developed in a prior patent application. A point iteration technique provides direct calculation of low order digits of winding counts without use of complex intervals. Easy to calculate derivatives define decomposition interval boundaries which substitute for methods using the slower complex interval processing of the prior patent. Methods common to this and the prior patent are developed for visualizing conformal mappings of iterated functions. | 09-25-2014 |
20140304314 | Decomposition Of Decimal Floating Point Data - A decimal floating point finite number in a decimal floating point format is composed from the number in a different format. A decimal floating point format includes fields to hold information relating to the sign, exponent and significand of the decimal floating point finite number. Other decimal floating point data, including infinities and NaNs (not a number), are also composed. Decimal floating point data are also decomposed from the decimal floating point format to a different format. | 10-09-2014 |
20150026227 | Block Exponent Integer Data Format - A digital processing system comprises an input configured for receiving data in block exponent integer format, wherein each block comprises a plurality of data values sharing a single exponent. The plurality of data values has a common data bit width, and the exponent has an exponent bit width. An arithmetic processor performs arithmetic operations on the input data to produce output data in block exponent integer format. The arithmetic processor comprises a format optimizer for reducing at least one of the data bit width and the exponent bit width prior to performing arithmetic operations. The bit width is reduced to improve system power efficiency while meeting a predetermined target system performance. | 01-22-2015 |
20150039661 | TYPE CONVERSION USING FLOATING-POINT UNIT - Techniques are disclosed relating to type conversion using a floating-point unit. In one embodiment, to convert a floating-point value to a normalized integer format, a floating-point unit is configured to perform an operation to generate a result having a significant portion and an exponent portion, where the operation includes multiplying the floating-point value by a constant. In one embodiment, the apparatus is further configured to add a value to the exponent portion of the result, and set a rounding mode to round to nearest. The constant may be a greatest value less than one that can be represented using the particular number of unsigned bits. The value added to the initial exponent may be equal to the number of unsigned bits of the normalized integer format. The apparatus may perform this conversion in response to a pack instruction. | 02-05-2015 |
20150074156 | METHODS AND SYSTEMS TO COMPENSATE FOR NON-LINEARITY OF A STOCHASTIC SYSTEM - Determination of digital compensation to compensate for non-linearity of stochastic system configured to sample a phase difference, based on statistical analysis of calibration data generated by the stochastic system in response to a linear phase ramp. The stochastic system may include a set of stochastic sampler circuits to sample a phase difference at periodic events, and calibration data may include a digital value of set of stochastic samples for each of multiple events. The calibration data may include sequences of the digital values in which the digital values increment over a range of the stochastic system (i.e., between saturation states of the stochastic system). Statistical analysis may include histogram analysis to estimate the probability distribution of the calibration data. The stochastic system may be configured as part of a time-to-digital converter, which may be configured within a feedback loop of a digitally controllable phase lock loop. | 03-12-2015 |
20150095387 | SYSTEM AND METHOD FOR CONVERSION OF NUMERIC VALUES BETWEEN DIFFERENT NUMBER BASE FORMATS, FOR USE WITH SOFTWARE APPLICATIONS - Described herein are systems and methods for conversion of numeric values between different number base formats, for use with software applications. In accordance with an embodiment, an integral part of a passed floating-point numeric value in a source number base (e.g., binary) format is isolated and converted to an integer. A fractional part of the numeric value is also isolated and converted to an integer, while limiting the isolation and conversion of the fractional part to a required precision or number of digits, depending on the particular requirements of a software application. The fractional part can be rounded, including determining an exact roundoff as appropriate, and if necessary propagating the rounding to the integral part. Digits from the resulting integers representing the integral and fractional parts can then be collected and used to prepare a representation of the original numeric value in a target number base (e.g., decimal) format. | 04-02-2015 |
20150100610 | GEOMETRIC COUNTING MECHANISMS - Disclosure for representing one or more numbers as a geometric counting mechanism that comprises an arrangement of geometric shapes and decoding the geometric counting mechanism into the represented number or numbers is provided. Decoding a geometric counting mechanism includes at least identifying a container geometry, determining a primary multiplier, a secondary multiplier, and an additive component value based on the geometric shapes identified in the geometric counting mechanism and their locations in the arrangement. The geometric counting mechanism can be decoded in a clockwise and/or counterclockwise manner, therefore one geometric counting mechanism can represent more than one number. | 04-09-2015 |
20150100611 | CONTROL DEVICE FOR EXECUTING CONTROL PROGRAM INCLUDING FLOATING POINT OPERATION COMMAND FOR CONTROLLING MACHINE AND METHOD OF CONVERTING FLOATING POINT PARAMETER IN CONTROL PROGRAM - A control device includes: a first conversion unit that converts floating point data generated by an operation of a floating point operation command into a numeric string in first format; and a second conversion unit that converts the numeric string in first format into a numeric string in second format. A character string data generation unit generates a character string data including the numeric strings in first format and in second format and outputs the character string data to an external device or an external storage medium. | 04-09-2015 |
20150106413 | METHOD AND SYSTEM FOR SOLVING A CONVEX INTEGER QUADRATIC PROGRAMMING PROBLEM USING A BINARY OPTIMIZER - A method and system are disclosed for solving a convex integer quadratic programming problem using a binary optimizer, the method comprising use of a processor for receiving a convex integer quadratic programming problem; converting the convex integer quadratic programming problem into a plurality of constrained and unconstrained binary quadratic programming problems and providing the plurality of unconstrained binary quadratic programming problems to the binary optimizer to thereby solve the convex integer quadratic programming problem. | 04-16-2015 |
20150113027 | METHOD FOR DETERMINING A LOGARITHMIC FUNCTIONAL UNIT - A method for determining a logarithmic functional unit comprises providing a segment number; using the segment number to determine a piecewise linear approximation on a plurality of corresponding intervals for approximating a function for converting a fraction; providing a bit precision; converting endpoints separating the plurality of intervals to corresponding binary endpoints separating an additional plurality of intervals in the bit precision; determining an adjusted piecewise linear approximation that has an approximation error less than a threshold and is on the additional plurality of intervals; encoding coefficients of the adjusted piecewise linear approximation; determining a less precise approximation from the adjusted piecewise linear approximation as a candidate linear approximation, wherein the less precise approximation uses an argument value having a least bit-width while still being able to have an approximation error less than the threshold; and implementing the less precise approximation to obtain an implementation circuit. | 04-23-2015 |
20150120795 | NUMBER FORMAT PRE-CONVERSION INSTRUCTIONS - Apparatus for processing data includes processing circuitry | 04-30-2015 |
20150120796 | Standing wave simple math processor - The standing wave simple math processor is a new system for doing simple math (addition). By utilizing standing waves and conventional connections, a charge of direct current is transferred from 2 adjacent standing waves to 1 final standing wave representing the output. In essence the two input waves function as operands in a math problem. The operator, in this sense, is an interconnection of DC current between the 3 standing waves, as well as a set of redistribution rules. The final solution is retrieved upon completion of the redistribution rules. | 04-30-2015 |
20150301801 | METHOD, APPARATUS AND INSTRUCTIONS FOR PARALLEL DATA CONVERSIONS - Method, apparatus, and program means for performing a conversion. In one embodiment, a disclosed apparatus includes a destination storage location corresponding to a first architectural register. A functional unit operates responsive to a control signal, to convert a first packed first format value selected from a set of packed first format values into a plurality of second format values. Each of the first format values has a plurality of sub elements having a first number of bits. The second format values have a greater number of bits. The functional unit stores the plurality of second format values into an architectural register. | 10-22-2015 |
20150378674 | CONVERTING NUMERIC-CHARACTER STRINGS TO BINARY NUMBERS - Improvements to the functioning of computers include algorithms and data structures for specific focal aspects of conversion from character strings to numeric values. Tables used include a Doubles10 table, BaseTbl, TensTbl, and others. Algorithms convert floating-point character strings into doubles or integers; process whitespace, signs, leading zeroes, and invalid characters; use addition instead of multiplying or shifting; use particular processor registers to advantage; eliminate some overflow testing; use few MULTIPLY commands and avoid DIVIDE instructions; create stub functions that call a core function as herein described; avoid carry-producing instructions; count digits before converting; use only aligned reads to access a memory via multiple-byte; and/or utilize other focal aspects. | 12-31-2015 |
20150378680 | UNDERFLOW/OVERFLOW DETECTION PRIOR TO NORMALIZATION - Methods and apparatuses for generating a condition code for a floating point number operation prior to normalization. A processor receives an intermediate result for an operation, wherein the intermediate result comprises an intermediate significand and an intermediate exponent. A processor determines a mask based on the value of the intermediate exponent. A processor generates a masked significand by applying the mask to the intermediate significand. A processor generates a condition code based on the masked significand having a predetermined value. | 12-31-2015 |
20160087646 | APPARATUS AND METHOD FOR MAPPING BINARY TO TERNARY AND ITS REVERSE - Described is an apparatus for converting binary data to ternary and back such that the apparatus comprises: a first look-up table (LUT) having a mapping of 19 binary bits to 12 ternary trits; and a first logic to receive a binary input and to convert the binary input to a ternary output according to the first LUT. | 03-24-2016 |
20160092162 | MACHINE INSTRUCTIONS FOR CONVERTING TO DECIMAL FLOATING POINT FORMAT FROM PACKED DECIMAL FORMAT - Embodiments relate to converting data from a packed decimal format to a decimal floating point format by executing a machine instruction. A method of executing the machine instruction is provided. The method reads data in a packed decimal format from a memory that is communicatively coupled to a processor. The method converts the data in the packed decimal format into a decimal floating point format. The method writes the data converted into the decimal floating point format to one or more target registers of the processor. | 03-31-2016 |
20160092163 | MACHINE INSTRUCTIONS FOR CONVERTING FROM DECIMAL FLOATING POINT FORMAT TO PACKED DECIMAL FORMAT - Embodiments relate to converting data from a decimal floating point format to a packed decimal format by executing a machine instruction. A method of executing the machine instruction is provided. The method reads data in a decimal floating point format from one or more registers of a processor that is communicatively coupled to a memory. The method converts the data in the decimal floating point format into a packed decimal format. The method writes the data converted into the packed decimal format to the memory. | 03-31-2016 |
20160092164 | MACHINE INSTRUCTIONS FOR CONVERTING TO DECIMAL FLOATING POINT FORMAT FROM PACKED DECIMAL FORMAT - Embodiments relate to converting data from a packed decimal format to a decimal floating point format by executing a machine instruction. A method of executing the machine instruction is provided. The method reads data in a packed decimal format from a memory that is communicatively coupled to a processor. The method converts the data in the packed decimal format into a decimal floating point format. The method writes the data converted into the decimal floating point format to one or more target registers of the processor. | 03-31-2016 |
20160092168 | APPARATUS AND METHOD FOR CONVERTING FLOATING-POINT OPERAND INTO A VALUE HAVING A DIFFERENT FORMAT - A data processing apparatus has floating-point add circuitry to perform a floating-point addition operation for adding or subtracting two floating-point values. The apparatus also has conversion circuitry to perform a conversion operation to convert a first floating-point value into a second value having a different format. The conversion circuitry is capable of converting to an integer or fixed-point value. The conversion circuitry is physically distinct from the floating-point add circuitry. | 03-31-2016 |
20160124708 | APPARATUS, METHOD AND PROGRAM FOR CALCULATING THE RESULT OF A REPEATING ITERATIVE SUM - An apparatus, method and program are provided for calculating a result value to a required precision of a repeating iterative sum, wherein the repeating iterative sum comprises multiple iterations of an addition using an input value. Addition is performed in a single iteration of addition as a sum operation using overlapping portions of the input value and a shifted version of the input value, wherein the shifted version of the input value has a partial overlap with the input value. At least one result portion is produced by incrementing an input derived from the input value using the output from the sum operation and the result value is constructed using the at least one result portion to give the result value to the required precision. The repeating iterative sum is thereby flattened into a flattened calculation which requires only a single iteration of addition using the input value, thus facilitating the calculation of the result value of the repeating iterative sum. | 05-05-2016 |
20160124717 | Method and System of Improved Galois Multiplication - Embodiments of the invention include an apparatus for performing Galois multiplication using an enhanced Galois table. Galois multiplication may include converting a first and second multiplicand to exponential forms using a Galois table, adding the exponential forms of the first and second multiplicands, and converting the added exponential forms of the first and second multiplicands to a decimal equivalent binary form using the Galois table to decimal equivalent binary result of the Galois multiplication. | 05-05-2016 |
20160126974 | APPARATUS AND METHOD FOR PERFORMING CONVERSION OPERATION - An apparatus comprises processing circuitry to perform a conversion operation to convert a vector comprising a plurality of data elements representing respective bit significance portions of a binary value to a scalar value comprising an alternative representation of said binary value. | 05-05-2016 |
20160126975 | APPARATUS AND METHOD FOR PERFORMING CONVERSION OPERATION - An apparatus comprises processing circuitry to perform a conversion operation to convert a floating-point value to a vector comprising a plurality of data elements representing respective bit significance portions of a binary value corresponding to the floating-point value. | 05-05-2016 |
20160132462 | Methods And Systems For Calculating Uncertainty - Disclosed are methods and systems for performing uncertainty calculations. For example, a first numeric value and an error range associated with the first numeric value is converted by a processor into a dual number, which is then converted into an input chordal, where the input chordal is both a numeric and a geometric form of the dual number. A chordal calculation is performed using the input chordal to create an output chordal, and the processor then converts the output chordal to an output numeric value that comprises both a number and an error range associated with that number. | 05-12-2016 |
20180024812 | DYNAMIC EVALUATION AND ADAPTION OF HARDWARE HASH FUNCTION | 01-25-2018 |
20220137923 | COMPUTING METHOD AND COMPUTING DEVICE FOR FLOATING-POINT MATHEMATIC OPERATION USING LOOKUP TABLE - A computing device for floating-point mathematic operation using look-up table is provided. The computing device includes: a bit arrangement unit used for receiving a floating-point input data and performing a bit arrangement or a format conversion on the floating-point input data to generate multiple index blocks; a first look-up table unit group used for receiving the index blocks and performing look-up operation using the index blocks as index to generate a plurality of look-up table results; and an operation unit used for performing operation on the look-up table results of the first look-up table unit group to generate an operation output. | 05-05-2022 |