| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 708204000 | Format conversion | 59 |
| 20080270495 | INSERT/EXTRACT BIASED EXPONENT OF DECIMAL FLOATING POINT DATA - A decimal floating point finite number in a decimal floating point format is composed from the number in a different format. A decimal floating point format includes fields to hold information relating to the sign, exponent and significand of the decimal floating point finite number. Other decimal floating point data, including infinities and NaNs (not a number), are also composed. Decimal floating point data are also decomposed from the decimal floating point format to a different format. For composition and decomposition, one or more instructions may be employed, including an insert biased exponent or extract biased exponent instruction. | 10-30-2008 |
| 20100049777 | REPRESENTATION CONVERTING APPARATUS, ARITHMETIC APPARATUS, REPRESENTATION CONVERTING METHOD, AND COMPUTER PROGRAM PRODUCT - When converting an affine representation representing a 2r-th degree algebraic torus T | 02-25-2010 |
| 20110202585 | GENERATING PARTIAL SUMS - A method for generating partial sums from at least four multiple-digit sequences in a computing device includes partitioning the multiple-digit sequences into at least a first set of multiple-digit sequences and a second set of multiple-digit sequences. The method also includes generating at least one auxiliary set of multiple-digit sequences. The auxiliary set includes digits copied from respective digit positions of multiple-digit sequences in the first and second sets. The method further includes replacing the copied digits in the first and second sets by zeros to obtain a first altered set and a second altered set, respectively, of multiple-digit sequences each comprising multiple segments separated by the replaced zeros. The method also includes generating at least a first partial sum by adding the multiple-digit sequences in at least one auxiliary set and generating at least a second and third partial sums by adding the multiple-digit sequences in the first altered set and second altered set, respectively. | 08-18-2011 |
| 20130046804 | METHOD FOR IMPLEMENTING 32 BIT COMPLEX MULTIPLICATION BY USING 16-BIT COMPLEX MULTIPLIERS - An apparatus including a first circuit and a second circuit. The first circuit may be configured to receive a first 2N-bit complex number and a second 2N-bit complex number, each having a first format, and to reformat the first and the second 2N-bit complex numbers to a second format such that a lower portion of each real and imaginary part of each 2N-bit complex number is positive. The second circuit may be configured to multiply the first and the second 2N-bit complex numbers using at least one N-bit signed complex multiplier, where N is an integer. | 02-21-2013 |
| 20130066932 | CONSTANT GEOMETRY SPLIT RADIX FFT - An apparatus for performing a Fast Fourier Transform (FFT) is provided. The apparatus comprises a reorder matrix, symmetrical butterflies, and a memory. The reorder matrix is configured to have a constant geometry, and the butterflies are coupled in parallel to the reorder matrix. The memory is also coupled to the reorder matrix and each butterfly. The reorder matrix, the butterflies, and the memory can then execute a split radix algorithm. | 03-14-2013 |
| 20110264719 | HIGH RADIX DIGITAL MULTIPLIER - The present invention relates to power and hardware efficient digital multipliers configured to multiply an N-bit multiplicand with an M-bit multiplier. The digital multipliers comprise efficient partial product generation through sharing of at least one partial product result. | 10-27-2011 |
| 20110270902 | Efficient Multipliers Based on Multiple-Radix Representations - Methods and apparatus for multiplying integers using a double-base numbering system are presented. In one embodiment, a method includes splitting a first integer into a plurality of binary blocks. The method may also include encoding the plurality of binary blocks into a plurality of encoded blocks in a double-base numbering system. Additionally, the method may include producing a plurality of multiples of a second integer. The method may also include producing a plurality partial results. The method may include selectively shifting the plurality of partial results to generate a plurality of shifted partial results, and adding the plurality of partial results and the shifted partial results to create the product of a plurality of integers. | 11-03-2011 |
| 20080281890 | FAST CORRECTLY-ROUNDING FLOATING-POINT CONVERSION - A system and method for converting bases of floating point numbers using fixed-point computation includes tables having different related spacings of exponent indices. The tables are adapted to cross-reference conversion ratios between exponent bases. The tables are characterized by bi-uniform spacings of source and target exponents and including near-unity table entries representing the conversion ratios. A source number is converted into a target number in a different radix by a sequence of reduction operations using a sequence of the tables. The reduction operations include reducing a source number exponent magnitude and accumulating a target exponent and multiplying a source number mantissa by a selected conversion ratio including a near-unity ratio of powers. A final mantissa is normalized and rounded to produce the target number in a new radix. | 11-13-2008 |
| 20080270496 | COMPOSITION/DECOMPOSITION OF DECIMAL FLOATING POINT DATA - A decimal floating point finite number in a decimal floating point format is composed from the number in a different format. A decimal floating point format includes fields to hold information relating to the sign, exponent and significand of the decimal floating point finite number. Other decimal floating point data, including infinities and NaNs (not a number), are also composed. Decimal floating point data are also decomposed from the decimal floating point format to a different format. | 10-30-2008 |
| 20080270499 | DECOMPOSITION OF DECIMAL FLOATING POINT DATA - A decimal floating point finite number in a decimal floating point format is composed from the number in a different format. A decimal floating point format includes fields to hold information relating to the sign, exponent and significand of the decimal floating point finite number. Other decimal floating point data, including infinities and NaNs (not a number), are also composed. Decimal floating point data are also decomposed from the decimal floating point format to a different format. | 10-30-2008 |
| 20110270901 | Method and System for Bit Stacked Fast Fourier Transform - An FFT algorithm that splits a large bit width waveform into two parts, making it possible to conduct the FFT with much lower logic resource consumption is disclosed. The waveform is split into its most significant bits and its least significant bits through division in the form of a bit shift. Each partial signal is then put through an FFT algorithm. The MSB FFT output is then right bit shifted. The two partial FFT's are summed to create a single output that is largely equivalent to an FFT of the original waveform. Rounding distortion is reduced by overlapping the MSB and LSB partial signals. | 11-03-2011 |
| 20090198752 | ASCII to Binary Decimal Integer Conversion in a Vector Processor - A system, method, and apparatus for the constant time, branchless conversion of decimal integers of varying size in ASCII format to a decimal integer in binary decimal format in a vector processor. | 08-06-2009 |
| 20100169396 | EFFICIENT COMPUTATION FOR EIGENVALUE DECOMPOSITION AND SINGULAR VALUE DECOMPOSITION OF MATRICES - For eigenvalue decomposition, a first set of at least one variable is derived based on a first matrix being decomposed and using Coordinate Rotational Digital Computer (CORDIC) computation. A second set of at least one variable is derived based on the first matrix and using a look-up table. A second matrix of eigenvectors of the first matrix is then derived based on the first and second variable sets. To derive the first variable set, CORDIC computation is performed on an element of the first matrix to determine the magnitude and phase of this element, and CORDIC computation is performed on the phase to determine the sine and cosine of this element. To derive the second variable set, intermediate quantities are derived based on the first matrix and used to access the look-up table. | 07-01-2010 |
| 20080307022 | Mixed Radix Conversion with a Priori Defined Statistical Artifacts - A method is presided for masking a process used in generating a random number sequence. The method includes generating a random number sequence. This step involves selectively generating the random number sequence utilizing a ring structure which has been punctured. The method also includes performing a mixed radix conversion to convert the random number sequence from a first number base to a second number base. The method further includes puncturing the ring structure by removing at least one element therefrom to eliminate a statistical artifact in the random number sequence expressed in the second number base. The first number base and second number base are selected so that they are respectively defined by a first Galois field characteristic and a second Galois field characteristic. | 12-11-2008 |
| 20120197953 | MONTGOMERY INVERSE CALCULATION DEVICE AND METHOD OF CALCULATING MONTGOMERY INVERSE USING THE SAME - A Montgomery inverse calculation device includes a plurality of registers each storing a value of a variable, a modulus register storing a modulus, a multiplier performing multiplication on the modulus. A comparator compares the value of the variable stored in each of the registers with an output value of the multiplier and generates a plurality of control signals. A plurality of shifters shifts bits of a value of a variable stored in a corresponding register among the registers in response to at least one first control signal, and a quotient generation block calculates a quotient of mod 2m with respect to values output from some of the shifters in response to a second control signal. A calculation block calculates an updated value of an output value of each of the shifters using the quotient in response to at least one third control signal. | 08-02-2012 |
| 20090319589 | USING FRACTIONAL EXPONENTS TO REDUCE THE COMPUTATIONAL COMPLEXITY OF NUMERICAL OPERATIONS - Technologies are described herein for using efficient log-linear transformations to reduce the complexity of numerical computations. Efficient transforms can convert between linear fixed point values and log space values in about ten processor cycles per sample. A fractional exponent and an integer exponent may be combined together into a log domain variable representation. Log domain arithmetic operations may be performed on the combined variable as a whole. A fractional exponent representation of log domain numerical values can support automatic bit carries from the fractional exponent into the integer exponent. If an intermediate result of a calculation in the log domain causes the fractional portion of the exponent to exceed one, a bit carry can occur over to the integer component of the exponent. This carry can occur automatically due to the conjoined placement of the integer and fractional components of the exponent in the log domain combined variable. | 12-24-2009 |
| 20080270498 | CONVERT SIGNIFICAND OF DECIMAL FLOATING POINT DATA TO PACKED DECIMAL FORMAT - A decimal floating point finite number in a decimal floating point format is composed from the number in a different format. A decimal floating point format includes fields to hold information relating to the sign, exponent and significand of the decimal floating point finite number. Other decimal floating point data, including infinities and NaNs (not a number), are also composed. Decimal floating point data are also decomposed from the decimal floating point format to a different format. For composition and decomposition, one or more instructions may be employed, including one or more convert instructions. | 10-30-2008 |
| 20100306289 | SORTABLE FLOATING POINT NUMBERS - The invention comprises methods for manipulating floating point numbers on a microprocessor where the numbers are sortable. That is, the numbers obey lexicographical ordering. Hence, the numbers may be quickly compared using bit-wise comparison functions such as memcmp( ). Conversion may result in a sortable floating point number in the form of a sign, leading bits of the exponent, and sets of digit triples in the form of declets (sets of 10 bits). In a variable-length version, numbers may be compressed by storing the number of trailing zero declets in lieu of storing the zero declets themselves. | 12-02-2010 |
| 20110145308 | SYSTEM TO IMPROVE NUMEREICAL CONVERSIONS AND ASSOCIATED METHODS - A system to improve numerical conversion may include a data processor and a controller configured to convert a floating-point number from the data processor to more than one different floating-point type number. The conversion may enable the selection of the more than one different floating-point type number that satisfies the requirements of an executing application and/or is closest to the original number. | 06-16-2011 |
| 20080270497 | CONVERT SIGNIFICAND OF DECIMAL FLOATING POINT DATA TO/FROM PACKED DECIMAL FORMAT - A decimal floating point finite number in a decimal floating point format is composed from the number in a different format. A decimal floating point format includes fields to hold information relating to the sign, exponent and significand of the decimal floating point finite number. Other decimal floating point data, including infinities and NaNs (not a number), are also composed. Decimal floating point data are also decomposed from the decimal floating point format to a different format. For composition and decomposition, one or more instructions may be employed, including one or more convert instructions. | 10-30-2008 |
| 20090210467 | ASCII to Binary Floating Point Conversion of Decimal Real Numbers on a Vector Processor - The present invention provides a system, method, and apparatus for converting a decimal real number in ASCII format to a decimal real number in floating point binary decimal format in a vector processor. | 08-20-2009 |
| 20090089346 | Method For Performing A Division Operation In A System - A method for performing a division operation in a system includes a) determining an approximate quotient of a numerator value and a denominator value; b) determining an initial error of the approximate quotient; c) determining a quotient adjustment value based on the initial error; d) determining whether to apply the quotient adjustment value to the approximate quotient; e) if the determination at d) is YES, then applying the quotient adjustment value to the approximate quotient; f) determining an iterative error of the approximate quotient; g) updating the quotient adjustment value based on the iterative error; h) repeating acts d) through g) until the determination at d) is NO, thereby determining a final value for the approximate quotient; i) generating an integer quotient based on the final value of the approximate quotient; and j) using the integer quotient with regard to at least one aspect of the system. | 04-02-2009 |
| 20120047190 | Composition of Decimal Floating Point Data - A decimal floating point finite number in a decimal floating point format is composed from the number in a different format. A decimal floating point format includes fields to hold information relating to the sign, exponent and significand of the decimal floating point finite number. Other decimal floating point data, including infinities and NaNs (not a number), are also composed. Decimal floating point data are also decomposed from the decimal floating point format to a different format. | 02-23-2012 |
| 20120005247 | PROCESSING OF LINEAR SYSTEMS OF EQUATIONS - Apparatus and computer programs are provided for generating n high-precision data elements corresponding to an n×1 vector x satisfying Ax=b where A is a symmetric, positive-definite n×n matrix corresponding to n×n predefined high-precision data elements and b is an n×1 vector corresponding to n predefined high-precision data elements. The apparatus ( | 01-05-2012 |
| 20120011181 | DECIMAL FLOATING-POINT FUSED MULTIPLY-ADD UNIT - A decimal floating-point Fused-Multiply-Add (FMA) unit that performs the operation of ±(A×B)±C on decimal floating-point operands. The decimal floating-point FMA unit executes the multiplication and addition operations compliant with the IEEE 754-2008 standard. Specifically, the decimal floating-point FMA includes a parallel multiplier and injects the addend after required alignment as an additional partial product in the reduction tree used in the parallel multiplier. The decimal floating-point FMA unit may be configured to perform addition-subtraction operations or multiplication operations as standalone operations. | 01-12-2012 |
| 20120023149 | BIT-WIDTH ALLOCATION FOR SCIENTIFIC COMPUTATIONS - Methods and devices for automatically determining a suitable bit-width for data types to be used in computer resource intensive computations. Methods for range refinement for intermediate variables and for determining suitable bit-widths for data to be used in vector operations are also presented. The invention may be applied to various computing devices such as CPUs, GPUs, FPGAs, etc. | 01-26-2012 |
| 20120117134 | FLOATING POINT ENCODING SYSTEMS AND METHODS - Systems and methods for encoding floating point numbers. A system can include encoding logic which encodes invalid floating point representations as valid data. Decoding logic can be used to recognize the invalid floating point representations and map can provide the invalid floating point representations to valid data values. The decoding logic then can provide the valid data values so that operations on the valid data values can be performed in accordance with instructions received from an associated program. | 05-10-2012 |
| 20120158807 | MATCHING DATA BASED ON NUMERIC DIFFERENCE - Systems and methods for matching data based on numeric difference are described herein. Input data elements are parsed to identify a first number and a second number. A difference between the first number and the second number is calculated based on a predefined formula. Based on the difference, a matching score between the input data elements is evaluated. The matching score is proportional to a base matching score corresponding to a threshold difference, and a maximum score corresponding to a match between the first number and the second number. A similarity between the input data elements is reported based on the evaluated matching score. | 06-21-2012 |
| 20110106867 | Method, Apparatus and Instructions for Parallel Data Conversions - Method, apparatus, and program means for performing a conversion. In one embodiment, a disclosed apparatus includes a destination storage location corresponding to a first architectural register. A functional unit operates responsive to a control signal, to convert a first packed first format value selected from a set of packed first format values into a plurality of second format values. Each of the first format values has a plurality of sub elements having a first number of bits. The second format values have a greater number of bits. The functional unit stores the plurality of second format values into an architectural register. | 05-05-2011 |
| 20120124116 | APPARATUS AND METHOD FOR CONVERTING DATA BETWEEN A FLOATING-POINT NUMBER AND AN INTEGER - An apparatus and method for converting data between a floating-point number and an integer is provided. The apparatus includes a data converter configured to determine a sign of input binary data and an output format to which to convert the input binary data and convert the input binary data into a one's complement number based on the sign and the output format of the input binary data, a bias value generator configured to determine whether the input binary data has been rounded up based on a rounding mode of the input binary data and generate a bias value accordingly; and an adder configured to convert the input binary data into a two's complement number by adding the one's complement number and the bias value. | 05-17-2012 |
| 20120124115 | METHODS AND APPARATUSES FOR CONVERTING FLOATING POINT REPRESENTATIONS - A method and an apparatus that determine an addend in a first floating point format from a first representation of a number in the first floating point format are described. An arithmetic processing unit may be instructed to perform a floating point add operation to generate a sum in the first floating point format from the addend and the first representation. A second representation of the number in a second floating point format may be extracted directly from the sum. The first floating point format and the second floating point format may be based on different precisions for the first and second representation of the number. | 05-17-2012 |
| 20120131078 | ARITHMETIC DEVICE - According to one embodiment, a first shift amount calculation unit counts the number of continuous zeros from a less significant bit toward a more significant bit of an intermediate result of a computation of Montgomery multiplication result z and calculates a first shift amount. A second shift amount calculation unit counts the number of continuous zeros from a less significant bit toward a more significant bit of redundant-binary-represented integer x and calculates a second shift amount. An addition/subtraction unit calculates the intermediate result by adding/subtracting, with respect to the intermediate result which has been bit-shifted by the first shift amount, the integer p, and the integer y which has been bit-shifted by the second shift amount. An output unit outputs, as the Montgomery multiplication result z, the intermediate result when the sum of the first shift amounts is equal to the number of bits of the integer p. | 05-24-2012 |
| 20120215822 | Number format pre-conversion instructions - Apparatus for processing data includes processing circuitry | 08-23-2012 |
| 20120136909 | CLOUD ANOMALY DETECTION USING NORMALIZATION, BINNING AND ENTROPY DETERMINATION - Illustrated is a system and method for anomaly detection in data centers and across utility clouds using an Entropy-based Anomaly Testing (EbAT), the system and method including normalizing sample data through transforming the sample data into a normalized value that is based, in part, on an identified average value for the sample data. Further, the system and method includes binning the normalized value through transforming the normalized value into a binned value that is based, in part, on a predefined value range for a bin such that a bin value, within the predefined value range, exists for the sample data. Additionally, the system and method includes identifying at least one vector value from the binned value. The system and method also includes generating an entropy time series through transforming the at least one vector value into an entropy value to be displayed as part of a look-back window. | 05-31-2012 |
| 20120084335 | METHOD AND APPARATUS OF PROCESSING FLOATING POINT NUMBER - A method and apparatus of processing floating point number(s) is provided. The method which processes a plurality of first floating point numbers each having a mantissa and an exponent includes: normalizing exponents of the first floating point numbers according to a minimum value of the exponents to generate normalized exponents of the first floating point numbers; generating a plurality of second floating point numbers respectively corresponding to the first floating point numbers according to mantissas and the normalized exponents of the first floating point numbers; utilizing a processor to perform a specific computation on the second floating point numbers to generate a plurality of third floating point numbers; and de-normalizing each of the normalized exponents to accordingly generate a de-normalization result and adjusting the third floating point numbers according to the de-normalization result. | 04-05-2012 |
| 20120226724 | FULLY DIGITAL CHAOTIC DIFFERENTIAL EQUATION-BASED SYSTEMS AND METHODS - Various embodiments are provided for fully digital chaotic differential equation-based systems and methods. In one embodiment, among others, a digital circuit includes digital state registers and one or more digital logic modules configured to obtain a first value from two or more of the digital state registers; determine a second value based upon the obtained first values and a chaotic differential equation; and provide the second value to set a state of one of the plurality of digital state registers. In another embodiment, a digital circuit includes digital state registers, digital logic modules configured to obtain outputs from a subset of the digital shift registers and to provide the input based upon a chaotic differential equation for setting a state of at least one of the subset of digital shift registers, and a digital clock configured to provide a clock signal for operating the digital shift registers. | 09-06-2012 |
| 20120271871 | DOUBLE PRECISION APPROXIMATION OF A SINGLE PRECISION OPERATION - A method for double precision approximation of a single precision operation is disclosed. The method may include steps (A) to (B). Step (A) may store an input value in a processor. The processor generally implements a plurality of first operations in hardware. Each first operation may receive a first variable as an argument. The first variable may be implemented in a fixed point format at a single precision. The input value may be implemented in the fixed point format at a double precision. Step (B) may generate an output value by emulating a selected one of the first operations using the input value as the argument. The emulation may utilize the selected first operation in hardware. The output value may be implemented in the fixed point format at the double precision. The emulation is generally performed by a plurality of instructions executed by the processor. | 10-25-2012 |
| 20120089655 | System and Method of Dynamic Precision Operations - In an embodiment, a method performs computer operations using a first fractional precision and a second fractional precision. A computer program has a source variable, a destination variable, and an operation. The source variable has a first dynamic fractional precision, the destination variable has a second dynamic fractional precision that differs from the first dynamic fractional precision, and the operation is related to the source variable and the destination variable. The source variable is aligned to a format of the destination variable, according to the first dynamic fractional precision and the second dynamic fractional precision. The operation is performed using the destination variable and the source variable. A value is assigned to the destination variable according to the operation. In this manner, a single codebase may be written that operates on various hardware that each have different bit precision capabilities, without requiring additional development and verification effort. | 04-12-2012 |
| 20120089654 | METHOD FOR DEQUANTIZATION OF 1-D LUT CORRECTION CURVES - A method is described to combine two integer lookup tables to realize a single integer lookup table. The method converts each lookup table to a set of floating point values. The conversion process generates a set of floating point values that are as close as possible to the underlying analytic or smooth function that generated the tables in the first place. A system to implement the method is also described. | 04-12-2012 |
| 20120089653 | Data Converting Method and a Device Therefor - A data converting method and device therefor are disclosed by the invention, relating to data converting algorithm field, solving the problem of complicate data converting method in prior art. Steps of the invention are obtaining offset from the predetermined byte of the data string to be converted; obtaining the predetermined bits of data from the data string to be converted according to the offset; converting the obtained bits to decimal number; determining whether size of the decimal number is smaller than the first predetermined length, if so, keeping adding 0 to the upper digit of the decimal number till the first predetermined length is reached, and taking the data with added 0 as the converted data; otherwise keeping obtaining data from low bit of the decimal number, till the first predetermined length is reached, and taking the obtained data as the converted data. The method of the invention is mainly used for devices and methods requiring data converting, e.g. one time password generating method and device therefor. | 04-12-2012 |
| 20110320511 | NAF CONVERSION APPARATUS - According to one embodiment, a NAF conversion apparatus which converts a binary representation of an integer into a w-NAF redundant binary representation includes an acceptance device, a storage device, a shift register, and an update device. The acceptance device accepts the binary representation of the integer for every bit from lower bits. The storage device stores a state value expressed by 1 bit. The shift register stores a state value expressed by (w-1) bits. The update device determines a state of the storage device and a state of the (w−1)-bit shift register at next time, and determines a w-bit parallel output at current time by referring to a 1-bit value accepted by the acceptance device, the state value in the storage device, and the state value in the (w−1)-bit shift register. | 12-29-2011 |
| 708205000 | Normalization | 18 |
| 20090006512 | NORMAL-BASIS TO CANONICAL-BASIS TRANSFORMATION FOR BINARY GALOIS-FIELDS GF(2m) - Basis conversion from normal form to canonical form is provided for both generic polynomials and special irreducible polynomials in the form of “all ones”, referred to as “all-ones-polynomials” (AOP). Generation and storing of large matrices is minimized by creating matrices on the fly, or by providing an alternate means of computing a result with minimal hardware extensions. | 01-01-2009 |
| 20090006511 | POLYNOMIAL-BASIS TO NORMAL-BASIS TRANSFORMATION FOR BINARY GALOIS-FIELDS GF(2m) - Basis conversion from polynomial-basis form to normal-basis form is provided for both generic polynomials and special irreducible polynomials in the form of “all ones”, referred to as “all-ones-polynomials” (AOP). Generation and storing of large matrices is minimized by creating matrices on the fly, or by providing an alternate means of computing a result with minimal hardware extensions. | 01-01-2009 |
| 20110219052 | DISCRETE FOURIER TRANSFORM IN AN INTEGRATED CIRCUIT DEVICE - Circuitry performing Discrete Fourier Transforms. The circuitry can be provided in a fixed logic device, or can be configured into a programmable integrated circuit device such as a programmable logic device. The circuitry includes a floating-point addition stage for adding mantissas of input values of the Discrete Fourier Transform operation, and a fixed-point stage for multiplying outputs of the floating-point addition stage by twiddle factors. The fixed-point stage includes memory for storing a plurality of sets of twiddle factors, each of those sets including copies of a respective twiddle factor shifted by different amounts, and circuitry for determining a difference between exponents of the outputs of the floating-point stage, and for using that difference as an index to select from among those copies of that respective twiddle factor in each of the sets. | 09-08-2011 |
| 20110231460 | APPARATUS AND METHOD FOR FLOATING-POINT FUSED MULTIPLY ADD - A fused multiply add (FMA) unit includes an alignment counter configured to calculate an alignment shift count, an aligner configured to align an addend input based on the alignment shift count and output an aligned addend, a multiplier configured to multiply a first multiplicand input and a second multiplicand input and output a product, an adder configured to add the aligned addend and the product and output a sum without determining the sign of the sum or complementing the sum, a normalizer configured to receive the sum directly from the adder and normalize the sum irrespective of the sign of the sum and output a normalized sum, and a rounder configured to round and complement-adjust the normalized sum and output a final mantissa. | 09-22-2011 |
| 20080215651 | Signal Separation Device, Signal Separation Method, Signal Separation Program and Recording Medium - A frequency domain transforming section | 09-04-2008 |
| 20100250635 | VECTOR MULTIPLICATION PROCESSING DEVICE, AND METHOD AND PROGRAM THEREOF - Intended is to reduce power consumption without requiring shift of an operand. A vector multiplication processing device comprising a speed-up circuit (a fixed point overflow foresight circuit | 09-30-2010 |
| 20100306290 | METHOD AND APPARATUS FOR SPATIO-TEMPORAL COMPRESSIVE SENSING - A method and apparatus for spatio-temporal compressive sensing, which allows accurate reconstruction of missing values in any digital information represented in matrix or tensor form, is disclosed. The method of embodiments comprises three main components: (i) a method for finding sparse, low-rank approximations of the data of interest that account for spatial and temporal properties of the data, (ii) a method for finding a refined approximation that better satisfies the measurement constraints while staying close to the low-rank approximations obtained by SRMF, and (iii) a method for combining global and local interpolation. The approach of embodiments also provides methods to perform common data analysis tasks, such as tomography, prediction, and anomaly detection, in a unified fashion. | 12-02-2010 |
| 20110072063 | Abstraction Apparatus for Processing Data - An abstraction apparatus for processing data is provided. The abstraction apparatus implements an abstraction layer that supports a variety of physical objects (hardware). The abstraction apparatus only manages information related to data denormalization and/or denormalization separately without embedding the information in the logical objects (software), thereby reducing overhead due to the normalization and/or denormalization. | 03-24-2011 |
| 20110040815 | Apparatus and method for performing fused multiply add floating point operation - A data processing apparatus is arranged to perform a fused multiply add operation. The apparatus | 02-17-2011 |
| 20110153699 | 16-POINT TRANSFORM FOR MEDIA DATA CODING - In general, techniques are described for implementing a 16-point inverse discrete cosine transform (IDCT) that is capable of applying multiple IDCTs of different sizes. For example, an apparatus comprising a 16-point inverse discrete cosine transform of type II (IDCT-II) unit may implement the techniques of this disclosure. The 16-point IDCT-II unit performs these IDCTs-II of different sizes to transform data from a spatial to a frequency domain. The 16-point IDCT-II unit includes an 8-point IDCT-II unit that performs one of the IDCTs-II of size 8 and a first 4-point IDCT-II unit that performs one of the IDCTs-II of size 4. The 8-point IDCT-II unit includes the first 4-point DCT-II unit. The 16-point IDCT-II unit also comprises an inverse 8-point DCT-IV unit that includes a second 4-point IDCT-II unit and a third 4-point IDCT-II unit. Each of the second and third 4-point IDCT-II units performs one of the IDCTs-II of size 4. | 06-23-2011 |
| 20090300087 | Computation processor, information processor, and computing method - A computation processor outputs whether a carry-out is generated, by incrementing a result of computation by 1, during rounding of the result of the computation. The computation processor includes a computing unit that performs the computation; a shift amount calculating unit that calculates a shift amount of the result of the computation; a normalizing unit that performs normalization of the result of the computation, by using the shift amount; a predicting unit that, when the result of the computation is shifted by an amount equal to or more than a predetermined shift amount by using the shift amount, predicts whether each of bits in a predetermined region of a shift result is 1, in parallel with the normalization; and a detecting unit that detects a generation of the carry-out, by receiving a normalized result from the normalizing unit and a predicted result from the predicting unit. | 12-03-2009 |
| 20120011182 | DECIMAL FLOATING-POINT SQUARE-ROOT UNIT USING NEWTON-RAPHSON ITERATIONS - A system including: an input processing unit configured to: extract a significant and a bias exponent from the decimal floating-point radicand; and calculate a normalized significand; a square root unit configured to: calculate, using a FMA unit, a refined reciprocal square-root of the normalized significand; calculate an unrounded square-root of the normalized significand by multiplying the refined reciprocal square-root by the normalized significand; and generate a rounded square-root based on a first difference between the normalized significand and a square of the unrounded square-root; a master control unit operatively connected to the input processing hardware unit and the square-root hardware unit and configured to calculate an exponent for the unrounded square-root based on the number of leading zeros and a precision of the decimal floating-point radicand; and an output formulation unit configured to output a decimal floating-point square-root of the radicand based on the rounded square-root and the exponent. | 01-12-2012 |
| 20120124117 | FUSED MULTIPLY-ADD APPARATUS AND METHOD - A fixed multiply-add (FMA) apparatus and method are provided. The FMA apparatus includes a partial product generator configured to generate a partial sum and a partial carry, a carry save adder configured to generate a partial sum having a first bit size and a partial carry having the first bit size by adding the partial sum and the partial carry to least significant bits (LSBs) of the mantissa of a third floating-point number, a carry select adder configured to generate a mantissa having a second bit size by adding the first bit-size partial sum and the first bit-size partial carry to most significant bits (MSBs) of the third floating-point number, and a selector configured to transmit the first bit-size partial sum and the first bit-size partial carry to the carry save adder or the carry select adder according to whether the mantissa of the third floating-point number is zero. | 05-17-2012 |
| 20100205234 | METHOD AND APPARATUS FOR DETECTING SIGNAL USING CYCLO-STATIONARY CHARACTERISITICS - A method and apparatus for detecting a signal using a cyclo-stationary characteristic value is provided. A method of detecting a signal using a cyclo-stationary characteristic value includes: calculating cyclo-stationary characteristic values with respect to a cyclic frequency domain of an input signal; multiplying the calculated cyclo-stationary characteristic values with each other; and detecting the signal from the input signal based on the result of the multiplication. | 08-12-2010 |
| 20100205233 | REFLECTIONLESS FILTERS - Reflectionless low-pass, high-pass, band-pass, and band-stop filters, as well as a method for designing such filters is disclosed. The filters function by absorbing the stop-band portion of the spectrum rather than reflecting it back to the source, which has significant advantages in many different applications. | 08-12-2010 |
| 20100174764 | REUSE OF ROUNDER FOR FIXED CONVERSION OF LOG INSTRUCTIONS - A method for converting a signed fixed point number into a floating point number that includes reading an input number corresponding to a signed fixed point number to be converted, determining whether the input number is less than zero, setting a sign bit based upon whether the input number is less than zero or greater than or equal to zero, computing a first intermediate result by exclusive-ORing the input number with the sign bit, computing leading zeros of the first intermediate result, padding the first intermediate result based upon the sign bit, computing a second intermediate result by shifting the padded first intermediate result to the left by the leading zeros, computing an exponent portion and a fraction portion, conditionally incrementing the fraction portion based on the sign bit, correcting the exponent portion and the fraction portion if the incremented fraction portion overflows, and returning the floating point number. | 07-08-2010 |
| 20120173597 | LEADING SIGN DIGIT PREDICTOR FOR FLOATING POINT NEAR SUBTRACTOR - An apparatus for predicting leading sign digits in a negative difference includes a comparator that determines a larger of two numbers that differ in magnitude by not more than one digit position. The larger of the two numbers is designated as the subtrahend and the smaller as the minuend. Wires and logic align the subtrahend relative to the minuend by the not more than one digit position and invert the aligned subtrahend. A plurality of NAND gates performs a Boolean NAND function of corresponding digits of the minuend and the aligned inverted subtrahend to produce a prediction string of bits. A zero value is assigned to the most significant bit of the prediction string. A string of leading zeros of the prediction string predicts a corresponding string of leading sign digits of a negative difference of the minuend and aligned subtrahend. | 07-05-2012 |
| 20110320512 | Decimal Floating Point Mechanism and Process of Multiplication without Resultant Leading Zero Detection - A decimal multiplication mechanism for fixed and floating point computation in a computer having a coefficient mechanism without resulting leading zero detection (LZD) and process which assumes that the final product will be M+N digits in length and performs all calculations based on this assumption. Least significant digits that would be truncated are no longer stored, but retained as sticky information which is used to finalize the result product. Once the computation of the product is complete, a final check based on the examination of key bits observed during partial product accumulation is used to determine if the final product is truly M+N digits in length, or M+N−1 digits. If the latter is true, then corrective final product shifting is employed to obtain the proper result. This eliminates the need for dedicated leading zero detection hardware used to determine the number of significant digits in the final product. The corrective final product shifting also incorporates adjustments to the coefficient of the product when the product's exponent is at its extremes and the final product must be brought to be within the precision and range of a given format. | 12-29-2011 |
