Class / Patent application number | Description | Number of patent applications / Date published |
708201000 | Absolute value or magnitude | 46 |
20080235310 | Difference degree evaluation device, difference degree evaluation method and program product - A difference degree evaluation device includes a signal acquisition unit which acquires at least two signals which are objects of matching, a memory unit which stores one of the two signals, which are acquired by the signal acquisition unit, as a reference signal, and stores the other of the two signals as an object signal, a sample extraction unit which extracts sample points in a predetermined block from the reference signal that is stored in the memory unit, and extracts sample points corresponding to the sample points of the reference signal from the object signal, and an arithmetic process unit which finds absolute difference values between the sample points of the reference signal and the sample points of the object signal, which are extracted by the sample extraction unit, and calculates a maximum value of the absolute difference values as an evaluation value. | 09-25-2008 |
20080250090 | Adaptive filter device and method for determining filter coefficients - An adaptive filter device, including a finite impulse response (FIR) filter which is based on filter coefficients, which are determined based on a predetermined iterative adaptation algorithm for determining filter coefficients of an adaptive filter, wherein, in at least one iteration step of said predetermined iterative adaptation algorithm a sum value is determined, wherein each summand of said sum value depends on one of said filter coefficients, and, if said sum value is above a predetermined threshold, the filter coefficients are modified. | 10-09-2008 |
20080313248 | Arrangement and method for cross-monitoring of data - An arrangement for cross monitoring two independent signals. The arrangement a calculator configured to calculate a value depending upon a signal value, a drift value and a feedback value, and a determining unit configured to determine a larger of the calculated value and a first predetermined value. The arrangement also includes a comparing unit configured to compared the determine larger value with a second predetermined value and a delaying unit configured to delay the determined larger value and change status of the larger value to become an updated feedback value to be provided to the calculator. The arrangement is characterized in that the signal value includes information about an absolute value of a difference between the two independent generated signals. | 12-18-2008 |
20080320065 | Arithmetic processing apparatus and arithmetic processing method - In an arithmetic processing apparatus, a dividing unit divides a second bit string into a low-order bit part having a bit width equal to a first bit width and a high-order bit part which is higher than the low-order bit part, a first arithmetic unit performs arithmetic operations for a carry to and a borrow from the high-order bit part; and a second arithmetic unit performs addition of absolute values of the low-order bit part and the first bit string. Finally, a selecting unit selects an output of the first arithmetic unit from among an arithmetic operation result with a carry, an arithmetic operation result with a borrow, and the high-order bit part itself, according to information about the high-order bit part, sign information of the first bit string and the second bit string, and an intermediate result of the addition of the absolute values by the second arithmetic unit. | 12-25-2008 |
20090063598 | APPARATUS AND METHOD FOR CALCULATING AND VISUALIZING TARGETS - A computer-readable medium includes executable instructions to define a target value, define an achievement boundary range, define specific values for the achievement boundary range, and combine the target value, achievement boundary range, and specific values associated with the achievement boundary range to form an absolute target metric object. | 03-05-2009 |
20090063599 | FAST COMPUTATION OF PRODUCTS BY DYADIC FRACTIONS WITH SIGN-SYMMETRIC ROUNDING ERRORS - A product of an integer value and an irrational value may be determined by a sign-symmetric algorithm. A process may determine possible algorithms that minimize metrics such as mean asymmetry, mean error, variance of error, and magnitude of error. Given an integer variable x and rational dyadic constants that approximate the irrational fraction, a series of intermediate values may be produced that are sign-symmetric. The intermediate values may include a sequence of addition, subtraction and right shift operations the when summed together approximate the product of the integer and irrational value. Other operations, such as additions or subtractions of 0s or shifts by 0 bits may be removed. | 03-05-2009 |
20090077143 | Nonlinear filtering and deblocking applications utilizing SIMD sign and absolute value operations - Method, apparatus, and program means for nonlinear filtering and deblocking applications utilizing SIMD sign and absolute value operations. The method of one embodiment comprises receiving first data for a first block and second data for a second block. The first data and said second data are comprised of a plurality of rows and columns of pixel data. A block boundary between the first block and the second block is characterized. A correction factor for a deblocking algorithm is calculated with a first instruction for a sign operation that multiplies and with a second instruction for an absolute value operation. Data for pixels located along said block boundary between the first and second block are corrected. | 03-19-2009 |
20090112955 | Apparatus and method for performing magnitude detection of arthimetic operations - An apparatus and method is provided comprising processing circuitry, one or more registers and control circuitry. The control circuitry is configured such that it is responsive to a combined magnitude-detecting arithmetic instruction to control the processing circuitry to perform an arithmetic operation on at least one data element and further to perform a magnitude-detecting operation. The magnitude-detecting operation calculates a magnitude-indicating result providing an indication of a position of a most-significant bit of a magnitude of a result of the arithmetic operation irrespective of whether the most-significant bit position exceeds the data element width of the at least one data element. | 04-30-2009 |
20090177723 | METHOD AND APPARATUS FOR APPROXIMATING AN UPPER-BOUND LIMIT FOR AN ABSOLUTE VALUE OF A COMPLEX NUMBER OR NORM OF A TWO-ELEMENT VECTOR - A method for approximating an upper bound limit for the absolute value of a complex number or the norm of a two-element vector is disclosed. An upper bound approximation algorithm is used to minimize software implementation efforts and make the hardware implementation less expensive. The hardware implementation of the upper bound approximation algorithm only requires a multiplier element and an adder element. Therefore, this algorithm can be implemented anywhere in a digital signal processing apparatus without increasing cost significantly. Moreover, the hardware employing the present invention can be implemented in a pipeline architecture configuration to achieve a real time function in digital audio or digital video applications. | 07-09-2009 |
20100262639 | DIGITAL DATA PROCESSOR - A digital data processor which receives an N-bit input signal from a data source and converts the N-bit input signal into an M-bit output signal, the M-bit being larger than the N-bit. The digital data processor includes: an weighted addition circuit which is operable to perform weighted addition on at least the input signal and a signal being time-shifted with respect to the input signal and output as a weighted added input signal; an arithmetic shift circuit which is operable to perform an arithmetic rightward shift operation on the weighted added input signal for a predetermined number of shifts and output as a processed input signal; a bit extension circuit which is operable to attach a predetermined bits to an LSD side of the input signal to generate an intermediate signal of M bits; and an addition circuit which is operable to perform addition of the intermediate signal and the processed input signal so as to generate the M-bit output signal. | 10-14-2010 |
20100332572 | EXPLOITATION OF TOPOLOGICAL CATEGORIZATION OF CHAOTIC AND FRACTAL FUNCTIONS, INCLUDING FIELD LINE CALCULATIONS - A topological categorization method, based on inclusive intervals, provides a general method of analyzing escape topologies for discrete dynamic systems, in complex and higher dimensions, including the calculation of both potential for complex and hypercomplex and field lines for complex iterations | 12-30-2010 |
20110010405 | Compression of non-dyadic sensor data organized within a non-dyadic hierarchy - Sensor data is received from one or more sensors. The sensor data is organized within a hierarchy. The sensor data is organized within a hierarchy that is non-dyadic. A processor of a computing device generates a discrete wavelet transform, based on the sensor data and based on the hierarchy of the sensor data, to compress the sensor data. The sensor data, as has been compressed via generation of the discrete wavelet transform, is processed. | 01-13-2011 |
20110022646 | PROCESSOR, CONTROL METHOD OF PROCESSOR, AND COMPUTER READABLE STORAGE MEDIUM STORING PROCESSING PROGRAM - A processor for dividing by calculating repeatedly an n-bit width partial quotient includes, a dividend zero count value counter that counts a dividend zero count value, a divisor zero count value counter that counts a divisor zero count value, a correction value calculator that calculates a correction value to a loop count value, a correction loop count value calculator that calculates a correction loop count value, a dividend shift unit that shifts leftward an absolute value of the dividend by the dividend zero count value and shifts rightward the leftward-shifted absolute value of the dividend by the correction value, a divisor shift unit that shifts leftward an absolute value of the divisor by the divisor zero count value, and a division loop operation unit that divides based on an output value from the dividend shift unit, an output value from the divisor shift unit, and the correction loop count value. | 01-27-2011 |
20110022647 | APPARATUS FOR CALCULATING ABSOLUTE DIFFERENCE - Provided is an apparatus for calculating an absolute difference capable of efficiently performing an absolute difference using an adder. The apparatus for calculating an absolute difference includes a comparator comparing values of two integers, first and second selectors each selecting and outputting one of the two integers according to the comparison results of the comparator, an inverter complementing the result value selected by the second selector; and an adder adding up the result value selected by the first selector, the value complemented by the inverter, and 1. | 01-27-2011 |
20110099214 | SYSTEM AND METHOD OF USING COMMON ADDER CIRCUITRY FOR BOTH A HORIZONTAL MINIMUM INSTRUCTION AND A SUM OF ABSOLUTE DIFFERENCES INSTRUCTION - A system which uses common adder circuitry to perform either one of a horizontal minimum instruction and a sum of absolute differences instruction including multiple adders, a sum circuit, a compare circuit, and a routing circuit. The input operands include multiple digital values which are delivered by the routing circuit to the adders depending upon which instruction is indicated. Each adder determines a difference between a pair of digital values. The differences are grouped and summed together by the sum circuit for the sum of absolute differences instruction. The adders are paired together for the horizontal minimum instruction, in which each pair provides carry and propagate outputs. The upper portions of a pair of digital values are compared by the upper adder and the lower portions are compared by the lower adder, and the carry and propagate outputs are collectively used to determine the minimum value. | 04-28-2011 |
20110137968 | METHOD FOR DETERMINING THE POSITION OF IMPACTS - A method for determining the position of impacts on an object comprising two acoustic sensors, and N active areas of said object, comprises the steps of: (a) receiving two acoustic signals S | 06-09-2011 |
20110302229 | CALCULATING LARGE PRECISION COMMON LOGARITHMS - Techniques are disclosed for calculating large precision common logarithms. A common logarithm may be calculated using addition and/or subtraction of known logarithm values. Embodiments of the invention permit calculation of common logarithms of real numbers stored within character arrays, where each element of the array corresponds to a digit in the real number. | 12-08-2011 |
20110302230 | LOW DELAY MODULATED FILTER BANK - The document relates to modulated sub-sampled digital filter banks, as well as to methods and systems for the design of such filter banks. In particular, the present document proposes a method and apparatus for the improvement of low delay modulated digital filter banks. The method employs modulation of an asymmetric low-pass prototype filter and a new method for optimizing the coefficients of this filter. Further, a specific design for a (64) channel filter bank using a prototype filter length of (640) coefficients and a system delay of (319) samples is given. The method substantially reduces artifacts due to aliasing emerging from independent modifications of subband signals, for example when using a filter bank as a spectral equalizer. The method is preferably implemented in software, running on a standard PC or a digital signal processor (DSP), but can also be hardcoded on a custom chip. The method offers improvements for various types of digital equalizers, adaptive filters, multiband companders and spectral envelope adjusting filterbanks used in high frequency reconstruction (HFR) or parametric stereo systems. | 12-08-2011 |
20120166501 | COMPUTATION OF JACOBIAN LOGARITHM OPERATION - An apparatus generally having a first circuit, a second circuit and a third circuit is disclosed. The first circuit may be configured to generate a plurality of first signals carrying (i) a maximum value among a plurality of input values and (ii) a plurality of difference values based on the input values. The second circuit may be configured to generate a plurality of second signals carrying a plurality of intermediate values based on the difference values. The intermediate values are generally respective powers of two. The third circuit may be configured to generate a third signal carrying an output value by adding the maximum value and the intermediate values. The output value may be a Jacobian logarithm computation of the input values. | 06-28-2012 |
20130080489 | SYSTEMS AND METHODS FOR DETERMINING RESPIRATION INFORMATION FROM A PHOTOPLETHYSMOGRAPH - A patient monitoring system may receive a photoplethysmograph (PPG) signal including samples of a pulse waveform. A plurality of morphology metric signals may be generated from the PPG signal. The system may generate an autocorrelation sequence for each of the morphology metric signals. An autocorrelation metric may be generated from each of the autocorrelation sequences and may represent the regularity or periodicity of the morphology metric signal. The autocorrelation sequences may be combined to generate a combined autocorrelation sequence, with the weighting of the autocorrelation sequences based on the autocorrelation metric. The combined autocorrelation sequence may be used to determine physiological information. | 03-28-2013 |
20130232182 | SIMD SIGN OPERATION - Method, apparatus, and program means for nonlinear filtering and deblocking applications utilizing SIMD sign and absolute value operations. The method of one embodiment comprises receiving first data for a first block and second data for a second block. The first data and said second data are comprised of a plurality of rows and columns of pixel data. A block boundary between the first block and the second block is characterized. A correction factor for a deblocking algorithm is calculated with a first instruction for a sign operation that multiplies and with a second instruction for an absolute value operation. Data for pixels located along said block boundary between the first and second block are corrected. | 09-05-2013 |
20130238680 | DECIMAL ABSOLUTE VALUE ADDER - A decimal absolute value adder includes a first circuit adding two operands for a first result; a second circuit adding the two operands to 10 for a second result; a third circuit adding the two operands to 6 for a third result; a fourth circuit adding the two operands to 1 for a fourth result; a fifth circuit adding the two operands to 11 for a fifth result; a sixth circuit adding the two operands to 7 for a sixth result; and a selection circuit selecting the first, second, fourth or fifth result when adding two numbers of identical signs or adding two numbers of different signs resulting in a non-negative result, and selecting a 1's complement of the first, third, fourth or sixth result when adding two numbers of different signs resulting in a negative result. | 09-12-2013 |
20130282777 | System and Method for a Floating-Point Format for Digital Signal Processors - An embodiment of a system and method for performing a numerical operation on input data in a hybrid floating-point format includes representing input data as a sign bit, exponent bits, and mantissa bits. The exponent bits are represented as an unsigned integer including an exponent bias, and a signed numerical value of zero is represented as a first reserved combination of the mantissa bits and the exponent bits. Each of all other combinations of the mantissa bits and the exponent bits represents a real finite non-zero number. The mantissa bits are operated on with a “one” bit before a radix point for the all other combinations of the mantissa bits and the exponent bits. | 10-24-2013 |
20140019500 | METHODS AND APPARATUS FOR MATRIX DECOMPOSITIONS IN PROGRAMMABLE LOGIC DEVICES - A processor is adapted for performing a QR-decomposition. The processor has a program memory, a program controller, connected to the program memory to receive program instructions, and at least one processing unit. The processing unit includes a CORDIC calculation block, and has a distributed memory structure, with separate memory blocks for storing respective parameter values. | 01-16-2014 |
20140067889 | DATAPATH CIRCUIT FOR DIGITAL SIGNAL PROCESSORS - A datapath circuit may include a digital multiply and accumulate circuit (MAC) and a digital hardware calculator for parallel computation. The digital hardware calculator and the MAC may be coupled to an input memory element for receipt of input operands. The MAC may include a digital multiplier structure with partial product generators coupled to an adder to multiply a first and second input operands and generate a multiplication result. The digital hardware calculator may include a first look-up table coupled between a calculator input and a calculator output register. The first look-up table may include table entry values mapped to corresponding math function results in accordance with a first predetermined mathematical function. The digital hardware calculator may be configured to calculate, based on the first look-up table, a computationally hard mathematical function such as a logarithm function, an exponential function, a division function and a square root function. | 03-06-2014 |
20140101214 | ARITHMETIC OPERATION IN A DATA PROCESSING SYSTEM - An arithmetic operation in a data processing unit, preferably by iterative digit accumulations, is proposed. An approximate result of the arithmetic operation is computed iteratively. Concurrently at least two supplementary values of the approximate result of the arithmetic operation are computed, and the final result selected from one of the values of the approximate result and the at least two supplementary values of the arithmetic operation depending on the results of the last iteration step. | 04-10-2014 |
20140122551 | ARITHMETIC LOGIC UNIT - An arithmetic logic unit (ALU) including a first routing grid connected to multiple data lanes to drive first data to the data lanes. A second routing grid is connected to the data lanes to drive second data to the data lanes. Each of the data lanes include multiple, e.g. N, functional units with first inputs from the first routing grid and second inputs from the second routing grid. The functional units compute pairwise a function of the respective first data on the respective first inputs and the respective second data on the respective second inputs. Each of the data lanes include a reduction unit with inputs adapted to receive K′ bits per word from the functional units. The reduction unit is configured to perform a reduction operation configured to output an output result having a reduced number J′ bits per word, wherein J′ is less than N multiplied by K′. | 05-01-2014 |
20140172932 | DEVICE AND METHOD FOR CALCULATING ABSOLUTE AMOUNT OF DISPLACEMENT, AND METHOD FOR SAME - Some embodiments address a problem of detecting the absolute amount of displacement of a moving body. In various embodiments, the multi-turn absolute angle of rotation of a main shaft is calculated from a rotation angle detected by an angle sensor joined to the main shaft and a countershaft. The rotation of a main shaft ( | 06-19-2014 |
20140188961 | Vectorization Of Collapsed Multi-Nested Loops - In an embodiment a method of vectorizing a collapsed multi-nested loop includes executing, in a vector unit of a processor, the collapsed loop to obtain a vector of offsets, including for each of a plurality of iterations, calculating a scalar offset into a multi-dimensional data structure, storing the scalar offset in a data element of a first vector register, and updating a loop counter value of a multi-dimensional loop counter vector. In turn, a plurality of data elements are loaded from the multi-dimensional data structure using a base value and indexes from the vector of offsets, at least one computation is performed on the loaded plurality of data elements to obtain a plurality of results, and the plurality of results are stored into the multi-dimensional data structure using the base value and the indexes from the vector of offsets. Other embodiments are described and claimed. | 07-03-2014 |
20140207836 | Vector Comparator System for Finding a Peak Number - A comparator ( | 07-24-2014 |
20140258352 | SPACE DILATING TWO-WAY VARIABLE SELECTION - A method of identifying a set of parameters representative of a data set is provided. An eigen decomposition of a covariance matrix is calculated to form a decomposed matrix and an eigenvalue vector. The covariance matrix is calculated for a matrix of data including a plurality of data values for each of a plurality of parameters. The decomposed matrix includes a number of eigenvectors equal to a number of the plurality of parameters with each eigenvector including a coefficient for each parameter. The eigenvalue vector includes an eigenvalue defined for each eigenvector. A first matrix is created by rank ordering the coefficient within each parameter of the plurality of parameters for each of the plurality of parameters. A score is determined for each parameter using the created first matrix and the eigenvalue vector. A parameter set is identified based on the determined score for each parameter. | 09-11-2014 |
20140280405 | CONVERSION OF A NORMALIZED N-BIT VALUE INTO A NORMALIZED M-BIT VALUE - A normalized n-bit value is converted into a normalized m-bit value in accordance with a predetermined rounding mode. An initial m-bit value is determined, where the bits of the initial m-bit value are equal to the m most significant bits of a concatenation of one or more copies of a group of one or more bits derived from the normalized n-bit value. An output state is selected based on bits of the normalized n-bit value and in accordance with the predetermined rounding mode. The output state indicates how the normalized m-bit value is to be determined from the initial m-bit value. In accordance with the selected output state, the normalized m-bit value is determined to be equal to one of a plurality of candidate m-bit values, wherein the plurality of candidate m-bit values consists of the initial m-bit value and at least one of: (i) the initial m-bit value incremented by one, and (ii) the initial m-bit value decremented by one. | 09-18-2014 |
20140280406 | SYSTEMS AND METHODS FOR ESTIMATING UNCERTAINTY - A computer-implemented method includes receiving instructions to execute an analytic, wherein the instructions comprise one or more analytic inputs and a corresponding one or more uncertainty values, and wherein the analytic defines a continuous, monotonic mathematical function. The method includes executing the analytic using the one or more analytic inputs to determine one or more analytic outputs. The method also includes executing an uncertainty calculation to estimate one or more uncertainty outputs corresponding to the one or more analytic outputs, based, at least in part, on the one or more analytic inputs and the corresponding one or more uncertainty values. The method further includes providing the one or more analytic outputs as well as the corresponding one or more uncertainty outputs. | 09-18-2014 |
20140297703 | SIGNAL RECONSTRUCTION USING TOTAL-VARIATION PRIMAL-DUAL HYBRID GRADIENT (TV-PDHG) ALGORITHM - A mechanism for reconstructing a signal (e.g., an image) based on a vector s, which includes measurements of the signal. The measurements have been acquired using at least a portion of a measurement vector set represented by a matrix H. Each of the measurements corresponds to a respective row of the matrix H. (For example, each of the measurements may correspond to an inner product between the signal and a respective row of the matrix product HD, wherein D is a generalized permutation matrix.) A total-variation primal-dual hybrid gradient (TV-PDHG) algorithm is executed based on data including the matrix H and the vector s, to determine an estimate for the signal. The TV-PDHG algorithm is implemented in fixed-point arithmetic. | 10-02-2014 |
20140358978 | VECTOR QUANTIZATION WITH NON-UNIFORM DISTRIBUTIONS - Systems and methods are described for encoding quantized vector parameters in a bitstream are described. An exemplary method may include receiving a vector of integers used in a data compression codebook, the sum of the integers equaling a pulse sum. An initial expected magnitude may be determined for a first integer, the initial expected magnitude being based on the pulse sum, a distribution parameter, and a value corresponding to a number of integers in the vector. The actual magnitude of the first integer may be encoded based on the initial expected magnitude of the first integer. The pulse sum may be adjusted using the encoded actual magnitude. Also, the value corresponding to the number of integers in the vector may be reduced by one. Expected magnitudes for each of the remaining integers of the vector may then be calculated recursively. | 12-04-2014 |
20150012577 | SIGNAL PROCESSING DEVICE AND METHOD - The present invention relates to a signal processing device and method. The device receives, from a sensor which measures a physical quantity applied thereto and outputs an accumulated or integrated value of the physical quantity as an M-bit digital value, the digital value, and, when a difference between the physical quantities at two successive data acquisition times lies within a predetermined range and an absolute value of a digital counter increment is greater than 2 | 01-08-2015 |
20150293884 | METHOD TO COMPUTE THE BARYCENTER OF A SET OF HISTOGRAMS - The object of the present invention is to provide novel methods to carry out clustering in huge datasets using generalized formulations. We propose (1) an efficient and novel method to compute the barycenter (or mean) of a set of histograms under the optimal transport distance; (2) as an extension of the first method, an efficient and novel method to cluster data sets of vectors R | 10-15-2015 |
20150370536 | FORMATTING FLOATING POINT NUMBERS - Flexible high-speed generation and formatting of application-specified strings in floating point and related formats is available through table-based base conversion which may be integrated with custom formatting, and through printf-style functionality based on separate control string parsing and specialized format command sequence execution. | 12-24-2015 |
20160004664 | BINARY TENSOR FACTORIZATION - In factorization of binary matrices or tensors, training algorithms usually scale linearly with the number of training examples. For very unbalanced learning problems, the number of non-zero training examples can be much smaller than the number of zeros in the full dataset. For some problems where the squared norm can be efficiently computed, the training time complexity can be reduced. A method herein receives a binary tensor defined by matrices comprising elements in a database. A processing device determines an upper bound for non-quadratic losses associated with factorization of the binary tensor. The upper bound is based on a variation parameter. The processing device performs factorization of the binary tensor by alternately minimizing the upper bound with respect to the variation parameter and minimizing the upper bound with respect to the elements of the matrices using a gradient descent method. | 01-07-2016 |
20160012013 | SCALED JACOBIAN VECTORS AND SKETCHING CONSTRAINTS | 01-14-2016 |
20160034256 | FAST INTEGER DIVISION - Embodiments disclosed pertain to apparatuses, systems, and methods for fast integer division. Disclosed embodiments pertain to an integer divide circuit to divide a dividend by a divisor and produce multiple quotient bits per iteration. In some embodiments, the fast integer divider may include a partial remainder register initialized with the dividend. Further, the fast integer divider circuit may include a plurality of adders, where each adder subtracts a multiple of the divisor from the current value in the partial remainder register. A logic block coupled to each of the adders, determines multiple quotient bits at each iteration based on the subtraction results. | 02-04-2016 |
20160092165 | MACHINE INSTRUCTIONS FOR CONVERTING FROM DECIMAL FLOATING POINT FORMAT TO PACKED DECIMAL FORMAT - Embodiments relate to converting data from a decimal floating point format to a packed decimal format by executing a machine instruction. A method of executing the machine instruction is provided. The method reads data in a decimal floating point format from one or more registers of a processor that is communicatively coupled to a memory. The method converts the data in the decimal floating point format into a packed decimal format. The method writes the data converted into the packed decimal format to the memory. | 03-31-2016 |
20160098248 | DECIMAL AND BINARY FLOATING POINT ROUNDING - Arithmetic logic circuitry is provided for performing a floating point arithmetic add/subtract operation on first and second floating point numbers. The method includes: generating a guard digit for the first or second number by transforming the first and second numbers by a compressing function; determining a result depending on the arithmetic operation, a sum of the transformed floating point numbers, and first and second differences of the transformed floating point numbers, and determining a corresponding result plus one by additionally adding a value of one to the result; generating injection values for rounding the final result; generating injection carry values based on the transformed first and second numbers and the injection values; and selecting the final result from the result, the result plus one, and a least significant digit, based on the injection carry values and the end around carry signals. | 04-07-2016 |
20160098249 | DECIMAL AND BINARY FLOATING POINT ARITHMETIC CALCULATIONS - Logic is provided for performing decimal and binary floating point arithmetic calculations on first and second operands. The method includes: receiving the first and second operands in packed format; unpacking the first and second operands; swapping the first operand to a fourth operand and the second operand to a third operand, if an exponent of the first operand is less than an exponent of the second operand, otherwise storing the first operand to the third operand and the second operand to the fourth operand; aligning the third operand and the fourth operands based on the exponent difference of the third and fourth operand and a number of leading zeroes of the third operand; performing an add/subtract operation on the aligned third and fourth operands with normalizing and rounding between the operands; and packing the result obtained from the add/subtract. | 04-07-2016 |
20160179469 | APPARATUS AND METHOD FOR PERFORMING ABSOLUTE DIFFERENCE OPERATION | 06-23-2016 |
20190147013 | APPARATUS AND METHOD OF LOW COMPLEXITY OPTIMIZATION SOLVER FOR PATH SMOOTHING WITH CONSTRAINT VARIATION | 05-16-2019 |