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Circuit simulation

Subclass of:

703 - Data processing: structural design, modeling, simulation, and emulation

703013000 - SIMULATING ELECTRONIC DEVICE OR ELECTRICAL SYSTEM

Patent class list (only not empty are listed)

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Class / Patent application numberDescriptionNumber of patent applications / Date published
703015000 Including logic 86
Entries
DocumentTitleDate
20090112555Design Structure For A Duty Cycle Measurement Apparatus That Operates In A Calibration Mode And A Test Mode - A design structure for an on-chip duty cycle measurement system may be embodied in a machine readable medium for designing, manufacturing or testing an integrated circuit. The design structure may embody an apparatus that measures the duty cycle of a reference clock signal that a clock circuit supplies to a duty cycle measurement (DCM) circuit. The design structure may specify that the DCM circuit includes a capacitor driven by a charge pump and that a reference clock signal drives the charge pump. The design structure may specify that the clock circuit varies the duty cycle of the reference clock signal among a number of known duty cycle values. The design structure may specify that the DCM circuit stores resultant capacitor voltage values corresponding to each of the known duty cycle values in a data store. The DCM circuit may apply a test clock signal having an unknown duty cycle to the capacitor via the charge pump, thus charging the capacitor to a new voltage value that corresponds to the duty cycle of the test clock signal. The design structure may specify that control software accesses the data store to determine the duty cycle to which the test clock signal corresponds.04-30-2009
20100057425AUTOMATICALLY CREATING MANUFACTURING TEST RULES PERTAINING TO AN ELECTRONIC COMPONENT - A system for creating manufacturing test rules. Stimuli for an electronic design are generated automatically by a stimuli generator. The stimuli generator takes into account certain limitations of the design when automatically generating the manufacturing test rules. The design is tested by a testbench using the stimuli. A simulation log for the design is generated by the testbench. The simulation log is then processed by a simulation log processor. An HDL representation of the design is generated by the simulation log processor using the processed simulation log. A gate-level version of the design is generated by a synthesis tool using the HDL representation of the design. The gate-level version of the design is further processed by the synthesis tool to make any necessary modifications. Then, the gate-level version of the design is outputted as the final manufacturing test rule. Thus, creating manufacturing test rules can be completely automated.03-04-2010
20110191093SYSTEM AND METHOD OF GENERATING EQUATION-LEVEL DIAGNOSTIC ERROR MESSAGES FOR USE IN CIRCUIT SIMULATION - A mechanism for providing equation-level diagnostic error messages for system models undergoing circuit simulations is discussed. The components in a model of a system being simulated are converted into multiple numerical equations where each equation corresponds to a component in the system being simulated or a topology equation for the system model. Each numerical equation is numerically analyzed in order to identify illegal configurations in the system. Upon detection of an error, an error message listing the components associated with the illegal configuration is generated for the user.08-04-2011
20090063120System for Performing a Co-Simulation and/or Emulation of Hardware and Software - The present invention relates to a system for performing a co-simulation and/or emulation of hardware and software. The system includes a hardware simulator with an integrated hardware model, a hardware and/or software environment for controlling the hardware simulator and performing a software simulation and/or a direct software application, at least one synchronization facility within the hardware model for indicating a request from the hardware and/or software environment, a receiver for setting the synchronization facility into a predetermined state, and a controller for switching the hardware simulator between a free-running state and a request-handling state.03-05-2009
20090192776CHARGE-BASED CIRCUIT ANALYSIS - A solution for analyzing a circuit using initial charge information is provided. In particular, one or more nodes in a design for the circuit is initialized with an initial charge. The charge can comprise a non-equilibrium charge, thereby simulating the history effect, the impact of a charged particle, electro-static discharge (ESD), and/or the like. Operation of the circuit is then simulated over a set of input cycles based on the initial charge(s). To this extent, the non-equilibrium initial condition solution enables the state of the circuit to be controlled and solves the initial system based on these values. This capability is very useful to condition the circuit at a worst-case, best-case, and/or the like, status. Further, in one embodiment of the invention, a set of equations are provided to implement the non-equilibrium initial charge analysis, which provide a more efficient initialization of the circuit than current solutions.07-30-2009
20090144041System and method for simulating a semiconductor wafer prober and a class memory test handler - A method runs a simulation. The method comprises receiving a selection of a device. The device is one of a prober used in wafer testing and a handler used in package testing. The method comprises receiving at least one parameter for a set of parameters for the simulation. The method comprises running the simulation by executing commands to be performed as if the device were present. A controller supplies the set of commands. Results from the simulation indicate a performance of the controller.06-04-2009
20080255820Behavioral modeling of high speed differential signals based on physical characteristics - A method of modeling the output drivers in an integrated circuit, for example a serializer/deserializer circuit, is provided. In accordance with embodiments of the invention, at least one parameter of the circuit is physically measured and a behavioral model utilizing that parameter is constructed. The behavioral model can then be utilized to predict the behavior of the integrated circuit output drivers.10-16-2008
20100076741SYSTEM, METHOD AND PROGRAM FOR DETERMINING WORST CONDITION OF CIRCUIT OPERATION - A system for determining a worst condition, wherein, in a model for which one or more parameters included in a model function that simulates a circuit performance index are random variable(s) to simulate the circuit performance index and fluctuations thereof, the parameter(s) for which the circuit performance index assumes a maximum or minimum value that is to be assumed from the viewpoint of designing is determined as the worst condition; the system comprises a worst condition search unit that searches for a point, having a maximum or minimum value of the circuit performance index, on an equi-probability surface corresponding to a preset good product ration within a space defined by the parameter(s); the point thus searched being determined as the worst condition.03-25-2010
20120245915SEMICONDUCTOR INTEGRATED CIRCUIT SIMULATION APPARATUS AND SIMULATION METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT - According to an embodiment, a simulation apparatus has a bus architecture information acquiring module configured to acquire bus architecture information of a bus included in a semiconductor integrated circuit, a transfer size calculating module configured to calculate a transfer size conforming to a bus architecture, based on the bus architecture information which is acquired, and a simulation executing module. The simulation executing module sets a transaction converting module configured to convert a transaction from a bus initiator included in the semiconductor integrated circuit into a transaction in a size conforming to the transfer size and output the transaction to the bus, and performs simulation of the semiconductor integrated circuit.09-27-2012
20100114553Systems and Methods for Executing Unified Process-Device-Circuit Simulation - A unified simulation system is provided. The unified simulation system includes an input database storing input data comprising an input parameter and environment information, a unified simulator executing a unified process-device-circuit simulation of characteristics of a semiconductor apparatus based on the input data and at least one predetermined model and outputting a simulation result as output data, and an output database storing the output data. The unified simulator includes a process simulator simulating at least one process based on the input data and outputting process characteristic data, a device simulator simulating at least one device based on the process characteristic data and outputting device characteristic data, and a circuit simulator simulating a circuit comprising the at least one device. Accordingly, multiple devices can be simultaneously optimized for the optimization of circuit characteristics and an accurate specification at process and device levels can be provided.05-06-2010
20100114552METHODS AND APPARATUS FOR CLOCK SIMULATION WITH CALIBRATION - A method for clock modeling in a simulation tool is described. An internal time (I) may be defined that governs the simulator tool's clock period. An external time (E) may be defined. The internal time may have a smaller resolution than the external time. A calibration period (C) may be defined for the clock. The calibration period may be smaller than 0.5E and greater than I. The largest inaccuracy of any clock edge may be monitored, and the clock may be calibrated if the largest inaccuracy is greater than (C−1).05-06-2010
20090216513Design verification using directives having local variables - A computer-implemented method for verifying a design includes representing a verification directive, which pertains to the design and includes a local variable, by a finite state machine. The state machine includes multiple states, with transitions among the states, transition conditions associated with the transitions, and procedural blocks, which correspond to the transitions and define operations to be performed on the local variable when traversing the respective transitions.08-27-2009
20130080137CONVERSION METHOD AND SYSTEM - A computer-implemented method for converting a representation of a system into a behaviour model of the system is provided. The method can be used to convert a schematic diagram into a behavioural model.03-28-2013
20130080136SIMULATION DEVICE AND SIMULATION METHOD - A simulation device having an ESD (Electro Static Discharge) protection element has a first parameter file creating unit, a second parameter file creating unit, a parameter file storage storing the parameter files created by the first and second parameter file creating units, a parameter file selector changing a parameter file to be selected from the parameter files stored in the parameter file storage, depending on whether or not operation of the ESD protection element should be verified, a netlist creating unit creating a netlist of the semiconductor circuit utilizing the parameter file selected by the parameter file selector, and a simulation executing unit verifying the operation of the semiconductor circuit based on the netlist.03-28-2013
20130080135SYSTEM, TOOL AND METHOD FOR INTEGRATED CIRCUIT AND COMPONENT MODELING - A system, tool and method for testing and modeling capabilities and functionalities of an integrated circuit or components thereof in an extreme environment, particularly for temperatures encountered in outer space, lunar and planetary environments.03-28-2013
20130085738EXECUTING A HARDWARE SIMULATION AND VERIFICATION SOLUTION - One embodiment of the present invention provides systems and techniques to execute a hardware simulation and verification solution on a multiprocessor system. The hardware simulation and verification solution can be partitioned into different modules which can include a simulation kernel to simulate changes in signal values, a value change dump module to store the changes in the signal values on a computer-readable storage medium, a functional coverage module to check functionality, a toggle coverage module to check signal toggling, an assertion engine to check complex behaviors, and a testbench module to generate test scenarios. Embodiments of the present invention can execute different modules on different processors, thereby improving performance.04-04-2013
20130041645RECORDING MEDIUM IN WHICH CIRCUIT SIMULATOR PROGRAM IS STORED, AND DEVICE AND METHOD FOR GENERATING EYE PATTERN - An eye pattern is generated by: simulating a rising step response to a rising step signal input into the circuit and a falling step response to a falling step signal input into the circuit; analyzing a result of the simulating of the rising step response and the falling step response; generating, on the basis of a result of the analyzing, an upper-part test pattern that defines a shape of an upper part of an eye of an eye pattern and a lower-part test pattern that defines a shape of a lower part of the eye of the eye pattern; and simulating a response to the upper-part test pattern and the lower-part test pattern both input into the circuit. This procedure rapidly generates a precise eye pattern.02-14-2013
20090157375POWER INDEX COMPUTING APPARATUS, METHOD OF COMPUTING POWER INDEX, AND COMPUTER PRODUCT - A power index computing apparatus that computes a power index for a circuit having one or more modules includes an obtaining unit that obtains estimated power consumption for a module in the circuit and a first computing unit that computes entropy based on a transition probability of an output signal of the module during a simulation period. The entropy is indicative of an expected value of a data volume output from the module, and the output signal is output to a destination that is external to the module. The power index computing apparatus further includes a second computing unit that computes a power index based on the estimated power consumption and the entropy, where the power index concerns power consumption for output of the output signal with respect to the estimated power consumption. An output unit of the power index apparatus outputs a result of the second computing unit.06-18-2009
20100106476Fast Simulation Method For Integrated Circuits With Power Management Circuitry - In a fast simulation technique, the output node of a power supply module of the integrated circuit can be designated as an ideal power node. At this point, the power supply module can be designated a fan-in block and any blocks connected to the power node can be designated fan-out blocks. Then, DC initialization and transient simulation for each time step can be performed for the circuit. During the transient simulation, any inter-relationship of the fan-out blocks can be determined and a sensitivity model can be calculated for each fan-out block. Because the power node is designated as an ideal power node, the results of the sensitivity model for each fan-out block can be added asynchronously to a total loadings of the power node. The total loadings can be loaded into a matrix, which is computed for the fan-in block, and a simulation waveform point can be output.04-29-2010
20090125292METHOD AND SYSTEM FOR TESTING FUNCTIONALITY OF A CHIP CHECKER - A method for testing functionality of a chip checker is disclosed. The checker is arranged for generating a predetermined verification signal when the chip, upon receiving a predetermined input signal, generates a corresponding response signal. The method comprises the steps of developing a model of the chip, the model at least partially emulating at least one response of the chip by generating, upon receiving the predetermined input signal, the corresponding response signal. The method further supplies the developed chip model with the predetermined input signal. The checker is then used to test whether the generated response signal corresponds to the respective predetermined input signal. A failure of the checker to generate the predetermined verification signal indicates checker malfunction.05-14-2009
20120166170DELAY CIRCUIT, AND DEVICE AND METHOD FOR SIMULATING ASYNCHRONOUS CIRCUIT IN FPGA USING DELAY CIRCUIT - Disclosed herein is an apparatus for simulating an asynchronous circuit in an FPGA. The apparatus includes a plurality of function execution units, a plurality of delay circuits, and a control unit. The function execution units are set for respective unit functions included in the asynchronous circuit, and are configured to perform the unit functions. The delay circuits are provided for the respective function execution units using a look-up table in the FPGA, and are configured to output delayed input signals by delaying input signals by respective preset delay times. The control unit transmits the input signals to the delay circuits and the function execution units, and receives the delayed input signals from the respective delay circuits.06-28-2012
20090043558DELAY CALCULATION METHOD CAPABLE OF CALCULATING DELAY TIME WITH SMALL MARGIN OF ERROR - A delay calculation method that is capable of calculating delay time with a small margin of error is provided for delay calculation in a logic circuit. The operating characteristics of transistor are expressed with a fixed resistance and a power supply voltage that changes with time. The power supply voltage is represented as a waveform which is a combination of two straight lines: the one indicating that the voltage, after a fixed delay of t02-12-2009
20090306953Generating Variation-Aware Library Data With Efficient Device Mismatch Characterization - In a method of generating variation-aware library data for statistical static timing analysis (SSTA), a “synthetic” Gaussian variable can be used to represent all instances of one or more mismatch variations in all devices (e.g. transistors), thereby capturing the effect on at least one timing property (e.g. delay or slew). By modeling device mismatch with synthetic random variables, the variation behavior (in terms of the distribution of delay, slew, constraint, etc.) can be interpreted as the outcomes of process variations instead of modeling the variation sources (e.g. transistor shape variations, variations in dopant atom density, and irregularity of edges).12-10-2009
20120191438METHODS AND SYSTEMS FOR THERMODYNAMIC EVOLUTION - Methods and systems for thermodynamic evolution. Adaptive control systems are constructed based on the property of volatile matter to self-organize to maximize the dissipation of energy. The logical state of sensory nodes in a node circuit are set and projected into a network. Then, the system evaluates logical state of processing nodes by summing input currents of processing nodes and project processing node's state into network. The strength of processing node is increased such that logical state of sensory node matches with logical states of processing node by utilizing plasticity rule. The system is configured to maximize energy dissipation by creating weight structures to stabilize nodes with logical state. The internal positive feedback of node circuit forces competition between nodes such that one node is driven to high logical state and other nodes to low logical state.07-26-2012
20120191437METHOD FOR EXTRACTING IBIS SIMULATION MODEL - A method for extracting an accurate IBIS simulation model of a semiconductor device including a plurality of semiconductor chips comprises: extracting an AC characteristics model of a first output buffer in an IBIS simulation model by treating first and second output buffers of first and second semiconductor chips connected to a single external connection terminal as a transistor model and executing a transistor-level circuit simulation; calculating an output capacitance model of the first output buffer as an IBIS simulation model by adding output capacitances of the first and second output buffers as a transistor-level circuit simulation model; and synthesizing an IBIS simulation model of the first output buffer viewed from the external connection terminal by using the AC characteristics model and the output capacitance model.07-26-2012
20130073274METHOD AND PROGRAM PRODUCT FOR VALIDATION OF CIRCUIT MODELS FOR PHASE CONNECTIVITY - Circuit component connectivity evaluation and validation method provides comparing and validating the correctness of electrical phase connectivity at connection nodes between conducting components within a circuit model of a power distribution network or other circuit. Phase connectivity requirements of each connected component/device/equipment in a particular circuit are obtained from a Common Interface Model (CIM) file containing parameter data describing the circuit. XML data strings obtained from the CIM file are parsed into enumerated data objects representing each component's phase connectivity requirements and assigned unique four bit binary phase connectivity mask values indicative of the particular electrical phase connectivity requirements of each component. Associated mask values corresponding to connection nodes between pairs of connected components are bit-wise logically “AND”ed and the result compared to each component's bit mask to validate that each connected component in the circuit is a correct phase type match with other components to which it is connected.03-21-2013
20130060551Technology Computer-Aided Design (TCAD)-Based Virtual Fabrication - A single finite element mesh is generated for predicting performance of an integrated circuit design. A plurality of sample points are identified for conducting a variability study on at least one parameter associated with the integrated circuit design. The sample points are selected to predict performance of the integrated circuit design when subject to variations in the at least one parameter due to variations in manufacturing processes to be used to manufacture the integrated circuit design. A parameterized netlist is generated corresponding to each of the sample points. A technology computer aided design (TCAD) simulation is run for each of the parameterized netlists, using the single finite element mesh for each of the parameterized netlists, until convergence is achieved, to obtain, for each of the parameterized netlists, at least one metric indicative of the performance of the integrated circuit design. A predicted design yield is developed for the integrated circuit design.03-07-2013
20090271167PEAK POWER DETECTION IN DIGITAL DESIGNS USING EMULATION SYSTEMS - A method of analyzing power consumption for a DUT (device under test) that includes an integrated circuit or an electronic system includes: providing emulation data for states of the DUT in one or more time windows; determining operational mode values from the emulation data and a selection of operational modes that characterize circuit behavior in the one or more time windows; dividing each time window into one or more segments based on at least one power criterion; determining power-activity values for the one or more segments; determining power-consumption values for the one or more segments from the power-activity values; using the power-activity values and the power-consumption values to determine relative power activity across the one or more segments and adjusting the one or more segments to target high power activity over operational modes in the one or more time windows; and saving one or more values for power activity of the DUT in a computer-readable medium.10-29-2009
20090271166SYSTEMS AND METHODS FOR CURRENT ANALYSIS OF CIRCUITS INCLUDING RELATIVELY LARGE RC NETWORKS - Improved performance of simulation analysis of a circuit with some non-linear elements and a relatively large network of linear elements may be achieved by systems and methods that partition the circuit so that simulation may be performed on a non-linear part of the circuit in pseudo-isolation of a linear part of the circuit. The non-linear part may include one or more transistors of the circuit and the linear part may comprise an RC network of the circuit. By separating the linear part from the simulation on the non-linear part, the size of a matrix for simulation on the non-linear part may be reduced. Also, a number of factorizations of a matrix for simulation on the linear part may be reduced. Thus, such systems and methods may be used, for example, to determine current in circuits including relatively large RC networks, which may otherwise be computationally prohibitive using standard simulation techniques.10-29-2009
20090089037Method and apparatus for circuit simulation in view of stress exerted on MOS transistor - A circuit simulation method includes: generating graphical data indicating dimensions of a subject MOS transistor; calculating a parameter correction amount based on said graphical data; correcting a given transistor model parameter in response to said parameter correction amount; and performing circuit simulation of a circuit that includes said subject MOS transistor by using said corrected transistor model parameter. The parameter correction amount is calculated based on said graphical data by using arithmetic equations. The arithmetic equations include at least one stress model equation expressing a stress exerted on a channel region of a model MOS transistor. The stress model equation is suitably defined to simulate the stress exerted on the channel region.04-02-2009
20090299720Circuit protection and control device simulator - A power circuit protection and control device simulator emulates in real time identical circuit protection and control functions performed by the actual device being simulated and generates real time simulated operational information concerning at least one of the device or the power circuit. A human-machine interface, such as through a web browser, allows a user to input power circuit operational parameters, such as motor current and load, and device variable circuit protection and control operational parameters, such as trip class, ground fault detection or phase unbalance protection. The simulator displays in real time simulated operational information on the human-machine interface. The simulator may be used to simulate operation of an electronic overload relay and an electric motor controlled by the relay.12-03-2009
20090030665Automatic, Hierarchy-Independent Partitioning Method For Transistor-Level Circuit Simulation - A method of providing simulation results includes detecting any power net and rail in a circuit netlist. The circuit can be divided into net-partitioned blocks. Using these net-partitioned blocks, a topological analysis can be performed to identify cuttable/un-cuttable devices and synchronization requirements. Then, the circuit can be re-divided into rail-partitioned blocks. Using these rail-partitioned blocks, a sparse solver can identify potential partitions, but eliminate fill-ins as determined by the topological analysis. A cost function can be applied to the potential partitions as well as the identified cuttable/un-cuttable devices to determine final cut points in the circuit and dynamic inputs to the final blocks. Simulation can be performed on the final blocks and simulation results can be generated.01-29-2009
20130066619Creating and Controlling a Model of a Sensor Device for a Computer Simulation - Various embodiments of a system and method for creating and controlling a model of a sensor device for a computer simulation are disclosed. Sensor information specifying physical properties of the sensor device may be received, and a model of the sensor device may be automatically generated using the sensor information. An electrical circuit simulation may be performed using the model of the sensor device. The system and method may enable the user to interactively change the sensor device model during the simulation. The user may interact with a graphical user interface during the simulation to provide input specifying a change in one or more physical properties of the sensor device. In response to the user input, the model of the sensor device may be dynamically modified during the simulation to simulate the change in the one or more physical properties of the sensor device.03-14-2013
20110022376ESD ANALYSIS DEVICE AND ESD ANALYSIS PROGRAM USED FOR DESIGNING SEMICONDUCTOR DEVICE AND METHOD OF DESIGNING SEMICONDUCTOR DEVICE - An ESD (Electrostatic Discharge) analysis device includes: a circuit simulation unit; a border cell extraction unit; and a check unit. The circuit simulation unit executes a circuit simulation of design data of a semiconductor integrated circuit including a plurality of circuits of a plurality of power supply systems, to calculate potentials in a plurality of current paths between pads of different two of the plurality of power supply systems, when one of an ESD current and an ESD voltage is applied between the pads. The border cell extraction unit extracts border cells from circuits of the different two of the plurality of power supply systems, wherein the circuits are included in the plurality of circuits, the border cells input and/or output signals between the circuits. The check unit checks an ESD tolerance by calculating a potential difference between the border cells, based on the calculated potentials, the extracted border cells.01-27-2011
20090234631Linear Time-Invariant System Modeling Apparatus And Method Of Generating A Passive Model - A linear time-invariant system modeling apparatus comprises a processing resource arranged to receive, when in use, model data constituting to a model of a linear time-invariant system. The model data includes residual value data and scattering data. The processing resource is arranged to perform, when in use, a single value decomposition in respect of the scattering data; the scattering data corresponds, when expressed in matrix form, to a scattering matrix in a state-space representation of the model. The processing resource is also arranged to use, when in use, a result of the single value decomposition in order to generate residual value modification data. The residual value modification data is applied to the residual value data, the residual value data corresponding, when expressed in the matrix form, to a residual value matrix in the state-space representation of the model.09-17-2009
20090234630Method and Apparatus for Assisting Integrated Circuit Designing - The invention concerns a method for verifying, prior to fabrication, the proper operation of integrated circuit electronic systems using analog signals. It comprises the following steps: identifying (09-17-2009
20100088083Method and Apparatus for Circuit Simulation - A method of integrated circuit simulation comprising the steps of providing a voltage lookup table having predetermined drain voltage data for a given transistor type, providing a voltage lookup table having predetermined gate voltage data for a given transistor type. Providing a temperature lookup table having predetermined temperature data. Providing a transistor lookup table having predetermined current and temperature data. Simulating operation of an integrated circuit by, for each transistor in the integrated circuit, determining a current value through the transistor in dependence upon one of the predetermined voltage data values and one of the predetermined temperature data values; and comparing the current value calculated to the current value obtained previously; and updating active transistor list detecting a change in the current value. Then incrementing a simulation time step and repeating simulation steps for all transistors. Simulating operation of an integrated circuit by, for each transistor in the integrated circuit, determining a transistor temperature value for all transistors in the active transistor list.04-08-2010
20130166269SIMULATION APPARATUS, SIMULATION METHOD, AND RECORDING MEDIUM - A simulation apparatus includes a storage device that stores a block of circuit data including a clock gating circuit including a control circuit and a first latch circuit, wherein the control circuit outputs a control signal according to a clock, and wherein the first latch circuit holds or outputs a block of input data according to the control signal; and a processor that executes a program having a procedure. The procedure includes: generating a block of substitution circuit data by substituting the first latch circuit by a selection circuit and a second latch circuit; and performing simulation with respect to the substitution circuit data using a pulse related to the reference clock and the reference clock.06-27-2013
20080294410METHOD OF SEPARATING THE PROCESS VARIATION IN THRESHOLD VOLTAGE AND EFFECTIVE CHANNEL LENGTH BY ELECTRICAL MEASUREMENTS - A IC wafer is fabricated using a process of interest to have a plurality of FET devices with different channel lengths (Leff) form a plurality of channel length groups. The threshold voltage (VT) is measured of a statistical sample of the FET devices in each channel length group at two different drain-to-source voltage (VDS). The mean of VT is calculated for each channel length and each VDS. A slope coefficient λ relating VT to Leff is calculated at each VDS. The total variance of VT is calculated at each VDS. Two equations at each VDS, each relating the total variance of VT to the variance of VT with respect to dopant levels and the square of the slope coefficient λ times the variance of Leff, are solved simultaneously to obtain the variance of VT with respect to dopant levels and the variance of Leff.11-27-2008
20110035204Layered Modeling for High-Level Synthesis of Electronic Designs - Methods and apparatuses for modeling and simulating a high-level circuit design are provided. With some implementations of the invention, a layered model corresponding to an algorithmic description for a circuit design is generated. The layered model includes a set of threads that describe the behavior of the circuit design, a schedule that describes timing constraints of the circuit design, and interfaces that facilitate the transfer of data between various layered models. With some implementations, a layered model may also include a shared variable that facilitates the transfer of data between ones of the set of threads within a layered model.02-10-2011
20110035203 SYSTEM LEVEL POWER EVALUATION METHOD - This invention relates to a system level power evaluation method in which detailed power macro-models (PMM) are created for operations of modules. These PMMs are stored in memory. A system level circuit description (SLCD) is evaluated using the PMMs stored in memory that are relevant to that SLCD and using other PMMs that are generated for operations of modules that do not have PMMs stored in memory. In this way, a highly accurate and computationally efficient power evaluation of the SLCD is possible. Furthermore, the user implementing the method may define a case, which relates to an operation of a module and has a PMM associated therewith, in a highly flexible manner that allows for more abstract analysis of the SLCD to be carried out. A case may relate to a single operation of a module, a plurality of operations of a module or operation(s) of a plurality of modules.02-10-2011
20110282639Modeling of Non-Quasi-Static Effects During Hot Carrier Injection Programming of Non-Volatile Memory Cells - A non-quasi-static model of the programming behavior of a floating-gate metal-oxide-semiconductor (MOS) transistor. This model is based on evaluation of a body current, for example determined as a function of voltages applied to the transistor from the circuit environment. The body current is used as an input to a non-quasi-static function on which the modeled gate injection current is based. In one example, the body current is applied to a representation of a series R-C circuit beginning from a time corresponding to the onset of avalanche breakdown, with the voltage across the capacitor serving as a control voltage of a voltage-controlled current source that drives the gate injection current. Integration of the gate injection current over the time interval of the programming pulse provides an estimate of the trapped charge at the floating gate.11-17-2011
20100125442MODEL PARAMETER EXTRACTING APPARATUS AND MODEL PARAMETER EXTRACTING PROGRAM FOR SEMICONDUCTOR DEVICE MODEL - A model parameter extracting apparatus includes: a binning processor for carrying out a binning process; and a model parameter extractor for extracting a model parameter for each of multiple bins formed by the binning process. The model parameter extractor extracts a first model parameter corresponding to a first end portion of a target bin. Based on the first model parameter, the model parameter extractor sets up a candidate for a second model parameter corresponding to a second end portion of the target bin. Subsequently, based on the first model parameter and the candidate for the second model parameter, the model parameter extractor finds a start-point-side gradient and an end-point-side gradient of a limited curve representing an electric characteristic of a semiconductor device. Then, based on a result of a comparison between the gradients, the model parameter extractor extracts the second model parameter.05-20-2010
20120290281TABLE-LOOKUP-BASED MODELS FOR YIELD ANALYSIS ACCELERATION - In one embodiment, the invention is a method and apparatus for table-lookup-based models for yield analysis acceleration. One embodiment of a method for statistically evaluating a design of an integrated circuit includes simulating the integrated circuit and generating a lookup table for use in the simulating, the lookup table comprising one or more blocks that specify a device element for an associated bias voltage, wherein the generating comprises generating only those of the one or more blocks that specify the device element for a bias voltage that is required during the simulating.11-15-2012
20100318340METHOD OF GENERATING A LEADFRAME IC PACKAGE MODEL, A LEADFRAME MODELER AND AN IC DESIGN SYSTEM - A method of generating a model of a leadframe IC package, a leadframe modeler and an IC design system are disclosed. In one embodiment the method includes: (1) adding connectivity information to a geometric representation of a leadframe, wherein the connectivity information represents electrical connections between the IC die and leads of the leadframe and (2) formatting the leads to represent BGA point of contacts for the IC die.12-16-2010
20110301932MOSFET MODEL OUTPUT APPARATUS AND METHOD, AND RECORDING MEDIUM - In one embodiment, a MOSFET model output apparatus is configured to output a MOSFET model for a simulation of a semiconductor circuit. The apparatus includes a shape data input part configured to input shape data of a MOSFET. The apparatus further includes a parameter calculation part configured to calculate a parameter of a parasitic device model to be added to the MOSFET model, using the shape data. The apparatus further includes a MOSFET model output part configured to generate and output the MOSFET model added with the parasitic device model, using the parameter of the parasitic device model. Further, the MOSFET model output part adds different parasitic device models to the MOSFET model in a case where the MOSFET is an N-type MOSFET and in a case where the MOSFET is a P-type MOSFET.12-08-2011
20100324879CIRCUIT SIMULATION APPARATUS AND CIRCUIT SIMULATION METHOD - A circuit simulation apparatus acquires wiring connection information indicating connection data in an electric circuit, selects a component constituting the circuit based on the wiring connection information, performs a setting of replacing the selected component with each resistor having different resistance values, generates at least one of netlists using the acquired wiring connection information and at least one of the set resistance values, calculates a value of an equivalent power source and a value of an internal resistance thereof for a part of the circuit using the acquired wiring connection information and at least one of the generated netlists, and calculates a resistance value of the selected component and a power consumption for the resistance value using the value of the equivalent power source and the value of the internal resistance.12-23-2010
20090299719CIRCUIT SIMULATION APPARATUS AND METHOD,MEDIUM CONTAINING CIRCUIT SIMULATION PROGRAM - A circuit simulation apparatus includes a first acquisition unit that acquires information on a jitter transfer function of a jitter pass element with respect to a predetermined frequency band, a second acquisition unit that acquires information pertaining to input jitter to the jitter pass element, a first calculation unit that determines a jitter frequency based on the information acquired by the first acquisition unit or the second acquisition unit to calculate a jitter transfer function value which is a value of the jitter transfer function acquired by the first acquisition unit at the jitter frequency, and a second calculation unit that calculates output jitter from the jitter pass element based on the information pertaining to the input jitter acquired by the second acquisition unit and the jitter transfer function value calculated by the first calculation unit.12-03-2009
20100138207Method and Apparatus for Circuit Simulation - An integrated circuit simulator and method of integrated circuit simulation comprising providing a voltage lookup table having predetermined drain voltage data for a given transistor type, providing a voltage lookup table having predetermined gate voltage data for a given transistor type and providing a temperature lookup table having predetermined temperature data. Then simulating operation for each transistor in the integrated circuit by determining a current value through the transistor in dependence upon one of the predetermined voltage data values and one of the predetermined temperature data values; and simulating operation for each transistor in the integrated circuit by determining a transistor temperature value and incrementing a simulation time step and repeating the last two steps until simulations complete.06-03-2010
20100057424Method for evaluating a test program quality - The invention relates to a method for rating the quality of a test program for integrated circuits simulated by means of a computer, comprising 03-04-2010
20090259452SIMULATION SYSTEM AND COMPUTER PRODUCT - A simulation system includes electromagnetic field analyzing units that execute electromagnetic field analysis with respect to electromagnetic field analysis areas obtained by division of an area to be analyzed into the electromagnetic field analysis areas; one or more circuit analyzing units that execute circuit analysis with respect to a circuit unit in the area to be analyzed; and an aggregating unit that aggregates, from the electromagnetic field analyzing units, data for the circuit analysis by the one or more circuit analyzing units and transmits the data to the circuit analyzing units. The simulation system links plural processing units that mutually exchange data.10-15-2009
20100114551SYSTEMS AND METHODS FOR IMPROVING DIGITAL SYSTEM SIMULATION SPEED BY CLOCK PHASE GATING - An apparatus for simulating digital systems is described. The apparatus includes a processor and memory in electronic communication with the processor. Instructions that are executable by the processor are stored in the memory. A simulation tool is started. The simulation tool is capable of simulating a plurality of components. A clock phase is adjusted to be turned off for at least one of the components. A digital system is simulated that includes the at least one component. The simulation does not simulate the clock phase for the at least one component.05-06-2010
20090187394HDL RE-SIMULATION FROM CHECKPOINTS - A computer-based simulation process executes a checkpoint operation while simulating behavior of an electronic circuit by forking an active checkpoint process having the same state as the original simulation process. While simulation time for the simulation process continues to increase after executing the checkpoint operation, simulation time for the checkpoint process remains unchanged so that the checkpoint process remains in the state of the simulation at the simulation time it executed the checkpoint operation (the “checkpoint time”). When the checkpoint process subsequently receives a request to resume simulating the circuit, it forks a new simulation process that mimics the original simulation process as of checkpoint time, and the new simulation process then begins to advance its simulation time, thereby enabling it to re-simulate behavior of the electronic circuit previously simulated by the original simulation process starting from the checkpoint time.07-23-2009
20110172983METHOD FOR INCORPORATING PATTERN DEPENDENT EFFECTS IN CIRCUIT SIMULATIONS - Methods, software, and apparatus for providing a netlist for simulation that includes one or more parameters that are determined by one or more pattern dependent effects. One particular embodiment of the present invention receives a layout of a circuit including one or more MOSFET transistors. For one or more of the MOSFET transistors, spacing between transistors is measured using the received layout and a pattern dependent parameter is determined. This parameter modifies the length of the gate that is used in simulation. In other embodiments, other pattern dependent effects can be used to determine the values of one or more parameters. These parameters may be used to modify gate length, emitter size, resistor width, or other device characteristics.07-14-2011
20090055152METHOD OF MODELING AND PRODUCING AN INTEGRATED CIRCUIT INCLUDING AT LEAST ONE TRANSISTOR AND CORRESPONDING INTEGRATED CIRCUIT - A system is provided for modeling an integrated circuit including at least one insulated-gate field-effect transistor. The system includes generator means for defining a parameter representing mechanical stresses applied to the active area of the transistor, and processing means for determining at least one of the electrical parameters of the transistor based at least partially on the stress parameter. Also provided is a method of modeling an integrated circuit including at least one insulated-gate field-effect transistor, and a method of producing an integrated circuit including at least one insulated-gate field-effect transistor.02-26-2009
20090144042SYSTEM AND METHOD FOR THREE-DIMENSIONAL SCHEMATIC CAPTURE AND RESULT VISUALIZATION OF MULTI-PHYSICS SYSTEM MODELS - A 3-D multi-physics design environment (“3-D design environment”) for designing and simulating multi-physics devices such as MEMS devices is discussed. The 3-D design environment is programmatically integrated with a system modeling environment that is suitable for system-level design and simulation of analog-signal ICs, mixed-signal ICs and multi-physics systems. A parameterized MEMS device model is created in a 3-D graphical view in the 3-D design environment using parameterized model components that are each associated with an underlying behavioral model. After the MEMS device model is completed, it may be exported to a system modeling environment without subjecting the model to preliminary finite element meshing.06-04-2009
20090150138Apparatus and method for analyzing circuit - In an aspect of the present invention, a circuit analyzing method includes: generating an analysis object circuit model by connecting a package model as a lumped parameter circuit model of a package, a noise source model as a lumped parameter circuit model of a noise source circuit, a noise-receiving circuit model as a lumped parameter circuit model of a noise-receiving circuit, and a substrate model as a lumped parameter circuit model of a substrate between the noise source circuit and a noise-receiving circuit; and performing a circuit simulation to the analysis object circuit model to calculate a power supply voltage waveform in the noise-receiving circuit.06-11-2009
20090150137Method for generating performance evaluation model - A method for generating performance evaluation model may be provided which executes, by using first models of function modules which are described in a transaction level, a first simulation of system operation at the transaction level between the function modules, records transactions which are generated in the first simulation per function module, executes, by using second models of the function modules which are described in a hardware level, a second simulation of circuit operation of each of the function modules to determine a delay time of each function module of the recorded transactions, and assigns information of the delay time to the first model and generating a third model per function module.06-11-2009
20090313000METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR DETECTING X STATE TRANSITIONS AND STORING COMPRESSED DEBUG INFORMATION - A method of generating debug data in a simulation environment includes generating a listing of one or more signals that relate to a failure signal; monitoring simulation data of the one or more signals for transitions between a defined state and an undefined state; and generating a waveform of data based on the transitions between the defined state and the undefined state.12-17-2009
20120239371Consistent Hierarchical Timing Model with Crosstalk Consideration - A method and apparatus to provide a hierarchical timing model with crosstalk consideration is provided. In one embodiment, the method comprises performing block level analysis of a circuit, in one or a plurality of iterations, and storing per iteration data. The method further comprises, in one embodiment, utilizing the per iteration data in performing top level analysis of the circuit.09-20-2012
20120109617OPTIMIZATION OF ELECTRICAL COMPONENT PARAMETERS IN ENERGY STORAGE SYSTEM MODELS - A method of predicting an electrochemical mapping parameter in a vehicle that derives at least a portion of its motive power from an energy storage system is provided. The method may comprise providing a plurality of electrochemical mapping parameter sources capable of rendering one or more electrochemical mapping parameters selected from the group consisting of resistance and capacitance and selecting at least one electrochemical mapping parameter source capable of rendering one or more electrochemical mapping parameters based on the state of the energy storage system. The method may also comprise determining an adaptive gain and determining an adaptive factor based on the operating state of the vehicle or the energy storage system. The method may also comprise adapting the one or more electrochemical mapping parameters based on the adaptive factor and adaptive gain to provide an adapted electrochemical mapping parameter value.05-03-2012
20090094013TWO-STEP SIMULATION METHODOLOGY FOR AGING SIMULATIONS - The present invention is a method and system for simulating the aging process of a circuit. A two-step process is employed whereby, in a first simulation step, a simulation is conducted to obtain node voltages for the original circuit and the node voltages are stored in a file. In the second step, a subsequent simulation is run after transistors of the circuit are replaced by aging subcircuits, which contain aging models, and initial node voltages are updated. A script is used to set the bias voltage inputs for the aging models using the node voltages stored in the file from the first step. With more accurate bias voltage inputs for the aging models, the aging simulations are conducted to compute the circuit degradation.04-09-2009
20120143582CHARACTERIZATION OF NONLINEAR CELL MACRO MODEL FOR TIMING ANALYSIS - A system, method and computer program product for modeling a semiconductor device structure. The system and method implemented includes performing a simulation of the circuit by applying at least one input waveform on a circuit input port, and loading an output port with at least one of output load; determining, at successive time steps of the circuit simulation, a voltage value Vi on the input port, a voltage value Vo on the output port, and a current values (ia) and (ib) on the respective input and output ports. Then there is computed from the respective current value for each successive time step of the simulation, at least one charge value (Qa(Vi, Vo)) and (Qb(Vi, Vo)), respectively, as a function of Vi and Vo voltage values; and generating a nonlinear charge source from the at least one charge value, the nonlinear charge source used in modeling a dynamic behavior of the cell. A voltage controlled charge source (VCCS) is thereby determined by capturing the natural digital circuit cell behavior.06-07-2012
20100125441Method and Apparatus for Circuit Simulation - An integrated circuit simulator and method of integrated circuit simulation comprising providing a voltage lookup table having predetermined drain voltage data for a given transistor type, providing a voltage lookup table having predetermined gate voltage data for a given transistor type and providing a temperature lookup table having predetermined temperature data. Then simulating operation for each transistor in the integrated circuit by determining a current value through the transistor in dependence upon one of the predetermined voltage data values and one of the predetermined temperature data values; and simulating operation for each transistor in the integrated circuit by determining a transistor temperature value and incrementing a simulation time step and repeating the last two steps until simulations complete.05-20-2010
20090281781METHOD AND APPARATUS FOR GENERATING ADAPTIVE NOISE AND TIMING MODELS FOR VLSI SIGNAL INTEGRITY ANALYSIS - A method, apparatus and program product are provided for performing a noise, timing, or other signal integrity simulation of a circuit under test. A simulation cache structure is accessed to retrieve cached simulation results for a first portion of the circuit under test. Simulation is performed on a second portion of the circuit under test to generate simulation results for the second portion. Simulation results are generated for the circuit under test by combining the simulation results for the second portion with the cached simulation results for the first portion.11-12-2009
20090112551MATRIX MODELING OF PARALLEL DATA STRUCTURES TO FACILITATE DATA ENCODING AND/OR JITTERY SIGNAL GENERATION - One or more embodiments of the disclosed computer-implementable method comprise a matrix-based approach to generating in parallel a plurality of realistic simulatable signal vectors, which vectors include the addition of amplitude noise and/or timing jitter and encoding. For example, each channel in a parallel bus can be populated in a matrix, with each row comprising ideal voltage values for the channel, and the columns comprising bits of the sequence of voltage values for that channel. Thereafter, encoding can be employed to modify the data in the matrix. Amplitude noise and/or timing jitter can then be applied to each channel (row) in the matrix. This modifies the time basis from a bit basis as used in the matrix to a time-step basis. With such modification accomplished, each row in the matrix can be transformed into simulatable vector, which vectors can then be simulated in parallel to test, for example, the robustness of the parallel bus of which the channels are part.04-30-2009
20090299718Power source network analyzing apparatus, power source network analyzing method, and power source network analyzing program - An area partitioning processing unit equally partitions a power source network analysis object area of an LSI according to the number or size of partitioned areas specified by a user or partitions the power source network analysis object area according to the user's specification. A border processing unit extracts and adds a range-of-influence part of the power source network that can electrically influence a border between the partitioned area partitioned by the area partitioning processing unit and an adjacent power source network area. A modeling processing unit performs processing of resistance modeling of the partitioned area or a correction spot with the range-of-influence part added thereto by the border processing unit. A power source network analyzing processing unit analyzes a resistance model modeled by the modeling processing unit and calculates potential of each via as a current source to a load element.12-03-2009
20090299717ENHANCED CHANNEL SIMULATOR FOR EFFICIENT ANTENNA EVALUATION - Method and apparatus for channel simulation is disclosed. The claimed invention provides method and apparatus 12-03-2009
20110270597Tracking Array Data Contents Across Three-Valued Read and Write Operations - A mechanism is provided in an integrated circuit simulator for tracking array data contents across three-value read and write operations. The mechanism accounts for write operations with data values and address values having X symbols. The mechanism performs writes to a tree data structure that is used to store the three-valued contents to the array. The simulator includes functionality for updating the array contents for a three-valued write and to read data for a three-valued read. The simulator also includes optimizations for dynamically reducing the size of the data structure when possible in order to save memory in the logic simulator.11-03-2011
20090037160METHOD AND APPARATUS TO SERVE IBIS DATA - In accordance with an embodiment of the present invention, a method of serving IBIS data may include determining a circuit specified for signal integrity simulation. IBIS data may be obtained for the circuit specified, from which polynomials may be determined to be representative of at least a portion of the IBIS data. The polynomial information determined may be stored in a file with indexing for enabling its subsequent selective retrieval by way of a request for the IBIS data for the specified circuit.02-05-2009
20120296622SIMULATING APPARATUS FOR SIMULATING INTEGRATED CIRCUIT - A device to simulate an integrated circuit (IC) includes a main body, a simulating signal generating module, and a converting module. The simulating signal generating module is positioned on the main body and generates signals indicative of signals of the IC. The converting module is positioned on the main body and converts the signals from digital to analog form. The connecting board is assembled to the main body and sends the converted signals to a printed circuit board (PCB).11-22-2012
20110270598Integrated Circuit Design and Simulation - An integrated circuit design method, system and simulator, wherein the integrated circuit design method includes: determining a region in which power supply noise shall be analyzed; determining current model parameters of the region; determining model parameters of a power supply network model; inputting into a simulator a net list; judging whether or not the region satisfies noise requirements of a chip power supply; and if the region satisfies noise requirements of the chip power supply, determining that the initial area is a minimum area that satisfies the noise requirements of the chip power supply in case the initial number of decoupling capacitors are used in the region.11-03-2011
20080275689Method for Simulating a Circuit in the Steady State - Method for simulating a response of an electronic circuit containing SOI transistors (11-06-2008
20080228460METHOD FOR DETERMINING BEST AND WORST CASES FOR INTERCONNECTS IN TIMING ANALYSIS - Roughly described, signal propagation delay values are estimated for a plurality of interconnects in a circuit design. For each interconnect, the propagation delay value(s) are estimated in dependence upon a preliminary approximate determination of whether the signal propagation delay is dominated more by an interconnect capacitance term or by an interconnect capacitance and resistance product term. If it is dominated more by the interconnect capacitance term, then the parameter values used for a minimum propagation delay calculation are obtained assuming a smallest capacitance process variation case and the parameter values used for a maximum propagation delay calculation are obtained assuming a largest capacitance process variation case. If the signal propagation delay is dominated more by the interconnect capacitance and resistance product term, then the opposite assumptions are made. Preferably the approximate determination is made by comparing Rint to k*Rd.09-18-2008
20080288230STRUCTURE FOR TESTING AN OPERATION OF INTEGRATED CIRCUITRY - A design structure is embodied in a machine readable medium for designing, manufacturing, or testing integrated circuitry. The design structure includes a general purpose computational resource for performing general purpose operations of a system. A special purpose computational resource is coupled to the general purpose computational resource. The special purpose computational resource is for: storing test patterns, a description of the integrated circuitry, and a description of hardware for testing the integrated circuitry; and executing software for simulating an operation of the described hardware's testing of the described integrated circuitry in response to the test patterns.11-20-2008
20090265155Method of predicting reliability of semiconductor device, reliability prediction system using the same and storage medium storing program causing computer to execute the same - An initial reliability of a semiconductor device is predicted before the design layout of a semiconductor product. A method of predicting the reliability of a semiconductor device according to the present invention: calculates the defect density of a plurality of wiring patterns on a wafer; extracts the critical area of a series of library elements formed of wiring patterns based on the defect density to determine the critical area value of each library element; determines a failure probability by wiring pattern from the result of a reliability test of the wiring pattern to form a correlation model from an expected value in which a defect is generated and which is obtained from the defect density and the failure probability of each wiring pattern; calculates the failure probability of each library element from the critical area value and the function of the correlation model; designs a layout of a semiconductor product with two library elements or more out of a series of the library elements combined together and calculates the reliability of the designed semiconductor device in consideration of the failure probability of the library elements combined together.10-22-2009
20090265154SIMULATION OF DIGITAL CIRCUITS - A method for simulating a circuit. The method includes, in response to a first mode change triggering event at a first time point and in response to a first data transfer triggering event at a second time point after the first time point, generating a random value of at least a first random value and a second random value. In response to the generated random value being the first random value, a first input value of an input of the circuit is assigned to an output of the circuit. In response to the generated random value being the second random value, an output value of the output of the circuit is maintained. In response to a second data transfer triggering event at a third time point after the second time point, a second input value of the input of the circuit is assigned to the output of the circuit.10-22-2009
20080270099CLOCK CONTROL MODULE SIMULATOR AND METHOD THEREOF - A method for simulating an integrated circuit having a plurality of clock control modules includes simulating the integrated circuit, and automatically receiving from each clock control model during simulation an indication of a simulated power state of the clock control model. Accordingly, the simulated power state of the portion of the integrated circuit model to be clocked by a clock control model can be monitored based on the indicator from the clock control model, rather than on a higher level analysis of the simulated input/output behavior of the integrated circuit model.10-30-2008
20090164196METHOD AND APPARATUS OF CIRCUIT SIMULATION OF HIGH-WITHSTAND-VOLTAGE MOS TRANSISTOR - Disclosed is a method in which a simulation is performed using a macro model for carrying out a simulation of a high-withstand-voltage MOSFET. The macro model is obtained by adding first and second JFETs to drain and source sides, respectively, of an NMOSFET; connecting one end of a first diode to a gate of the first JFET and connecting the other end of the first diode to the source of the NMOSFET; and connecting one end of a second diode to a gate of the second JFET and connecting the other end of the second diode to the drain of the MOSFET.06-25-2009
20090119085METHOD AND SYSTEM FOR MODELING DYNAMIC BEHAVIOR OF A TRANSISTOR - Method and system are disclosed for modeling dynamic behavior of a transistor. The method includes representing static behavior of a transistor using a lookup table, selecting an instance of the transistor from the lookup table for modeling dynamic behavior of the transistor, computing a previous state of the instance using a non-quasi static analytical model, computing a variation in channel charge of the instance according to a rate of change in time, computing a current state of the instance using the previous state and the variation in channel charge, computing a modified terminal voltage that includes a dynamic voltage across a parasitic resistance at the terminal of the transistor according to the current state and previous state of the instance, and storing the modified terminal voltage in a memory device for modeling dynamic behavior of the transistor at the current state.05-07-2009
20090119084SYSTEM, METHOD, AND PROGRAM PRODUCT FOR SIMULATING TEST EQUIPMENT - A simulation system includes a Response database for storing Response Data in which an output result of a device-under-test (DUT) model for a predetermined test item is set, and a framework for causing the test plan program to operate. The framework determines an output result of a DUT or a DUT model for a predetermined test item, which is executed based on the test plan program, based on the Response Data stored in the Response database. That enables a test flow to be verified in an offline simulation environment of the test equipment without loading a pattern program.05-07-2009
20090138253HARNESS DESIGN APPARATUS - First, the position and the length of a harness are set. Next, a shape setting function having an unknown variable that minimizes potential energy as a binding position is generated, and a position of the minimum potential energy at a bending position is calculated in the Lagrange Multiplier Method. The position of the minimum potential energy obtained by the Lagrange Multiplier Method is the optimum binding position.05-28-2009
20090006065METHOD TO PRODUCE SUBSTRATE NOISE MODEL AND RELATED SYSTEM AND ARTICLE OF MANUFACTURE - A method is provided to produce a model of an integrated circuit substrate, the method comprising: providing a tile definition that specifies an electrical model associated with instances of the tile; mapping a plurality of respective tile instances to respective locations of the substrate; and connecting the mapped tile instances to each other to produce a tile grid that models overall electrical behavior of the substrate.01-01-2009
20110144968SIMULATION PARAMETER EXTRACTING METHOD OF MOS TRANSISTOR - A simulation parameter extracting method of a MOS transistor according to an exemplary aspect of the present invention includes evaluating a measured value that includes a true gate-overlap capacitance by measuring a capacitance between the gate and the drain in each of a plurality of layout patterns at a predetermined bias voltage, only the number of contact plugs being different for each layout pattern, evaluating a gate-overlap capacitance calculation value of each layout pattern by subtracting a contact parasitic capacitance between the contact plug and the gate from the measured value, the contact parasitic capacitance being obtained by a simulation with varying a model parameter for evaluating a parasitic capacitance between the contact plug and the gate, and extracting the gate-overlap capacitance calculation value as the true gate-overlap capacitance at the model parameter when the gate-overlap capacitance calculation value is about constant regardless of the number of the contact plugs.06-16-2011
20090144043POST INITIAL MICROCODE LOAD CO-SIMULATION - Disclosed is simulation of circuit behavior by running a central electronic core simulation in a high level simulator up to and including initial microload, creation of a post-IML (initial microcode load) state, and transferring the post-initial microcode state from the central electronic core simulation to the post-initial microcode load co-simulator.06-04-2009
20090326902Logic simulation method and logic simulator - A logic simulation method includes causing a physical specification detector to detect physical specifications of an analog circuit (a PLL circuit and a DLL circuit) as a verification object described in a logic library; causing a monitor to monitor whether a signal or setting during a logic simulation satisfies the physical specifications; and causing a warning section to issue a warning when the signal or the setting fails to satisfy the physical specifications.12-31-2009
20090326901APPARATUS AND METHOD FOR ESTIMATING CHANGE AMOUNT IN REGISTER TRANSFER LEVEL STRUCTURE AND COMPUTER-READABLE RECORDING MEDIUM - An apparatus for estimating a change amount in a register transfer level structure includes: a correspondence relationship creating unit which describes a correspondence relationship among a behavioral description, a control data flow graph, and a register transfer level structure of a register transfer level description created by performing high-level synthesis on the behavioral description, based on the behavioral description which is input, the control data flow graph which is input and created by performing high-level synthesis on the behavioral description, and binding information which is input and created by performing high-level synthesis on the behavioral description; and a register transfer level change amount estimating unit which estimates and outputs a change amount in the register transfer level structure, the change amount in the register transfer level structure being necessary to change the register transfer level description to a description equivalent to a partially changed behavioral description, based on information of the partially changed behavioral description obtained by partially changing the behavioral description and the created correspondence relationship.12-31-2009
20090024378SIMULATION METHOD FOR EFFICIENT CHARACTERIZATION OF ELECTRONIC SYSTEMS UNDER VARIABILITY EFFECTS - A method of determining the behavior of an electronic system comprising electronic components under variability is disclosed. In one aspect, the method comprises for at least one parameter of at least one of the electronic components, showing variability defining a range and a population of possible values within the range, each possible value having a probability of occurrence, thereby defining an input domain. The method further comprises selecting inputs randomly from the input domain, wherein the probability to sample (PTS) is obtained from the probability of occurrence (PTOIR). The method further comprises performing simulation to obtain the performance parameters of the electronic system, thereby defining an output domain sample. The method further comprises aggregating results of the individual computations into the parameter/variability of the electronic system and assigning a frequency of occurrence (FoO) to the resulting sample, the parameter variability and the frequency of occurrence defining the behavior.01-22-2009
20090099830Detecting counterfeit electronic components using EMI telemetric fingerprints - One embodiment of the present invention provides a system that non-intrusively detects counterfeit components in a target computer system. During operation, the system collects target electromagnetic interference (EMI) signals generated by the target computer system using one or more antennas positioned in close proximity to the target computer system. The system then generates a target EMI fingerprint for the target computer system from the target EMI signals. Next, the system compares the target EMI fingerprint against a reference EMI fingerprint to determine whether the target computer system contains a counterfeit component.04-16-2009
20090099829INTEGRATED CIRCUIT TESTER INFORMATION PROCESSING SYSTEM FOR NONLINEAR MOBILITY MODEL FOR STRAINED DEVICE - A method for operating an integrated circuit tester information processing system includes: measuring current information from test structures for an integrated circuit having a stress liner; forming a transfer curve by simulating based on the current information with a first range of first mobility multipliers; forming an inverse transfer curve by applying an inverse transfer function to the transfer curve; forming a stress curve with second mobility multipliers from the inverse curve; and validating the second mobility multipliers by comparing a measured curve and a simulated curve with the measured curve based on the current information and the simulated curve based on stress curve.04-16-2009
20110231175ELECTRONIC DEVICE AND METHOD OF GENERATING COMPOSITE ELECTRICAL SIGNALS - In an electronic device and a method of generating composite electrical signals, a plurality of post-processing software is installed. An output file, which comprises times and voltages of data points that represent an electrical signal, of an electronic circuit simulation software is loaded, and is read using the installed post-processing software. A time interval of outputs of the electrical signal is obtained by selecting an output type of the electrical signal. The worst bit combination of outputs of the electrical signal is analyzed according to the times, the voltage, and the time interval, and a composite electrical signal is generated according to the worst bit combination.09-22-2011
20120078605Methods and Apparatuses for Circuit Simulation - In one embodiment, a method comprising identifying a sub-network of the linear circuit, the sub-network having one or more internal nodes, one or more interface nodes, and branches connecting the one or more internal nodes and the one or more interface nodes, the sub-network having at least one of a capacitor and an inductor, is described. The method in one embodiment comprises determining a linear equation system for transient simulation of the linear circuit, the linear equation system containing no variable representing the one or more internal nodes.03-29-2012
20090099828Device Threshold Calibration Through State Dependent Burnin - Disclosed are embodiments of a design structure for reducing and/or eliminating mismatch. The embodiments sample the bias of one or more circuit sub-components that require a balanced state (e.g., sampling the bias of the cross-coupled transistors in each memory cell and/or sense amp in a memory array) before chip burn-in, by initiating a burn-in process during which an individually selected state is applied to each of the devices in the circuit. This fatigues the devices away from their preferred states and towards a balanced state. The bias is periodically reassessed during the burn-in process to avoid over-correction. By using this method both memory cell and sense-amplifier mismatch can be reduced in memory arrays, resulting in smaller timing uncertainty and therefore faster memories.04-16-2009
20090099831METHOD FOR GENERATING AND EVALUATING A TABLE MODEL FOR CIRCUIT SIMULATION - A method for generating and evaluating a table model for circuit simulation in N dimensions employing mathematical expressions for modeling a device. The table model uses an unstructured N-dimensional grid for approximating the expressions. The method includes the steps of: (a) establishing a function domain having boundary limits in the N dimensions; (b) performing an accuracy partitioning operation to establish accuracy partitions; the mathematical expressions being satisfied within each accuracy partition within a predetermined error criteria; (c) performing a continuity partitioning operation to establish continuity partitions ensuring continuity of solutions of the mathematical expressions across boundaries separating adjacent accuracy partitions; (d) performing a grid refining operation to configure the continuity partitions to assure monotonic solutions of the mathematical expressions in the continuity partitions; (e) if a continuity partition is altered during the grid refining operation, returning to step (c), else proceeding to next step; (f) ending the method.04-16-2009
20090210211METHOD FOR RECONSTRUCTING STATEMENT, AND COMPUTER SYSTEM HAVING THE FUNCTION THEREFOR - Provided is a computer system (08-20-2009
20080262818Creation of Clock and Data Simulation Vectors with Periodic Jitter - Methods for generating simulation vectors incorporating periodic jitter, or phase-shifted periodic jitter are disclosed. Periodic jitter, such as sinusoidal jitter, is preferably represented by a mathematical equation which defines the amount of jitter experienced at each cycle of a clock or data signal. The calculated periodic jitter for each cycle is used to form a new multi-cycle vector incorporating the jitter. If a particular signal to be simulated additionally needs to travel a particular distance such that it would experience a time delay, that time delay may also be incorporated into the jitter equation as a phase shift. So incorporating the time delay into the jitter equation allows for the easy simulation of circuits receiving the vectors without the need to actually design or “lay out” the circuits that imposing the time delay. This technique is particularly useful in efficient modeling, or optimization of, the clock distribution network and sample circuits used to receive data in a SDRAM integrated circuit.10-23-2008
20110224963Fast Photolithography Process Simulation to Predict Remaining Resist Thickness - A lithography model uses a transfer function to map exposure energy dose to the thickness of remaining photoresist after development; while allowing the flexibility to account for other physical processes. In one approach, the model is generated by fitting empirical data. The model may be used in conjunction with an aerial image to obtain a three-dimensional profile of the remaining photoresist thickness after the development process. The lithography model is generally compact, yet capable of taking into account various physical processes associated with the photoresist exposure and/or development process for more accurate simulation.09-15-2011
20090222250Hard/Soft Cooperative Verifying Simulator - The present invention provides a hard/soft cooperative verifying simulator based on a SystemC simulator, capable of reducing overhead of context switching control thereby to shorten processing time. Time keepers for controlling simulation times of a plurality of threads are provided corresponding to the threads generated as simulation models for hardware and software. Each of the time keepers has a variable which holds a simulation time for each thread, a variable which holds a summation time, and a break request queue which stores a break time and its corresponding break method therein. The time keeper manages both variables and the queue in response to six types of method invocations from the thread, and invokes a wait function of the SystemC simulator when necessary. It is thus possible to reduce the number of times that a wait function invocation is performed, and shorten the entire processing time.09-03-2009
20090222251Structure For An Integrated Circuit That Employs Multiple Interfaces - A design structure for a integrated circuit interfacing system may be embodied in a machine readable medium for designing, manufacturing or testing a integrated circuit. In one embodiment, the design structure specifies an integrated circuit that includes multiple interfaces. The design structure may specify that each of the interfaces couples to a respective set of registers or storage elements on the integrated circuit. The design structure may also specify a bridge circuit on the integrated circuit that switchably couples the two interfaces together such that one interface may communicate with the registers that associate with that interface as well as the registers that associate with the other interface.09-03-2009
20090248384PROCESS CONTROL SYSTEM IN AN AUTOMATION INSTALLATION - A process control system is disclosed in an automation installation having field devices which are networked by means of a system bus and which can be operated using associated system control units which are connected by means of a terminal bus to at least one central engineering computer for configuring the system and to a central control station for monitoring and operating the system. For the purpose of linking at least one extraneous control unit to the terminal bus an interposed control computer is proposed which, under software control, simulates a system-compliant I/O unit on the terminal bus, which I/O unit is bi-directionally connected to an OPC client residing on the extraneous control unit.10-01-2009
20090248385SIMPLIFIED DATA SIGNAL SUPPORT FOR DIAGRAMMING ENVIRONMENT LANGUAGES - In a graphical modeling environment, bus signals, which group a plurality of signals together for simplifying a model, include a partial or complete physical definition. Models are simplified by passing bus signals through graphical objects representing functional entities, without degrouping the bus signal. During simulation of the model, code can be generated for the bus signal having a complete definition independent of other components of the graphical model.10-01-2009
20090177456Mixed Decoupled Electromagnetic Circuit Solver - In a method, system and computer readable medium for determining a composite circuit model of a 3D geometry, first and second sides of an analytical model of the 3D geometry are discretize into first and second surface and/or volume meshes. For each mesh, a current that flows in each cell thereof and the a voltage induced in the cell in response to the application of an exemplary bias to the geometry are determined. For each mesh, from the currents flowing in the cells thereof and voltages induced in the cells thereof, a corresponding circuit model is determined. The circuit models of the meshes are then combined to form a composite circuit model for the geometry.07-09-2009
20100153086SYSTEM FOR CREATING PARAMETER INFORMATION, SYSTEM FOR ESTIMATING YIELDS, PROGRAM AND RECORDING MEDIUM - The simulation information creating part 06-17-2010
20090248383BITCELL SIMULATION DEVICE AND METHODS - A method of simulating operation of a bitcell includes determining sensitivities of a bitcell model to different component characteristics and device parameters, such as device temperature, operating voltage, and process characteristics. The determined sensitivities are normalized, so that each normalized value represents the relative sensitivity of the bitcell, under the simulated device parameters, to the component characteristic associated with the value. The normalized sensitivity values can be scaled based on a tolerance factor, and the adjusted sensitivities used to model the behavior of each component of the bitcell in subsequent simulations.10-01-2009
20100161304METHOD OF INTERCONNECT CHECKING AND VERIFICATION FOR MULTIPLE ELECTROSTATIC DISCHARGE SPECIFICATIONS - A method for designing a semiconductor device circuit comprising a electrostatic discharge (ESD) protection circuit can include device simulations using at least one, for example two or more ESD models, and designing device features such that they are resilient to damage from the two or more ESD testing models.06-24-2010
20100262413COMPENSATING FOR VARIATIONS IN DEVICE CHARACTERISTICS IN INTEGRATED CIRCUIT SIMULATION - According to a method of simulation data processing, a difference is determined between a simulated value of a characteristic for a simulated integrated circuit device and a corresponding empirical value of the characteristic for a fabricated integrated circuit device. A data structure containing a simulation model of the fabricated integrated circuit device is accessed, where the data structure includes a plurality of entries each accessed via a unique index and an index used to access the data structure is offset in accordance with the difference between the simulated value and the empirical value. Operation of the simulated integrated circuit device is then simulated utilizing a value obtained from one of the plurality of entries of the data structure. Results of the simulation are stored in a data storage medium.10-14-2010
20100049495METHOD AND APPARATUS FOR THE SIMULTANEOUS MULTI-LEVEL AND/OR MULTI-SIMULATOR DESIGN OPTIMIZATION OF ELECTRONIC CIRCUITS - The present invention relates to a system for synthesizing an electronic circuit at plural abstraction levels. The system includes one or more evaluation tools for evaluating the performance and/or behavior of the circuit at the abstraction levels. The system further includes means for passing parameters and/or performances between abstraction levels and/or evaluation tools. The system is adapted for evaluating the performance and/or behavior of the circuit using at least part of the passed parameters and/or performances at a plurality of the abstraction levels within one synthesis iteration.02-25-2010
20100262415METHOD OF VERIFYING THE PERFORMANCE MODEL OF AN INTEGRATED CIRCUIT - A method of verifying a performance model of an integrated circuit is provided. The method comprises the following steps: obtaining statistical request numbers and corresponding latency values of memory access requests; developing functions of latency value based on the statistical request numbers and the corresponding latency values; bringing a random value to one of the functions to retrieve a latency value; and verifying the logic of the performance model using the latency value retrieved in the step above.10-14-2010
20100262412INTEGRATED CIRCUIT MODELING BASED ON EMPIRICAL TEST DATA - In accordance with one embodiment, a plurality of empirical measurements of a fabricated integrated circuit including a fabricated transistor having multiple terminals is received. The plurality of empirical measurements each include an empirical terminal current set and an empirical terminal voltage set for the terminals of the fabricated transistor. A mathematical simulation model of a simulated transistor is also received. Utilizing the mathematical simulation model, an intermediate data set is calculated by determining, for each of a plurality of different terminal voltage sets, a simulated terminal current set and a simulated terminal charge set. A modeling tool processes the intermediate data set to obtain a time domain simulation model of the fabricated transistor that, for each of the plurality of empirical measurements, provides a simulated terminal charge set. The time domain simulation model is stored in a computer-readable data storage medium.10-14-2010
20080215303Method, Apparatus and Program for Creating a Power Pin Model of a Semiconductor Integrated Circuit - A method of creating a power pin model of an LSI having appropriate analysis accuracy in consideration of information on positions within the LSI is provided. A divided cell size decision unit automatically decides a divided cell size of the LSI from power supply circuit network wire information, transistor structure information, analysis frequency information, size information, and element arrangement information of the LSI as well as from a semiconductor integrated circuit entire power pin model. A model creation unit allocates a model of an active section and a model of an internal capacitance section, including the positional information, within the LSI to the cells at an appropriate proportion, and a model coupling unit couples the models in each cell to create a power pin model of the LSI. Here, the size of each divided cell is determined to be electrically sufficiently smaller than a wavelength corresponding to an upper limit analysis frequency derived from power supply circuit network wire information, transistor structure information, and analysis frequency information.09-04-2008
20080215304COHERENT STATE AMONG MULTIPLE SIMULATION MODELS IN AN EDA SIMULATION ENVIRONMENT - A circuit design is simulated in a simulation environment. When a simulation model in the simulation environment transfers state information to a second simulation model, the simulation environment receives the state information and makes it available to the second simulation model without simulating the transfer through the simulated circuit design.09-04-2008
20100191518COMPACT ABBE'S KERNEL GENERATION USING PRINCIPAL COMPONENT ANALYSIS - Some embodiments provide techniques for determining a set of Abbe's kernels which model an optical system of a photolithography process. During operation, the system can receive optical parameters (e.g., numerical aperture, wavelength, etc.) for the photolithography process's optical system. Next, the system can use the optical parameters to determine a point spread function for an Abbe's source. Note that the point spread function for the Abbe's source can be determined either by discretizing the optical system's light source using a set of concentric circles, or by discretizing the optical system's light source in an orthogonal fashion. The system can then determine a correlation matrix from the point spread function. Next, the system can determine the set of Abbe's kernels by performing an eigen decomposition of the correlation matrix using principal component analysis. The system can then use the set of Abbe's kernels to compute image intensity.07-29-2010
20100241414DEBUGGING SIMULATION WITH PARTIAL DESIGN REPLAY - A virtual platform simulates behavior of a modular circuit based on a circuit design including both high-level and low-level models of circuit modules. A compiler that converts the high-level and low-level models into executable models prior to an initial simulation also generates a separate “replay engine” corresponding to each low-level module for use during subsequent replay simulations. During the initial simulation, the virtual platform simulates circuit behavior by concurrently executing the high-level and low-level executable models and recording data representing behavior of output signals of the low-level design modules modeled by the executable models. To speed up subsequent replays of the simulation, the virtual platform executes one or more of the replay engines in lieu of executing their corresponding low-level executable models. Each executed replay engine simulates behavior of each output signal of a corresponding low-level module in response to the data recorded during the initial simulation representing the behavior of that output signal.09-23-2010
20100241413METHOD AND SYSTEM FOR MODELING AN LDMOS TRANSISTOR - A processor with a computer program product embodied thereon for modeling an LDMOS transistor having a drift region is provided. Characteristic behavior of a CMOS transistor with its body coupled to its source is generated, and characteristic behavior of a resistor is generated, where the resistor is coupled to the drain of the CMOS transistor. Then to account for impact ionization, an impact ionization current for electrons in the drift region an impact ionization current for holes in the drift region are calculated.09-23-2010
20100211373CAPTURE OF INTERCONNECTIVITY DATA FOR MULTI-PIN DEVICES IN THE DESIGN OF EMULATOR CIRCUIT BOARDS - Capturing interconnectivity data for one or more multi-pin devices in the design of emulator circuit boards is automated using a translator that extracts relevant information, from a text-based input/output (I/O) definition file. The I/O definition file contains textual descriptions of I/O connectivity information for the various devices created by partitioning the design for application on the emulator circuit board, undefined connector interface entries, and design-specific information. The translator parses through the I/O definition file extracting the I/O connectivity and design-specific information, and retrieves connector interface definitions for the undefined connector interface entries using vendor data.08-19-2010
20100125440Method and Apparatus for Circuit Simulation - A method of preparing a circuit simulator, said method comprising initializing a normalized adjusted gate voltage value. Then performing the steps of determining a normalized adjusted gate voltage datum in dependence upon the initial normalized adjusted gate voltage value. Storing the normalized adjusted gate voltage datum at a memory address in a one-dimensional array based on the normalized adjusted gate voltage. Decrementing the normalized adjusted gate voltage value by a predetermined decrement amount. And verifying the decremented gate voltage value. Then repeating until a stop gate voltage value is reached.05-20-2010
20120143584COMPUTING DEVICE AND METHOD FOR ENFORCING PASSIVITY OF SCATTERING PARAMETER EQUIVALENT CIRCUIT - A computing device and a method for scattering parameter equivalent circuit reads a scattering parameter file from a storage device. A non-common-pole rational function of the scattering parameters in the scattering parameter file is created by applying a vector fitting algorithm to the scattering parameters. Passivity of the non-common-pole rational function is enforced if the non-common-pole rational function does not satisfy a determined passivity requirement.06-07-2012
20120143583SYSTEM-LEVEL EMULATION/VERIFICATION SYSTEM AND SYSTEM-LEVEL EMULATION/VERIFICATION METHOD - A system-level emulation/verification system includes an operating device for using a simulator to set soft intellectual properties (soft IPs) corresponding to a System-on-Chip (SOC) design module, executing a simulation corresponding to the SOC design module, and using a transactor to interact with the simulator via an Application Programming Interface (API); and a hard-wired based platform, including a hard IP corresponding to a soft IP of the SOC design module, wherein the hard-wired based platform sets the hard IP according to a setting of the SOC design module, and outputs an operating result of the hard IP corresponding to the setting of the SOC design module. The hard-wired based platform executes an IP model proxy for receiving an output of the transactor, transmitting the output to the hard-wired platform for controlling the operation of the hard IP, and transmitting the operating result to the transactor executed by the operating device.06-07-2012
20090326900SETTINGS EMULATOR FOR A CIRCUIT INTERRUPTER TRIP UNIT AND SYSTEM INCLUDING THE SAME - A settings emulator for a circuit breaker trip unit includes a handheld enclosure and a plurality of adjustable rotary switches mounted on the handheld enclosure. The adjustable rotary switches define a plurality of different trip settings for the circuit breaker trip unit. A communication channel is also mounted on the handheld enclosure. A microprocessor is enclosed by the handheld enclosure. The processor reads the different trip settings from the adjustable rotary switches and communicates the different trip settings through the communication channel to the circuit breaker trip unit.12-31-2009
20090319252METHOD AND APPARATUS FOR EXTRACTING ASSUME PROPERTIES FROM A CONSTRAINED RANDOM TEST-BENCH - One embodiment of the present invention provides systems and techniques to extract assume properties from a constrained random test-bench. During operation, the system can receive a constrained random test-bench for verifying the design-under-test (DUT), wherein the constrained random test-bench includes a statement which assigns a random value to a random variable according to a constraint. Next, the system can modify the constrained random test-bench by replacing the statement with another statement which assigns a free input variable's value to the random variable. The system can also add a statement to the constrained random test-bench that toggles a marker variable to localize the scope of the statement. The system can then generate an assume property which models the constraint on the free input variable. The assume property can then be used by a formal property verification tool to verify the DUT.12-24-2009
20090319250SYSTEM, METHOD AND APPARATUS FOR SENSITIVITY BASED FAST POWER GRID SIMULATION WITH VARIABLE TIME STEP - A system and method of analyzing a power grid in an integrated circuit includes inputting a circuit design to a test bench, inputting a plurality of initial values for the circuit design in to the test bench, setting a current time t to 0 value for an initial time (t12-24-2009
20090210212Validating One or More Circuits Using One or More Grids - In one embodiment, a method includes simulating by one or more computer systems a larger circuit to assign one or more values to one or more latch variables associated with the larger circuit, generating by the one or more computer systems one or more reduced circuits from the larger circuit according to the values assigned to the latch variables, generating by the one or more computer systems a transition relation (TR) for each reduced circuit, and generating by the one or more computer systems an initial state set for one or more instances of validation on the reduced circuits according to the TRs.08-20-2009
20090319251Circuit Simulation Using Step Response Analysis in the Frequency Domain - A method for simulating a response of a circuit to an ESD input stimulus applied to the circuit includes the steps of: receiving a description of the circuit into a circuit simulation program, the circuit including at least one mutual inductance element indicative of magnetic coupling in the circuit; generating a linear approximation of nonlinear elements in the circuit at respective DC bias points of the nonlinear elements; obtaining a frequency domain transfer function of the circuit; obtaining a time domain impulse response of the circuit as a function of the frequency domain transfer function; integrating the time domain impulse response to yield a step response of the circuit, the step response being indicative of a response of the circuit to the ESD input stimulus; and analyzing the step response of the circuit to determine whether the circuit will operate within prescribed parameters corresponding to the circuit.12-24-2009
20090112554Test Bench, Method, and Computer Program Product for Performing a Test Case on an Integrated Circuit - The disclosure relates to a test bench, method, and computer program product for performing a test case on an integrated circuit. The test bench may comprise a simulation environment representing an environment for implementing the integrated circuit and a reference model of the integrated circuit, wherein the reference model may be prepared for running within the simulation environment. The test bench may further comprise a device for running a simulation on the reference model within the simulation environment. The reference model may be based on an original reference model provided for a formal verification.04-30-2009
20090112552Method, System and Program Product for Reporting Temporal Information Regarding Count Events of a Simulation - At a simulation client, a design is simulated utilizing a hardware description language (HDL) simulation model by stimulating the HDL simulation model with a testcase. The HDL simulation model includes instrumentation not forming a portion of the design that includes a plurality of count event counters that count occurrences of count events in the design during stimulation by the testcase. At multiple intervals during stimulation of the HDL simulation model by the testcase, the simulation client records count values of the plurality of count event counters. The simulation client determines, for each of the multiple intervals, a temporal statistic regarding the count values of the plurality of count event counters and outputs a report containing temporal statistics for the multiple intervals.04-30-2009
20090112550System and Method for Generating a Worst Case Current Waveform for Testing of Integrated Circuit Devices - A system and method for generating a worst case current waveform for testing of integrated circuit devices are provided. Architectural analysis of an integrated circuit device is first performed to determine an initial worst case power workload to be applied to the integrated circuit device. Thereafter, the derived worst case power workload is applied to a model and is simulated to generate a worst case current waveform that is input to an electrical model of the integrated circuit device to generate a worst case noise budget value. The worst case noise budget value is then compared to measured noise from application of the worst case power workload to a hardware implemented integrated circuit device. The worst case current waveform may be selected for future testing of integrated circuit devices or modifications to the simulation models may be performed and the process repeated based on the results of the comparison.04-30-2009
20090112549TECHNIQUES FOR GENERATING AND SIMULATING A SIMULATABLE VECTOR HAVING AMPLITUDE NOISE AND/OR TIMING JITTER ADDED THERETO - Methods for generating realistic waveform vectors with controllable amplitude noise and timing jitter, simulatable in a computer-based simulation environment are disclosed. In one implementation, a transition vector is created from a sequence of bits having a rise time and a fall time, in which the transition vector comprises voltage values at timings corresponding to midpoints of transitions in the bit sequence. A jittered transition vector is created from the transition vector, in which the timing of the transitions in the jittered transition vector include timing jitter. An upscaled jittered transition vector is then formed having additional points, in which at least some of the additional points comprise corners of the sequence of bits. The voltages of the additional points are set by the sequence of bits, and the timing of the corners are set in accordance with the rise time and the fall time. Although this resulting vector can be simulated, this vector can also be re-sampled to produce a new simulatable vector in which the voltages are separated by a constant time step.04-30-2009
20090112556RECONSTRUCTION OF DATA FROM SIMULATION MODELS - Systems, method, and media for reconstructing data from simulation models are disclosed. Embodiments may include a method for accessing an alias from an alias file. The method may generally include searching for a net name and, if the net name is not found, searching an alias index file for an alias index entry associated with the net name, the alias index entry having a net name and an associated position. The method may also generally include, if the net name entry is found, accessing from an alias file an alias associated with the net name. A further embodiment may generally include receiving a net name and a position of an alias in the alias file, creating an alias index entry for the alias having a net name and the position of the alias, and storing the created alias index entry in the alias index file.04-30-2009
20090112553DISPLAY DESIGN SYSTEM AND METHOD - An LCD display design system and method are disclosed. The method includes performing operations by a variety of operation modules after initial parameters are input and an operation type is selected, so as to generate operation results and transfer the operation results to an integration module; integrating the operation results by an integration module to generate a correspondence relation such as an operation window, a compare-table or an equation, and further transferring the operation results and the correspondence relation to an output module such that the output module can display performance variations of a variety of designs corresponding to the different initial parameters. Therefore, the present invention provides a user with a convenient way to obtain optimal design parameters for designing a display pixel circuit.04-30-2009
20080270100Method, Apparatus, and Computer Program Product for Implementing Optimized Channel Routing With Generation of FIR Coefficients - A method, apparatus and computer program product implement optimized channel routing in an electronic package design. Electronic package physical design data are received. A physical design including a netlist including a plurality of nets is generated. Finite impulse response (FIR) driver coefficients are determined for each net in the netlist from simulation with generation of impulse responses of the netlist.10-30-2008
20090106009RECONSTRUCTION OF DATA FROM SIMULATION MODELS - Systems and media for reconstructing data from simulation models are disclosed. Embodiments may include a media containing instructions for accessing an alias from an alias file. The media may include instructions for searching for a net name and, if the net name is not found, searching an alias index file for an alias index entry associated with the net name, the alias index entry having a net name and an associated position. The instructions may also include, if the net name entry is found, instructions for accessing from an alias file an alias associated with the net name. A further embodiment may include instructions for receiving a net name and a position of an alias in the alias file, creating an alias index entry for the alias having a net name and the position of the alias, and storing the created alias index entry in the alias index file.04-23-2009
20130138417METHODS, SYSTEMS, AND COMPUTER-READABLE MEDIA FOR MODEL ORDER REDUCTION IN ELECTROMAGNETIC SIMULATION AND MODELING - Methods, systems, and computer readable media are disclosed for simulating a circuit. The method may comprise a step of providing a network model of the circuit having a plurality of ports, the plurality of ports being associated with one or more net pairs. The method may also comprise combining the plurality of ports into one or more groups based on the net pairs, each group corresponding to a net pair. In addition, the method may comprise calculating, for each group, one or more expansion elements, wherein the one or more expansion elements are associated with a shared property among all ports of the group. Moreover, the method may comprise simulating the circuit using a combination of the expansion elements calculated for each group.05-30-2013
20130144589SYSTEMS AND METHODS FOR CIRCUIT DESIGN, SYNTHESIS, SIMULATION, AND MODELING - Systems and methods for specifying, modelings simulating, and implementing a circuit design using a circuit design database comprising re-usable program elements to represent circuit design elements. The re-usable program elements may be used to build an overall circuit design description in the database. In example embodiments, the circuit design may be structured as a computer program and library to deterministically specify the circuit design elements to be used. Circuit synthesis functionality and circuit simulation functionality may be embedded as part of the re-usable program elements. Libraries may be compiled with the computer program instructions specifying the circuits to generate an executable that can be used for synthesis and simulation The combined executable code may be executed on an instruction set processor directly or through an interpreter.06-06-2013
20100332206METHOD FOR SIMULATING LEAKAGE DISTRIBUTION OF INTEGRATED CIRCUIT DESIGN - A method is provided for simulating leakage distribution of integrated circuit design. The method analyzes a layout of the integrated circuit design to understand the groups of dimensions of the transistors and capacitors of the layout, and then simulates a leakage distribution of the layout resulted from possible fabrication process variations. Therefore, designer can know the leakage distribution of the integrated circuit design before the integrated circuit design is actually fabricated, and modify the layout if a leakage failure happens to the layout.12-30-2010
20100332207VIA IMPEDANCE MATCHING METHOD - A via impedance matching method is provided. Firstly, a circuit model of a via in the PCB is created, which comprises a low pass filter circuit composed of two capacitors connected in parallel and an inductor connected between the two capacitors. Then, S parameters of the via by analyzing the circuit model is obtained and converted to an ABCD matrix, and parameters of an ideal low pass filter model is obtained by equaling an ABCD matrix of the ideal low pass filter model to the ABCD matrix with the S parameters. Then, impedance matching parameters are calculated according to the parameters of the ideal low pass filter model. Finally, proper capacitors and inductors are selected and disposed on the PCB to match the via.12-30-2010
20110029299Hierarchical Order Ranked Simulation Of Electronic Circuits - A method of simulating an integrated circuit design is provided. In this method, a node order ranking of nodes in a netlist can be determined. Circuits of the netlist can then be partitioned based on the node order ranking with both static current driving and dynamic current driving schemes. A hierarchical data structure can be built based on the node order partitioning. In one embodiment, intermediate node orders can be dynamically merged for simulation optimization. Then, the circuits can be re-partitioned based on one or more merged intermediate node orders. Solving and integration can be performed using the hierarchical data structure to generate an order-ranked hierarchy engine. Analysis on the order-ranked hierarchy engine can be performed. At this point, simulation data of the IC design can be exported based on the analysis. By using this method, linear network reduction with its attendant accuracy loss is unnecessary.02-03-2011
20110082681COUPLED ANALYSIS SIMULATION APPARATUS AND COUPLED ANALYSIS SIMULATION METHOD - A coupled analysis simulation apparatus includes a coupled analysis processing unit configured to perform coupled analysis by performing electromagnetic field analysis and circuit analysis in coordination with each other, the electromagnetic field analysis being performed on a space including conductive layers to which an electronic circuit module is connected, the circuit analysis being performed on the electronic circuit module; a first generating unit configured to generate a virtual conductive part in a section or a region including connection parts connecting the electronic circuit module with the conductive layers; and a second generating unit configured to generate virtual connection parts that virtually connect the virtual conductive part with the conductive layers at positions where the connection parts are connected to the conductive layers.04-07-2011
20110087478Systems and Methods of Efficient Library Characterization for Integrated Circuit Cell Libraries - A method of efficient library characterization of a circuit of a logic gate having a plurality of transistors and a plurality of nodes defining interconnection points in the circuit is disclosed. The method includes determining a plurality of vectors for a plurality of arcs. Each of the plurality of vectors represents possible data bits to inputs and nodes of the logic gate. The method selects a plurality of substantially distinct vectors from the plurality of vectors for each of the plurality of arcs, and performs circuit pruning for each of the plurality of substantially distinct vectors, taking each one substantially distinct vector at a time. The circuit pruning includes identifying an active circuit for each vector. The active circuit is identified by determining which circuit features are activated when applying a particular one of the substantially distinct vectors. Then, the circuit simulations limited to a plurality of transistors in the active circuit are performed. The circuit pruning and circuit simulations are repeated for remaining ones of the plurality of substantially distinct vectors. The results of the circuit simulations are then stored on a non-volatile compute readable media, for each active circuit corresponding to each of the plurality of substantially distinct vectors.04-14-2011
20120245916CONVEYING DATA FROM A HARDWARE DEVICE TO A CIRCUIT SIMULATION - A system and method is described for connecting a logic circuit simulation to a hardware peripheral that includes a computer running software for communicating data to and from the hardware peripheral. The software transmits the data received from the hardware peripheral to the device being simulated by the logic circuit simulation. The computer also transmits the data received from the device being simulated by the electronic circuit simulation to the hardware peripheral. This allows the user to test the device being simulated using real hardware for input and output instead of simulated hardware.09-27-2012
20100131259IN-SITU DESIGN METHOD AND SYSTEM FOR IMPROVED MEMORY YIELD - A system and method for designing integrated circuits includes determining a target memory module for evaluation and improvement by evaluating performance variables of the memory module. The performance variables are statistically simulated over subset combinations of variables based on pin information for the module. Sensitivities of performance on yield to the variables in the subset combinations are determined. It is then determined whether yield of the target module is acceptable, and if the yield is not acceptable, a design which includes the target module is adjusted in accordance with the sensitivities to adjust the yield.05-27-2010
20090216515Using a serial profiler to estimate the performance of a parallel circuit simulation - Some embodiments of the present invention provide a system that profiles a serial simulation of a circuit to estimate the performance of a parallel simulation of the circuit. During operation, the system profiles execution of module instances during a serial simulation of the circuit, wherein each module instance includes code which simulates signal propagation through a corresponding circuit module. Next, the system uses execution times for the module instances obtained from the serial simulation to estimate the performance of a parallel simulation of the circuit.08-27-2009
20090216514RESOURCE REMAPPING IN A HARDWARE EMULATION ENVIRONMENT - A system and method is disclosed in an emulation environment that dynamically remaps user designs. In one embodiment, a request is received to load an integrated circuit design to be emulated in a desired partition within the emulator. The emulator automatically determines the availability of the partition requested. If the partition is not available, the design is dynamically remapped to a different partition that is available. In another embodiment, clocks associated with the integrated circuit design are also dynamically remapped. In yet another embodiment, the user can control the size of the partitions (e.g., the number of printed circuit boards in a partition).08-27-2009
20090216512Method and apparatus for indirectly simulating a semiconductor integrated circuit - A method and an apparatus for indirectly simulating a semiconductor integrated circuit (IC) are described. A circle chain is formed using input pins and output pins to provide an intellectual property (IP) core model that substitutes for a real IP core circuit. A test bench for the IP core model is generated, the semiconductor IC that includes the IP core model is integrated using the generated test bench, and the semiconductor IC is simulated.08-27-2009
20100057426Logic Design Modeling and Interconnection - A dynamic reconfigurable interconnect network architecture in a logic simulation system that interconnects a plurality of simulation engines together, providing a high degree of interconnectivity in an efficient manner. The logic simulation system may create and manage linkable sub-programs for execution by a simulation engine. The logic simulation system may schedule various tasks in a design to be simulated, including horizontal and vertical partitioning of the design and determination of an order in which events such as clock edges and asynchronous signals are to be implemented by a logic simulation system.03-04-2010
20120203532Method for Dynamically Switching Analyses and For Dynamically Switching Models in Circuit Simulators - Performing a transient analysis with a compact FET model that is predominantly intended for DC analysis, such as an IDDQ leakage model, to enable toggling logic states in sequential logic circuits that cannot otherwise be examined in a DC analysis. An embodiment enables examining the DC or AC conditions of any logic state of any logic circuit in a DC or AC analysis, and additionally, it eliminates a potentially long execution time of a transient analysis with a DC model. Further solved is the present need to run two simulations and to maintain two netlists in order to overcome being unable to toggle certain logic states in the DC analysis. The invention achieves the aforementioned in a single simulation with a single netlist that calculates the DC operating circuit conditions with a model A on the fly at predetermined times or in certain logic states, during a transient analysis with a model B.08-09-2012
20110040548PHYSICS-BASED MOSFET MODEL FOR VARIATIONAL MODELING - A method of optimizing MOSFET device production which includes defining key independent parameters, formulating those key independent parameters into a canonical variational form, calculating theoretical extracted parameters using at least one of key independent parameters in canonical variational form, physics-based analytical models, or corner models. The method also includes calculating simulated characteristics of a device using the key independent parameters and extracting target data parameters based on at least one of measured data and predicted data, comparing the simulated characteristics to the target data parameters, and modifying the theoretical extracted parameters or key independent parameters in canonical form as a result of the comparison. Then, calculating and outputting the simulated characteristics based on the modified theoretical extracted parameters and the modified key independent parameters in canonical form.02-17-2011
20110153304CIRCUIT SIMULATION APPARATUS AND TRANSIENT ANALYSIS METHOD FOR PERFORMING TRANSIENT ANALYSIS - A storage section stores a netlist representing a test object circuit. An extracting section extracts, from the netlist stored in the storage section, a subnetlist representing a periodic circuit which is included in the test object circuit and which outputs a periodic output signal corresponding to a periodic input signal. An analyzing section performs transient analysis of the periodic circuit represented by the subnetlist extracted by the extracting section, for one period of the periodic output signal outputted by the periodic circuit. A simulation section performs transient analysis of the test object circuit represented by the netlist stored in the storage section on the basis of the result of the analysis performed by the analyzing section.06-23-2011
20100262414METHODOLOGY FOR CORRELATED MEMORY FAIL ESTIMATIONS - Correlated failure distribution for memory arrays having different groupings of memory cells is estimated by constructing memory unit models for the groupings based on multiple parameters, establishing failure conditions of the memory unit model using fast statistical analysis, calculating a fail boundary of the parameters for each memory unit model based on its corresponding failure conditions, and constructing memory array models characterized by the fail boundaries. Operation of a memory array model is repeatedly simulated with random values of the parameters assigned to the memory cells and peripheral logic elements to identify memory unit failures for each simulated operation. A mean and a variance is calculated for each memory array model, and an optimal architecture can thereafter be identified by selecting the grouping exhibiting the best mean and variance, subject to any other circuit requirements such as power or area.10-14-2010
20110153303Static IR (voltage) drop Analyzing Apparatus and Associated Method - A static voltage drop analyzing apparatus applied to a Multi-Threshold Complementary Metal-Oxide-Semiconductor (MTCMOS) transistor is provided. The static voltage drop analyzing apparatus includes a calculating module, a processing module, and a measuring module. The calculating module calculates a voltage drop tolerance according to the voltage drop characteristic of the MTCMOS transistor. The processing module selects a simulation metal layer corresponding to the voltage drop tolerance from a plurality of candidate simulation metal layers, and adds the simulation metal layer into the MTCMOS transistor. The measuring module measures the voltage drop of the simulation metal layer added into the MTCMOS transistor. The measured voltage drop of the simulation layer added into the MTCMOS is substantially the static voltage drop of the MTCMOS transistor.06-23-2011
20090210210METHOD OF ACCURATE PREDICTION OF ELECTROSTATIC DISCHARGE (ESD) PERFORMANCE IN MULTI-VOLTAGE ENVIRONMENT - The present invention relates generally to semiconductor wafer fabrication and more particularly but not exclusively to predictive, pre-fabrication methodologies for determining inefficiencies in an integrated circuit (IC) design. The present invention, in one or more implementations, provides an effective pre-production methodology for predicting the efficiency and behavior of a designed ESD protective circuit and testing the ESD protective circuit with a simulated IC. The method of the present invention yields predictive results that have been comparatively tested.08-20-2009
20120203533Improper Voltage Level Detection in Emulation Systems - Method and apparatus for detecting an improper voltage levels between a hardware emulator and an auxiliary hardware device are provided. In various implementations, a voltage level detector is attached to a bus that connects an emulator with an auxiliary hardware device. Subsequently, the voltage level detector can be used to detect when operating conditions on the bus are outside specification. More specifically, when the voltage level on the bus falls outside a threshold level, the voltage level detector may be used to alert a user, pause operation of the emulator or both.08-09-2012
20080208554Simulator development system and simulator development method - A simulator development system is disclosed, including a data file management part to create a data file storing data concerning a plurality of types of integrated circuits, for each update and to manage the data file with a file name including a date and time when the data file is updated; and a simulator generation part to specify a latest data file from a plurality of the data files retrieved based on a type name, by referring to the date and time included in the file name in response to a selection of the type name of the integrated circuit, and to generate the simulator corresponding to the type of the integrated circuit, which type is specified by a type name.08-28-2008
20110054875Design Specifications-Driven Platform for Analog, Mixed-signal, and Radio Frequency Verification - A design specifications-driven platform (03-03-2011
20100292977SUPPORT COMPUTER PRODUCT, APPARATUS AND METHOD - A computer-readable recording medium stores therein a program causing a computer that accesses a simulator to execute receiving a measured yield distribution that expresses an actually measured yield distribution concerning leak current of a circuit-under-design, and model data for leak current of a cell of the circuit-under-design; providing the simulator with the model data and values for a normal distribution concerning variation components of the leak current of the cell; acquiring the leak current of the circuit-under-design; calculating, based on the acquired leak current, an estimated yield distribution concerning the leak current of the circuit-under-design; calculating values for the normal distribution that minimize error between the measured yield distribution and the estimated yield distribution; setting an initial value to the normal distribution and the calculated values for the normal distribution to the normal distribution; and outputting the estimated yield distribution that is based on the leak current of the circuit-under-design.11-18-2010
20110257954Versatile Method and Tool for Simulation of Aged Transistors - In an embodiment, an aging analysis tool may be configured to identify transistors that are expected to experience aging effects according to worst case stress vectors and/or designer identified worst case conditions. The aging analysis tool may modify a representation of the circuit (e.g. a netlist), replacing the identified transistors with aged transistors (e.g. by modifying parameters of the transistors in the netlist). The aging analysis tool may process the modified netlist over a range of conditions at which the circuit is expected to operate, to ensure that the design meets specifications after aging. The process may be repeated until the aged design meets specifications (with circuit modifications made by the designer to improve the design).10-20-2011
20110257953SIMULATION TOOL FOR HIGH-SPEED COMMUNICATIONS LINKS - A link simulation tool for simulating high-speed communications link systems is provided. Communications links may include link subsystems such as transmit (TX) circuitry, receive (TX) circuitry, oscillator circuits that provide reference clock signals to the TX and RX circuitry, and channels that link the TX and RX circuitry. The link simulation tool may model each of the subsystems using behavioral models. The behavioral models may include characteristic functions such as transfer functions, probability density functions, and eye characteristics. The link simulation tool may have a link analysis engine that is capable of performing two-dimensional (two-variable) convolution operations and in applying dual-domain (frequency-time) transformations on the characteristic functions provided by the behavioral models to simulate the performance of the link system. The link simulation tool may have an input screen that allows a user to specify desired link parameters and a data display screen that display simulated results.10-20-2011
20110071812Small-Signal Stability Analysis at Transient Time Points of Integrated Circuit Simulation - Simulation method and system for analyzing the stability of a modeled electronic circuit. Simulation of the transient response to a desired input stimulus is performed in a piece-wise fashion, in a sequence of transient time points. At one or more user-specified time points (“tpunch” points) within the transient interval, the state of the circuit in the transient response at that time point is applied to the model as if it were a DC operating point, and the small-signal stability of the circuit under those conditions is analyzed. Transient instability of the circuit is thus discovered by way of simulation, allowing the designer to determine the cause and cure of that instability.03-24-2011
20120150522CONVERSION OF CIRCUIT DESCRIPTION TO AN ABSTRACT MODEL OF THE CIRCUIT - A system and method is disclosed for converting an existing circuit description from a lower level description, such as RTL, to a higher-level description, such as TLM, while raising the abstraction level. By changing the abstraction level, the conversion is not simply a code conversion from one language to another, but a process of learning the circuit using neural networks and representing the circuit using a system of equations that approximate the circuit behavior, particularly with respect to timing aspects. A higher level of abstraction eliminates much of the particular implementation details, and allows easier and faster design exploration, analysis, and test, before implementation. In one aspect, a model description of the circuit, protocol information relating to the circuit, and simulation data associated with the lower level description of the circuit are used to generate an abstract model of the circuit that approximates the circuit behavior.06-14-2012
20110125480COMPUTER PRODUCT, ANALYSIS SUPPORT APPARATUS, AND ANALYSIS SUPPORT METHOD - A non-transitory, computer-readable recording medium stores therein a program causing a computer to execute calculating, using respective standard deviations of first delay distributions of delay variation independent to each element included in a path among parallel paths in a circuit, standard deviation of a first delay distribution of the path when modeled as a series circuit; correcting the standard deviation of the first delay distribution for each element, using the calculated standard deviation of the first delay distribution of the path and a standard deviation of a first delay distribution of the path obtained by a statistical delay analysis on the circuit; obtaining a correlation distribution representing a correlation between delay and leak current of the circuit by executing, using the corrected standard deviation of the first delay distribution for each element, correlation analysis between delay and leak current of the target circuit; and outputting the obtained correlation distribution.05-26-2011
20100324880Techniques for Processor/Memory Co-Exploration at Multiple Abstraction Levels - Processor/memory co-exploration at multiple abstraction levels. An architecture description language (ADL) description of a processor/memory system is accessed. The ADL description models on one of a plurality of abstraction levels. The abstraction levels may include a functional (or bit-accurate) level and a cycle-accurate level. Further, a communication protocol for the processor/memory system is accessed. The communication protocol is formed from primitives, wherein a memory interface formed from the primitives is useable in simulation at the abstraction levels. A processor/memory simulation model is automatically generated from the description and description of the communication protocol. The processor/memory simulation model comprises a processor/memory interface comprising the primitives and based on the communication protocol. The memory interface allows simulation of the processor/memory on the appropriate abstraction level for the simulation. For example, the processor/memory interface may be a functional interface or a cycle-accurate interface.12-23-2010
20100324878METHODS, SYSTEMS, AND COMPUTER PROGRAM PRODUCT FOR IMPLEMENTING HOTSPOT DETECTION, REPAIR, AND OPTIMIZATION OF AN ELECTRONIC CIRCUIT DESIGN - Disclosed are a method, a system, and a computer program product for implementing hotspot detection, repair, and optimization of an electronic circuit design, which, in some embodiments, defines, identifies criteria for hotspots/metrics or optimization objective function; performs the initial hotspot or metric prediction; identifies correction candidate(s); applies a correction candidate to the electronic circuit design; and determines whether the outcome of applying the correction candidate is acceptable. The method or the system identifies custom correction candidate(s) or custom command(s) and identifies one or more hints for the predicted hotspots or metrics; provides a single architecture to use a first model for hotspot identification/correction and a second model for design check; and provides the capability to apply a correction for a hotspot or metric, evaluate the effectiveness of the correction on the fly, and revert any changes made to the electronic circuit design by the correction.12-23-2010
20090171644CA RESISTANCE VARIABILITY PREDICTION METHODOLOGY - A methodology for obtaining improved prediction of CA resistance in electronic circuits and, particularly, an improved CA resistance model adapted to capture larger than anticipated “out of spec” regime. In one embodiment, a novel bucketization scheme is implemented that is codified to provide a circuit designer with considerably better design options for handling large CA variability as seen through the design manual. The tools developed for modeling the impact of CA variable resistance phenomena provide developers with a resistance model, such as conventionally known, modified with a new CA model Basis including a novel CA intrinsic resistance model, and, a novel CA layout bucketization model.07-02-2009
20100121628INTEGRATED CIRCUIT VERIFICATION DEVICE AND METHOD - An integrated circuit verification device includes a trace-back unit having structure data of an integrated circuit to be verified, and configured to trace back nodes of the integrated circuit in a direction from an output node to an input node; and a state defining unit having data with respect to a target state of the output node of the integrated circuit, and configured to sequentially define states of back-traced nodes to satisfy the target state of the output node.05-13-2010
20120310619FAST FUNCTION EXTRACTION - For application to analog, mixed-signal, and custom digital circuits, as well as other fields have use for high-dimensional regression, or symbolic modeling, a system and method to extract functions, where each function relates a set of input variables to an output variable (performance metric). The technique enumerates a large set of candidate basis functions, performs pathwise regularized learning on those basis functions to generate a set of candidate models, and finally performs nondominated filtering to identify models that trade off complexity versus error.12-06-2012
20110082680COMPACT MODEL FOR DEVICE/CIRCUIT/CHIP LEAKAGE CURRENT (IDDQ) CALCULATION INCLUDING PROCESS INDUCED UPLIFT FACTORS - A system, method and computer program product for implementing a quiescent current leakage specific model into semiconductor device design and circuit design flows. The leakage model covers all device geometries with wide temperature and voltage ranges and, without the need for stacking factor calculations nor spread sheet based IDDQ calculations. The leakage model for IDDQ calculation incorporates further parasitic and proximity effects. The leakage model implements leakage calculations at different levels of testing, e.g., from a single device to a full chip design, and are integrated within one single model. The leakage model implements leakage calculations at different levels of testing with the leverage of a single switch setting. The implementation is via a hardware definition language code or object oriented code that can be compiled and operated using a netlist of interest, e.g., for conducting a performance analysis.04-07-2011
20100223043Electromagnetic Field Simulation Apparatus and Computer Readable Storage Medium Storing Electromagnetic Field Simulation Program - A computer readable storage medium storing an electromagnetic field simulation program that causes a computer to execute receiving data defining, in virtual space, a shape of a conductor and an insulator included in a conductive layer and a dielectric layer of a printed circuit board; setting a plurality of cells in the virtual space by arranging nodes of the cells on a boundary between the conductive layer and the dielectric layer in a thickness direction of the printed circuit board and by arranging nodes of the cells at regular intervals in a plane parallel to the printed circuit board; giving, to each of the cells, an electric constant of a medium occupying an area of each of the cells; and determining a change over time in a an electromagnetic field strength in each of the cells.09-02-2010
20090292519Circuit simulating apparatus and method thereof - A circuit simulating apparatus includes a block dividing unit that divides a logic circuit into a plurality of partial circuits; a pattern generating unit that generates a simulation-purpose pattern to an input terminal of the partial circuit; and a phase-difference setting unit that sets a phase difference between input simultaneously-changing signals as phase-difference setting information for each input terminal of the analysis-target circuit. The apparatus also includes a signal-waveform generating unit that generates a simulation signal waveform reflecting the phase difference for each input terminal of the analysis-target circuit; and a simulation performing unit that receives an input of the simulation signal waveform for each input terminal of the analysis-target circuit to obtain a timing analysis result of the analysis-target circuit based on the input result.11-26-2009
20110191092PARALLEL SIMULATION USING MULTIPLE CO-SIMULATORS - A method includes accepting a simulation task for simulation by a simulator that controls multiple co-simulators. Each of the multiple co-simulators is assigned to execute one or more respective sub-tasks of the simulation task. The simulation task is executed by invoking each co-simulator to execute the respective assigned sub-tasks.08-04-2011
20110191091Extremely Compact Table Lookup Method for Fast and Accurate Physics Based Models for SPICE-Like Simulators - Techniques for electronic circuit design simulation are provided. In one aspect, a method for electronic circuit design simulation includes the following steps. A model (e.g., a physics-based model) of the circuit design is created. Error tables are created containing data related to one or more regions of the circuit design. The model is modified with data from the error tables. The modified model is used to simulate the circuit design.08-04-2011
20100185431CIRCUIT VERIFICATION DEVICE, METHOD, AND PROGRAM STORAGE MEDIUM - A circuit verification device includes a simulation section and a determination section. The simulation section performs a first simulation using a first net list and a second simulation using a second net list. The first net list includes a size parameter of the pair of transistors and, in the first net list, an instance parameter of a first transistor is specified as +P and an instance parameter of a second transistor is specified as −P, and the second net list includes the same size parameter as in the first net list and, in the second net list, the instance parameter of the first transistor is specified as −P and the instance parameter of the second transistor is specified as +P. The value of P is set at α, which is ½ the control upper limit of mismatch of the threshold voltage between the pair transistors.07-22-2010
20110307235EQUIVALENT CIRCUIT MODEL FOR MULTILAYER CHIP CAPACITOR, CIRCUIT CONSTANT ANALYSIS METHOD, PROGRAM, DEVICE, AND CIRCUIT SIMULATOR - Improved equivalent circuits and circuit analysis using the same for a multiplayer capacitor are provided. In one aspect, the equivalent series capacitance C and part of the equivalent series resistance R of a basic equivalent circuit for a multiplayer chip capacitor are replaced with a capacitance CO, and capacitances Cm and C12-15-2011
20110307233COMMON SHARED MEMORY IN A VERIFICATION SYSTEM - The debug system described in this patent specification provides a system that generates hardware elements from normally non-synthesizable code elements for placement on an FPGA device. This particular FPGA device is called a Behavior Processor. This Behavior Processor executes in hardware those code constructs that were previously executed in software. When some condition is satisfied (e.g., If . . . then . . . else loop) which requires some intervention by the workstation or the software model, the Behavior Processor works with an Xtrigger device to send a callback signal to the workstation for immediate response.12-15-2011
20120041747Dynamically Adjusting Simulation Fidelity Based on Checkpointed Fidelity State - Mechanisms are provided for controlling a fidelity of a simulation of a system. A model of the system is received, the model of the system having a plurality of individual components of the system. Fidelity values are assigned to models of the individual components of the system. A simulation of the system is executed using the model of the system and the models of the individual components of the system. The fidelity values of one or more of the models of the individual components of the system are dynamically adjusted during the execution of the simulation by creating a checkpoint of a state of the simulation and modifying one or more fidelity values of one or more of the models of the individual components after generating the checkpoint, thereby generating a modified fidelity value state.02-16-2012
20090177457DUTY CYCLE DISTORTION (DCD) JITTER MODELING, CALIBRATION AND GENERATION METHODS - A method and system for modeling and calibrating duty cycle distortion (DCD) of a Serializer and Deserializer (SerDes) device, including first generating a clock DCD signal. Once the clock DCD signal is generated, it is calibrating based upon results obtained from a filtering process of the clock DCD signal. Once the clock DCD signal is calibrated, a data DCD signal is generated and calibrated based upon results obtained from a filtering process of the data DCD signal.07-09-2009
20100030546GUI-FACILITATED SIMULATION AND VERIFICATION FOR VEHICLE ELECTRICAL/ELECTRONIC ARCHITECTURE DESIGN - Disclosed herein are computer aided design (CAD) techniques to implement a unified data schema and graphical user interface (GUI) to link ECU/devices, in-vehicle communications, and vehicle harness information together with respect to architectural relation, performance relation, and cost relation, and to facilitate a designer's understanding and manipulation of this information. The domain-specific information from each domain is converted to objects in this unified data schema and stored in a unified database that is accessible to every domain, so that the impact of the current state in the device domain can be accessed and analyzed by a designer from any domain. This approach enables design data sharing and real-time collaboration between different electrical/electronic (E/E) design domains, thereby facilitating the realization of design data collaboration, design change management, and product lifetime management (PLM) and product data management (PDM) implementation.02-04-2010
20120041748Design support apparatus and method - A design support apparatus includes an extraction part, a creation part, and a correction part. The extraction part extracts from among a power supply layer and a ground layer a range related to a signal transmission of a pair of signal transmission circuit models disposed in a predetermined layer of a substrate model having a plurality of layers. The creation part processes, based on given constrained conditions, the power supply layer and ground layer in a range extracted by the extraction part and creates a layer model. The correction part corrects the substrate model based on the created layer model.02-16-2012
20120150523Modeling of Multi-Layered Power/Ground Planes using Triangle Elements - In a method of simulating electrical characteristics of a circuit board having a plurality of features, the plurality of features is projected onto a planar construct. A Delaunay triangulation routine for generating a triangular mesh that corresponds to the single planar construct is executed on the digital computer. A routine that generates a Voronoi diagram corresponding to the triangular mesh. An equivalent circuit for each triangle is determined. The equivalent circuit includes exactly three sub-circuits that couple a vertex within the triangle to a vertex within an adjacent triangle and exactly one sub-circuit that couples the vertex within the triangle to a reference plane. A routine solves, for each triangle, an equation describing an electrical characteristic value based on the equivalent circuit corresponding to the triangle. A routine for generating a human-perceptible indication of the electrical characteristic value for each triangle is executed on the digital computer.06-14-2012
20100332208APPARATUS AND METHOD FOR EMULATION OF PROCESS VARIATION INDUCED IN SPLIT PROCESS SEMICONDUCTOR WAFERS - Predictive Split Lot Emulator, and methods simulating integrated circuit performance variations, before IC fabrication. The emulator receives a split lot parameter, maps the split lot parameter onto an IC element model, and transforms the IC element into a predictive IC element model. The emulator uses the predictive model to determine simulated performance characteristic of the IC element model. Also, a predictive split lot analyzer, a CAD simulation system, and a PDK including the emulator. IC simulating methods include choosing a Split Condition from a Split Table; a Predictive Split Lot Emulator receiving the Condition, determining a Split Parameter Condition Perturbation, mapping the Perturbation into a Model Parameter Perturbation for an IC element, and storing the Model Perturbation for an IC element into a Model Parameter Perturbation Library. The Perturbation Library emulates IC element performance characteristic in a Split Condition. Determining, mapping, and emulating are executed prior to integrated circuit fabrication.12-30-2010
20120004896COMPONENT BEHAVIOR MODELING USING SEPARATE BEHAVIOR MODEL - A behavior model is provided, which is configured to simulate one aspect of the behavior of a component apart from the component model for the component. The behavior model can be included in a circuit model used to simulate operation of a circuit. The circuit model can include a component model for a component and a corresponding behavior model, which is located in parallel or series with the component model. The component model and behavior model can collectively simulate all of the behavior of the component within the circuit. In an embodiment, the behavior model simulates snapback behavior exhibited by the component.01-05-2012
20100217576Multi-Layer Finite Element Method for Modeling of Package Power and Ground Planes - In a method for simulating electrical characteristics of a plurality of power planes, each power plane includes a plurality of geometric features. The geometric features of each power plane are projected onto a single planar construct. A polygonal mesh, including a plurality of pairs of interconnected nodes, that corresponds to the single planar construct is generated. The polygonal mesh is projected onto at least one power plane an equivalent circuit between each adjacent node of the plurality of interconnected nodes is projected onto the power plane. An equivalent capacitance is assigned between each node and a common ground planer. A finite element equation that includes a plurality of discrete terms is generated. The equation is solved, thereby determining the electrical characteristic value between each pair of adjacent nodes.08-26-2010
20110166847SILICON CONTROLLED RECTIFIER MODELING - A model for a silicon controlled rectifier includes three diode models connected in series, with the middle diode model being reverse biased. Each diode model corresponds to and can be configured to simulate DC operation of a junction in the silicon controlled rectifier. The model can be used to evaluate behavior of a circuit that includes the silicon controlled rectifier. For example, the circuit can include an electrostatic discharge protection circuit that includes the silicon controlled rectifier.07-07-2011
20120016652SYSTEM AND METHOD FOR FAST POWER GRID AND SUBSTRATE NOISE SIMULATION - Systems and methods related to fast simulation of power supply networks and identification of a set of extrema (e.g., maxima or minima) waveforms associated with the power supply networks. In accordance with an embodiment, a method is provided for simulating an electrical circuit, comprising preselecting an input vector file, initializing a supply voltage to a fixed value, performing event driven simulation using the input vector file, so as to extract time-varying power supply current waveforms at a plurality of power grid points. The method also comprises simulating a power grid using a linear network simulator or other SPICE type simulation tool, so as to derive time-varying voltage waveforms from the current waveforms for each point on the power grid. The method further comprises comparing current and/or voltage waveforms with a previous simulation; and repeating the above steps from event driven simulation onwards, using a function of voltage waveforms from previous simulations, until the values of current and/or voltage waveforms converge within a pre-specified tolerance, or an iteration limit has been reached.01-19-2012
20120022847COHERENT STATE AMONG MULTIPLE SIMULATION MODELS IN AN EDA SIMULATION ENVIRONMENT - A circuit design is simulated in a simulation environment. When a simulation model in the simulation environment transfers state information to a second simulation model, the simulation environment receives the state information and makes it available to the second simulation model without simulating the transfer through the simulated circuit design.01-26-2012
20120022846METHODS, SYSTEMS, AND ARTICLES OF MANUFACTURE FOR IMPLEMENTING ELECTRONIC CIRCUIT DESIGNS WITH ELECTRO-MIGRATION AWARENESS - Disclosed are methods, systems, and articles of manufacture for implementing electronic circuit designs with electro-migration awareness. Some embodiments perform schematic level simulation(s) to determine electrical characteristics, identifies physical parasitics of a layout component, determines the electrical or physical characteristics associated to electro-migration analysis on the component, and determines whether the component meets EM related constraint(s) while implementing the physical design of the electronic circuit in some embodiments. Some embodiments further determine adjustment(s) to the component or related data where the EM related constraints are not met and/or and present the adjustment(s) in the form of hints. Various data and information, such as currents in various forms or voltages, are passed between various schematic level tools and physical level tools.01-26-2012
20120209583COMPUTER PRODUCT, VERIFICATION SUPPORT APPARATUS, AND VERIFICATION SUPPORT METHOD - A computer-readable medium stores therein a verification support program that causes a computer to execute a process including first detecting an assertion that evaluates to true during simulation of a circuit, the assertion being detected from an assertion group prescribing values of registers to be met by the circuit; updating, at a clock tick subsequent to a clock tick at which the assertion is detected at the first detecting, an expected value of a register, to a value of the register as prescribed by the assertion; second detecting inconsistency between the expected value that has been updated at the updating and the value of the register; determining, based on a detection result obtained at the second detecting, validity of a change in the value of the register; and outputting a determination result obtained at the determining.08-16-2012
20110066418CIRCUIT SIMULATION METHOD - A exemplary aspect of the present invention is a simulation method for a semiconductor circuit that includes: a semiconductor resistor; a plurality of contacts arranged at regular intervals in a longitudinal direction and in a width direction of the semiconductor resistor on a terminal region of the semiconductor resistor; and a wiring line formed on the plurality of contacts, the simulation method including: defining a ratio of a parasitic-resistance by the semiconductor resistor between two of the contacts neighboring in the longitudinal direction to a resistance of one of the plurality of contacts as a constant k; and modeling a parasitic-resistance net by using the constant k, the parasitic-resistance net including the terminal region of the semiconductor resistor and the plurality of contacts.03-17-2011
20110066419Method to Simulate a Digital System - A simulator is partitioned into a functional component and a behavior prediction component and the components are executed in parallel. The execution path of the functional component is used to drive the behavior prediction component and the behavior prediction component changes the execution path of the functional component.03-17-2011
20080281570Closed-Loop Modeling of Gate Leakage for Fast Simulators - A method for circuit simulation using a netlist in which a first device having an unmodeled, nonlinear behavior is modified by inserting a second device which has a nonlinear response approximating the unmodeled nonlinear behavior. The first device may be for example a first transistor and the second device may be a variable current source, in particular one whose current is modeled after a floating transistor template which represents gate leakage current of the first transistor (gate-to-source or gate-to-drain). During simulation of the circuit a parameter such as a gate-to-source voltage of the second transistor is controlled to model gate leakage. The model parameters can be a function of an effective quantum mechanical oxide thickness value of a gate of the first transistor technology.11-13-2008
20080306721Dynamic-Verification-Based Verification Apparatus Achieving High Verification Performance and Verification Efficiency and the Verification Methodology Using the Same - The present invention relates to a simulation-based verification apparatus and a verification method, which enhance the simulation performance and efficiency greatly, for verifying a digital system containing at least million gates. Also, the present invention relates to a simulation-based verification apparatus and a verification method used together with formal verification, simulation acceleration, hardware emulation, and prototyping to achieve the high verification performance and efficiency for verifying a digital system containing at least million gates.12-11-2008
20110106517METHOD OF SIMULATING AN ELECTRONIC CIRCUIT COMPRISING AT LEAST ONE ANALOGUE PART WITH A POWER SPECTRAL DENSITY - An electronic circuit, comprising at least an analog part, subjected to predefined input signals in the time domain, is broken down into at least one modeled elementary block. The input signal is transformed into a simulation signal which comprises at least one useful signal component representative of the spectral power density of the input signal. Application to an input of the simulation signal circuit is simulated. The useful component of the simulated signal is computed on output of each successive block. The useful component of the simulated signal output from the circuit is compared with at least one predefined signal to test at least one characteristic of the circuit. A noise component can be introduced in a simulation signal or in the output signal of a block passed through.05-05-2011
20100094609Modeling electrical interconnections in three-dimensional structures - Disclosed are apparatus, methods and software that implement a partial element equivalent circuit (PEEC) method having global basis functions on cylindrical coordinates to determine wide-band resistance, inductance, capacitance, and conductance from a large number of three-dimensional interconnections in order to provide for the electrical design of system-in-package (SIP) modules, and the like. The apparatus, methods and software use a modal equivalent network from mixed potential integral equation with cylindrical conduction and accumulation mode basis functions, which reduces the matrix size for large three-dimensional interconnection problems. Combined with these modal basis functions, the mixed potential integral equations describe arbitrary skin and proximity effects, and allow determination of partial impedance and admittance values. Additional enhancement schemes further reduces the cost for computing the partial inductances. Therefore, the apparatus, methods and software can be used to construct accurate models of a large number of three-dimensional interconnection structures, including more than 100 bonding wires used for stacking integrated circuit chips, through-silicon via interconnections, and the like.04-15-2010
20120316858METHOD AND SYSTEM FOR IMPLEMENTING PARALLEL EXECUTION IN A COMPUTING SYSTEM AND IN A CIRCUIT SIMULATOR - A method and mechanism for implementing a general purpose scripting language that supports parallel execution is described. In one approach, parallel execution is provided in a seamless and high-level approach rather than requiring or expecting a user to have low-level programming expertise with parallel processing languages/functions. Also described is a system and method for performing circuit simulation. The present approach provides methods and systems that create reusable and independent measurements for use with circuit simulators. Also disclosed are parallelizable measurements having looping constructs that can be run without interference between parallel iterations. Reusability is enhanced by having parameterized measurements. Revisions and history of the operating parameters of circuit designs subject to simulation are tracked.12-13-2012
20120123763METHOD AND APPARATUS FOR EXECUTING A HARDWARE SIMULATION AND VERIFICATION SOLUTION - One embodiment of the present invention provides systems and techniques to execute a hardware simulation and verification solution on a multiprocessor system. The hardware simulation and verification solution can be partitioned into different modules which can include a simulation kernel to simulate changes in signal values, a value change dump module to store the changes in the signal values on a computer-readable storage medium, a functional coverage module to check functionality, a toggle coverage module to check signal toggling, an assertion engine to check complex behaviors, and a testbench module to generate test scenarios. Embodiments of the present invention can execute different modules on different processors, thereby improving performance.05-17-2012
20120123762Thermal Memory In A Fault Powered System - A circuit breaker system for providing thermal protection to a conductor conducting current from a power source to a load. While the power source is connected to the load, a microcontroller is powered by the current passing through the conductor to thermally model the temperature of the conductor. If the microcontroller determines that the temperature of the conductor has risen to an undesirable or unsafe level, the circuit breaker disconnects the power source from the load and the current no longer passes through the conductor. With no current passing through the conductor, the microcontroller no longer receives power from the conductor. Instead, the microcontroller continues to model the temperature of the conductor as the conductor cools to an ambient temperature by receiving power from an energy storage device. Accordingly, the microcontroller continuously models the temperature of the conductor until the temperature of the conductor cools to the ambient temperature.05-17-2012
20120166169MODELING TECHNIQUE FOR RESISTIVE RANDOM ACCESS MEMORY (RRAM) CELLS - Accurate simulation of two-terminal resistive random access memory (RRAM) behavior is accomplished by solving equations including state variables for filament length growth, filament width growth, and temperature. Such simulations are often run in a SPICE environment. Highly accurate models simulate the dynamic nature of filament propagation and multiple resistive states by using a sub-circuit to represent an RRAM cell. In the sub-circuit, voltages on floating nodes control current output while the voltage dropped across the sub-circuit controls growth and temperature characteristics. Properly executed, such a sub-circuit can accurately model filament growth at all phases of conductance including dynamic switching and a plurality of resistive states.06-28-2012
20120166168METHODS AND SYSTEMS FOR FAULT-TOLERANT POWER ANALYSIS - Methods and systems are described which enable a user to conduct a power analysis of a behavior description of a circuit design. The elements of the circuit design are described at the register transfer level and synthesized to a gate-level netlist. Embodiments of the invention allow a user to conduct accurate power analysis during register transfer level to gate-level netlist synthesis.06-28-2012
20100250223SEMICONDUCTOR CIRCUIT DETERIORATION SIMULATION METHOD AND COMPUTER PROGRAM MEDIUM - A semiconductor circuit deterioration simulation method for a circuit including MOSFETs includes inserting a dynamic voltage source associated with a fluctuation in voltage/current characteristics into each gate terminal of a plurality of MOSFETs in series, calculating dynamic deterioration amounts of the plurality of MOSFETs by performing circuit simulation and calculating a dynamic deterioration amount, and repeating the above processing to perform the circuit deterioration simulation over the long term.09-30-2010
20120084067METHOD AND APPARATUS FOR SYNTHESIZING PIPELINED INPUT/OUTPUT IN A CIRCUIT DESIGN FROM HIGH LEVEL SYNTHESIS - A method and apparatus for synthesizing pipelined input/output in a circuit design from high level synthesis is described. In one example, an operation is selected to be performed by a circuit, the operation including a plurality of partial operations of different types. The partial operations are ordered based on the ordering of the variables. A plurality of hardware components for performing the operations are represented with a data flow graph having edges and nodes, the edges and nodes being connected based on the ordering of partial operations. A plurality of solutions are simulated for performing the operations as hardware component combinations represented as paths on the data flow graph. For each solution, a cost including a number of edges and nodes traversed on the data flow graph is determined, and a solution is selected with the lowest cost as a hardware component combination for a circuit.04-05-2012
20120084066SYSTEM AND METHOD FOR EFFICIENT MODELING OF NPSKEW EFFECTS ON STATIC TIMING TESTS - A computer-implemented method that simulates NPskew effects on a combination NFET (Negative Field Effect Transistor)/PFET (Positive Field Effect Transistor) semiconductor device using slew perturbations includes performing a timing test by a computing device, by: (1) evaluating perturb slews in Strong N/Weak P directions on the combination semiconductor device for a timing test result; (2) evaluation perturb slews in Weak N/Strong P directions on the combination semiconductor device for a timing test result; and (3) evaluating unperturbed slews in a balanced condition on the combination semiconductor device for a timing test result. After each test is performed, a determination is made as to which evaluation of the perturbed and unperturbed slews produces a most conservative timing test result for the combination semiconductor device. An NPskew effect adjusted timing test result is finally output based on determining the most conservative timing test result.04-05-2012
20120221312METHOD AND SYSTEM FOR POWER DELIVERY NETWORK ANALYSIS - The subject application relates to a method and system for power delivery network analysis. The present disclosure is directed towards a computer-implemented method for analyzing a power delivery network (PDN) system. The method may include receiving at least one of a chip power model, a package power model and a board power model at the computing device and co-simulating at least two of the chip power model, the package power model, and the board power model. Numerous other features are also within the scope of the present disclosure.08-30-2012
20120215515PRINTED CIRCUIT BOARD VIA MODEL DESIGN FOR HIGH FREQUENCY PERFORMANCE - Methods herein provide for estimating a high frequency performance of a PCB via model through simulation. A via model is generated to include a representation of structures of a via, such as input and output pads, and input and output stubs. A signal path in the model is defined from an input pad of the model to an output pad of the model along a transmission line segment between the input pad and the output pad. Frequency dependent input impedance values at the input pad are generated based on one or more of the input pad diameter value, the output pad diameter value, the input stub length value, and the output sub length value. A high frequency performance of the via model is estimated based on the frequency dependent input impedance values at the input pad.08-23-2012
20110184715SYSTEM AND METHOD OF PREDICTING PROBLEMATIC AREAS FOR LITHOGRAPHY IN A CIRCUIT DESIGN - A system and method is provided which predicts problematic areas for lithography in a circuit design, and more specifically, which uses modeling data from a modeling tool to accurately predict problematic lithographic areas. The method includes identifying surface heights of plurality of tiles of a modeled wafer, and mathematically mimicking a lithographic tool to determine best planes of focus for exposure for the plurality of tiles.07-28-2011
20100174520SIMULATOR - A simulator comprising: a simulation executing unit to execute a simulation of circuit description data in which a circuit is described in a description language; a bit width monitor to monitor whether a bit width of a simulation result of an operation described in the circuit description data overflows from a bit width of an operation result assignment target variable described in the circuit description, while the simulation executing unit is executing the simulation; and an overflow avoiding unit to dynamically extend a bit width of the operation result assignment target variable that stores the simulation result, when the bit width monitor detects an occurrence of an overflow.07-08-2010
20100174519Virtual Platform and Related Simulation Method - A platform for simulating a chip includes a component module, a configuration module and a top module. The component module is utilized for storing a plurality of component models and information related to the plurality of component models. The configuration module is utilized for generating a configuration result according to the component model needed by the chip. The top module is coupled to the component module and the configuration module, for reading information related to the component model from the component module according to the configuration result, so as to simulate the chip.07-08-2010
20100274548Clock Approximation for Hardware Simulation - Clock approximate signals within an electronic design may be identified. Allowing the identified clock approximate signals to be conditionally ignored during a subsequent simulation of the electronic design may provide for a significant increase in the efficiency of the simulation.10-28-2010
20100010798Modeling of variations in drain-induced barrier lowering (DIBL) - The present method is a method of modeling Drain-Induced Barrier Lowering (DIBL) in a transistor model, the transistor model being based on a MOSFET transistor. The transistor model includes a base, a source, a drain, a gate, and a gate terminal. In the present method, a voltage is applied to the gate terminal, a voltage is applied to the drain, and an electrical potential is applied between the gate terminal and gate. The magnitude of electrical potential applied between the gate terminal and gate is varied in proportion to the magnitude of voltage applied to the drain.01-14-2010
20120253775Multidimensional Monte-Carlo Simulation for Yield Prediction - An embodiment includes a computer program product for providing a yield prediction. The computer program product has a non-transitory computer readable medium with a computer program embodied thereon. The computer program comprises computer program code for obtaining a representation of a circuit. The circuit comprises a common path and a critical path, and the critical path represents multiple parallel paths. The computer program further comprises computer program code for obtaining a first table representing the common path and a second table representing the multiple parallel paths and computer program code for performing a variable based simulation based on the representation of the circuit, the first table, and the second table. The computer program also comprises computer program code for determining a result indication of each of the multiple parallel paths based on the variable based simulation compared with a predetermined specification.10-04-2012
20120316857Method for Circuit Simulation - A computer-implemented method for simulating an electrical circuit. The method includes (a) setting a first temperature distribution in the electrical circuit, (b) performing an electrical simulation across the electrical circuit taking into consideration the first temperature distribution, (c) performing a thermal simulation across the electrical circuit taking into consideration a result of the electrical simulation, to obtain a second temperature distribution, and (d) determining whether a criterion for termination the simulation is met. If the criterion is met, terminate the simulation. If the criterion is not met, assign the second temperature distribution to the first temperature distribution, and repeat steps (b), (c), and (d).12-13-2012
20080300846METHODS AND APPARATUS FOR HARDWARE SIMULATION AND DESIGN VERIFICATION - A scripting approach to managing the test bench complexity issue is provided. Partitioning the functionality of a test bench between Verilog and a scripting language allows for a significant reduction in compile times during ASIC verification. If done correctly, partitioning also offers great potential for re-use of test bench components. The Tcl language was chosen as a basis for implementing a library of PLI routines that allow fully customizable interpreters to be instantiated in Verilog test benches. This library allows multiple Tcl interpreters to be instantiated in a Verilog simulation. The Tcl interpreters can interact with the simulation and cause tasks to be executed in the Verilog simulation. It has been found the TCL_PLI library is extremely valuable in speeding up verification efforts on multi-million gate ASICs.12-04-2008
20080300848EFFICIENT SIMULATION OF DOMINANTLY LINEAR CIRCUITS - A method of simulating a circuit parameter such as voltage or current for a dominantly linear circuit by constructing a circuit equation matrix whose elements correspond to nodes of the circuit, decoupling linear and nonlinear contributions to the circuit parameter based on a partition of an inverse matrix of the circuit equation matrix, computing linear and nonlinear components using the decoupled contributions, and combining the nonlinear and linear components to yield a state of the circuit parameter for a given time step. The computation of the nonlinear component includes Newton-Raphson iterations to linearize nonlinear devices of the circuit, wherein the Newton-Raphson technique is applied to the right-hand side of the circuit state matrix equation. The computations are iteratively repeated for successive time steps which are advantageously separated by a constant time interval to avoid further recalculation of the state matrix.12-04-2008
20080300847ON-THE-FLY IMPROVEMENT OF CERTAINTY OF STATISTICAL ESTIMATES IN STATISTICAL DESIGN, WITH CORRESPONDING VISUAL FEEDBACK - A system and method to analyze analog, mixed-signal, and custom digital circuits. The system and method displays to a user characteristic values of a circuit and statistical uncertainty values of the characteristic values early in a sampling or characterization run of the circuit. The characteristic values and their statistical uncertainties are updated as the sampling or characterization run progresses. The user can halt the sampling or characterization run once a desired level of uncertainty is attained. The system can automatically halt the sampling or characterization run, once the statistical uncertainty lie within a pre-determined range.12-04-2008
20110131030LINK ANALYSIS COMPLIANCE AND CALIBRATION VERIFICATION FOR AUTOMATED PRINTED WIRING BOARD TEST SYSTEMS - A transmission line on a printed wiring board is tested and printed wiring board manufacturing variability is assessed. A response of the transmission line to a signal test pattern is measured. A network including a plurality of components connected by the transmission line is then simulated. The simulated network is based on the measured scattering parameters and virtual models representative of each of the components in the network. A system-level output response of the simulated network to a simulated input signal is analyzed, and the printed wiring board is characterized based on a comparison of the system-level output response to a printed wiring board performance metric threshold.06-02-2011
20120323549SYSTEM, METHOD AND APPARATUS FOR A SCALABLE PARALLEL PROCESSOR - A system and method of parallel processing includes a computer system including a first processor, the first processor being a control flow type processor, a second processor, the second processor being a data flow type processor. The second processor is coupled to a second memory system, the second memory system including instructions stored therein in an order of execution and corresponding events data stored therein in the order of execution. A first one of the instructions are stored at a predefined location in the second memory system. The system also includes a run time events insertion and control unit coupled to the first processor and the second processor. The first processor, the second processor and the run time events insertion and control unit are on a common integrated circuit.12-20-2012
20110213604SIGNAL ANALYZING METHOD FOR ELECTRONIC DEVICE HAVING ON-CHIP NETWORK AND OFF-CHIP NETWORK - The present invention provides a signal analyzing method for an electronic device having an on-chip network and an off-chip network. Compared with the conventional signal analyzing method for an electronic device having an on-chip network and an off-chip network, the signal analyzing method of the present invention is able to provide a complete electrical connection and accurate electrical characteristics for an electronic device having an on-chip network and an off-chip network.09-01-2011
20120278056Characterizing Performance of an Electronic System - In one embodiment of the present invention, the performance of an electronic circuit having a clock path between a clock source cell and a clock leaf cell is characterized over a simulation duration, where the clock path has one or more intermediate cells. Variations in the effective power supply voltage level of at least one intermediate cell over the simulation duration are determined using a system-level power-grid simulation tool. Static timing analysis (STA) software is used to determine cell delays for at least one of the intermediate cells for different clock-signal transitions at different times during the simulation duration. The cell delays are then used to generate one or more metrics characterizing the performance of the electronic circuit, such as maximum and minimum pulse widths, maximum cycle-to-cycle jitter, and maximum periodic jitter.11-01-2012
20110246169SYSTEM AND METHOD FOR SUPPORTING DESIGNING OF SEMICONDUCTOR DEVICE - A semiconductor circuit designing supporting system, includes: a storage unit in which two models of a first model and a second model are stored as device models a semiconductor device; and an operation unit. The operating unit includes: a characteristic variation calculating section configured to calculate a variation of a device characteristic when process parameters are varied by using the first model; and an analyzing section configured to normalize based on the variation, an error between a device characteristic calculated by using the second model and actual measurement data and to analyze the second model by using the normalized error.10-06-2011
20120089383METHODS AND SYSTEMS FOR PERFORMING TIMING SIGN-OFF OF AN INTEGRATED CIRCUIT DESIGN - Systems and methods for performing timing sign-off of an integrated circuit design are disclosed. In one example embodiment the integrated circuit design is divided into plurality of blocks based on a pre-determined logic. A timing model is extracted for each block using static timing analysis (STA), wherein the extracted timing model includes timing information. An integrated circuit design level STA is performed using the extracted timing model of all of the plurality of blocks to obtain first integrated circuit design timing. The first integrated circuit timing is compared with a predetermined performance criterion.04-12-2012
20110276321DEVICE SPECIFIC CONFIGURATION OF OPERATING VOLTAGE - A method and circuit for device specific configuration of an operating voltage is provided. A circuit design is analyzed to determine a maximum gate-level delay for the circuit design. A minimum voltage value corresponding to the maximum gate-level delay is determined along with a default voltage value corresponding to a default gate-level delay. A voltage scaling factor corresponding to the minimum voltage and default voltage values is determined. The circuit design is synthesized such that the synthesized design includes the voltage scaling value. The synthesized design specifies setting an operating voltage to a value of a startup voltage value scaled by the voltage scaling value.11-10-2011
20120330637METHOD FOR PROVIDING DEBUGGING TOOL FOR A HARDWARE DESIGN AND DEBUGGING TOOL FOR A HARDWARE DESIGN - A method is provided for providing a debugging tool for a hardware design specified in a hardware description language. The method includes receiving one or multiple source files of the specified hardware design; processing each source file in a way that hardware description language constructs from the hardware design are directly simulatable; wherein the processing process includes at least one of the following: restructuring procedural source code of the source file; preserving functional equivalence to unaltered source code of the source file; and adding debug information to the hardware description of said source file.12-27-2012
20110320183COMPUTING DEVICE AND METHOD FOR ANALYZING DIFFERENTIAL TRANSMISSION LINES PORT RELATIONSHIPS - A computing device and a method determines port relationships of a differential transmission line of a circuit board according to an original scattering parameters file, which records scattering parameter values measured from ports of the differential transmission line under different signal frequencies. The computing device generates a new scattering parameters file matching a scattering parameters model predefined for the differential transmission line according to the determined port relationships. Design of the differential transmission line is analyzed to determine if the differential transmission line is qualified according to the new scattering parameters file and the scattering parameters model.12-29-2011
20100198575Generation and Manipulation of Realistic Signals for Circuit and System Verification - Methods for generating realistic waveforms with controllable voltage noise and timing jitter in a computer-based simulation environment and the simulation of a subset of those waveforms with system elements along the signal path is disclosed. By deriving a generic, re-useable, parameterized Fourier series, time-domain clock and pseudo-random data signals are generated from a subset of their true harmonic components. Time-domain signal parameters including high, low, and common-mode voltage levels, transition slew-rates, transition timing, period and/or frequency, may be designated by the user, and the computer calculates the harmonic components that will combine through the inverse Fourier transform to provide the required time-domain characteristics. By computing the frequency content of the signal directly it is possible to simulate the interaction of the signal with various system blocks while remaining in the frequency domain, thereby reducing simulation time and memory requirements. By allowing the parameters of the signal model to vary on a cycle-to-cycle basis, signal characteristics such as voltage noise and timing jitter may be modeled with flexibility and precision down to the numerical limitations of the simulator.08-05-2010
20100198574Programmer View Timing Model For Performance Modeling And Virtual Prototyping - In various implementations of the invention, methods and apparatuses are provided that enable timing accurate, bit level hardware models for simulation at a rapid rate. With various implementations of the invention, a functional module is combined with a timing module. The combination may be employed to assist in performing performance modeling. With various implementations of the invention, a functional module, a timing module, and a module wrapper are provided, the module wrapper having at least a slave and master port. The slave port and the master port allowing for the exchange of data between modules, between the module and a host computing environment, and between the module and a performance modeling platform.08-05-2010
20100198573SIGNAL SELECTING APPARATUS, CIRCUIT AMENDING APPARATUS, CIRCUIT SIMULATOR, CIRCUIT EMULATOR, METHOD OF SIGNAL SELECTION AND PROGRAM - Signal selecting apparatus 08-05-2010
20100169064SYSTEM, AN APPARATUS AND A METHOD FOR PERFORMING CHIP-LEVEL ELECTROSTATIC DISCHARGE SIMULATIONS - A modeler for components of an IC under ESD conditions, a method of simulating ESD behavior of an IC and an ESD simulation system. In one embodiment, the modeler includes: (1) a circuit analyzer configured to provide identified ESD cells and circuitry of the IC by comparing component information of the IC with predefined ESD protection elements and predefined circuit topologies and (2) a model generator configured to create linearized models of the identified ESD cells and the identified circuitry based on physical attributes associated with the identified ESD cells and the identified circuitry, wherein a combination of the linearized models represent operation of the IC component under ESD conditions.07-01-2010
20130018646TIME-DOMAIN SIGNAL GENERATION - Methods and apparatus disclosed herein operate to receive a plurality of cycles characterized by a set of time-domain aspects, to modify at least one of the time-domain aspects of at least some of the plurality of cycles to produce a plurality of modified cycles, to process at least some of the modified cycles to produce time-domain cycles, and to create a time-domain signal based at least in part on concatenating the time-domain cycles.01-17-2013
20130018645Prediction Of Circuit Performance Variations Due To Device Mismatch - Aspects of the invention relate to techniques for predicting circuit performance variations due to device mismatch. Circuit simulation is performed to generate circuit simulation results based on a circuit description and information of circuit element parameters. Based on the simulation results, sensitivity information for the circuit design and current/charge deviations caused by individual circuit element parameter variations may be computed. Based on the sensitivity information and the current/charge deviations, steady-state mismatch effect information is determined. The determination may comprise first computing output parameter deviations caused by the individual variations of the circuit element parameters and then computing a total output parameter deviation based on the output parameter deviations.01-17-2013
20130018643METHODS AND SYSTEMS FOR SIMULATING CIRCUIT OPERATIONAANM Sharma; PrashantAACI CummingAAST GAAACO USAAGP Sharma; Prashant Cumming GA USAANM Ma; Jia QiangAACI HollywoodAAST FLAACO USAAGP Ma; Jia Qiang Hollywood FL US - A processor for use in simulating operation of a portion of an electrical circuit is provided. The processor is configured to receive at least one input indicative of electrical circuit data related to the electrical circuit being simulated, generate a model of the electrical circuit based on the at least one input, receive a user input that indicates the portion of the electrical circuit to be simulated, generate, based on the user input and the electrical circuit model, a partial circuit snapshot that corresponds to the portion of the electrical circuit, and apply at least one event to the partial circuit snapshot to simulate operation of the corresponding portion of the electrical circuit.01-17-2013
20130018644System and Method For Controlling Granularity of Transaction Recording In Discrete Event SimulationAANM Motel; VincentAACI GrenobleAACO FRAAGP Motel; Vincent Grenoble FRAANM Bhatnagar; NeetiAACI San JoseAAST CAAACO USAAGP Bhatnagar; Neeti San Jose CA USAANM Frazier; George F.AACI LawrenceAAST KSAACO USAAGP Frazier; George F. Lawrence KS USAANM LaRue, JR.; William W.AACI LeawoodAAST KSAACO USAAGP LaRue, JR.; William W. Leawood KS US - A method and system for controlling granularity of transaction recording and visualizing system performance and behavior in a discrete functional verification software simulation environment is disclosed. According to one embodiment, a simulation of a model is run in a discrete event simulation system for a period of time. During the simulation, statistical values of attribute for a plurality of transactions occurring during the period of time are monitored. Based on a granularity setting, a group of consecutive transactions is grouped into a super transaction, and the statistical values representing the super transaction are recorded to represent the group of transactions. The super transactions are visualized in a visualization tool for analyzing the performance of the model.01-17-2013
20110161065ULTRASONIC MODELLING - A method of producing a temperature model of a surface of an object using ultrasonic transducers comprises the steps of iteratively adjusting a temperature model by using measured travel times of ultrasonic waves and their predictions model-based. The ultrasonic waves used for producing the temperature model are preferably substantially non-dispersive ultrasonic waves. The method may further involve a height model of the surface, which height model is produced using substantially dispersive ultrasonic waves and is corrected by using the temperature model.06-30-2011
20110161064Physics-based compact model generation from electromagnetic simulation data - Some embodiments of the present invention provide a method of circuit design and circuit simulation. A method for electrical modeling of passive structures of a circuit design wherein the passive structures have DC properties is disclosed. The method comprises constructing a physical topology based on the passive structures of the circuit design, mapping the physical topology to a network of EM modeling elements, and determining parameters of the EM modeling elements to model the passive structures based on electromagnetic simulation data.06-30-2011
20130024178PLAYBACK METHODOLOGY FOR VERIFICATION COMPONENTS - Circuit verification structures and techniques are disclosed that relate to both passive verification components and active verification components, including verification components that cannot (or cannot easily) be synthesized to emulator hardware. In one aspect, a computer system may record signals from a circuit under test, and then play back those signals to a simulated verification component (which may be a passive verification component) for testing purposes. In another aspect, a computer system may also construct a representative behavior model of a verification component (which may be an active component) by providing input signals to a simulated verification component, recording corresponding output signals of the simulated verification component, and using the input and/or output signals to construct a representative behavior model of that verification component. The representative behavior model may be synthesized to hardware and used in association with verification of at least a portion of the circuit under test.01-24-2013
20080234997Design Structure for Compensating for Variances of a Buried Resistor in an Integrated Circuit - A design structure comprising elements that when processed in a computer-aided design system generates a machine-executable representation of a circuit that compensates for variances in the resistance of the buried resistor during operation of the integrated circuit using a waveform that is representative of the thermal characteristics of the buried resistor.09-25-2008
20080221852Method For Order Selection In Passive Transmission Line Macromodels Based On The Lie Criteria - A passive macromodel for lossy, dispersive multiconductor transmission lines uses a multiplicative approximation of the matrix exponential known as the Lie product. The circuit implementation of the macromodel is a cascade of elementary cells, each cell being the combination of a pure delay element and a lumped circuit representing the transmission line losses. Compared with passive rational macromodeling, the Lie product macromodel is capable of efficiently simulating long, low-loss multiconductor transmission lines while preserving passivity. This result is combined with transmission line theory to derive a time-domain error criterion for the Lie product macromodel. This criterion is used to determine the minimum number of cells needed in the macromodel to assure that the magnitude of the time-domain error is less than a given engineering tolerance.09-11-2008
20080221851Aid design system for analog integrated circuit and the method thereof - The aid design system for analog ICs includes an analog IC database, a peripheral component database, an input module, a computing simulation module, a selection module and an output module. The analog IC database includes parameters of a plurality of analog ICs. The peripheral component database includes parameters of the peripheral components cooperating with the analog ICs. The input module is for use in inputting a desirable parameter specification or specific IC according to the user's discretion. The computing simulation module includes transfer functions of the analog ICs. The selection module is for use in picking out suggested peripheral components based on the computing result of the computing simulation module. The output module is for use in displaying the suggested peripheral components or analog ICs.09-11-2008
20080221850Effective current density and continuum models for conducting networks - An Effective Current Density (ECD) method for continuum representation of conducting networks is disclosed. ECD is a method for representing large numbers of conductors in a single, compact model for use in circuit simulation and in other such applications. The models created through the application of ECD are continuum models, valid in both long and short wavelength limits, with the important property that the computation time does not grow with the number of wires in the network. Therefore, in circuits where the method can be applied, there is no limit to the number of conducting wires or components in the network to be simulated. Circuits with an unlimited number of conductors can be simulated using modest computing hardware and at an approximately constant order of simulation complexity.09-11-2008
20080221849Method, Apparatus And Computer Program Product For Creating Electric Circuit Models Of Semiconductor Circuits From Fabrication Process Parameters - Disclosed herein are methods and apparatus that automatically generate an electric circuit model from process parameters used to specify a semiconductor fabrication procedure, wherein at least one of the process parameters is specified as a statistical distribution. The methods and apparatus convert the process parameters into an electric circuit model. The electric circuit model is specified in terms of electric parameters, wherein at least one of the electric parameters is specified in terms of a statistical distribution. The methods and apparatus thus allow a process engineer whose expertise may not extend to state-of-the-art circuit modeling to develop insight into the effect of process parameter selection on the performance of the resulting electric circuit. The resulting insight is further enhanced since at least one of the electric parameters is specified in terms of a statistical distribution.09-11-2008
20130185045ANALYZING A PATTERNING PROCESS USING A MODEL OF YIELD - Techniques are presented that include accessing results of forward simulations of circuit yield, the results including at least circuit yield results including simulated device shapes. Using the circuit yield results, high-level traits of at least the simulated device shapes are determined. Based on the determined high-level traits and using the circuit yield results, a compact model for predicted yield is constructed, the compact model including a plurality of adjustable parameters, and the constructing the compact model for predicted yield including adjusting the adjustable parameters until at least one first predetermined criterion is met. An optimization problem is constructed including at least the compact model for yield, an objective, and a plurality of constraints. Using the optimization problem, the objective is modified subject to the plurality of constraints until at least one second predetermined criterion is met.07-18-2013
20130185046Analyzing A Patterning Process Using A Model Of Yield - Techniques are presented that include accessing results of forward simulations of circuit yield, the results including at least circuit yield results including simulated device shapes. Using the circuit yield results, high-level traits of at least the simulated device shapes are determined. Based on the determined high-level traits and using the circuit yield results, a compact model for predicted yield is constructed, the compact model including a plurality of adjustable parameters, and the constructing the compact model for predicted yield including adjusting the adjustable parameters until at least one first predetermined criterion is met. An optimization problem is constructed including at least the compact model for yield, an objective, and a plurality of constraints. Using the optimization problem, the objective is modified subject to the plurality of constraints until at least one second predetermined criterion is met.07-18-2013
20130179142DISTRIBUTED PARALLEL SIMULATION METHOD AND RECORDING MEDIUM FOR STORING THE METHOD - Provided is a distributed parallel simulation method. In the method, a plurality of local simulations is executed in parallel for a plurality of local design objects, respectively. The local design objects are included in a model at a specific abstraction level and are spatially distributed. At least one actual output is generated using at least one of the local design objects in a current local simulation of the plurality of local simulations. At least one expected output and the at least one actual output in the current local simulation are compared. Values of the at least one actual output and position information of the values from the current local simulation are transmitted to at least one remaining local simulation of the plurality of local simulations in response to a determination from the comparison that a difference exists between the at least one expected output and the at least one actual output.07-11-2013
20100017186Noise Model Method of Predicting Mismatch Effects on Transient Circuit Behaviors - A method of simulating device mismatch effects on transient circuit behaviors utilizes a circuit model corresponding to an electronic circuit. The circuit model includes a plurality of circuit elements and one or more noise sources. The noise sources have noise characteristics that correspond to device mismatch effects associated with the circuit elements. A noise analysis is performed on the circuit model to generate a noisy steady-state waveform of a selected output of the electronic circuit. Then, the noisy steady-state waveform is translated into a prediction of the variation of a respective circuit parameter associated with the electronic circuit.01-21-2010
20120253776MACRO MODEL OF OPERATIONAL AMPLIFIER AND CIRCUIT DESIGN SIMULATOR USING THE SAME - The present invention aims to simulate a response more similar to a actual machine while inhibiting load increase in analog operation. Program configuration of the present invention is a component of a simulation program for circuit design, which is executed by a computer. The computer includes an operation portion, a storage portion, a manipulation portion, and a display portion, so that the computer exerts a function of a circuit design simulator, and as a macro model of an operational amplifier for use in the circuit design simulator, enabling the computer to act by simulating a response of the operational amplifier on the circuit design simulator. The macro model of the operational amplifier includes a control portion (LMT10-04-2012
20130103377APPARATUS AND METHOD FOR POWER MANAGEMENT OF MEMORY CIRCUITS BY A SYSTEM OR COMPONENT THEREOF - An apparatus and method are provided for communicating with a plurality of physical memory circuits. In use, at least one virtual memory circuit is simulated where at least one aspect (e.g. power-related aspect, etc.) of such virtual memory circuit(s) is different from at least one aspect of at least one of the physical memory circuits. Further, in various embodiments, such simulation may be carried out by a system (or component thereof), an interface circuit, etc.04-25-2013
20130124181Methods, Systems, and Computer-readable Media for Improving Accuracy of Network Parameter in Electromagnetic Simulation and Modeling - Method, system, and computer readable medium are disclosed for analyzing electrical properties of a circuit. The method may comprise: providing a network model including at least one network parameter, the network parameter being defined over a frequency range; converting the network parameter into an intermediate network parameter having first and second portions; identifying first and second frequencies defining a frequency sub-range; replacing the first portion of the intermediate network parameter with a DC value when a frequency associated with the intermediate network parameter is lower than the first frequency; replacing the first portion of the intermediate network parameter with a transitional value when the frequency associated with the intermediate network parameter is within the frequency sub-range; and converting the intermediate network parameter with the replaced first portion into an updated network parameter.05-16-2013
20130124182RETRIEVING ODD NET TOPOLOGY IN HIERARCHICAL CIRCUIT DESIGNS - According to one aspect of the present disclosure, a method and technique for identifying odd nets in a hierarchical electronic circuit design is disclosed. The method includes: receiving a very high-speed integrated circuit hardware description language (VHDL) model of an electronic circuit design; modifying an architecture section of VHDL code of each endpoint component of the VHDL model to connect each input/output (IO) of the endpoint component VHDL code to an instance of a snoop VHDL code; executing a simulation of the VHDL model through a plurality of clock cycles while driving a logical value by the snoop VHDL code and deriving simulation clashes detected by the snoop VHDL code for each IO of the endpoint components; and extracting an odd net topology for the VHDL model based on the simulation clashes derived from the simulation.05-16-2013
20130124183Techniques for Processor/Memory Co-Exploration at Multiple Abstraction Levels - Processor/memory co-exploration at multiple abstraction levels. An architecture description language (ADL) description of a processor/memory system is accessed. The ADL description models on one of a plurality of abstraction levels. The abstraction levels may include a functional (or bit-accurate) level and a cycle-accurate level. Further, a communication protocol for the processor/memory system is accessed. The communication protocol is formed from primitives, wherein a memory interface formed from the primitives is useable in simulation at the abstraction levels. A processor/memory simulation model is automatically generated from the description and description of the communication protocol. The processor/memory simulation model comprises a processor/memory interface comprising the primitives and based on the communication protocol. The memory interface allows simulation of the processor/memory on the appropriate abstraction level for the simulation. For example, the processor/memory interface may be a functional interface or a cycle-accurate interface.05-16-2013
20130132056SIMULATION APPARATUS AND SIMULATION METHOD - A simulation apparatus includes a discrete events simulation section to perform a discrete type simulation of components of a configured model as defined based on attribute information that is information on parts of the components of the defined configured model and connection information showing a connectional relationship among the components of the defined configured model; and a soft error rate computation processing section to compute a soft error rate of the defined configured model based on the simulation result of the discrete events simulation section and data on soft error rates in the attribute information.05-23-2013
20130144588System and Method for Analyzing Spiral Resonators - A spiral resonator is analyzed by modeling a set of loops of the spiral resonator with a model of a circuit including a set of units, wherein each unit includes a resistor and an inductor to model one loop of the spiral resonator. Values of the resistor and the inductor of each unit are based on properties of a corresponding loop. Electrical connection of the loops is modeled by electrically connecting the units in a corresponding order of the loops. A capacitive coupling in the spiral resonator is modeled by connecting adjacent units with at least one capacitor having a value based on the capacitive coupling between two corresponding adjacent loops. An inductive coupling in the spiral resonator is modeled based on inductive coupling between pairs of loops. The operation of the spiral resonator is simulated with the model of the circuit.06-06-2013
20080208553Parallel circuit simulation techniques - Methods for improving the accuracy and performance of large complex circuit simulations including; special processing of clock structures, minimizing repetitive simulation of identical structures, partitioning designs into sub-systems for use by one of a variety of matrix inversion techniques, row partitioning matrices for parallel solving, applying two stage Newton-Ralphon's method and iteratively selecting one of a number of serial and parallel matrix solvers to perform circuit simulation.08-28-2008
20080201127USING A SUGGESTED SOLUTION TO SPEED UP A PROCESS FOR SIMULATING AND CORRECTING AN INTEGRATED CIRCUIT LAYOUT - One embodiment of the invention provides a system for speeding up an iterative process that simulates and, if necessary, corrects a layout of a target cell within an integrated circuit so that a simulated layout of the target cell matches a desired layout for the target cell. The system operates by determining if the target cell is similar to a preceding cell for which there exists a previously calculated solution. If so, the system uses the previously calculated solution as an initial input to the iterative process that produces the solution for the target cell.08-21-2008
20080201126Method of Automatically Generating the Structures From Mask Layout - A method of defining three-dimensional structure from mask layout for computer simulation, which provides a technology for defining a three-dimensional structure of liquid crystal cell which comprises a apparatus of liquid crystal display for designing and analyzing a apparatus of liquid crystal display.08-21-2008
20110224964SIMULATION DEVICE, SIMULATION METHOD, AND RECORDING MEDIUM STORING PROGRAM - Provided are a device model, a recording medium storing a program, a simulation circuit, device, and method that calculate a local temperature increase in an element. The device model according to the present invention is used for a semiconductor circuit simulation and has at least two model parameters. The model parameters include an electrical model describing temperature characteristics and a thermal model describing thermal characteristics and corresponding to the electrical model.09-15-2011
20100286975Reliability Simulation Method and System - The present invention relates to a method for finding design weakness and potential field failure of a PCB assembly which includes components, comprising the steps of: (a) creating a model of the PCB assembly by which natural frequencies and mode shapes of the PCB assembly can be determined; (b) performing a natural frequencies simulation for determining natural frequencies and mode shapes of the PCB assembly; and (c) analyzing said determined natural frequencies and mode shapes and identifying local dominant oscillations of components, components identified as having a local dominant oscillation in at least one of said determined mode shapes are identified as components having a relatively high potential of field failure.11-11-2010
20100286974TECHNIQUE USING POWER MACROMODELING FOR REGISTER TRANSFER LEVEL POWER ESTIMATION - A method for estimating power consumption of a design block of an integrated circuit includes obtaining power consumption data from designs of older-generation microprocessors, selecting a set of power consumption parameters, applying a curve-fitting technique on the obtained power consumption data for the selected set of power consumption parameters, creating a new power consumption model based on the curve-fitting technique and one or more of the power consumption parameters, using the model at a register transfer level of a newer-generation microprocessor to represent estimates of register transfer level power consumption of the newer-generation microprocessor, and outputting the register transfer level power consumption estimates based on the model.11-11-2010
20130151225AUTOMATED VERIFICATION FLOW - A method for verifying a circuit is provided. A first portion of a simulation of the circuit is executed within a hardware description language (HDL) environment so as to generate a first data set. A tool (which is external to the HDL environment) is called using a system task within the HDL environment. The tool is then executed on the first data set to generate a second data set, and a second portion of the simulation of the circuit is executed within the HDL environment using the second data set.06-13-2013
20130151226CIRCUIT SIMULATION METHOD - By considering a Deep Nwell diffusing into a Pwell region, accuracy of a substrate parasitic-resistance extraction is improved. A well region of a semiconductor integrated circuit where a Pwell and a Deep Nwell are formed in a substrate is divided into two or more meshes each including two or more resistor segments and a substrate noise is analyzed based thereon. In this regard, parallel components of resistors coupling the Pwell with the substrate are deleted in accordance with a state of the Deep Nwell diffusing into the Pwell region, so that an arithmetic processing unit executes a process for expressing a rise in the resistance value. By deleting the parallel components of the resistors coupling the Pwell with the substrate, the rise in the resistance value caused by the Deep Nwell can be reflected in the substrate parasitic-resistance extraction. Therefore, the accuracy of the substrate parasitic-resistance extraction can be improved.06-13-2013
20130096902Hardware Execution Driven Application Level Derating Calculation for Soft Error Rate Analysis - Mechanisms are provided for predicting effects of soft errors on an integrated circuit device design. A data processing system is configured to implement a unified derating tool that includes a machine derating front-end engine used to generate machine derating information, and an application derating front-end engine used to generate application derating information, for the integrated circuit device design. The machine derating front-end engine executes a simulation of the integrated circuit device design to generate the machine derating information. The application derating front-end engine executes an application workload on existing hardware similar in architecture to the integrated circuit device design and injects a fault into the existing hardware during execution of the application workload to generate application derating information. The machine derating information is combined with the application derating information to generate at least one soft error rate value for the integrated circuit device design.04-18-2013
20100318342MODEL GENERATING METHOD AND DEVICE AND RECORDING MEDIUM - A method includes causing a circuit simulator to perform a circuit simulation using circuit data stored in a storage, the circuit data containing a module to be modeled and a circuit for making a change to a clock to be inputted into the module and clock setting data stored in a storage, the clock setting data being intended to, at a predetermined timing, make a change to the clock to be inputted into the module, and storing a result of the circuit simulation in a simulation result data storage; and generating a hidden markov model about input and output signals of the module from values and times of the signals in accordance with a predetermined algorithm, the values and times being contained in the circuit simulation result stored in the simulation result data storage, and storing data about the model in a hidden markov model data storage.12-16-2010
20100318341COMPUTER PRODUCT, DESIGN SUPPORT APPARATUS, AND DESIGN SUPPORT METHOD - A non-transitory computer-readable recording medium stores therein a program that causes a processor to execute inputting a driving capability value, a lumped-constant capacitance value, and an input capacitance value included in the lumped-constant capacitance value, respectively defined in a circuit model, and further inputting a first delay time of the circuit model, based on the driving capability value and the lumped-constant capacitance value; setting in the circuit model, the driving capability value, the lumped-constant capacitance value, and the input capacitance value; acquiring a second delay time of the circuit model, by providing to a simulator, the circuit model having values set therein; calculating a relative evaluation value for the first delay time and the second delay time; and storing to a storage apparatus and as a delay time correcting coefficient, the relative evaluation value correlated with the driving capability value, the lumped-constant capacitance value, and the input capacitance value.12-16-2010
20120284007VERIFYING A PROCESSOR DESIGN USING A PROCESSOR SIMULATION MODEL - An improved method of verifying a processor design using a processor simulation model in a simulation environment is disclosed, wherein the processor simulation model includes at least one execution unit for executing at least one instruction of a test file. The method includes tracking each execution of each of the at least one instruction, monitoring relevant signals in each simulation cycle, maintaining information about the execution of the at least one instruction, wherein the maintained information includes a determination of an execution length of a completely executed instruction, matching the maintained information about the completely executed instruction against a set of trap elements provided by the user through a trap file, and collecting the maintained information about the completely executed instruction in a monitor file in response to a match found between the maintained information and at least one of the trap elements.11-08-2012
20130158972Automated Recovery System Verification - Disclosed are various embodiments for simulating distribution electric circuit models containing simulated software intelligent electronic devices. The distribution circuit and intelligent electronic simulator application facilitates the creation of user created software intelligent electronic devices. The software intelligent electronic devices imitate the operation of actual intelligent electronic devices on a power line. Communication between the software intelligent electronic devices and the automated recovery system can be captured using the distribution circuit and intelligent electronic device simulator application.06-20-2013
20130158973PARITY ERROR DETECTION VERIFICATION - A circuit design is simulated on a computing system. Simulating the circuit design includes selecting a first memory location in the circuit design in which to introduce a parity error according to the first memory location having a higher probability of being read than a second memory location of the circuit design. A parity error is inserted in the first memory location during simulation of the design.06-20-2013
20110307234CIRCUIT SIMULATION METHOD AND CIRCUIT SIMULATION DEVICE - The present invention provides a circuit simulation method of executing a high-precision circuit simulation. A voltage fluctuation analysis step at a gate level is executed (step S12-15-2011
20110313749CIRCUIT CONSTANT ANALYSIS METHOD AND CIRCUIT SIMULATION METHOD OF EQUIVALENT CIRCUIT MODEL OF MULTILAYER CHIP INDUCTOR - The occurrence of errors between circuit design using a circuit simulator and the actual circuit performance is quite adequately suppressed. Mutual inductance (Lm) between direct current inductance (L12-22-2011
20110313748METHOD OF SIMULATION AND DESIGN OF A SEMICONDUCTOR DEVICE - The invention relates to a method of simulation of semiconductor devices, such as wide-bandgap devices. The method employs a device substitution technique and involves simulation of a device which is structurally similar to the target device, and for which it is relatively easy to compute a model. Such a device may have a reduced material bandgap or a different doping/fixed-charge concentration. Based on the model of the simplified device, a model of the device under consideration is produced via a sequence of simulation steps, wherein simulated intermediate devices eventually transform into the target device for which a model is sought.12-22-2011
20110313747Technology Computer-Aided Design (TCAD)-Based Virtual Fabrication - A single finite element mesh is generated for predicting performance of an integrated circuit design. A plurality of sample points are identified for conducting a variability study on at least one parameter associated with the integrated circuit design. The sample points are selected to predict performance of the integrated circuit design when subject to variations in the at least one parameter due to variations in manufacturing processes to be used to manufacture the integrated circuit design. A parameterized netlist is generated corresponding to each of the sample points. A technology computer aided design (TCAD, e.g., finite element) simulation is run for each of the parameterized netlists, using the single finite element mesh for each of the parameterized netlists, until convergence is achieved, to obtain, for each of the parameterized netlists, at least one metric indicative of the performance of the integrated circuit design. A predicted design yield is developed for the integrated circuit design, based on the at least one metric determined for each of the parameterized netlists. In at least some instances, an importance sampling technique is tightly integrated with the TCAD process.12-22-2011
20130191103System and Method of Waveform Analysis to Identify and Characterize Power-Consuming Devices on Electrical Circuits - Waveform analysis is performed to identify and characterize power-consuming devices operating on a building electrical circuit. Current waveforms are measured from the building circuit with electrical devices operating thereon. The waveforms are separated into wavelets and analyzed to identify a representative wavelet model which is transmitted to a server for analysis. The server compares the representative wavelet model to a predictive model built from waveform signatures of known electrical devices operating on a circuit. When the predictive model matches the representative wavelet model, the electrical devices contributing to the representative wavelet, their operating mode(s) (e.g., “on”, “off”, “paused”, “hibernating”) and/or their performance state(s) (e.g., normal operation, deterioration, or failure modes) can be identified. This information can be communicated as feedback to the consumer to facilitate more efficient and more cost-effective energy usage.07-25-2013
20130191104SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR MODELING ELECTRONIC CIRCUITS - A system, method and computer program product for modeling electronic circuits via a sparse solution, or a sparse representation of a recurrent single or multi kernel support vector regression machine is provided. In one embodiment, the sparse representation may be attained, for example, by limiting a number of training data points for the method involving support vector regression. Each training data point may be selected based on the accuracy of a non-recurrent or fully recurrent model using an active learning principle applied to the non-successive or successive (time domain) data. A training time may be adjusted, for example, by (i) selecting how often one or more hyperparameters are optimized; or (ii) limiting the number of iterations of the method and consequently the number of support vectors.07-25-2013
20120078604METHOD FOR MINIMIZING TRANSISTOR AND ANALOG COMPONENT VARIATION IN CMOS PROCESSES THROUGH DESIGN RULE RESTRICTIONS - Various embodiments provide an integrated circuit (IC) design method and design kit for reducing context variations through design rule restrictions. The design method can be applied to components (e.g., analog blocks) with a context variation in an IC design. By drawing a cover layer over such components, context-variation-reduction design rule restrictions can be applied to reduce the context variations.03-29-2012
20080249758PROGRAM PRODUCT FOR DEFINING AND RECORDING MINIMUM AND MAXIMUM EVENT COUNTS OF A SIMULATION UTILIZING A HIGH LEVEL LANGUAGE - According to one method of simulation processing, instrumentation code, such as an runtime executive (rtx), receives one or more statements describing an count event and identifying the count event as an outlying count event. While simulating a design utilizing the HDL simulation model, occurrences of the outlying count event are counted to obtain a count event value. Simulation result data obtained from simulating the design is then received and processed. In the processing, the count event value is recorded within a data storage subsystem responsive to a determination of whether or not the count event value of the outlying count event exceeds a previously recorded count event value.10-09-2008
20120095746NOVEL MODELING APPROACH FOR TIMING CLOSURE IN HIERARCHICAL DESIGNS LEVERAGING THE SEPARATION OF HORIZONTAL AND VERTICAL ASPECTS OF THE DESIGN FLOW - A method of designing an integrated circuit and a model of an integrated circuit block, an electronic design automation tool, an apparatus and a computer-readable medium are disclosed herein. In one embodiment, the method of designing an integrated circuit includes: (1) generating a timing budget for the integrated circuit employing designer input of the integrated circuit, (2) establishing design constraints for a block of the integrated circuit employing the timing budget, (3) creating an input and output timing budget for the block employing the design constraints, (4) combining implementation information for the integrated circuit based on designer knowledge with the input and output timing budget to generate an updated input and output timing budget and (5) generating a model of the block based on the updated input and output timing budget.04-19-2012

Patent applications in class Circuit simulation

Patent applications in all subclasses Circuit simulation