| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 702120000 | Including input/output or test mode selection means | 65 |
| 20090240459 | INDENTIFYING SEQUENTIAL FUNCTIONAL PATHS FOR IC TESTING METHODS AND SYSTEM - A method and system of identifying sequential functional paths for IC testing methods are disclosed. In one embodiment, a method may include a method of sequential functional path identification for at-speed structural test, the method comprising: using a timing tool to enumerate a plurality of critical paths in a circuit; identifying which of the plurality of critical paths are sequential functional paths that will function during functional operation of the IC by identifying which of the plurality of critical paths a test can be generated for using a test sequence having n functional capture cycles, where n is greater than 2; performing path test generation for the sequential functional paths using launch-off-scan test sequences; and performing path test generation for critical paths not tested by the launch-of-scan test sequences, using launch-off-capture test sequences having two functional captures. | 09-24-2009 |
| 20100076715 | Trigger router and test system including the trigger router - A test system | 03-25-2010 |
| 20120166131 | INTEGRATED DEVICE TEST CIRCUITS AND METHODS - Test circuits and methods for detecting faults in integrated devices are disclosed. In an embodiment, a circuit may include an input node configured to receive a test signal, and a transition circuit configured to generate a transit on at least one voltage level indicator pin dependent on the test signal. The circuit may also include a data capture circuit configured to capture the output of the at least one voltage level indicator pin to test for stuck-at faults. In another embodiment, a method may include receiving a test signal, generating a transit on at least one voltage level indicator pin dependent on the test signal, and capturing the output of the at least one voltage level indicator pin to test for stuck-at faults. | 06-28-2012 |
| 20100268507 | APPARATUS FOR TESTING MULTIPLE CONDUCTOR WIRING AND TERMINATIONS FOR ELECTRONIC SYSTEMS - An apparatus for testing connections in a system has a plurality of inputs each adapted to couple to a test point in the system under test and a switching module. The switching module includes a first output selectively coupled to receive a first group of one or more of the inputs and a set of outputs corresponding in number to the plurality of inputs, each being selectively coupled to receive a corresponding one of the plurality of inputs. The apparatus may also include a meter coupled to the first switching module output and an array of nodes coupled to the set of switching module outputs, where each node couples a signal to a row sense line and a column sense line. | 10-21-2010 |
| 20120191403 | PROTECTING CHIP SETTINGS USING SECURED SCAN CHAINS - Some embodiments include a method for processing a scan chain in an integrated circuit. The method can include: receiving, in the integrated circuit, the scan chain, wherein the scan chain includes a secret key pattern; separating the secret key pattern from the scan chain; comparing the secret key pattern to a reference key pattern; determining, based on the comparing the secret key pattern to the reference key pattern, that the secret key pattern does not match the reference key pattern; and generating a signal indicating that the secret key pattern does not match the reference key pattern. | 07-26-2012 |
| 20090271140 | SEMICONDUCTOR DEVICE - Cost of testing is reduced. An SiP ( | 10-29-2009 |
| 20130066581 | INTEGRATED CIRCUIT TESTING MODULE INCLUDING SIGNAL SHAPING INTERFACE - Systems and methods of testing integrated circuits are disclosed. The systems include a test module configured to operate between automated testing equipment and an integrated circuit to be tested. The testing interface is configured to test the integrated circuit at a higher slew rate than the slew rate at which signals are received from the automated testing equipment. | 03-14-2013 |
| 20090210188 | 1149.1 TAP LINKING MODULES - IEEE 1149.1 Test Access Ports (TAPs) may be utilized at both IC and intellectual property core design levels. TAPs serve as serial communication ports for accessing a variety of embedded circuitry within ICs and cores including; IEEE 1149.1 boundary scan circuitry, built in test circuitry, internal scan circuitry, IEEE 1149.4 mixed signal test circuitry, IEEE P5001 in-circuit emulation circuitry, and IEEE P1532 in-system programming circuitry. Selectable access to TAPs within ICs is desirable since in many instances being able to access only the desired TAP(s) leads to improvements in the way testing, emulation, and programming may be performed within an IC. A TAP linking module is described that allows TAPs embedded within an IC to be selectively accessed using 1149.1 instruction scan operations. | 08-20-2009 |
| 20110282617 | TEST APPARATUS, TEST METHOD AND SYSTEM - A test apparatus for testing a device under test includes a control apparatus, a plurality of test modules, and a plurality of relay apparatuses that connect the control apparatus and the plurality of test modules, each relay apparatus including (1) an upper port section connected either to the control apparatus or to a relay apparatus nearer the control apparatus; and (2) at least one lower port section connected either to a relay apparatus nearer the plurality of test modules or to a corresponding test module, where each relay apparatus receives, at one of the at least one lower port section, a packet transmitted from the corresponding test module to the control apparatus, and transmits, from the upper port section, the received packet after adding thereto port identification information of the one of the at least one lower port section. | 11-17-2011 |
| 20120239338 | EMPIRICAL PREDICTION OF SIMULTANEOUS SWITCHING NOISE - In an example embodiment, the system obtains the mutual inductance (e.g., M | 09-20-2012 |
| 20100125431 | COMPACT TEST CIRCUIT AND INTEGRATED CIRCUIT HAVING THE SAME - A compact test circuit prevents a chip area increase by reducing the number of global lines, i.e., transmission paths of test mode item signals. The test circuit is capable of reducing a test time by performing several tests in parallel through one test mode item signal. The test circuit includes a test mode item signal generating block configured to generate a plurality of test mode item signals corresponding to test mode items, and a coding block configured to code each of the test mode item signals to generate a multiplicity of test control signals. | 05-20-2010 |
| 20100280786 | ADDRESSABLE INTEGRATED CIRCUIT AND METHOD THEREOF - An exemplary method and system of addressing an integrated circuit within a daisy chain network. In the exemplary method, the address of the integrated circuit may be initialized to a predetermined initial address. The integrated circuit may receive a command that includes a type identifier and an address field. Based on the type identifier, the type of command may be determined. As a result of the determination, reading the address from the address field. The read address may be stored in a register. The address may be modified, and may be output. Upon receipt of the data or a command, the integrity of the data including data within the received command, may be confirmed by an error checking algorithm. | 11-04-2010 |
| 20110270567 | TOOLS FOR DESIGN AND ANALYSIS OF OVER-THE-AIR TEST SYSTEMS WITH CHANNEL MODEL EMULATION CAPABILITIES - A wireless electronic device may serve as a device under test in a test system. The test system may include an array of over-the-air antennas that can be used in performing over-the-air wireless tests on the device under test (DUT). A channel model may be used in modeling a multiple-input-multiple-output (MIMO) channel between a multi-antenna wireless base station and a multi-antenna DUT. The test system may be configured to perform over-the-air tests that emulate the channel model. A design and analysis tool may be used to identify an optimum over-the-air test system setup. The tool may be used in converting a geometric model to a stochastic model for performing conducted tests. The tool may be used in converting a stochastic model to a geometric model and then further convert the geometric model to an over-the-air emulated stochastic model. The over-the-air emulated stochastic model may be used in performing conducted tests. | 11-03-2011 |
| 20080281546 | TEST ACCESS PORT WITH ADDRESS AND COMMMAND CAPABILITY - The disclosure provides a novel method and apparatus for inputting addresses to devices to select the device TAP for access. Further, the disclosure provides a novel method and apparatus for inputting addresses for selecting device TAPs and for inputting commands for commanding circuitry within the device. The inputting of addresses or the inputting of addresses and commands is initiated by a control bit input on TDI that is recognized during the Run Test/Idle, Pause-DR or Pause-IR TAP states. | 11-13-2008 |
| 20100280785 | METHOD FOR TESTING A SOFTWARE APPLICATION - To test a software application, a method submits an electronic board including a component implementing an application to a laser radiation generated in test equipment. The component is excited with laser pulses having very short durations distributed during complex operational phases of the component for running the application, and the reaction of the component and the application are observed. | 11-04-2010 |
| 20080208508 | Test Prepared Rf Integrated Circuit - An integrated circuit ( | 08-28-2008 |
| 20090182523 | APPARATUS AND METHOD FOR CONNECTION TEST ON PRINTED CIRCUIT BOARD - A connection test apparatus includes a controlling section, controlling each connection test device to switch the operation mode between the first and the second modes such that a first connection test device among the connection test devices is in the first mode and the remaining connection devices are in the second mode, and controlling a signal generating circuit to output the connection test signal; and a judging section judging, on the basis of the response signal that the first connection test device outputs in response to the connection test signal, a state of connection of a first connector connected to the first connection test device and a first net including the first connector among the nets. | 07-16-2009 |
| 20110224938 | SYSTEMS AND METHODS FOR TEST TIME OUTLIER DETECTION AND CORRECTION IN INTEGRATED CIRCUIT TESTING - Methods and systems for semiconductor testing are disclosed. In one embodiment, devices which are testing too slowly are prevented from completing testing, thereby allowing untested devices to begin testing sooner. | 09-15-2011 |
| 20110144939 | COMPUTERISED STORAGE SYSTEM COMPRISING ONE OR MORE REPLACEABLE UNITS FOR MANAGING TESTING OF ONE OR MORE REPLACEMENT UNITS - A method, apparatus and software is disclosed, for use in a computerised storage system comprising one or more replaceable units, for managing testing of one or more replacement units, where the storage system is automatically placed in a testing mode in response to a given unit being replaced and if testing fails the storage system automatically fails back to a service mode. | 06-16-2011 |
| 20080319700 | TEST APPARATUS, PATTERN GENERATOR, TEST METHOD AND PATTERN GENERATING METHOD - Provided is a test apparatus for testing a specimen by using a test pattern and an expected value pattern. The test apparatus includes: a control unit for outputting a test pattern to the specimen; a pattern converting unit for converting the expected value pattern based on an output pattern output from the specimen upon an input of the test pattern; and a determination unit for determining the specimen as a non-defective product or a defective product by using the converted expected value pattern. | 12-25-2008 |
| 20100185410 | THREE DIMENSIONAL CHIP FABRICATION - A three-dimensional (3D) chip is fabricated from components that have been cut out of a two-dimensional (2D) chip to create the layers of the 3D chip. By testing the 2D chip first, the layers of the 3D chip have been pre-tested, thus reducing testing and production costs. | 07-22-2010 |
| 20100262397 | MULTIPLY APPARATUS FOR SEMICONDUCTOR TEST PATTERN SIGNAL - An apparatus for multiplying a semiconductor test pattern signal is disclosed. The multiplying apparatus firstly encodes a plurality of pattern signals to have different pattern types, and multiplies the encoded pattern signals according to an exclusive-OR (XOR) scheme in order to generate a single pattern signal, thereby recognizing a relationship between a pattern signal before the multiplication and the other pattern signal after the multiplication. A pattern-signal segmenting/outputting unit segments a semiconductor test pattern signal into a plurality of pattern signals, and simultaneously outputs the segmented pattern signals. A pattern-signal restoring/multiplying unit restores the segmented pattern signals received from the pattern-signal segmenting/outputting unit to the semiconductor test pattern signal, outputs the restored result to a driver which records a test pattern in an objective semiconductor to be tested, and multiplies the signal outputted to the driver by a predetermined frequency band rather than a frequency band of the segmented signals. | 10-14-2010 |
| 20080215282 | 1149.1 TAP LINKING MODULES - IEEE 1149.1 Test Access Ports (TAPs) may be utilized at both IC and intellectual property core design levels. TAPs serve as serial communication ports for accessing a variety of embedded circuitry within ICs and cores including; IEEE 1149.1 boundary scan circuitry, built in test circuitry, internal scan circuitry, IEEE 1149.4 mixed signal test circuitry, IEEE P5001 in-circuit emulation circuitry, and IEEE P1532 in-system programming circuitry. Selectable access to TAPs within ICs is desirable since in many instances being able to access only the desired TAP(s) leads to improvements in the way testing, emulation, and programming may be performed within an IC. A TAP linking module is described that allows TAPs embedded within an IC to be selectively accessed using 1149.1 instruction scan operations. | 09-04-2008 |
| 20090037133 | DEVICE FOR THOROUGH TESTING OF SECURE ELECTRONIC COMPONENTS - An apparatus including a test circuit, an output circuit and a control circuit. The test circuit may be configured to generate test data in response to one or more test vectors. The output circuit may be configured to present data in a first mode and prevent presentation of data in a second mode. The output circuit may be configured to switch between the first mode and the second mode in response to a control signal. The control circuit may be configured to generate the control signal according to predetermined criteria for protecting secure data within the apparatus while allowing the test data to be presented. | 02-05-2009 |
| 20090070061 | SEMICONDUCTOR MEMORY DEVICE INCLUDING TEST MODE CIRCUIT - A semiconductor memory device having a test mode circuit is presented which includes: a mode setting unit, in response to an external command and a first address signal for a mode set, providing a mode register set signal corresponding to predetermined mode setting; and a test mode circuit, in response to the mode register set signal and a second address signal for test enable control in an initial operation, performing test mode enable; the test mode circuit, in response to the mode register set signal and a third address signal for test item selection in the test mode enable state, outputting a test mode item signal; and the test mode circuit, in a subsequent operation, receiving the fed-back test mode item signal to maintain the test mode enable state. | 03-12-2009 |
| 20110246121 | TEST ELEMENT GROUP AND SEMICONDUCTOR DEVICE - A device with a plurality of elements separated into groups, each element including an activation terminal, an input terminal and an output terminal, a plurality of first signal lines, and a plurality of second signal lines, where the input terminals of each element in each group are commonly connected to one of the plurality of first signal lines, the input terminals of the different groups are connected to different first signal lines, and the output terminals of the each element in each group are independently connected to a different one of the plurality of second signal lines. | 10-06-2011 |
| 20100153054 | TEST APPARATUS AND DIAGNOSIS METHOD - Provided is a test apparatus that tests a device under test, comprising: a plurality of modules that each include an output circuit that outputs a prescribed output signal to the device under test and a measurement circuit that measures a prescribed characteristic of the device under test; and a control section that, for each module, causes the measurement circuit to measure output of the output circuit and diagnoses the module based on a measurement result of the measurement circuit. Each measurement circuit measures the output of the corresponding output circuit in parallel, and the control section is provided in common to the plurality of modules and sequentially reads the measurement result of the measurement circuit of each module. | 06-17-2010 |
| 20110119016 | Deterministic Reconfiguration of Measurement Modules Using Double Buffered DMA - Configuring at least one radio frequency (RF) instrument according to a plurality of RF measurement configurations for performing a plurality of tests on a device under test (DUT). A list of RF measurement configurations may be stored in a computer memory. The list of RF measurement configurations comprises a plurality of parameters for configuring operation of the at least one instrument. Information regarding the list of RF measurement configurations (e.g., a data stream) may be provided to the at least one RF instrument. The at least one RF instrument may perform the plurality of tests on the DUT, including the at least one RF instrument configuring itself according to the RF measurement configurations based on processing of the information. Configuring enables the at least one RF instrument to perform the plurality of tests on the DUT in a deterministic manner. | 05-19-2011 |
| 20090048801 | Method and apparatus for generating thermal test vectors - Temperature aware testing enables computation of thermal test vectors that are applied, via a tester, to a Device Under Test (DUT) to place various internal elements of the DUT at respective temperature operating points. The respective temperature operating points are selected to sensitize the DUT to measurements of selected temperature-dependent critical parameters, including frequency, leakage current behaviors, voltage drops, power profiles, thermal gradients, and absolute temperature. In operation, the thermal test vectors are applied to the DUT for a sufficient time for the DUT to reach thermal equilibrium, or alternatively for the internal elements to reach the respective temperature operating points. Subsequently critical parameter vectors are applied to enable measurement of one or more of the critical parameters. The critical parameter vectors are typically developed based in part on a multi-dimensional temperature map analysis of the DUT, using manufacturing process parameters and device physical design (or layout) information. | 02-19-2009 |
| 20110251819 | INTEGRATED CIRCUIT TESTING MODULE INCLUDING SIGNAL SHAPING INTERFACE - Systems and methods of testing integrated circuits are disclosed. The systems include a test module configured to operate between automated testing equipment and an integrated circuit to be tested. The testing interface is configured to test the integrated circuit at a higher slew rate than the slew rate at which signals are received from the automated testing equipment. In order to do so, the testing interface includes components configured for generating addresses, commands, and test data to be conveyed to the integrated circuit. A variety of test data patterns can be produced and the test data can be address dependent. The systems are optionally configured to include a test plan memory component configured to store one or more test plans. A test plan may include a sequence of test patterns and/or conditional branches whereby the tests to be performed next are dependent on the results of the preceding tests. The test plan memory is, optionally, be detachable from the test module. | 10-13-2011 |
| 20110251818 | KEYBOARD TEST PROGRAM GENERATING METHOD - A keyboard test program generating method includes the following steps. Firstly, a first key number is received. By pressing a first key, a first key identification code corresponding to the first key is generated. The first key number is assigned to the first key so as to generate a first key conditional expression. By pressing a next key, a next key identification code corresponding to the next key is generated. A second key number following the first key number is assigned to the next key so as to generate a next key conditional expression. Afterwards, these key conditional expressions, a keyboard test program header and a keyboard test program trailer are combined together, thereby generating the keyboard test program. | 10-13-2011 |
| 20100235136 | SYSTEM AND METHOD FOR AUTOMATICALLY GENERATING TEST PATTERNS FOR AT-SPEED STRUCTURAL TEST OF AN INTEGRATED CIRCUIT DEVICE USING AN INCREMENTAL APPROACH TO REDUCE TEST PATTERN COUNT - Disclosed are embodiments of a system and method for automatically selecting and generating test patterns for an at-speed structural test of an integrated circuit device. Specifically, a test pattern generation pass is started and proceeds until the “knee” of the simulated test coverage curve is observed. Next, the test patterns are optionally reordered and some are removed. Then, another test pattern generation pass is started. The process is repeated iteratively until some predetermined final stopping criterion is met. By performing multiple test pattern generation passes and reducing the number of available test patterns that can be generated with each pass, the method exploits the initial increase in the test coverage curve inherent in each pass and limits the overall test pattern count. | 09-16-2010 |
| 20110082661 | Card Interface Direction Detection System - A card interface direction detection system includes a card. A power pin is mounted to the card and connected to a power source. A ground pin is mounted to the card and connected to a ground. A direction pin is mounted to the card. A controller is coupled to an information handling system (IHS) and that includes an in node and an out node that are each connected to the direction pin. The in node is directly connected to the direction pin and a resistor is located between the out node and the direction pin such that a signal sent through out node results in a signal received through the in node that allows the controller to detect whether the mode of operation of the card is supported by the IHS. | 04-07-2011 |
| 20110060546 | Intergrated circuit (IC) with primary and secondary networks and device containing such IC - Some embodiments provide an integrated circuit (“IC”) with a primary circuit structure. The primary circuit structure is for performing multiple operations that implement a user design. The primary circuit structure includes multiple circuits. The IC also includes a secondary monitoring structure for monitoring multiple operations. The secondary monitoring structure includes a network communicatively coupled to multiple circuits of the primary circuit structure. The secondary monitoring circuit structure is for analyzing the monitored operations and reporting on the analysis to a circuit outside of the IC. | 03-10-2011 |
| 20110060545 | TEST APPARATUS AND TEST METHOD - Provided is a test apparatus that tests a device under test, comprising a pattern list storage section that stores a plurality of pattern lists that each designate, in a prescribed order, the test patterns to be output by the device under test; and a pattern list processing section that (i) sequentially outputs the test patterns by sequentially executing the pattern lists according to test results of the device under test and, (ii) when transitioning from a current pattern list to a subsequent pattern list, repeatedly outputs a prescribed idle pattern until execution of the subsequent pattern list is begun. | 03-10-2011 |
| 20090248347 | TESTING MODULE, TESTING APPARATUS AND TESTING METHOD - To increase the overall efficiency of a test apparatus, provided is a test module that includes an instruction information storage section that stores instruction information indicating an order in which basic patterns are expanded; a basic pattern data storage section that stores basic pattern data; a plurality of pattern generating sections that each include a temporary instruction information storage section, which temporarily stores a portion of the instruction information, and that each generate a test pattern supplied to a device under test by expanding the basic pattern data in the order indicated by the instruction information stored in the corresponding temporary instruction information storage section; and a plurality of position information storage sections that independently store position information indicating reading positions of the instruction information stored in the instruction information storage section that is common to the plurality of pattern generating sections, in association with each pattern generating section. | 10-01-2009 |
| 20090240460 | TEST CIRCUIT FOR PERFORMING MULTIPLE TEST MODES - A test circuit includes a first reset pulse generator configured to generate a first reset pulse when a test mode is performed or when power is up, a test mode maintenance signal generator configured to provide a test mode maintenance signal activated in response to a predetermined consecutive test information data, the activation of the test mode maintenance signal being controlled by the first reset pulse, a second reset pulse generator configured to generate a second reset pulse when the test information data is received as a predetermined test mode reset data or when power is up, and a test mode selection signal generator configured to receive the test information data provided from the test mode maintenance signal generator and the test mode maintenance signal and to generate a specific test mode selection signal, the activation of the specific test mode selection signal being controlled by the second reset pulse. | 09-24-2009 |
| 20090240458 | METHOD FOR TESTING INTEGRATED CIRCUITS - A method of testing an integrated circuit. The method includes selecting a set of physical features of nets and devices of the integrated circuit, the integrated circuit having pattern input points and pattern observation points connected by the nets, each of the nets defined by an input point and all fan out paths to (i) input points of other nets of the nets or (ii) to the pattern observation points; selecting a measurement unit for each feature of the set of features; assigning a weight to each segment of each fan out path based on a number of the measurement units of the feature in each segment of each fan out path of each of the nets; and generating a set of test patterns optimized for test-coverage and cost based on the weights assigned to each segment of each of the nets of the integrated circuit. | 09-24-2009 |
| 20120150477 | DRIVING CIRCUIT OF A TEST ACCESS PORT - A driving circuit of a test access port is disclosed. The driving circuit includes an input terminal for receiving a first test data signal when the driving circuit is operating in an external test mode. The driving circuit is configured to receive a second test data signal (BS) carrying a test command to be executed on the test access port when the driving circuit is operating in an internal test mode. The driving circuit comprises a control logic circuit configured for processing the test command and generating therefrom an internal test data signal carrying the processed test command when the driving circuit is operating in the internal test mode. The driving circuit includes a selector configured for generating a selected test data signal, the selected test data signal being selected from the first test data signal when the driving circuit is operating in the external test mode. | 06-14-2012 |
| 20110071786 | SEMICONDUCTOR DEVICE AND ITS TESTING METHOD - A semiconductor device | 03-24-2011 |
| 20100312518 | Integrated Circuit Arrangement - An integrated circuit arrangement has a signal input | 12-09-2010 |
| 20090171611 | Reducing Mission Signal Output Delay in IC Having Mission and Test Modes - An integrated circuit apparatus includes a switching circuit that provides respective signal paths to permit a mission signal, a test signal, and a boundary scan test signal to share an output terminal. The signal path associated with the mission signal imposes a smaller switching delay than do the signal paths associated with the test and boundary scan test signals. | 07-02-2009 |
| 20110137605 | TEST MODULE, TEST APPARATUS, AND TEST METHOD - Provided is a test module comprising a specified pattern detecting section that detects a specified pattern output in response to a specified test pattern from a device under test outputting output patterns in response to test patterns; a timing detecting section that detects a timing at which the specified pattern is detected; and a phase adjusting section that adjusts phases of the output patterns to match phases of expected value patterns, which are expected from the device under test as responses to the test patterns, based on the timing detected by the timing detecting section. | 06-09-2011 |
| 20100204949 | Semiconductor test system with self-inspection of electrical channel - A semiconductor test system with self-inspection of an electrical channel is disclosed, which comprises a tester head, a plurality of parameter detection units and a self-inspection controller. The tester head includes a plurality of pin electronics cards inserted therein, in which the plurality of pin electronics cards contain a plurality of power channels, a plurality of I/O channels and a plurality of drive channels. The self-inspection controller outputs different inspection signals respectively to each power channel, each I/O channel and each drive channel. Then, the plurality of parameter detection units detect response signals respectively produced by each power channel, each I/O channel and each drive channel in response to the inspection signals respectively received thereby, and the response signals are judged by the self-inspection controller. Thus, the invention is capable of self-inspecting each electrical channel if it is in a normal condition, either in an open or short circuit, or if there exists a leakage condition. | 08-12-2010 |
| 20100082284 | TEST APPARATUS - Provided is a test apparatus | 04-01-2010 |
| 20110307209 | Diagnosis of Integrated Driver Circuits - A circuit arrangement includes a controller and an integrated driver arrangement coupled to the controller. The integrated driver circuit includes a driver unit having at least one operation parameter, and a diagnostic unit coupled to the driver unit. The diagnostic unit is adapted to retrieve the at least one operation parameter from the driver unit, and is coupled to the controller. | 12-15-2011 |
| 20110166819 | DIFFERENTIAL SR FLIP-FLOP - A differential SR flip-flop | 07-07-2011 |
| 20110015890 | TEST APPARATUS - Provided is a test apparatus that tests a device under test, comprising a test module that transmits and receives signals to and from the device under test; and a test control section that executes a test program for testing the device under test and that instructs the test module to execute a function designated by the test program from among a plurality of functions of the test module. The test module includes a signal input/output section that transmits and receives signals to and from the device under test; and a module control section that executes a function program according to the function designated by the test program and that accesses at least one of a register and a memory in the signal input/output section. | 01-20-2011 |
| 20120022821 | INTEGRATED CIRCUIT THAT TRANSFERS MISSION MODE SIGNAL IN DEBUG MODE - A system including an integrated circuit configured to transfer a mission mode signal between a mission mode circuit on the integrated circuit and a first input/output pin on the integrated circuit in mission mode and to transfer a development mode signal between a development mode circuit on the integrated circuit and the first input/output pin in debug mode. The integrated circuit is configured to transfer the mission mode signal between the mission mode circuit and a second input/output pin on the integrated circuit in debug mode. | 01-26-2012 |
| 20080281547 | Test circuit - A test circuit including a TAP controller specified in IEEE (Institute of Electrical and Electronics Engineers) 1149 and a test access port includes a first controller including a selecting circuit and a first TAP controller, the selecting circuit generating an internal TMS signal in accordance with TMS signal and selecting an output destination of the internal TMS signal in accordance with a selection signal, and the first TAP controller changing internal state based on the internal TMS signal, testing corresponding test target block in accordance with instruction code for test, and generating the selection signal in accordance with instruction code for selection, and a second controller including a second TAP controller changing internal state based on the internal TMS signal and testing corresponding test target block in accordance with the instruction code for test. | 11-13-2008 |
| 20110093235 | SEMICONDUCTOR DEVICE - A semiconductor device is provided. The semiconductor device applies data applied through a bump pad on which a bump is mounted through a test pad to a test apparatus such that the reliability of the test can be improved. The amount of test pads is significantly reduced by allowing data output through bump pads to be selectively applied to a test pad. Data and signals applied from test pads are synchronized with each other and applied to bump pads during a test operation such that the reliability of the test can be improved without the need of an additional test chip. | 04-21-2011 |
| 20110106483 | METHOD AND APPARATUS FOR SELECTING PATHS FOR USE IN AT-SPEED TESTING - In one embodiment, the invention is a method and apparatus for selecting paths for use in at-speed testing. One embodiment of a method for selecting a set of n paths with which to test an integrated circuit chip includes: organizing the set of n paths into a plurality of sub-sets, receiving a new candidate path, and adding the new candidate path to one of the sub-sets when the new candidate path improves the process coverage metric of the sub-sets. | 05-05-2011 |
| 20110184688 | SEMICONDUCTOR DEVICE, TEST METHOD THEREOF, AND SYSTEM - A semiconductor device includes a plurality of chips comprising a plurality of I/O terminals connected in common via through electrodes. Each of the chips includes an I/O compression circuit operable to output a compression result obtained by compression of data of a plurality of internal data buses to a first I/O terminal of the plurality of I/O terminals. Each of the chips also includes a test control circuit having a register group that sets the number of the first I/O terminal. Setting information that assigns different first I/O terminals to different chips is set in the register group. Each of the chips inputs or outputs data with use of the number of the I/O terminal that is different from those in other chips. Thus, the I/O compression circuits can concurrently perform an I/O compression test in parallel in the plurality of chips without a bus fight. | 07-28-2011 |
| 20100049464 | SYSTEM FOR TESTING INTEGRATED CIRCUITS - The invention provides for a system for testing integrated circuitry. The system includes a local computational device, a communications link connected to the computational device, and testing circuitry operatively connected to the computational device via the communications link and configured to generate integrated circuitry test signals. The system also includes adaptor circuitry connected to the testing circuitry and configured to provide an electrical and physical interface with the integrated circuits, as well as routing circuitry interposed between the testing and adaptor circuitry to rout the test signals to respective dies of the integrated circuits. Also included is a handling mechanism for retaining and manipulating a carrier on which the integrated circuits are positioned, and a controller operatively connected to the handling mechanism for controlling operation thereof and connected to the communications device for supervision by the computational device. | 02-25-2010 |
| 20100274518 | Diagnostic Test Pattern Generation For Small Delay Defect - Methods of diagnostic test pattern generation for small delay defects are based on identification and activation of long paths passing through diagnosis suspects. The long paths are determined according to some criteria such as path delay values calculated with SDF (Standard Delay Format) timing information and the number of logic gates on a path. In some embodiments of the invention, the long paths are the longest paths passing through a diagnosis suspect and reaching a corresponding failing observation point selected from the failure log, and N longest paths are identified for each of such pairs. | 10-28-2010 |
| 20120253733 | TRANSACTION BASED WORKLOAD MODELING FOR EFFECTIVE PERFORMANCE TEST STRATEGIES - A method for creating workload model to test performance of a critical application in a data processing network ( | 10-04-2012 |
| 20120259575 | INTEGRATED CIRCUIT CHIP INCORPORATING A TEST CIRCUIT THAT ALLOWS FOR ON-CHIP STRESS TESTING IN ORDER TO MODEL OR MONITOR DEVICE PERFORMANCE DEGRADATION - Disclosed is an integrated circuit chip incorporating a test circuit having multiple logic blocks. Each logic block is a matrix of individually selectable, physically different, test devices in a specific class of devices. An embedded processor ensures that specific stress conditions are selectively applied to the test devices and further controls selective testing, by a sensor system, of the test devices to determine the impact of the applied stress conditions. In a laboratory or test system environment, accelerated stress conditions are selectively applied to the test devices and the testing results are used to model device performance degradation due to class-specific failure mechanisms. In the field, stress conditions are selectively applied to test devices so as to mimic stress conditions impacting active devices in use on the same chip and the testing results are used to indirectly monitor performance degradation of the active devices due to class-specific failure mechanisms. | 10-11-2012 |
| 20110004434 | LOW POWER TESTING OF VERY LARGE CIRCUITS - Plural scan test paths ( | 01-06-2011 |
| 20120283981 | TEST PATTERN GENERATION FOR SEMICONDUCTOR INTEGRATED CIRCUIT - A test pattern is sequentially selected from an original test pattern sequence constituted by a plurality of test patterns including a don't care bit. Power consumption in each of regions obtained by substantially equally dividing a layout region of a semiconductor integrated circuit in a case where a don't care value is specified in the selected test pattern and this selected test pattern is applied to the semiconductor integrated circuit is estimated. A searching is conducted for a don't care value of the selected test pattern which minimizes a variation in power consumption among the regions by repeatedly changing the don't care value and repeatedly estimating power consumption in the regions. A new test pattern sequence constituted by a plurality of test patterns including no don't care bit is generated by defining the don't care value obtained by the searching as a don't care value of the selected test pattern. | 11-08-2012 |
| 20110320160 | INTEGRATED CIRCUIT, SIMULATION APPARATUS AND SIMULATION METHOD - The disclosed device performs a control of generating a test pattern for the delay test of LSI. The input pattern control circuit counts a cycle number of an input pattern supplied to a test object circuit, and stops supply of the input pattern to the test object circuit when the cycle number of the input pattern coincides with a certain count number. The scan control circuit receives a control signal from the input pattern control circuit, and supplies a scan shift signal to the test object circuit to shift a scan chain in the test object circuit. | 12-29-2011 |
| 20120150478 | METHOD OF TESTING AN OBJECT AND APPARATUS FOR PERFORMING THE SAME - In a method of testing an object, a first test pattern for testing a first device in the object may be set in a tester. A second test pattern for testing a second device in the object may be set in a test head electrically connected between the tester and the object. The first test pattern may be provided to the first device through the test head and the second test pattern may be provided to the second device by the test head to simultaneously test the first device and the second device. Thus, the first device and the second device different from each other may be simultaneously tested without changing test conditions in the tester, so that a time for testing the object may be reduced. | 06-14-2012 |
| 20100088059 | ABNORMAL SIMULATION SIGNAL ANALYSIS METHODS AND ABNORMAL SIGNAL SIMULATION ANALYSIS MODULE FOR 4.about.20mA INSTRUMENTAL SYSTEM - The present invention relates to a negative pulse transient signal analysis methods and negative pulse transient signal analysis module for a PC base simulation equivalent circuit capable of grasping and improving error causes through an abnormal signal analysis after configuring a simulation equivalent circuit for a 4˜20 mA instrument unsatisfied in a temperature environmental impact assessment. | 04-08-2010 |
| 20130090887 | HETEROGENEOUS MULTI-CORE INTEGRATED CIRCUIT AND METHOD FOR DEBUGGING SAME - A heterogeneous multi-core integrated circuit includes first and second sets of processor cores and corresponding first and second test access ports (TAPs). The first and second TAPs are connected to corresponding first and second debug ports by way of corresponding first and second TAP controllers. A debug control circuit is connected between the first and second TAP controllers and the first and second debug ports. Based on external configuration signals, the debug control circuit configures the connections between the first and second TAP controllers and the first and second debug ports according to predetermined configuration modes, which allows flexibility in debugging the heterogeneous multi-core integrated circuit. | 04-11-2013 |
| 20130124134 | FAST SINGLE-ENDED TO DIFFERENTIAL CONVERTER - A single ended to a differential signal converter. The single ended signal is passed through a high pass filter to block DC components. A positive and a negative version of the filtered signal are used collectively as the differential output of the converter. To allow accurate measurements on the input signal without waiting for the output of the high pass filter to settle, the differential outputs are offset by a dynamically generated signal representative of the midpoint of the filtered signal. That offset is generated by capturing a value representing the midpoint when a signal is first applied. This captured value is allowed to change with a time constant matching a time constant of the high pass filter. The converter may be used to connect a test instrument to a unit under test that generates test signals in a format that the test instrument is not specifically configured to measure. | 05-16-2013 |
| 20130124133 | PRODUCT PERFORMANCE TEST BINNING - A method, test system and computer program product and system for voltage binning integrated circuit chips. The method includes selecting or changing a voltage bin of an integrated circuit chip using functional testing of data paths of the integrated circuit chip. | 05-16-2013 |
