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Of circuit

Subclass of:

702 - Data processing: measuring, calibrating, or testing

702108000 - TESTING SYSTEM

Patent class list (only not empty are listed)

Deeper subclasses:

Class / Patent application numberDescriptionNumber of patent applications / Date published
702120000 Including input/output or test mode selection means 67
702119000 Including program initialization (e.g., program loading) or code selection (e.g., program creation) 61
702118000 Testing multiple circuits 31
Entries
DocumentTitleDate
20130030752OPERATION CHECK TEST METHOD, PROGRAM AND CLOCK DISTRIBUTION CIRCUIT - A method to perform an operation check test of a phase control circuit of a clock distribution circuit is disclosed that includes shifting one of the phases of the first differential signals and the second differential signals with reference to the other of the phases; obtaining an output data signal of the differential DFF to which the first differential signals and the second differential signals are input, one of the phases being shifted by the shifting; and comparing first values of the plural output data signals with first expected data values, the first values of the plural output data signals being obtained by performing the shifting and the obtaining repeatedly until phase differences of the first differential signals and the second differential signals reach one cycle of the first differential signals and the second differential signals.01-31-2013
20110191055METHOD AND APPARATUS FOR SELECTING VOLTAGE AND FREQUENCY LEVELS FOR USE IN AT-SPEED TESTING - In one embodiment, the invention is a method and apparatus for selecting voltage and frequency levels for use in at-speed testing. One embodiment of a method for selecting a set of test conditions with which to test an integrated circuit chip includes formulating a statistical optimization problem and obtaining a solution to the statistical optimization problem, where the solution is the set of test conditions.08-04-2011
20090192754SYSTEMS AND METHODS FOR TEST TIME OUTLIER DETECTION AND CORRECTION IN INTEGRATED CIRCUIT TESTING - Methods and systems for semiconductor testing are disclosed. In one embodiment, devices which are testing too slowly are prevented from completing testing, thereby allowing untested devices to begin testing sooner.07-30-2009
20090192752AUTOMATED PORTABLE MEDIA DEVICE TESTING SYSTEM - Circuits, methods, and apparatus for testing media devices. One example provides a test system for testing a number of media players. One or more computers can control the testing of the media players and collect results. Each media player tested may be connected to a computer via an adapter. The adapter may include a connection control circuit and an interface. The connection control circuit may connect and disconnect a power supply to the media player being tested. The voltage waveform produced when the power supply is connected and disconnected may be designed to mimic the voltage waveform produced when a user connects and disconnects a cable or docking station from the media player. The interface may receive commands to provide specific instructions to the media player. The interface may monitor the status and activities performed by the media player and report back to the computer.07-30-2009
20120179411SEMICONDUCTOR CIRCUIT, SEMICONDUCTOR DEVICE, LINE BREAK DETECTION METHOD, AND COMPUTER READABLE MEDIUM STORING LINE BREAK DETECTION PROGRAM - When line break detection of signal line Ln is carried out, potential smaller than signal line Ln−1 having lower potential than signal line Ln is supplied to signal line Ln, and potentials of signal line Ln and signal line Ln−1 are compared. If potential of signal line Lc>signal line Li, it is detected no line break, and if signal line Lcsignal line Li, it is detected that a line break exists.07-12-2012
20120245879PROGRAMMABLE TEST CHIP, SYSTEM AND METHOD FOR CHARACTERIZATION OF INTEGRATED CIRCUIT FABRICATION PROCESSES - A test chip, system and method for testing large numbers of test devices on a single test chip decreases the time and complexity required to characterize the variation and reliability of the IC fabrication process. A remotely configurable test chip can be programmed with varying bias conditions for testing of process variation or numerous failure modes on large sample sizes. An on-chip addressing technique allows large numbers of test devices to be tested simultaneously and the measurement signals read out serially for different test devices. The test chip may be configured for wafer, die or package-level testing.09-27-2012
20130080107TESTER HAVING SYSTEM MAINTENANCE COMPLIANCE TOOL - A tester module for automatic test equipment (ATE) includes test instruments for testing an integrated circuit device under test (DUI). A plurality of sensors include sensors coupled to or proximate to the test instruments for detecting a plurality of different maintenance triggers associated with the test instruments. A memory stores code including operating system code for controlling the test instruments and for implementing a system maintenance compliance tool. A processor is coupled to the test instruments, the sensors and the memory. The processor runs the operating system code including the system maintenance compliance tool. The system maintenance compliance tool upon receiving notification of at least a first maintenance trigger automatically blocks the ATE being used for the testing. The system maintenance compliance tool can include a listing of needed maintenance actions associated with the maintenance triggers that when completed automatically releases the ATE to allow resumption of testing.03-28-2013
20100106448VOTER TESTER FOR REDUNDANT SYSTEMS - A tester is configured to access and test each redundant channel of a voter. The tester is disposed between the voter and a multitude of redundant circuits supplying redundant channel signals to the voter. The tester includes a number of input ports receiving the redundant channel signals as well as the test signals. In response to a number of logic combinations of the test signals, the voter generates output signals each corresponding to one of the redundant channel signals. In response to other logic combinations of the test signals, the voter generates a voted output signal. The voter is optionally a majority voter.04-29-2010
20100106447DEFECT ANALYZING APPARATUS AND DEFECT ANALYZING METHOD - A defect analyzing apparatus capable of acquiring standard data easily and a defect analyzing method are provided. The defect analyzing apparatus includes: a storage section storing data including information of a processing pattern corresponding to a predetermined processing to a semiconductor wafer; a first extracting section extracting a first frequency distribution of each of characteristics in a plurality of sample places in a semiconductor chip; a second extracting section extracting a second frequency distribution of each of the characteristics in a plurality of defect places in the semiconductor chip; and a detecting section detecting discrepancies between the first and second frequencies.04-29-2010
20090125272METHOD FOR ANALYZING CIRCUIT - A method for analyzing circuit comprises the steps of selecting a plurality of elements; sampling the selected elements, resulting in a plurality of sampling-parameter sets; simulating the sampling-parameter sets to generate a plurality of simulation-results, and process the regression operation for the sampling-parameter sets and simulation-results in order to acquire the contribution rank of each sampling-parameter set and element. Accordingly, while analyzing similar circuits, the partial elements can be selected according to the contribution rank and further sampled; thereby, the amount of sampling-parameter sets can be advantageously reduced, and the analysis efficiency can be improved according to the circuit.05-14-2009
20100094580Method and system for device reconfiguration for defect amelioration - Embodiments of the present invention are directed to cost-effective defect amelioration in manufactured electronic devices that include nanoscale components. Certain embodiments of the present invention are directed to amelioration of defects in electronic devices that contain nanoscale demultiplexers. In certain embodiments of the present invention, the nanoscale-demultiplexer-containing devices include reconfigurable encoders. In one embodiment of the present invention, the table of codes within a reconfigurable encoder is permuted, and a device is configured in accordance with the permuted codes, in order to produce a permuted table of codes that, when input to an appropriately configured nanoscale demultiplexer, produces correct outputs despite defects in the nanoscale demultiplexer.04-15-2010
20130046504COMPUTING DEVICE, STORAGE MEDIUM, AND METHOD FOR TESTING INTEGRITY OF SIGNALS TRANSMITTED FROM HARD DISK INTERFACES - In a method for testing integrity of signals transmitted from hard disk interfaces using a computing device, the computing device connects to an oscilloscope and a mechanical arm that is equipped with a test fixture. The mechanical arm controls the test fixture to make contact with one of the hard disk interfaces to be tested. The method adjusts an intensity grade of the signals through the hard disk interface, and controls the hard disk interface to produce a signal corresponding to the adjusted intensity grade. The test fixture obtains the signal from the hard disk interface, and the oscilloscope measures one or more test parameters of the signal. The method analyzes values of the test parameters to find an optimal signal, determines an intensity grade of the optimal signal as a driving parameter of the hard disk interface, and generates a test report of the hard disk interfaces.02-21-2013
20130046503TESTING SYSTEM AND METHOD HAVING WIRELESS DATA TRANSMISSION CAPABILITY - Testing system and method with wireless transmission tested data function are provided. An electronic device performs self-testing by a testing program or a testing instrument so as to generate tested data and transmits the tested data to a server via a wireless network. A processing device linked to the server via the wireless network obtains and processes the tested data so as to generate processed data. The processing device further transmits the processed data to the server via the wireless network. Accordingly, the processing device immediately and remotely monitors the electronic device, which is located on a production line, thereby effectively reducing manpower and costs.02-21-2013
20130046502MOTHERBOARD TEST DEVICE - A test device for testing a motherboard includes a connector, a processor, and a controller. The motherboard includes a slot including a sleep unit and a wake port. The connector is inserted into the slot to make an electrical connection with the motherboard. The processor includes a first pin connected to the wake port, a second pin connected to the sleep unit, and a control port sending control signals to the first pin and the second pin. The controller includes a first control module, a second control module, and a timer. The timer is programmed with at least two time points. Wherein the first control module and the second control module respectively send signals to the control port at each time point, to control the motherboard to enter the sleep mode and wake mode by turns.02-21-2013
20130060506INTACT METHOD OF EVALUATING UNIT CELLS IN A FUEL CELL STACK AND A DEVICE USING THE SAME - Disclosed are a method and an apparatus for an intact evaluation of the unit cells in a fuel cell stack. Since the degradation of the unit cells can be detected intactly, i.e. without disassembly of the stack, the time required for the detection and analysis thereof can be greatly reduced.03-07-2013
20130060505TECHNIQUE FOR WAFER TESTING WITH MULTIDIMENSIONAL TRANSFORM - Wafer sort data can be converted to binary data, whereby each integrated circuit of the wafer is assigned a value of one or zero, depending on whether test data indicates the integrated circuit complies with a specification. In addition, each integrated circuit is assigned position data to indicate its position on the wafer. A frequency transform, such as a multidimensional discrete Fourier transform (DFT), is applied to the binary wafer sort data and position data to determine a spatial frequency spectrum that indicates error patterns for the wafer. The spatial frequency spectrum can be analyzed to determine the characteristics of the wafer formation process that resulted in the errors, and the wafer formation process can be modified to reduce or eliminate the errors.03-07-2013
20120226463SYSTEM AND METHOD FOR PHYSICALLY DETECTING COUNTERFEIT ELECTRONICS - A system for inspecting or screening electrically powered device includes a signal generator inputting a preselected signal into the electrically powered device. There is also an antenna array positioned at a pre-determined distance above the electrically powered device. Apparatus collects RF energy emitted by the electrically powered device in response to input of said preselected signal. The signature of the collected RF energy is compared with an RF energy signature of a genuine part. The comparison determines one of a genuine or a counterfeit condition of the electrically powered device.09-06-2012
20120116708GRAPHIC RENDERING OF CIRCUIT POSITIONS - A method may include receiving circuit information from a backend circuit test system and grouping components in the circuit information into collections by types, the types including segments, equipment, ports, and connections. The method may further include positioning, based on the grouping by types, the components from the circuit information for presentation of a circuit design on a display, and performing path rendering for the circuit design based on the positioning of the components. The method may also include sending an output file with the path rendering to a web browser.05-10-2012
20130166244SUPERVISOR MONITORING SYSTEM - A supervisor monitoring system for autonomous test supervision is presented. A system can comprise a first supervisor monitor (SM) and a second SM, each configured to simultaneously monitor one or more tests conducted by one or more testing apparatus. First and second SMs can be configured to verify the other's integrity throughout a testing procedure, providing a failsafe system. The first and second SMs can be interlocked so that if the first SM detects a fault at the second SM, the first SM can interrupt testing monitored at the first SM, and can also interrupt testing monitored at the second SM, and vice versa. An SM can be configured to control a safety relay configured to couple a power channel of a battery exerciser to a battery cell, and be configured to monitor input at the battery exerciser from the cell to determine whether a test constraint has been violated.06-27-2013
20110087453RELIABILITY TEST WITH MONITORING OF THE RESULTS - An embodiment for executing a reliability test is proposed. A corresponding electronic device includes functional means for implementing a functionality of the electronic device, and testing means for executing a test of the functional means including a plurality of test operations on the functional means; the testing means returns an indication of a result of each test operation. In an embodiment, the electronic device further includes control means for causing the testing means to reiterate the test, monitoring means for monitoring the result of each test operation to detect a failure of the test operation, and storage means for storing failure information indicative of temporal characteristics of each failure.04-14-2011
20110282616TEST APPARATUS AND TEST METHOD - Provided is a test apparatus that tests a device under test, comprising a control apparatus that controls testing of the device under test; a test unit that sends and receives signals to and from the device under test; and a buffer section that buffers access requests transmitted from the control apparatus to the test unit and, prior to completion of a write request to a predetermined buffer control address from the control apparatus, issues previously buffered access requests to the test unit side.11-17-2011
20110288807FAILURE DETECTING METHOD, SEMICONDUCTOR DEVICE, AND MICROCOMPUTER APPLICATION SYSTEM - The present invention is directed to improve the precision of failure detection by performing the failure detection by changing an analog amount of a circuit to be subjected to the failure detection. An analog amount of the circuit to be subjected to failure detection is changed under a predetermined condition by a tuning circuit, and a state change in the circuit to be subjected to failure detection based on the change in the analog amount in the circuit to be subjected to failure detection is determined by a failure detection circuit, thereby detecting a failure in the circuit to be subjected to failure detection. In such a manner, without monitoring an output of the failure detection circuit on the outside of a semiconductor device, a failure in the circuit to be subjected to failure detection can be detected. Moreover, an actual state change in the circuit to be subjected to failure detection based on a change in the analog amount in the circuit to be subjected to failure detection is determined by the failure detection circuit, so that precision of failure detection is improved.11-24-2011
20120065920EVALUATION METHOD, EVALUATION APPARATUS, AND SIMULATION METHOD OF SEMICONDUCTOR DEVICE - An evaluation method of a semiconductor device according to an aspect of the present invention includes MISFETs including a gate insulating film, the evaluation method including measuring an RTN of a plurality of MISFETs, and extracting at least two parameters selected from a position of a trap in the gate insulating film, an energy of the trap, an RTN time constant, and an RTN amplitude based on a measurement result of the RTN, and obtaining a correlation between these at least two parameters.03-15-2012
20110218755INTEGRATED CIRCUIT AND TEST METHOD THEREFOR - Disclosed is a method of testing an integrated circuit (09-08-2011
20090306925SYSTEMS AND METHODS FOR TESTING INTEGRATED CIRCUIT DEVICES - Embodiments described herein relate to systems and methods for testing integrated circuit devices within an environment that is representative of the application environment in which an integrated circuit device will be used. In at least one embodiment, the testing system comprises a controller coupled to at least one coupling between a processor and a first reference integrated circuit device of an application system, wherein the first controller is configured to: tap the first test data transmitted via the at least one coupling; transmit second test data to a second reference integrated circuit device, wherein the second test data comprises at least a portion of the first test data; receive reference response data from the second reference integrated circuit device in response to the second test data transmitted thereto; transmit the second test data to at least one integrated circuit device under test; and transmit the reference response data to at least one comparator coupled to the at least one integrated circuit device under test.12-10-2009
20120271585Test System Having a Sub-System to Sub-System Bridge - A test system having a sub-system to sub-system bridge may be provided that utilizes the useful attributes of a plurality of circuit testing techniques, while reducing deficiencies associated with certain types of circuit testing. A bridged test system structure is utilized to facilitate circuit testing that is more effective and time efficient. The method analyzes performance data acquired by a first component for one or more circuits, and sends that performance data to a second test component. The second test component provides test signals to the circuits, using the performance date to enhance the use of the test signals, and also provides test response data for the circuits in response to the provided test signals.10-25-2012
20090089003Accessory-testing device and method therefor - An accessory-testing device for an information processing apparatus includes a micro-processing unit (MPU) and a signal conversion unit. The MPU sends a mimic signal. The signal conversion unit is electrically connected to the MPU and an accessory respectively, for receiving the mimic signal and converting the mimic signal into a test signal to test the accessory. The accessory receives the test signal and then responds to the test signal to output a feedback signal. The feedback signal is received by the signal conversion unit and transmitted to the MPU, such that the MPU determines if the accessory operates normally according to the feedback signal. Conventional testing methods are Therefore, it is achieved that the effects of reducing the inspection time and improving the production efficiency.04-02-2009
20090281757Self-testing device component - A device has a microcontroller (11-12-2009
20100204947BRIDGE FAULT REMOVAL APPARATUS, BRIDGE FAULT REMOVAL METHOD, AND COMPUTER READABLE MEDIUM COMPRISING COMPUTER PROGRAM CODE FOR REMOVING BRIDGE FAULT - A bridge fault removal apparatus includes a bridge fault extraction unit configured to extract a bridge fault from layout information of a semiconductor integrated circuit, a test pattern generator configured to generate the test pattern aiming at the bridge fault extracted by the bridge fault extraction unit, a logical value information calculator configured to calculate logical value information of all the signals in the semiconductor integrated circuit by applying the test pattern generated by the test pattern generator to logical connection information of the semiconductor integrated circuit, and a bridge fault remover configured to select an exchange signal candidate for an undetected bridge fault signal corresponding to the test pattern based on the logical value information calculated by the logical value information calculator.08-12-2010
20110208467CALIBRATION STANDARDS AND METHODS OF THEIR FABRICATION AND USE - An embodiment of a calibration standard includes a substrate, a set of conductive structures fabricated on the substrate, and a conductive end structure fabricated on the substrate. The set of conductive structures include an inner conductive structure, a first outer conductive structure positioned to one side of the inner conductive structure, and a second outer conductive structure positioned to an opposite side of the inner conductive structure. The inner and outer conductive structures are aligned in parallel with each other along offset principal axes of the inner and outer conductive structures. The conductive end structure is electrically connected between an end of the first outer conductive structure and an end of the second outer conductive structure, and the conductive end structure is spatially separated from an end of the inner conductive structure at the surface of the substrate.08-25-2011
20080234966Acquiring Test Data From An Electronic Circuit - Methods, systems, and computer program products are disclosed for acquiring test data from an electronic circuit by mounting a probe adjacent to a capture point on an electronic circuit board, capturing by the probe an electronic signal of the electronic circuit, digitizing by the probe the captured signal, and transmitting by the probe the digitized signal from the probe through a data communications connection to a remote device. Acquiring test data from an electronic circuit also includes storing by the probe the digitized signal in the probe. Acquiring test data from an electronic circuit may include processing by the probe the digitized signal. Acquiring test data from an electronic circuit also may include synchronizing acquisition of test data by the probe with acquisition of test data by one or more other probes.09-25-2008
20090119053Serial Interface Device Built-In Self Test - A built-in self test circuit includes a pattern generator, an elastic buffer, a symbol detector, and a comparison unit. A pattern generator generates a first test pattern to test a port under test and then a result pattern is gotten and stored in the elastic buffer. The symbol detector detects if a starting symbol exists in the test result pattern. If it exists, a second test pattern is generated to be compared with the test result pattern. As a result, a reliability of data transmission of the port under test is determined.05-07-2009
20090144012TRANSACTION BASED VERIFICATION OF A SYSTEM ON CHIP ON SYSTEM LEVEL BY TRANSLATING TRANSACTIONS INTO MACHINE CODE - In a transaction-based verification environment for complex semiconductor devices, enhanced verification efficiency may be achieved by providing a transaction to machine code translator and an appropriate interface that enables access of the translated machine code instruction by a CPU under test. In this manner, transaction-based test environments may have a high degree of reusability and may be used for verification on block level and system level.06-04-2009
20120095717SYSTEM AND METHOD FOR TESTING SERIAL PORTS - In a system and method for testing a serial port of a computing device, the serial port electronically connects to a test fixture. Test data is sent to a receive data (RXD) pin by a transmit data (TXD) pin. A test result is received from the serial port by the RXD pin. The TXD pin and the RXD pin work normally if the test data is identical to the test result. When voltages of a request to send (RTS) pin and a data terminal ready (DTR) pin are set at high level, the RTS pin, a data carrier detect (DCD) pin, the DTR pin, a ring indicator (RI) pin, a data send ready (DSR) pin and a clear to send (CTS) pin work normally, upon the condition that status values of the serial port indicate the voltages of the above six pins are at high level.04-19-2012
20120143557METHOD FOR ESTIMATING THE LIFESPAN OF A DEEP-SUB-MICRON INTEGRATED ELECTRONIC CIRCUIT - A large range of commercial VLSI Deep Submicron circuits are used in aeronautics for designs of electronic cards. Due to miniaturization, a continually increasing level of integration and the use of new materials in the foundries, the main failure mechanisms change whilst other ones appear. The lifetimes linked to these failure mechanisms are suspected of being shorter and shorter, so that predicting the lifetime becomes a significant challenge for the reliability of Deep Submicron (DSM) semiconductors. A new approach is proposed here, based on analyzing the technology so as to determine the potential risks to reliability with respect to the specific use of DSM components for avionics applications.06-07-2012
20120143556DIFFERENTIAL SIGNAL OUTPUT DEVICE, TEST METHOD OF DIFFERENTIAL SIGNAL OUTPUT DEVICE, AND TESTER - In a differential signal test mode, the first control circuit causes, in response to the first control signal, the differential signal generating circuit to generate the differential signal depending upon the data signal and output the differential signal. The second control circuit stops the operation of the common mode signal generating circuit in response to the second control signal. In a common mode signal test mode, the first control circuit causes, in response to the first control signal, the differential signal generating circuit to generate a fixed differential signal and output the differential signal. The second control circuit causes, in response to the second control signal, the common mode signal generating circuit to generate the common mode signal depending upon the clock signal and output the common mode signal.06-07-2012
20120078565Methods, Systems, and Products for Reflective Maintenance - Methods, systems, and products maintain reflective maintenance records for a network. Test results are mirrored from different testing applications to a centralized testing database. The test results are associated to circuit identifiers. A work order is received that identifies trouble associated with a customer. A circuit identifier associated with the customer is retrieved and, prior to performing a test of a circuit to resolve the trouble, the centralized testing database is queried for the circuit identifier. A test result associated with the circuit identifier is retrieved and the work order is updated with the test result.03-29-2012
20080262777SYSTEM FOR TESTING PROCESSOR CORES - Systems, methods and program codes are provided for testing multi-core processor chip structures. Individual processor core power supply voltages are provided through controlling individual power supplies for each core, in one aspect to ensure that one or more cores operate at clock rates in compliance with one or more performance specifications. In one example, a first power supply voltage supplied to a first processing core differs from a second core power supply voltage supplied to a second processing core, both cores operating in compliance with a reference clock rate specification. Core power supply voltages may be selected from ordered discrete supply voltages derived by progressively raising or lowering a first supply voltage, optionally wherein the selected supply voltage also enables the core to operate within another performance specification.10-23-2008
20080234965TEST APPARATUS AND ELECTRONIC DEVICE - A test apparatus for testing a device under test is provided. The test apparatus includes: a timing data output section for outputting timing data to define at least one of a timing of modifying a test signal provided to the device under test and a timing of acquiring an output signal outputted by the device under test; a variable delay circuit for delaying a reference clock pulse of the test apparatus by a delay amount corresponding to designated delay data so as to generate a timing signal having a transition point corresponding to the at least one timing; and a range modification section for modifying the modification amount of the delay data when the timing data are changed by one unit in response to a change of a setting range within which the at least one timing is set.09-25-2008
20090254296CIRCUIT TESTING APPARATUS - A circuit testing apparatus for testing a device under test is disclosed. The device under test comprises a first output end and second output end for generating a first output signal and a second output signal, respectively. The circuit testing apparatus determines a test result for the device under test according to the first output signal and the second output signal.10-08-2009
20120035877SEMICONDUCTOR DEVICE HAVING TEST FUNCTION AND TEST METHOD USING THE SAME - A semiconductor device having a test function includes a program counter for storing a breaking address in a storage unit in response to control signals, increasing a count address in response to the control signals, and storing the increased count address in the storage unit; a controller for stopping the increase of the count address when the count address is identical to the breaking address and outputting a pump holding signal; an oscillator for generating a clock signal in response to an enable signal and maintaining a current cycle of the clock signal in response to the pump holding signal; and a pump unit for generating an output voltage in response to the clock signal.02-09-2012
20100235134METHODS AND SYSTEMS FOR GENERATING AN INSPECTION PROCESS FOR A WAFER - Methods and systems for generating an inspection process for a wafer are provided. One computer-implemented method includes separately determining a value of a local attribute for different locations within a design for a wafer based on a defect that can cause at least one type of fault mechanism at the different locations. The method also includes determining a sensitivity with which defects will be reported for different locations on the wafer corresponding to the different locations within the design based on the value of the local attribute. In addition, the method includes generating an inspection process for the wafer based on the determined sensitivity. Groups may be generated based on the value of the local attribute thereby assigning pixels that will have at least similar noise statistics to the same group, which can be important for defect detection algorithms. Better segmentation may lead to better noise statistics estimation.09-16-2010
20090276178WARRANTY MONITORING AND ENFORCEMENT FOR INTEGRATED CIRCUIT AND RELATED DESIGN STRUCTURE - An integrated circuit (IC) including a warranty and enforcement system, and a related design structure and HDL design structure are disclosed. In one embodiment, an IC includes a parameter obtainer for obtaining a value of a parameter of the IC; a warranty data storage system for storing warranty limit data regarding the IC; a comparator for determining whether a warranty limit has been exceeded by comparing the value of the parameter to a corresponding warranty limit; and an action taker for taking a prescribed action in response to the warranty limit being exceeded.11-05-2009
20090319218APPARATUS, METHOD AND COMPUTER-READABLE MEDIUM FOR TESTING A PANEL OF INTERFEROMETRIC MODULATORS - In some embodiments, each interferometric modulator has a stiction threshold voltage. If a voltage above the stiction threshold voltage is applied to the interferometric modulator, the interferometric modulator enters a stiction state permanently, i.e., becomes “stuck,” and the interferometric modulator becomes inoperable. Disclosed are apparatuses, methods and computer-readable media for testing a panel of interferometric modulators. A ramped voltage waveform is applied to a plurality of interferometric modulators of the panel. In response to applying the ramped voltage, the stiction threshold voltage is identified. At or above this voltage, the number of stuck interferometric modulators in the panel reaches or exceeds a first threshold number, for example, 50% of the total number of the interferometric modulators constituting the panel. The embodiments can be used to establish stiction benchmark for panel manufacturing processes, to collect data for generating statistical distribution, etc.12-24-2009
20090319219SIGNAL SELECTION APPARATUS AND SYSTEM, AND CIRCUIT EMULATOR AND METHOD AND PROGRAM - Disclosed is a system in which in order to obtain the operation parameter of a circuit based on an implementable area indicating a circuit scale that can be implemented on a circuit implementation device, circuit area information, and operation parameter measuring circuit area information, an observation signal number determining means determines observation signal information on a circuit that obtains the operation parameter of the circuit. The number of the extracted signals is determined in view of the area that can be implemented on a digital LSI or an emulator and the area of the circuit to be implemented (refer to FIG. 12-24-2009
20080312863SYSTEM AND METHOD FOR IMPLEMENTING A PROGRAMMABLE DMA MASTER WITH DATE CHECKING UTILIZING A DRONE SYSTEM CONTROLLER - A method, system, and computer-usable medium for implementing a programmable DMA master with data checking utilizing a drone system controller. According to an embodiment of the present invention, a drone processor generates a collection of random data and stores a first and second copy of the collection of random data in a first and second memory location in a drone memory. The drone processor writes a third copy of the collection of random data in a processor memory. When the drone processor retrieves the third copy from the processor memory, the drone processor writes the third copy in the second memory location in the drone memory. When the drone processor compares the first copy with the third copy, the results of the compare is written in a status location within the drone processor.12-18-2008
20100312516PROTOCOL AWARE DIGITAL CHANNEL APPARATUS - In one embodiment, provided is a protocol specific circuit for simulating a functional operational environment into which a device-under-test is placed for functional testing. The protocol specific circuit includes a protocol aware circuit constructed to receive a non-deterministic signal communicated by a device-under-test and to control a transfer of the test stimulus signal to the device-under-test in response to the a non-deterministic signal.12-09-2010
20100318313MEASUREMENT METHODOLOGY AND ARRAY STRUCTURE FOR STATISTICAL STRESS AND TEST OF RELIABILTY STRUCTURES - System and method for obtaining statistics in a fast and simplified manner at the wafer level while using wafer-level test equipment. The system and method performs a parallel stress of all of the DUTs on a given chip to keep the stress time short, and then allows each DUT on that chip to be tested individually while keeping the other DUTs on that chip under stress to avoid any relaxation. In one application, the obtained statistics enable analysis of Negative Temperature Bias Instability (NTBI) phenomena of transistor devices. Although obtaining statistics may be more crucial for NBTI because of its known behavior as the device narrows, the structure and methodology, with minor appropriate adjustments, could be used for stressing multiple DUTs for many technology reliability mechanisms.12-16-2010
20130138380Methods of Combinatorial Processing for Screening Multiple Samples on a Semiconductor Substrate - In embodiments of the current invention, methods of combinatorial processing and a test chip for use in these methods are described. These methods and test chips enable the efficient development of materials, processes, and process sequence integration schemes for semiconductor manufacturing processes. In general, the methods simplify the processing sequence of forming devices or partially formed devices on a test chip such that the devices can be tested immediately after formation. The immediate testing allows for the high throughput testing of varied materials, processes, or process sequences on the test chip. The test chip has multiple site isolated regions where each of the regions is varied from one another and the test chip is designed to enable high throughput testing of the different regions.05-30-2013
20110035177DISTRIBUTED COMPUTING - On a typical motherboard the processor and memory are separated by a printed circuit data bus that traverses the motherboard. Throughput, or data transfer rate, on the data bus is much lower than the rate at which a modern processor can operate. The difference between the data bus throughput and the processor speed significantly limits the effective processing speed of the computer when the processor is required to process large amounts of data stored in the memory. The processor is forced to wait for data to be transferred to or from the memory, leaving the processor under-utilized. The delays are compounded in a distributed computing system including a number of computers operating in parallel. The present disclosure describes systems, method and apparatus that tend to alleviate delays so that memory access bottlenecks are not compounded within distributed computing systems.02-10-2011
20110035176 APPARATUS FOR AUTOMATICALLY TESTING INTEGRATED CMOS MAGNETORESISTIVE BIOCHIPS - An apparatus for automatically testing CMOS magnetoresistive biochips is disclosed. The apparatus includes: means for directly or indirectly applying physical pressure to the fluid pumping chamber in a cartridge; a liquid injector for injecting liquid into the reaction chamber in the cartridge through an inlet or inlets in fluid connection to said reaction chamber; a CMOS magnetoresistive biochip located in the reaction chamber in the cartridge; means for applying a magnetic field to said CMOS magnetoresistive biochip in the cartridge; an electronic module for communicating with and supplying power as well as control signals to said biochip; a microprocessor to control and coordinate the aforementioned components; and a user interface for information processing. The apparatus provided by the present invention reduces the complexity of operation and enhances the detection sensitivity to a great extent.02-10-2011
20100332177TEST ACCESS CONTROL APPARATUS AND METHOD THEREOF - A test access control apparatus includes test access mechanism (TAM) buses and an extended IEEE 1149.1 Test Access Port (TAP) Controller. The TAM buses support memory built-in-self-test (BIST) circuit for the memory known-good-die (KGD) test, scan chains for the logic KGD test; and through-silicon-via (TSV) chains that are configured to conduct the TSV test that verifies any defect in vertical interconnects between any two chip layers of the stacked chip device. The TAP Controller is coupled to the TAM buses and is configured to control the memory KGD test, the logic KGD test and the TSV test between two chip layers. A cost-effective connection or configuration of test access control apparatus in 3D-IC is also present. In accordance with an embodiment of the present invention, a test access control method includes a yield-concerned test methodology for 3D-IC, and an integrated flow of test access control apparatus supporting heterogeneous test protocols of SOC12-30-2010
20110040516TEST APPARATUS AND TEST METHOD FOR UNIVERSAL SERIAL BUS INTERFACE - A test apparatus for testing USB interfaces of an electronic device. The test apparatus includes a number of USB interfaces connected to the USB interfaces of the electronic device via cables respectively, to communicate with the electronic device. A memory stores a special file, to note phrases generated during test. A single-chip is connected to the number of USB interfaces, a power switch, and the memory, and stores a preset phrase. When the power switch is turned on, the single-chip writes a ready phrase in the special file, when one of the USB interfaces of the electronic device passes test, the single-chip reads a test phrase from the special file and writes a test finish phrase in the special file and controls the test apparatus to test a next USB interface of the USB interfaces of the electronic device.02-17-2011
20090024346IMPORTATION OF VIRTUAL SIGNALS INTO ELECTRONIC TEST EQUIPMENT TO FACILITATE TESTING OF AN ELECTRONIC COMPONENT - Electronic component validation testing is facilitated by a method, system and program product which allows the importation of virtual signals derived from simulation verification testing of the electronic component design into electronic test equipment employed during validation testing of the actual electronic component. The method includes: storing simulation data resulting from simulation testing of an electronic component's design; employing electronic test equipment to perform real-time testing of the actual electronic component and obtain real-time test signals therefor; automatically correlating the stored simulation data with the actual real-time test signals; and performing at least one of overlaying and/or displaying the correlated simulation data as virtual signals with the real-time test signals; and employing a trigger event automatically ascertained from the stored simulation data and triggering the electronic test equipment based thereon, thereby automatically controlling real-time testing of the electronic component via the stored simulation data.01-22-2009
20090063086APPARATUS FOR TESTING SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD FOR TESTING SEMICONDUCTOR INTEGRATED CIRCUIT - An apparatus for testing a semiconductor integrated circuit includes an input part that inputs circuit description data that describes a circuit structure of the semiconductor integrated circuit, a clock domain of the semiconductor integrated circuit, and a first test vector to be used for testing a normal operation of the semiconductor integrated circuit, and a simulator that performs a simulation on the semiconductor integrated circuit with the use of a test vector. The simulator includes an asynchronous transfer point extraction unit that extracts an asynchronous transfer point in the semiconductor integrated circuit in accordance with the circuit description data and the clock domain that are input through the input part, a simulation unit that calculates a logic circuit output of the semiconductor integrated circuit by performing a simulation in accordance with the circuit description data and the first test vector that are input through the input part, and a second test vector generation unit that generates a second test vector by changing a signal of an asynchronous transfer point of the logic circuit output calculated by the simulation unit in accordance with the asynchronous transfer point extracted by the asynchronous transfer point extraction unit.03-05-2009
20110087452TEST DEVICE - A test device for testing a system, which has first interface circuit, second interface circuit, and a power switch, comprises a power supply, status detector, and a controller. The power supply includes a supplying unit and a switch controller. The supplying unit provides a test power signal according to a wall wart signal. The switch controller enables the power switch to power the system with the test power signal in response to a control signal. The system boots according to operation system data provided via first interface circuit in response to the test power signal. The status detector generates a status detection signal indicating whether the system boots up successfully in response to an operation signal on the second interface circuit. The controller provides the control signal and processes the status detection signal.04-14-2011
20110246120EQUIVALENT CIRCUIT OF INDUCTANCE ELEMENT, METHOD OF ANALYZING CIRCUIT CONSTANT, CIRCUIT CONSTANT ANALYSIS PROGRAM, DEVICE FOR ANALYZING CIRCUIT CONSTANT, CIRCUIT SIMULATOR - The present invention provides an equivalent circuit, circuit constant analysis method, circuit constant analysis program, circuit constant analysis device, and circuit simulator for an inductance element that are capable of good approximation of characteristics even in the band region greater than or equal to the resonance frequency. To a parallel circuit of an inductance Ls, a capacitance Cp, and a resistance Rp, added are another capacitance Cr, which is connected in series to the resistance Rp, another inductance Lr, which is connected in parallel to the resistance Rp, another resistance Rs, which is connected in series to the parallel circuit, a first closed circuit, which is magnetically coupled with the inductance Ls with a coupling coefficient k10-06-2011
20110246119PROCESS FOR TESTING THE RESISTANCE OF AN INTEGRATED CIRCUIT TO A SIDE CHANNEL ANALYSIS - A process for testing an integrated circuit includes collecting a set of points of a physical property while the integrated circuit is executing a multiplication, dividing the set of points into a plurality subsets of lateral points, calculating an estimation of the value of the physical property for each subset, and applying to the subset of lateral points a step of horizontal transversal statistical processing by using the estimations of the value of the physical property, to verify a hypothesis about the variables manipulated by the integrated circuit.10-06-2011
20100057394COMPONENTS AND CONFIGURATIONS FOR TEST AND VALUATION OF INTEGRATED OPTICAL BUSSES - An apparatus and method is provided for the testing of an optical bus, that method comprising: loading transmission test data and address information for at least one receiving cell via an electronic bus in a first register; setting a clock rate for the optical bus; employing the optical bus to transmit the test data from the first register to the at least one receiving cell; reading out received test data from the receiving cell via the electronic bus; correlating the received test data from the first register with the transmission test data; analyzing errors in the received data and handling of the received data by the bus.03-04-2010
20110077893Delay Test Apparatus, Delay Test Method and Delay Test Program - A delay test apparatus for a semiconductor integrated circuit includes (03-31-2011
20120136610Method and Apparatus for Providing Leak Detection in Data Monitoring and Management Systems - Method and apparatus for providing a leak detection circuit for a data monitoring and management system using the guard trace of a glucose sensor by applying a leak detection test signal to determine whether a leakage current is present is provided. The leak detection circuit may include an interface circuit, such as a capacitor, coupled to the guard trace to detect the leakage current when the leak detection test signal is applied to the guard trace, such that the user or patient using the data monitoring and management system, such as glucose monitoring systems, is notified of a failed sensor and prompted to replace the sensor.05-31-2012
20120203494METHOD FOR MEASURING A SEMICONDUCTOR STRUCTURE, WHICH IS A SOLAR CELL OR A PRECURSOR OF A SOLAR CELL - The invention relates to a method for measuring a semiconductor structure, which has an emitter and a base, and which is a solar cell or a precursor of a solar cell, comprising the following steps: A) Generating luminescence radiation in the semiconductor structure, and spatially resolved measuring of the luminescence radiation emitted by the semiconductor structure, wherein a first measurement is conducted under a first measurement condition a, and depending on the measurement data that are obtained at least from the first measurement, a first spatially resolved, voltage-calibrated image V08-09-2012
20100280784Method for monitoring the quality of a control circuit in a power plant - A method of monitoring quality of a control circuit in a power plant is provided. The quality of the control circuit is continuously assessed by determining characteristic quantities describing the quality by applying a plurality of testing methods suitable for describing dynamic properties of the control circuit to current operating data originating from the instrumentation and control equipment of the power plant, and by evaluating the characteristic quantities. Further, a system and a computer readable medium are provided.11-04-2010
20090240456Circuits and Methods for Calibrating a Delay Element - A controllable delay element is coupled in parallel with a calibration circuit. The calibration circuit receives a periodic reference signal and generates a series of sample voltages responsive to a time-varying analog voltage, the periodic reference signal, and the delayed periodic signal at the output of the controllable delay element. The calibration circuit distributes the series of sampled voltages for determining the components of a first vector. The first vector components are used to calculate the phase that results from a control signal applied to the controllable delay element. After the control signal is modified, a second vector is used to calculate the phase that results from the control signal. The delay can be determined by the product of the period of the reference signal and the difference in phase.09-24-2009
20080243419Photon transfer curve test time reduction - An improved method for photon transfer curve (PTC) testing in an image sensor is described. A cost and time savings is achieved by reducing the number of frames necessary for measurements to two that are generated by illuminating a first plurality of pixel rows at a first intensity level m10-02-2008
20090037131METHOD AND CONFIGURATION FOR CONNECTING TEST STRUCTURES OR LINE ARRAYS FOR MONITORING INTEGRATED CIRCUIT MANUFACTURING - A test chip comprises at least one level having an array of regions. Each region is capable of including at least one test structure. At least some of the regions include respective test structures. The level has a plurality of driver lines that provide input signals to the test structures. The level has a plurality of receiver lines that receive output signals from the test structures. The level has a plurality of devices for controlling current flow. Each test structure is connected to at least one of the driver lines with a first one of the devices in between. Each test structure is connected to at least one of the receiver lines with a second one of the devices in between, so that each of the test structures can be individually addressed for testing using the driver lines and receiver lines.02-05-2009
20110257923WiFi Positioning Bench Test Method and Instrument - The present invention relates to simulation on a lab workbench of conditions that would be encountered by a mobile device during a so-called drive test, which involves transporting the mobile device along a course so that it encounters fading and changing wireless access points used normally to connect the mobile device to a wireless network but in this case used to locate the device. The instrument and method also support parametric testing of transceivers used for WiFi positioning and, optionally, GNSS positioning by the same mobile device used for WiFi positioning.10-20-2011
20080208507METHOD AND APPARATUS FOR DIAGNOSING BROKEN SCAN CHAIN BASED ON LEAKAGE LIGHT EMISSION - A mechanism for diagnosing broken scan chains based on leakage light emission is provided. An image capture mechanism detects light emission from leakage current in complementary metal oxide semiconductor (CMOS) devices. The diagnosis mechanism identifies devices with unexpected light emission. An unexpected amount of light emission may indicate that a transistor is turned off when it should be turned on or vice versa. All possible inputs may be tested to determine whether a problem exists with transistors in latches or with transistors in clock buffers. Broken points in the scan chain may then be determined based on the locations of unexpected light emission.08-28-2008
20120150473CLOCK EDGE GROUPING FOR AT-SPEED TEST - A method of grouping clock domains includes: separating a plurality of test clocks into a plurality of domain groups by adding to each respective one of the plurality of domain groups those test clocks that originate from a same clock source and have a unique clock divider ratio; sorting the domain groups in decreasing order of size; and creating a plurality of parts by adding the respective one of the plurality of domain groups to a first one of the plurality of parts in which already present test clocks have a different clock source, and creating a new part and adding the respective one of the plurality of domain groups to the new part when test clocks present in the respective one of the plurality of domain groups originate from a respective same clock source and have a different clock divider ratio as test clocks present in all previously-created parts.06-14-2012
20090254297Arrangement and Method for Determining an Electrical Feature - Arrangement to determine at least one electrical feature of an electrical device includes a signal injection unit configured to inject first and second test signals into electric, a signal conversion unit configured to measure electrical qualities in the electrical circuits resulting from the test signals, and a processing device including at least two input channels configured to receive the measured electrical quantities and to determine the electrical feature based on the measured electrical quantities, a mixing unit configured to add the measurements of the first electrical quantity from the test signals and based thereon generate a first mixed signal, to add the measurements of the second electrical quantity from the test signals and based thereon generate a second mixed signal, and to supply the first and second mixed signals to first and second input channels.10-08-2009
20110010126HIGH VOLTAGE INTERLOCK STRATEGY - A High Voltage Interlock Strategy (HVIS) uses feedback current to detect cable connectivity status for a high-voltage cable configured to connect a power conversion circuit with a remote permanent magnet synchronous machine (PMSM). One or more feedback factors are calculated based on detected feedback current. Various algorithms for calculating a feedback factor, and for determining connectivity status based on calculated feedback factors, can be practiced, according to the PMSM operational mode. Fault detection action can be performed in response to detecting a cable disconnect. The HVIS can be implemented by software, making it a safe, economical solution for cable connectivity detection.01-13-2011
20110264396ELECTRICAL CIRCUIT WITH PHYSICAL LAYER DIAGNOSTICS SYSTEM - An electrical circuit has a power supply, one or more devices and a diagnostics system. The diagnostics system includes a monitoring means adapted to monitor physical layer characteristics of the electrical circuit, a database containing circuit design data for the electrical circuit, and comparator means adapted to diagnose the status of the monitored physical layer characteristics of the electrical circuit by comparing them with the circuit design data.10-27-2011
20110137602INSERTION OF FAULTS IN LOGIC MODEL USED IN SIMULATION - A method of selecting fault candidates based on the physical layout of an Integrated Circuit (IC) layout, that includes, identifying failing observation points in an IC layout, determining the failing observation points proximity geometry in the IC circuit layout, determining if a proximity criteria for the failing observation points is met, and identifying faults associated with the failing observation points that meet the proximity criteria; and including the identified faults in a fault candidate set.06-09-2011
20100179784TEST PATTERN COMPRESSION - A method for test pattern compression generates a first test pattern comprising a plurality of bits. The method identifies bits comprising a don't-care bit value in the first test pattern and replaces the identified bit values with random bit values, to generate a second test pattern. The method determines a fault coverage level of the second test pattern. In the event the determined fault coverage level of the second test pattern exceeds a predetermined individual test pattern fault coverage level, for at least one bit position in the second test pattern corresponding to a replaced identified bit value and detecting at least one fault, the method exchanges the don't care value in the bit position in the first test pattern with the bit value in the corresponding bit position in the second test pattern. The method merges subsequent test patterns that increase fault coverage with the second test pattern.07-15-2010
20110137604REAL-TIME ADAPTIVE HYBRID BiST SOLUTION FOR LOW-COST AND LOW-RESOURCE ATE PRODUCTION TESTING OF ANALOG-TO-DIGITAL CONVERTERS - An integrated circuit configured to perform hybrid built in self test (BiST) of analog-to-digital converters (ADCs) is described. The integrated circuit includes an ADC. The integrated circuit also includes a BiST controller that controls the hybrid BiST. The integrated circuit further includes a ramp generator that provides a voltage ramp to the ADC. The integrated circuit also includes a first multiplexer that switches an input for the ADC between the voltage ramp and a voltage reference signal. The integrated circuit further includes feedback circuitry for the ramp generator that maintains a constant ramp slope for the ramp generator. The integrated circuit also includes an interval counter that provides a timing reference.06-09-2011
20110137603Enforcing Worst-Case Behavior During Transmit Channel Analysis - Techniques for analyzing the signal integrity of a channel by enforcing a worst-case behavior during the analysis are presented. Initially a channels response to an input bit sequence, followed by a test bit sequence is simulated. Subsequently, a pulse response is extracted from the simulated channel response. A worst-case pattern bit sequence is then derived from the extracted pulse sequence and the channels response to the worst-case pattern bit sequence is simulated. In further implementations, the channels response to the worst-case pattern bit sequence is displayed for a user.06-09-2011
20090192753APPARATUS AND METHOD FOR TESTING ELECTRONIC SYSTEMS - The technology and economics of system testing have evolved to the point where a radical change in methodology is needed for effective functional testing of systems at clock rates of 1 GHz and higher. Rather than providing a test fixture to interface between the system under test and an external tester, it is preferable to provide critical testing functions within each electronic system in the form of one or more special-purpose test chips. An architecture is proposed that supports full-speed testing with improved noise margins, and also efficient methods for learning correct system behavior and generating the test vectors. The test program is preferably written using the same programming language as used for the system application.07-30-2009
20100153052Tester, Method for Testing a Device Under Test and Computer Program - A tester for testing a device under test has a first channel unit and a second channel unit. The first channel unit has a corresponding first pin connection for a signal from a device under test, a corresponding first test processor adapted to process, at least partially, data obtained from the first pin connection, and a corresponding first memory coupled with the first test processor and adapted to store data provided by the first test processor. The first channel unit is adapted to transfer at least a part of the data obtained from the first pin connection to the second channel unit as transfer data. The second channel unit has a corresponding second test processor adapted to process, at least partly, the transfer data from the first channel unit.06-17-2010
20090292498RESISTANCE TESTING DEVICE - A resistance testing device detects resistances between testing points of an electronic element. The resistance testing device includes controls accepting input of data to the resistance testing device, a relay module, a multimeter, testing probes electrically connected to the relay module, a testing platform including a base and a probe mounting board, a driving assembly mounted on the base and moving the probe mounting board relative to the electronic device, a display, and a central processing assembly mounted within the base. The relay module controls the testing probes and implements the multimeter to detect resistances between the testing points. The base seats the electronic element, the probe mounting board fixes the testing probes, and the probe mounting board is adjustably mounted above the base. The central processing assembly includes a central processing unit. The central processing unit is respectively and electronically connected to the controls, driving assembly, display and the relay module. The central processing unit provides input of data and implements the driving assembly, display, relay module and the multimeter, and analyzes testing results, and the display shows input data and testing results.11-26-2009
20110196641Semiconductor device and diagnostic method thereof - A semiconductor device includes a test target circuit subjected to self-diagnosis, a PLL circuit that outputs a clock for the self-diagnosis to the test target circuit, a diagnostic register that stores a clock frequency corresponding to an operation speed limit of the test target circuit, and a control circuit that sets a frequency of the clock output from the clock circuit based on the clock frequency stored in the diagnostic register when executing the self-diagnosis.08-11-2011
20100030508PIN ELECTRONICS CIRCUIT, SEMICONDUCTOR DEVICE TEST EQUIPMENT AND SYSTEM - A main driver and a sub-driver control circuit are provided respectively to receive a test pattern signal for testing a device. The main driver drives the test pattern signal to output a first driven signal. The sub-driver control circuit modifies the test pattern signal to output a modified pattern signal. The modified pattern signal is provided to a sub-driver. The first sub-driver drives the modified pattern signal to output a second driven signal. The first and the second driven signals are combined. The combined signal is provided to a terminal of the device as a test signal.02-04-2010
20100204948SYSTEM LEVEL TESTING FOR SUBSTATION AUTOMATION SYSTEMS - Protection, measurement and control IEDs in a substation compute if switches they control may be operated safely, according to interlocking rules or physical principles as well as the dynamic topology of the substation. The IEDs have access to the substation electrical topology, to real-time information generated by other IEDs, and to the rules for interlocking. A standardized Substation Configuration Description (SCD) of the substation for which a Substation Automation system is intended, and a standardized description of the implemented device functions or capabilities of an individual IED are utilized. The substation topology is available from SCD file, real time information about the position of switches and line voltage/current can be obtained via an appropriate protocol, and the interlocking rules are available in script form. These features apply both to simulated and real devices, and increase system testing possibilities by supporting an efficient configuration of a simulation.08-12-2010
20120065919BUILT-IN SELF-TEST CIRCUIT-BASED RADIATION SENSOR, RADIATION SENSING METHOD AND INTEGRATED CIRCUIT INCORPORATING THE SAME - A radiation sensor for an integrated circuit (IC), a radiation sensing method and an IC incorporating the sensor or the method. In one embodiment, the radiation sensor includes: (1) a built-in self-test (BIST) controller configured to provide BIST with respect to main IC circuitry of the IC and (2) a radiation sensor controller coupled to the main IC circuitry and the BIST controller and configured to identify temporarily inactive portions of the main IC circuitry and cause the BIST controller to perform at least one BIST with respect to at least one of the portions, the at least one of the portions acting as a radiation target.03-15-2012
20090063085PMU TESTING VIA A PE STAGE - An apparatus for use in testing a device includes a parametric measurement unit to measure a first signal from the device, and pin electronics to provide a second signal to the device. The pin electronics includes circuitry along a path to the device. The parametric measurement unit is electrically connected to the device via the circuitry to receive the first signal via the circuitry.03-05-2009
20110166818LOW POWER SCAN TESTING TECHNIQUES AND APPARATUS - Disclosed below are representative embodiments of methods, apparatus, and systems used to reduce power consumption during integrated circuit testing. Embodiments of the disclosed technology can be used to provide a low power test scheme and can be integrated with a variety of compression hardware architectures (e.g., an embedded deterministic test (“EDT”) architecture). Among the disclosed embodiments are integrated circuits having programmable test stimuli selectors, programmable scan enable circuits, programmable clock enable circuits, programmable shift enable circuits, and/or programmable reset enable circuits. Exemplary test pattern generation methods that can be used to generate test patterns for use with any of the disclosed embodiments are also disclosed.07-07-2011
20120158345CURRENT BALANCE TESTING SYSTEM - A current balance testing system is configured for measuring current flowing in a main board, the main board comprises a load, a power source supplying power to the loads, and a number of inductors connected between the power source and the loads. The current balance testing system includes a data acquiring device and a data processing device. The data acquiring device includes a plurality of input terminals and an output terminal, each input terminal correspondingly is connected to one inductor and configured for measuring a voltage drop across the inductor. The data processing device is connected to the output terminal and stores resistances of the inductors in the data processing device. The data processing device uses the voltage drops and the resistances of the inductors to calculate the current flowing through the inductors to determine whether or not the current flowing between the power source and the load are balanced.06-21-2012
20110106481SYSTEM AND METHOD FOR CHECKING GROUND VIAS OF A CONTROLLER CHIP OF A PRINTED CIRCUIT BOARD - A system and method for checking a ground via of control chips of a printed circuit board (PCB) provides a graphical user interface (GUI) displaying a layout of the PCB. The control chip has a plurality of ground pins. The computer searches for signal path routing of each ground pin and ground vias along each signal path routing of each ground pin. If there are any ground vias having the same absolute coordinates, the computer determines that the ground vias are shared by more than one ground pin.05-05-2011
20120123726TEST APPARATUS, TEST METHOD, AND STORAGE MEDIUM - The time required for timing training is reduced by a test apparatus having an expected value comparing section judging whether a value resulting from sampling input/output data using a strobe signal matches a pre-set expected value a pre-set number of times, and a test section adjusting a phase of a test signal to be supplied to the device under test based on the first relative phase changing from a fail state to a pass state and the second relative phase changing from the pass state to the fail state, and testing the device under test using the test signal whose phase has been adjusted, where the fail state being in which at least one of the pre-set number of judgment results indicates mismatch, and the pass state being in which all the pre-set number of judgment results indicate match.05-17-2012
20120123725PERFORMING RELIABILITY ANALYSIS OF SIGNAL WIRES - A computer-implemented system, method, and storage device simulate a periodic voltage waveform in a network model of the integrated circuit design. The method then determines resultant current values in each segment of nets of the integrated circuit design resulting from the periodic voltage waveform and performs a Fourier transform of the periodic voltage waveform to generate a frequency domain representation of the periodic voltage waveform. The frequency domain representation comprises multiple Fourier terms, each of the Fourier terms is a frequency that is a multiple of the base frequency. Next, the method performs an AC analysis of the resultant voltage at each frequency of the multiple Fourier terms. The AC analysis provides an electrical current value for each of the frequencies of the Fourier terms for each of the nets. This allows the method to compute a root mean square current through each of the nets based on the AC analysis. Then, the method determines whether the root mean square current for any of the segments of the nets exceeds a current limit, and reports any segment of the nets for which the root mean square current exceeds the current limit.05-17-2012
20120123724Detecting an Unstable Input to an IC - Additional circuitry is included in an input cell design structure for an integrated circuit to detect and report transitions on an input that was expected to be stable, and to store that event for later analysis. Two or more modified input cells may have their error indications daisy-chained together to minimize additional routing. The storage elements may be included in a scan chain to allow for isolation of which input had the unexpected transition.05-17-2012
20120166130METHOD FOR EVALUATING FAILURE RATE - A method for evaluating failure rate, which is applied to a plurality of semiconductor chips with error checking and correcting function includes the following steps. A first read-write test operation is applied to the semiconductor chips, thereby obtaining a plurality of first failure bit counting values. The error checking and correcting function of each of the semiconductor chips is off. An aging test is applied to the semiconductor chips. A second read-write test operation as the first read-write test operation is applied to the semiconductor chips, thereby obtaining a plurality of second failure bit counting values. The number of the semiconductor chips, the first failure bit counting values, the second failure bit counting values and an error checking and correcting coefficient are calculated to obtain a failure rate of the semiconductor chips.06-28-2012
20120130669VARIATION AWARE TESTING OF SMALL RANDOM DELAY DEFECTS - In one embodiment, the invention is a method and apparatus for variation aware testing of small random delay defects. One embodiment of a method for selecting a set of paths with which to test an integrated circuit chip includes computing a metric that considers the joint impact of parametric process variation delay defects and single random delay defects and selecting the set of paths such that the value of the metric is at least as great as a target value.05-24-2012
20120136609BINARY DEFINITION FILES - A computer implemented system for testing electronic equipment where files are provided to aid in the conversion of device generic messages into device specific messages and conversion of device specific messages into device generic messages.05-31-2012
20100299096DELAY FAULT TESTING COMPUTER PRODUCT, APPARATUS, AND METHOD - A computer-readable medium stores therein a program that causes a computer to execute acquiring for each chip, first delay values of paths in chips manufactured using circuit information concerning a circuit-under-test; building a function model representing a delay value of a path, based on the first delay values for the path and the circuit information; calculating a second delay value of a path included in and having the same configuration in each chip, using a built function model and the circuit information; comparing for each chip, a given calculated second delay value and the first delay value of a given path having a configuration identical to that of the path for which the given second delay value has been calculated; determining based on a comparison result, the given path to be a path that includes a delay error occurring irregularly according to chip; and outputting a determination result.11-25-2010
20100274517Chip Handler with a Buffer Traveling between Roaming Areas for Two Non-Colliding Robotic Arms - Two robotic arms roam in separate, non-overlapping areas of a test station, avoiding collisions. A traveling buffer moves along x-tracks between a front position and a back position. In the front position, a first robotic arm loads IC chips from an input tray or stacker into buffer cavities in the traveling buffer. The traveling buffer then moves along the x-tracks to the back position, where a second robotic arm moves chips from the traveling buffer to test boards for testing. After testing, the second robotic arm moves chips to a second traveling buffer, which then moves along tracks to a front position for unloading by the first robotic arm. Two traveling buffers may move on the same tracks in a loop. The buffer cavities in the traveling buffer move on internal tracks to expand and contract spacing and pitch between the front and back positions to match test-board pitch.10-28-2010
20120179412Circuits and Methods for Characterizing Random Variations in Device Characteristics in Semiconductor Integrated Circuits - Circuits for measuring and characterizing random variations in device characteristics of integrated circuit devices.07-12-2012
20120179409VOLTAGE-DRIVEN INTELLIGENT CHARACTERIZATION BENCH FOR SEMICONDUCTOR - A system for testing a plurality of transistors on a wafer having a storage device or personal computer connected via a bus to a plurality of drivers. Each of the voltage drivers having a microcontroller adapted to receive test parameters and provide test data from a plurality of voltage drivers. By utilizing a bus structure, the personal computer can look on one bus for flags indicating test data is available from a driver and receive the data. In addition a bus may be used to provide test parameters to the drivers. In this manner, multiple drivers may be run at the same time incorporating multiple tests. When data is available it is transferred to the personal computer, for providing test parameters to a plurality of drivers, and connected via a second bus for receiving test results from the plurality of drivers.07-12-2012
20120179410VOLTAGE DRIVER FOR A VOLTAGE-DRIVEN INTELLIGENT CHARACTERIZATION BENCH FOR SEMICONDUCTOR - A voltage driver is provided having an input to receive test parameters from a microcontroller. The voltage driver having a first amplifier to provide an input to a first switch, based on the test parameters. The first switch having an output to a first connector such as a probe adapted to be connected to a device under test or DUT. A second switch having an input from a second connector to the device under test, the output of the second switch connected to a ground. A third switch has an input connected to the second switch input, the third switch having an output connected to the first connector to the device under test, wherein the first switch is open, and the second and third switch are closed to set the first connector and the second connector to ground. A buffer is provided such that the microcontroller is sets the test parameters in the first voltage driver, the first voltage driver is adapted to provide test data to the buffer. The device is set such that all of the inputs may be set to ground to minimize the possibility of electrostatic discharge building up on the probes and damaging the DUT.07-12-2012
20100010768IDENTIFYING MANUFACTURING DISTURBANCES USING PRELIMINARY ELECTRICAL TEST DATA - A method includes receiving measured values for a plurality of electrical test parameters associated with integrated circuit devices on at least one wafer measured prior to completion of the wafer. Values of the electrical test parameters are predicted. The measured values are compared to the predicted values to generate residual values associated with the electrical test parameters. At least one performance metric associated with the devices is generated based on the residual values.01-14-2010
20120221282MOTHERBOARD TESTING APPARATUS - A motherboard testing apparatus for testing a motherboard by subjecting it to sequential power-on and power-off modes includes a control module, a switch module and a display module. The control module stores power-on and power-off number of times and outputs control signals accordingly. The switch module provides a first voltage to the motherboard according to the control signals. The switch module includes a photocoupler and a delay. The photocoupler includes an LED and a phototransistor. The delay includes a winding element and a switch element. The display module displays the time periods and the number of times the motherboard abnormally power-on and power-off. The LED receives the control signals. The phototransistor turns on when the LED emits light. The winding element is powered up and closes the switch element. The switch element outputs the first voltage.08-30-2012
20120259574DESIGNED-BASED YIELD MANAGEMENT SYSTEM - An integrated-circuit yield improvement system includes a global signature analysis/grouping module configured to receive an integrated circuit (IC) design and identify areas in the IC design that include potential defect signatures based on the defect signatures stored in the defect signature library. The global signature analysis/grouping module can produce a global signature map indicating these areas and their associated potential defect signatures in the IC design. A local signature analysis/grouping module can identify and group local defect signatures in the IC design with the process monitoring and yield data as input, to output grouped local signatures. An intelligent learning engine can analyze the global signature map and the grouped local signatures and update some of the defect signatures in the defect signature library. A feedback loop is formed to update and renew the contents of the defect signature library for each new IC design while process and yield are improved.10-11-2012
20120191399System and Method for Detecting Miswiring of an Electrical Appliance - A system for detecting the miswiring of an electrical appliance that includes a microprocessor having first and second input connections to sample signals on two different electrical power lines. The microprocessor further includes a third input connection for a neutral line. In an embodiment of the invention, there is at least one switch through which electrical power can flow into a load. The at least one switch is controlled by the microprocessor. In a particular embodiment, the microprocessor is configured to compare the signals sampled at the first and second input connections to determine whether the electrical appliance has been wired correctly.07-26-2012
20120232826APPARATUS AND METHOD FOR WIRELESS TESTING OF A PLURALITY OF TRANSMIT PATHS AND A PLURALITY OF RECEIVE PATHS OF AN ELECTRONIC DEVICE - An apparatus for wireless testing, the apparatus comprising: a test interface, a test generator, a test module, and an analysis module. The test interface is coupled to an electronic device and is configured to transmit data to the electronic device and to receive data from the electronic device. The test generator drives the electronic device through the test interface to vary the beam direction. The test module determines a plurality of transmit values of a transmit parameter based on the test signal wirelessly received from the electronic device using at least one static antenna for receiving the test signal. Each transmit value of the transmit parameter is associated with a different beam direction. The analysis module provides an assessment of the plurality of transmit paths of the electronic device based on the plurality of transmit values.09-13-2012
20120232825FUNCTIONAL FABRIC-BASED TEST CONTROLLER FOR FUNCTIONAL AND STRUCTURAL TEST AND DEBUG - A Test Access Mechanism (TAM) architecture for facilitating testing of IP blocks integrated on a System on a Chip (SoC). The TAM architecture includes a Test Controller and one or more Test Wrappers that are integrated on the SoC proximate to IP blocks. Test data and commands corresponding to input from an external tester are packaged by the Test Controller and sent to the Test Wrappers via an interconnect fabric. The Test Wrappers employ interface with one or more test ports to provide test data, control, and/or stimulus signals to the IP block to facilitate circuit-level testing of the IP block. Test results for the circuit-level tests are returned to the Test Controller via the fabric. Test Wrappers may be configured to pass through interconnect signals, enabling functional testing of IP blocks to be facilitated via test packages and test results transmitted between the Test Controller and the IP blocks via the fabric. The TAM may be implemented in a fabric-to-fabric bridge, enabling testing of IP blocks connected to fabrics on both sides of the bridge.09-13-2012
20110130999TEST SYSTEM FOR CONNECTORS - A test system includes a main selector, a first and a second switching connectors, a first and a second sub-selectors, and a processor. The main selector includes a number of first switches, a number of first contacts, and a number of second contacts. Each sub-selector includes a second switch, a third contact, and a fourth contact. The processor sends a first instruction and a second instruction to correspondingly control the main selector and a selected sub-selector.06-02-2011
20120265475Device for Testing a Charge System and Method of Providing and Using the Same - In some embodiments, a device for testing a charge system and method of providing and using the same. Other embodiments of related devices and methods are also disclosed.10-18-2012
20100169037FLASH MEMORY THRESHOLD VOLTAGE CHARACTERIZATION - In an embodiment, the invention provides a method for characterizing a threshold voltage of a flash memory cell. The method comprises generating a pulse train signal on flash memory IC, applying the pulse train signal to an external low-pass filter, and applying an output of the low-pass filter to the input of an external gain stage. An analog signal from the output of the gain stage is directed to a control gate of the flash memory cell. An electrical parameter of the flash memory cell is measured by an external tester.07-01-2010
20130013247SEMICONDUCTOR DEVICE, DETECTION METHOD AND PROGRAM - A semiconductor device and the like that can determine the performance of a semiconductor integrated circuit with higher accuracy even when test environment fluctuates. The semiconductor device detects degradation of the semiconductor integrated circuit, including measurement unit that measures temperature and voltage, decision unit that judges whether the test is executed within an allowable test timing in the detection target circuit portion at each test operation frequency and decides a maximum test operation frequency and calculation unit that converts a maximum test operation frequency into that at a standard temperature and voltage and calculates a degradation amount. The semiconductor integrated circuit has a monitor block circuit that monitors the values for the measurement unit to measure temperature and voltage. The measurement unit has estimation unit that estimates temperature and voltage of a detection target circuit portion based on the monitored values. The calculation unit uses the estimated temperature and voltage.01-10-2013
20130013246METHOD AND APPARATUS FOR POST-SILICON TESTING - An apparatus and a computer-implemented method performed by a computerized device, comprising: generating a collection of test data for testing one or more domains, wherein the test data is useful for post-silicon verification of hardware devices; selecting a subset of the collection of test data in accordance with a hardware device to be tested and at least one of the domains to be tested with respect to the hardware device; and indexing the subset of the collection of test data to obtain an indexed collection.01-10-2013
20120150475APPARATUS FOR OBTAINING PLANARITY MEASUREMENTS WITH RESPECT TO A PROBE CARD ANALYSIS SYSTEM - A system and method of mitigating the effects of component deflections in a probe card analyzer system may implement three-dimensional comparative optical metrology techniques to model deflection characteristics. An exemplary system and method combine non-bussed electrical planarity measurements with fast optical planarity measurements to produce “effectively loaded” planarity measurements.06-14-2012
20120150474DEBUG STATE MACHINE CROSS TRIGGERING - In an electronic system that includes a plurality of electronic modules and a plurality of debug circuits, each of which is integrated with one of the plurality of electronic modules, a method for performing debug operations is performed by the plurality of debug circuits. The method includes each of the plurality of debug circuits producing a first cross trigger signal on a communications interface between the plurality of debug circuits, where the first cross trigger signal indicates that a triggering event has not occurred. The method further includes each of the plurality of debug circuits determining whether the triggering event has occurred, and in response to determining that the triggering event has occurred, each of the plurality of debug circuits producing a second cross trigger signal on the communications interface, which indicates that the triggering event has occurred.06-14-2012
20110161040COMPUTER SYSTEM ON AND OFF TEST APPARATUS - A computer system on/off test apparatus includes a parameter setting and test control circuit, a test indicating circuit, a voltage converting circuit, and an on/off signal switch circuit. The parameter setting and test control circuit includes a micro control unit (MCU) to set a number of test times and control an on/off test of a motherboard. The test indicating circuit is operable to display the number set by the parameter setting and test control circuit, and display a successful number of test times of the on/off test. The voltage converting circuit is operable to convert a first voltage received from a first standby power connector to a second voltage. The on/off signal switch circuit is operable to switch the first and second voltages according the control by the MCU.06-30-2011
20130024153MICROPROCESSOR TESTING CIRCUIT - A microprocessor testing circuit includes a sensor selection circuit to select a sensor measuring a characteristic of a microprocessor. An offset circuit artificially drives a signal from the selected sensor out of a predetermined range to invoke a fault operation in the microprocessor.01-24-2013
20130173203HARDWARE-EFFICIENT ON-CHIP CALIBRATION OF ANALOG/RF THROUGH SUB-SAMPLING - A digital on-die-test engine (OTE) is disclosed to generate stimuli signals for an analog/RF circuit, where the OTE is embedded within the circuitry. The stimuli signals are injected into the circuit, feed through the circuit, and are received back into the OTE for analysis. The OTE includes an input subsystem to receive signals from various locations throughout the circuit. The received signals are sub-sampled before being tested. The OTE includes memory-aware and memory-less algorithms for testing the signals. The OTE is capable of changing the configuration of the circuit, where needed, following the tests.07-04-2013
20110313709POWER CIRCUIT ANALYSIS APPARATUS AND METHOD - A power circuit analysis apparatus includes a segmentation unit that segments an analysis target region in a power circuit included in an analysis target circuit into a plurality of segmented regions, and an analysis unit that outputs an analysis result of the power circuit with respect to each of the plurality of segmented regions on a basis of a consumption current value in the segmented region and a number of via holes formed in each interlayer connecting power line wirings in upper and lower layers to each other in the segmented region.12-22-2011
20110313708METHODS FOR MANUFACTURING DEVICES WITH FLEX CIRCUITS AND RADIO-FREQUENCY CABLES - A flex circuit may have test structures and antenna structures. The test structures may include test capacitors and transmission lines. The performance of the test structures may be measured using test equipment. Pass/fail criteria may be applied to the flex circuit based on the measured values. If the flex circuit is a failing circuit, flex circuit manufacturing settings may be adjusted. The performance of a radio-frequency (RF) cable may also be measured using the test equipment. Sample portions of the RF cable may be obtained and measured. Pass/fail criteria may be applied to the RF cable based on measured cable loss values. If the RF cable is a failing cable, RF cable manufacturing settings may be adjusted. Antenna structures associated with passing flex circuits and RF cable segments associated with passing sample RF cable segments may be incorporated into a wireless device during production device assembly.12-22-2011
20110276302RE-CONFIGURABLE TEST CIRCUIT, METHOD FOR OPERATING AN AUTOMATED TEST EQUIPMENT, APPARATUS, METHOD AND COMPUTER PROGRAM FOR SETTING UP AN AUTOMATED TEST EQUIPMENT - A re-configurable test circuit for use in an automated test equipment includes a test circuit, a test processor and a programmable logic device. The pin electronics circuit is configured to interface the re-configurable test circuit with a DUT. The test processor includes a timing circuit configured to provide one or more adjustable-timing signals having adjustable timing. The programmable logic device is configured to implement a state machine, a state sequence of which depends on one or more input signals received from the pin electronics circuit, to provide an output signal, which depends on a current or previous state of the state machine, to the pin electronics circuit in response to the signal(s) received from the pin electronics circuit. The test processor is coupled to the programmable logic device to provide at least one of the adjustable-timing signal(s) to the programmable logic device to define timing of the programmable logic device.11-10-2011
20130185014SYSTEMS, PROCESSES AND COMPUTER-ACCESSIBLE MEDIUM FOR PROVIDING A BI-DIRECTIONAL SCAN PATH FOR PEAK CAPTURE POWER REDUCTION IN LAUCH-OFF-SHIFT TESTING - Exemplary systems, methods and computer-readable mediums can assign, from the circuit, at least two scan cells as at least two interface registers, and generate at least one bidirectional scan path between the at least two interface registers of the at least one portion of the circuit. The at least two interface registers can be disposed in neighboring positions, and the assigning can include a partitioning procedure that can iteratively merge the scan cells of the at least one portion of the circuit into a plurality of regions.07-18-2013
20130191065CLOCK FAULT DETECTOR - A method and apparatus for providing clock fault detection is presented. A first clock of a plurality of clocks on a printed circuit board (PCB) is designated as a reference clock. A reference clock counter is in communication with the reference clock, counting cycles of the reference clock. A counter is provided for each other clock of the plurality of clocks, each counter counting cycles of a respective clock. The reference clock counter and each of the counters are started at a same time. When the reference clock counter reaches a maximum count value the value of each of the counters is stored and a determination is made whether the stored values are expected values.07-25-2013
20120029861SEMICONDUCTOR CIRCUIT, SEMICONDUCTOR CIRCUIT TEST METHOD, AND SEMICONDUCTOR CIRCUIT TEST SYSTEM - In general, according to one embodiment, a semiconductor circuit test method is disclosed. The method can generate a basic format of a test pattern and store the basic format in a test device. The basic format includes at least one parameter and a test program for testing a test target semiconductor circuit. The method can set a predetermined value for the parameter to generate the test pattern including the test program and the parameter set to the predetermined value and supply the test pattern to the test target semiconductor circuit. The method can have store the test program in a first address of a storing module in the test target semiconductor circuit and store the parameter set to the predetermined value in a second address of the storing module. In addition, the method can execute the test program stored in the first address while referring to the parameter stored in the second address.02-02-2012
20120029860TEST CIRCUIT FOR NETWORK INTERFACE - A first output pin of a microcontroller is connected to a control pin of a high speed switch chip. A second output pin of the microcontroller is connected to two control pins of first and second switch chips. Two output pins of the high speed switch chip are connected to two input pins of the first switch chip. Two input pins of a third switch chip are connected to two output pins of the second switch chip. Two control pins of the third switch chip are connected to a third output pin of the microcontroller. Three input pins of a bus switch chip are connected to fourth to sixth output pins of the microcontroller. A load board is connected to six output pins of the bus switch chip and four switch pins of the first and second switch chips.02-02-2012
20130197850Methods for Testing Wireless Electronic Devices Using Automatic Self-Test Mode - A device under test (DUT) may be tested using a radio-frequency test station. The DUT may include at least one antenna, wireless communications circuitry associated with the antenna, and other peripheral components such as a camera module, a display module, and audio circuitry. The test station may include a shielded enclosure in which the DUT is placed during testing. The DUT need not be electrically wired to any test equipment. The DUT may be configured to operate in self test mode. The DUT may be configured to obtain baseline noise floor measurements while all the peripheral components are deactivated and may be configured to obtain elevated noise floor measurements while selectively activating desired subsets of the peripheral components. The difference between the elevated and baseline noise floor measurements may be computed to determine whether at least some of the peripheral components negatively impact the antenna performance by an excessive amount.08-01-2013
20130204569SYSTEM, A METHOD AND A COMPUTER PROGRAM PRODUCT FOR CAD-BASED REGISTRATION - A system for generating calibration information usable for wafer inspection, the system including: (I) a displacement analysis module, configured to: (a) calculate a displacement for each target out of multiple targets selected in multiple scanned frames which are included in a scanned area of the wafer, the calculating based on a correlation of: (i) an image associated with the respective target which was obtained during a scanning of the wafer, and (ii) design data corresponding to the image; and (b) determining a displacement for each of the multiple scanned frames, the determining based on the displacements calculated for multiple targets in the respective scanned frame; and (II) a subsequent processing module, configured to generate calibration information including the displacements determined for the multiple scanned frames, and a target database that includes target image and location information of each target of a group of database targets.08-08-2013

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