Class / Patent application number | Description | Number of patent applications / Date published |
505191000 | Semiconductor thin film device or thin film electric solid-state device or system (i.e., active or passive) | 9 |
20110251071 | Method of Realization of Hyperconductivity and Super Thermal Conductivity - The application relates to electricity, electro-physics and thermo conductivity of materials, to the phenomena of zero electric resistance, i.e. to hyperconductivity (superconductivity) and zero thermal resistance, i.e. to superthermoconductivity of materials at near-room and higher temperatures. The matter: on the surface of in the volume of non-degenerate or poorly degenerate semiconductor material or layer of such material on semi-insulating or dielectric substrate the electrodes are located forming rectifying contacts to the material. The distance between the electrodes (D) is chosen much smaller comparing to the depth of penetration into the material of the electric field caused by their contact difference of potentials (L), (D<10-13-2011 | |
20120028806 | Method For Planar Implementation Of PI/8 Gate In Chiral Topological Superconductors - Disclosed herein is a topologically protected π/8-gate which becomes universal when combined with the gates available through quasi-particle braiding and planar quasi-particle interferometry. A twisted interferometer, and a planar π/8-gate in CTS, implemented with the help of the twisted interferometer, are disclosed. Embodiments are described in the context of state X (CTS) supported by an ISH, although the concept of a twisted-interferometer is more general and has relevance to all anionic, i.e. quasiparticle systems. | 02-02-2012 |
20130196856 | IRON BASED SUPERCONDUCTING STRUCTURES AND METHODS FOR MAKING THE SAME - In some embodiments of the invention, superconducting structures are described. In certain embodiments the superconducting structures described are thin films of iron-based superconductors on textured substrates; in some aspects a method for producing thin films of iron-based superconductors on textured substrates is disclosed. In some embodiments applications of thin films of iron-based superconductors on textured substrates are described. Also contemplated is the formation of a film of iron-based superconductor having a thickness and an in-plane lattice constant formed on a textured substrate having a thickness and an in-plane lattice constant similar to the in-plane lattice constant of the iron-based superconductor. | 08-01-2013 |
20150045228 | Radio Frequency-Assisted Fast Superconducting Switch - A radio frequency-assisted fast superconducting switch is described. A superconductor is closely coupled to a radio frequency (RF) coil. To turn the switch “off,” i.e., to induce a transition to the normal, resistive state in the superconductor, a voltage burst is applied to the RF coil. This voltage burst is sufficient to induce a current in the coupled superconductor. The combination of the induced current with any other direct current flowing through the superconductor is sufficient to exceed the critical current of the superconductor at the operating temperature, inducing a transition to the normal, resistive state. A by-pass MOSFET may be configured in parallel with the superconductor to act as a current shunt, allowing the voltage across the superconductor to drop below a certain value, at which time the superconductor undergoes a transition to the superconducting state and the switch is reset. | 02-12-2015 |
20170237252 | CURRENT LIMITER ARRANGEMENT AND METHOD FOR MANUFACTURING A CURRENT LIMITER ARRANGEMENT | 08-17-2017 |
505193000 | Superconducting transistor (e.g., Josephson transistor, etc.) | 4 |
20080312088 | Field effect transistor, logic circuit including the same and methods of manufacturing the same - Provided are a field effect transistor, a logic circuit including the same and methods of manufacturing the same. The field effect transistor may include an ambipolar layer that includes a source region, a drain region, and a channel region between the source region and the drain region, wherein the source region, the drain region, and the channel region may be formed in a monolithic structure, a gate electrode on the channel region, and an insulating layer separating the gate electrode from the ambipolar layer, wherein the source region and the drain region have a width greater than that of the channel region in a second direction that crosses a first direction in which the source region and the drain region are connected to each other. | 12-18-2008 |
20110287941 | Method for Planar Implementation of PI/8 Gate in Chiral Topological Superconductors - Disclosed herein is a topologically protected π/8-gate which becomes universal when combined with the gates available through quasi-particle braiding and planar quasi-particle interferometry. A twisted interferometer, and a planar π/8-gate in CTS, implemented with the help of the twisted interferometer, are disclosed. Embodiments are described in the context of state X (CTS) supported by an ISH, although the concept of a twisted-interferometer is more general and has relevance to all anionic, i.e. quasiparticle systems. | 11-24-2011 |
20130123111 | ELECTRONIC DEVICE HAVING THERMALLY MANAGED ELECTRON PATH AND METHOD OF THERMAL MANAGEMENT OF VERY COLD ELECTRONS - A device and a method of thermal management. In one embodiment, the device includes an integrated circuit, including: (1) a conductive region configured to be connected to a voltage source, (2) a transistor having a semiconductor channel with a controllable conductivity and (3) first and second conducting leads connecting to respective first and second ends of said channel, wherein a charge in the conductive region is configured to substantially raise an electrical potential energy of conduction charge carriers in the semiconductor channel and portions of said leads are located where an electric field produced by said charge is substantially weaker than near the semiconductor channel. | 05-16-2013 |
20160028402 | SUPERCONDUCTING THREE-TERMINAL DEVICE AND LOGIC GATES - A three-terminal device that exhibits transistor-like functionality at cryogenic temperatures may be formed from a single layer of superconducting material. A main current-carrying channel of the device may be toggled between superconducting and normal conduction states by applying a control signal to a control terminal of the device. Critical-current suppression and device geometry are used to propagate a normal-conduction hotspot from a gate constriction across and along a portion of the main current-carrying channel. The three-terminal device may be used in various superconducting signal-processing circuitry. | 01-28-2016 |