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Plural coating steps

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438 - Semiconductor device manufacturing: process

438689000 - CHEMICAL ETCHING

438694000 - Combined with coating step

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DocumentTitleDate
20120184107SEMICONDUCTOR DEVICE MANUFACTURING METHOD - In a semiconductor device manufacturing method, the formation of a sacrificial oxide film and removal thereof by wet etching and/or the formation of a silicon dioxide film and removal thereof by wet etching are performed. In the process for manufacturing a semiconductor device, the formation of the sacrificial oxide film and/or the silicon dioxide film is performed within a processing chamber of a plasma processing apparatus using a plasma in which O(07-19-2012
20120184106METHOD AND ALGORITHM FOR RANDOM HALF PITCHED INTERCONNECT LAYOUT WITH CONSTANT SPACING - An embodiment of a system and method produces a random half pitched interconnect layout. A first normal-pitch mask and a second normal-pitch mask are created from a metallization layout having random metal shapes. The lines and spaces of the first mask are printed at normal pitch and then the lines are shrunk to half pitch on mask material. First spacers are used to generate a half pitch dimension along the outside of the lines of the first mask. The mask material outside of the first spacer pattern is partially removed. The spacers are removed and the process is repeated with the second mask. The mask material remains at the locations of first set of spacers and/or the second set of spacers to create a half pitch interconnect mask with constant spaces.07-19-2012
20120184105METHOD OF FORMING OPENINGS - A method for forming openings is provided. First, a substrate with a silicon-containing photo resist layer thereon is provided. Second, a first photo resist pattern is formed on the silicon-containing photo resist layer. Later, a first etching procedure is carried out on the silicon-containing photo resist layer to form a plurality of first openings by using the first photo resist pattern as an etching mask. Next, a second photo resist pattern is formed on the silicon-containing photo resist layer. Then, a second etching procedure is carried out on the silicon-containing photo resist layer to form a plurality of second openings by using the second photo resist pattern as an etching mask.07-19-2012
20120184104METHOD FOR FABRICATING FINE PATTERN IN SEMICONDUCTOR DEVICE - A method for fabricating a fine pattern in a semiconductor device includes forming a first photoresist over a substrate where an etch target layer is formed, doping at least one impurity selected from group III elements and group V elements, of the periodic table, into the first photoresist, forming a photoresist pattern over the first photoresist, performing a dry etching process using the photoresist pattern to expose the first photoresist, etching the first photoresist by an oxygen-based dry etching to form a first photoresist pattern where a doped region is oxidized, and etching the etch target layer using the first photoresist pattern as an etch barrier.07-19-2012
20120184103RESIST UNDERLAYER FILM COMPOSITION AND PATTERNING PROCESS USING THE SAME - There is disclosed a resist underlayer film composition, wherein the composition contains a polymer obtained by condensation of, at least, one or more compounds represented by the following general formulae (1-1) and/or (1-2), and one or more kinds of compounds, represented by the following general formulae (2-1) and/or (2-2), and/or equivalent bodies thereof. There can be provided an underlayer film composition, especially for a trilayer resist process, that can form an underlayer film having reduced reflectance, (namely, an underlayer film having optimum n-value and k-value as an antireflective film), excellent filling-up properties, high pattern-antibending properties, and not causing line fall or wiggling after etching especially in a high aspect line that is thinner than 60 nm, and a patterning process using the same.07-19-2012
20100151685METHODS OF REMOVING MULTI-LAYERED STRUCTURE AND OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of removing a multi-layered structure includes the following processes. A semiconductor substrate is prepared. The semiconductor substrate has a multi-layered structure including a first film over the semiconductor substrate, a second film on the first film, and a mask pattern film on the second film. Then, the mask pattern film is removed. Then, the second film is removed by etching the second film with a first etching selectivity of the second film to the first film. The first etching selectivity is greater than a second etching selectivity of the second film to the first film with which the second film is patterned by etching using the mask pattern film. Then, the third film is removed.06-17-2010
20120178261SILICON-CONTAINING COMPOSITION HAVING SULFONAMIDE GROUP FOR FORMING RESIST UNDERLAYER FILM - There is provided a lithographic resist underlayer film-forming composition for forming a resist underlayer film which can be used as a hard mask. A lithographic resist underlayer film-forming composition including a silane compound having sulfonamide group, wherein the silane compound having sulfonamide group is a hydrolyzable organosilane having a sulfonamide group in the molecule, a hydrolyzate thereof, or a hydrolytic condensation product thereof. The composition including a silane compound having sulfonamide group and a silane compound lacking a sulfonamide group, wherein the silane compound having sulfonamide group is present within the silane compounds overall in a proportion of less than 1 mol %, for example 0.1 to 0.95 mol %.07-12-2012
20130084704METHOD FOR MANUFACTURING MICROSTRUCTURE - According to one embodiment, a method for manufacturing a microstructure includes forming a guide film on a patterning material, forming a cured film, forming a mask member, and performing processing of the patterning material using the mask member as a mask. An opening is made in the guide film. An upper surface of the guide film is hydrophilic, a side surface of the opening is hydrophobic. The forming the cured film includes applying a solution to cover the patterning material and the guide film, separating the solution into a hydrophobic block and a hydrophilic block, and curing the solution. The solution contains an amphiphilic polymer having a hydrophobic portion and a hydrophilic portion. A length of the hydrophobic portion is longer than a length of the hydrophilic portion. The mask member is formed by removing the hydrophilic block from the cured film.04-04-2013
20100075503INTEGRAL PATTERNING OF LARGE FEATURES ALONG WITH ARRAY USING SPACER MASK PATTERNING PROCESS FLOW - Embodiments of the present invention pertain to methods of forming patterned features on a substrate having an increased density (i.e. reduced pitch) as compared to what is possible using standard photolithography processing techniques using a single high-resolution photomask while also allowing both the width of the patterned features and spacing (trench width) between the patterned features to vary within an integrated circuit.03-25-2010
20120244714EXPOSURE MASK AND METHOD FOR MANUFACTURING SAME AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - An exposure mask includes: an insulative substrate; a light reflecting film provided on the substrate; a light absorbing film provided on the light reflecting film and forming a pattern in a center region on the substrate; and an interconnect provided on the substrate, the light reflecting film and the light absorbing film not being provided in a frame-shaped region surrounding the center region, and the interconnect being placed so that a portion of a laminated film composed of the light reflecting film and the light absorbing film located inside the frame-shaped region is electrically connected to a portion of the laminated film located outside the frame-shaped region.09-27-2012
20120244713METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device, comprising forming a first photoresist pattern having a hole on a first layer, forming a surface curing layer in the hole and curing the first photoresist pattern on an inner sidewall of the hole to form a first curing pattern, removing the surface curing layer, forming a second photoresist pattern in the hole and curing the second photoresist pattern that contacts with the first curing pattern to form a second curing pattern, removing the first and second photoresist patterns, and etching the first layer using the first and second curing patterns as an etch barrier.09-27-2012
20120244712MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - According to one embodiment, a stacked film including at least a silicon oxide film is formed by stacking a plurality of films formed of different materials and a hard mask pattern is formed on the stacked film. Then, a stacked film pattern of a predetermined shape is formed by performing anisotropic etching on the stacked film by using the hard mask pattern as an etching mask and the hard mask pattern is removed. The hard mask pattern is formed by stacking at least one first hard mask layer and at least one second hard mask layer. The first hard mask layer is formed of a material having a higher removability in wet etching than the second hard mask layer. The first hard mask layer is arranged immediately above the stacked film.09-27-2012
20130078814RESIST UNDERLAYER FILM FORMING COMPOSITION CONTAINING SILICON HAVING ANION GROUP - There is provided a method of making a semiconductor device utilizing a resist underlayer film forming composition comprising a silane compound containing an anion group, wherein the silane compound containing an anion group is a hydrolyzable organosilane in which an organic group containing an anion group is bonded to a silicon atom and the anion group forms a salt structure, a hydrolysis product thereof, or a hydrolysis-condensation product thereof. The anion group may be a carboxylic acid anion, a phenolate anion, a sulfonic acid anion, or a phosphonic acid anion. The hydrolyzable organosilane may be a compound of Formula (1): R03-28-2013
20090130854PATTERNING STRUCTURE AND METHOD FOR SEMICONDUCTOR DEVICES - Methods for forming a pattern layer over a target layer are disclosed. The methods use a novel low temperature spacer structure which results in a pattern layer having a decreased pattern pitch versus conventional patterning using photolithography. The decreased pattern pitch allows the target layer to be divided into multiple regions separated by a small distance, which in turn allows for greater density and device miniaturization. The structure and methods may be applied to patterning a word line layer in a memory device.05-21-2009
20090142928MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A manufacturing method for a semiconductor device simplifies a process for forming an oxide film of a high-voltage device, thereby reducing the manufacturing costs and manufacturing time of the high-voltage device. The manufacturing method includes applying a gate oxide material over a semiconductor wafer, applying a photoresist material over the gate oxide material, performing an exposure process and a primary development process on the photoresist material to form a photoresist pattern, performing an etching process using the photoresist pattern to form a gate oxide film, and performing a secondary development process to remove the photoresist pattern.06-04-2009
20130034965METHODS OF FORMING FINE PATTERNS USING DRY ETCH-BACK PROCESSES - In a method of fabricating patterns in an integrated circuit device, first mask patterns, sacrificial patterns, and second mask patterns are formed on a target layer such that the sacrificial patterns are provided between sidewalls of adjacent ones of the first and second mask patterns. The sacrificial patterns between the sidewalls of the adjacent ones of the first and second mask patterns are selectively removed using a dry etch-back process, and the target layer is patterned using the first and second mask patterns as a mask.02-07-2013
20100041235MANUFACTURING METHOD OF SEMICONDUCTOR DEVICES - A semiconductor device manufacturing method includes: depositing a first insulating film and a second insulating film on a substrate sequentially and forming a pattern on the second insulating film; forming a silicon film on the pattern; forming a sidewall made of the silicon film by processing the silicon film until a part of the second insulating film is exposed by use of etch-back; removing the second insulating film; and performing dry etching by use of a fluorocarbon-based gas, to process the first insulating film by using the sidewall as a mask. The processing of the first insulating film includes applying on the substrate a self-bias voltage Vdc that satisfies a relational expression of Vdc<46x−890, where a film thickness of the silicon film that constitutes the sidewall is x nm (19.5≦x≦22.1).02-18-2010
20100330810METHOD FOR REMOVING THRESHOLD VOLTAGE ADJUSTING LAYER WITH EXTERNAL ACID DIFFUSION PROCESS - The present invention provides a method of forming a threshold voltage adjusted gate stack in which an external acid diffusion process is employed for selectively removing a portion of a threshold voltage adjusting layer from one device region of a semiconductor substrate. The external acid diffusion process utilizes an acid polymer which when baked exhibits an increase in acid concentration which can diffuse into an underlying exposed portion of a threshold voltage adjusting layer. The diffused acid reacts with the exposed portion of the threshold voltage adjusting layer providing an acid reacted layer that can be selectively removed as compared to a laterally adjacent portion of the threshold voltage adjusting layer that is not exposed to the diffused acid.12-30-2010
20090124086METHOD OF FABRICATING A FLASH MEMORY DEVICE - A method of fabricating a flash memory device, in which a pre-metal dielectric layer, a hard mask layer, and a first etch mask pattern are sequentially formed over a semiconductor substrate; an auxiliary layer is formed along a surface of the first etch mask pattern and the hard mask layer; and an etch mask layer is formed on the auxiliary layer to gap-fill between adjacent first etch mask pattern elements. The etch mask layer is etched to form a second etch mask pattern between adjacent first etch mask pattern elements. The auxiliary layer between the first and second etch mask patterns is removed; and a hard mask pattern is formed by etching the hard mask layer between the first etch mask pattern and the second etch mask pattern. The pre-metal dielectric layer is etched process using the hard mask pattern as a mask to form contact holes.05-14-2009
20130045603SEMICONDUCTOR PROCESS - A semiconductor process is described as follows. A material layer is provided on a substrate. A low-temperature oxidation treatment is performed to the material layer. A photoresist layer is formed on the material layer after the low-temperature oxidation treatment. The photoresist layer is patterned.02-21-2013
20130052832PRODUCING TRANSISTOR INCLUDING SINGLE LAYER REENTRANT PROFILE - A method of producing a transistor includes providing a substrate including a first electrically conductive material layer. A resist material layer is deposited over the first electrically conductive material layer. The resist material layer is patterned to expose a portion of the first electrically conductive material layer. Some of the first electrically conductive material layer is removed to create a reentrant profile in the first electrically conductive material layer and expose a portion of the substrate. The first electrically conductive material layer and at least a portion of the substrate are conformally coated with an electrically insulating material layer.02-28-2013
20130089985Enhancing Transistor Performance by Reducing Exposure to Oxygen Plasma in a Dual Stress Liner Approach - When forming strain-inducing dielectric material layers above transistors of different conductivity type, the patterning of at least one strain-inducing dielectric material may be accomplished on the basis of a process sequence in which a negative influence of a fluorine species in an oxygen plasma upon removing the resist mask is avoided or at least significantly suppressed. For example, a substantially oxygen-free plasma process may be applied for removing the resist material.04-11-2013
20130089986METHOD OF FORMING PATTERNS OF SEMICONDUCTOR DEVICE - A method of forming patterns of a semiconductor device may include forming a photoresist layer that includes a photo acid generator (PAG) and a photo base generator (PBG), generating an acid from the PAG in a first exposed portion of the photoresist layer by first-exposing the photoresist layer, and generating a base from the PBG in a second exposed portion of the photoresist layer by second-exposing a part of the first exposed portion and neutralizing the acid. The method may also include baking the photoresist layer after the first and second-exposing and deblocking the photoresist layer of the first exposed portion in which the acid is generated to form a deblocked photoresist layer, and forming a photoresist pattern by removing the deblocked photoresist layer by using a developer.04-11-2013
20130072023METHOD OF CONTROLLED LATERAL ETCHING - A method of controlled lateral etching is disclosed. In one embodiment, the method may comprise: forming on a first material layer, which comprises a protruding structure, a second material layer; forming spacers on outer surfaces of the second material layer opposite to vertical surfaces of the protruding structure; forming a third material layer on surfaces of the second material layer and the spacers; forming on the third material layer a mask layer which extends in a direction lateral to a surface of the first material layer; and laterally etching portions of the respective layers arranged on the vertical surfaces of the protruding structure.03-21-2013
20090269932Method for fabricating self-aligned complimentary pillar structures and wiring - A method of making a semiconductor device includes forming at least one device layer over a substrate, forming at least two spaced apart features over the at least one device layer, forming sidewall spacers on the at least two features, selectively removing the spaced apart features, filling a space between a first sidewall spacer and a second sidewall spacer with a filler feature, selectively removing the sidewall spacers to leave a plurality of the filler features spaced apart from each other, and etching the at least one device layer using the filler feature as a mask.10-29-2009
20130065397Methods to increase pattern density and release overlay requirement by combining a mask design with special fabrication processes - A novel process technique and mask design based on the optimized self-aligned triple patterning are invented for the semiconductor manufacturing. This invention pertains to methods of forming one and/or two dimensional features on a substrate having the feature density increased to three times of what is possible using optical lithography, and methods to release the overlay requirement when patterning the critical layers of semiconductor devices.03-14-2013
20090047790Selective Wet Etching of Hafnium Aluminum Oxide Films - Methods and etchant compositions for wet etching to selectively remove a hafnium aluminum oxide (HfAlO02-19-2009
20090029556METHOD FOR FORMING A SHALLOW TRENCH ISOLATION - A method for forming a shallow trench isolation includes providing a substrate with a trench, a first liner layer and a second liner layer sequentially in the trench with a first oxide filling the trench, performing a first wet etching to remove part of the first oxide and part of the first liner layer to expose the substrate, performing a second wet etching to remove part of the second liner layer so that the second liner layer is lower than surface of the substrate, performing a third wet etching to remove part of the first oxide and part of the first liner layer, and filling the trench with a second oxide to form a shallow trench isolation.01-29-2009
20090011603METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - The invention prevents a wiring layer in a memory region from being exposed to prevent a change in wire resistance and degradation of reliability. A SiO01-08-2009
20080318430METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE HAVING POROUS LOW DIELECTRIC CONSTANT LAYER FORMED FOR INSULATION BETWEEN METAL LINES - The present invention related to a method for manufacturing a semiconductor device. More particularly, this method describes how to manufacture a semiconductor device having a porous, low dielectric constant layer formed between metal lines, comprising an insulation layer enveloping fillers.12-25-2008
20120238099METHOD OF MANUFACTURING ELECTRONIC PART - According to one embodiment, a process target above a substrate is processed in order to produce a wiring pattern including dense wirings and sparse wirings. Next, a sacrificial film filled between wirings is formed in a region where the dense wirings are formed, and then an insulation film is formed above the substrate. A mask is formed such that a part of the region where the dense wirings are formed is exposed and a region where the sparse wirings are formed is exposed, and the insulation film is etched using the mask. Then, the sacrificial film is removed through a part of the region where the dense wirings are formed. Thereafter, an embedded insulation film is formed above the substrate to fill a gap between adjacent wirings in the region where the sparse wirings are formed.09-20-2012
20110281435FAST GAS SWITCHING PLASMA PROCESSING APPARATUS - A plasma chamber with a plasma confinement zone with an electrode is provided. A gas distribution system for providing a first gas and a second gas is connected to the plasma chamber, wherein the gas distribution system can substantially replace one gas in the plasma zone with the other gas within a period of less than 1 s. A first frequency tuned RF power source for providing power to the electrode in a first frequency range is electrically connected to the at least one electrode wherein the first frequency tuned RF power source is able to minimize a reflected RF power. A second frequency tuned RF power source for providing power to the plasma chamber in a second frequency range outside of the first frequency range wherein the second frequency tuned RF power source is able to minimize a reflected RF power.11-17-2011
20130023124METHOD OF PATTERNING A LOW-K DIELECTRIC FILM - Methods of patterning low-k dielectric films are described. For example, a method includes forming and patterning a mask layer above a low-k dielectric layer, the low-k dielectric layer disposed above a substrate. Exposed portions of the low-k dielectric layer are modified with a plasma process. The modified portions of the low-k dielectric layer are removed selective to the mask layer and unmodified portions of the low-k dielectric layer.01-24-2013
20110130006MASK MATERIAL CONVERSION - The dimensions of mask patterns, such as pitch-multiplied spacers, are controlled by controlled growth of features in the patterns after they are formed. To form a pattern of pitch-multiplied spacers, a pattern of mandrels is first formed overlying a semiconductor substrate. Spacers are then formed on sidewalls of the mandrels by depositing a blanket layer of material over the mandrels and preferentially removing spacer material from horizontal surfaces. The mandrels are then selectively removed, leaving behind a pattern of freestanding spacers. The spacers comprise a material, such as polysilicon and amorphous silicon, known to increase in size upon being oxidized. The spacers are oxidized to grow them to a desired width. After reaching the desired width, the spacers can be used as a mask to pattern underlying layers and the substrate. Advantageously, because the spacers are grown by oxidation, thinner blanket layers can be deposited over the mandrels, thereby allowing the deposition of more conformal blanket layers and widening the process window for spacer formation.06-02-2011
20110300713OVERLAY VERNIER KEY AND METHOD FOR FABRICATING THE SAME - Methods are disclosed for fabricating an overlay vernier key. A method includes forming a pattern layer and an insulating layer over a semiconductor substrate. The insulating layer is etched to form insulating layer patterns to partially expose the pattern layer. Spacers are formed on sidewalls of the insulating layer patterns. The insulating layer patterns are removed while leaving the spacers to obtain a spacer-shaped etch mask. The pattern layer is etched using the spacer-shaped etch mask to form vernier patterns. At least one of the vernier patterns has a hollow shape.12-08-2011
20110300712Methods of Forming a Photoresist Pattern Using Plasma Treatment of Photoresist Patterns - Methods of forming a photoresist pattern include forming a first photoresist pattern on a substrate and treating the first photoresist pattern with plasma that modifies etching characteristics of the first photoresist pattern. This modification may include making the first photoresist pattern more susceptible to removal during subsequent processing. The plasma-treated first photoresist pattern is covered with a second photoresist layer, which is patterned into a second photoresist pattern that contacts sidewalls of the plasma-treated first photoresist pattern. The plasma-treated first photoresist pattern is selectively removed from the substrate to reveal the remaining second photoresist pattern. The second photoresist pattern is used as an etching mask during the selective etching of a portion of the substrate (e.g., target layer). The use of the second photoresist pattern as an etching mask may yield narrower linewidths in the etched portion of the substrate than are achievable using the first photoresist pattern alone.12-08-2011
20110124197METHOD TO IMPROVE THE RELIABILITY OF THE BREAKDOWN VOLTAGE IN HIGH VOLTAGE DEVICES - A structure to diminish high voltage instability in a high voltage device when under stress includes an amorphous silicon layer over a field oxide on the high voltage device.05-26-2011
20110143544METHOD OF FORMING MICROPATTERN, DIE FORMED BY THIS METHOD OF FORMING MICROPATTERN, TRANSFER METHOD AND MICROPATTERN FORMING METHOD USING THIS DIE - A micropattern is joined to a substrate (W06-16-2011
20110294297Method of manufacturing semiconductor device - In a method of forming a dense contact-hole pattern in a semiconductor device, the method uses a self-align double patterning technique including forming a square or triangular lattice dot pattern on double layers of mask materials, forming first holes in the upper mask material and second holes wider than the first holes in the lower mask material by double patterning, additionally forming an insulating layer to a thickness such that the first holes are closed such that voids are left in the second holes, and transferring the shape of the voids to a base layer. The hole pattern formed thereby has a high precision, with a density thereof being double or triple that of a pattern formed by a lithography technique.12-01-2011
20120088369Atomic Layer Deposition Of Photoresist Materials And Hard Mask Precursors - Methods for forming photoresists sensitive to radiation on substrate are provided. Atomic layer deposition methods of forming films (e.g., silicon-containing films) photoresists are described. The process can be repeated multiple times to deposit a plurality of silicon photoresist layers. Process of depositing photoresist and forming patterns in photoresist are also disclosed which utilize carbon containing underlayers such as amorphous carbon layers.04-12-2012
20120015522SUBSTRATE PROCESSING METHOD, SEMICONDUCTOR CHIP MANUFACTURING METHOD, AND RESIN-ADHESIVE-LAYER-BACKED SEMICONDUCTOR CHIP MANUFACTURING METHOD - To provide a substrate processing method and a semiconductor chip manufacturing method that enable low-cost formation of a mask for etching using plasma etching. During formation of a mask used in plasma dicing for separating a semiconductor wafer 01-19-2012
20120015521AMORPHOUS CARBON DEPOSITION METHOD FOR IMPROVED STACK DEFECTIVITY - Embodiments described herein relate to materials and processes for patterning and etching features in a semiconductor substrate. In one embodiment, a method of forming a composite amorphous carbon layer for improved stack defectivity on a substrate is provided. The method comprises positioning a substrate in a process chamber, introducing a hydrocarbon source gas into the process chamber, introducing a diluent source gas into the process chamber, introducing a plasma-initiating gas into the process chamber, generating a plasma in the process chamber, forming an amorphous carbon initiation layer on the substrate, wherein the hydrocarbon source gas has a volumetric flow rate to diluent source gas flow rate ratio of 1:12 or less; and forming a bulk amorphous carbon layer on the amorphous carbon initiation layer, wherein a hydrocarbon source gas used to form the bulk amorphous carbon layer has a volumetric flow rate to a diluent source gas flow rate of 1:6 or greater to form the composite amorphous carbon layer.01-19-2012
20090104780METHOD FOR MANUFACTURING SEMICONDCUTOR DEVICE - A method for manufacturing a semiconductor device includes forming an ONO layer in a memory region and forming several gate oxide layer patterns in a logic region, a nitride layer in the logic region can be used as a hard mask, enabling a reduction in the number of masks used. This results in improved manufacturing efficiency and reduced manufacturing costs of a SONOS semiconductor device.04-23-2009
20090291560FORMING METHOD OF ETCHING MASK, CONTROL PROGRAM AND PROGRAM STORAGE MEDIUM - A feedforward control is performed so that a line width of a mask constituted by an Si11-26-2009
20100136791Method of Reducing Delamination in the Fabrication of Small-Pitch Devices - A method of forming an integrated circuit structure includes providing a substrate; forming a first hard mask layer over the substrate; forming a second hard mask layer over the first hard mask layer; patterning the second hard mask layer to form a hard mask; and, after the step of patterning the second hard mask layer, baking the substrate, the first hard mask layer, and the hard mask. After the step of baking, a spacer layer is formed, which includes a first portion on a top of the hard mask, and a second portion and a third portion on opposite sidewalls of the hard mask. The method further includes removing the first portion of the spacer layer; removing the hard mask; and using the second portion and the third portion of the spacer layer as masks to pattern the first hard mask layer.06-03-2010
20090298293Etching with Improved Control of Critical Feature Dimensions at the Bottom of Thick Layers - The present invention relates to a method for etching a feature in an etch layer that has a thickness of more than 2 micrometers from an initial contact face for the etchant to an opposite bottom face of the etch layer, at a lateral feature position in the etch layer and with a critical lateral extension at the bottom face. The method includes fabricating, at the lateral feature position on the substrate layer, a mask feature from a mask-layer material, the mask feature having the critical lateral extension. The etch layer is deposited to a thickness of more than 2 micrometers, on the mask feature and on the substrate layer, from an etch-layer material, which is selectively etchable relative to the mask-layer material. Then, the feature is etched in the etch layer at the first lateral position with a lateral extension larger than the critical lateral extension, using an etchant that selectively removes the etch layer-material relative to the mask-layer material.12-03-2009
20090163028METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes forming an organic bottom anti-reflective coating over an etch target layer, forming a photoresist pattern over the organic bottom anti-reflective coating, and etching the organic bottom anti-reflective coating using a sulfur-containing gas.06-25-2009
20120190206SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor device manufacturing method includes forming a first organic film pattern on a to-be-etched layer on a substrate, forming a silicon oxide film coating the first organic film pattern-etching the silicon oxide film to form a first mask pattern to cause the width of the line part of the first organic film pattern to have a fixed proportion with respect forming a second organic film pattern coating the silicon oxide film, forming a second mask pattern including the silicon oxide film on a side face part in an area coated by the second organic film pattern, and forming, in an area other than the area coated by the second organic film pattern, a third mask pattern in which an even number of the silicon oxide films are arranged.07-26-2012
20120190205METHODS FOR SELF-ALIGNED SELF-ASSEMBLED PATTERNING ENHANCEMENT - Methods for producing self-aligned, self-assembled sub-ground-rule features without the need to use additional lithographic patterning. Specifically, the present disclosure allows for the creation of assist features that are localized and self-aligned to a given structure. These assist features can either have the same tone or different tone to the given feature.07-26-2012
20110217846METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - To prevent the occurrence of short circuit or abnormality of wiring resistance values, a semiconductor wafer is subjected to nitrogen plasma treatment after one of the following steps is over; a step of providing a resist pattern on an inter-layer insulation film and then dry-etching the inter-layer insulation film, and a step of dry-etching a stressor SiN film after the resist pattern is removed.09-08-2011
20090098735METHOD OF FORMING ISOLATION LAYER IN SEMICONDCUTOR DEVICE - A method of forming an isolation layer in a semiconductor device which prevents formation of voids in the isolation layer by sequentially forming an insulating layer and an anti-reflective layer on and/or over a semiconductor substrate, and then forming a photoresist pattern on and/or over the anti-reflective layer, and then forming an insulating layer pattern on and/or over and corresponding to an isolation area of the substrate by performing an etch process using the photoresist pattern as an etch mask, and then forming a polysilicon layer around the insulating layer pattern such that the insulating layer patterns protrudes from the uppermost surface of the polysilicon layer.04-16-2009
20090149026METHOD FOR FORMING HIGH DENSITY PATTERNS - Methods are disclosed, such as those involving increasing the density of isolated features in an integrated circuit. In one or more embodiments, a method is provided for forming an integrated circuit with a pattern of isolated features having a final density of isolated features that is greater than a starting density of isolated features in the integrated circuit by a multiple of two or more. The method can include forming a pattern of pillars having a density X, and forming a pattern of holes amongst the pillars, the holes having a density at least X. The pillars can be selectively removed to form a pattern of holes having a density at least 2X. In some embodiments, plugs can be formed in the pattern of holes, such as by epitaxial deposition on the substrate, in order to provide a pattern of pillars having a density 2X. In other embodiments, the pattern of holes can be transferred to the substrate by etching.06-11-2009
20120142194METHOD OF FORMING SEMICONDUCTOR MEMORY DEVICE - A method of forming semiconductor memory device includes forming first to fourth spacers over a target layer including a first region and second regions adjacent to the first region so that a first spacer group including the first spacers spaced at a first interval is formed in the first region of the target layer, a second spacer group including the second spacers spaced at second intervals is formed in the second regions, a third spacer is formed between the first and the second spacer groups, and fourth spacers are formed between the third spacer and the first spacer group; forming an overlap pattern blocking the target layer; and forming first patterns, spaced at the first interval and each formed to have a first width, in the first region and second patterns, spaced at the second intervals and each formed to have a second width, in the second regions.06-07-2012
20100099262METHOD OF MANUFACTURING NON-VOLATILE MEMORY CELL USING SELF-ALIGNED METAL SILICIDE - In a method of manufacturing a non-volatile memory cell, a self-aligned metal silicide is used in place of a conventional tungsten metal layer to form a polysilicon gate, and the self-aligned metal silicide is used as a connection layer on the polysilicon gate. By using the self-aligned metal silicide to form the polysilicon gate, the use of masks in the etching process may be saved to thereby enable simplified manufacturing process and accordingly, reduced manufacturing cost. Meanwhile, the problem of resistance shift caused by an oxidized tungsten metal layer can be avoided.04-22-2010
20090258500METHOD OF FORMING A PATTERN FOR A SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE RELATED MOS TRANSISTOR - A method of forming a pattern for a semiconductor device, in which, two hard masks are included between an upper spin-on glass (SOG) layer and a lower etching target layer. The SOG layer is etched twice through two different patterned photoresists respectively to form a fine pattern in the SOG layer. Subsequently, an upper hard mask is etched by utilizing the patterned SOG layer as an etching mask so the upper patterned hard mask can have a fine pattern with a sound shape and enough thickness. A lower hard mask and the etching target layer are thereafter etched by utilizing the upper patterned hard mask as an etching mask, so portions of the etching target layer that are covered by the two hard masks can be well protected from the etching processes.10-15-2009
20090263973FIN MASK AND METHOD FOR FABRICATING SADDLE TYPE FIN USING THE SAME - A fin mask for forming saddle type fins in each of active regions formed in an island shape having a certain size with a major axis and a minor axis includes a first fin mask of a line type, and a second fin mask of an island type, wherein the first fin mask and the second fin mask in combination expose saddle type fin regions and cover ends of the neighboring active regions along the major axis.10-22-2009
20100081283METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - According to an aspect of the present invention, there is provided a method for manufacturing a semiconductor device, the method including: sequentially forming a first film and a second film on a base film; processing the second film, thereby forming a second pattern; processing the first film with the second pattern as a mask, thereby forming a first pattern; removing the second pattern; depositing a third film on the base film and on the first pattern; processing the third film, thereby forming a third side wall pattern on a side wall of the first pattern; removing the first pattern; and processing the base film with the third side wall pattern as a mask, thereby forming a target pattern so that, in the target pattern, a space dimension is larger than a pattern dimension.04-01-2010
20110201207BACKPLANE STRUCTURES FOR SOLUTION PROCESSED ELECTRONIC DEVICES - There is provided a backplane for an organic electronic device. The backplane has a TFT substrate; a multiplicity of electrode structures; and a bank structure defining a multiplicity of pixel openings on the electrode structures. The bank structure has a height adjacent to the pixel opening, h08-18-2011
20110201206METHOD FOR FORMING AMORPHOUS CARBON NITRIDE FILM, AMORPHOUS CARBON NITRIDE FILM, MULTILAYER RESIST FILM, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND STORAGE MEDIUM IN WHICH CONTROL PROGRAM IS STORED - An amorphous carbon film, which has excellent etching resistance and is capable of reducing reflectance when a resist film is exposed to light, is form. A method for manufacturing a semiconductor device includes forming an object film to be etched on a wafer, supplying a process gas containing a CO gas and an N08-18-2011
20090087993METHODS AND APPARATUS FOR COST-EFFECTIVELY INCREASING FEATURE DENSITY USING A MASK SHRINKING PROCESS WITH DOUBLE PATTERNING - Methods and apparatus are provided for forming an array of devices. The invention includes forming a stack of material layers, forming a first hardmask over the plurality of material layers, exposing the first hardmask to ozone mixed with a halogenated additive, forming a protective layer over the first hardmask, forming a second mask on the protective layer shifted relative to the first mask, exposing the second hardmask to ozone mixed with the halogenated additive, and etching the plurality of material layers to remove material not covered by the hardmasks. Numerous other aspects are disclosed.04-02-2009
20090142926Line edge roughness reduction and double patterning - Embodiments of the present invention relate to lithographic processes used in integrated circuit fabrication for improving line edge roughness (LER) and reduced critical dimensions (CD) for lines and/or trenches. Embodiments use the combinations of polarized light lithography, shrink coating processes, and double exposure processes to produce synergetic effects in the formation of trench structures having good resolution, reduced CDs, reduced pitch, and reduced LER in the lines and/or trenches of the patterned interconnect structures.06-04-2009
20090286403METHOD OF FORMING THIN FILM PATTERN FOR SEMICONDUCTOR DEVICE AND APPARATUS FOR THE SAME - A method of forming a thin film pattern includes: forming a thin film on a substrate; forming an amorphous carbon layer including first and second carbon layers on the thin film, wherein the first carbon layer is formed by one of a spin-on method and a plasma enhanced chemical vapor deposition (PECVD) method and the second carbon layer is formed by a physical vapor deposition (PVD) method; forming a hard mask layer on the amorphous carbon layer; forming a PR pattern on the hard mask layer; forming a hard mask pattern by etching the hard mask layer using the PR pattern as an etch mask; forming an amorphous carbon pattern including first and second carbon patterns by etching the amorphous carbon layer using the hard mask pattern as an etch mask; and forming a thin film pattern by etching the thin film using the amorphous carbon pattern.11-19-2009
20090275203METHOD FOR PROCESSING A THIN FILM MICRO DEVICE ON A SUBSTRATE - A method for processing a thin film micro device on a substrate includes: 1) depositing a carbon film on the substrate as a sacrificial layer; 2) photolithographically defining a first predetermined pattern in the carbon film; 3) etching an unwanted portion of the carbon film outside the first predetermined pattern; 4) depositing a structural film including a single or multiple layers of solid state materials; 5) photolithographically defining a second predetermined pattern in the structural film; 6) etching the discarded portion of the structural film outside the second predetermined pattern; 7) selectively removing the remaining portion of the sacrificial carbon film by using a selective etch process gas in a reactor chamber, so that the overlapped portion of the remaining structural element with the first predetermined pattern is suspended above an underneath cavity above the substrate.11-05-2009
20090286402METHOD FOR CRITICAL DIMENSION SHRINK USING CONFORMAL PECVD FILMS - A method and apparatus for forming narrow vias in a substrate is provided. A pattern recess is etched into a substrate by conventional lithography. A thin conformal layer is formed over the surface of the substrate, including the sidewalls and bottom of the pattern recess. The thickness of the conformal layer reduces the effective width of the pattern recess. The conformal layer is removed from the bottom of the pattern recess by anisotropic etching to expose the substrate beneath. The substrate is then etched using the conformal layer covering the sidewalls of the pattern recess as a mask. The conformal layer is then removed using a wet etchant.11-19-2009
20090291561METHOD OF FORMING PATTERN - Disclosed is a method of forming a pattern. A first organic polymer layer is formed on a substrate on which an underlying layer, and then a second organic polymer layer, which has an opening partially exposing the first organic polymer layer, is formed on the first organic polymer layer. Next, a silicon-containing polymer layer is formed on the second organic polymer layer to cover the opening. The silicon-containing polymer layer is oxidized and simultaneously the second organic polymer layer and the first organic polymer layer are ashed by oxygen plasma to form a pattern having an anisotropy-shape. The underlying layer is etched using the silicon-containing polymer layer and the first organic polymer layer as an etching mask to form a pattern.11-26-2009
20090191713METHOD OF FORMING FINE PATTERN USING BLOCK COPOLYMER - Provided is a method of forming a fine pattern using a block copolymer. The method comprises forming a coating layer including a block copolymer having a plurality of repeating units on a substrate. A mold is provided having a first pattern comprising a plurality of ridges and valleys. The first pattern is transferred from the mold into the coating layer. Then, a self-assembly structure is formed comprising a plurality of polymer blocks aligned in a direction guided by the ridges and valleys of the mold thereby rearranging the repeating units of the block copolymer within the coating layer by phase separation while the coating layer is located within the valleys of the mold. A portion of the polymer blocks are removed from among the plurality of polymer blocks and a self-assembly fine pattern of remaining polymer blocks is formed.07-30-2009
20110207331Resist underlayer film forming composition for lithography, containing aromatic fused ring-containing resin - There is provided a resist underlayer film forming composition for lithography, which in order to prevent a resist pattern from collapsing after development in accordance with the miniaturization of the resist pattern, is applied to multilayer film process by a thin film resist, has a lower dry etching rate than resists and semiconductor substrates, and has a satisfactory etching resistance relative to a substrate to be processed in the processing of the substrate. A resist underlayer film forming composition used in lithography process by a multiplayer film, comprises a polymer containing a unit structure having an aromatic fused ring, a unit structure having a protected carboxyl group or a unit structure having an oxy ring. A method of forming a pattern by use of the resist underlayer film forming composition. A method of manufacturing a semiconductor device by utilizing the method of forming a pattern.08-25-2011
20090149027Method of Fabricating an Integrated Circuit - Embodiments of the invention relate to a method of fabricating an integrated circuit, including etching of a layer that includes a high k material in the form of a metal oxide composition, wherein an etchant is used that includes a silicon halogen composition.06-11-2009
20090170330METHOD OF FORMING A MICRO PATTERN OF A SEMICONDUCTOR DEVICE - In a method of forming micro patterns of a semiconductor device, first etch mask patterns are formed over a semiconductor substrate. An auxiliary film is formed over the semiconductor substrate including a surface of the first etch mask patterns. Second etch mask patterns are formed between the auxiliary films formed on sidewalls of the first etch mask patterns. The first etch mask patterns and the second etch mask patterns are formed using the same material. The auxiliary films between the first and second etch mask patterns are removed. Accordingly, more micro patterns can be formed than allowed by the resolution limit of an exposure apparatus while preventing misalignment.07-02-2009
20090286404Method of forming minute patterns in semiconductor device using double patterning - A method of forming minute patterns in a semiconductor device, and more particularly, a method of forming minute patterns in a semiconductor device having an even number of insert patterns between basic patterns by double patterning including insert patterns between a first basic pattern and a second basic pattern which are transversely separated from each other on a semiconductor substrate, wherein a first insert pattern and a second insert pattern are alternately repeated to form the insert patterns, the method includes the operation of performing a partial etching toward the second insert pattern adjacent to the second basic pattern, or the operation of forming a shielding layer pattern, thereby forming the even number of insert patterns.11-19-2009
20080293249In-situ photoresist strip during plasma etching of active hard mask - A method for etching features in a silicon layer is provided. A hard mask layer is formed over the silicon layer. A photoresist layer is formed over the hard mask layer. The hard mask layer is opened. The photoresist layer is stripped by providing a stripping gas; forming a plasma with the stripping gas by providing a high frequency RF power and a low frequency RF power, wherein the low frequency RF power has a power less than 50 watts; and stopping the stripping gas when the photoresist layer is stripped. The opening the hard mask layer and the stripping the photoresist layer are performed in a same chamber.11-27-2008
20080305642METHOD FOR FORMING FINE PATTERN OF SEMICONDUCTOR DEVICE - A method for forming a fine pattern of a semiconductor device comprises forming a deposition pattern including first, second, and third mask patterns over a semiconductor substrate having an underlying layer, side-etching the second mask pattern with the third mask pattern as an etching barrier mask, removing the third mask pattern, forming a spin-on-carbon layer that exposes the upper portion of the second mask pattern, performing an etching process to expose the underlying layer with the spin-on-carbon layer as an etching barrier mask, and removing the spin-on-carbon layer.12-11-2008
20080305641REVERSE MASKING PROFILE IMPROVEMENTS IN HIGH ASPECT RATIO ETCH - A method of improving high aspect ratio etching by reverse masking to provide a more uniform mask height between the array and periphery is presented. A layer of amorphous carbon is deposited over a substrate. An inorganic hard mask is deposited on the amorphous carbon followed by a layer of photodefinable material which is deposited over the array portion of the substrate. The photodefinable material is removed along with the inorganic hard mask overlaying the periphery. A portion of the amorphous carbon layer is etched in the exposed periphery. The inorganic hard mask is removed and normal high aspect ratio etching continues. The amount of amorphous carbon layer remaining in the periphery results in a more uniform mask height between the array and periphery at the end of high aspect ratio etching. The more uniform mask height mitigates twisting at the edge of the array.12-11-2008
20120295445Methods of Fabricating Substrates - A method of fabricating a substrate includes forming spaced first features and spaced second features over a substrate. The first and second features alternate with one another and are spaced relative one another. Width of the spaced second features is laterally trimmed to a greater degree than any lateral trimming of width of the spaced first features while laterally trimming width of the spaced second features. After laterally trimming of the second features, spacers are formed on sidewalls of the spaced first features and on sidewalls of the spaced second features. The spacers are of some different composition from that of the spaced first features and from that of the spaced second features. After forming the spacers, the spaced first features and the spaced second features are removed from the substrate. The substrate is processed through a mask pattern comprising the spacers. Other embodiments are disclosed.11-22-2012
20110207330Method of manufacturing semiconductor device - A sidewall core that is slimmed is formed in a memory cell array area by patterning a polysilicon layer formed over a silicon nitride layer. A silicon oxide layer that at least covers side surfaces of the sidewall core and the polysilicon layer are sequentially formed and an embedded hard mask is formed by etching back the polysilicon layer. Thereafter, the silicon nitride layer within the memory cell array area that does not overlap with the sidewall core or the embedded hard mask and the silicon nitride layer within a peripheral circuit area that overlaps with a positioning monitor mark are exposed by etching the silicon oxide layer, and then the silicon nitride layer that is to be etched is patterned.08-25-2011
20090035944METHODS OF FOR FORMING ULTRA THIN STRUCTURES ON A SUBSTRATE - Methods for forming an ultra thin structure using a method that includes multiple cycles of polymer deposition of photoresist (PDP) process and etching process. The embodiments described herein may be advantageously utilized to fabricate a submicron structure on a substrate having a critical dimension less than 55 nm and beyond. In one embodiment, a method of forming a submicron structure on a substrate may include providing a substrate having a patterned photoresist layer disposed on a film stack into an etch chamber, wherein the film stack includes at least a hardmask layer disposed on a dielectric layer, performing a polymer deposition process to deposit a polymer layer on the pattered photoresist layer, thus reducing a critical dimension of an opening in the patterned photoresist layer, and etching the underlying hardmask layer through the opening having the reduced dimension.02-05-2009
20120064724Methods of Forming a Pattern of Semiconductor Devices - Methods of forming a pattern of a semiconductor device including performing a double patterning process without using an atomic layer deposition (ALD) oxide film are provided. The methods may include forming a mask pattern on a substrate; forming a chemical attach process (CAP) material layer covering at least a portion of the mask pattern; forming a CAP adhesive layer by adhering at least a portion of the CAP material layer to the mask pattern by using a first baking process and a first development process; forming an interlayer covering at least a portion of the mask pattern and the CAP adhesive layer; and removing the mask pattern and the interlayer while allowing the CAP adhesive layer to remain by using a second baking process and a second development process.03-15-2012
20090029555Multi-Step selective etching for cross-point memory - Multi-step selective etching. Etching an unmasked region associated with each layer of a plurality of layers, the plurality of layers comprising a stack, wherein the unmasked region of each of the plurality of layers is etched while exposed to a temperature, a pressure, a vacuum, using a plurality of etchants, wherein at least one of the plurality of etchants comprises an inert gas and oxygen, wherein the etchant oxidizes the at least one layer that can be oxidized such that the etching stops, the plurality of etchants leaving substantially unaffected a masked region associated with each layer of the plurality of layers, wherein two or more of the plurality of layers comprises a memory stack, and preventing corrosion of at least one of the plurality of layers comprising a conductive metal oxide by supplying oxygen to the stack after etching the unmasked region without breaking the vacuum.01-29-2009
20090029554Method of Batch Integration of Low Dielectric Substrates with MMICs - A method for mounting a dielectric substrate to a semiconductor substrate, such as mounting a dielectric antenna substrate to an MMIC semiconductor substrate. The method includes providing a thin dielectric antenna substrate having metallized layers on opposing sides. In one embodiment, carrier wafers are used to handle and maintain the dielectric substrate in a flat configuration as the metallized layers are patterned. The dielectric substrate is sealed to the semiconductor substrate using a low temperature bonding process. In an alternate embodiment, the metallized layers on the dielectric substrate are patterned simultaneously so as to prevent the substrate from curling.01-29-2009
20090163030SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A first silicon containing film, an organic material film, a second silicon containing film are formed. The second silicon containing film is patterned to have a narrow width pattern and a wide width pattern. The organic material film is patterned to have a narrow width pattern and a wide width pattern. A side wall is formed on a side surface of the second silicon containing film and the organic material film by coating with a third silicon containing film. The narrow width pattern of the second silicon containing film is removed by using a mask that covers the second silicon containing film patterned to have a wide width pattern and the side wall. Finally, the organic material film is removed.06-25-2009
20090163029METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device has forming a first nitride layer over a substrate, forming a first oxide layer on the first nitride layer, forming a second nitride layer on the first oxide layer, forming a photoresist layer over the second nitride layer, forming a opening in the photoresist layer, etching the second nitride layer using the photoresist layer as a mask such that the opening is reached to the first oxide layer, etching the first oxide layer using the second nitride layer as a mask such that the opening is reached to the first nitride layer, etching the first oxide layer such that bottom zone of the opening is increased in diameter, and etching the first nitride layer using the first oxide layer as a mask such that the opening is reached to the substrate thereby to form contact hole reaching to the substrate.06-25-2009
20090137126METHOD OF FORMING A SPACER - A sacrificial layer and wet etch are used to form a sidewall spacer so as to prevent damage to the structure on which the spacer is formed and to the underlying substrate as well. Once the structure is formed on the substrate a spacer formation layer is formed to cover the structure, and a sacrificial layer is formed on the spacer formation layer. The sacrificial layer is wet etched to form a sacrificial layer pattern on that portion of the spacer formation layer extending along a sidewall of the structure. The spacer is formed on the sidewall of the structure by wet etching the spacer formation layer using the sacrificial layer pattern as a mask.05-28-2009
20090142927Fabricating sub-lithographic contacts - A small critical dimension element, such as a heater for an ovonic unified memory, may be formed within a pore by using successive sidewall spacers. The use of at least two successive spacers enables the limitations imposed by lithography and the limitations imposed by bread loafing to be overcome to provide reduced critical dimension elements.06-04-2009
20090191712MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - In one aspect of the present invention, a method of manufacturing a semiconductor device may include forming a first film on an amorphous silicon layer to be patterned, the first film and the amorphous film having a line-and-space ratio of approximately 3:1, sliming down, after processing the first film, a line portion of the pattern from both longitudinal sides of the line portion until the width of the line portion is reduced to approximately one third, reforming a part of the amorphous silicon layer where the first film is not provided such that reformed part has different etching ratio, and removing the first film and the amorphous silicon layer other than reformed part.07-30-2009
20120171868RESIST UNDERLAYER FILM COMPOSITION AND PATTERNING PROCESS USING THE SAME - There is disclosed A resist underlayer film composition, wherein the composition contains a polymer obtained by condensation of, at least, one or more compounds represented by the following general formulae (1-1) and/or (1-2), one or more kinds of a compound represented by the following general formula (2), and one or more kinds of a compound, represented by the following general formula (3), and/or an equivalent body thereof. There can be provided an underlayer film composition, especially for a trilayer resist process, that can form an underlayer film having reduced reflectance, (namely, an underlayer film having optimum n-value and k-value as an antireflective film), excellent filling-up properties, high pattern-antibending properties, and not causing line fall or wiggling after etching especially in a high aspect line that is thinner than 60 nm, and a patterning process using the same.07-05-2012
20090253267REVERSE MASKING PROFILE IMPROVEMENTS IN HIGH ASPECT RATIO ETCH - A method of improving high aspect ratio etching by reverse masking to provide a more uniform mask height between the array and periphery is presented. A layer of amorphous carbon is deposited over a substrate. An inorganic hard mask is deposited on the amorphous carbon followed by a layer of photodefinable material which is deposited over the array portion of the substrate. The photodefinable material is removed along with the inorganic hard mask overlaying the periphery. A portion of the amorphous carbon layer is etched in the exposed periphery. The inorganic hard mask is removed and normal high aspect ratio etching continues. The amount of amorphous carbon layer remaining in the periphery results in a more uniform mask height between the array and periphery at the end of high aspect ratio etching. The more uniform mask height mitigates twisting at the edge of the array.10-08-2009
20090258501Double patterning method - A method of making a device includes forming a first photoresist layer over an underlying layer, patterning the first photoresist layer to form a first photoresist pattern, rendering the first photoresist pattern insoluble to a solvent, forming a second photoresist layer over the first photoresist pattern, patterning the second photoresist layer to form a second photoresist pattern over the underlying layer, and etching the underlying layer using both the first and the second photoresist patterns as a mask.10-15-2009
20090258499METHOD OF FORMING AT LEAST AN OPENING USING A TRI-LAYER STRUCTURE - A method of forming openings is disclosed. A substrate is first provided, and the tri-layer structure is formed on the substrate. The tri-layer structure includes a bottom photoresist layer, a silicon-containing layer and a top photoresist layer form bottom to top. Subsequently, the top photoresist layer is patterned, and the silicon-containing layer is etched by utilizing the top photoresist layer as an etching mask to partially expose the bottom photoresist layer. Next, the partially exposed bottom photoresist layer is etched through two etching steps in turn by utilizing the patterned silicon-containing layer as an etching mask. The first etching step includes an oxygen gas and at least one non-carbon-containing halogen-containing gas, while the second etching step includes at least one halogen-containing gas. The substrate is thereafter etched by utilizing the patterned bottom photoresist layer as an etching mask to form at least an opening in the substrate.10-15-2009
20090053899METHOD OF PATTERN FORMATION IN SEMICONDUCTOR FABRICATION - Provided is a method of fabricating a semiconductor device. The method includes providing a substrate, forming a photo acid generator (PAG) layer on the substrate, exposing the PAG layer to radiation, and forming a photoresist layer on the exposed PAG layer. The exposed PAG layer generates an acid. The acid decomposes a portion of the formed photoresist layer. In one embodiment, the PAG layer includes organic BARC. The decomposed portion of the photoresist layer may be used as a masking element.02-26-2009
20130122710CARBAZOLE NOVOLAK RESIN - There is provided a resist underlayer film having heat resistance that is used for a lithography process in the production of semiconductor devices, and a high refractive index film having transparency that is used for an electronic device. A polymer comprising a unit structure of Formula (1):05-16-2013
20100261353WAFER PLANARITY CONTROL BETWEEN PATTERN LEVELS - A method for controlling the flatness of a wafer between lithography pattern levels. A first lithography step is performed on a topside semiconductor surface of the wafer. Reference curvature information is obtained for the wafer. The reference curvature is other than planar. At least one process step is performed that results in a changed curvature relative to the reference curvature. The changed curvature information is obtained for the wafer. Stress on a bottomside surface of the wafer is modified that reduces a difference between the changed curvature and the reference curvature. A second lithography step is performed on the topside semiconductor surface while the modified stress distribution is present.10-14-2010
20110059613MASK PATTERN FOR SEMICONDUCTOR DEVICE FABRICATION, METHOD OF FORMING THE SAME, AND METHOD OF FABRICATING FINELY PATTERNED SEMICONDUCTOR DEVICE - Provided are a mask pattern including a silicon-containing self-assembled molecular layer, a method of forming the same, and a method of fabricating a semiconductor device. The mask pattern includes a resist pattern formed on a semiconductor substrate and the self-assembled molecular layer formed on the resist pattern. The self-assembled molecular layer has a silica network formed by a sol-gel reaction. To form the mask pattern, first, the resist pattern is formed with openings on an underlayer covering the substrate to expose the underlayer to a first width. Then, the self-assembled molecular layer is selectively formed only on a surface of the resist pattern to expose the underlayer to a second width smaller than the first width. The underlayer is etched by using the resist pattern and the self-assembled molecular layer as an etching mask to obtain a fine pattern.03-10-2011
20120196444METHOD FOR THE SELECTIVE DELIVERY OF MATERIAL TO A SUBSTRATE - A method of selective delivery of material to locations on a substrate using a continuous stream deposition device to deposit the material at selected locations on the substrate. This is achieved by creating a mask with an opening, locating the mask over the substrate and depositing the material through the opening onto the substrate. When locating the mask, over the substrate, a portion of the substrate is exposed through the opening and when the continuous stream deposition device is moved relative to the substrate and the mask, the continuous stream deposition device follows a path relative to the mask which intersects the opening. While the continuous stream deposition device moves, it discharges a continuous stream comprising the material to be delivered, to deposit the material through the mask at a discrete location on the substrate, at the intersection of the opening and the path of the continuous stream deposition device. Alternatively the mask may be dispensed with and two materials deposited on two intersecting paths whereby at the intersections the two materials react.08-02-2012
20100136792SELF-ALIGNED MULTI-PATTERNING FOR ADVANCED CRITICAL DIMENSION CONTACTS - Embodiments of the present invention pertain to methods of forming patterned features on a substrate having a reduced pitch in two dimensions as compared to what is possible using standard photolithography processing techniques using a single high-resolution photomask. A spacer layer is formed over a two-dimensional square grid of cores with a thickness chosen to leave a dimple at the center of four cores on the corners of a square. The spacer layer is etched back to reveal the substrate at the centers of the square. Removing the core material results in double the pattern density of the lithographically defined grid of cores. The regions of exposed substrate may be filled again with core material and the process repeated to quadruple the pattern density.06-03-2010
20120129352SILICON-CONTAINING FILM, RESIN COMPOSITION, AND PATTERN FORMATION METHOD - A pattern-forming method includes forming a silicon-containing film on a substrate, the silicon-containing film having a mass ratio of silicon atoms to carbon atoms of 2 to 12. A shape transfer target layer is formed on the silicon-containing film. A fine pattern is transferred to the shape transfer target layer using a stamper that has a fine pattern to form a resist pattern. The silicon-containing film and the substrate are dry-etched using the resist pattern as a mask to form a pattern on the substrate in nanoimprint lithography. According to another aspect of the invention, a silicon-containing film includes silicon atoms and carbon atoms. A mass ratio of silicon atoms to carbon atoms is 2 to 12. The silicon-containing film is used for a pattern-forming method employed in nanoimprint lithography.05-24-2012
20120129353METHOD FOR PATTERN FORMATION, METHOD AND COMPOSITION FOR RESIST UNDERLAYER FILM FORMATION, AND RESIST UNDERLAYER FILM - Provided by the present invention is a method including: (1) forming a resist underlayer film on the upper face side of a substrate to be processed using a composition for forming a resist underlayer film, the composition containing (A) a compound having a group represented by the following formula (1); (2) forming a resist coating film by applying a resist composition on the resist underlayer film; (3) exposing the resist coating film by selectively irradiating the resist coating film with a radiation; (4) forming a resist pattern by developing the exposed resist coating film; and (5) forming a predetermined pattern on the substrate to be processed by sequentially dry etching the resist underlayer film and the substrate using the resist pattern as a mask.05-24-2012
20120142195COMPOSITION FOR FORMING RESIST UNDERLAYER FILM FOR LITHOGRAPHY INCLUDING RESIN CONTAINING ALICYCLIC RING AND AROMATIC RING - There is provided a resist underlayer film having both heat resistance and etching selectivity. A composition for forming a resist underlayer film for lithography, comprising a reaction product (C) of an alicyclic epoxy polymer (A) with a condensed-ring aromatic carboxylic acid and monocyclic aromatic carboxylic acid (B). The alicyclic epoxy polymer (A) may include a repeating structural unit of Formula (1):06-07-2012
20120142193RESIST UNDERLAYER FILM COMPOSITION AND PATTERNING PROCESS USING THE SAME - There is disclosed a resist underlayer film composition, wherein the composition contains a polymer obtained by condensation of, at least, one or more compounds represented by the following general formula (1-1) and/or general formula (1-2), and one or more kinds of compounds and/or equivalent bodies thereof represented by the following general formula (2). There can be provided an underlayer film composition, especially for a trilayer resist process, that can form an underlayer film having reduced reflectance, (namely, an underlayer film having optimum n-value and k-value), excellent filling-up properties, high pattern-antibending properties, and not causing line fall or wiggling after etching especially in a high aspect line that is thinner than 60 nm, and a patterning process using the same.06-07-2012
20100022090RESIST UNDERLAYER FILM FORMING COMPOSITION FOR LITHOGRAPHY, CONTAINING AROMATIC FUSED RING-CONTAINING RESIN - There is provided a resist underlayer film forming composition for lithography, which in order to prevent a resist pattern from collapsing after development in accordance with the miniaturization of the resist pattern, is applied to multilayer film process by a thin film resist, has a lower dry etching rate than resists and semiconductor substrates, and has a satisfactory etching resistance relative to a substrate to be processed in the processing of the substrate. A resist underlayer film forming composition used in lithography process by a multiplayer film, comprises a polymer containing a unit structure having an aromatic fused ring, a unit structure having a protected carboxyl group or a unit structure having an oxy ring. A method of forming a pattern by use of the resist underlayer film forming composition. A method of manufacturing a semiconductor device by utilizing the method of forming a pattern.01-28-2010
20090246960METHOD OF FABRICATING A SEMICONDUCTOR DEVICE - In a method of fabricating a semiconductor device, an additive gas is mixed with an etching gas to reduce a fluorine ratio of the etching gas. The etching gas having a reduced fluorine rate is utilized in the process for etching a nitride layer formed on an oxide layer to prevent the oxide layer formed below the nitride layer from being etched along with the nitride layer. The method comprises primarily etching an exposed charge storage layer using an etching gas; and secondarily etching the charge storage layer using the etching gas under a condition that a ratio of fluorine contained in the etching gas utilized in the secondary etching step is less than a ratio of fluorine contained in the etching gas utilized in the primary etching step. Thus, the tunnel insulating layer formed below the charge storage layer is not damaged when the charge storage layer is patterned.10-01-2009
20090181543METHOD OF FORMING A PATTERN OF A SEMICONDUCTOR DEVICE - In a method of forming patterns of a semiconductor device, a to-be-etched layer is formed on a semiconductor substrate. First etch mask patterns are formed over the to-be-etched layer. An auxiliary layer is formed on the first etch mask patterns and the to-be-etched layer. The auxiliary layer is thicker on upper sidewalls of the first etch mask patterns than on lower sidewalls thereof. Second etch mask patterns are formed in concave portions of the auxiliary layer. The auxiliary layer between the first and second etch mask patterns is removed. The to-be-etched layer is patterned using the first and second etch mask patterns as an etch mask.07-16-2009
20090111272METHOD OF FORMING STRAIN-CAUSING LAYER FOR MOS TRANSISTORS AND PROCESS FOR FABRICATING STRAINED MOS TRANSISTORS - A method of forming a strain-causing layer for MOS transistors is provided, which is applied to a substrate having a plurality of gate structures of the MOS transistors thereon. A non-conformal stressed film that is thicker on the gate structures than between the gate structures is formed over the substrate. The non-conformal stressed film is then etched, without an etching mask thereon, to remove portions thereof between the gate structures and disconnect the stressed film between the gate structures. At least one extra stressed film may be further formed over the substrate, wherein each extra stressed film has the same type of stress as the above stressed film and is connected or disconnected between the gate structures.04-30-2009
20090111273Method for Manufacturing Semiconductor Device - The invention defines a pillar pattern or an island pattern by forming a contact hole and filling the contact hole with a hard mask material by using a spacer formation process, so that the mask pattern formation process margin for island (e.g., pillar) pattern formation is increased. Accordingly, the yield and reliability of the formation process of a semiconductor device are improved.04-30-2009
20100311244DOUBLE-EXPOSURE METHOD - The present invention discloses a double-exposure method comprising a first lithography process and a second lithography process. Between the first and the second lithography process, coat Resolution Enhancement Lithography Assisted by Chemical Shrink (RELACS) material on the first photoresist pattern, promote thermal crosslinking reaction at the interface between the RELACS materials and the first photoresist pattern; afterwards, remove the RELACS material which does not crosslink with the first photoresist pattern. This method not only realizes higher lithography resolution, but also avoids the adverse effects of the second exposure on the first photoresist pattern in double-exposure technology.12-09-2010
20110008968METHOD AND MATERIAL FOR FORMING A DOUBLE EXPOSURE LITHOGRAPHY PATTERN - A method of lithography patterning includes forming a first material layer on a substrate; forming a first patterned resist layer including at least one opening therein on the first material layer; forming a second material layer on the first patterned resist layer and the first material layer; forming a second patterned resist layer including at least one opening therein on the second material layer; and etching the first and second material layers uncovered by the first and second patterned resist layers.01-13-2011
20110008969FREQUENCY DOUBLING USING SPACER MASK - A method for fabricating a semiconductor mask is described. A semiconductor stack having a sacrificial mask and a spacer mask is first provided. The sacrificial mask is comprised of a series of lines and the spacer mask has spacer lines adjacent to the sidewalls of the series of lines. Next, the spacer mask is cropped. Finally, the sacrificial mask is removed to provide a cropped spacer mask. The cropped spacer mask doubles the frequency of the series of lines of the sacrificial mask.01-13-2011
20100178772METHOD OF FABRICATING HIGH-K METAL GATE DEVICES - The present disclosure provides a method for fabricating a semiconductor device. The method includes providing a semiconductor substrate having a first region and a second region, forming a high-k dielectric layer over the semiconductor substrate, forming a first metal layer and a first silicon layer by an in-situ deposition process, patterning the first silicon layer to remove a portion overlying the second region, patterning the first metal layer using the patterned first silicon layer as a mask, and removing the patterned first silicon layer including applying a solution. The solution includes a first component having an [F—] concentration greater than 0.01 M, a second component configured to adjust a pH of the solution from about 4.3 to about 6.7, and a third component configured to adjust a potential of the solution to be greater than −1.4 volts.07-15-2010
20100178773METHOD OF FORMING SEMICONDUCTOR DEVICES EMPLOYING DOUBLE PATTERNING - A first material film is formed on a substrate. Linear second material film patterns are formed on the first material film. Spacer patterns are formed on sidewalls of the second material film patterns, and the second material film patterns are removed to expose portions of the first material film between the spacer patterns. The exposed portions of the first material film are removed to form first material film patterns. Third material film patterns are formed in trenches defined by the first material film patterns. Adjacent first portions of the second material film patterns proximate ends of the second material film patterns are separated by a distance less than twice a width of the individual spacer patterns. In some embodiments, the distance separating the adjacent first portions of the second material film patterns is greater than a minimum feature size, and a width of the individual spacer patterns is approximately equal to the minimum feature size.07-15-2010
20110111599METHOD FOR PATTERNED ETCHING OF SELECTED MATERIAL - Surface processing in which the area to be processed is restricted to a predetermined pattern, can be achieved by: (a) providing a layer of a first reagent over a region of the surface to be processed which at least covers an area of the predetermined pattern; (b) providing one or more further reagents which are further reagents required for the processing of the surface; and (c) applying at least one of the further reagents over the region to be processed according to the predetermined pattern; such that the first reagent acts with the one or more of the further reagents to process the surface only in the area of the predetermined pattern. The process is particularly applicable to etching where an etchant having two or more components is used. In that case at least a first etchant component is applied over the surface and at least one further etchant component is applied in the predetermined pattern.05-12-2011
20110117745METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device according to an embodiment includes processing a second film 05-19-2011
20110244690COMBINATORIAL PLASMA ENHANCED DEPOSITION AND ETCH TECHNIQUES - According to various embodiments of the disclosure, an apparatus and method for enhanced deposition and etch techniques is described, including a pedestal, the pedestal having at least two electrodes embedded in the pedestal, a showerhead above the pedestal, a plasma gas source connected to the showerhead, wherein the showerhead is configured to deliver plasma gas to a processing region between the showerhead and the substrate and a power source operably connected to the showerhead and the at least two electrodes with plasma being substantially contained in an area which corresponds with one electrode of the at least two electrodes.10-06-2011
20110086512SEMICONDUCTOR DEVICE FABRICATION METHOD AND SEMICONDUCTOR DEVICE - A resist pattern (04-14-2011
20110250757METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A coating film is formed on a member to be etched, which includes an amorphous carbon film and a silicon oxynitride film, by a spin coating method; a sidewall core is formed by pattering the coating film; a silicon oxide film is formed to cover at least the side surface of the sidewall core; and an organic anti-reflection film is formed on the silicon oxide film by a spin coating method. Thereafter, an embedded mask is formed to cover concave portions of the silicon oxide film by etching the organic anti-reflection film; exposed is a portion of the member to be etched which does not overlap the sidewall core or the embedded mask by etching the silicon oxide film; and the member to be etched is etched. Thus, it is possible to obtain a pattern with a size less than the photolithography resolution limit.10-13-2011
20110151672Method of Etching Oxide Layer and Nitride Layer - An exemplary method of patterning oxide layer and removing residual nitride includes steps of forming a first oxide layer, a nitride layer, a second oxide layer and a complex hard mask on a substrate in turn. The first oxide layer covers an insulating structure. The second oxide layer, the complex hard mask and the nitride layer are etched by utilizing a patterned photoresist as an etching mask, so as to expose the first oxide layer. In addition, the part of the nitride layer covering the insulating structure can be further removed. Accordingly, the present invention can effectively control layout patterns of material layers and doped regions and thereby can improve the performance of a narrow width device.06-23-2011
20100015808Impact sensor and method for manufacturing the impact sensor - An impact sensor comprises a silicon substrate; an insulating layer formed over the silicon substrate; a plurality of beams having flexibility that are formed of conductive silicon material; a fixing portion to fix a fixed end of each of the beams, the fixing portion being formed of conductive silicon material; a fixed end line at whose one end is formed the fixing portion, the fixed end line being formed of conductive silicon material on the insulating layer; and a free end line having a pressing portion that faces a free end of each of the beams via a space, the free end line being formed of conductive silicon material on the insulating layer. Respective beam widths, each measured in a direction orthogonal to a length direction joining the fixed end and the free end, of the plurality of beams are set different from each other, thus reducing the space occupied by the sensor.01-21-2010
20120244711SIDEWALL IMAGE TRANSFER PROCESS - An improved method of performing sidewall spacer imager transfer is presented. The method includes forming a set of sidewall spacers next to a plurality of mandrels, the set of sidewall spacers being directly on top of a hard-mask layer; transferring image of at least a portion of the set of sidewall spacers to the hard-mask layer to form a device pattern; and transferring the device pattern from the hard-mask layer to a substrate underneath the hard-mask layer.09-27-2012
20100068885SIDEWALL FORMING PROCESSES - An etch layer underlying a patterned photoresist mask is provided. A plurality of sidewall forming processes are performed. Each sidewall forming process comprises depositing a protective layer on the patterned photoresist mask by performing multiple cyclical depositions. Each cyclical deposition involves at least a depositing phase for depositing a deposition layer over surfaces of the patterned photoresist mask and a profile shaping phase for shaping vertical surfaces in the deposition layer. Each sidewall forming process further comprises a breakthrough etch for selectively etching horizontal surfaces of the protective layer with respect to vertical surfaces of the protective layer. Afterwards, the etch layer is etched to form a feature having a critical dimension that is less than the critical dimension of the features in the patterned photoresist mask.03-18-2010
20100062605METHOD OF FORMING A CONTACT HOLE FOR A SEMICONDUCTOR DEVICE - Forming contact holes of a semiconductor device includes forming a reaction layer that is provided with a reaction pattern on a semiconductor substrate. Subsequently, a self-assembled monolayer is formed by injecting a polymer from a functional group that is capable of being chemically bonded to the reaction pattern. A coating layer is then formed on substantially all of the structure that includes the self-assembled monolayer. Afterwards, the contact holes are formed on the semiconductor substrate by performing an etching process.03-11-2010
20090215272DOUBLE MASK SELF-ALIGNED DOUBLE PATTERNING TECHNOLOGY (SADPT) PROCESS - A method for providing features in an etch layer is provided by forming an organic mask layer over the inorganic mask layer, forming a silicon-containing mask layer over the organic mask layer, forming a patterned mask layer over the silicon-containing mask layer, etching the silicon-containing mask layer through the patterned mask, depositing a polymer over the etched silicon-containing mask layer, depositing a silicon-containing film over the polymer, planarizing the silicon-containing film, selectively removing the polymer leaving the silicon-containing film, etching the organic layer, and etching the inorganic layer.08-27-2009
20110076850METHOD OF FABRICATING SEMICONDUCTOR DEVICE - In one embodiment, a method of fabricating a semiconductor device is disclosed. The method can selectively form a core material made of carbon-containing material above a workpiece member. Additionally, the method can form a protective film made of material containing no oxygen so as to cover an upper surface and side faces of the core material. Furthermore, the method can form an oxide film so as to cover the core material and the workpiece member via the protective film. Moreover, the method can shape at least the oxide film into a sidewall in a position lateral to the core material. In addition, the method can etch the workpiece member by using the sidewall as a mask after removal of at least the core material, thereby transferring a pattern of the sidewall to the workpiece member.03-31-2011
20110076851METHOD FOR FABRICATING FINE PATTERN IN SEMICONDUCTOR DEVICE - A method for fabricating a fine pattern in a semiconductor device includes forming a first photoresist over a substrate where an etch target layer is formed, doping at least one impurity selected from group III elements and group V elements, of the periodic table, into the first photoresist, forming a photoresist pattern over the first photoresist, performing a dry etching process using the photoresist pattern to expose the first photoresist, etching the first photoresist by an oxygen-based dry etching to form a first photoresist pattern where a doped region is oxidized, and etching the etch target layer using the first photoresist pattern as an etch barrier.03-31-2011
20120202350METHOD FOR POSITIONING SPACERS IN PITCH MULTIPLICATION - Multiple pitch-multiplied spacers are used to form mask patterns having features with exceptionally small critical dimensions. One of each pair of spacers formed mandrels is removed and alternating layers, formed of two mutually selectively etchable materials, are deposited around the remaining spacers. Layers formed of one of the materials are then etched, leaving behind vertically-extending layers formed of the other of the materials, which form a mask pattern. Alternatively, instead of depositing alternating layers, amorphous carbon is deposited around the remaining spacers followed by a plurality of cycles of forming pairs of spacers on the amorphous carbon, removing one of the pairs of spacers and depositing an amorphous carbon layer. The cycles can be repeated to form the desired pattern. Because the critical dimensions of some features in the pattern can be set by controlling the width of the spaces between spacers, exceptionally small mask features can be formed.08-09-2012
20080242097Selective deposition method - The invention refers to a selective deposition method. A substrate comprising at least one structured surface is provided. The structured surface comprises a first area and a second area. The first area is selectively passivated regarding reactants of a first deposition technique and the second area is activated regarding the reactants the first deposition technique. A passivation layer on the second area is deposited via the first deposition technique. The passivation layer is inert regarding a precursors selected from a group of oxidizing reactants. A layer is deposited in the second area using a second atomic layer deposition technique as second deposition technique using the precursors selected form the group of oxidizing reactants.10-02-2008
20080242098Method for forming pattern in semiconductor device - A method for forming a pattern in a semiconductor device includes forming an etch target layer over a substrate, forming a hard mask pattern over the etch target layer, and etching the etch target layer using the hard mask pattern as an etch mask and a gas mixture including a fluorine (F)-based gas and a bromine (Br)-based gas as an etch gas to form a target pattern.10-02-2008
20090023292PHOTOELECTRIC CONVERSION DEVICE AND METHOD FOR PRODUCING PHOTOELECTRIC CONVERSION DEVICE - A photoelectric conversion device according to the present invention has a plurality of photoreceiving portions provided in a substrate, an interlayer film overlying the photoreceiving portion, a large refractive index region which is provided so as to correspond to the photoreceiving portion and has a higher refractive index than the interlayer film, and a layer which is provided in between the photoreceiving portion and the large refractive index region, and has a lower etching rate than the interlayer film, wherein the layer of the lower etching rate is formed so as to cover at least the whole surface of the photoreceiving portion. In addition, the layer of the lower etching rate has a refractive index in between the refractive indices of the large refractive index region and the substrate. Such a configuration can provide the photoelectric conversion device which inhibits the lowering of the sensitivity and the variation of the sensitivity among picture elements.01-22-2009
20100068886METHOD OF FABRICATING A DIFFERENTIAL DOPED SOLAR CELL - A method of fabricating a differential doped solar cell is described. The method includes the following steps. First, a substrate is provided. A doping process is conducted thereon to form a doped layer. A heavy doping portion of the doped layer is partially or fully removed. Subsequently, an anti-reflection coating layer is formed thereon. A metal conducting paste is printed on the anti-reflection coating layer and is fired to form the metal electrodes for the solar cell.03-18-2010
20090317977MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE - A manufacturing method for a semiconductor device includes: forming a first deposition film on a surface of a member in a chamber configured to perform plasma etching of a wafer, by introducing a first seasoning gas into the chamber; forming a second deposition film on the first deposition film to coat the first deposition film by introducing a second seasoning gas into the chamber; loading the wafer into the chamber; and performing plasma etching of the wafer.12-24-2009
20090317978MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - In one aspect of the present invention, a method of manufacturing semiconductor device may include forming a second core on a member to be processed, and a first core on the second core, the second core located below the first core and having a width larger than that of the first core, forming a coating film on a top surface and side surfaces of the first core, and a top surface and side surfaces of the second core, processing the coating film into sidewall masks by partially removing the coating film in a manner that portions of the coating film, which are located on the side surfaces of the first and second cores, are left remaining, etching the first and second cores by using the sidewall masks as a mask so as to remove the first core and portions of the second core which are not covered with the sidewall masks from above, so that an etching mask including the sidewall masks and portions of the second core which remain directly below the sidewall masks is formed, and etching the member by using the etching mask as a mask, so that the member is patterned.12-24-2009
20090317976ETCHING SYSTEM AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - An etching system includes: a vacuum chamber; a stage for mounting a workpiece, the stage being disposed within the vacuum chamber; a first electrode located within the vacuum chamber and above the stage; a second located between the first electrode and a ceiling of the vacuum chamber; a gas supply for introducing a process gas into the vacuum chamber; a variable capacitance element connected to the second electrode; and a radio frequency power supply connected to the first electrode and connected through the variable capacitance element to the second electrode. The radio frequency power supply supplies radio frequency power to the first and second electrodes to produce an inductively coupled plasma in the process gas within the vacuum chamber.12-24-2009
20080280449SELF-ALIGNED DIELECTRIC CAP - A method of forming a dielectric layer includes providing a substrate that has a copper region and a non-copper region. The substrate is etched to remove any copper oxides from the copper region. A dielectric cap is then selectively formed over the copper region of the substrate so that little or no dielectric cap is formed over the non-copper region of the substrate.11-13-2008
20110256727METHOD OF FORMING SEMICONDUCTOR PATTERNS - Semiconductor patterns are formed by performing trimming simultaneously with the process of depositing the spacer oxide. Alternatively, a first part of the trimming is performed in-situ, immediately before the spacer oxide deposition process in the same chamber in which the spacer oxide deposition is performed whereas a second part of the trimming is performed simultaneously with the process of depositing the spacer oxide. Thus, semiconductor patterns are formed reducing PR footing during PR trimming with direct plasma exposure.10-20-2011
20100285668TECHNIQUE FOR COMPENSATING FOR A DIFFERENCE IN DEPOSITION BEHAVIOR IN AN INTERLAYER DIELECTRIC MATERIAL - By selectively providing a buffer layer having an appropriate thickness, height differences occurring during the deposition of an SACVD silicon dioxide may be reduced during the formation of an interlayer dielectric stack of advanced semiconductor devices. The buffer material may be selectively provided after the deposition of contact etch stop layers of both types of internal stress or may be provided after the deposition of one type of dielectric material and may be used during the subsequent patterning of the other type of dielectric stop material as an efficient etch stop layer.11-11-2010
20090197417METHOD FOR FORMING SPACERS OF DIFFERENT SIZES - A method for forming spacers of different sizes includes the following steps. First a substrate is provided, which has a first element, a second element, a first material layer and a second material layer thereon. A first dry etching is performed to remove part of the second material layer to form a first spacer by the first element and to form a second side wall by the second element, so that the first material layer between the first spacer and the second side wall is exposed to become a damaged first material layer. A trimming procedure is performed to trim the damaged first material layer. A mask is used to cover the first element, the first spacer and part of the first material layer then a wet etching is performed to remove the second side wall.08-06-2009
20120309202METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, a method for manufacturing a semiconductor device, includes forming a mask film on a base material. The base material includes a first portion made of a first material and a second portion made of a second material. The mask film includes a third portion located immediately above the first portion and made of a third material and a fourth portion located immediately above the second portion and made of a fourth material. The mask film has an opening formed in both the third portion and the fourth portion.12-06-2012
20100190348Manufacturing method of semiconductor substrate and substrate processing apparatus - A first processing gas containing a first element and a second processing gas containing a second element are alternately supplied to a surface of a substrate placed in a processing chamber, to thereby form a first thin film, and a second processing gas and a third processing containing the first element and different from the first processing gas are alternately supplied, to thereby form a second thin film on the first thin film, having the same element component as that of the first thin film.07-29-2010
20110189859Method of Etching Oxide Layer and Nitride Layer - An exemplary method of etching an oxide layer and a nitride layer is provided. In particular, a substrate is provided. A surface of the substrate has an isolating structure projecting therefrom. A first oxide layer, a nitride layer and a second oxide layer are sequentially provided on the surface of the substrate, wherein the first oxide layer is uncovered on the isolating structure, the nitride layer is formed overlying the first oxide layer, and the second oxide layer is formed overlying the nitride layer. An isotropic etching process is performed by using an etching mask unmasking the isolating structure, and thereby removing the unmasked portion of the second oxide layer and the unmasked portion of the nitride layer and further exposing sidewalls of the isolating structure. The unmasked portion of the first oxide layer generally is partially removed due to over-etching.08-04-2011
20100022089Method for manufacturing semiconductor device using quadruple-layer laminate - There is provided a laminate used as an underlayer layer for a photoresist in a lithography process of a semiconductor device and a method for manufacturing a semiconductor device by using the laminate. The method comprising: laminating each layer of an organic underlayer film (layer A), a silicon-containing hard mask (layer B), an organic antireflective film (layer C) and a photoresist film (layer D) in this order on a semiconductor substrate. The method also comprises: forming a resist pattern in the photoresist film (layer D); etching the organic antireflective film (layer C) with the resist pattern; etching the silicon-containing hard mask (layer B) with the patterned organic antireflective film (layer C); etching the organic underlayer film (layer A) with the patterned silicon-containing hard mask (layer B); and processing the semiconductor substrate with the patterned organic underlayer film (layer A).01-28-2010
20110117746COATING COMPOSITION AND PATTERN FORMING METHOD - It is an object to provide a coating composition applicable to “reversal patterning” and suitable for forming a film covering a resist pattern. The object is accomplished by a coating composition for lithography comprising an organopolysiloxane, a solvent containing the prescribed organic solvent as a main component, and a quaternary ammonium salt or a quaternary phosphonium salt; or a coating composition for lithography comprising a polysilane, a solvent containing the prescribed organic solvent as a main component, and at least one additive selected from a group consisting of a crosslinking agent, a quaternary ammonium salt, a quaternary phosphonium salt, and a sulfonic acid compound, wherein the polysilane has, at a terminal thereof, a silanol group or a silanol group together with a hydrogen atom.05-19-2011
20080299775GAPFILL EXTENSION OF HDP-CVD INTEGRATED PROCESS MODULATION SIO2 PROCESS - Methods are disclosed for depositing a silicon oxide film on a substrate disposed in a substrate processing chamber. The substrate has a gap formed between adjacent raised surfaces. A silicon-containing gas, an oxygen-containing gas, and a fluent gas are flowed into the substrate processing chamber. A high-density plasma is formed from the silicon-containing gas, the oxygen-containing gas, and the fluent gas. A first portion of the silicon oxide film is deposited using the high-density plasma at a deposition rate between 900 and 6000 Å/min and with a deposition/sputter ratio greater than 30. The deposition/sputter ratio is defined as a ratio of a net deposition rate and a blanket sputtering rate to the blanket sputtering rate. Thereafter, a portion of the deposited first portion of the silicon oxide film is etched. A second portion of the silicon oxide film is deposited over the etched portion of the silicon oxide film.12-04-2008
20100099263NF3/H2 REMOTE PLASMA PROCESS WITH HIGH ETCH SELECTIVITY OF PSG/BPSG OVER THERMAL OXIDE AND LOW DENSITY SURFACE DEFECTS - A method and apparatus for selectively etching doped semiconductor oxides faster than undoped oxides. The method comprises applying dissociative energy to a mixture of nitrogen trifluoride and hydrogen gas remotely, flowing the activated gas toward a processing chamber to allow time for charged species to be extinguished, and applying the activated gas to the substrate. Reducing the ratio of hydrogen to nitrogen trifluoride increases etch selectivity. A similar process may be used to smooth surface defects in a silicon surface.04-22-2010
20120302069METHOD OF PATTERNED IMAGE REVERSAL - A method of forming a reverse image pattern on a semiconductor base layer is disclosed. The method comprises depositing a transfer layer of amorphous carbon on the semiconductor base layer, depositing a resist layer on the transfer layer, creating a first pattern in the resist layer, creating the first pattern in the transfer layer, removing the resist layer, depositing a reverse mask layer, planarizing the reverse mask layer, and removing the transfer layer, thus forming a second pattern that is a reverse image of the first pattern.11-29-2012
20110065278METHOD FOR FABRICATING PELLICLE OF EUV MASK - A method for fabricating a pellicle of an EUV mask is provided. An insulation layer is formed over a silicon substrate, and a mesh is formed over the insulation layer. A frame exposing a rear surface of the insulation layer is formed by selectively removing a center portion of a rear surface of the silicon substrate. A membrane layer is deposited over the mesh and an exposed top surface of the insulation layer which is adjacent to the mesh. A rear surface of the membrane layer is exposed by selectively removing the portion of the insulation layer which is exposed by the frame.03-17-2011
20120009795CHEMICALLY AMPLIFIED RESIST MATERIAL AND PATTERN FORMATION METHOD USING THE SAME - A resist film (01-12-2012
20120045901METHOD OF FORMING A PATTERN STRUCTURE FOR A SEMICONDUCTOR DEVICE - In a method of forming a pattern structure, a cut-off portion of the node-separated line of a semiconductor device is formed by a double patterning process by using a connection portion of the sacrificial mask pattern and the mask pattern to thereby improve alignment margin. The alignment margin between the mask pattern and the sacrificial mask pattern is increased to an amount of the length of the connection portion of the sacrificial mask pattern. The lines adjacent to the node-separated line include a protrusion portion protruding toward the cut-off portion of the separated line.02-23-2012
20120156884FILM FORMING METHOD OF AMORPHOUS CARBON FILM AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE USING THE SAME - Disclosed is a film forming method of an amorphous carbon film, including: disposing a substrate in a processing chamber; supplying a processing gas containing carbon, hydrogen and oxygen into the processing chamber; and decomposing the processing gas by heating the substrate in the processing chamber and depositing the amorphous carbon film on the substrate.06-21-2012
20120064725NAPHTHALENE DERIVATIVE, RESIST BOTTOM LAYER MATERIAL, AND PATTERNING PROCESS - A naphthalene derivative having formula (1) is provided wherein An and Art denote a benzene or naphthalene ring, and n is such a natural number as to provide a weight average molecular weight of up to 100,000. A material comprising the naphthalene derivative or a polymer comprising the naphthalene derivative is spin coated to form a resist bottom layer having improved properties. A pattern forming process in which a resist bottom layer formed by spin coating is combined with an inorganic hard mask formed by CVD is available.03-15-2012
20120108071RESIST UNDERLAYER FILM COMPOSITION AND PATTERNING PROCESS USING THE SAME - There is disclosed a resist underlayer film composition, wherein the composition contains a polymer obtained by condensation of, at least, one or more compounds represented by the following general formula (1-1) and/or (1-2), and one or more kinds of compounds and/or equivalent bodies thereof represented by the following general formula (2). There can be provided an underlayer film composition, especially for a trilayer resist process, that can form an underlayer film having reduced reflectance, namely, an underlayer film having optimum n-value and k-value, excellent filling-up properties, high pattern-antibending properties, and not causing line fall or wiggling after etching especially in a high aspect line that is thinner than 60 nm, and a patterning process using the same.05-03-2012
20120156883METHOD OF FORMING PATTERNS OF SEMICONDUCTOR DEVICE - A method of forming patterns of a semiconductor device includes forming partition patterns on a hard mask layer; forming a first auxiliary layer on the entire structure including a surface of the partition patterns; forming auxiliary patterns to cover a portion of the first auxiliary layer formed over sidewalls of the partition pattern formed in second region, where each of the auxiliary patterns in the second region has a width greater than a thickness of the first auxiliary layer; forming spacers on sidewalls of the partition patterns, so that a portion of the partition patterns and a portion of the hard mask layer are exposed; removing the auxiliary patterns; etching the partition patterns exposed between the spacers; and removing remaining regions of the partition patterns and the hard mask layer exposed between the spacers.06-21-2012
20120156882METHOD FOR FABRICATING LARGE-AREA NANOSCALE PATTERN - A method for fabricating a large-area nanoscale pattern includes: forming multilayer main thin films isolated by passivation layers; patterning a first main thin film to form a first main pattern; forming a first spacer pattern with respect to the first main pattern; and forming a second main pattern by transferring the first spacer pattern onto a second main thin film. By using multilayer main thin films isolated by different passivation films, spacer lithography capable of reducing a pattern pitch can be repetitively performed, and the pattern pitch is repetitively reduced without shape distortion after formation of micrometer-scale patterns, thereby forming nanometer-scale fine patterns uniformly over a wide area.06-21-2012
20120070993PASSIVATION OF INTEGRATED CIRCUITS CONTAINING FERROELECTRIC CAPACITORS AND HYDROGEN BARRIERS - A method for forming a hydrogen barrier layer that overlies ferroelectric capacitors and a buffer region but is removed from a portion of the logic region.03-22-2012
20120156881METHOD FOR DEFINING A SEPARATING STRUCTURE WITHIN A SEMICONDUCTOR DEVICE - A method includes depositing a material layer over a semiconductor substrate and using a first mask in a first exposure/patterning process to pattern the material layer thereby forming a plurality of first and second features. The first features include patterns for the semiconductor device and the second features include printing assist features. The method includes using a second mask in a second exposure/patterning process to effectively remove the second features from the material layer and to define at least one separating structure between two first features.06-21-2012
20120108070METHOD FOR FORMING SEMICONDUCTOR DEVICE - A method for forming a semiconductor device is disclosed. A method for forming a semiconductor device includes forming a first hard mask layer over a semiconductor substrate including a cell region and a peripheral circuit region, forming a spacer pattern over the first hard mask layer of the cell region, forming a cell-open mask pattern over the peripheral circuit region, forming a first hard mask pattern by etching the first hard mask layer using the spacer pattern of the cell region as an etch mask, forming a second hard mask layer over the first hard mask pattern of the cell region and a first hard mask layer of the peripheral circuit region, forming a cutting mask pattern over the second hard mask layer; and forming an active region in the cell region and a device isolation region in the peripheral circuit region by etching the second hard mask layer, the first hard mask pattern of the cell region, the first hard mask layer of the peripheral circuit region, and the semiconductor substrate using the cutting mask pattern as an etch mask.05-03-2012
20120208368METHOD AND APPARATUS FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE - A method of manufacturing an SiC semiconductor device includes the steps of forming a first oxide film on a first surface of an SiC semiconductor, removing the first oxide film, and forming a second oxide film constituting the SiC semiconductor device on a second surface exposed as a result of removal of the first oxide film in the SiC semiconductor. Between the step of removing the first oxide film and the step of forming a second oxide film, the SiC semiconductor is arranged in an atmosphere cut off from an ambient atmosphere.08-16-2012
20120208367METHOD FOR FABRICATING CARBON HARD MASK AND METHOD FOR FABRICATING PATTERNS OF SEMICONDUCTOR DEVICE USING THE SAME - A method for fabricating a carbon hard mask layer includes: loading a substrate with a pattern target layer into a chamber; performing a primary thermal treatment on the substrate; depositing a carbon hard mask layer over the pattern target layer by using C08-16-2012
20120252218BIPHENYL DERIVATIVE, RESIST BOTTOM LAYER MATERIAL, BOTTOM LAYER FORMING METHOD, AND PATTERNING PROCESS - A biphenyl derivative having formula (1) is provided wherein Ar1 and Ar2 denote a benzene or naphthalene ring, and x and z each are 0 or 1. A material comprising the biphenyl derivative or a polymer comprising recurring units of the biphenyl derivative is spin coated and heat treated to form a resist bottom layer having improved properties, optimum values of n and k, step coverage, etch resistance, heat resistance, solvent resistance, and minimized outgassing.10-04-2012
20120252217COMPOSITION FOR FORMING RESIST UNDERLAYER FILM AND METHOD FOR FORMING PATTERN - A resist underlayer film-forming composition includes (A) a polymer that includes a repeating unit shown by a formula (1), and has a polystyrene-reduced weight average molecular weight of 3000 to 10,000, and (B) a solvent,10-04-2012
20110104901SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor device manufacturing method includes a process of forming a first organic film pattern on a to-be-etched layer on a substrate, a process of forming a silicon oxide film coating the first organic film pattern in an isotropic manner, a process of etching the silicon oxide film to form a first mask pattern in such a manner to cause the width of the line part of the first organic film pattern to have a fixed proportion with respect to a thickness of the silicon oxide film that coats a surface of the line part in the isotropic manner, a process of forming a second organic film pattern coating the silicon oxide film, a process of forming a second mask pattern that includes the silicon oxide film on a side face part in an area that is coated by the second organic film pattern, and a process of, in an area other than the area that is coated by the second organic film pattern, forming a third mask pattern in which an even number of the silicon oxide films are arranged.05-05-2011
20120129351COMPOSITE REMOVABLE HARDMASK - A method and apparatus for forming an amorphous carbon layer on a substrate is provided. A first portion of the amorphous carbon layer having a high stress level is formed from a hydrocarbon precursor having high dilution ratio, with optional amine precursor included to add stress-elevating nitrogen. A second portion of the amorphous carbon layer having a low stress level is formed on the first portion by reducing the dilution ratio of the hydrocarbon precursor and lowering or eliminating the amine gas. Pressure, temperature, and RF power input may be adjusted instead of, or in addition to, precursor flow rates, and different precursors may be used for different stress levels.05-24-2012
20120220133Integrated Circuit Having Interleaved Gridded Features, Mask Set, and Method for Printing - A method for fabricating an integrated circuit includes the steps of: providing a substrate having a semiconductor surface; providing a hardmask material on the semiconductor surface. For at least one masking level of the integrated circuit: providing a mask pattern for the masking level partitioned into a first mask and at least one second mask, the first mask providing features in a first grid pattern and the at least one second mask providing features in a second grid pattern, wherein the first and the second grid pattern have respective features which interleave with one another over at least one area; applying a first photoresist layer with the first mask; exposing the first grid pattern using the first mask; developing the first photoresist layer; etching the hardmask material to transfer the first grid pattern in the surface of the substrate; removing the first photoresist layer.08-30-2012
20120164837FEATURE SIZE REDUCTION - Methods for semiconductor device fabrication are provided. Features are created using spacers. Methods include creating a pattern comprised of at least two first features on the substrate surface, depositing a first conformal layer on the at least two first features, depositing a second conformal layer on the first conformal layer, partially removing the second conformal layer to partially expose the first conformal layer, and partially removing the first conformal layer from between the first features and the second conformal layer thereby creating at least two second features. Optionally the first conformal film is partially etched back before the second conformal film is deposited.06-28-2012
20100173497Method of fabricating semiconductor integrated circuit device - A method manufacturing a semiconductor integrated circuit device includes providing a substrate; sequentially forming a layer to be etched, a first layer, and a second layer on the substrate; forming on the first and second layers a first etch mask having a plurality of first line patterns separated from each other by a first pitch and extending in a first direction; sequentially performing first etching on the second layer and the first layer using the first etch mask to form an intermediate mask pattern with second and first patterns; forming on the intermediate mask pattern a second etch mask including a plurality of second line patterns separated from each other by a second pitch and extending in a second direction other than the first direction; performing second etching using the second etch mask on a portion of the second pattern so that the remaining portion of the second pattern is left on the first pattern; performing third etching using the second etch mask under different conditions than the second etching on the first pattern and the remaining portion of second pattern of the intermediate mask pattern and forming a final mask pattern; and patterning the layer to be etched using the final mask pattern.07-08-2010
20120252216Low-Temperature in-situ Removal of Oxide from a Silicon Surface During CMOS Epitaxial Processing - Low-temperature in-situ techniques are provided for the removal of oxide from a silicon surface during CMOS epitaxial processing. Oxide is removed from a semiconductor wafer having a silicon surface, by depositing a SiGe layer on the silicon surface; etching the SiGe layer from the silicon surface at a temperature below 700 C (and above, for example, approximately 450 C); and repeating the depositing and etching steps a number of times until a contaminant is substantially removed from the silicon surface. In one variation, the deposited layer comprises a group IV semiconductor material and/or an alloy thereof.10-04-2012
20120171869ETCHING METHOD - There is provided an etching method which can form trenches or via holes having desired aspect ratios and shapes in a to-be-processed object made of silicon. The etching method includes: a hydrogen halide-containing gas-based etching step of etching a silicon substrate by introducing a hydrogen halide-containing gas into a vacuum chamber; a fluorine-containing gas-based etching step of etching the silicon substrate by introducing a fluorine-containing gas into the vacuum chamber; a protective film formation step forming a protective film on the silicon substrate by sputtering a solid material; and a protective film removal step of removing part of the protective film by applying radio frequency bias power to a substrate electrode. The fluorine-containing gas-based etching step, the protective film formation step, and the protective film removal step are repeatedly performed in this order.07-05-2012
20100048025NANOSTRUCTURES AND NANOSTRUCTURE FABRICATION - Nanostructure and techniques for fabricating nanostructures are provided. In one embodiment, nanostructures may be formed by providing a Silicon-on-Insulator (SOI) substrate, forming a pattern on the SOI substrate, disposing a conformal layer over the pattern, etching the conformal layer, except for a sidewall portion, removing the pattern, transferring the sidewall pattern to the silicon layer of the SOI substrate to form the nanostructure, and releasing the nanostructure.02-25-2010
20120220132SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor device manufacturing method includes: forming a core layer, an anti-reflection film and a photoresist layer on a layer to be etched of a substrate; trimming first line patterns of the photoresist layer; forming a first film on the first line patterns; removing the first film such that the first film is left in sidewall portions of the first line patterns of the photoresist layer; removing the photoresist layer; producing the core layer into second line patterns by etching the anti-reflection film and the core layer; forming a second film on the core layer produced into the second line patterns; removing the second film such that the second film is left in sidewall portions of the second line patterns of the core layer; and producing the layer to be etched into third line patterns by etching the layer to be etched.08-30-2012
20090061637MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE - A manufacturing method for a semiconductor device includes: forming a first material film, a second material film, each having a function of preventing metal diffusion, and a third material film of which the etching rate for a first etchant is sufficiently lower than that of the first material film and the etching rate for a second etchant is sufficiently lower than that of the second material film, in this order on the outer peripheral surface of the semiconductor substrate; forming a trench structure; forming a buried insulating film and flattening it; removing the second material film through a wet etching process using the second etchant until the first material film formed on the main surface side is exposed; and removing the first material film on the main surface side through a wet etching process using the first etchant until the semiconductor substrate is exposed on the main surface side.03-05-2009
20090061636Etching method for nitride semiconductor - The invention discloses etching method for the nitride semiconductor. Firstly dielectric layer is formed on gallium nitride. The line pattern or dot pattern is formed on the dielectric layer by using the exposure, development, and etching processes. The dielectric layer is used as the mask for the epitaxial lateral overgrowth of follow-up gallium nitride layer. The thick gallium nitride film is grown on the dielectric layer. Then the wet etching process is used to remove the dielectric layer, and the thick gallium nitride film on the dielectric layer is etched to form the specific shape as required.03-05-2009
20120083127METHOD FOR FORMING A PATTERN AND A SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A method for forming a fine pattern on a substrate includes providing a substrate including a material with an initial pattern formed thereon and having a first line width, performing a self-limiting oxidation and/or nitridation process on a surface of the material and thereby forming an oxide, a nitride, or an oxynitride film on a surface of the initial pattern, and removing the oxide, nitride, or oxynitride film. The method further includes repeating the formation and removal of the oxide, nitride, or oxynitride film to form a second pattern having a second line width that is smaller than the first line width of the initial pattern. The patterned material can contain silicon, a silicon-containing material, a metal, or a metal-nitride, and the self-limiting oxidation process can include exposure to vapor phase ozone, atomic oxygen generated by non-ionizing electromagnetic (EM) radiation, atomic nitrogen generated by ionizing or non-ionizing EM radiation, or a combination thereof.04-05-2012
20120225560MANUFACTURING METHOD OF INTEGRATED CIRCUITS BASED ON FORMATION OF LINES AND TRENCHES - The disclosure relates to a method for etching a target layer, comprising: depositing a hard mask layer onto a target layer and onto the hard mask layer, a first photosensitive layer, exposing the first photosensitive layer through a first mask to transfer first patterns into the photosensitive layer, transferring the first patterns into the hard mask layer, depositing onto the hard mask layer etched a second photosensitive layer, exposing the second photosensitive layer through a second mask to transfer second patterns into the second photosensitive layer, transferring the second patterns into the hard mask layer by etching this layer, and transferring the first and second patterns into the target layer through the hard mask, the second patterns forming lines, and the first patterns forming trenches cutting the lines in the hard mask.09-06-2012
20090017631SELF-ALIGNED PILLAR PATTERNING USING MULTIPLE SPACER MASKS - A method for fabricating a semiconductor mask is described. The image of a series of lines from a first spacer mask is first provided to a mask layer to form a patterned mask layer. The image of a series of lines from a second spacer mask is then provided to the patterned mask layer to form a pillar mask comprised of a series of pillars. The image of the series of lines from the second spacer mask is non-parallel with the series of lines from the first spacer mask.01-15-2009
20080299776FREQUENCY DOUBLING USING SPACER MASK - A method for fabricating a semiconductor mask is described. A semiconductor stack having a sacrificial mask and a spacer mask is first provided. The sacrificial mask is comprised of a series of lines and the spacer mask has spacer lines adjacent to the sidewalls of the series of lines. Next, the spacer mask is cropped. Finally, the sacrificial mask is removed to provide a cropped spacer mask. The cropped spacer mask doubles the frequency of the series of lines of the sacrificial mask.12-04-2008
20120322268METHOD OF FORMING A PATTERN - A method of forming a pattern includes forming a mask pattern on a substrate; etching the substrate by deep reactive ion etching (DRIE) and by using the mask pattern as an etch mask; partially removing the mask pattern to expose a portion of an upper surface of the substrate; and etching the exposed portion of the upper surface of the substrate. In the method, when a pattern is formed by DRIE, an upper portion of the pattern does not protrude or scarcely protrudes, and scallops of a sidewall of the pattern are smooth, and thus a conformal material layer may be easily formed on a surface of the pattern.12-20-2012
20110223769METHOD OF FABRICATING A SEMICONDUCTOR DEVICE - According to one embodiment, a method of fabricating a semiconductor device, including, selectively forming a first film as a core member on a film to be processed, forming a second film on a side surface and an upper surface of the core member, and on an upper surface of the film to be processed to cover the film, the second film which is constituted with same material as the first film and is doped with impurities being different in amount from impurities in the first film, removing the second film on the core member and on the film to be processed to form a sidewall mask constituted with the second film on the side surface of the core member, selectively removing the core member, and etching the film to be processed using the sidewall mask film as a mask.09-15-2011
20120322269Methods of Fabricating Substrates - A method of fabricating a substrate includes forming first and second spaced features over a substrate. The first spaced features have elevationally outermost regions which are different in composition from elevationally outermost regions of the second spaced features. The first and second spaced features alternate with one another. Every other first feature is removed from the substrate and pairs of immediately adjacent second features are formed which alternate with individual of remaining of the first features. After such act of removing, the substrate is processed through a mask pattern comprising the pairs of immediately adjacent second features which alternate with individual of the remaining of the first features. Other embodiments are disclosed.12-20-2012
20120276745METHOD FOR FABRICATING HOLE PATTERN IN SEMICONDUCTOR DEVICE - A method for fabricating a hole pattern in a semiconductor device includes forming a first organic layer over an etch layer, forming a first inorganic layer pattern over the first organic layer, etching the first organic layer using the first inorganic layer pattern as an etching barrier, forming a second organic layer over the first organic layer, forming a second inorganic layer pattern over the second organic layer, where the second inorganic layer pattern crosses the first inorganic pattern, etching the first and second organic layers using the second inorganic layer pattern as an etching barrier, and etching the etch layer using the etched first and second organic layers as an etch barrier to form a hole pattern.11-01-2012
20110294298TEXTURED SINGLE CRYSTAL - A method for fabricating a textured single crystal including depositing pads made of metal on a surface of a single crystal. A protective layer is deposited on the pads and on the single crystal between the pads; and etching the surface with a first compound that etches the metal more rapidly than the protective layer is carried out. Processing continues with etching the surface with a second compound that etches the single crystal more rapidly than the protective layer; and etching the surface with a third compound that etches the protective layer more rapidly than the single crystal. The textured substrate may be used for the epitaxial growth of GaN, AlN or III-N compounds (i.e. a nitride of a metal the positive ion of which carries a +3 positive charge) in the context of the fabrication of LEDs, electronic components or solar cells.12-01-2011
20120329282METHOD AND MATERIAL FOR FORMING A DOUBLE EXPOSURE LITHOGRAPHY PATTERN - Various lithography methods are disclosed. An exemplary lithography method includes forming a first patterned silicon-containing organic polymer layer over a substrate by removing a first patterned resist layer, wherein the first patterned silicon-containing organic polymer layer includes a first opening having a first dimension and a second opening having the first dimension, the first opening and the second opening exposing the substrate; forming a second patterned silicon-containing organic polymer layer over the substrate by removing a second patterned resist layer, wherein a portion of the patterned second silicon-containing organic polymer layer combines with a portion of the first patterned silicon-containing organic polymer layer to reduce the first dimension of the second opening to a second dimension; and etching the substrate exposed by the first opening having the first dimension and the second opening having the second dimension.12-27-2012
20100190347REMOVAL CHEMISTRY FOR SELECTIVELY ETCHING METAL HARD MASK - Embodiments of the present invention describe a removal chemistry for removing hard mask. The removal chemistry is a wet-etch solution that removes a metal hard mask formed on a dielectric layer, and is highly selective to a metal conductor layer underneath the dielectric layer. The removal chemistry comprises an aqueous solution of hydrogen peroxide (H07-29-2010
20100130016METHODS OF FORMING A MASKING PATTERN FOR INTEGRATED CIRCUITS - In some embodiments, methods for forming a masking pattern for an integrated circuit are disclosed. In one embodiment, mandrels defining a first pattern are formed in a first masking layer over a target layer. A second masking layer is deposited to at least partially fill spaces of the first pattern. Sacrificial structures are formed between the mandrels and the second masking layer. After depositing the second masking layer and forming the sacrificial structures, the sacrificial structures are removed to define gaps between the mandrels and the second masking layer, thereby defining a second pattern. The second pattern includes at least parts of the mandrels and intervening mask features alternating with the mandrels. The second pattern may be transferred into the target layer. In some embodiments, the method allows the formation of features having a high density and a small pitch while also allowing the formation of features having various shapes and sizes.05-27-2010
20100130015PATTERNING METHOD - Disclosed is a patterning method including: forming a first film on a substrate; forming a first resist film on the first film; processing the first resist film into a first resist pattern having a preset pitch by photolithography; forming a silicon oxide film on the first resist pattern and the first film by alternately supplying a first gas containing organic silicon and a second gas containing an activated oxygen species to the substrate; forming a second resist film on the silicon oxide film; processing the second resist film into a second resist pattern having a preset pitch by the photolithography; and processing the first film by using the first resist pattern and the second resist pattern as a mask.05-27-2010
20130017685METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SUBSTRATE PROCESSING APPARATUSAANM Akae; NaonoriAACI Imizu-shiAACO JPAAGP Akae; Naonori Imizu-shi JPAANM Murakami; KotaroAACI Toyama-shiAACO JPAAGP Murakami; Kotaro Toyama-shi JPAANM Hirose; YoshiroAACI Toyama-shiAACO JPAAGP Hirose; Yoshiro Toyama-shi JPAANM Kameda; KenjiAACI Toyama-shiAACO JPAAGP Kameda; Kenji Toyama-shi JP - To provide a method of manufacturing a semiconductor device, including: forming a thin film different from a silicon oxide film on a substrate by supplying a processing gas into a processing vessel in which the substrate is housed; removing a deposit including the thin film adhered to an inside of the processing vessel by supplying a fluorine-containing gas into the processing vessel after executing forming the thin film prescribed number of times; and forming a silicon oxide film having a prescribed film thickness on the inside of the processing vessel by alternately supplying a silicon-containing gas, and an oxygen-containing gas and a hydrogen-containing gas into the heated processing vessel in which a pressure is set to be less than an atmospheric pressure after removing the deposit.01-17-2013
20110159697ETCHING METHOD AND ETCHING APPARATUS - There are provided an etching method and an etching apparatus suitable for etching an antireflection coating layer by using a resist film as a mask. The etching method includes forming the antireflection coating layer (Si-ARC layer) on an etching target layer; forming a patterned resist film (ArF resist film) on the antireflection coating layer; and forming a desired pattern on the antireflection coating layer by introducing an etching gas including a CF06-30-2011
20110159696METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES - A method of manufacturing semiconductor devices comprises forming an etch target layer and auxiliary patterns over a semiconductor substrate, forming spacers on sidewalls of the auxiliary patterns, removing the auxiliary patterns, performing an etch process to change both corners of upper portions of the spacers to be symmetrical to one another, and patterning the etch target layer by using the spacers.06-30-2011
20110159695METHOD FOR MANUFACTURING MASK - Openings are formed in first and second mask layers. Next, diameter of the opening in the second mask layer is enlarged so that the diameter of the opening in the second mask layer becomes larger by a length X than diameter of the opening in the first mask layer. Thereafter, mask material is formed into the opening in the second mask layer, to form a cavity with a diameter X within the opening in the second mask layer. There is formed a mask which includes the second mask layer and the mask material having therein opening including the cavity.06-30-2011
20110159694METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes: providing a substrate, forming an insulation layer, an adhesive layer, and a photoresist pattern, etching the adhesive layer using the photoresist pattern as an etch barrier, and wet etching the insulation layer using the etched adhesive layer and the photoresist pattern as etch barriers.06-30-2011
20110159693METHOD FOR FABRICATING HOLE PATTERN - A method for fabricating a hole pattern includes forming a first hard mask layer over an etch target layer, forming a second hard mask pattern over the first hard mask layer, which are patterned to be a line type in a first direction and have a selective etch ratio to the first hard mask layer, forming a third hard mask layer over the first hard mask layer to bury a space between adjacent ones of the second hard mask pattern, forming a photoresist pattern over the third hard mask layer, which is patterned to be a line type in a second direction; etching the third hard mask layer using the photoresist pattern to form a third hard mask pattern, removing the photoresist pattern, and etching the first hard mask layer using the second and third hard mask patterns.06-30-2011
20080254634Photoresist composition and method of manufacturing a thin-film transistor substrate using the same - In one example, a photoresist composition includes about 1 to about 70 parts by weight of a first binder resin including a repeat unit represented by the following Chemical Formula 1, about 1 to about 70 parts by weight of a second binder resin including a repeat unit represented by the following Chemical Formula 2, about 0.5 to about 10 parts by weight of a photo-acid generator, about 1 to about 20 parts by weight of a cross-linker and about 10 to about 200 parts by weight of a solvent. The photoresist composition may improve the heat resistance and adhesion ability of a photoresist pattern.10-16-2008
20080254633MULTIPLE EXPOSURE LITHOGRAPHY METHOD INCORPORATING INTERMEDIATE LAYER PATTERNING - A method of patterning a semiconductor substrate includes creating a first set of patterned features in a first inorganic layer; creating a second set of patterned features in one of the first inorganic layer and a second inorganic layer; and transferring, into an organic underlayer, both the first and second sets of patterned features, wherein the first and second sets of patterned features are combined into a composite set of patterned features that are transferable into the substrate by using the organic underlayer as a mask.10-16-2008
20080248651METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A first oxide film and a second oxide film 16 are formed in a first region 10-09-2008
20080227300Method for manufacturing semiconductor device - A method of manufacturing a semiconductor device prevents a pattern bridge phenomenon generated by a proximity effect between patterns and a thickness lowering phenomenon of the pattern. As a result, a length of the major axis required in characteristics of the device is secured to improve an electric characteristic and an overlapping margin. A photoresist pattern is formed to have a line/space type, thereby securing a DOF margin in comparison with a photoresist pattern of an island type.09-18-2008
20080220613PROTECTION OF POLYMER SURFACES DURING MICRO-FABRICATION - A method of protecting a polymeric layer from contamination by a photoresist layer. The method includes: (a) forming a polymeric layer over a substrate; (b) forming a non-photoactive protection layer over the polymeric layer; (c) forming a photoresist layer over the protection layer; (d) exposing the photoresist layer to actinic radiation and developing the photoresist layer to form a patterned photoresist layer, thereby exposing regions of the protection layer; (e) etching through the protection layer and the polymeric layer where the protection layer is not protected by the patterned photoresist layer; (f) removing the patterned photoresist layer in a first removal process; and (g) removing the protection layer in a second removal process different from the first removal process.09-11-2008
20080220612PROTECTION OF POLYMER SURFACES DURING MICRO-FABRICATION - A method of protecting a polymeric layer from contamination by a photoresist layer. The method includes: (a) forming a polymeric layer over a substrate; (b) forming a non-photoactive protection layer over the polymeric layer; (c) forming a photoresist layer over the protection layer; (d) exposing the photoresist layer to actinic radiation and developing the photoresist layer to form a patterned photoresist layer, thereby exposing regions of the protection layer; (e) etching through the protection layer and the polymeric layer where the protection layer is not protected by the patterned photoresist layer; (f) removing the patterned photoresist layer in a first removal process; and (g) removing the protection layer in a second removal process different from the first removal process.09-11-2008
20130095664ATOMIC LAYER DEPOSITION OF ANTIMONY OXIDE FILMS - Antimony oxide thin films are deposited by atomic layer deposition using an antimony reactant and an oxygen source. Antimony reactants may include antimony halides, such as SbCl04-18-2013
20130115778Dry Etch Processes - Provided methods of etching and/or patterning films. Certain methods comprise exposing at least part of a film on a substrate, the film comprising one or more of HfO05-09-2013
20130115777MANUFACTURING METHOD FOR SEMICONDUCTOR STRUCTURES - A manufacturing method for semiconductor structures includes providing a substrate having a first region and a second region defined thereon, forming a plurality of first patterns in the first region and at least a second pattern in the second region, forming a plurality of first spacers respectively on sidewalls of the first patterns and at least a second spacer on a sidewall of the second pattern, forming a patterned protecting layer in the second region, removing the first patterns from the first region to form a plurality of first masking patterns in the first region and at least a second masking pattern in the second region, and transferring the first masking patterns and the second masking pattern to the substrate.05-09-2013
20130115776PRESSURE CONTROL VALVE ASSEMBLY OF PLASMA PROCESSING CHAMBER AND RAPID ALTERNATING PROCESS - A pressure control valve assembly of a plasma processing chamber in which semiconductor substrates are processed includes a housing having an inlet, an outlet and a conduit extending between the inlet and the outlet, the inlet adapted to be connected to an interior of the plasma processing chamber and the outlet adapted to be connected to a vacuum pump which maintains the plasma processing chamber at desired pressure set points during rapid alternating phases of processing a semiconductor substrate in the chamber. A fixed slotted valve plate having a first set of parallel slots therein is fixed in the conduit such that gasses withdrawn from the chamber into the conduit pass through the first set of parallel slots. A movable slotted valve plate having a second set of parallel slots therein is movable with respect to the fixed slotted valve plate so as to adjust pressure in the chamber.05-09-2013
20130130504METHOD OF MANUFACTURING NON-PHOTOSENSITIVE POLYIMIDE PASSIVATION LAYER - A method of manufacturing non-photosensitive polyimide passivation layer is disclosed. The method includes: spin-coating a non-photosensitive polyimide layer over a wafer and baking it; depositing a silicon dioxide thin film thereon; spin-coating a photoresist layer over the silicon dioxide thin film and baking it; exposing and developing the photoresist layer to form a photoresist pattern; etching the silicon dioxide thin film by using the photoresist pattern as a mask; removing the patterned photoresist layer; dry etching the non-photosensitive polyimide layer by using the patterned silicon dioxide thin film as a mask; removing the patterned silicon dioxide thin film; and curing to form a imidized polyimide passivation layer. The method addresses issues of the traditional non-photosensitive polyimide process, including aluminum corrosion by developer, tapered profile of non-photosensitive polyimide layer and generation of photoresist residues.05-23-2013
20130130503METHOD FOR FABRICATING ULTRA-FINE NANOWIRE - Disclosed herein is a method for fabricating an ultra-fine nanowire by combining a trimming process and a mask blocking oxidation process. The ultra-thin nanowire is fabricated by a combination of performing a trimming process on a mask to reduce a width of the mask and blocking an oxidation through the mask. A diameter of the floated ultra-thin nanowire fabricated by the method is controlled to 20 nm below by a thickness of a deposited silicon oxide film, a width of the silicon oxide nanowire after trimming, and a time and a temperature for performing a wet oxidation process. Also, since a speed of the wet oxidation process is faster, the width of the nanowire obtained by a conventional photolithography is reduced faster. Moreover, when fabricating an ultra-thin nanowire by using the method, the cost is reduced and it is more feasible to be implemented.05-23-2013
20130203257PATTERNING PROCESS FOR FIN-LIKE FIELD EFFECT TRANSISTOR (FINFET) DEVICE - A method for patterning a plurality of features in a non-rectangular pattern on an integrated circuit device includes providing a substrate including a surface with a first layer and a second layer, forming a plurality of elongated protrusions in a third layer above the first and second layers, and forming a first patterned layer over the plurality of elongated protrusions. The plurality of elongated protrusions are etched to form a first pattern of the elongated protrusions, the first pattern including at least one inside corner. The method also includes forming a second patterned layer over the first pattern of elongated protrusions and forming a third patterned layer over the first pattern of elongated protrusions. The plurality of elongated protrusions are etched using the second and third patterned layers to form a second pattern of the elongated protrusions, the second pattern including at least one inside corner.08-08-2013
20100279508METHOD FOR REDUCING AMINE BASED CONTAMINANTS - Method for reducing resist poisoning. The method includes the steps of forming a first structure in a dielectric on a substrate, reducing amine related contaminants from the dielectric and the substrate prior to a formation of a second structure on the substrate such that the amine related contaminates will not diffuse out from either the substrate or the dielectric, wherein the reducing utilizes a plasma treatment which one of chemically ties up the amine related contaminates and binds, traps, or consumes the amine related contaminates during subsequent processing steps, forming the second structure on the substrate, and after the forming of the first structure, preventing poisoning of a resist layer in subsequent processing by the reducing.11-04-2010
20080200035METHOD OF FORMING CONTACT HOLE OF SEMICONDUCTOR DEVICE - A method of forming a contact hole of a semiconductor device is disclosed. At the time of a hard mask formation process for forming a contact hole of a semiconductor device, first patterns are formed using a photoresist pattern employing an exposure process. Spacers having a predetermined thickness are formed on sidewalls of the first patterns using an amorphous carbon layer. Spaces between the first patterns including the spacers are gap filled to form second patterns. Accordingly, a contact hole having a pitch with exposure equipment resolution or less can be formed.08-21-2008
20110237082MICRO PATTERN FORMING METHOD - There is provided a micro pattern forming method including forming a thin film on a substrate; forming a film serving as a mask when processing the thin film; processing the film serving as a mask into a pattern including lines having a preset pitch; trimming the pattern including the lines; and forming an oxide film on the pattern including the lines and on the thin film by alternately supplying a source gas and an activated oxygen species. Here, the process of trimming the pattern and the process of forming an oxide film are consecutively performed in a film forming apparatus configured to form the oxide film.09-29-2011
20100297848ETCHING OF TUNGSTEN SELECTIVE TO TITANIUM NITRIDE - The present invention in one embodiment provides an etch method that includes providing a structure including a tungsten (W) portion and a titanium nitride (TiN) portion; applying a first etch feed gas of sulfur hexafluoride (SF11-25-2010
20130157468ETCHING METHOD, SUBSTRATE PROCESSING METHOD, PATTERN FORMING METHOD, METHOD FOR MANUFACTURING SEMICONDUCTOR ELEMENT, AND SEMICONDUCTOR ELEMENT - A fluorocarbon layer is formed on a silicon substrate that is a to-be-processed substrate (step A). A resist layer is formed on the thus-formed fluorocarbon layer (step B). Then, the resist layer is patterned into a predetermined shape by exposing the resist layer to light by means of a photoresist layer (step C). The fluorocarbon layer is etched using the resist layer, which has been patterned into a predetermined shape, as a mask (step D). Next, the resist layer served as a mask is removed (step E). After that, the silicon substrate is etched using the remained fluorocarbon layer as a mask (step F). Since the fluorocarbon layer by itself functions as an antireflective film and a harm mask, the reliability of processing can be improved, while reducing the cost.06-20-2013
20120282779SIDEWALL IMAGE TRANSFER PROCESS EMPLOYING A CAP MATERIAL LAYER FOR A METAL NITRIDE LAYER - A cap material layer is deposited on a metal nitride layer. An antireflective coating (ARC) layer, an organic planarizing layer (OPL), and patterned line structures are formed upon the cap material layer. The pattern in the patterned line structures is transferred into the ARC layer and the OPL. Exposed portions of the cap material layer are etched simultaneously with the etch removal of the patterned line structures and the ARC layer. The OPL is employed to etch the metal nitride layer. The patterned cap material layer located over the metal nitride layer protects the top surface of the metal nitride layer, and enables high fidelity reproduction of the pattern in the metal nitride layer without pattern distortion. The metal nitride layer is subsequently employed as an etch mask for pattern transfer into an underlying layer.11-08-2012
20120282778Methods Of Forming A Pattern On A Substrate - A method of forming a pattern on a substrate includes forming a repeating pattern of four first lines elevationally over an underlying substrate. A repeating pattern of four second lines is formed elevationally over and crossing the repeating pattern of four first lines. First alternating of the four second lines are removed from being received over the first lines. After the first alternating of the four second lines have been removed, elevationally exposed portions of alternating of the four first lines are removed to the underlying substrate using a remaining second alternating of the four second lines as a mask. Additional embodiments are disclosed and contemplated.11-08-2012
20130183829METHODS FOR INCREASED ARRAY FEATURE DENSITY - A method is provided that includes forming completely distinct first features above a substrate, forming sidewall spacers on the first features, filling spaces between adjacent sidewall spacers with filler features, and removing the sidewall spacers. Numerous other aspects are provided.07-18-2013
20130183830SILICON-CONTAINING COMPOSITION FOR FORMATION OF RESIST UNDERLAYER FILM, WHICH CONTAINS ORGANIC GROUP CONTAINING PROTECTED ALIPHATIC ALCOHOL - Described herein are compositions for forming an underlayer film for a solvent-developable resist. These compositions can include a hydrolyzable organosilane having a silicon atom bonded to an organic group containing a protected aliphatic alcohol group, a hydrolysate of the hydrolyzable organosilane, a hydrolysis-condensation product of the hydrolyzable organosilane, or a combination thereof and a solvent. The composition can form a resist underlayer film including, a hydrolyzable organosilane, a hydrolysate of the hydrolyzable organosilane, a hydrolysis-condensation product of the hydrolyzable organosilane, or a combination thereof, the silicon atom in the silane compound having a silicon atom bonded to an organic group containing a protected aliphatic alcohol group in a ratio of 0.1 to 40% by mol based on the total amount of silicon atoms. Also described is a method for applying the composition onto a semiconductor substrate and baking the composition to form a resist underlayer film.07-18-2013
20110312185PATTERN FORMATION METHOD AND PATTERN FORMATION DEVICE - According to one embodiment, a pattern formation method includes: forming a first pattern in a first region on a substrate to be treated; coating a plurality of types of block copolymers which are different in composition ratio on a second region which is different from the first region; and forming in the second region, by a heat treatment, a second pattern including a plurality of types of structures based on the coated plurality of types of block copolymers.12-22-2011
20120021608SUBSTRATE PROCESSING METHOD, SEMICONDUCTOR CHIP MANUFACTURING METHOD, AND RESIN-ADHESIVE-LAYER-BACKED SEMICONDUCTOR CHIP MANUFACTURING METHOD - To provide a substrate processing method and a semiconductor chip manufacturing method that enable low-cost formation of a mask for etching using plasma etching. During formation of a mask used in plasma dicing for separating a semiconductor wafer 01-26-2012
20120021607METHOD OF PITCH DIMENSION SHRINKAGE - An embodiment of the disclosure includes a method of pitch reduction. A substrate is provided. A first material layer is formed over the substrate. A second material layer is formed on the first material layer. A hardmask layer is formed on the second material layer. A first imaging layer is formed on the hardmask layer. The first imaging layer is patterned to form a plurality of first features over the hardmask layer. The hardmask layer is etched utilizing the first imaging layer as a mask to form the first features in the hardmask layer. The first imaging layer is removed to expose the etched hardmask layer and a portion of a top surface of the second material layer. A second imaging layer is formed and the process is repeated, such that first and second features are alternating with a pitch substantially half the original pitch.01-26-2012
20120028473Method of Reducing Delamination in the Fabrication of Small-Pitch Devices - A method of forming an integrated circuit structure includes providing a substrate; forming a first hard mask layer over the substrate; forming a second hard mask layer over the first hard mask layer; patterning the second hard mask layer to form a hard mask; and, after the step of patterning the second hard mask layer, baking the substrate, the first hard mask layer, and the hard mask. After the step of baking, a spacer layer is formed, which includes a first portion on a top of the hard mask, and a second portion and a third portion on opposite sidewalls of the hard mask. The method further includes removing the first portion of the spacer layer; removing the hard mask; and using the second portion and the third portion of the spacer layer as masks to pattern the first hard mask layer.02-02-2012
20120045900COMPOSITION FOR RESIST UNDERLAYER FILM, PROCESS FOR FORMING RESIST UNDERLAYER FILM, PATTERNING PROCESS, AND FULLERENE DERIVATIVE - The invention provides a composition for a resist underlayer film, the composition for a resist underlayer film to form a resist underlayer film of a multilayer resist film used in lithography, wherein the composition comprises at least (A) a fullerene derivative that is a reaction product of a substance having a fullerene skeleton with a 1,3-diene compound derivative having an electron-withdrawing group and (B) an organic solvent. There can be a composition for a resist underlayer film for a multilayer resist film used in lithography, the composition giving a resist underlayer film having excellent high dry etching resistance, capable of suppressing wiggling during substrate etching with high effectiveness, and capable of avoiding a poisoning problem in upperlayer patterning that uses a chemical amplification resist; a process for forming a resist underlayer film; a patterning process; and a fullerene derivative.02-23-2012
20120070994RESIST UNDERLAYER FILM FORMING COMPOSITION CONTAINING SILICON HAVING SULFIDE BOND - There is provided a resist underlayer film forming composition for lithography for forming a resist underlayer film capable of being used as a hard mask; and a forming method of a resist pattern using the underlayer film forming composition for lithography. A resist underlayer film forming composition for lithography comprising: as a silicon atom-containing compound, a hydrolyzable organosilane containing a sulfur atom-containing group, a hydrolysis product thereof, or a hydrolysis-condensation product thereof, wherein in the whole silicon atom-containing compound, the ratio of a sulfur atom to a silicon atom is less than 5% by mole. The hydrolyzable organosilane is preferably a compound of Formula (1): [R03-22-2012
20120077345CARBAZOLE NOVOLAK RESIN - There is provided a resist underlayer film having heat resistance that is used for a lithography process in the production of semiconductor devices, and a high refractive index film having transparency that is used for an electronic device. A polymer comprising a unit structure of Formula (03-29-2012
20130210233Methods for Particle Reduction in Semiconductor Processing - Methods for removing particles from a wafer for photolithography. A method is provided including providing a semiconductor wafer; attaching a polyimide layer to a backside of the semiconductor wafer; and performing an etch on an active surface of the semiconductor wafer; wherein particles that impinge on the backside during the etch are captured by the polyimide layer. In another method, includes attaching a layer of polyimide film to a backside of a semiconductor wafer; dry etching a material on an active surface of the semiconductor wafer; depositing of an additional layer of material on the active surface of the semiconductor wafer; removing the layer of polyimide film from the backside of the semiconductor wafer; patterning the layer of material using an immersion photolithography process to expose a photoresist on the active surface of the wafer; and repeating the attaching, dry etching, depositing, removing and patterning steps.08-15-2013
20130210234LITHOGRAPHY PROCESSES UTILIZING EXTREME ULTRAVIOLET RAYS AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES USING THE SAME - Lithography processes are provided. The lithography process includes installing a reticle masking (REMA) part having a REMA open region in a lithography apparatus, loading a reticle including at least one reticle chip region in which circuit patterns are disposed into the lithography apparatus, and sequentially exposing a first wafer field, which includes a first chip region corresponding to the reticle chip region, and a second wafer field, which includes a second chip region corresponding to the reticle chip region, of a wafer to rays using the reticle and the REMA part to transfer images of the circuit patterns onto the wafer. An edge boundary of the REMA open region transferred on the first wafer field is located on a scribe lane region between the first and second chip regions while the first wafer field is exposed. Methods of manufacturing a semiconductor device using the lithography process are also provided.08-15-2013

Patent applications in class Plural coating steps