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Plural coating steps

Subclass of:

438 - Semiconductor device manufacturing: process

438689000 - CHEMICAL ETCHING

438694000 - Combined with coating step

438700000 - Formation of groove or trench

Patent class list (only not empty are listed)

Deeper subclasses:

Class / Patent application numberDescriptionNumber of patent applications / Date published
438702000 Plural coating steps 89
20110207329DOUBLE PATTERNING STRATEGY FOR CONTACT HOLE AND TRENCH IN PHOTOLITHOGRAPHY - A method of lithography patterning includes forming a mask layer on a material layer and forming a capping layer on the mask layer. The capping layer is a boron-containing layer with a higher resistance to an etching reaction of patterning process of the material layer. By adapting the boron-containing layer as the capping layer, the thickness of the mask layer can be thus reduced. Hence, a better gap filling for forming an interconnect metallization in the material layer could be achieved as well.08-25-2011
20110195576DOUBLE PATTERNING STRATEGY FOR CONTACT HOLE AND TRENCH IN PHOTOLITHOGRAPHY - A method of lithography patterning includes forming a first etch stop layer, a second etch stop layer, and a hard mask layer on a material layer. The materials of the first etch stop layer and the second etch stop layer are selected by the way that there is a material gradient composition between the second etch stop layer, the first etch stop layer, and the material layer. Hence, gradient etching rates between the second etch stop layer, the first etch stop layer, and the material layer are achieved in an etching process to form etched patterns with smooth and/or vertical sidewalls within the second and the first etch stop layers and the material layer.08-11-2011
20130034964METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - The present invention discloses a method of manufacturing a semiconductor device. In order to form a trench with a smaller width, patterns of various monomers are formed by utilizing self-assembly characteristics of a block copolymer comprising various monomers. A metal or metal nitride is deposited on a surface of the block copolymer, the metal or metallic nitride selectively depositing due to a preferential chemical affinity between various monomers and the metal or metal nitride. After reaching a certain thickness, the metal or metal nitride layer begins to grow laterally. Deposition can be stopped by controlling deposition time so that the metal or metal nitride layer grows laterally but does not completely cover the surface of the block copolymer. Etching is then conducted using the metal or metal nitride layer as a mask to obtain a trench with a very small width.02-07-2013
20130078813PATTERN FORMING METHOD - The invention provides a pattern-formation process comprising a step of providing a substrate material having on a major surface a difficult-to-access recess formed by the presence of a 103-28-2013
20130040464METHOD OF PATTERNING A LOW-K DIELECTRIC FILM - Methods of patterning low-k dielectric films are described.02-14-2013
20130040463METHOD AND APPARATUS FOR MANUFACTURING SEMICONDUCTOR DEVICE - A mask layer is formed by: a step in which a first photoresist layer is formed, exposed, and developed on a substrate, thereby forming a first photoresist pattern; a step in which the first photoresist pattern is made insoluble; a step in which a second photoresist layer is formed, exposed, and developed on top of the first photoresist layer, thereby forming a second photoresist pattern that intersects the first photoresist pattern; a step in which the second photoresist pattern is made insoluble; and a step in which a third photoresist layer is formed, exposed, and developed on top of the first and second photoresist patterns, thereby forming a third photoresist pattern.02-14-2013
20120164836INTEGRATED CIRCUIT FABRICATION METHODS UTILIZING EMBEDDED HARDMASK LAYERS FOR HIGH RESOLUTION PATTERNING - Embodiments of a method for fabricating integrated circuits are provided. In one embodiment, the method includes the steps of depositing a dielectric layer over a semiconductor device, forming a plurality of trimmed hardmask structures at predetermined locations over the dielectric layer, embedding the plurality of trimmed hardmask structures in a surrounding hardmask layer, removing the plurality of trimmed hardmask structures to create a plurality of openings through the surrounding hardmask layer, and etching the dielectric layer through the plurality of openings to form a plurality of etch features therein.06-28-2012
20090124085METHOD FOR FORMING A SEMICONDUCTOR DEVICE HAS A LENGTHENED CHANNEL LENGTH - The present invention discloses a method for forming a semiconductor device. The method includes providing a substrate; forming at least one first opening in the substrate to a predetermined depth and exposing a sidewall of the substrate in the first opening; forming a spacer on the sidewall and exposing a portion of the substrate in the bottom of the first opening; etching the exposed substrate in the bottom of the first opening by using the spacer as a mask to form a second opening; forming an isolation layer in the second opening and a portion of the first opening; forming a gate dielectric layer on the surface of the substrate; and forming a conductive layer covering the substrate.05-14-2009
20130052831METHOD OF PATTERNING HARD MASK LAYER FOR DEFINING DEEP TRENCH - A method of patterning a hard mask layer for defining a deep trench is described. A substrate formed with an isolation structure therein is provided. A hard mask layer is formed over the substrate provided. A patterned photoresist layer is formed over the hard mask layer, having therein a deep-trench opening pattern over the isolation structure. An etching gas not containing hydrogen is used to etch the hard mask layer with the patterned photoresist layer as a mask and thereby transfer the deep-trench opening pattern to the hard mask layer.02-28-2013
20120220131METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor memory device includes forming a photoresist layer on a substrate, performing an exposure process such by illuminating a first area of the photoresist layer with a first amount of a light and illuminating a second area of the photoresist layer with a light of a second amount smaller than the first amount, removing the first area of the photoresist layer to form a photoresist pattern, and forming a capping layer on a surface of the photoresist pattern.08-30-2012
20130059443REDUCTION OF ETCH MICROLOADING FOR THROUGH SILICON VIAS - A method of making a support structure is provided. The method includes depositing a photoresist layer on a substrate of the support structure and patterning the photoresist layer. The method further includes etching the patterned photoresist layer. Etching the patterned photoresist includes forming a first group of through silicon vias (TSVs) configured to electrically connect a first surface of the substrate to a first electrical interface adjacent an opposite second surface of the substrate. Etching the patterned photoresist further includes forming a second group of TSVs configured to conduct thermal energy from the first surface of the substrate to a thermal interface adjacent the second surface of the substrate. A difference in cross-sectional area between TSVs in the first group of TSVs and TSVs in the second group of TSVs is less than 10%, and the first electrical interface is separated from the thermal interface.03-07-2013
20130059442METHOD FOR ADJUSTING TRENCH DEPTH OF SUBSTRATE - A method for adjusting the trench depth of a substrate has the steps as follows. Forming a patterned covering layer on the substrate, wherein the patterned covering layer defines a wider spacing and a narrower spacing. Forming a wider buffering layer arranged in the wider spacing and a narrower buffering layer arranged in the narrower spacing. The thickness of the narrower buffering layer is thinner than the wider buffering layer. Implementing dry etching process to make the substrate corresponding to the wider and the narrower buffering layers form a plurality of trenches. When etching the wider and the narrower buffering layers, the narrower buffering layer is removed firstly, so that the substrate corresponding to the narrower buffering layer will be etched early than the substrate corresponding to the wider buffering layer.03-07-2013
20110014792FIN MASK AND METHOD FOR FABRICATING SADDLE TYPE FIN USING THE SAME - A fin mask for forming saddle type fins in each of active regions formed in an island shape having a certain size with a major axis and a minor axis includes a first fin mask of a line type, and a second fin mask of an island type, wherein the first fin mask and the second fin mask in combination expose saddle type fin regions and cover ends of the neighboring active regions along the major axis.01-20-2011
20120190204NON-CONFORMAL HARDMASK DEPOSITION FOR THROUGH SILICON ETCH - The present invention provides a method to form deep features in a stacked semiconductor structure. Deposition of a non-conformal hardmask onto a patterned topography can form a hardmask to protect all but recessed areas with minimal integration steps. The invention enables etching deep features, even through multiple BEOL layers, without multiple additional process steps.07-26-2012
20110281434Methods of Forming Patterned Photoresist Layers Over Semiconductor Substrates - This invention comprises methods of forming patterned photoresist layers over semiconductor substrates. In one implementation, a semiconductor substrate is provided. An antireflective coating is formed over the semiconductor substrate. The antireflective coating has an outer surface. The outer surface is treated with a basic fluid. A positive photoresist is applied onto the outer surface which has been treated with the basic treating fluid. The positive photoresist is patterned and developed effective to form a patterned photoresist layer having increased footing at a base region of said layer than would otherwise occur in the absence of said treating the outer surface. Other aspects and implementations are contemplated.11-17-2011
20130023122METHOD OF MULTIPLE PATTERNING OF A LOW-K DIELECTRIC FILM - Methods of multiple patterning of low-k dielectric films are described. For example, a method includes forming and patterning a first mask layer above a low-k dielectric layer, the low-k dielectric layer disposed above a substrate. A second mask layer is formed and patterned above the first mask layer. A pattern of the second mask layer is transferred at least partially into the low-k dielectric layer by modifying first exposed portions of the low-k dielectric layer with a first plasma process and removing the modified portions of the low-k dielectric layer. Subsequently, a pattern of the first mask layer is transferred at least partially into the low-k dielectric layer by modifying second exposed portions of the low-k dielectric layer with a second plasma process and removing the modified portions of the low-k dielectric layer.01-24-2013
20130023123METHOD OF REMOVING A PHOTORESIST FROM A LOW-K DIELECTRIC FILM - Methods of removing photoresists from low-k dielectric films are described. For example, a method includes forming and patterning a photoresist layer above a low-k dielectric layer, the low-k dielectric layer disposed above a substrate. Trenches are formed in the exposed portions of the low-k dielectric layer. A plurality of process cycles is performed to remove the photoresist layer. Each process cycle includes forming a silicon source layer on surfaces of the trenches of the low-k dielectric layer, and exposing the photoresist layer to an oxygen source to form an Si—O-containing layer on the surfaces of the trenches of the low-k dielectric layer and to remove at least a portion of the photoresist layer.01-24-2013
20080280447SPIN ON GLASS (SOG) ETCH IMPROVEMENT METHOD - A system and method of preventing pattern lifting during a trench etch/clean process is disclosed. A first layer comprising a first dip is formed over a first via pattern. A trench resist layer is formed. The trench resist layer is patterned with a trench reticle to produce a second via pattern in the trench resist layer over the first via pattern. A photo resist over the first via pattern is opened during a trench processing. Thus, an additional pattern added on a trench pattern reticle is used to open, i.e., remove resist over, a huge via feature area causing under layer dip.11-13-2008
20120289051METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device is provided. According to an embodiment, the method includes forming a layer to be etched on a semiconductor substrate, and forming a photoresist pattern on the layer to be etched. A block copolymer including a hydrophobic radical and a hydrophilic radical is formed in the photoresist pattern, and the block copolymer is assembled to allow a polymer having the hydrophobic radical to be formed in a pillar pattern within a polymer having the hydrophilic radical. The polymer having the hydrophobic radical is then selectively removed.11-15-2012
20120289050METHOD OF ETCHING TRENCHES IN A SEMICONDUCTOR SUBSTRATE UTILIZING PULSED AND FLUOROCARBON-FREE PLASMA - A method of etching trenches in a semiconductor substrate. A patterned hard mask is formed over a semiconductor substrate. Using the patterned hard mask as an etching mask, a plasma etching process is then carried out to etch trenches into the semiconductor substrate not covered by the patterned hard mask, wherein the plasma etching process employs a fluorocarbon-free plasma etching chemistry and is performed under a plasma pulse output mode.11-15-2012
20110294296Using edges of self-assembled monolayers to form narrow features - The present invention provides a method for manufacturing a structure over a semiconductor substrate. To form a trench, a patterned layer is formed on a portion of a substrate such that the patterned layer forms a target area located adjacent an edge of the patterned layer. A self-assembled monolayer (SAM) is coupled to the substrate up to the patterned layer, but excluded from the patterned layer. The substrate is then removed within the target area. A wire is formed in a similar fashion except that the first SAM is exchanged with a second SAM in the target area. Then either the substrate outside of the target area is removed, or conductive metal crystals are grown within the target area. Such structures may be advantageously used in the manufacture of a number of active or passive electronic devices, such as a field effect transistor.12-01-2011
20100120253Post Etch Dielectric Film Re-Capping Layer - Methods for improving post etch in via or trench formation in semiconductor devices. A preferred embodiment comprises forming a re-capping layer over a dielectric film following an initial etch to form a feature in the dielectric film, followed by additional etch and etch back processing steps. The re-capping method provides protection for underlying films and prevents film damage post etch. Uniform feature profiles are maintained and critical dimension uniformity is obtained by use of the methods of the invention. The time dependent dielectric breakdown performance is increased.05-13-2010
20110201204Precisely Tuning Feature Sizes on Hard Masks Via Plasma Treatment - Methods are provided for fabricating devices. A first layer is formed. A hardmask on the first layer is formed. Features on the hardmask are patterned. The sizes of features on the hardmask are reduced by applying a plasma treatment process to form reduced size features. Also, the size of features on the hardmask can be enlarged to form enlarged size features by applying the plasma treatment process and/or removing the oxidized part of the feature during plasma treatment process. Another method may include a first layer formed on a substrate and a second layer formed on the first layer. First features are patterned on the first layer, and second features are patterned on the second layer. A size of second features on the second layer is closed due to the different oxidation rate of the two layers during the plasma treatment process, to form a self-sealed channel and/or self-buried trench.08-18-2011
20110201205METHOD OF FORMING A DEEP TRENCH IN A SUBSTRATE - Methods of forming deep trenches in substrates are described. A method includes providing a substrate with a patterned film disposed thereon, the patterned film including a trench having a first width and a pair of sidewalls, the trench exposing the top surface of the substrate. The method also includes forming a material layer over the patterned film and conformal with the trench. The method also includes etching the material layer to form sidewall spacers along the pair of sidewalls of the trench, the sidewall spacers reducing the first width of the trench to a second width. The method also includes etching the substrate to form a deep trench in the substrate, the deep trench undercutting at least a portion of the sidewall spacers.08-18-2011
20090186486METHOD OF FORMING DAMASCENE PATTERNS OF SEMICONDUCTOR DEVICES - A method of forming damascene patterns of semiconductor devices comprise forming a first insulating layer and contact plugs, formed in the first insulating layer, over a semiconductor substrate, forming an etch barrier layer and a second insulating layer over the first insulating layer, forming damascene patterns in the second insulating layer, forming a mask layer over the second insulating layer of other region except a region in which the contact plugs are formed so that the damascene patterns are exposed through the region in which the contact plugs are formed, removing the etch barrier layer under the exposed damascene patterns using an etching process employing the mask layer, and removing the mask layer.07-23-2009
20090186485SUB-LITHOGRAPHIC PRINTING METHOD - A method to form sub-lithographic trench structures in a substrate and an integrated circuit comprising sub-lithographic trench structures in a substrate. The method includes forming sets of trenches with a lithographic mask and filling the sets of trenches with sets of step spacer blocks comprising two alternating spacer materials which are separately removable from each other. In one embodiment, the trench structures formed are one-nth the thickness of the lithographic mask's feature size. The size of the trench structures being dependent on the thickness and number of spacer material layers used to form the set of step spacer blocks. The number of spacer material layers being n/2 and the thickness of each spacer material layer being one-nth of the lithographic mask's feature size.07-23-2009
20080280448METHOD FOR MANUFACTURING GATE OXIDE LAYER WITH DIFFERENT THICKNESSES - A method of manufacturing gate oxide layers with different thicknesses is disclosed. The method includes that a substrate is provided first. The substrate has a high voltage device region and a low voltage device region. Then, a high voltage gate oxide layer is formed on the substrate. Afterwards, a first wet etching process is performed to remove a portion of the high voltage gate oxide layer in the low voltage device region. Then, a second wet etching process is performed to remove the remaining high voltage gate oxide layer in the low voltage device region. The etching rate of the second wet etching process is smaller than that of the first wet etching process. Next, a low voltage gate oxide layer is formed on the substrate in the low voltage device region.11-13-2008
20080286974Etching solution for multiple layer of copper and molybdenum and etching method using the same - An etching solution for a multiple layer of copper and molybdenum includes: about 5% to about 30% by weight of a hydrogen peroxide; about 0.5% to about 5% by weight of an organic acid; about 0.2% to about 5% by weight of a phosphate; about 0.2% to about 5% by weight of a first additive having nitrogen; about 0.2% to about 5% by weight of a second additive having nitrogen; about 0.01% to about 1.0% by weight of a fluoric compound; and de-ionized water making a total amount of the etching solution 100% by weight.11-20-2008
20080286973METHOD FOR FORMING SEMICONDUCTOR FINE-PITCH PATTERN - A method for forming a fine-pitch pattern on a semiconductor substrate is provided. The method includes patterning the semiconductor substrate to form a plurality of fine lines, forming a thermal oxide layer on the fine lines, polishing the thermal oxide layer to expose a top surface of the fine lines; etching the fine lines using the thermal oxide layer as a mask to expose first portions of the semiconductor substrate, etching a central bottom portion of the thermal oxide layer to expose second portions of the semiconductor substrate, and etching the semiconductor substrate using the etched thermal oxide layer as a mask.11-20-2008
20080305640METHOD FOR PREPARING TRENCH POWER TRANSISTORS - A method for preparing a trench power transistor comprises the steps of forming a mask layer having a plurality of openings on a semiconductor substrate, removing a portion of the semiconductor substrate under the openings to form a plurality of trenches in the semiconductor substrate in an array manner, coating a photoresist layer covering the surface of the mask layer, patterning the photoresist layer, and removing a portion of the mask layer not covered by the photoresist layer to form a mask block exposing a portion of the semiconductor substrate in the array region.12-11-2008
20090156009Method for manufacturing semiconductor device - Provided is a method of manufacturing a semiconductor device capable of providing a stable trench depth, including: forming, on a semiconductor substrate, a first film having a high etching selectivity with respect to the semiconductor substrate; forming, on the first film, a second film having a high etching selectivity with respect to the first film; etching a region of a part of the second film and the first film to expose a surface of the semiconductor substrate in the region; and etching the exposed surface of the semiconductor substrate to form a trench.06-18-2009
20090004868Amorphous silicon oxidation patterning - In one embodiment, a method comprises forming a sacrificial amorphous silicon layer on a semiconductor substrate, forming a hardmask on the amorphous silicon layer, etching one or more lines in the sacrificial amorphous silicon layer, growing oxide structures on the amorphous silicon layer, and forming a trench in the semiconductor substrate between the oxide structures.01-01-2009
20090075483ULTRA LIGHTWEIGHT PHOTOVOLTAIC DEVICE AND METHOD FOR ITS MANUFACTURE - An ultra lightweight semiconductor device such as a photovoltaic device is fabricated on a non-etchable barrier layer which is disposed upon an etchable substrate. The device is contacted with an appropriate etchant for a period of time sufficient to remove at least a portion of the thickness of the substrate. The barrier layer prevents damage to the photovoltaic material during the etching process. Photovoltaic devices fabricated by this method have specific power levels in excess of 300 w/kg.03-19-2009
20090104779Method of producing phase change memory device - An area where a lower electrode is in contact with a variable resistance material needs to be reduced to lower the power consumption of a variable resistance memory device. The present invention is to provide a method of producing a variable resistance memory element whereby the lower electrode can be formed smaller. Combining an anisotropic etching process with an isotropic etching process enables the lower electrode to be formed smaller.04-23-2009
20130122709INVERSE SPACER PROCESSING - A method includes making a target feature of an integrated circuit by providing a main layer over a substrate, depositing a first mask layer over the main layer, patterning the first mask layer, forming sidewall spacers with a width (w) in adjoining sidewalls of the patterned first mask layer and exposing a top area of the patterned first mask layer, selectively removing the first mask layer and exposing a portion of the main layer between the sidewall spacers, depositing a second mask layer over the main layer between the sidewall spacers, selectively removing the sidewall spacers to form an opening and exposing another portion of the main layer in the opening, etching the main layer through the opening to form the target feature.05-16-2013
20100197141NOVEL SELF-ALIGNED STATIC RANDOM ACCESS MEMORY (SRAM) ON METAL GATE - A method for fabricating an integrated circuit providing an enlarged contact process window while reducing device size is disclosed. The method comprises providing a substrate including a first region and a second region, the first and second regions having one or more gate structures including a dummy gate layer; removing the dummy gate layer from at least one of the one or more gate structures in the first and second regions to form one or more trenches in the first and second regions; filling the one or more trenches in the first and second regions with a conductive layer; selectively etching back the conductive layer of the one or more gate structures in the second region of the substrate; forming a protective layer over the etched back conductive layer of the one or more gate structures in the second region; and forming one or more contact openings in the first and second regions.08-05-2010
20110117744PATTERN FORMING METHOD AND PATTERN FORMING APPARATUS - According to one embodiment, a first pattern is formed at first pattern coverage in a first region on a film to be processed and a second pattern is formed at second pattern coverage in a second region on the film to be processed. During the formation of the second pattern, a second film formed of a block copolymer containing film or the like is formed on the film to be processed and is self-assembled. A plurality of kinds of polymers contained in the self-assembled second film are selectively removed to leave at least one kind of polymer to form the second pattern to bring the second coverage close to the first pattern coverage.05-19-2011
20100184295MULTIPLE DEPTH SHALLOW TRENCH ISOLATION PROCESS - A method for manufacturing a semiconductor die may have the steps of:—Providing a semiconductor substrate;—Processing the substrate to a point where shallow trench isolation (STI) can be formed;—Depositing at least one underlayer having a predefined thickness on the wafer;—Depositing a masking layer on top of the underlayer;—Shaping the masking layer to have areas of predefined depths;—Applying a photolithograthy process to expose all the areas where the trenches are to be formed; and—Etching the wafer to form silicon trenches wherein the depth of a trench depends on the location with respect to the masking layer area.07-22-2010
20110003479METHODS OF MAKING SELF-ALIGNED NANO-STRUCTURES - A method for creating structures in a semiconductor assembly is provided. The method includes etching apertures into a dielectric layer and applying a polymer layer over the dielectric layer. The polymer layer is applied uniformly and fills the apertures at different rates depending on the geometry of the apertures, or on the presence or absence of growth accelerating material. The polymer creates spacers for the etching of additional structure in between the spacers. The method is capable of achieving structures smaller than current lithography techniques.01-06-2011
20130217234CLEANING SOLUTION AND DAMASCENE PROCESS USING THE SAME - A cleaning solution is provided. The cleaning solution includes an aliphatic polycarboxylic acid, a chain sulfonic acid substantially less than 4 wt % and an amine containing buffer agent.08-22-2013
20130217233Methods for Controlling Line Dimensions in Spacer Alignment Double Patterning Semiconductor Processing - Methods for forming uniformly spaced and uniformly shaped fine lines in semiconductor processes using double patterning. Dummy lines are formed over a substrate. Sidewall spacer material is deposited over the top and sides of each of the dummy lines. Etching is performed to remove the top surface sidewall spacer material from the tops of the dummy lines. The dummy material is removed by selective etching leaving the spacer material. A photolithographic mask is formed defining inner lines that are desired for a substrate etching step, and temporary lines outside of the desired lines. The temporary lines are partially masked. The temporary lines are partially removed while the inner desired lines are retained. A transfer etch process then patterns an underlying mask layer corresponding to the inner desired lines, and the mask layer is used for etching lines in an underlying semiconductor substrate.08-22-2013
20130137270METHOD FOR FORMING CONTACT HOLE - A method for forming contact holes includes following steps. A substrate including a dense region and an isolation region is provided. A material layer is formed on the substrate. Sacrificed patterns are formed on the material layer in the dense region, wherein there is a first opening between the two adjacent sacrificed patterns. A spacer is formed on each of two sides of each of the sacrificed patterns, wherein the spacers are separated from each other. The sacrificed patterns are removed to form a second opening between two adjacent spacers. A planar layer is formed to fill up the second openings. A first slit is formed in the planar layer, wherein the first slit exposes a portion of the material layer under the second openings. The portion of the material layer exposed by the first slit is removed to form third openings in the material layer.05-30-2013
20110034030METHOD OF FORMING MINUTE PATTERNS IN SEMICONDUCTOR DEVICE USING DOUBLE PATTERNING - A method of forming minute patterns in a semiconductor device, and more particularly, a method of forming minute patterns in a semiconductor device having an even number of insert patterns between basic patterns by double patterning including insert patterns between a first basic pattern and a second basic pattern which are transversely separated from each other on a semiconductor substrate, wherein a first insert pattern and a second insert pattern are alternately repeated to form the insert patterns, the method includes the operation of performing a partial etching toward the second insert pattern adjacent to the second basic pattern, or the operation of forming a shielding layer pattern, thereby forming the even number of insert patterns.02-10-2011
20110244689METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes forming a first mask pattern on a substrate by using a material including a polymer having a protection group de-protectable by an acid, the first mask pattern having a plurality of holes; forming a capping layer on an exposed surface of the first mask pattern, the capping layer including an acid source; diffusing the acid source into the first mask pattern so that the protection group becomes de-protectable from the polymer in the first mask pattern; forming a second mask layer on the capping layer, the second mask layer separate from the first mask pattern and filling the plurality of holes in the first mask pattern; and forming a plurality of second mask patterns in the plurality of holes by removing the capping layer and the first mask pattern.10-06-2011
20110244688METHOD OF PRODUCING MASK - According to one embodiment, a method of producing a mask includes: a step of forming a pattern on a substrate; a step of forming a first film that covers the top surface and side surface of the pattern and contains a first material; a step of forming a second film containing a second material on the first film; a step of performing anisotropic etching of the first and second films in a way that forms a sidewall layer including the first and second films on the side surface of the pattern and removes the first and second films on any location other than the sidewall layer; a step of performing isotropic etching of the first film of the sidewall layer; and a step of removing the pattern.10-06-2011
20110070738DOUBLE PATTERNING STRATEGY FOR CONTACT HOLE AND TRENCH IN PHOTOLITHOGRAPHY - A method of lithography patterning includes forming a hard mask layer on a material layer and forming a capping layer on the hard mask layer. The capping layer does not react with oxygen gas during a photoresist ashing process. The capping layer is patterned by using a first resist pattern and a second resist pattern as etch masks. After the capping layer is patterned, the hard mask layer is patterned by using the patterned capping layer as an etch mask.03-24-2011
20100304569METHOD OF FORMING A CONTACT HOLE - A method of forming a contact hole is provided. A pattern is formed in a photo resist layer. The pattern is exchanged into a silicon photo resist layer to form a first opening. Another pattern is formed in another photo resist layer. The pattern is exchanged into a silicon photo resist layer to form a second opening. The pattern having the first, and second openings is exchanged into the interlayer dielectric layer, and etching stop layer to form the contact hole. The present invention has twice exposure processes and twice etching processes to form the contact hole having small distance.12-02-2010
20090317975METHOD FOR FORMING AN 0N-CHIP HIGH FREQUENCY ELECTRO-STATIC DISCHARGE DEVICE - A method for forming an on-chip high frequency electro-static discharge device is described. In one embodiment, a wafer with a multi-metal level wiring is provided and a hermetically sealed gap is formed therein to provide electro-static discharge protection for an integrated circuit.12-24-2009
20120202349Photo-imageable Hardmask with Dual Tones for Microphotolithography - Disclosed is a method of making polysiloxane and polysilsesquioxane based hardmask respond to radiations with positive tone and negative tone simultaneously. Unradiated films are insoluble in developers, showing positivity tone. Radiated films are insoluble in developers as well, showing negative tone. Only half-way radiated films are soluble in developers. The dual-tone photo-imageable hardmask produces splitted patterns. Compositions of dual-tone photo-imageable hardmask based on the chemistry of polysiloxane and polysilsesquioxanes are disclosed as well. Further disclosed are processes of using photo-imageable hardmasks to create precursor structures on semiconductor substrates with or without an intermediate layer.08-09-2012
20080305639DUAL DAMASCENE PROCESS - A method and system for forming dual damascene structures in a semiconductor package. In one embodiment, the method includes forming an intermediate dielectric layer on a bottom stop layer; forming an ashing removable dielectric layer on the intermediate dielectric layer; forming a patterned photoresist layer above the ashing removable dielectric layer in the semiconductor structure; and defining an in-situ hard mask in the ashing removable dielectric layer having an opening with a profile selected from the group consisting of a via, a trench, or a combination thereof. The profile of the in-situ mask preferably is capable of being transferred to the intermediate dielectric layer by etching.12-11-2008
20110027998Method of Manufacturing A Nano Structure By Etching, Using A Substrate Containing Silicon - A method of manufacturing a nano structure by etching, using a substrate containing Si. A focused Ga ion or In ion beam is irradiated on the surface of the substrate containing Si. The Ga ions or the In ions are injected while sputtering away the surface of the substrate so that a layer containing Ga or In is formed on the surface of the substrate. Dry etching by a gas containing fluorine (F) is performed with the layer containing the Ga or the In formed on the surface of the substrate taken as an etching mask, and the nano structure is formed having a pattern of at least 2 μm tin in depth according to a predetermined line width.02-03-2011
20100285667METHOD TO PRESERVE THE CRITICAL DIMENSION (CD) OF AN INTERCONNECT STRUCTURE - A method of restoring the dielectric constant, loss and leakage of an exposed surface of a low k dielectric material caused during dry etching of the low k dielectric material prior to the removal of the damaged layer by wet etch chemistries is provided. Once restored, the surface of the dielectric material will no longer be susceptible to removal by the highly anisotropic wet etching process. However, the wet etch will still pose an advantage as it can remove any etch/ash residues at the bottom of a feature formed into the low k dielectric material.11-11-2010
20110256726PLASMA ACTIVATED CONFORMAL FILM DEPOSITION - Methods of depositing a film on a substrate surface include surface mediated reactions in which a film is grown over one or more cycles of reactant adsorption and reaction. In one aspect, the method is characterized by the following operations: (a) exposing the substrate surface to a first reactant in vapor phase under conditions allowing the first reactant to adsorb onto the substrate surface; (b) exposing the substrate surface to a second reactant in vapor phase while the first reactant is adsorbed on the substrate surface; and (c) exposing the substrate surface to plasma to drive a reaction between the first and second reactants adsorbed on the substrate surface to form the film.10-20-2011
20100105210Method of making pillars using photoresist spacer mask - A method of making a device includes forming a first hard mask layer over an underlying layer, forming first features over the first hard mask layer, forming a first spacer layer over the first features, etching the first spacer layer to form a first spacer pattern and to expose top of the first features, removing the first features, patterning the first hard mask using the first spacer pattern as a mask to form first hard mask features, removing the first spacer pattern. The method also includes forming second features over the first hard mask features, forming a second spacer layer over the second features, etching the second spacer layer to form a second spacer pattern and to expose top of the second features, removing the second features, etching the first hard mask features using the second spacer pattern as a mask to form second hard mask features, and etching at least part of the underlying layer using the second hard mask features as a mask.04-29-2010
20120309200METHOD FOR FABRICATING A BOTTOM OXIDE LAYER IN A TRENCH - A method for fabricating a bottom oxide layer in a trench (12-06-2012
20120309197METHODS OF FORMING SEMICONDUCTOR STRUCTURES - A method of forming a semiconductor structure includes forming an opening in a substrate. A dielectric layer is formed and substantially conformal to the opening. A sacrificial structure is formed within the opening, covering a portion of the dielectric layer. A portion of the dielectric layer is removed by using the sacrificial structure as an etch mask layer. The sacrificial structure is removed.12-06-2012
20120309196MANUFACTURING METHOD FOR DUAL DAMASCENE STRUCTURE - A manufacturing method for a dual damascene structure includes providing a substrate having a dielectric layer, a first hard mask layer and a second hard mask layer sequentially formed thereon, performing a first double patterning process to sequentially form a plurality of first trench openings and a plurality of second trench openings in the second hard mask layer, performing a second double patterning process to sequentially form a plurality of first via openings and a plurality of second via openings in the fist hard mask layer, and transferring the first trench openings, the second trench openings, the first via openings, and the second via openings to the dielectric layer to form a plurality of dual damascene openings.12-06-2012
20120309201CRITICAL DIMENSION REDUCTION AND ROUGHNESS CONTROL - A method for forming a feature in an etch layer is provided. A photoresist layer is formed over the etch layer. The photoresist layer is patterned to form photoresist features with photoresist sidewalls. A control layer is formed over the photoresist layer and bottoms of the photoresist features. A conformal layer is deposited over the sidewalls of the photoresist features and control layer to reduce the critical dimensions of the photoresist features. Openings in the control layer are opened with a control layer breakthrough chemistry. Features are etched into the etch layer with an etch chemistry, which is different from the control layer break through chemistry, wherein the control layer is more etch resistant to the etch with the etch chemistry than the conformal layer.12-06-2012
20120309199MANUFACTURING METHOD FOR DUAL DAMASCENE STRUCTURE - A manufacturing method for a dual damascene structure first includes providing a substrate having at least a dielectric layer, a first hard mask layer, a first cap layer, a second hard mask layer, and a second cap layer sequentially formed thereon, performing a first double patterning process to form a plurality of first trench openings and second trench openings in the second cap layer and the second hard mask, and the first layer being exposed in bottoms of the first trench openings and the second trench openings, performing a second double patterning process to form a plurality of first via openings and second via openings in the first cap layer and the first hard mask layer, and transferring the first trench openings, the second trench openings, the first via openings, and the second via openings to the dielectric layer to form a plurality of dual damascene openings.12-06-2012
20120309198USE OF SPECTRUM TO SYNCHRONIZE RF SWITCHING WITH GAS SWITCHING DURING ETCH - A method for etching features into an etch layer in a plasma processing chamber is provided. An optically timed deposition phase is provided comprising providing a flow of deposition phase gas, detecting the presence of deposition gas within the plasma processing chamber, providing RF energy for forming a plasma from the deposition phase gas in the plasma processing chamber, and stopping the flow of the deposition gas into the plasma processing chamber. An optically timed etching phase is provided, comprising providing a flow of an etch gas, detecting the presence of the etch gas within the plasma processing chamber, providing RF energy for forming a plasma from the etch gas in the plasma processing chamber, and stopping the flow of the etch gas into the plasma processing chamber.12-06-2012
20120302068METHOD FOR MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT - A method for manufacturing a semiconductor integrated circuit includes providing a substrate having at least a metal hard mask formed thereon. Subsequently a patterning step is performed to the metal hard mask to form a patterned metal hard mask and followed by performing a H11-29-2012
20100120254Passivation Layer for a Circuit Device and Method of Manufacture - According to one embodiment of the disclosure, a method for passivating a circuit device generally includes providing a substrate having a substrate surface, forming an electrical component on the substrate surface, and coating the substrate surface and the electrical component with a first protective dielectric layer. The first protective dielectric layer is made of a generally moisture insoluble material having a moisture permeability less than 0.01 gram/meter05-13-2010
20120064723METHOD FOR FABRICATING SEMICONDUCTOR DEVICE USING DUAL DAMASCENE PROCESS - A method for fabricating a semiconductor device using a dual damascene process is provided. The method includes forming a dielectric layer over a conductive layer, forming a via hole exposing the conducting layer by selectively etching the dielectric layer, projecting a portion of the dielectric layer at an edge of the via hole by selectively etching the dielectric layer to a first depth, and forming a trench by selectively etching the dielectric layer to a second depth, wherein the trench is overlapped with the via hole to form a dual damascene pattern.03-15-2012
20090130853METHOD FOR FABRICATING A DEEP TRENCH IN A SUBSTRATE - The invention provides a method for forming a deep trench in a substrate. A sacrificial layer and a liner layer are first used to define the deep trench pattern. The sacrificial layer is then replaced with a silicon glass layer. A thick mask layer includes the silicon glass layer, the liner layer and a silicon nitride layer is formed on the substrate. Through an opening of the thick mask layer, a deep trench is etched into the substrate.05-21-2009
20120129350METHOD FOR REDUCING WORDLINE BRIDGE RATE - The method of forming a wordline is provided in the present invention. The proposed method includes steps of: (a) etching a metal-silicide layer and a POLY layer via a hard mask, wherein the metal-silicide layer is disposed on the POLY layer; (b) forming a POLY recess in the POLY layer; and (c) forming a liner film covering the metal-silicide layer.05-24-2012
20120214311Process of Multiple Exposures With Spin Castable Films - Methods of multiple exposure in the fields of deep ultraviolet photolithography, next generation lithography, and semiconductor fabrication comprise a spin-castable methodology for enabling multiple patterning by completing a standard lithography process for the first exposure, followed by spin casting an etch selective overcoat layer, applying a second photoresist, and subsequent lithography. Utilizing the etch selectivity of each layer, provides a cost-effective, high resolution patterning technique. The invention comprises a number of double or multiple patterning techniques, some aimed at achieving resolution benefits, as well as others that achieve cost savings, or both resolution and cost savings. These techniques include, but are not limited to, pitch splitting techniques, pattern decomposition techniques, and dual damascene structures.08-23-2012
20120214310WIGGLING CONTROL FOR PSEUDO-HARDMASK - A method for etching features in an etch layer. A conditioning for a patterned pseudo-hardmask of amorphous carbon or polysilicon disposed over the etch layer is provided, where the conditioning comprises providing a fluorine free deposition gas comprising a hydrocarbon gas, forming a plasma from the fluorine free deposition gas, providing a bias less than 500 volts, and forming a deposition on top of the patterned pseudo-hardmask. The etch layer is etched through the patterned pseudo-hardmask.08-23-2012
20120171867METHOD FOR FABRICATING FINE PATTERN BY USING SPACER PATTERNING TECHNOLOGY - A method for fabricating a fine pattern includes forming a line-shaped partition pattern on an underlayer, adhering a first spacer to the sides of the partition pattern, dividing the first spacer into two line patterns where one line pattern has one end bent by selectively etching the first spacer portion with a division region, adhering a second spacer, which has a connection protrusion filling the division region and connecting to the partition pattern, to the outer side of the two line patterns, and selectively removing the two line patterns.07-05-2012
20120077344METHOD OF PATTERNING A LOW-K DIELECTRIC FILM - Methods of patterning low-k dielectric films are described.03-29-2012
20100009542SUBSTRATE PROCESSING METHOD - A substrate processing method that forms an opening, which has a size that fills the need for downsizing a semiconductor device and is to be transferred to an amorphous carbon film, in a photoresist film of a substrate to be processed. Deposit is accumulated on a side wall surface of the opening in the photoresist film using plasma produced from a deposition gas having a gas attachment coefficient S of 0.1 to 1.0 so as to reduce the opening width of the opening.01-14-2010
20120225559CAVITY OPEN PROCESS TO IMPROVE UNDERCUT - A process of forming a MEMS device with a device cavity underlapping an overlying dielectric layer stack having an etchable sublayer over an etch-resistant lower portion, including: etching through at least the etchable sublayer of the overlying dielectric layer stack in an access hole to expose a lateral face of the etchable sublayer, covering exposed surfaces of the etchable sublayer by protective material, and subsequently performing a cavity etch. A cavity etch mask may cover the exposed surfaces of the etchable sublayer. Alternatively, protective sidewalls may be formed by an etchback process to cover the exposed surfaces of the etchable sublayer. Alternatively, the exposed lateral face of the etchable sublayer may be recessed by an isotropic etch, than isolated by a reflow operation which causes edges of an access hole etch mask to drop and cover the exposed lateral face of the etchable sublayer.09-06-2012
20120083126METHOD FOR FORMING SEMICONDUCTOR DEVICE - A method for forming a semiconductor device includes forming a partition line pattern and a partition pad pattern connected to an end part of the partition line pattern over the semiconductor substrate. Spacer insulation layers are formed at sidewalls of the partition line pattern and the partition pad pattern. A gap-filling layer is formed between the spacer insulation layers. A first cutting mask pattern is formed to expose a connecting part between the partition line pattern and the partition pad pattern. The partition line pattern and the gap-filling layer adjacent to the spacer insulation layer are removed using the first cutting mask pattern as a mask. A second cutting mask pattern including a first pattern and a second pattern are formed. The spacer insulation layer is removed using the second cutting mask pattern as a mask to form a gate trench in the substrate.04-05-2012
20120322267METHOD OF PATTERNING A SUBSTRATE - In various embodiments, a method of patterning a substrate may include: forming an auxiliary layer on or above a substrate and forming a plasma etch mask layer on or above the auxiliary layer, wherein the auxiliary layer is configured such that it may be removed from the substrate more easily than the plasma etch mask layer; patterning the plasma etch mask layer and the auxiliary layer such that at least a portion of the substrate is exposed; patterning the substrate by means of a plasma etch process using the patterned plasma etch mask layer as a plasma etch mask.12-20-2012
20090017630Methods For Forming Contacts For Dual Stress Liner CMOS Semiconductor Devices - Semiconductor fabrication methods to forma of via contacts in DSL (dual stress liner) semiconductor devices are provided, in which improved etching process flows are implemented to enable etching of via contact openings through overlapped and non-overlapped regions of the dual stress liner structure to expose underlying salicided contacts and other device contacts, while mitigating or eliminating defect mechanisms such as over etching of contact regions underlying non-overlapped regions of the DSL.01-15-2009
20120264306Method of Forming Opening on Semiconductor Substrate - The present invention provides a method of forming an opening on a semiconductor substrate. First, a substrate is provided. Then a dielectric layer and a cap layer are formed on the substrate. A ratio of a thickness of the dielectric layer and a thickness of the cap layer is substantially between 15 and 1.5. Next, a patterned boron nitride layer is formed on the cap layer. Lastly, an etching process is performed by using the patterned hard mask as a mask to etch the cap layer and the dielectric layer so as to form an opening in the cap layer and the dielectric layer.10-18-2012
20120094497METHOD OF FABRICATING SEMICONDUCTOR DEVICE - The present method includes: forming a device isolation region in a substrate dividing the device isolation region into first and second diffusion regions; forming a target film to be processed on the substrate; forming a hard mask layer and a first resist layer on the film; forming a first pattern on the first resist layer; etching the hard mask layer using the first pattern as a mask; forming a second resist layer on the hard mask layer; forming a second pattern including a first space on the second resist layer isolating the first pattern; forming a third pattern including a second space shrunk from the first space on the hard mask layer by carrying out size conversion etching by using the second pattern formed on the second resist layer as a mask; and etching the film to be processed by using the third pattern formed on the hard mask layer.04-19-2012
20120276744Patterning Method for High Density Pillar Structures - A method of making a device includes forming a first photoresist layer over a sacrificial layer, patterning the first photoresist layer to form first photoresist features, rendering the first photoresist features insoluble to a solvent, forming a second photoresist layer over the first photoresist features, patterning the second photoresist layer to form second photoresist features, forming a spacer layer over the first and second photoresist features, etching the spacer layer to form spacer features and to expose the first and second photoresist features, forming third photoresist features between the spacer features, removing the spacer features, and patterning the sacrificial layer using the first, second and third photoresist features as a mask to form sacrificial features.11-01-2012
20100048024MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A manufacturing method of semiconductor device comprises: sequentially laminating a third mask layer, a second mask layer, and a first mask layer on a processed layer; forming a fourth mask layer on the first mask layer; processing the first mask layer so as to have a line pattern form using the fourth mask layer as a mask; removing the first mask layer; processing the second mask layer so as to have a pair of line pattern forms using the pair of sidewall layers as a mask; forming a fifth mask layer on the third mask layer; forming a pair of opening portions in the third mask layer using the fifth mask layer as a mask; and forming a pair of groove portions on the processed layer using the third mask layer as a mask.02-25-2010
20100048023Methods for Manufacturing a Structure on a Substrate and Intermediate Product - Among other implementations, a method for manufacturing a structure on a substrate is described wherein at least one carrier structure is positioned on a substrate and at least one spacer structure is positioned on the sidewalls of the at least one carrier structure, the at least one carrier structure or the at least one spacer structure is subsequently removed and before or after the removal of the at least one spacer structure or the removal of the at least one carrier structure, an etch resistant layer is positioned in at least one of the following regions: a region not covered by the at least one carrier structure, a region not covered by the at least one spacer structure and a region not covered by the at least one carrier structure and the at least one spacer structure.02-25-2010
20130012026METHODOLOGY FOR FABRICATING ISOTROPICALLY RECESSED SOURCE AND DRAIN REGIONS OF CMOS TRANSISTORS - A method for fabricating recessed source and recessed drain regions of aggressively scaled CMOS devices. In this method a processing sequence of plasma etch, deposition, followed by plasma etch is used to controllably form recessed regions of the source and the drain in the channel of a thin body, much less than 40 nm, device to enable subsequent epitaxial growth of SiGe, SiC, or other materials, and a consequent increase in the device and ring oscillator performance. A Field Effect Transistor device is also provided, which includes: a buried oxide layer; a silicon layer above the buried oxide layer; an isotropically recessed source region; an isotropically recessed drain region; and a gate stack which includes a gate dielectric, a conductive material, and a spacer.01-10-2013
20120149205METHOD FOR FABRICATING SIDE CONTACT IN SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes etching a substrate to form a body separated by a trench, forming liner layers that cover sidewalls of the body, forming a sacrificial layer that fills the trench and exposes an upper sidewall of each liner layer, forming a hard mask pattern that covers a first one of the liner layers having the exposed upper sidewalls, forming a barrier layer to be selectively grown over the exposed upper sidewalls of a second one of the liner layers, removing the hard mask pattern, removing a part of the sacrificial layer to expose a lower sidewall of a first one of the liner layers, and removing the lower sidewall of the first one of the liner layers to form a side contact.06-14-2012
20130115775METHOD OF FORMING WIDE TRENCHES USING A SACRIFICIAL SILICON SLAB - A method of forming an encapsulated wide trench includes providing a silicon on oxide insulator (SOI) wafer, defining a first side of a first sacrificial silicon slab by etching a first trench in a silicon layer of the SOI wafer, defining a second side of the first sacrificial silicon slab by etching a second trench in the silicon layer, forming a first sacrificial oxide portion in the first trench, forming a second sacrificial oxide portion in the second trench, forming a polysilicon layer above the first sacrificial oxide portion and the second sacrificial oxide portion, and etching the first sacrificial oxide portion and the second sacrificial oxide portion.05-09-2013
20130130502MICROMECHANICAL MEMBRANES AND RELATED STRUCTURES AND METHODS - Micromechanical membranes suitable for formation of mechanical resonating structures are described, as well as methods for making such membranes. The membranes may be formed by forming cavities in a substrate, and in some instances may be oxidized to provide desired mechanical properties. Mechanical resonating structures may be formed from the membrane and oxide structures.05-23-2013
20110275218DOUBLE PATTERNING STRATEGY FOR CONTACT HOLE AND TRENCH IN PHOTOLITHOGRAPHY - A method of lithography patterning includes forming a hard mask layer on a material layer and forming a capping layer on the hard mask layer. The capping layer does not react with oxygen gas during a photoresist ashing process. The capping layer is patterned by using a first resist pattern and a second resist pattern as etch masks. After the capping layer is patterned, the hard mask layer is patterned by using the patterned capping layer as an etch mask.11-10-2011
20100317195METHOD FOR FABRICATING AN APERTURE - A method for fabricating an aperture is disclosed. The method includes the steps of: depositing a dielectric layer and a hard mask on surface of a semiconductor substrate; patterning the hard mask by forming an aperture in the hard mask; utilizing a gas containing C12-16-2010
20130157467METHOD FOR FORMING SEMICONDUCTOR DEVICE - A method of patterning a material layer of a semiconductor device is disclosed, the method including treating a material layer above a semiconductor substrate with plasma oxygen; depositing a layer of photoresist over a first surface of the material layer after the treating of the material layer; patterning the layer of photoresist, thereby forming a patterned photoresist, exposing portions of the material layer; etching the exposed portions of at least the material layer to form at least one contact via in the material layer extending to a source or drain region of a device at a surface of the substrate; and removing the patterned photoresist from the first surface of the material layer.06-20-2013
20120282777METHOD FOR INCREASING ADHESION BETWEEN POLYSILAZANE AND SILICON NITRIDE - A method for increasing adhesion between polysilazane and silicon nitride is disclosed, comprising, providing a substrate comprising a trench, forming a silicon nitride liner layer on a bottom surface and a sidewall of the trench, performing a treating process to the silicon nitride liner layer for producing a hydrophilic surface with OH groups that can increase adhesion between the silicon nitride liner layer and a subsequently formed polysilazane coating layer, and forming a polysilazane coating layer into the trench and on the silicon nitride liner layer.11-08-2012
20120021606PROCESS FOR PRODUCING TWO INTERLEAVED PATTERNS ON A SUBSTRATE - A process for producing two interleaved patterns on a substrate uses photolithography and etching to produce, on the substrate, a first pattern of first material protruding regions separated by recessed regions. A non-conformal deposition of a second material on the first pattern forms cavities in the recessed regions of the first pattern. These cavities are opened and filled with a third material. The second material is then removed, and the remaining third material forms a second pattern of third material protruding regions, wherein the second pattern is interleaved with the first pattern.01-26-2012
20120021605SEMICONDUCTOR DEVICE PRODUCING METHOD - In a semiconductor device producing method according to one embodiment, an insulating film containing silicon is formed on a semiconductor substrate, a resist is deposited on the insulating film, the resist is patterned into a predetermined pattern, and the insulating film is processed by a dry etching treatment in which gas containing C, F, Br, H, and O is used with the resist having the predetermined pattern as a mask. A deposited film in which C and Br are coupled is produced on the resist.01-26-2012

Patent applications in class Plural coating steps