Class / Patent application number | Description | Number of patent applications / Date published |
438701000 | Tapered configuration | 26 |
20080207000 | METHOD OF MAKING HIGH-ASPECT RATIO CONTACT HOLE - A substrate has thereon a conductive region to be partially exposed by the contact hole, a contact etch stop layer overlying the substrate and covering the conductive region, and an inter-layer dielectric (ILD) layer on the contact etch stop layer. A photoresist pattern is formed on the ILD layer. The photoresist pattern has an opening directly above the conductive region. Using the photoresist pattern as an etch hard mask and the contact etch stop layer as an etch stop, an anisotropic dry etching process is performed to etch the ILD layer through the opening, thereby forming an upper hole region. The photoresist pattern is removed. An isotropic dry etching process is performed to dry etching the contact etch stop layer selective to the ILD layer through the upper hole region, thereby forming a widened, lower contact bottom that exposes an increased surface area of underlying conductive region. | 08-28-2008 |
20080242096 | METHOD FOR PREPARING BOTTLE-SHAPED DEEP TRENCHES - A method for preparing a bottle-shaped deep trench first forms a first mask with at least one opening on a substrate including a first epitaxy layer, an insulation layer on the first epitaxy layer and a second epitaxy layer on the insulation layer. A first etching process is performed to remove a portion of the substrate under the opening down to the interior of the insulation layer to form a trench, and a thermal treating process is then performed to form a second mask on the inner sidewall of the trench. Subsequently, a second etching process is performed to remove a portion of the substrate under the opening down to the interior of the first epitaxy layer to form a deep trench, and a third etching process is performed to remove a portion of the first epitaxy layer so as to form the bottle-shaped deep trench with an enlarged surface. | 10-02-2008 |
20080254632 | Method for forming a semiconductor structure having nanometer line-width - A method for forming a semiconductor structure having a deep sub-micron or nano scale line-width is disclosed. Structure consisting of multiple photoresist layers is first formed on the substrate, then patterned using adequate exposure energy and development condition so that the bottom photoresist layer is not developed while the first under-cut resist groove is formed on top of the bottom photoresist layer. Anisotropic etching is then performed at a proper angle to the normal of the substrate surface, and a second resist groove is formed by the anisotropic etching. Finally, the metal evaporation process and the lift-off process are carried out and the Γ-shaped metal gate with nano scale line-width can be formed. | 10-16-2008 |
20080280446 | METHOD OF PRODUCING A MICROSCOPIC HOLE IN A LAYER AND INTEGRATED DEVICE WITH A MICROSCOPIC HOLE IN A LAYER - A microscopic hole is produced in a dielectric layer having a dielectric first material, a first surface and a second surface. In one embodiment, the tapered through-hole is etched from the second surface of the layer to the first surface of the layer. The tapered hole provides a first cross section near the first surface of the dielectric layer and a second cross section near the second surface of dielectric layer. A cladding is deposited at the inner surface of the through-hole. The cladding includes a second material and provides a thickness decreasing from the second surface to the first surface. | 11-13-2008 |
20090053898 | Formation of a slot in a silicon substrate - A slot is formed that reaches through a first side of a silicon substrate to a second side of the silicon substrate. A trench is laser patterned. The trench has a mouth at the first side of the silicon substrate. The trench does not reach the second side of the silicon substrate. The trench is dry etched until a depth of at least a portion of the trench is extended approximately to the second side of the silicon substrate ( | 02-26-2009 |
20090061635 | METHOD FOR FORMING MICRO-PATTERNS - A method for forming micro-patterns is disclosed. The method forms a sacrificial layer and a mask layer. A plurality of first taper trenches is formed in the sacrificial layer. A photoresist layer is filled in the plurality of first taper trenches. The photoresist layer is used as a mask and a plurality of second taper trenches is formed in the sacrificial layer. Then, the photoresist layer is stripped to be capable of patterning a layer by the first taper trenches and the second taper trenches in the sacrificial layer. Therefore, a patterned sacrificial layer duplicating the line density by double etching is formed. | 03-05-2009 |
20090087992 | METHOD OF MINIMIZING VIA SIDEWALL DAMAGES DURING DUAL DAMASCENE TRENCH REACTIVE ION ETCHING IN A VIA FIRST SCHEME - A method of minimizing undercut of a hard mask in an integrated circuit (IC) structure including steps of providing an IC structure having a substrate, a interlayer dielectric layer, and a hard mask, forming a via in said IC structure, and depositing an organic planarizing layer (OPL) over the IC structure such that it fills the vias formed therein. The method also includes steps of forming a masking structure layer over the OPL, forming an opening in the masking structure that has a critical dimension (CD) smaller than an opening design dimension, anisotropic etching the OPL such that sidewall of the via remains covered with the OPL while forming a trench, and removing any remaining OPL on the sidewalls and trench, wherein the undercut of the sidewalls with respect to the hard mask is minimized by the covering of OPL during the anisotropic etching process. | 04-02-2009 |
20090093122 | Method For Producing Group III-V Nitride Semiconductor Substrate - The present invention provides a method for producing a group III-V nitride semiconductor substrate. The method for producing a group III-V nitride semiconductor substrate comprises the steps of (I-1) to (I-6): (I-1) placing inorganic particles on a template, (I-2) dry-etching the template by using the inorganic particles as an etching mask, to form convexes on the template, (I-3) forming a coating film for an epitaxial growth mask on the template, (I-4) removing the inorganic particles to form an exposed surface of the template, (I-5) growing a group III-V nitride semiconductor on the exposed surface of the template, and (I-6) separating the group III-V nitride semiconductor from the template. | 04-09-2009 |
20090111271 | ISOTROPIC SILICON ETCH USING ANISOTROPIC ETCHANTS - Methods for isotropically etching a monocrystalline silicon wafer. An example method includes applying a layer of material at least one of onto a first side or into a first side of the monocrystalline silicon wafer and isotropically etching a non-linear pit into the monocrystalline silicon wafer using an anisotropic etchant. The applied layer of material has a faster etch rate than the monocrystalline silicon wafer. | 04-30-2009 |
20090209107 | METHOD OF FORMING AN ELECTRONIC DEVICE INCLUDING FORMING FEATURES WITHIN A MASK AND A SELECTIVE REMOVAL PROCESS - A method of forming an electronic device can include forming a patterned mask layer overlying a underlying layer such that the mask layer has a first feature, a second feature, and a third feature, and the first feature is between the second feature and the third feature. The first feature can be spaced apart from the second feature by a first opening in the mask layer, and can be spaced apart from the third feature by a second opening in the mask layer. The method can further include selectively removing portions of the underlying layer under the first opening, the second opening, the second feature, and the third feature, and also removing the second feature and the third feature while leaving substantially all of the first feature and a significant portion of the underlying layer under the first feature. | 08-20-2009 |
20100003823 | Method for Forming Trenches with Wide Upper Portion and Narrow Lower Portion - A method for forming a semiconductor structure includes the following steps. A hard mask layer is formed over a semiconductor region. The hard mask layer has inner portions that are thinner than its outer portions, and the inner portions define an exposed surface area of the semiconductor region. A portion of the semiconductor region is removed through the exposed surface area of the semiconductor region. The thinner portions of the hard mask layer are removed to expose surface areas of the semiconductor region underlying the thinner portions. An additional portion of the semiconductor region is removed through all exposed surface areas of the semiconductor region thereby forming a trench having an upper portion that is wider than its lower portion. | 01-07-2010 |
20100029084 | PATTERN FORMING METHOD AND PATTERN FORMING DEVICE - A pattern size is arbitrarily adjusted with the use of the same template in imprint lithography. A pattern forming method includes: applying droplets onto a substrate; forming a light curing organic film by bringing a template into contact with the droplets, the template having a pattern formed with protrusions and grooves; adjusting and keeping the distance between the template and the substrate at a predetermined value; forming a cured organic film including organic film convex portions and organic film concave portions each having a predetermined film thickness by curing the light curing organic film through exposure to ultraviolet light, the organic film convex portions and the organic film concave portions corresponding to the grooves and protrusions of the template; detaching the template from the cured organic film; and forming a resist pattern by performing etching to turn each of the organic film concave portions into a tapered shape under such conditions as to obtain a predetermined taper angle, the resist pattern having openings each having a smaller width than the protrusions of the template. | 02-04-2010 |
20100190346 | Method of processing resist, semiconductor device, and method of producing the same - A surface component film ( | 07-29-2010 |
20120244710 | Shrinkage of Critical Dimensions in a Semiconductor Device by Selective Growth of a Mask Material - In sophisticated semiconductor devices, manufacturing techniques and etch masks may be formed on the basis of a mask layer stack which comprises an additional mask layer, which may receive an opening on the basis of lithography techniques. Thereafter, the width of the mask opening may be reduced by applying a selective deposition or growth process, which thus results in a highly uniform and well-controllable adjustment of the target width of the etch mask prior to performing the actual patterning process, for instance for forming sophisticated contact openings, via openings and the like. | 09-27-2012 |
20120309195 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a high-quality semiconductor device having stable characteristics is provided. The method for manufacturing the semiconductor device includes the steps of: preparing a silicon carbide layer having a main surface; forming a trench in the main surface by removing a portion of the silicon carbide layer; and removing a portion of a side wall of the trench by thermal etching. | 12-06-2012 |
20140273465 | METHOD OF FORMING DUAL GATE OXIDE - A method of forming a dual gate oxide is disclosed which includes: providing a silicon substrate; depositing a first silicon oxide film over the silicon substrate; coating a photoresist over the first silicon oxide film; exposing and developing the photoresist to expose a portion of the first silicon oxide film; coating a crosslinking agent containing amine compound or polyamine compound on the photoresist and performing a heat curing process, thereby forming a protective layer of crosslinked macromolecules over the photoresist; removing the remaining crosslinking agent; performing a wet etching process to reduce a thickness of, or completely remove, the exposed portion of the first silicon oxide film; removing the photoresist and the protective layer formed thereon; and depositing a second silicon oxide film. | 09-18-2014 |
20140273466 | LOCAL AND GLOBAL REDUCTION OF CRITICAL DIMENSION (CD) ASYMMETRY IN ETCH PROCESSING - Local and global reduction of critical dimension (CD) asymmetry in etch processing is described. In an example, a method of etching a wafer of to form a plurality of staircase structures with reduced local and global asymmetry involves forming a photoresist layer on a plurality of micron-scale semiconductor structures. The photoresist layer is then trimmed with a high pressure and pulsed plasma etch process performed in a reverse MESA mode. | 09-18-2014 |
20140322915 | SEMICONDUCTOR DEVICE HAVING HARD MASK STRUCTURE AND FINE PATTERN AND FORMING METHOD THEREOF - A method for fabricating a semiconductor device includes forming a plurality of first hard mask patterns separated by a plurality of trenches on a target layer, forming a plurality of second hard mask patterns filling the plurality of trenches, forming a plurality of first opening units in the plurality of second hard mask patterns, forming a plurality of second opening units in the plurality of first hard mask patterns and forming a plurality of patterns using the plurality of first opening units and the plurality of second opening units, which are transferred by etching the target layer. | 10-30-2014 |
20140349487 | Methods of Etching Trenches into Silicon of a Semiconductor Substrate, Methods of Forming Trench Isolation in Silicon of a Semiconductor Substrate, and Methods of Forming a Plurality of Diodes - A method of etching trenches into silicon of a semiconductor substrate includes forming a mask over silicon of a semiconductor substrate, with the mask comprising trenches formed there-through. Plasma etching is conducted to form trenches into the silicon of the semiconductor substrate using the mask. In one embodiment, the plasma etching includes forming an etching plasma using precursor gases which include SF | 11-27-2014 |
20140370710 | METHOD FOR MANUFACTURING ELECTRONIC DEVICE - A method includes the stage of partially removing a first insulator layer to form an opening passing through the first insulator layer by plasma etching using a gas of a first type, and the stage of partially removing a second insulator layer to form an opening passing through the second insulator layer by plasma etching using a gas of a second type. The gas of a first type contains a first component capable of etching the first insulator layer, and a gas of the second type contains a second component different from the first component, capable of etching the second insulator layer and a third component having a higher deposition ability than the second component. | 12-18-2014 |
20150118849 | MANUFACTURING METHOD OF SEMICONDUCTOR SUBSTRATE - A trench is etched in a semiconductor wafer by turning a first introduced gas introduced into a reaction chamber into plasma. A protection film is formed on a wall surface of the trench by turning a second introduced gas introduced into the reaction chamber into plasma. The protection film formed on a bottom surface of the trench is removed by turning a third introduced gas introduced into the reaction chamber into plasma. The reaction chamber is evacuated after the protection film formed on the bottom surface of the trench is removed. | 04-30-2015 |
20150303099 | VIA-HOLE ETCHING METHOD - The present invention discloses a via-hole etching method related to semiconductor manufacturing field, and the method overcomes the defects of an uncontrollable end point of a via-hole and an unfavorable profile-angle in a conventional via-hole etching method. The via-hole etching method includes: forming a structure for via-hole etching, includes: a low-temperature poly-silicon layer, a gate insulating layer, a gate metal layer and an interlayer insulating layer, which are sequentially formed on a substrate; forming a mask layer comprising a via-hole masking pattern on the structure for via-hole etching; by using a first etching process, etching the structure for via-hole etching to a first thickness of the gate insulating layer; by using a second etching process, etching the structure for via-hole etching to etch away the remaining thickness of the gate insulating layer, and uncovering the low-temperature poly-silicon layer; removing the mask layer to form a via-hole structure. | 10-22-2015 |
20160013071 | METHOD OF MAKING A SEMICONDUCTOR DEVICE USING MULTIPLE LAYER SETS | 01-14-2016 |
20160020088 | METHOD OF MAKING A SEMICONDUCTOR DEVICE USING A BARRIER AND ANTIREFLECTIVE COATING (BARC) LAYER - A method of forming a semiconductor device includes forming a dielectric layer over a substrate. The method includes forming a layer set over the dielectric layer, wherein the layer set comprises a plurality of layers. The method further includes forming a bottom antireflective coating (BARC) layer over the layer set. The method further includes etching the layer set to form a tapered opening in the layer set, wherein etching the layer set comprises etching at least one layer comprising a silicon-rich photoresist material layer and a second material layer different from the silicon-rich photoresist material, and the tapered opening has sidewalls at an angle with respect to a top surface of the dielectric layer. The method further includes etching the dielectric layer using the layer set as a mask to form an opening in the dielectric layer, wherein etching the dielectric layer comprises reducing a thickness of the layer set. | 01-21-2016 |
20160197009 | Device and Method for Stopping an Etching Process | 07-07-2016 |
20170236717 | UNIFORM DIELECTRIC RECESS DEPTH DURING FIN REVEAL | 08-17-2017 |