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Combined with coating step

Subclass of:

438 - Semiconductor device manufacturing: process

438689000 - CHEMICAL ETCHING

Patent class list (only not empty are listed)

Deeper subclasses:

Class / Patent application numberDescriptionNumber of patent applications / Date published
438703000 Plural coating steps 217
438700000 Formation of groove or trench 174
438696000 Coating of sidewall 63
438697000 Planarization by etching and coating 20
438695000 Simultaneous etching and coating 11
Entries
DocumentTitleDate
20110183520Method for Removing Copper Oxide Layer - The invention is directed to a method for removing copper oxide from a copper surface to provide a clean copper surface, wherein the method involves exposing the copper surface containing copper oxide thereon to an anhydrous vapor containing a carboxylic acid compound therein, wherein the anhydrous vapor is generated from an anhydrous organic solution containing the carboxylic acid and one or more solvents selected from hydrocarbon and ether solvents.07-28-2011
20100062603SEMICONDUCTOR DEVICES SUITABLE FOR NARROW PITCH APPLICATIONS AND METHODS OF FABRICATION THEREOF - Semiconductor devices suitable for narrow pitch applications and methods of fabrication thereof are described herein. In some embodiments, a semiconductor device may include a floating gate having a first width proximate a base of the floating gate that is greater than a second width proximate a top of the floating gate. In some embodiments, a method of shaping a material layer may include (a) oxidizing a surface of a material layer to form an oxide layer at an initial rate; (b) terminating formation of the oxide layer when the oxidation rate is about 90% or below of the initial rate; (c) removing at least some of the oxide layer by an etching process; and (d) repeating (a) through (c) until the material layer is formed to a desired shape. In some embodiments, the material layer may be a floating gate of a semiconductor device.03-11-2010
20090258497PHOTORESIST RESIN, AND METHOD FOR FORMING PATTERN AND METHOD FOR MANUFACTURING DISPLAY PANEL USING THE SAME - A photoresist resin composition, a method for forming a pattern and a method for manufacturing a display panel using the photoresist resin composition are disclosed. The photoresist resin composition includes an alkali soluble resin, a photoresist compound, and a solvent, wherein the alkali soluble resin includes a first polymer resin represented by the following Chemical Formula 1, wherein, of R10-15-2009
20120184102Method for smoothing group lll nitride semiconductor substrate - The invention discloses a smoothing method to decrease bowing of group III nitride semiconductor substrate. The certain face of group III nitride semiconductor substrates is etched under the appropriate etching recipe and time, the certain morphology such as rod-type and other structures are appeared at the certain face. And such structures releases the compressive stresses at these certain faces, resulting in clearly increasing the bowing radius of the group III nitride semiconductor substrates, finally decreasing the bowing phenomenon of the group III nitride semiconductor substrate.07-19-2012
20100159700Method for Fabricating Cylinder Type Capacitor - A method for fabricating a cylinder type capacitor includes forming connection contacts passing through a lower layer over a semiconductor substrate; forming a mold layer covering the connection contacts; forming a first floated pinning layer with a stress in a first direction over the mold layer; forming a second floated pinning layer for stress relief with a stress in a second direction over the first floated pinning layer, said second direction being opposite to the first direction; forming opening holes passing through the first and second floated pinning layers and the mold layer and exposing the connection contacts; forming storage nodes following a profile of the opening holes; removing portions of the first and second floated pinning layers to form a floated pinning layer pattern, the floated pinning layer pattern exposing a portion of the mold layer and contacting upper tips of the storage nodes; exposing outer walls of the storage nodes by selectively removing the exposed mold layer; and forming a dielectric layer and an upper electrode over the storage node.06-24-2010
20090017625Methods For Removing Gate Sidewall Spacers In CMOS Semiconductor Fabrication Processes - Semiconductor fabrication processes are provided for removing sidewall spacers from gate structures while mitigating or otherwise preventing defect mechanisms such as damage to metal silicide structures or otherwise impeding or placing limitations on subsequent process flows.01-15-2009
20090075482PROCESS FOR FORMING A PATTERN INCLUDING ON A SEMICONDUCTOR DEVICE - An objective of this invention is to prevent resist poisoning and sensitivity deterioration in a chemically amplified resist. The chemically amplified resist comprises a base resin, a photoacid generator and a salt exhibiting buffer effect in the base resin.03-19-2009
20120244707METHOD OF CORRECTING MASK PATTERN, COMPUTER PROGRAM PRODUCT, MASK PATTERN CORRECTING APPARATUS, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - In the method of correcting a mask pattern according to the embodiments, a mask pattern correction amount for a reference flare value is calculated as a reference mask correction amount, for every type of patterns within the layout, and a change amount of the mask pattern correction amount corresponding to the change amount of the flare value is calculated as the change amount information. A mask pattern corresponding to the flare value of the pattern is created based on the reference mask correction amount and the change amount information corresponding to the pattern, extracted from the information having the pattern, the reference mask correction amount, and the change amount information correlated with each other, and based on a difference between the flare value of the pattern and the reference flare value.09-27-2012
20130084703RESTRICTED STRESS REGIONS FORMED IN THE CONTACT LEVEL OF A SEMICONDUCTOR DEVICE - In sophisticated semiconductor devices, an efficient stress decoupling may be accomplished between neighboring transistor elements of a densely packed device region by providing a gap or a stress decoupling region between the corresponding transistors. For example, a gap may be formed in the stress-inducing material so as to reduce the mutual interaction of the stress-inducing material on the closely spaced transistor elements. In some illustrative aspects, the stress-inducing material may be provided as an island for each individual transistor element.04-04-2013
20130034960METHOD OF FABRICATING A SEMICONDUCTOR DEVICE - The present invention discloses a method of fabricating a semiconductor device. In the present invention, after the formation of a photo-resist mask on a substrate, the photo-resist is subjected to a plasma pre-treatment, and then etch is conducted. With the plasma pre-treatment, a line width roughness of a linear pattern of the photo-resist can be improved, and thus much better linear patterns can be formed on the substrate during the subsequent etching steps.02-07-2013
20130210230METHOD FOR PROVIDING ELECTRICAL CONNECTIONS TO SPACED CONDUCTIVE LINES - An integrated circuit and a method of formation provide a contact area formed at an angled end of at least one linearly extending conductive line. In an embodiment, conductive lines with contact landing pads are formed by patterning lines in a mask material, cutting at least one of the material lines to form an angle relative to the extending direction of the material lines, forming extensions from the angled end faces of the mask material, and patterning an underlying conductor by etching using said material lines and extension as a mask. In another embodiment, at least one conductive line is cut at an angle relative to the extending direction of the conductive line to produce an angled end face, and an electrical contact landing pad is formed in contact with the angled end face.08-15-2013
20130210229SILICON-CONTAINING SURFACE MODIFIER, RESIST LOWER LAYER FILM-FORMING COMPOSITION CONTAINING THE SAME, AND PATTERNING PROCESS - The present invention provides a silicon-containing surface modifier containing one or more repeating units each represented by the following general formula (A), or one or more partial structures each represented by the following general formula (C):08-15-2013
20090075481METHOD OF FABRICATING SEMICONDUCTOR SUBSTRATE BY USE OF HETEROGENEOUS SUBSTRATE AND RECYCLING HETEROGENEOUS SUBSTRATE DURING FABRICATION THEREOF - The invention discloses a method of fabricating a first substrate and a method of recycling a second substrate during fabrication of the first substrate. The second substrate is heterogeneous for the first substrate. First, the fabricating method according to the invention is to prepare the second substrate. Subsequently, the fabricating method is to deposit a buffer layer on the second substrate. Then, the fabricating method is to deposit a semiconductor material layer on the buffer layer. The buffer layer assists the epitaxial growth of the semiconductor material layer, and serves as a lift-off layer. Finally, with an etching solution, the fabricating method is to only etch the lift-off layer to debond the second substrate away from the semiconductor material layer, where the semiconductor material layer serves as the first substrate.03-19-2009
20090163026IMMERSION LITHOGRAPHY WAFER EDGE BEAD REMOVAL FOR WAFER AND SCANNER DEFECT PREVENTION - A method of performing a single step/single solvent edge bead removal (EBR) process on a photolithography layer stack including a photoresist layer and a top coat layer using propylene glycol monomethyl ether acetate (PGMEA) or a mixture of PGMEA and gamma-butyrolactone (GBL) is disclosed. The single step/single solvent EBR process is compatible with organic and inorganic BARC layers.06-25-2009
20100105207METHOD FOR FORMING FINE PATTERN OF SEMICONDUCTOR DEVICE - A method for forming a fine pattern of a semiconductor device includes forming an insulating layer and an etch layer over a semiconductor substrate, coating a photoresist layer over the etch layer, forming a photoresist pattern by performing a photolithography process for the photoresist layer, forming spacers at sidewalls of the photoresist pattern by performing a primary etching process using the photoresist pattern as a mask, and forming an etch layer pattern and an insulating layer pattern by performing a secondary etching process using the photoresist pattern and the spacers as a mask.04-29-2010
20100041233FABRICATION METHODS FOR INTEGRATION CMOS AND BJT DEVICES - Fabrication methods for integrating CMOS and BJT devices are presented. A semiconductor substrate having a first region and a second region are provided, wherein the first region includes a CMOS device, and the second region includes a BJT device. A dielectric layer is conformably deposited on the semiconductor substrate. Part of the dielectric layer is removed, thereby forming sidewall spacers on a gate structure of the CMOS device and remaining a thin dielectric layer on the BJT device. The remaining thin dielectric layer is completely removed, completing integration of the CMOS device and the BJT device.02-18-2010
20090130850Semiconductor Devices and Method of Fabricating the Same - A method of fabricating a semiconductor device is provided. A contact hole with a finer width can be formed by solving an exposure limit of KrF exposure apparatuses. The fabrication method includes forming a first insulation layer on a substrate; forming a photoresist pattern on the first insulation layer; forming a second insulation layer covering the photoresist pattern; forming a second insulation layer spacer in a sidewall of the photoresist pattern by etching the second insulation layer; forming a contact hole by etching the first insulation layer using the photoresist pattern and the second insulation layer spacer as a mask; removing the photoresist pattern; and removing the second insulation layer spacer. A contact hole with a finer width can be formed using a KrF exposure apparatus, and furthermore, contact resistance can be lowered and device characteristics can be improved05-21-2009
20130029490HIGH LATERAL TO VERTICAL RATIO ETCH PROCESS FOR DEVICE MANUFACTURING - A layer stack over a substrate is etched using a photoresist pattern deposited on the layer stack as a first mask. The photoresist pattern is in-situ cured using plasma. At least a portion of the photoresist pattern can be modified by curing. In one embodiment, silicon by-products are formed on the photoresist pattern from the plasma. In another embodiment, a carbon from the plasma is embedded into the photoresist pattern. In yet another embodiment, the plasma produces an ultraviolet light to cure the photoresist pattern. The cured photoresist pattern is slimmed. The layer stack is etched using the slimmed photoresist pattern as a second mask.01-31-2013
20100093176METHOD OF FORMING A SACRIFICIAL LAYER - The present disclosure provides a method for making a semiconductor device. The method includes forming a material layer on a substrate; forming a sacrificial layer on the material layer, where the material layer and sacrificial layer each as a thickness less than 100 angstrom; forming a patterned photoresist layer on the sacrificial layer; applying a first wet etching process to etch the sacrificial layer to form a patterned sacrificial layer using the patterned photoresist layer as a mask; applying a second wet etching process to etch the first material layer; and applying a third wet etching process to remove the patterned sacrificial layer.04-15-2010
20120164834Variable-Density Plasma Processing of Semiconductor Substrates - Methods and hardware for generating variable-density plasmas are described. For example, in one embodiment, a process station comprises a showerhead including a showerhead electrode and a substrate holder including a mesa configured to support a substrate, wherein the substrate holder is disposed beneath the showerhead. The substrate holder includes an inner electrode disposed in an inner region of the substrate holder and an outer electrode being disposed in an outer region of the substrate holder. The process station further comprises a plasma generator configured to generate a plasma in a plasma region disposed between the showerhead and the substrate holder, and a controller configured to control the plasma generator, the inner electrode, the outer electrode, and the showerhead electrode to effect a greater plasma density in an outer portion of the plasma region than in an inner portion of the plasma region.06-28-2012
20090124083Film formation apparatus and method for using same - A method for using a film formation apparatus for a semiconductor process to form a thin film on a target substrate while supplying a film formation reactive gas from a first nozzle inside a reaction chamber includes performing a cleaning process to remove a by-product film deposited inside the reaction chamber and the first nozzle, in a state where the reaction chamber does not accommodate the target substrate. The cleaning process includes, in order, an etching step of supplying a cleaning reactive gas for etching the by-product film into the reaction chamber, and activating the cleaning reactive gas, thereby etching the by-product film, and an exhaust step of stopping supply of the cleaning reactive gas and exhausting gas from inside the reaction chamber. The etching step is arranged to use conditions that cause the cleaning reactive gas supplied in the reaction chamber to flow into the first nozzle.05-14-2009
20130045601COMPOSITION FOR FORMING A SILICON-CONTAINING RESIST UNDERLAYER FILM AND PATTERNING PROCESS USING THE SAME - A composition for forming a silicon-containing resist underlayer film that contains: a component (A) including at least one or more compounds selected from the group consisting of a polymer having repeating units shown by the following general formulae (1-1a) and (1-1b) and being capable of generating a phenolic hydroxyl group, a hydrolysate of the polymer, and a hydrolysis-condensate of the polymer, and a component (B) which is a silicon-containing compound obtained by hydrolysis-condensation of a mixture containing, at least, one or more hydrolysable silicon compounds represented by the following general formula (2) and one or more hydrolysable silicon compounds represented by the following general formula (3).02-21-2013
20130045600METHOD FOR FORMING FIN-SHAPED SEMICONDUCTOR STRUCTURE - A method for fabricating a fin-shaped semiconductor structure is provided, including: providing a semiconductor substrate with a semiconductor island and a dielectric layer formed thereover; forming a mask layer over the semiconductor island and the dielectric layer; forming an opening in the mask layer, exposing a top surface of the semiconductor island and portions of the dielectric layer adjacent to the semiconductor island; performing an etching process, simultaneously etching portions of the mask layer, and portions of the semiconductor island and the dielectric layer exposed by the opening; and removing the mask layer and the dielectric layer, leaving an etched semiconductor island with curved top surfaces and various thicknesses over the semiconductor substrate.02-21-2013
20130052828SUBSTRATE PROCESSING METHOD AND SUBSTRATE PROCESSING APPARATUS - In a substrate processing apparatus (02-28-2013
20130052827SELECTIVE SUPPRESSION OF DRY-ETCH RATE OF MATERIALS CONTAINING BOTH SILICON AND OXYGEN - A method of suppressing the etch rate for exposed silicon-and-oxygen-containing material on patterned heterogeneous structures is described and includes a two stage remote plasma etch. Examples of materials whose selectivity is increased using this technique include silicon nitride and silicon. The first stage of the remote plasma etch reacts plasma effluents with the patterned heterogeneous structures to form protective solid by-product on the silicon-and-oxygen-containing material. The plasma effluents of the first stage are formed from a remote plasma of a combination of precursors, including a nitrogen-containing precursor and a hydrogen-containing precursor. The second stage of the remote plasma etch also reacts plasma effluents with the patterned heterogeneous structures to selectively remove material which lacks the protective solid by-product. The plasma effluents of the second stage are formed from a remote plasma of a fluorine-containing precursor.02-28-2013
20130052826High Aspect Ratio Grid for Phase Contrast X-ray Imaging and Method of Making the Same - Semiconductor substrates with high aspect ratio recesses formed therein are described. The high aspect ratio recesses have bottom surface profile characteristics that promote formation of initial growth sites of plated metal as compared to the side surfaces of the recesses. Processes for making and plating the recesses are also disclosed. The metal-plated high aspect ratio recesses can be used as X-ray gratings in Phase Contrast X-ray imaging apparatuses.02-28-2013
20090042394MANUFACTURING METHOD FOR WIRING - In the case in which a film for a resist is formed by spin coating, there is a resist material to be wasted, and the process of edge cleaning is added as required. Further, when a thin film is formed on a substrate using a vacuum apparatus, a special apparatus or equipment to evacuate the inside of a chamber vacuum is necessary, which increases manufacturing cost. The invention is characterized by including: a step of forming conductive layers on a substrate having a dielectric surface in a selective manner with a CVD method, an evaporation method, or a sputtering method; a step of discharging a compound to form resist masks so as to come into contact with the conductive layer; a step of etching the conductive layers with plasma generating means using the resist masks under the atmospheric pressure or a pressure close to the atmospheric pressure; and a step of ashing the resist masks with the plasma generating means under the atmospheric pressure or a pressure close to the atmospheric pressure. With the above-mentioned characteristics, efficiency in use of a material is improved, and a reduction in manufacturing cost is realized.02-12-2009
20090305505METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes forming a plurality bar patterns over an underlying layer. A spacer is formed at both sides of the bar patterns and the bar patterns are removed. The spacers are isolated by an exposing process to form a vernier pattern. The underlying layer is etched using the vernier pattern as an etching mask.12-10-2009
20130164939METHOD, APPARATUS FOR HOLDING AND TREATMENT OF A SUBSTRATE - Some embodiments discussed relates to an apparatus for holding a substrate, comprising a body with a surface for a semiconductor wafer to rest on, with the surface having a first surface area on which a first area of the semiconductor wafer can rest, and a second surface area on which a second area of the semiconductor wafer can rest, wherein the second surface area protrudes with respect to the first surface area.06-27-2013
20130183827Methods Of Patterning Substrates - A method of patterning a substrate includes forming spaced first features over a substrate. Individual of the spaced first features include sidewall portions of different composition than material that is laterally between the sidewall portions. A mixture of immiscible materials is provided between the spaced first features. At least two of the immiscible materials are laterally separated along at least one elevation between adjacent spaced first features. The laterally separating forms a laterally intermediate region including one of the immiscible materials between two laterally outer regions including another of the immiscible materials along the one elevation. The laterally outer regions are removed and material of the spaced first features is removed between the sidewall portions to form spaced second features over the substrate. Other embodiments are disclosed.07-18-2013
20130059441METHOD FOR FABRICATING A SEMICONDUCTOR STRUCTURE - A method for fabricating a semiconductor structure is disclosed. The method includes the steps of: providing a substrate; depositing a material layer on the substrate; forming at least one dielectric layer on the material layer; forming a patterned resist on the dielectric layer; performing a first trimming process on at least the patterned resist; and performing a second trimming process on at least the dielectric layer, wherein the second trimming process comprises trimming greater than 70% of a total trimming value.03-07-2013
20130059440SELECTIVE SUPPRESSION OF DRY-ETCH RATE OF MATERIALS CONTAINING BOTH SILICON AND NITROGEN - A method of suppressing the etch rate for exposed silicon-and-nitrogen-containing material on patterned heterogeneous structures is described and includes a two stage remote plasma etch. The etch selectivity of silicon relative to silicon nitride and other silicon-and-nitrogen-containing material is increased using the method. The first stage of the remote plasma etch reacts plasma effluents with the patterned heterogeneous structures to form protective solid by-product on the silicon-and-nitrogen-containing material. The plasma effluents of the first stage are formed from a remote plasma of a combination of precursors, including nitrogen trifluoride and hydrogen (H03-07-2013
20090269929NON-PLASMA CAPPING LAYER FOR INTERCONNECT APPLICATIONS - The present invention provides an interconnect structure which has a high leakage resistance and substantially no metallic residues and no physical damage present at an interface between the interconnect dielectric and an overlying dielectric capping layer. The interconnect structure of the invention also has an interface between each conductive feature and the overlying dielectric capping layer that is substantially defect-free. The interconnect structure of the invention includes a non-plasma deposited dielectric capping layer which is formed utilizing a process including a thermal and chemical-only pretreatment step that removes surface oxide from atop each of the conductive features as well as metallic residues from atop the interconnect dielectric material. Following this pretreatment step, the dielectric capping layer is deposited.10-29-2009
20090087991Manufacturing method, manufacturing apparatus, control program and program recording medium of semicontructor device - A manufacturing method of a semiconductor device, which etches a layer to be etched on a substrate into a predetermined pattern based on a first pattern of photoresist produced by exposing and developing a photoresist film, the manufacturing method includes the steps of, patterning an organic membrane based on a first pattern of the photoresist, forming an SiO04-02-2009
20130065396APPARATUS INCLUDING GAS DISTRIBUTION MEMBER SUPPLYING PROCESS GAS AND RADIO FREQUENCY (RF) POWER FOR PLASMA PROCESSING - A plasma processing apparatus includes a gas distribution member which supplies a process gas and radio frequency (RF) power to a showerhead electrode. The gas distribution member can include multiple gas passages which supply the same process gas or different process gases at the same or different flow rates to one or more plenums at the backside of the showerhead electrode. The gas distribution member provides a desired process gas distribution to be achieved across a semiconductor substrate processed in a gap between the showerhead electrode and a bottom electrode on which the substrate is supported.03-14-2013
20090233446Plasma etching method - The present invention is a plasma etching method for etching a surface of a substrate in which a metal nitride film and a silicon film have been respectively formed on a first base film and a second base film that had been side-by-side arranged, with surfaces of the metal nitride film and the silicon film being exposed. At least a surface area of the silicon film is nitrided. A first etching plasma is supplied onto the surface of the substrate so as to etch the metal nitride film and to expose the first base film. A second etching plasma is supplied onto the surface of the substrate so as to etch the silicon film and to expose the second base film.09-17-2009
20090233445METHOD OF MAKING DIAMOND NANOPILLARS - A method for fabricating diamond nanopillars includes forming a diamond film on a substrate, depositing a metal mask layer on the diamond film, and etching the diamond film coated with the metal mask layer to form diamond nanopillars below the mask layer. The method may also comprise forming diamond nuclei on the substrate prior to forming the diamond film. Typically, a semiconductor substrate, an insulating substrate, a metal substrate, or an alloy substrate is used.09-17-2009
20090047789METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes forming an amorphous carbon layer over a substrate, forming a hard mask pattern over the amorphous carbon layer, and etching the amorphous carbon layer with an etching gas including sulfur (S) using the hard mask pattern as an etch barrier. Deformation of the amorphous carbon patterns is prevented by hardening the sidewalls of the amorphous carbon layer exposed during etching of the amorphous carbon layer. Therefore, when the etch target layer is etched with the amorphous carbon patterns having a vertical shape, pattern uniformity of the etch target pattern can be improved.02-19-2009
20090047788METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes forming a plurality of first hard mask patterns at certain intervals over a substrate where an etch target layer is formed, forming a sacrificial layer along a step of the substrate where the first hard mask patterns are formed, forming a second hard mask layer over the sacrificial layer, etching a portion of the second hard mask layer to expose the sacrificial layer and form second hard mask patterns remaining between the first hard mask patterns, removing the sacrificial layer between the first hard mask patterns and the second hard mask patterns, and etching the etch target layer using the first hard mask patterns and the second hard mask patterns as an etch mask.02-19-2009
20120115331METHODS OF FORMING FINE PATTERNS AND METHODS OF FABRICATING SEMICONDUCTOR DEVICES - Method of forming fine patterns and methods of fabricating semiconductor devices by which a photoresist (PR) pattern may be transferred to a medium material layer with a small thickness and a high etch selectivity with respect to a hard mask to form a medium pattern and the hard mask may be formed using the medium pattern. According to the methods, the PR pattern may have a low aspect ratio so that a pattern can be transferred using a PR layer with a small thickness without collapsing the PR pattern.05-10-2012
20090011602Film Forming Method of Amorphous Carbon Film and Manufacturing Method of Semiconductor Device Using the Same - Disclosed is a film forming method of an amorphous carbon film, including: disposing a substrate in a processing chamber; supplying a processing gas containing carbon, hydrogen and oxygen into the processing chamber; and decomposing the processing gas by heating the substrate in the processing chamber and depositing the amorphous carbon film on the substrate.01-08-2009
20090011601Over-coating agent for forming fine patterns and a method of forming fine patterns using such agent - It is disclosed an over-coating agent for forming fine-line patterns which is applied to cover a substrate having thereon photoresist patterns and allowed to shrink under heat so that the spacing between adjacent photoresist patterns is lessened, with the applied film of the over-coating agent being removed substantially completely to form or define fine trace patterns, further characterized by containing a copolymer or a mixture of polyvinyl alcohol with a water-soluble polymer other than polyvinyl alcohol. Also disclosed is a method of forming fine-line patterns using the over-coating agent. According to the invention, one can effectively increase the shrinkage amount (the amount of heat shrinking) of the agent, thereby achieving a remarkably improved effect of forming or defining fine-line patterns and which also present satisfactory profiles and meet the characteristics required of today's semiconductor devices.01-08-2009
20090011600METHOD AND APPARATUS FOR MANUFACTURING SEMICONDUCTOR DEVICE - The present invention is directed to a method and an apparatus for manufacturing a semiconductor device including step S01-08-2009
20120238097METHOD FOR FABRICATING FINE LINE - Disclosed herein is a method for fabricating a fine line, which belongs to a field of ultra-large-scale integrated circuit manufacturing technology. In the invention, three trimming mask processes are performed to effectively improve a profile of the line and greatly reduce the LER (line edge roughness) of the line. At the same time, the invention is combined with a sidewall process, so that a nano-scaled fine line can be successfully fabricated and precisely controlled to 20 nm. Thus, a nano-scaled line with an optimized LER can be fabricated over the substrate.09-20-2012
20120238096METHOD AND APPARATUS FOR INSPECTING A REFLECTIVE LITHOGRAPHIC MASK BLANK AND IMPROVING MASK QUALITY - An EUV integrated circuit fabrication method and system EUV that includes blank inspection, defect characterization, simulation, pattern compensation, modification of the mask writer database, inspection and simulation of patterned masks, and patterned mask repair. The system performs blank inspection to identify defects at multiple focal planes within the blank. The mask can be relocated on the blank and alterations to the pattern can be developed to compensate for the defects prior to prior to patterning the mask. Once the mask has been patterned, the reticle is inspected to identify any additional or remaining defects that were not picked up during blank inspection or fully mitigated through pattern compensation. The patterned reticle can then be repaired prior to integrated circuit fabrication.09-20-2012
20120238095PATTERNING PROCESS AND COMPOSITION FOR FORMING SILICON-CONTAINING FILM USABLE THEREFOR - The invention provides a patterning process for forming a negative pattern by lithography, comprising at least the steps of: using a composition for forming silicon-containing film, containing specific silicon-containing compound (A) and an organic solvent (B), to form a silicon-containing film; using a silicon-free resist composition to form a photoresist film on the silicon-containing film; heat-treating the photoresist film, and subsequently exposing the photoresist film to a high energy beam; and using a developer comprising an organic solvent to dissolve an unexposed area of the photoresist film, thereby obtaining a negative pattern. There can be a patterning process, which is optimum as a patterning process of a negative resist to be formed by adopting organic solvent-based development, and a composition for forming silicon-containing film to be used in the process.09-20-2012
20130164938Selective Bias Compensation for Patterning Steps in CMOS Processes - A method includes forming a photo resist pattern, and performing a light-exposure on a first portion of the photo resist pattern, wherein a second portion of the photo resist pattern is not exposed to light. A photo-acid reactive material is coated on the first portion and the second portion of the photo resist pattern. The photo-acid reactive material reacts with the photo resist pattern to form a film. Portions of the photo-acid reactive material that do not react with the photo resist pattern are then removed, and the film is left on the photo resist pattern.06-27-2013
20100144152Method of manufacturing semiconductor package - The present invention relates to a method of manufacturing a semiconductor package capable of simplifying a process and remarkably reducing a production cost by including the steps of: preparing a different bonded panel including at least one metal layer; forming a pad unit electrically connected to the metal layer; mounting a semiconductor chip over the different bonded panel to be electrically connected to the pad unit; sealing the semiconductor chip; forming a rearrangement wiring layer by etching the metal layer; and forming an external connection unit electrically connected to the rearrangement wiring layer.06-10-2010
20120100719METHOD FOR MAKING A PLANAR MEMBRANE - A method for determining a minimum tension compensation stress which will have a membrane of a thickness of less than or equal to one micrometer, secured to a frame, having, in the absence of any external stress, a desired deflection. The membrane can be made as planar as possible in absence of any external stress, and its thickness can be less than or equal to one micrometer.04-26-2012
20090130852PROCESS FOR IMPROVING CRITICAL DIMENSION UNIFORMITY OF INTEGRATED CIRCUIT ARRAYS - Methods for patterning integrated circuit (IC) device arrays employing an additional mask process for improving center-to-edge CD uniformity are disclosed. In one embodiment, a repeating pattern of features is formed in a masking layer over a first region of a substrate. Then, a blocking mask is applied over the features in the masking layer. The blocking mask is configured to differentiate array regions of the first region from peripheral regions of the first region. Subsequently, the pattern of features in the array regions is transferred into the substrate. In the embodiment, an etchant can be uniformly introduced to the masking layer because there is no distinction of center/edge in the masking layer. Thus, CD uniformity can be achieved in arrays which are later defined.05-21-2009
20110281433ETCHING METHOD USING AN AT LEAST SEMI-SOLID MEDIA - An etching method that uses an etch reactant retained within at least a semi-solid media (11-17-2011
20100173495SUBSTRATE PROCESSING APPARATUS USING A BATCH PROCESSING CHAMBER - Aspects of the invention include a method and apparatus for processing a substrate using a multi-chamber processing system (e.g., a cluster tool) adapted to process substrates in one or more batch and/or single substrate processing chambers to increase the system throughput. In one embodiment, a system is configured to perform a substrate processing sequence that contains batch processing chambers only, or batch and single substrate processing chambers, to optimize throughput and minimize processing defects due to exposure to a contaminating environment. In one embodiment, a batch processing chamber is used to increase the system throughput by performing a process recipe step that is disproportionately long compared to other process recipe steps in the substrate processing sequence that are performed on the cluster tool. In another embodiment, two or more batch chambers are used to process multiple substrates using one or more of the disproportionately long processing steps in a processing sequence. Aspects of the invention also include an apparatus and method for delivering a precursor to a processing chamber so that a repeatable ALD or CVD deposition process can be performed.07-08-2010
20110143541APPARATUS AND METHOD OF TREATING SURFACE OF SEMICONDUCTOR SUBSTRATE - In one embodiment, an apparatus of treating a surface of a semiconductor substrate comprises a substrate holding and rotating unit, first to fourth supplying units, and a removing unit. A substrate holding and rotating unit holds a semiconductor substrate, having a convex pattern formed on its surface, and rotates the semiconductor substrate. A first supplying unit supplies a chemical onto the surface of the semiconductor substrate in order to clean the semiconductor substrate. A second supplying unit supplies pure water to the surface of the semiconductor substrate in order to rinse the semiconductor substrate. A third supplying unit supplies a water repellent agent to the surface of the semiconductor substrate in order to form a water repellent protective film onto the surface of the convex pattern. A fourth supplying unit supplies alcohol, which is diluted with pure water, or acid water to the surface of the semiconductor substrate in order to rinse the semiconductor substrate. A removing unit removes the water repellent protective film with the convex pattern being left.06-16-2011
20120108067Edge Bead Remover For Coatings - The invention relates to an edge bead remover composition for an organic film disposed on a substrate surface, comprising an organic solvent and at least one polymer having a contact angle with water greater than 70°. The invention also relates to a process for using the composition as an edge bead remover for an organic film.05-03-2012
20080206997Method for Manufacturing Insulating Film and Method for Manufacturing Semiconductor Device - A method for manufacturing an insulating film, by which the insulating film can be formed of a non-photosensitive siloxane resin and formed into a desired shape by wet etching. A thin film is formed with a suspension in which a siloxane resin or a siloxane-based material is included in an organic solvent; a first heat treatment is performed on the thin film; a mask is formed over the thin film after the first heat treatment; wet etching with an organic solvent is performed to process the shape of the thin film after the first heat treatment; and a second heat treatment is performed on the processed thin film.08-28-2008
20110294295METHOD FOR MAKING THREE-DIMENSIONAL NANO-STRUCTURE ARRAY - A method for making a three-dimensional nano-structure array includes following steps. First, a substrate is provided. Next, a mask is formed on the substrate. The mask is a monolayer nanosphere array or a film defining a number of holes arranged in an array. The mask is then tailored and simultaneously the substrate is etched by the mask. Lastly, the mask is removed.12-01-2011
20090170328Method for manufacturing semiconductor device and substrate processing method - The method according to the invention includes the steps of: purging an inside of the processing chamber with gas while applying a thermal impact onto the thin film deposited on the inside of the processing chamber by decreasing the temperature in the processing chamber, so as to forcibly generate a crack in the thin film and forcibly peel the adhered material with a weak adhesive force, in a state where the substrate is not present in the processing chamber; removing the thin film deposited on the inside of the processing chamber by supplying a fluorine-based gas to the inside of the processing chamber heated to a first temperature, in the state where the substrate is not present in the processing chamber; and removing an adhered material remaining on the inside of the processing chamber after removing the thin film by supplying a fluorine-based gas to the inside of the processing chamber heated to a second temperature, in the state where the substrate is not present in the processing chamber.07-02-2009
20090170329PHOTO MASK - A photo mask comprises a H-type light-shield pattern. In an exposure process, a photo mask is used to form a STAR (Step Asymmetry Recess) gate region, thereby stably securing a storage node contact region and improving a refresh characteristic of a semiconductor device.07-02-2009
20120190202METHOD FOR FABRICATING SEMICONDUCTOR NANO CIRCULAR RING - The present invention discloses a method for fabricating a semiconductor nano circular ring. In the method, firstly, a positive photoresist is coated on a semiconductor substrate, then the photoresist is exposed by using a circular mask with a micrometer-sized diameter to obtain the circular ring-shaped photoresist, based on the poisson diffraction principle. Then, a plasma etching is performed on the substrate under a protection of the circular ring-shaped photoresist to form a circular ring-shaped structure with a nano-sized wall thickness on a surface of the substrate. The embodiment of present invention fabricates a nano-sized circular ring-shaped structure by using a micrometer-sized lithography equipment and a micrometer-sized circular mask, and overcomes the dependence on advanced technologies, so as to effectively reduce the fabrication cost of the circular ring-shaped nano structure.07-26-2012
20090280650FLOWABLE DIELECTRIC EQUIPMENT AND PROCESSES - Methods of depositing and curing a dielectric material on a substrate are described. The methods may include the steps of providing a processing chamber partitioned into a first plasma region and a second plasma region, and delivering the substrate to the processing chamber, where the substrate occupies a portion of the second plasma region. The methods may further include forming a first plasma in the first plasma region, where the first plasma does not directly contact with the substrate, and depositing the dielectric material on the substrate to form a dielectric layer. One or more reactants excited by the first plasma are used in the deposition of the dielectric material. The methods may additional include curing the dielectric layer by forming a second plasma in the second plasma region, where one or more carbon-containing species is removed from the dielectric layer.11-12-2009
20090239381POROUS FILM - A porous film which is formed using a block copolymer composed of a water-soluble polymer and a water-insoluble polymer, has nanometer-size pores, and in which a desired functional polymer is present on the pore inner walls is provided. The porous film includes a microphase-separated morphology including a continuous phase which is composed primarily of a water-insoluble polymer A, and a plurality of cylindrical microdomains which are composed primarily of a water-soluble polymer B incompatible with the water-insoluble polymer A, distributed within the continuous phase and oriented perpendicular to a surface of the film. The cylindrical microdomains contain therein pores having a cylindrical shape and an average diameter of between 1 and 200 nm.09-24-2009
20100112817METHOD FOR FORMlNG PATTERN OF SEMICONDUCTOR DEVICE - A method for forming a pattern of a semiconductor device using a spacer patterning process comprises coating a developable antireflection film over a substrate including a spacer pattern, coating a photoresist film over the antireflection film, and patterning the antireflection film and the photoresist film by an exposing and developing process to form an etching mask pattern. The etching mask pattern has an excellent profile. When a lower underlying layer is etched using the etching mask pattern, a sufficient etching margin can be secured, thereby obtaining a reliable semiconductor device.05-06-2010
20120083124Method of Patterning NAND Strings Using Perpendicular SRAF - A lithography mask includes a plurality of patterning features formed on a mask substrate and a first plurality of sub-resolution assist features (SRAFs) formed substantially perpendicular to the patterning features on the mask substrate.04-05-2012
20080268645METHOD FOR FRONT END OF LINE FABRICATION - In one embodiment, a method for removing native oxides from a substrate surface is provided which includes supporting a substrate containing silicon oxide within a processing chamber, generating a plasma of reactive species from a gas mixture within the processing chamber, cooling the substrate to a first temperature of less than about 65° C. within the processing chamber, and directing the reactive species to the cooled substrate to react with the silicon oxide thereon while forming a film on the substrate. The film usually contains ammonium hexafluorosilicate. The method further provides positioning the substrate in close proximity to a gas distribution plate, and heating the substrate to a second temperature of about 100° C. or greater within the processing chamber to sublimate or remove the film. The gas mixture may contain ammonia, nitrogen trifluoride, and a carrier gas.10-30-2008
20080268644MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SUBSTRATE PROCESSING APPARATUS - There are provided the steps of loading a substrate into a reaction vessel; forming a film on the substrate while supplying a film forming gas into the reaction vessel; unloading the substrate after film formation from the reaction vessel; supplying a cleaning gas into the reaction vessel while lowering a temperature in the reaction vessel and removing a deposit deposited on at least an inner wall of the reaction vessel in the film forming step.10-30-2008
20080206998SEMICONDUCTOR FABRICATION APPARATUSES TO PERFORM SEMICONDUCTOR ETCHING AND DEPOSITION PROCESSES AND METHODS OF FORMING SEMICONDUCTOR DEVICE USING THE SAME - A semiconductor fabrication apparatus and a method of fabricating a semiconductor device using the same performs semiconductor etching and deposition processes at an edge of a semiconductor substrate after disposing the semiconductor substrate at a predetermined place in the semiconductor fabrication apparatus. The semiconductor fabrication apparatus has lower, middle and upper electrodes sequentially stacked. The semiconductor substrate is disposed on the middle electrode. Semiconductor etching and deposition processes are performed on the semiconductor substrate in the semiconductor fabrication apparatus. The semiconductor fabrication apparatus forms electrical fields along an edge of the middle electrode during performance of the semiconductor etching and deposition processes.08-28-2008
20120034782Method of Forming Fine Patterns - A method of forming fine patterns according to an aspect of the present disclosure comprises stacking a hard mask layer and a first auxiliary layer over an underlying layer, removing regions of the first auxiliary layer, thereby forming first auxiliary patterns to expose regions of the hard mask layer, filling between the first auxiliary patterns with a second auxiliary layer, wherein a material of the second auxiliary layer is different from that of the first auxiliary layer, lowering a height of the second auxiliary layer by removing the second auxiliary layer to expose sidewalls of the first auxiliary patterns, forming spacers on the exposed sidewalls of the first auxiliary patterns to expose regions of the second auxiliary layer, wherein a material of the spacers is different from that of the second auxiliary layer, removing the exposed regions of the second auxiliary layer, removing the spacers and the first auxiliary patterns to expose regions of the hard mask layer and removing the exposed regions of the hard mask layer, thereby forming hard mask patterns.02-09-2012
20100120251Large Area Patterning of Nano-Sized Shapes - Methods for creating nano-shaped patterns are described. This approach may be used to directly pattern substrates and/or create imprint lithography molds that may be subsequently used to directly replicate nano-shaped patterns into other substrates in a high throughput process.05-13-2010
20090275200TECHNIQUE FOR REDUCING TOPOGRAPHY-RELATED IRREGULARITIES DURING THE PATTERNING OF A DIELECTRIC MATERIAL IN A CONTACT LEVEL OF CLOSELY SPACED TRANSISTORS - In a dual stress liner approach, the surface conditions after the patterning of a first stress-inducing layer may be enhanced by appropriately designing an etch sequence for substantially completely removing an etch stop material, which may be used for the patterning of the second stress-inducing dielectric material, while, in other cases, the etch stop material may be selectively formed after the patterning of the first stress-inducing dielectric material. Hence, the dual stress liner approach may be efficiently applied to semiconductor devices of the 45 nm technology and beyond.11-05-2009
20110230051METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A post-CMP cleaning process of a copper layer is to be performed as follows. An alkaline aqueous solution, a polycarboxylic acid, BTA, and an alkaline aqueous solution are sequentially brought into contact with a primary surface of a silicon substrate over which the copper layer is provided.09-22-2011
20090263971METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SUBSTRATE PROCESSING APPARATUS - A method of manufacturing a semiconductor device comprises: (a) loading a substrate into a process chamber, wherein the substrate has at least a silicon exposure surface and an exposure surface of silicon oxide film or silicon nitride film on a substrate surface; (b) simultaneously supplying at least a first process gas containing silicon and a second process gas for etching into the process chamber under conditions that the substrate inside the process chamber is heated to a predetermined temperature; and (c) supplying a third process gas having a stronger etchability than the second process gas into the process chamber, wherein the operation (b) and the operation (c) are performed at least one or more times so that an epitaxial film is selectively grown on the silicon exposure surface of the substrate surface10-22-2009
20110201201METHODS OF FABRICATING LARGE-AREA, SEMICONDUCTING NANOPERFORATED GRAPHENE MATERIALS - Methods for forming a nanoperforated graphene material are provided. The methods comprise forming an etch mask defining a periodic array of holes over a graphene material and patterning the periodic array of holes into the graphene material. The etch mask comprises a pattern-defining block copolymer layer, and can optionally also comprise a wetting layer and a neutral layer. The nanoperforated graphene material can consist of a single sheet of graphene or a plurality of graphene sheets.08-18-2011
20090258498Method for Manufacturing a Semiconductor Device - A method for manufacturing a semiconductor device using a photoresist polymer comprising a fluorine component, a photoresist composition containing the photoresist polymer and an organic solvent to reduce surface tension, by forming a photoresist film uniformly on the whole surface of an underlying layer pattern to allow a subsequent ion-implanting process to be stably performed.10-15-2009
20090286401METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device according to one embodiment includes: forming a core material on a workpiece; forming a coating film comprising an amorphous material so as to cover an upper surface and side faces of the core material; crystallizing the coating film by applying heat treatment; forming a sidewall mask by removing the crystallized coating film while leaving a portion thereof located on the side faces of the core material; removing the core material after forming the sidewall mask; and etching the workpiece using the sidewall mask as a mask after removing the core material.11-19-2009
20090286399Substrate Processing Method and Storage Medium - A substrate processing method includes performing an etching process on a low dielectric constant film disposed on a substrate, thereby forming a predetermined pattern thereon; denaturing a remaining substance to be soluble in a predetermined liquid after the etching process; dissolving and removing the substance thus denatured, by supplying the predetermined liquid thereon; then, performing a silylation process on a surface of the low dielectric constant film, by supplying a silylation agent thereon, after said dissolving and removing the substance denatured; and baking the substrate after the silylation process.11-19-2009
20080286969Patterning methods - The invention includes a template comprising one or both of Cbs and CdSe adhered to a base in a desired pattern. The base can be any transparent or translucent material, and the desired pattern can include two or more separated segments. The template can be utilized for patterning a plurality of substrates. For instance, the substrates can be provided to have masking layers thereover, and the CdS and/or CdSe can be utilized as catalytic material to sequentially impart patterns in the masking layers. The imparting of the patterns can modify some regions of the masking layers relative to others, and either the modified or unmodified regions can be selectively removed to form patterned masks from the masking layers. Patterns from the patterned masks can then be transferred into the substrates.11-20-2008
20110269313SEMICONDUCTOR SUBSTRATE SURFACE TREATMENT METHOD - In one embodiment, a method for treating a surface of a semiconductor substrate is disclosed. The semiconductor substrate has a first pattern covered by a resist and a second pattern not covered by the resist. The method includes supplying a resist-insoluble first chemical solution onto a semiconductor substrate to subject the second pattern to a chemical solution process. The method includes supplying a mixed liquid of a water repellency agent and a resist-soluble second chemical solution onto the semiconductor substrate after the supply of the first chemical solution, to form a water-repellent protective film on a surface of at least the second pattern and to release the resist. In addition, the method can rinse the semiconductor substrate using water after the formation of the water-repellent protective film, and dry the rinsed semiconductor substrate.11-03-2011
20120270402METHOD OF MAKING AN ARRAY COLUMNAR HOLLOW SEMICONDUCTOR STRUCTURE - A method of making an array columnar hollow semiconductor structure includes: providing an oxide layer; placing a chromeless mask on the oxide layer, wherein the chromeless mask is a bank-shaped frame; forming a silicone nitride layer to cover the first partial top surface of the oxide layer and the whole outer surface of the bank-shaped frame; removing one part of the silicone nitride layer to expose a second partial top surface of the oxide layer and a top surface of the bank-shaped frame; removing the bank-shaped frame to expose a third partial top surface of the oxide layer; removing a first part of the oxide layer under the second partial top surface and a second portion of the oxide layer under the third partial top surface to form a plurality of columnar hollow bodies; and removing the other silicone nitride layer to completely expose the columnar hollow bodies.10-25-2012
20090170326METHOD OF FORMING MICRO PATTERN OF SEMICONDUCTOR DEVICE - The present invention relates to a method of forming micro patterns of a semiconductor device. In the method according to an aspect of the present invention, first etch mask patterns having a second pitch, which is twice larger than a first pitch of target patterns, are formed in a column direction over a semiconductor substrate. An auxiliary film is formed over the semiconductor substrate including a surface of the first etch mask patterns. An etch mask film is formed over the semiconductor substrate including the auxiliary film. An etch process is performed in order to form second etch mask patterns having the second pitch in such a manner that the etch mask film, the auxiliary film, and the first etch mask patterns are isolated from one another in a row direction and the etch mask film remains between the first etch mask patterns. The auxiliary film between the first and second etch mask patterns is removed.07-02-2009
20090170327Method of manufacturing a semiconductor device - In this method of manufacturing a semiconductor device, the remaining layer of an etching mask layer remains in a predetermined thickness when the stamping face of a nano-stamper is pressed on the surface of the etching mask layer. Therefore, the remaining layer of the etching mask layer functions as a cushion so that the stress added to the nano-stamper and the semiconductor substrate is reduced. Accordingly, the crystal defect that might otherwise be introduced in the semiconductor substrate in pressing the nano-stamper on the semiconductor substrate can be restrained, resulting in suppression of the degradation of optical characteristics of the semiconductor device. Also, since the nano-stamper can be prevented from being damaged, extra steps such as the replacement of the nano-stamper can be avoided.07-02-2009
20090170325METHOD OF FORMING A SEMICONDUCTOR DEVICE PATTERN - In a method of forming patterns of a semiconductor device, first etch mask patterns are formed over a semiconductor substrate. An auxiliary film is formed over the first etch mask patterns to a thickness in which a step corresponding to the first etch mask patterns can be maintained. Second etch mask patterns are formed in spaces defined by the auxiliary film between adjacent first etch mask patterns. First auxiliary film patterns are formed by removing the auxiliary film formed on the first etch mask patterns. Each first auxiliary film pattern has opposite ends projecting upwardly. The first etch mask patterns and the second etch mask patterns are removed. Second auxiliary film patterns are formed by etching between the ends of the first auxiliary film patterns such that the opposite ends of the first auxiliary film patterns are isolated from each other.07-02-2009
20080274621III-Nitride semiconductor device with trench structure - A III-nitride trench device has a vertical conduction region with an interrupted conduction channel when the device is not on, providing an enhancement mode device. The trench structure may be used in a vertical conduction or horizontal conduction device. A gate dielectric provides improved performance for the device by being capable of withstanding higher electric field or manipulating the charge in the conduction channel. A passivation of the III-nitride material decouples the dielectric from the device to permit lower dielectric constant materials to be used in high power applications.11-06-2008
20090298291METHOD FOR FORMING A PATTERN OF A SEMICONDUCTOR DEVICE - In a method for forming a pattern of a semiconductor device, an ultra fine pattern is formed using a spacer patterning technology to overcome resolution limits of an exposer. A silicon-containing resist enhancement lithography assisted by a chemical shrink (RELACS) layer is formed with a spin-con-coating method in a track apparatus over a photoresist pattern. As a result, a cross-linking reaction is generated between the RELACS layer and the photoresist patterns to form the spacer, and the spacer is used as a mask in the patterning process.12-03-2009
20090149025Remover Compositions - A remover composition containing 1,3-propanediamine (a), 1-hydroxyethylidene-1,1-diphosphonic acid (b) and water, wherein the remover composition contains the component (a) in an amount of from 0.2 to 30% by weight, the component (b) in an amount of from 0.05 to 10% by weight, and the water in an amount of from 60 to 99.75% by weight, and wherein the composition has a pH at 20° C. of from 9 to 13; and a remover composition containing an organic amine (A), an organic phosphonic acid (B), a linear sugar alcohol (C) and water, wherein the remover composition contains the component (A) in an amount of from 0.2 to 30% by weight, the component (B) in an amount of from 0.05 to 10% by weight, the component (C) in an amount of from 0.1 to 10% by weight, and the water in an amount of from 50 to 99.65% by weight, and wherein the composition has a pH at 20° C. of from 9 to 13.06-11-2009
20090170324Reducing adherence in a MEMS device - In one embodiment, an apparatus for reducing adherence in a micro-electromechanical system (MEMS) device comprises a substrate. A MEMS is disposed outwardly from the substrate. The MEMS comprises structures and corresponding landing pads. Dibs are disposed outwardly from the substrate. Each dib has a surface with depressions. An adherence-reducing material is disposed within each depression. The adherence-reducing material reduces adherence between at least a portion of a structure and a corresponding landing pad.07-02-2009
20080280443Exposure Mask And Method Of Forming A Contact Hole Of A Semiconductor Device Employing The Same - An exposure mask and a method of forming a contact hole of a semiconductor device using the same, in which micro patterns can be formed are disclosed herein. In an aspect, an exposure mask method includes a mask substrate, a light-shield pattern formed on the mask substrate, and a transparent pattern in which a plurality of patterns, which are limited to the light-shield pattern and have different short-direction widths and long-direction widths, form a group which is repeatedly arranged. Accordingly, micro photoresist patterns can be formed uniformly.11-13-2008
20080280444METHOD OF FORMING MICRO PATTERN OF SEMICONDUCTOR DEVICE - The present invention relates to a method of forming a micro pattern of a semiconductor device. In the method according to an aspect of the present invention, an etch target layer, a first hard mask layer, and insulating patterns of a lonzenge are formed over a semiconductor substrate. A first auxiliary pattern is formed on the first hard mask layer including the insulating patterns, wherein a contact hole having the same shape as that of the insulating pattern is formed at the center of four adjacent insulating patterns, which form a quadrilateral. A second auxiliary pattern is formed by etching the first auxiliary pattern so that a top surface of the insulating patterns is exposed. The exposed insulating patterns are removed. A first hard mask pattern is formed by etching the first hard mask layer using an etch process employing the second auxiliary pattern as an etch mask. The etch target layer is etched using the first hard mask pattern.11-13-2008
20080286971CMOS Gate Structures Fabricated by Selective Oxidation - A sidewall image transfer process for forming sub-lithographic structures employs a layer of sacrificial material that is deposited over a structure layer and covered by a cover layer. The sacrificial material layer and the cover layer are patterned with conventional resist and etched to form a sacrificial mandrel. The edges of the mandrel are oxidized or nitrided in a plasma at low temperature, after which the material layer and the cover layer are stripped, leaving sublithographic sidewalls. The sidewalls are used as hardmasks to etch sublithographic gate structures in the gate conductor layer.11-20-2008
20080286970Method for producing a semiconductor component and a semiconductor component produced according to the method - A method for producing a semiconductor component includes forming an n-doped layer in a p-doped layer of the semiconductor component, wherein the n-doped layer comprises at least one of: a sieve-like layer or a network-like layer. The method also includes porously etching the p-doped layer between the material of the n-doped layer to form a top electrode, and forming a cavity below the n-doped layer.11-20-2008
20120295444TECHNIQUES FOR FORMING 3D STRUCTURES - A technique for forming 3D structures is disclosed. In one particular exemplary embodiment, the technique may be realized as a method for forming 3D structures. The method may comprise providing a substrate comprising at least two vertically extending fins that are spaced apart from one another to define a trench; depositing a dielectric material in the trench between the at least two vertically extending fins; providing an etch stop layer within the dielectric material, the etch stop layer having a first side and a second opposite side; removing the dielectric material near the first side of the etch stop layer.11-22-2012
20080242092METHOD OF MANUFACTURING SPACER - A method of manufacturing an L-shaped spacer is described. First, a substrate is provided and a protruding structure is formed thereon. Next, a dielectric material is formed on the substrate and covers the stacked structure. Then, the dielectric material on the top of the protruding structure and on portions of the substrate is removed to form an L-shaped spacer.10-02-2008
20080293248METHOD OF FORMING AMORPHOUS CARBON FILM AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAME - The present invention relates to a method of forming an amorphous carbon film and a method of manufacturing a semiconductor device using the method. An amorphous carbon film is formed on a substrate by vaporizing a liquid hydrocarbon compound, which has chain structure and one double bond, and supplying the compound to a chamber, and ionizing the compound. The amorphous carbon film is used as a hard mask film.11-27-2008
20100136790Method of fabricating semiconductor integrated circuit device - A method of fabricating a semiconductor integrated circuit device, including providing a semiconductor substrate, sequentially forming an etching target layer and a hard mask layer on the semiconductor substrate, forming first etch masks on the hard mask layer, the first etch masks including a plurality of first line patterns spaced apart from one another at a first pitch and extending in a first direction, forming first hard mask patterns by etching the hard mask layer using the first etch masks, forming second etch masks on the first hard mask patterns, the second etch masks including a plurality of second line patterns spaced apart from one another at a second pitch and extending in a second direction different from the first direction, forming second hard mask patterns by etching the first hard mask patterns using the second etch masks, forming spacers on sidewalls of the second hard mask patterns, and patterning the etching target layer using the second hard mask patterns having the spacers.06-03-2010
20110207328METHODS AND APPARATUS FOR THE MANUFACTURE OF MICROSTRUCTURES - A method of manufacturing microstructures is disclosed, the method comprising a applying a mask to substrate; forming a pattern in the mask; processing the substrate according to the pattern; and mechanically removing the mask from the substrate. A polymer mask is disclosed for manufacturing micro scale structure, the polymer mask comprising a thin, preferably ultra thin flexible film. A method of manufacturing an integrated circuit is disclosed, the method comprising forming a plurality of isolated semiconductor devices on a common substrate; and connecting some of the devices. Apparatus for manufacturing microstructures is disclosed comprising: a mechanism for coating a mass substrate to create a structure; a mechanism for removing a mask from the substrate; and processing apparatus. A thin film transistor is disclosed comprising drain source and gate electrodes, the drain and source electrode being separated by a semiconductor, and the gate electrode being separated from the semiconductor by an insulator, comprising a bandgap alignment layer disposed between a semiconductor and the insulator.08-25-2011
20090186484PATTERN FORMATION METHOD - After forming a resist film made from a chemically amplified resist material pattern exposure is carried out by selectively irradiating the resist film with exposing light while supplying, onto the resist film, water that includes triphenylsulfonium nonaflate, that is, an acid generator, and is circulated and temporarily stored in a solution storage. After the pattern exposure, the resist film is subjected to post-exposure bake and is then developed with an alkaline developer. Thus, a resist pattern made of an unexposed portion of the resist film can be formed in a good shape.07-23-2009
20090093120HOLE PATTERN FORMING METHOD AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A hole pattern forming method that forms a fine hole pattern in a work target layer that is formed on a semiconductor substrate, includes: forming a three-layer structure by laminating a carbon film layer, an intermediate mask layer, and a photoresist layer in that order on the work target layer; after patterning a hole pattern in the photoresist layer, patterning the hole pattern in the intermediate mask layer with the patterned photoresist layer serving as a mask; forming a sidewall oxide film on exposed portions of the photoresist layer, the intermediate mask layer, and the carbon film layer; forming a sidewall portion that includes the sidewall oxide film on inner wall surfaces of the hole pattern by etching back the sidewall oxide film; and after patterning a fine hole pattern in the carbon film layer with the sidewall portion and the intermediate mask layer serving as a mask, patterning the fine hole pattern in the work target layer with the patterned carbon film layer serving as a mask.04-09-2009
20100003822METHOD FOR PRODUCING COLUMNAR STRUCTURED MATERIAL - A microcolumnar structured material having a desired material. The columnar structured material includes columnar members obtained by introducing a filler into columnar holes formed in a porous material. The porous material has the columnar holes formed by removing columnar substances from a structured material in which the columnar substances containing a first component are dispersed in a matrix member containing a second component capable of forming a eutectic with the first component. The matrix member may be removed. In the columnar structured material, the filler is a conductive material, and an electrode can be structured by electrically connecting the conductive materials in at least a part of a plurality of holes to a conductor.01-07-2010
20090004866METHOD OF FORMING MICRO PATTERN OF SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes forming a target etch layer over a substrate, a first auxiliary layer over the target etch layer, an isolation layer over the first auxiliary layer, and a second auxiliary layer over the isolation layer. A first exposure process is performed, where the first auxiliary layer is in focus and the second auxiliary layer is out of focus. A second exposure process is performed, where the second auxiliary layer in focus and the first auxiliary layer is out of focus. The second auxiliary layer is developed to form first mask patterns. The isolation layer and the first auxiliary layer are etched by using the first mask patterns to form second mask patterns. The second mask patterns are developed to form third mask patterns that are used to facilitate subsequent etching of the target etch layer.01-01-2009
20110223767CONTROL WAFER RECLAMATION PROCESS - A method of recycling a control wafer having a low-k dielectric layer deposited thereon involves etching a portion of the low-k dielectric layer using a plasma resulting in a residual film of the low-k dielectric layer and byproduct particulates of carbon on the substrate. The residual dielectric film is removed by wet etching with a low polarization organic solvent that includes HF and a surfactant.09-15-2011
20110223765SILICON NITRIDE PASSIVATION LAYER FOR COVERING HIGH ASPECT RATIO FEATURES - A method of forming a passivation layer comprising silicon nitride on features of a substrate is described. In a first stage of the deposition method, a dielectric deposition gas, comprising a silicon-containing gas and a nitrogen-containing gas, is introduced into the process zone and energized to deposit a silicon nitride layer. In a second stage, a treatment gas, having a different composition than that of the dielectric deposition gas, is introduced into the process zone and energized to treat the silicon nitride layer. The first and second stages can be performed a plurality of times.09-15-2011
20110223766METHOD AND APPARATUS FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes: exposing an insulating film including a siloxane bond to an energy beam or plasma; and exposing the insulating film to a gas (excluding N09-15-2011
20130217232Method of Fabricating Semiconductor Cleaners - A method of manufacturing cleaning solvents is provided. The method includes selecting a small plurality of test solvents from a large plurality of perspective solvents. The equilibrium composition of a multi-component solution is preferably described by the Hansen solubility model. A small plurality of test solvents is applied to solute samples and the degree of dissolution or swelling recorded. Based on the degree of dissolution or swelling, at least one solvent is selected from the large plurality of perspective solvents based on the Hansen parameters.08-22-2013
20100248481CAD FLOW FOR 15NM/22NM MULTIPLE FINE GRAINED WIMPY GATE LENGTHS IN SIT GATE FLOW - Methods are described for forming an integrated circuit having multiple devices, such as transistors, with respective element lengths. The methods include a new CAD flow for producing masks used for exposing sidewall spacers which are to be etched to a smaller base width than other sidewall spacers and which in turn are used as an etch mask to form gate structures with smaller element lengths than those formed from the other sidewall spacers. Embodiments include generating a schematic of an integrated circuit and a corresponding netlist, establishing design rules for the integrated circuit, generating a computer aided design layout for the integrated circuit, plural transistors of the integrated circuit respectively having different gate lengths, checking the integrated circuit layout and netlist for compliance with the established design rules and for correspondence with the generated schematic, and generating a mask with different openings that correspond to the integrated circuit layout, in response to a satisfactory outcome of the checking step.09-30-2010
20090075480Silicon Carbide Doped Oxide Hardmask For Single and Dual Damascene Integration - Interconnects of integrated circuits (ICs) utilize low-k dielectrics, copper metal lines, dual damascene processing and amplified photoresist chemistry to build ICs with features smaller than 100 nm. Photolithographic processing of interconnects with these elements are subject to resist poisoning from nitrogen in etch stop and hard mask dielectric layers. Attempts to solve this problem cause lower IC circuit performance or higher fabrication process cost and complexity. This invention comprises a method of fabricating interconnects in an IC using layers of silicon carbide doped oxide (SiCO) in a via etch stop layer, in a trench etch stop layer, as a via etch hard mask and as a trench etch hard mask.03-19-2009
20090203216PHOTOLITHOGRAPHIC SYSTEMS AND METHODS FOR PRODUCING SUB-DIFFRACTION-LIMITED FEATURES - Systems and methods for near-field photolithography utilize surface plasmon resonances to enable imaging of pattern features that exceed the diffraction limit. An example near-field photolithography system includes a plasmon superlens template including a plurality of opaque features to be imaged onto photosensitive material and a metal plasmon superlens. The opaque features and the metal superlens are separated by a polymer spacer layer. Light propagates through the superlens template to form an image of the opaque features on the other side of the superlens. An intermediary layer including solid or liquid material is interposed between the superlens and a photoresist-coated semiconductor wafer to reduce damage resulting from contact between the superlens template and the photoresist-coated semiconductor wafer.08-13-2009
20090209105PATTERN FORMING METHOD, SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE MANUFACTURING APPARATUS - A pattern forming method for forming a pattern serving as a mask, includes a process for forming a first pattern 08-20-2009
20090221147METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device according to an embodiment includes: forming a core material on a workpiece material; forming a cover film to cover the upper and side surfaces of the core material; after forming the cover film, removing the core material; after removing the core material, removing the cover film while leaving portions thereof located on the side surfaces of the core material, so as to form sidewall spacer masks; and etching the workpiece material by using the sidewall spacer masks as a mask.09-03-2009
20090117743Film formation apparatus and method for using same - A method for using a film formation apparatus for a semiconductor process to form a thin film on a target substrate inside a reaction chamber includes performing a cleaning process to remove a by-product film deposited on a predetermined region in a gas route from a film formation gas supply system, which supplies a film formation gas contributory to film formation, through the reaction chamber to an exhaust system, by alternately repeating an etching step and an exhaust step a plurality of times in a state where the reaction chamber does not accommodate the target substrate. The etching step includes supplying a cleaning gas in an activated state for etching the by-product film onto the predetermined region, thereby etching the by-product film. The exhaust step includes stopping supply of the cleaning gas and exhausting gas by the exhaust system from a space in which the predetermined region is present.05-07-2009
20090117741METHOD FOR FABRICATING MONOLITHIC TWO-DIMENSIONAL NANOSTRUCTURES - A patterning method for the creation of two-dimensional nanowire structures. Nanowire patterning methods are used with lithographical patterning approaches to form patterns in a layer of epoxy and resist material. These patterns are then transferred to an underlying thin film to produce a two-dimensional structure with desired characteristics.05-07-2009
20090117742METHOD FOR FABRICATING FINE PATTERN IN SEMICONDUCTOR DEVICE - A method for fabricating a pattern in a semiconductor device includes a single polysilicon hard mask by appropriately selecting spacer material in an SPT, thereby decreasing the number of fabrication processes. Furthermore, since the spacers are easily removed, it is possible to prevent the formation of a step between patterns of a cell region and a peripheral region.05-07-2009
20090221146Nonvolatile memory device and manufacturing method for the same - The object of the present invention is to provide a manufacturing method for a nonvolatile memory device including a variable resistance having a constricted shape. The nonvolatile memory device of the present invention has a storage section composed of two electrodes and a variable resistance sandwiched between the electrodes. The variable resistance is formed to a constricted shape between the electrodes.09-03-2009
20090253265METHOD FOR FABRICATING SEMICONDUCTOR DEVICE AND SUBSTRATE PROCESSING APPARATUS - Provided is a method and a substrate processing apparatus for fabricating a semiconductor device by forming a film at a relatively high rate without etching an N10-08-2009
20090246958METHOD FOR REMOVING RESIDUES FROM A PATTERNED SUBSTRATE - The present invention relates to a method for removing residues from open areas of a patterned substrate involving the steps of providing a layer of a developable anti-reflective coating (DBARC) over a substrate; providing a layer of a photoresist over said DBARC layer; pattern-wise exposing said photoresist layer and said DBARC layer to a radiation; developing said photoresist layer and said DBARC layer with a first developer to form patterned structures in said photoresist and DBARC layers; depositing a layer of a developer soluble material over said patterned structures; and removing said developer soluble material with a second developer.10-01-2009
20090258496Method for fabricating semiconductor devices using strained silicon bearing material - A method of manufacturing an integrated circuit on semiconductor substrates, e.g., silicon wafer. The method includes providing a semiconductor substrate characterized by a first lattice with a first structure and a first spacing. In a specific embodiment, the semiconductor substrate has an overlying film of material with a second lattice with a second structure and a second spacing, the second spacing placing the film of material in a strain mode characterized by a first tensile and/or compressive mode along a single film surface crystal axis across a first portion of the film of material relative to the semiconductor substrate with the first structure and the first spacing. The method patterns a predetermined region of the first portion of the film of material to cause the first tensile and/or compressive mode in the first portion of the film of material to change to a second tensile and/or compressive mode in a resulting patterned portion of the first portion of the film of material. In a preferred embodiment, the patterns are made using a masking and etching process.10-15-2009
20090258494INLINE INTEGRATED CIRCUIT SYSTEM - An integrated circuit package system including: providing a leadframe with an integrated circuit mounted thereover; encapsulating the integrated circuit with an encapsulation; mounting an etch barrier below the leadframe; and etching the leadframe.10-15-2009
20090258495Modified darc stack for resist patterning - A method of making a device includes forming a device layer, forming an organic hard mask layer over the device layer, forming a first oxide hard mask layer over the organic hard mask layer, forming a DARC layer over the first oxide hard mask layer, forming a photoresist layer over the DARC layer, patterning the photoresist layer to form a photoresist pattern, and transferring the photoresist pattern to the device layer using the DARC layer, the first oxide hard mask layer and the organic hard mask layer.10-15-2009
20080311753OXYGEN SACVD TO FORM SACRIFICAL OXIDE LINERS IN SUBSTRATE GAPS - A method of forming and removing a sacrificial oxide layer is described. The method includes forming a step on a substrate, where the step has a top and sidewalls. The method may also include forming the sacrificial oxide layer around the step by chemical vapor deposition of molecular oxygen and TEOS, where the oxide layer is formed on the top and sidewalls of the step. The method may also include removing a top portion of the oxide layer and the step; removing a portion of the substrate exposed by the removal of the step to form a etched substrate; and removing the entire sacrificial oxide layer from the etched substrate.12-18-2008
20120034781METHOD FOR FABRICATING A SEMICONDUCTOR STRUCTURE - A method for fabricating a semiconductor structure is disclosed. The method includes the steps of: providing a substrate; depositing a material layer on the substrate; forming at least one dielectric layer on the material layer; forming a patterned resist on the dielectric layer; performing a first trimming process on at least the patterned resist; performing a second trimming process on at least the dielectric layer; and using the dielectric layer as mask for etching the material layer.02-09-2012
20080311751Method for Etching a Layer on a Substrate - A method for etching a layer that is to be removed on a substrate, in which a Si12-18-2008
20120244708Methods Of Patterning Materials - Some embodiments include methods of forming openings. For instance, a construction may have a material over a plurality of electrically conductive lines. A plurality of annular features may be formed over the material, with the annular features crossing the lines. A patterned mask may be formed over the annular features, with the patterned mask leaving segments of the annular features exposed through a window in the patterned mask. The exposed segments of the annular features may define a plurality of openings, and such openings may be transferred into the material to form openings extending to the electrically conductive lines.09-27-2012
20130122706METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, a method of manufacturing of a semiconductor device is provided. In the method, a front surface of a semiconductor substrate and a front surface of a support substrate are bonded to each other by an adhesive. A part of a circumferential part of the support substrate is subjected to water-repellent treatment to thereby form a water-repellent area on the part of the circumferential part in such a manner that the water-repellent area and an end face of the adhesive are in contact with each other. The semiconductor substrate is removed from a rear surface side by wet etching.05-16-2013
20130122707METHODS OF POLYMERS DEPOSITION FOR FORMING REDUCED CRITICAL DIMENSIONS - Methods of polymer deposition for forming reduced critical dimensions are described. In one embodiment, a substrate is provided into a chamber, the substrate having a patterned layer disposed on an underlying layer formed thereon. The patterned layer includes a plurality of openings, each opening having a sidewall, a bottom, and a critical dimension. A gas mixture is provided into the chamber, the gas mixture having an etching gas and a polymer control gas. The polymer control gas includes a polymerizing fluorocarbon C05-16-2013
20130122708Partial Die Process For Uniform Etch Loading Of Imprint Wafers - Methods, systems, and devices which result from, or facilitates, convenient processing of partial dies of a semiconductor chip in a lithography process are disclosed. Embodiments utilize an exposure through an imprint-style template which does not come in physical contact with the partial die. In one embodiment, a semiconductor process is disclosed which has at least one full die and at least one partial die. The semiconductor chip is fabricated, in part, by using an etching process which utilizes an imprint template configured to be exposed to the at least one full die when the imprint template is in contact with resist which has been dispensed onto the at least one full die. Further, at least one partial die of the semiconductor chip is configured to be exposed to the imprint template without the template contacting resist dispensed onto the at least one partial die.05-16-2013
20100173493SUBSTRATE PROCESSING METHOD - The present invention provides a substrate processing method to process a substrate including at least a process layer, an intermediate layer, and a mask layer which are stacked in this order. The mask layer includes an aperture configured to expose a portion of the intermediate layer. The substrate processing method includes a material deposition step of depositing a material on a side surface of the aperture and exposing a portion of the process layer by etching the exposed portion of the intermediate layer by plasma generated from a deposit gas, and an etching step of etching the exposed portion of the process layer.07-08-2010
20110111596Sidewall Image Transfer Using the Lithographic Stack as the Mandrel - In one non-limiting exemplary embodiment, a method includes: providing a structure having at least one lithographic layer on a substrate, where the at least one lithographic layer includes a planarization layer (PL); forming a sacrificial mandrel by patterning at least a portion of the at least one lithographic layer using a photolithographic process, where the sacrificial mandrel includes at least a portion of the PL; and producing at least one microstructure by using the sacrificial mandrel in a sidewall image transfer process.05-12-2011
20100261352METHOD FOR LOW-K DIELECTRIC ETCH WITH REDUCED DAMAGE - A method for etching features in a low-k dielectric layer disposed below an organic mask is provided by an embodiment of the invention. Features are etched into the low-k dielectric layer through the organic mask. A fluorocarbon layer is deposited on the low-k dielectric layer. The fluorocarbon layer is cured. The organic mask is stripped.10-14-2010
20100173494Method and apparatus for anisotropic etching - We suggest a method of anisotropic etching of the substrates, where ultra-thin and conformable layers of materials are used to passivate sidewalls of the etched features. According to an exemplary embodiment such sidewall passivation layer is a Self-assembled monolayer (SAM) material deposited in-situ etching process from a vapor phase. According to another exemplary embodiment such sidewall passivation layer is an inorganic-based material deposited using Atomic Layer Deposition (ALD) method. SAM or ALD layers deposition can be carried out in a pulsing regime alternating with an sputtering and/or etching processes using process gasses with or without plasma. Alternatively, SAM deposition process is carried out continuously, while etch or sputtering process turns on in a pulsing regime. Alternatively, SAM deposition process and etch or sputtering processes are carried out continuously. Both types of suggested passivation materials give advantage over state-of-the-art methods in ability to carefully control thickness and uniformity of the layers, thus enable anisotropic etching process for high aspect ratio nanosize features.07-08-2010
20100159701EXPOSURE MASK AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAME - A method for manufacturing a semiconductor device comprises performing an exposing and developing process using an exposure mask including shading patterns and assistant patterns arranged in parallel to the shading patterns to prevent a scum phenomenon generated when a main pattern is formed in a cell region over a semiconductor substrate, thereby improving characteristics, reliability and yield of the semiconductor device. As a result, the method enables high-integration of the semiconductor device.06-24-2010
20100216310Process for etching anti-reflective coating to improve roughness, selectivity and CD shrink - A method of dry developing an anti-reflective coating (ARC) layer on a substrate is described. The method comprises disposing a substrate comprising a multi-layer mask in a plasma processing system, wherein the multi-layer mask comprises a lithographic layer overlying a silicon-containing ARC layer and wherein the lithographic layer comprises a feature pattern formed therein using a lithographic process. The method further comprises: introducing a process gas to the plasma processing system according to a process recipe, the process gas comprising a nitrogen-containing gas, a hydrogen-containing gas, and a C08-26-2010
20100184294Method of Manufacturing a Semiconductor Device - In a method of manufacturing a semiconductor device, a substrate is loaded to a process chamber having, unit process sections in which unit processes are performed, respectively. The unit processes are performed on the substrate independently from one another at the unit process sections under a respective process pressure. The substrate sequentially undergoes the unit processes at the respective unit process section of the process chamber. Cleaning processes are individually performed to the unit process sections, respectively, when the substrate is transferred from each of the unit process sections and no substrate is positioned at the unit process sections. Accordingly, the process defects of the process units may be sufficiently prevented and the operation period of the manufacturing apparatus is sufficiently elongated.07-22-2010
20080214008METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - In a method of manufacturing a semiconductor device, a plurality of structures are formed on a substrate, and a coating film is formed over a whole surface of the substrate to cover the plurality of structures. A photoresist layer is formed to have an opening portion above a target structure of the plurality of structures, and the coating film on a side of the opening is etched to expose a part of the target structure by using the photoresist layer as a mask while maintaining the substrate in a state covered with the coating film. Also, a target portion as at least a portion of the target structure is etched while leaving the coating film, and the photoresist layer and the coating film are removed.09-04-2008
20110003478POLYMER FOR ORGANIC ANTI-REFLECTIVE COATING LAYER AND COMPOSITION INCLUDING THE SAME - A polymer which has siloxane group at a main chain thereof and a composition including the same, for forming an organic anti-reflective coating layer are disclosed. The polymer for forming an organic anti-reflective coating layer is represented by following Formula.01-06-2011
20100144151Methods of Fabricating Substrates - A method of fabricating a substrate includes forming spaced first features over a substrate. An alterable material is deposited over the spaced first features and the alterable material is altered with material from the spaced first features to form altered material on sidewalls of the spaced first features. A first material is deposited over the altered material, and is of some different composition from that of the altered material. The first material is etched to expose the altered material and spaced second features comprising the first material are formed on sidewalls of the altered material. Then, the altered material is etched from between the spaced second features and the spaced first features. The substrate is processed through a mask pattern comprising the spaced first features and the spaced second features. Other embodiments are disclosed.06-10-2010
20100144150Methods of Fabricating Substrates - A method of fabricating a substrate includes forming first and second spaced features over a substrate. The first spaced features have elevationally outermost regions which are different in composition from elevationally outermost regions of the second spaced features. The first and second spaced features alternate with one another. Every other first feature is removed from the substrate and pairs of immediately adjacent second features are formed which alternate with individual of remaining of the first features. After such act of removing, the substrate is processed through a mask pattern comprising the pairs of immediately adjacent second features which alternate with individual of the remaining of the first features. Other embodiments are disclosed.06-10-2010
20100099261METHOD FOR FORMING PATTERN OF SEMICONDUCTOR DEVICE - A method for forming a pattern of a semiconductor device comprises: forming a stacked film including an underlying layer, an antireflection film and a photoresist film over a semiconductor substrate; coating an over-coating composition over the photoresist film to form an over-coating film; performing an exposing and developing process with a cell mask on the photoresist film where the over-coating film is formed to form a photoresist pattern; forming a silicon-containing-RELACS layer over the antireflection film including the photoresist pattern where the over-coating film is formed; removing the over-coating film and the silicon containing RELACS layer on the photoresist pattern to form a spacer of the silicon containing RELACS layer at sidewalls of the photoresist pattern; removing the photoresist pattern; and etching the antireflection film and the underlying layer with the spacer of the silicon containing RELACS layer as a mask to form an antireflection pattern and an underlying pattern.04-22-2010
20100197139METHOD OF FORMING A HARD MASK AND METHOD OF FORMING A FINE PATTERN OF SEMICONDUCTOR DEVICE USING THE SAME - A method of forming hard mask employs a double patterning technique. A first hard mask layer is formed on a substrate, and a first sacrificial pattern is formed on the first hard mask layer by photolithography. Features of the first sacrificial pattern are spaced from one another by a first pitch. A second hard mask layer is then formed conformally on the first sacrificial pattern and the first hard mask layer so as to delimit recesses between adjacent features of the first sacrificial pattern. Upper portions of the second hard mask layer are removed to expose the first sacrificial pattern, and the exposed first sacrificial pattern and the second sacrificial pattern are removed. The second hard mask layer and the first hard mask layer are then etched to form a hard mask composed of residual portions of the first hard mask layer and the second hard mask layer. A fine pattern of a semiconductor device, such as a trench isolation region or a pattern of contact holes, can be formed using the hard mask as an etch mask.08-05-2010
20100062602Etching method, method for producing dielectric film of low dielectric constant, method for producing porous member, etching system and thin film forming equipment - To provide an etching method employing a novel CVD system and an etching apparatus applicable to the method.03-11-2010
20100221919Method of forming patterns for semiconductor device - Provided is a method of forming patterns for a semiconductor device in which fine patterns and large-width patterns are formed simultaneously and adjacent to each other. In the method, a first layer is formed on a substrate so as to cover a first region and a second region which are included in the substrate. Both a blocking pattern covering a portion of the first layer in the first region and a low-density large-width pattern covering a portion of the first layer in the second region are simultaneously formed. A plurality of sacrificial mask patterns are formed on the first layer and the blocking pattern in the first region. A plurality of spacers covering exposed sidewalls of the plurality of sacrificial mask patterns are formed. The plurality of sacrificial mask patterns are removed. The first layer in the first and second regions are simultaneously etched by using the plurality of spacers and the blocking pattern as etch masks in the first region and using the low-density large-width pattern as an etch mask in the second region.09-02-2010
20100197137PLASMA PROCESSING APPARATUS AND PLASMA PROCESSING METHOD - A plasma processing apparatus includes a processing chamber arranged in a vacuum vessel. A wafer placed on a sample stage in the processing chamber is processed using a plasma formed in the processing chamber. Before etching the film layers provided on the wafer composed of a metal substance and an underlying oxide film or a material having a high dielectric constant, another wafer, provided on a surface thereof a film composed of a metal of the same kind as the metal substance, is processed and particles of the metal are deposited on an inner wall of said processing chamber.08-05-2010
20100197138METHOD AND APPARATUS FOR ETCHING - Embodiments of the invention relate to a substrate etching method and apparatus. In one embodiment, a method for etching a substrate in a plasma etch reactor is provided that include flowing a backside process gas between a substrate and a substrate support assembly, and cyclically etching a layer on the substrate.08-05-2010
20090275201SUBSTRATE PROCESSING SYSTEM - A substrate processing method implemented in a substrate processing system that includes an etching apparatus that carries out plasma etching processing on a substrate and a vacuum-type substrate transferring apparatus to which the etching apparatus is connected is provided. A first step includes forming a protective film on a rear surface of the substrate before the plasma etching processing is carried out. The protective film prevents the rear surface of the substrate from being scratched by an electrostatic chuck that electrostatically attracts the substrate during the plasma etching processing. A second step includes electrostatically attracting the substrate to the electrostatic chuck such that the electrostatic chuck directly contacts the rear surface of the substrate and of carrying out the plasma etching processing on the substrate. A third step includes removing the protective film from the rear surface of the substrate after the plasma etching processing has been carried out.11-05-2009
20090111270Method for Forming Patterns in Semiconductor Memory Device - A method for forming patterns in a semiconductor memory device, wherein first spacers arranged at a first spacing and second spacers arranged at a second spacing are formed on a target layer which is formed on a semiconductor substrate. A mask pattern is formed to cover a portion of the target layer defined by the two adjacent second spacers. At least two first patterns and at least one second pattern is formed by patterning the target layer using the first spacers, the second spacers and the mask pattern as an etch mask. Here, the second pattern is wider than the first pattern.04-30-2009
20100297847Method of forming sub-lithographic features using directed self-assembly of polymers - Methods involving the self-assembly of block copolymers are described herein, in which by beginning with openings (in one or more substrates) that have a targeted CD (critical dimension), holes are formed, in either regular arrays or arbitrary arrangements. Significantly, the percentage variation in the average diameter of the formed holes is less than the percentage variation of the average diameter of the initial openings. The formed holes (or vias) can be transferred into the underlying substrate(s), and these holes may then be backfilled with material, such as a metallic conductor. Preferred aspects of the invention enable the creation of vias with tighter pitch and better CD uniformity, even at sub-22 nm technology nodes.11-25-2010
20130137266MANUFACTURING TECHNIQUES TO LIMIT DAMAGE ON WORKPIECE WITH VARYING TOPOGRAPHIES - Some embodiments relate to a method for processing a workpiece. In the method, a first photoresist layer is provided over the workpiece, wherein the first photoresist layer has a first photoresist tone. The first photoresist layer is patterned to provide a first opening exposing a first portion of the workpiece. A second photoresist layer is then provided over the patterned first photoresist layer, wherein the second photoresist layer has a second photoresist tone opposite the first photoresist tone. The second photoresist layer is then patterned to provide a second opening that at least partially overlaps the first opening to define a coincidentally exposed workpiece region. A treatment is then performed on the coincidentally exposed workpiece region. Other embodiments are also disclosed.05-30-2013
20130137267Methods for Atomic Layer Etching - Provided are methods of etching a substrate using atomic layer deposition apparatus. Atomic layer deposition apparatus including a gas distribution plate with a thermal element are discussed. The thermal element is capable of locally changing the temperature of a portion of the surface of the substrate to vaporize an etch layer deposited on the substrate.05-30-2013
20130137268METHOD FOR PATTERN FORMATION - According to one embodiment, a method for pattern formation comprises forming a first pattern on a first region of a processed film, forming a reverse material film, having a photosensitive compound, on the processed film so that the reverse material film covers the first pattern, exposing and developing the reverse material film and processing the reverse material film into a second pattern in a second region different from the first region on the processed film, applying etch-back, after exposing and developing the reverse material film, to the reverse material film to expose an upper surface of the first pattern and processing the reverse material film into a third pattern in the first region, and etching the processed film using the second pattern and the third pattern as masks.05-30-2013
20090068842METHOD FOR FORMING MICROPATTERNS IN SEMICONDUCTOR DEVICE - A method for forming a semiconductor device includes forming an etch target layer over a substrate, forming a first etch stop layer over the etch target layer, forming a second etch stop layer over the first etch stop layer, forming a first sacrificial layer over the second etch stop layer, forming first sacrificial patterns by selectively etching the first sacrificial layer, forming second sacrificial layer over the second etch stop layer and the first sacrificial patterns, etching the second sacrificial layer and the second etch stop layer until the first sacrificial patterns are exposed and the second sacrificial layer remain only on sidewalls of the first sacrificial patterns, removing the exposed first sacrificial patterns, etching the exposed second etch stop layer mask to define a plurality of first structures, etching the first etch stop layer, and etching the etch target layer.03-12-2009
20110117741Method of fabricating SOI wafer - There is provided a method of fabricating an SOI wafer, the method including: a) preparing a bonded SOI substrate that has a buried oxide layer and an SOI layer formed in this sequence on a circular plate shaped support, and at a peripheral edge portion of the support substrate, has a silicon island region in which the SOI layer is not well formed with scattered defective silicon layer; b) etching a silicon island region defective silicon layer to remove the defective silicon layer scattered in the silicon island region by dry etching; and c) etching a silicon island region buried oxide layer to remove the buried oxide layer in the silicon island region by wet etching.05-19-2011
20100261351Spacer Linewidth Control - A method for forming a plurality of variable linewidth spacers adjoining a plurality of uniformly spaced topographic features uses a conformal resist layer upon a spacer material layer located over the plurality of uniformly spaced topographic features. The conformal resist layer is differentially exposed and developed to provide a differential thickness resist layer that is used as a sacrificial mask when forming the variable linewidth spacers. A method for forming uniform linewidth spacers adjoining narrowly spaced topographic features and widely spaced topographic features over the same substrate uses a masked isotropic etching of a variable thickness spacer material layer to provide a more uniform partially etched spacer material layer, followed by an unmasked anisotropic etching of the partially etched spacer material layer. A related method for forming the uniform linewidth spacers uses a two-step anisotropic etch method that includes at least one masking process step.10-14-2010
20100048022SEMICONDUCTOR MANUFACTURING APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor manufacturing apparatus that forms a carbon film on a wafer by plasma enhanced chemical vapor deposition includes a body having a top opening; a stage provided within the body for placement of the wafer; a showerhead that encloses the top opening and that introduces a deposition gas or an etch gas; and a gas delivery system including a central gas inlet that introduces gas toward a central portion of the wafer from a central portion of the showerhead, and a peripheral gas inlet that introduces gas toward a bevel of the wafer from an outer peripheral portion of the showerhead, wherein the gas delivery system, after activating the etch gas outside the body, delivers the activated etch gas toward the bevel of the wafer to selectively remove a portion of the carbon film formed on the bevel of the wafer.02-25-2010
20100178769SPACER FORMATION FOR ARRAY DOUBLE PATTERNING - A method for forming an array area with a surrounding periphery area, wherein a substrate is disposed under an etch layer, which is disposed under a patterned organic mask defining the array area and covers the entire periphery area is provided. The patterned organic mask is trimmed. An inorganic layer is deposited over the patterned organic mask where a thickness of the inorganic layer over the covered periphery area of the organic mask is greater than a thickness of the inorganic layer over the array area of the organic mask. The inorganic layer is etched back to expose the organic mask and form inorganic spacers in the array area, while leaving the organic mask in the periphery area unexposed. The organic mask exposed in the array area is stripped, while leaving the inorganic spacers in place and protecting the organic mask in the periphery area.07-15-2010
20100178770Method of etching a thin film using pressure modulation - A method for transferring a feature pattern to a thin film on a substrate is described. The method comprises disposing a substrate comprising one or more mask layers overlying a thin film in a plasma processing system, and forming a feature pattern in the one or more mask layers. The method further comprises transferring the feature pattern in the one or more mask layers to the thin film by: performing a first plasma etching process at a first pressure less than about 80 mtorr, and performing a second plasma etching process at a second pressure greater than about 80 mtorr.07-15-2010
20110244686INORGANIC RAPID ALTERNATING PROCESS FOR SILICON ETCH - A method for etching features into a silicon substrate disposed below a mask in a plasma processing chamber is provided. The silicon substrate is etched through the mask comprising a plurality of cycles, wherein each cycle comprises a sidewall deposition phase and an etch phase. The sidewall deposition phase comprises providing a flow of sidewall inorganic deposition phase gas comprising a silicon containing compound gas and at least one of oxygen, nitrogen or NO10-06-2011
20120034783MANUFACTURING INTEGRATED CIRCUIT COMPONENTS HAVING MULTIPLE GATE OXIDATIONS - STI divot formation is minimized and STI field height mismatch between different regions is eliminated. A nitride cover layer (02-09-2012
20110212622SURFACE TEXTURING USING A LOW QUALITY DIELECTRIC LAYER - A low cost method is described for forming a textured Si surface such as for a solar cell which includes forming a dielectric layer containing pinholes, anisotropically etching through the pinholes to form inverted pyramids in the Si surface and removing the dielectric layer thereby producing a high light trapping efficiency for incident radiation.09-01-2011
20100035434PLASMA TREATMENT OF A SEMICONDUCTOR SURFACE FOR ENHANCED NUCLEATION OF A METAL-CONTAINING LAYER - A method for forming a dielectric layer is provided. The method may include providing a semiconductor surface and etching a thin layer of the semiconductor substrate to expose a surface of the semiconductor surface, wherein the exposed surface is hydrophobic. The method may further include treating the exposed surface of the semiconductor substrate with plasma to neutralize a hydrophobicity associated with the exposed surface, wherein the exposed surface is treated using plasma with a power in a range of 02-11-2010
20090311866METHOD AND APPARATUS FOR PRODUCTION OF METAL FILM OR THE LIKE - In a metal film production apparatus, a copper plate member is etched with a Cl12-17-2009
20090311865Method for double patterning lithography - A method for double patterning lithography includes: (a) forming a first pattern on a first material layer that is formed on a semiconductor substrate, the first pattern having a plurality of first parts extending in a first direction and spaced apart along a second direction transverse to the first direction, and a plurality of first gaps among the first parts; (b) forming a second pattern on the first pattern, the second pattern having a plurality of second parts extending in the second direction and spaced apart along the first direction, and a plurality of second gaps among the second parts, the first and second gaps intersecting each other and cooperatively defining a plurality of uncovering regions where the first and second gaps intersect each other; and (c) etching portions of the first material layer exposed via the uncovering regions.12-17-2009
20100009541Process for Adjusting the Size and Shape of Nanostructures - In accordance with the invention, a lateral dimension of a microscale device on a substrate is reduced or adjusted by the steps of providing the device with a soft or softened exposed surface; placing a guiding plate adjacent the soft or softened exposed surface; and pressing the guiding plate onto the exposed surface. Under pressure, the soft material flows laterally between the guiding plate and the substrate. Such pressure induced flow can reduce the lateral dimension of line spacing or the size of holes and increase the size of mesas. The same process also can repair defects such as line edge roughness and sloped sidewalls. This process will be referred to herein as pressed self-perfection by liquefaction or P-SPEL.01-14-2010
20110177691METHOD FOR FORMING HOLE PATTERN - A method for forming a hole pattern includes forming a hard mask layer for a hole pattern over an etch target layer, forming pillar patterns having a gap therebetween over the hard mask layer for a hole pattern, forming spacer patterns on sidewalls of the pillar patterns, removing the pillar patterns between the spacer patterns, and etching the hard mask layer for a hole pattern by using the spacer patterns as etch barriers.07-21-2011
20100055910EXPOSURE MASK AND METHOD FOR FORMING SEMICONDUCTOR DEVICE USING THE SAME - Disclosed herein is a method for forming a semiconductor device that stacks an etched layer and a first hard mask layer on a semiconductor substrate, patterns the first hard mask layer in a high density region and a low density region, using a first exposure mask, forms a first spacer on a sidewall of the first hard mask layer in the high density region, forms a second spacer on a sidewall of the first hard mask layer in the low density region at the same time, etches an end with the first spacer connected thereto using a second exposure mask to thereby form a first spacer pattern, forms a planarized second hard mask layer that exposes the first spacer pattern and the second spacer, removes the first spacer pattern and the second spacer such that the second hard mask layer is left, and etches the etched layer using the second hard mask layer as an mask. This method makes it possible to easily form a micro pattern in the high density region and the low density region.03-04-2010
20100055911PLASMA PROCESSING METHOD AND RESIST PATTERN MODIFYING METHOD - A plasma processing method includes modifying a resist pattern of the substrate; and trimming the modified resist pattern through a plasma etching. The modifying includes: supplying the processing gas for modification from the processing gas supply unit to the inside of the processing chamber while the substrate having a surface on which the resist pattern is formed is mounted on the lower electrode; supplying the high frequency power from the high frequency power supply to generate a plasma of the processing gas for modification; and supplying the negative DC voltage from the DC power supply to the upper electrode.03-04-2010
20100068884METHOD OF ETCHING A LAYER OF A SEMICONDUCTOR DEVICE USING AN ETCHANT LAYER - A method of semiconductor fabrication including an etching process is provided. The method includes providing a substrate and forming a target layer on the substrate. An etchant layer is formed on the target layer. The etchant layer reacts with the target layer and etches a portion of the target layer. In an embodiment, an atomic layer of the target layer is etched. The etchant layer is then removed from the substrate. The process may be iterated any number of times to remove a desired amount of the target layer. In an embodiment, the method provides for decreased lateral etching. The etchant layer may provide for improved control in forming patterns in thin target layers such as, capping layers or high-k dielectric layers of a gate structure.03-18-2010
20110097899METHOD OF FORMING FUNNEL-SHAPED OPENING - A method of forming a funnel-shaped opening is provided. First, a substrate is provided, wherein a conductive layer is formed on the substrate. Then, a dielectric layer is formed over the conductive layer. Further, a first opening is formed in the dielectric layer, wherein the first opening exposes the conductive layer. Thereafter, a portion of the dielectric layer at a top corner of the first opening is removed to form a second opening by an etching gas containing argon in a reaction chamber, wherein a power of the reaction chamber is about 500˜1800 W.04-28-2011
20090087990Manufacturing method, manufacturing apparatus, control program and program recording medium of semiconductor device - A manufacturing method of a semiconductor device, which etches a layer to be etched on a substrate into a predetermined pattern based on a first pattern of photoresist produced by exposing and developing a photoresist film, the manufacturing method including the steps of forming an SiO04-02-2009
20110256723METHOD FOR FORMING SEMICONDUCTOR DEVICE - A method for forming a semiconductor device is disclosed. A method for forming a semiconductor device includes forming a first sacrificial hard mask layer over a semiconductor substrate including an etch layer, forming a first spacer over the first sacrificial hard mask layer, forming a first sacrificial hard mask pattern by etching the first sacrificial hard mask layer using the first spacer as an etch mask, forming a second spacer at both sidewalls of the first sacrificial hard mask pattern, partially isolating the second spacer, and forming a pad pattern over the second spacer. As a result, a line-and-space pattern such as a control gate of the NAND flash memory and a pad portion coupled to a drain contact in an X-decoder of a peripheral circuit region can be easily implemented.10-20-2011
20110212623Substrate treatment device - It is intended to provide a substrate treatment device capable of adjusting both of a growth speed and an etching speed in a selective epitaxial growth, avoiding particle generation from nozzles, and achieving good etching characteristics. A substrate treatment device for selectively growing an epitaxial film on a surface of a substrate by alternately supplying a raw material gas containing silicon and an etching gas to a treatment chamber, the substrate treatment device being provided with a substrate support member for supporting the substrate in the treatment chamber, a heating member provided outside the treatment chamber for heating the substrate and an atmosphere of the treatment chamber, a gas supply system provided inside the treatment chamber, and a discharge port opened on the treatment chamber, wherein the gas supply system comprises first gas supply nozzles for supplying the raw material gas and second gas supply nozzles for supplying the etching gas.09-01-2011
20090004865METHOD FOR TREATING A WAFER EDGE - A method for treating an edge portion of a wafer with a plasma or select chemical formulation in order to enhance adhesion characteristics and inhibit delamination of a layer of material from the wafer surface only on the edge portion that is being treated. Alternatively, the method may be utilized to effectuate a cleaning of an edge portion of a wafer.01-01-2009
20090253264THIN FILM FORMATION METHOD AND MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE - A method of forming a thin film including a first portion having a first film thickness and a second portion having a second film thickness thinner than the first film thickness. A thin film having the first film thickness is formed on a substrate, an interference waveform upon film formation from reflected light by irradiating with laser light is acquired, the second portion of the thin film is etched, an interference waveform upon etching is acquired by irradiating, with laser light, the second portion, and calculating an interference waveform upon target etching on condition that the second portion has the second film thickness, based on the interference waveform upon film formation. The etching is stopped when the interference waveform upon etching becomes the same as the interference waveform upon target etching.10-08-2009
20090137125ETCHING METHOD AND ETCHING APPARATUS - Disclosed is an etching method for etching a target layer formed on a surface of a target object, including: a resist forming step for forming a resist layer uniformly on the surface of the target object; a mask forming step for forming a patterned etching mask by forming an etching recess on the resist layer; a plasma resistant film forming step for forming a plasma resistant film on the entire surface of the etching mask including a bottom and a sidewall of the etching recess; a bottom plasma resistant film removing step for removing the plasma resistant film formed on the bottom of the etching recess; and a main etching step for etching the target layer by using the etching mask as a mask, after the bottom plasma resistant film removing step.05-28-2009
20110256724GAS AND LIQUID INJECTION METHODS AND APPARATUS - A liquid injection system for a processing chamber includes a liquid injector that receives a liquid from a liquid supply and that selectively pulses the liquid into a conduit. A control module selects a number of pulses and a pulse width of the liquid injector. A gas supply supplies gas into the conduit. A sensor senses at least one of a first temperature and a first pressure in the conduit and that generates at least one of a first temperature signal and a first pressure signal, respectively. The control module confirms that the selected number of pulses occur based on the at least one of the first temperature signal and the first pressure signal.10-20-2011
20080242093Method for manufacturing semiconductor integrated circuit device - Cracks are generated in a resist film part used to form an opening part in a photoreceptor part, whereby etching is performed as far as the inter-layer insulating film in unintended portions. In order to prevent this, the resist pattern used as an etching mask is formed in a shape that disperses the stress. The stress is generated because the resist is hardened by post baking after having been exposed and developed. In order to disperse the stress, the opening part of the resist pattern is formed in a planar shape that has no corners.10-02-2008
20110256725STRUCTURE AND METHOD FOR THIN FILM DEVICE WITH STRANDED CONDUCTOR - Provided is a thin film device and an associated method of making a thin film device. For example, fabrication of an inverter thin film device is described. Moreover, a parallel spaced electrically conductive strips are provided upon a substrate. A functional material is deposited upon the conductive strips. A 3D structure is then provided upon the functional material, the 3D structure having a plurality of different heights, at least one height defining a first portion of the conductive strips to be bundled. The 3D structure and functional material are then etched to define a TFD disposed above the first portion of the conductive strips. The first portion of the conductive strips is bundled adjacent to the TFD.10-20-2011
20080254630DEVICE AND METHODOLOGY FOR REDUCING EFFECTIVE DIELECTRIC CONSTANT IN SEMICONDUCTOR DEVICES - Method of manufacturing a semiconductor device structure, including the steps of providing a structure having an insulator layer with at least one interconnect, forming a sub lithographic template mask over the insulator layer, and selectively etching the insulator layer through the sub lithographic template mask to form sub lithographic features spanning to a sidewall of the at least one interconnect.10-16-2008
20120149199SAMPLE CONTAMINATION METHOD - A sample contamination method according to an embodiment includes spraying a chemical solution containing contaminants into a casing, carrying a semiconductor substrate into the casing filled with the chemical solution by the spraying, leaving the semiconductor substrate in the casing filled with the chemical solution for a predetermined time, and carrying the semiconductor substrate out of the casing after the predetermined time passes.06-14-2012
20110021027METHODS FOR FABRICATING NON-PLANAR ELECTRONIC DEVICES HAVING SIDEWALL SPACERS FORMED ADJACENT SELECTED SURFACES - Methods are provided for fabricating an electronic device having at least one sidewall spacer formed adjacent a selected surface. In one embodiment, the method includes the step of depositing spacer material adjacent first and second raised structures formed on the substrate and extending along substantially perpendicular axes. The method further includes the step of selectively removing spacer material laterally adjacent one of the first raised structure and the second raised structure. During the step of selectively removing, the electronic device is bombarded with ions from a first predetermined direction forming a first predetermined grazing angle with the substrate such that the spacer material adjacent a first sidewall of the first raised structure is substantially exposed to the ion bombardment while the spacer material adjacent opposing sidewalls of the second raised structure is substantially shielded therefrom.01-27-2011
20110263127Method for Fabricating Low-k Dielectric and Cu Interconnect - A system and method for improving the performance of an integrated circuit by lowering RC delay time is provided. A preferred embodiment comprises adding a reactive etch gas to the ash/flush plasma process following a low-k dielectric etch. The illustrative embodiments implement a removal of the damage layer that is formed during a low-k dielectric etch.10-27-2011
20100240217SUBSTRATE PROCESSING METHOD - A method of processing a substrate having a processing target layer and an organic film serving as a mask layer includes a mineralizing process of mineralizing the organic film. The mineralizing process includes an adsorption process for allowing a silicon-containing gas to be adsorbed onto a surface of the organic film; and an oxidation process for oxidizing the adsorbed silicon-containing gas to be converted into a silicon oxide film. A monovalent aminosilane is employed as the silicon-containing gas.09-23-2010
20110136345Process for the Manufacture of Etched Items - C4 compounds selected from the group of trifluorobutadienes and tetrafluorobutenes can be used as etching gases, especially for anisotropic etching in the production of etched items, for example, of semiconductors, e.g. semiconductor memories or semiconductor logic circuits, flat panels, or solar cells. Preferred compounds are 1,1,3-trifluoro-1,3-butadiene, (E)-1,1,1,3-tetrafluoro-2-butene, 2,4,4,4-tetrafluoro-06-09-2011
20080206999METHOD FOR WET ETCHING WHILE FORMING INTERCONNECT TRENCH IN INSULATING FILM - A wet etching method that includes forming an insulating film on a substrate, and irradiating laser light to the insulating film during wet etching of the insulating film using an etching solution.08-28-2008
20090117744Ion implantation mask forming method - A method of forming an ion implantation mask includes forming a field area on a semiconductor substrate, forming an amorphous carbon layer on the semiconductor substrate, forming a hard mask layer on the amorphous carbon layer, forming an etching mask pattern on the hard mask layer, and etching the hard mask layer and the amorphous carbon layer to expose the field area through the etching mask pattern, wherein etching the hard mask layer and the amorphous carbon layer forms a hard mask layer pattern and an amorphous carbon layer pattern.05-07-2009
20100167548METHOD FOR FORMING FINE PATTERN USING QUADRUPLE PATTERNING IN SEMICONDUCTOR DEVICE - A method for forming a fine pattern in a semiconductor device using a quadruple patterning includes forming a first partition layer over a first material layer which is formed over a substrate, performing a photo etch process on the first partition layer to form a first partition pattern, performing an oxidation process to form a first spacer sacrificial layer over a surface of the first partition pattern, forming a second spacer sacrificial layer over the substrate structure, forming a second partition layer filling gaps between the first partition pattern, removing the second spacer sacrificial layer, performing an oxidation process to form a third spacer sacrificial layer over a surface of the second partition layer and define a second partition pattern, forming a third partition pattern filling gaps between the first partition pattern and the second partition pattern, and removing the first and third spacer sacrificial layers.07-01-2010
20090197416SILICON NANO WIRE HAVING A SILICON-NITRIDE SHELL AND MTHOD OF MANUFACTURING THE SAME - Silicon nano wires having silicon nitride shells and a method of manufacturing the same are provided. Each silicon nano wire has a core portion formed of silicon, and a shell portion formed of silicon nitride surrounding the core portion. The method includes removing silicon oxide formed on the shell of the silicon nano wire and forming a silicon nitride shell.08-06-2009
20120309194METHOD FOR PROVIDING HIGH ETCH RATE - A method for etching features into an etch layer in a plasma processing chamber, comprising a plurality of cycles is provided. Each cycle comprises a deposition phase and an etching phase. The deposition phase comprises providing a flow of deposition gas, forming a plasma from the deposition gas in the plasma processing chamber, providing a first bias during the deposition phase to provide an anisotropic deposition, and stopping the flow of the deposition gas into the plasma processing chamber. The etching phase, comprises providing a flow of an etch gas, forming a plasma from the etch gas in the plasma processing chamber, providing a second bias during the etch phase, wherein the first bias is greater than the second bias, and stopping the flow of the etch gas into the plasma processing chamber.12-06-2012
20100190341APPARATUS, METHOD FOR DEPOSITING THIN FILM ON WAFER AND METHOD FOR GAP-FILLING TRENCH USING THE SAME - Provided are an apparatus and method for depositing a thin film, and a method for gap-filling a trench in a semiconductor device. The thin film depositing apparatus includes a plurality of substrates provided on the same space inside a reactor, wherein deposition of the thin film and partial etching of the deposited thin film are repeated to form the thin film on the plurality of substrates by exposing the substrates to two or more source gases and an etching gas supplied together at predetermined time intervals while rotating the substrates. According to exemplary embodiments, it is possible to concurrently or alternatively perform deposition and etching of a thin film, so that a thin film with good gap-fill capability can be deposited.07-29-2010
20100190342PATTERN GENERATING METHOD, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, COMPUTER PROGRAM PRODUCT, AND PATTERN-SHAPE-DETERMINATION-PARAMETER GENERATING METHOD - A pattern generating method includes: extracting, from a shape of a pattern generated on a substrate, a contour of the pattern shape; setting evaluation points as verification points for the pattern shape on the contour; calculating curvatures on the contour in the evaluation points; and verifying the pattern shape based on whether the curvatures satisfy a predetermined threshold set in advance.07-29-2010
20100190344Methods of Forming Semiconductor Constructions - The invention includes methods in which silicon is removed from titanium-containing container structures with an etching composition having a phosphorus-and-oxygen-containing compound therein. The etching composition can, for example, include one or both of ammonium hydroxide and tetra-methyl ammonium hydroxide. The invention also includes methods in which titanium-containing whiskers are removed from between titanium-containing capacitor electrodes. Such removal can be, for example, accomplished with an etch utilizing one or more of hydrofluoric acid, ammonium fluoride, nitric acid and hydrogen peroxide.07-29-2010
20100190343LOAD LOCK HAVING SECONDARY ISOLATION CHAMBER - A load lock includes a chamber including an upper portion, a lower portion, and a partition between the upper portion and the lower portion, the partition including an opening therethrough. The load lock further includes a first port in communication with the upper portion of the chamber and a second port in communication with the lower portion of the chamber. The load lock includes a rack disposed within the chamber and a workpiece holder mounted on a first surface of the rack, wherein the rack and the workpiece holder are movable by an indexer that is capable of selectively moving wafer slots of the rack into communication with the second port. The indexer can also move the rack into an uppermost position, at which the first surface of the boat and the partition sealingly separate the upper portion and the lower portion to define an upper chamber and a lower chamber. Auxiliary processing, such as wafer pre-cleaning, or metrology can be conducted in the upper portion.07-29-2010
20110189858METHOD FOR REDUCING PATTERN COLLAPSE IN HIGH ASPECT RATIO NANOSTRUCTURES - A method is provided for treating the surface of high aspect ratio nanostructures to help protect the delicate nanostructures during some of the rigorous processing involved in fabrication of semiconductor devices. A wafer containing high aspect ratio nanostructures is treated to make the surfaces of the nanostructures more hydrophobic. The treatment may include the application of a primer that chemically alters the surfaces of the nanostructures preventing them from getting damaged during subsequent wet clean processes. The wafer may then be further processed, for example a wet cleaning process followed by a drying process. The increased hydrophobicity of the nanostructures helps to reduce or prevent collapse of the nanostructures.08-04-2011
20100029081SINGLE SPACER PROCESS FOR MULTIPLYING PITCH BY A FACTOR GREATER THAN TWO AND RELATED INTERMEDIATE IC STRUCTURES - Single spacer processes for multiplying pitch by a factor greater than two are provided. In one embodiment, n, where n≧2, tiers of stacked mandrels are formed over a substrate, each of the n tiers comprising a plurality of mandrels substantially parallel to one another. Mandrels at tier n are over and parallel to mandrels at tier n−1, and the distance between adjoining mandrels at tier n is greater than the distance between adjoining mandrels at tier n−1. Spacers are simultaneously formed on sidewalls of the mandrels. Exposed portions of the mandrels are etched away and a pattern of lines defined by the spacers is transferred to the substrate.02-04-2010
20100022088MULTIPLE EXPOSURE AND SINGLE ETCH INTEGRATION METHOD - A process including forming a silicon layer over a semiconductor wafer having features thereon and then selectively ion implanting in the silicon layer to form ion implanted regions. The step of selectively ion implanting is repeated as many times as necessary to obtain a predetermined number and density of features. Thereafter, the silicon layer is etched to form openings in the silicon layer that were formerly occupied by the ion implanted regions. The opened areas in the silicon layer form a mask for further processing of the semiconductor wafer.01-28-2010
20100081282PROCESS FOR ADJUSTING THE SIZE AND SHAPE OF NANOSTRUCTURES - In accordance with the invention, a lateral dimension of a microscale device on a substrate is reduced or adjusted by the steps of providing the device with a soft or softened exposed surface; placing a guiding plate adjacent the soft or softened exposed surface; and pressing the guiding plate onto the exposed surface. Under pressure, the soft material flows laterally between the guiding plate and the substrate. Such pressure induced flow can reduce the lateral dimension of line spacing or the size of holes and increase the size of mesas. The same process also can repair defects such as line edge roughness and sloped sidewalls. This process will be referred to herein as pressed self-perfection by liquefaction or P-SPEL.04-01-2010
20100311243Bottom electrode etching process in MRAM cell - A BE patterning scheme in a MRAM is disclosed that avoids damage to the MTJ array and underlying ILD layer while reducing BE-BE shorts and BE-bit line shorts. A protective dielectric layer is coated over a MTJ array before a photoresist layer is coated and patterned on the dielectric layer. The photoresist pattern is transferred through the dielectric layer with a dielectric etch process and then through the BE layer with a metal etch that includes a certain amount of overetch to remove metal residues. The photoresist is stripped with a sequence involving immersion or spraying with an organic solution followed by oxygen ashing to remove any other organic materials. Finally, a second wet strip is performed with a water based solution to provide a residue free substrate. In another embodiment, a bottom anti-reflective coating (BARC) is inserted between the photoresist and dielectric layer for improved critical dimension control.12-09-2010
20100093175Methods Of Forming Patterns Utilizing Lithography And Spacers - Some embodiments include methods of forming patterns. A first set of features is photolithographically formed over a substrate, and then a second set of features is photolithographically formed over the substrate. At least some of the features of said second set alternate with features of the first set. Spacer material is formed over and between the features of the first and second sets. The spacer material is anisotropically etched to form spacers along the features of the first and second sets. The features of the first and second sets are then removed to leave a pattern of the spacers over the substrate.04-15-2010
20120302065PULSE-PLASMA ETCHING METHOD AND PULSE-PLASMA ETCHING APPARATUS - The present invention relates to a pulse-plasma etching method and apparatus for preparing a depression structure with reduced bowing. The pulse-plasma etching apparatus comprises a container, an upper electrode plate, a lower electrode plate, a gas source, a first ultrahigh RF power supply, a bias RF power supply, and a pulsing module. When the pulsing module supplies an ultrahigh-frequency voltage between the upper electrode plate and the lower electrode plate, an ultrahigh-frequency voltage is switched to the off state, and a large amount of electrons pass through the plasma and reach the substrate to neutralize the positive ions during the duration of the off state (T11-29-2012
20100323523Methods Of Plasma Etching Platinum-Comprising Materials, Methods Of Processing Semiconductor Substrates In The Fabrication Of Integrated Circuitry, And Methods Of Forming A Plurality Of Memory Cells - A platinum-comprising material is plasma etched by being exposed to a plasma etching chemistry that includes CHCl12-23-2010
20090286400PLASMA PROCESS WITH PHOTORESIST MASK PRETREATMENT - A method for etching features in a dielectric layer through a photoresist (PR) mask is provided. The PR mask is patterned using laser light having a wavelength not more than 193 nm. The PR mask is pre-treated with a noble gas plasma, and then a plurality of cycles of a plasma process is provided. Each cycle includes a deposition phase that deposits a deposition layer over the PR mask, the deposition layer covering a top and sidewalls of mask features of the PR mask, and a shaping phase that shapes the deposition layer deposited over the PR mask.11-19-2009
20120040533Method of Manufacturing Semiconductor Devices - A method of manufacturing semiconductor devices comprises forming a plurality of patterns by patterning a thin film formed over an underlying layer and cleaning contaminants generated when the thin film is patterned using a plasma both having oxidative and reductive properties.02-16-2012
20100227477METHOD FOR FORMING THIN FILM, METHOD FOR PRODUCING ORGANIC ELECTROLUMINESCENT DEVICE, METHOD FOR PRODUCING SEMICONDUCTOR DEVICE, AND METHOD FOR PRODUCING OPTICAL DEVICE - The present invention has the object of providing a method by which a thin film pattern can be formed using a liquid material application in a prescribed area in an economical and simple manner, and a method for producing organic electroluminescent devices, semiconductor devices, and optical devices using said method.09-09-2010
20120045899PATTERN REVERSAL FILM FORMING COMPOSITION AND METHOD OF FORMING REVERSED PATTERN - There is provided to a pattern reversal film forming composition that is capable of forming a pattern reversal film which is not mixed with a resist pattern formed on a substrate, and that is only capable of forming a pattern reversal film advantageously covering the pattern, but also irrespective of whether the resist pattern is coarse or fine, capable of forming a planar film excellent in temporal stability on the pattern. A pattern reversal film forming composition including a polysiloxane, an additive and an organic solvent, characterized in that the polysiloxane is a product of a hydrolysis and/or condensation reaction of a silane compound containing a tetraalkoxysilane of Si(OR02-23-2012
20120009791PATTERN FORMATION METHOD - According to one embodiment, a pattern formation method is disclosed. The method can include filling an imprint material between a first protrusion-depression pattern of a first pattern transfer layer formed on a first replica substrate and a second pattern transfer layer being transparent to energy radiation and formed on a second replica substrate transparent to the energy radiation. The method can include curing the imprint material by irradiating the imprint material with the energy radiation from an opposite surface side of the second replica substrate. The method can include releasing the first protrusion-depression pattern from the imprint material. The method can include forming a second protrusion-depression pattern in the second pattern transfer layer by processing the second pattern transfer layer using the imprint material as a mask.01-12-2012
20120009792SEMICONDUCTOR WET ETCHANT AND METHOD OF FORMING INTERCONNECTION STRUCTURE USING THE SAME - A semiconductor wet etchant includes deionized water, a fluorine-based compound, an oxidizer and an inorganic salt. A concentration of the fluorine-based compound is 0.25 to 10.0 wt % based on a total weight of the etchant, a concentration of the oxidizer is 0.45 to 3.6 wt % based on a total weight of the etchant, and a concentration of the inorganic salt is 1.0 to 5.0 wt % based on a total weight of the etchant. The inorganic salt comprises at least one of an ammonium ion (NH01-12-2012
20120015520Methods of Modifying Oxide Spacers - Methods for reducing line roughness of spacers and other features utilizing a non-plasma and non-wet etch fluoride processing technology are provided. Embodiments of the methods can be used for spacer or line reduction and/or smoothing the surfaces along the edges of such features through the reaction and subsequent removal of material.01-19-2012
20110165778ELECTRON BEAM DEPICTING PATTERN DESIGN, PHOTOMASK, METHODS OF DEPICTING AND FABRICATING PHOTOMASK, AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE USING THE SAME - A method of depicting a photomask using e-beams includes preparing a photomask having an e-beam resist, depicting the e-beam resist and forming an e-beam resist pattern on the photomask. Depicting the e-beam resist includes irradiating e-beams to an e-beam depiction region without irradiating the e-beams to an e-beam non-depiction region disposed in the e-beam depiction region. The e-beam depiction region and the e-beam non-depiction region are formed using an e-beam resist pattern having the same polarity.07-07-2011
20090111269SILICON WAFER RECLAMATION PROCESS - By exposing a process control wafer having a porous low-k-dielectric layer thereon in an HF-based low-k dielectric etching solvent comprising a dilating additive and a passivating additive, the pores in the low-k dielectric layer are dilated some of which connect with one another to form one or more continuous channels extending through the thickness of the dielectric layer and allowing the HF-based solvent to reach down to the substrate. Then the passivating additive component of the HF-based etching solvent forms a passivation layer at the dielectric layer and the substrate interface that protects substrate from the HF-based etchant.04-30-2009
20120028469METHOD OF TAILORING CONFORMALITY OF Si-CONTAINING FILM - A method of tailoring conformality of a film deposited on a patterned surface includes: (I) depositing a film by PEALD or pulsed PECVD on the patterned surface; (II) etching the film, wherein the etching is conducted in a pulse or pulses, wherein a ratio of an etching rate of the film on a top surface and that of the film on side walls of the patterns is controlled as a function of the etching pulse duration and the number of etching pulses to increase a conformality of the film; and (III) repeating (I) and (II) to satisfy a target film thickness.02-02-2012
20120156879RESIST PATTERN IMPROVING MATERIAL, METHOD FOR FORMING RESIST PATTERN, AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE - To provide a resist pattern improving material, containing: a compound represented by the following general formula (1), or a compound represented by the following general formula (2), or both thereof; and water:06-21-2012
20120070992METHOD OF STRIPPING HOT MELT ETCH RESISTS FROM SEMICONDUCTORS - Hot melt etch resist is selectively applied to an anti-reflective coating or a selective emitter on a semiconductor wafer. The exposed portions of the anti-reflective coating or selective emitter are etched away using an inorganic acid containing etch to expose the semiconductor surface. The hot melt etch resist is then stripped from the semiconductor with an alkaline stripper which does not compromise the electrical integrity of the semiconductor. The exposed semiconductor is then metalized to form current tracks.03-22-2012
20120108068Method for Patterning Sublithographic Features - A method of uniformly shrinking hole and space geometries by forming sidewalls of an ALD film deposited at low temperature on a photolithographic pattern.05-03-2012
20110092071METHOD OF PRODUCING SILYLATED POROUS INSULATING FILM, METHOD OF PRODUCING SEMICONDUCTOR DEVICE, AND SILYLATED MATERIAL - Provided is a method for the effective silylation treatment of a silica-based porous insulating film having a plurality of pores. The method of producing a silylated porous insulating film (04-21-2011
20120156880RAPID AND UNIFORM GAS SWITCHING FOR A PLASMA ETCH PROCESS - An inductively coupled plasma processing apparatus includes a processing chamber in which a semiconductor substrate is processed, a substrate support, a dielectric window forming a wall of the chamber, an antenna operable to generate and maintain a plasma in the processing chamber, and a showerhead plate of dielectric material adjacent the dielectric window. The showerhead plate includes gas holes in fluid communication with a plenum below the dielectric window, the plenum having a gas volume of no greater than 500 cm06-21-2012
20110065276Apparatus and Methods for Cyclical Oxidation and Etching - Apparatus and methods for the manufacture of semiconductor devices suitable for narrow pitch applications and methods of fabrication thereof are described herein. Disclosed are various single chambers configured to form and/or shape a material layer by oxidizing a surface of a material layer to form an oxide layer; removing at least some of the oxide layer by an etching process; and cyclically repeating the oxidizing and removing processes until the material layer is formed to a desired shape. In some embodiments, the material layer may be a floating gate of a semiconductor device.03-17-2011
20110065277REFLOW METHOD, PATTERN GENERATING METHOD, AND FABRICATION METHOD FOR TFT FOR LCD - A to-be-processed object including an underlying layer and a resist film giving a pattern allowing formation of an exposure region in which the underlying layer is exposed at an upper layer to the underlying layer and a coverage region in which the underlying layer is covered is prepared. A reflow method is provided which softens the resist film to be in a flowing state, resulting in a part of or all of the exposure region covered by it. The resist film has different regions in thickness of at least a thick region and a thin region relatively thinner than the thick region.03-17-2011
20110104900Alkaline Rinse Agents For Use In Lithographic Patterning - Lithographic patterning methods involve the formation of a (one or more) metal oxide capping layer, which is rinsed with an aqueous alkaline solution as part of the method. The rinse solution does not damage the capping layer, but rather allows for lithographic processing without thinning the capping layer or introducing defects into it. Ammoniated water is a preferred rinse solution, which advantageously leaves behind no nonvolatile residue.05-05-2011
20090130851METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device, comprises forming a first film above a pattern forming material, patterning the first film to form a core material pattern, forming a second film above the pattern forming material so as to cover a side surface and an upper surface of the core material pattern, forming a third film above the second film as a protective material for the second film, etching the second and third films so that side wall sections including the second film and the third film are formed on both sides of the core material pattern and the second film and the third film of an area other than the side wall sections are removed, removing the core material pattern between the side wall sections, and transferring patterns corresponding to the side wall sections on the pattern forming material by using the side wall sections as a mask.05-21-2009
20110183521METHODS AND SYSTEMS OF MATERIAL REMOVAL AND PATTERN TRANSFER - Polymerized material on a substrate may be removed by exposure to vacuum ultraviolet (VUV) radiation from an energy source within a gaseous atmosphere of a controlled composition. Following such removal, additional etching techniques are also described for nano-imprinting.07-28-2011
20120164835Method of Forming Via Hole - The present invention provides a method of forming via holes. First, a substrate is provided. A plurality of first areas is defined on the substrate. A dielectric layer and a blocking layer are formed on the substrate. A patterned photoresist layer is formed on the blocking layer. The patterned photoresist layer includes a plurality of holes arranged in a regular array wherein the area of the hole array is greater than those of the first areas. The blocking layer in the first areas is removed by using the patterned photoresist layer as a mask. Lastly, the dielectric layer is patterned to form at least a via hole in the dielectric layer in the first area.06-28-2012
20120129347Apparatus and Method For Incorporating Composition Into Substrate Using Neutral Beams - An apparatus and method for processing a surface of a substrate using neutral beams are provided to repeatedly process an oxide layer using the neutral beams having low energy to minimize electrical damage to the oxide layer and improve characteristics of the oxide layer. The apparatus is mounted in a plasma generating chamber, and includes: an ion beam generating gas inlet, which injects a gas for generating ion beams; an ion source, which generates the ion beams having a polarity from the gas introduced through the ion beam generating gas inlet; a grid assembly, which is installed on one end of the ion source; a reflector, which is aligned with the grid assembly and converts the ion beams to the neutral beams; and a stage, on which the substrate is placed on a traveling path of the neutral beams.05-24-2012
20120220129METHOD FOR FORMING MASK FOR FORMING CONTACT HOLES OF SEMICONDUCTOR DEVICE - A method for forming a mask for forming contact holes of a semiconductor device includes coating an etch target layer with a first photoresist layer, patterning the first photoresist layer in a type of lines and spaces to form a first photoresist pattern, wherein the first photoresist pattern comprises pads formed at both ends of the first photoresist pattern, and lines repeatedly formed between the pads at the both ends, forming a protective layer on a surface of the first photoresist pattern by performing a freezing process onto the first photoresist pattern, and forming a second photoresist pattern having a type of lines stretched in a second direction which is perpendicular to the first direction on the etch target layer including the protective layer.08-30-2012
20100210110ETCHING APPARATUS, A METHOD OF CONTROLLING AN ETCHING SOLUTION, AND A METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - An etching apparatus includes a chamber containing an etching solution including first and second components and water, a concentration of the water in the etching solution is at a specified level or lower; a circulation path circulating the etching solution; a concentration controller sampling the etching liquid from the circulation path and controls concentrations of the etching solution respectively; and a refilling chemical liquid feeder feeding a refilling chemical liquid including the first component having a concentration higher than the first component in the etching solution.08-19-2010
20120214308METHOD OF FABRICATING SEMICONDUCTOR DEVICE - An aspect of the present embodiment, there is provided a method of fabricating a semiconductor device including providing a film to be processed above a semiconductor substrate, providing a negative-type resist and a photo-curable resist in order, pressing a main surface of a template onto the photo-curable resist, the main surface of the template having a concavo-convex pattern with a light shield portion provided on at least a part of a convex portion, irradiating the template with light from a back surface of the template, developing the negative-type resist and the photo-curable resist so as to print the concavo-convex pattern of the template on the negative-type resist and the photo-curable resist, and etching the film to be processed by using the concavo-convex pattern printed on the negative-type resist and the photo-curable resist as a mask.08-23-2012
20120135603METHODS FOR INCREASED ARRAY FEATURE DENSITY - The embodiments generally relate to methods of making semiconductor devices, and more particularly, to methods for making semiconductor pillar structures and increasing array feature pattern density using selective or directional gap fill. The technique has application to a variety of materials and can be applied to making monolithic two or three-dimensional memory arrays.05-31-2012
20100190340Methods of forming fine patterns using a nanoimprint lithography - In a method of forming fine patterns, a photocurable coating layer is formed on a substrate. A first surface of a template makes contact with the photocurable coating layer. The first surface of the template includes at least two first patterns having a first dispersion degree of sizes, and at least one portion of the first surface of the template includes a photo attenuation member. A light is irradiated onto the photocurable coating layer through the template to form a cured coating layer including second patterns having a second dispersion degree of sizes. The second patterns are generated from the first patterns and the second dispersion degree is less than the first dispersion degree. The template is separate from the cured coating layer. A size dispersion degree of the patterns used in a nanoimprint lithography process may be adjusted by the light attenuation member, so that the fine patterns may be formed to have an improved size dispersion degree.07-29-2010
20120171865METHOD FOR FABRICATING FINE PATTERNS - A method for fabricating fine patterns includes forming a first photomask including first line patterns and first assist features and forming a second photomask including second line patterns extending to a portion corresponding to the first assist features in a direction perpendicular to the first line patterns. A first resist layer may be exposed through a first exposure process by using the first photomask, and a first resist pattern formed to open regions following the shape of the first line patterns. The first resist pattern may be frozen and a second resist layer may be formed to fill the opened regions of the first resist pattern. The second resist layer may be exposed through a second exposure process by using the second photomask, and a second resist pattern formed to open regions corresponding to the intersections between the first and second line patterns with the first resist pattern.07-05-2012
20120171866SUBSTRATE STRUCTURE INCLUDING FUNCTIONAL REGION AND METHOD FOR TRANSFERRING FUNCTIONAL REGION - According to a method for transferring a functional region, at least part of functional regions on separation layers arranged on a first substrate is transferred onto a second substrate, the separation layers being capable of being brought into a separable state by treatment. In a first bonding step, the first substrate is bonded to the second substrate with a dry film resist arranged between the second substrate and the at least part of the functional regions above the first substrate. In an exposure step, at least part of the dry film resist is exposed. In a patterning step, the exposed dry film resist is patterned.07-05-2012
20120077343RESIST COMPOSITION AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE - A resist composition includes: a crosslinking material that is crosslinked in the presence of an acid; an acid amplifier; and a solvent.03-29-2012
20120252215METHOD FOR FABRICATING SEMICONDUCTOR DEVICE, PATTERN WRITING APPARATUS, RECORDING MEDIUM RECORDING PROGRAM, AND PATTERN TRANSFER APPARATUS - A method for fabricating a semiconductor device, includes dividing a pattern region of a desired pattern that is to be formed on a semiconductor substrate into a plurality of sub-regions; calculating combination condition including a shape of illumination light for transferring and a mask pattern obtained by correcting a partial pattern in the sub-region of the desired pattern formed on a mask used during transferring for each of the plurality of sub-regions, to make a dimension error of the partial pattern of each of the plurality of sub-regions smaller when transferred to the semiconductor substrate; and forming the desired pattern by making multiple exposures on the semiconductor substrate in such a way that the partial patterns of the sub-regions divided are sequentially transferred by transferring a pattern to the semiconductor substrate using the combination conditions calculated for each of the sub-regions.10-04-2012
20100041234Process For Restoring Dielectric Properties - A method for preparing an interlayer dielectric to minimize damage to the interlayer's dielectric properties, the method comprising the steps of: depositing a layer of a silicon-containing dielectric material onto a substrate, wherein the layer has a first dielectric constant and wherein the layer has at least one surface; providing an etched pattern in the layer by a method that includes at least one etch process and exposure to a wet chemical composition to provide an etched layer, wherein the etched layer has a second dielectric constant, and wherein the wet chemical composition contributes from 0 to 40% of the second dielectric constant; contacting the at least one surface of the layer with a silicon-containing fluid; optionally removing a first portion of the silicon-containing fluid such that a second portion of the silicon-containing fluid remains in contact with the at least one surface of the layer; and exposing the at least one surface of the layer to UV radiation and thermal energy, wherein the layer has a third dielectric constant that is restored to a value that is at least 90% restored relative to the second dielectric constant.02-18-2010
20120315765RESIST UNDERLAYER FILM FORMING COMPOSITION CONTAINING SILICON HAVING NITROGEN-CONTAINING RING - There is provided a resist underlayer film forming composition for lithography for forming a resist underlayer film capable of being used as a hardmask. A resist underlayer film forming composition for lithography, includes as a silane compound, a hydrolyzable organosilane, a hydrolysis product thereof, or a hydrolysis-condensation product thereof, wherein the hydrolyzable organosilane is a hydrolyzable organosilane of Formula (1):12-13-2012
20120178259METHOD OF CLEANING SILICON CARBIDE SEMICONDUCTOR AND APPARATUS FOR CLEANING SILICON CARBIDE SEMICONDUCTOR - A method of cleaning an SiC semiconductor includes the steps of forming an oxide film on a surface of an SiC semiconductor and removing the oxide film. In the step of removing the oxide film, the oxide film is removed with halogen plasma or hydrogen plasma. In the step of removing the oxide film, fluorine plasma is preferably employed as halogen plasma. The SiC semiconductor can be cleaned such that good surface characteristics are achieved.07-12-2012
20100273331METHOD OF FABRICATING A NANO/MICRO STRUCTURE - A method of fabricating a nano/micro structure comprising the following steps is provided. First, a film is provided and then a mixed material comprising a plurality of ball-shape particles and a filler among the ball-shape particles is formed on the film. Next, the ball-shape particles are removed by the etching process, the solvent extraction process or the like, such that a plurality of concaves is formed on the surface of the filler, which serves as a nano/micro structure of the film.10-28-2010
20090061633METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - According to an aspect of an embodiment, a method of manufacturing a semiconductor device has forming an insulating layer comprising silica-based insulating material, processing the insulating layer, hydrophobizing the insulating layer by applying a silane compound to act on the insulating layer; and irradiating the insulating layer with light or an electron beam.03-05-2009
20090061631GATE REPLACEMENT WITH TOP OXIDE REGROWTH FOR THE TOP OXIDE IMPROVEMENT - Methods of replacing/reforming a top oxide around a charge storage element of a memory cell and methods of improving quality of a top oxide around a charge storage element of a memory cell are provided. The method can involve removing a first poly over a first top oxide from the memory cell; removing the first top oxide from the memory cell; and forming a second top oxide around the charge storage element. The second top oxide can be formed by oxidizing a portion of the charge storage element or by forming a sacrificial layer over the charge storage element and oxidizing the sacrificial layer to a second top oxide.03-05-2009
20090061632METHODS FOR CLEANING ETCH RESIDUE DEPOSITED BY WET ETCH PROCESSES FOR HIGH-K DIELECTRICS03-05-2009
20100291770METHOD OF FORMING OPENINGS IN A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE FABRICATED BY THE METHOD - A method of forming openings to a layer of a semiconductor device comprises forming a dielectric layer over the layer of the semiconductor device, and forming a mask over the dielectric layer. The mask comprises a plurality of mask openings arranged in a regular pattern extending over the dielectric layer and the plurality of mask openings include a plurality of first mask openings and a plurality of second mask openings, each of the plurality of first mask openings being greater in size than each of the plurality of second mask openings. The method further comprises reducing the size of the plurality of second mask openings such that each of the second mask openings is substantially closed and removing portions of the dielectric layer through the plurality of first mask openings to provide openings extending through the dielectric layer to the layer.11-18-2010
20120225558METHODS FOR CONTACT CLEAN - Methods and apparatus for removing oxide from a surface, the surface comprising at least one of silicon and germanium, are provided. The method and apparatus are particularly suitable for removing native oxide from a metal silicide layer of a contact structure. The method and apparatus advantageously integrate both the etch stop layer etching process and the native oxide removal process in a single chamber, thereby eliminating native oxide growth or other contaminates redeposit during the substrate transfer processes. Furthermore, the method and the apparatus also provides the improved three-step chemical reaction process to efficiently remove native oxide from the metal silicide layer without adversely altering the geometry of the contact structure and the critical dimension of the trenches or vias formed in the contact structure.09-06-2012
20120225557SILICON GERMANIUM MASK FOR DEEP SILICON ETCHING - Polycrystalline silicon germanium (SiGe) can offer excellent etch selectivity to silicon during cryogenic deep reactive ion etching in an SF09-06-2012
20090017626SEMICONDUCTOR WET ETCHANT AND METHOD OF FORMING INTERCONNECTION STRUCTURE USING THE SAME - A semiconductor wet etchant includes deionized water, a fluorine-based compound, an oxidizer and an inorganic salt. A concentration of the fluorine-based compound is 0.25 to 10.0 wt % based on a total weight of the etchant, a concentration of the oxidizer is 0.45 to 3.6 wt % based on a total weight of the etchant, and a concentration of the inorganic salt is 1.0 to 5.0 wt % based on a total weight of the etchant. The inorganic salt comprises at least one of an ammonium ion (NH01-15-2009
20120231629TEMPLATE AND PATTERN FORMING METHOD - A template for imprinting in which a pattern is transferred onto a first substrate applied curable resin thereon, including a second substrate having a surface to be contacted with the curable resin, a concave portion provided on the surface and corresponding to a pattern to be transferred onto the first substrate, and at least one convex portion arranged in the concave portion to decrease volume of09-13-2012
20120231628REDUCTION OF A PROCESS VOLUME OF A PROCESSING CHAMBER USING A NESTED DYNAMIC INERT VOLUME - A substrate processing chamber includes a lift actuator that moves a pedestal between a substrate loading position and a substrate processing position. An adjustable seal defines an expandable sealed volume between a bottom surface of the pedestal and a bottom surface of the substrate processing chamber and is moveable between the substrate loading position and the substrate processing position. When the pedestal is in the substrate processing position, the pedestal and the adjustable seal define a first inert volume and a first process volume. When the pedestal is in the substrate loading position, the pedestal and the adjustable seal define a second inert volume and a second process volume. The second inert volume is less than the first inert volume and the second process volume is greater than the first process volume.09-13-2012
20130171825PHOTORESIST PATTERN TRIMMING METHODS - Provided are methods of trimming photoresist patterns. The methods involve coating a photoresist trimming composition over a photoresist pattern, wherein the trimming composition includes a matrix polymer, a thermal acid generator and a solvent, the trimming composition being free of cross-linking agents. The coated semiconductor substrate is heated to generate an acid in the trimming composition from the thermal acid generator, thereby causing a change in polarity of the matrix polymer in a surface region of the photoresist pattern. The photoresist pattern is contacted with a developing solution to remove the surface region of the photoresist pattern. The methods find particular applicability in the formation of very fine lithographic features in the manufacture of semiconductor devices.07-04-2013
20080299773SEMICONDUCTOR DEVICE MANUFACTURING METHOD - In a semiconductor device manufacturing method, on a film to be processed, a mask material film is formed which has pattern openings for a plurality of contact patterns and connection openings for connecting adjacent pattern openings in such a manner that the connection between them is constricted in the middle. Then, a sidewall film is formed on the sidewalls of the individual openings in the mask material film, thereby not only making the diameter of the pattern openings smaller but also separating adjacent pattern openings. Then, the film to be processed is selectively etched with the mask material film and sidewall film as a mask, thereby making contact holes.12-04-2008
20120264305Footing Reduction Using Etch-Selective Layer - A method of forming side spacers upwardly extending from a substrate, includes: providing a template constituted by a photoresist formed on and in contact with an etch-selective layer laminated on a substrate; anisotropically etching the template in a thickness direction with an oxygen-containing plasma to remove a footing of the photoresist and an exposed portion of the underlying layer; depositing a spacer film on the template by atomic layer deposition (ALD); and forming side spacers using the spacer film by etching. The etch-selective layer has a substantially lower etch rate than that of the photoresist.10-18-2012
20120322266Methods of Forming Semiconductor Constructions - The invention includes methods in which silicon is removed from titanium-containing container structures with an etching composition having a phosphorus-and-oxygen-containing compound therein. The etching composition can, for example, include one or both of ammonium hydroxide and tetra-methyl ammonium hydroxide. The invention also includes methods in which titanium-containing whiskers are removed from between titanium-containing capacitor electrodes. Such removal can be, for example, accomplished with an etch utilizing one or more of hydrofluoric acid, ammonium fluoride, nitric acid and hydrogen peroxide.12-20-2012
20110237080Method for integrating low-k dielectrics - A method for treating a dielectric film on a substrate and, in particular, a method for integrating a low-k dielectric film with subsequently formed metal interconnects is described. The method includes preparing a dielectric film on a substrate, wherein the dielectric film is a low-k dielectric film having a dielectric constant less than or equal to a value of about 4. Thereafter, the method further includes performing a preliminary curing process on the dielectric film, forming a pattern in the dielectric film using a lithographic process and an etching process, removing undesired residues from the substrate, and performing a final curing process on the dielectric film, wherein the final curing process includes irradiating the substrate with ultraviolet (UV) radiation.09-29-2011
20120094493METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND APPARATUS FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device in which an insulating film is filled between patterns etched into a workpiece structure is disclosed. The method includes cleaning etch residues residing between the etched patterns by a first chemical liquid; rinsing the workpiece structure cleaned by the first chemical liquid by a rinse liquid; and coating the workpiece structure rinsed by the rinse liquid with a coating liquid for formation of the insulating film. The cleaning to the coating are carried out within the same processing chamber such that a liquid constantly exists between the patterns of the workpiece structure.04-19-2012
20120094492METHOD OF FORMING PATTERN, RETICLE, AND COMPUTER READABLE MEDIUM FOR STORING PROGRAM FOR FORMING PATTERN - A method of forming a pattern includes forming a plurality of target patterns, forming a plurality of pitch violating patterns that make contact with the plurality of target patterns and are disposed between the plurality of target patterns, classifying the plurality of pitch violating patterns into a first region and a second region adjacent to the first region, and forming an initial pattern corresponding to one of the first region and the second region.04-19-2012
20120276743METHODS OF FORMING A CARBON TYPE HARD MASK LAYER USING INDUCED COUPLED PLASMA AND METHODS OF FORMING PATTERNS USING THE SAME - A method of forming a carbon type hard mask layer using induced coupled plasma includes loading a substrate onto a lower electrode in a process chamber of an induced coupled plasma (ICP) deposition apparatus, the process chamber including an upper electrode and the lower electrode therein, generating a plasma in the process chamber, injecting a reactive gas into the process chamber such that the reactive gas is activated by colliding with the plasma, the reactive gas including a hydrocarbon compound gas, and applying a bias power to the lower electrode to form a diamond-like carbon layer on the substrate from the activated reactive gas.11-01-2012
20110244687SEMICONDUCTOR DEVICE MANUFACTURING METHOD - In a process for forming trenches having M different widths in a substrate, a passivation step and an etching step are alternately performed. The passivation step includes depositing a passivation layer on a bottom of the trenches by converting gas introduced in a chamber into plasma. The etching step includes removing the passivation layer on the bottom of the trenches and applying reactive ion etching to the bottom to increase a depth of the trenches. The etching step further includes setting energy for the reactive ion etching to a predetermined value when the passivation layer on the bottom of the trench having the Nth smallest width is removed. The value allows the etching amount of the trench having the Nth smallest width to be equal to or greater than the etching amount of the trench having the (N+1)th smallest width.10-06-2011
20120088367SEMICONDUCTOR DEVICE AND STRUCTURE - A method of manufacturing a semiconductor wafer, the method comprising: providing a base wafer comprising a semiconductor substrate; preparing a first monocrystalline layer comprising semiconductor regions; preparing a second monocrystalline layer comprising semiconductor regions overlying the first monocrystalline layer; and etching portions of said first monocrystalline layer and portions of said second monocrystalline layer as part of forming at least one transistor on said first monocrystalline layer.04-12-2012
20120329280METHOD FOR FORMING PHOTORESIST PATTERNS - A method for forming photoresist patterns includes providing a substrate, forming a bi-layered photoresist on the substrate, and performing a photolithography process to pattern the bi-layered photoresist. The bi-layered photoresist includes a first photoresist layer and a second photoresist layer positioned between the first photoresist layer and the substrate. The first photoresist layer has a first refraction index and the second photoresist layer has a second refraction index, and the second refraction index is larger than the first refraction index.12-27-2012
20100203733ETCHING METHOD, SEMICONDUCTOR AND FABRICATING METHOD FOR THE SAME - An organic/inorganic hybrid film represented by SiC08-12-2010
20100203732FIN AND FINFET FORMATION BY ANGLED ION IMPLANTATION - A semiconductor device is formed by providing a substrate and forming a semiconductor-containing layer atop the substrate. A mask having a plurality of openings is then formed atop the semiconductor-containing layer, wherein adjacent openings of the plurality of openings of the mask are separated by a minimum feature dimension. Thereafter, an angled ion implantation is performed to introduce dopants to a first portion of the semiconductor-containing layer, wherein a remaining portion that is substantially free of dopants is present beneath the mask. The first portion of the semiconductor-containing layer containing the dopants is removed selective to the remaining portion of semiconductor-containing layer that is substantially free of the dopants to provide a pattern of sublithographic dimension, and the pattern is transferred into the substrate to provide a fin structure of sublithographic dimension.08-12-2010
20100203731Formation of a Zinc Passivation Layer on Titanium or Titanium Alloys Used in Semiconductor Processing - Embodiments of the current invention describe methods of processing a semiconductor substrate that include applying a zincating solution to the semiconductor substrate to form a zinc passivation layer on the titanium-containing layer, the zincating solution comprising a zinc salt, FeCl08-12-2010
20100203730Epitaxial Lift Off in Inverted Metamorphic Multijunction Solar Cells - A process for selectively freeing an epitaxial layer from a single crystal substrate upon which it was grown, by providing a first substrate; depositing a separation layer on said first substrate; depositing on said separation layer a sequence of layers of semiconductor material forming a solar cell; mounting and bonding a surrogate substrate on top of the sequence of layers; attaching a connecting link element to at least two opposed points on the periphery of the surrogate substrate; and etching said separation layer while applying tension to said link element so as to remove said epitaxial layer from said first substrate.08-12-2010
20120289049COPPER OXIDE REMOVAL TECHNIQUES - A method for the removal of copper oxide from a copper and dielectric containing structure of a semiconductor chip is provided. The copper and dielectric containing structure may be planarized by chemical mechanical planarization (CMP) and treated by the method to remove copper oxide and CMP residues. Annealing in a hydrogen (H11-15-2012
20120135604PROCESSING LIQUID FOR SUPPRESSING PATTERN COLLAPSE OF FINE METAL STRUCTURE, AND METHOD FOR PRODUCING FINE METAL STRUCTURE USING SAME - There are provided a processing liquid that is capable of suppressing pattern collapse of a fine metal structure, such as a semiconductor device and a micromachine, and a method for producing a fine metal structure using the same. The processing liquid for suppressing pattern collapse of a fine metal structure, contains a phosphate ester and/or a polyoxyalkylene ether phosphate ester, and the method for producing a fine metal structure, uses the same.05-31-2012
20100130014TEXTURING MULTICRYSTALLINE SILICON - Techniques are disclosed for surface texturing multicrystalline silicon using drop jetting technology to form mask or etch patterns on a surface of a multicrystalline silicon substrate.05-27-2010
20130017682Overburden Removal For Pore Fill Integration ApproachAANM Bruce; Robert L.AACI White PlainsAAST NYAACO USAAGP Bruce; Robert L. White Plains NY USAANM Dubois; Geraud Jean-MichelAACI San JoseAAST CAAACO USAAGP Dubois; Geraud Jean-Michel San Jose CA USAANM Frot; Theo J.AACI Los GatosAAST CAAACO USAAGP Frot; Theo J. Los Gatos CA USAANM Volksen; WilliAACI San JoseAAST CAAACO USAAGP Volksen; Willi San Jose CA US - In one exemplary embodiment of the invention, a method includes: providing a structure having a first layer overlying a substrate, where the first layer includes a dielectric material having a plurality of pores; applying a filling material to a surface of the first layer; after applying the filling material, heating the structure to enable the filling material to at least partially fill the plurality of pores, where heating the structure results in residual filling material being left on the surface of the first layer; and after heating the structure, removing the residual filling material by applying a solvent wash.01-17-2013
20130017683METHOD OF MANUFACTURING SILICON CARBIDE SUBSTRATE AND METHOD OF MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE - A silicon carbide substrate is prepared. By exposing the silicon carbide substrate to an atmosphere having a nitrogen dioxide concentration greater than or equal to 2 μg/m01-17-2013
20130023121DOUBLE PATTERNING METHOD USING TILT-ANGLE DEPOSITION - Methods for patterning material layers, which may be implemented in forming integrated circuit device features, are disclosed. In an example, a method includes forming a first resist layer over a material layer; forming a second resist layer over the first resist layer; forming an opening that extends through the second resist layer and the first resist layer to expose the material layer, wherein the opening has a substantially constant width in the second resist layer and a tapered width in the first resist layer; and performing a tilt-angle deposition process to form a feature over the exposed material layer.01-24-2013
20080248650Etching apparatus and method for semiconductor device - Disclosed is an etching method for a semiconductor device. The protecting layer, such as the hydrocarbon layer or the hydrocarbon layer containing phosphorous, is formed on the photoresist layer by using the precursor gas containing no fluorine. Therefore, the etching process enabling the thin photoresist to have a high selectivity can be performed, thereby improving the etching efficiency. The method includes the steps of placing a semiconductor substrate in a chamber, in which a material layer is formed on the semiconductor substrate and a photoresist layer is formed on the material layer, forming a hydrocarbon layer on the photoresist layer by introducing precursor gas containing no fluorine into the chamber and etching an etching target material by introducing etching gas into the chamber.10-09-2008
20080227299TAPERED EDGE EXPOSURE FOR REMOVAL OF MATERIAL FROM A SEMICONDUCTOR WAFER - A semiconductor wafer edge exposure process as described herein employs a photoresist exposure step that exposes photoresist material to radiation having a gradient intensity profile near the outer edge of the wafer. The gradient intensity profile creates a tapered outer edge in the developed photoresist material, which in turn creates a tapered outer edge in the underlying target material after etching. Different gradient intensity profiles can also be used for subsequent layers of material. The resulting tapered edge profile of the wafer is resistant to edge peeling and flaking.09-18-2008
20130171826SEMICONDUCTOR DEVICE PRODUCTION METHOD AND RINSE - The present invention provides a semiconductor device production method and a rinse used in the production method. The method includes: a sealing composition application process in which a semiconductor sealing layer is formed by applying, to at least a portion of a surface of a semiconductor substrate, a semiconductor sealing composition that includes a resin having a cationic functional group and a weight average molecular weight of from 2,000 to 600,000, wherein a content of sodium and a content of potassium are 10 mass ppb or less on an elemental basis, respectively; and, subsequently, a rinsing process in which the surface of the semiconductor substrate on which the semiconductor sealing layer has been formed is rinsed with a rinse having a pH at 25° C. of 6 or lower.07-04-2013
20130171827METHOD AND APPARATUS FOR MANUFACTURING THREE-DIMENSIONAL-STRUCTURE MEMORY DEVICE - A method for manufacturing a memory device having a vertical structure according to one embodiment of the present invention comprises: a step for alternatingly laminating one or more insulation layers and one or more sacrificial layers on a substrate; a step for forming a penetration hole for penetrating the insulation layer and the sacrificial layer; a step for forming a pattern for filling up the penetration hole; a step for forming an opening for penetrating the insulation layer and the sacrificial layer; and a step for removing the sacrificial layer by supplying an etchant through the opening, wherein the step for laminating the insulation layer includes a step for depositing a first silicon oxide film by supplying to the substrate at least one gas selected from the group consisting of SiH07-04-2013
20080220611Method of forming fine patterns of semiconductor devices using double patterning - A method of forming fine patterns of semiconductor device according to an example embodiment may include forming a plurality of multi-layered mask patterns by stacking first mask patterns and buffer mask patterns on an etch film to be etched on a substrate, forming, on the etch film, second mask patterns in spaces between the plurality of multi-layered mask patterns, removing the second mask patterns to expose upper surfaces of the first mask patterns, and forming the fine patterns by etching the etch film using the first and second mask patterns as an etch mask. This example embodiment may result in the formation of diverse dimensions at diverse pitches on a single substrate.09-11-2008
20130143406TECHNIQUES PROVIDING PHOTORESIST REMOVAL - A method for manufacturing a semiconductor device includes forming a patterned photoresist layer over a substrate, performing a plasma ashing process to the patterned photoresist layer, thereby removing a portion of the patterned photoresist layer, exposing the patterned photoresist layer to broadband ultraviolet radiation and ozone, thereby removing other portions of the patterned photoresist layer, and performing a cleaning of the patterned photoresist layer after exposing the patterned photoresist layer to broadband ultraviolet radiation and ozone.06-06-2013
20130143407METHOD FOR PRODUCING A THIN SINGLE CRYSTAL SILICON HAVING LARGE SURFACE AREA - The present invention relates to a method for producing a thin single crystal silicon having large surface area, and particularly relates to a method for producing a silicon micro and nanostructure on a silicon substrate (or wafer) and lifting off the silicon micro and nanostructure from the silicon substrate (or wafer) by metal-assisted etching. In this method, a thin single crystal silicon is produced in the simple processes of lifting off and transferring the silicon micro and nanostructure from the substrate by steps of depositing metal catalyst on the silicon wafer, vertically etching the substrate, laterally etching the substrate. And then, the surface of the substrate is processed, for example planarizing the surface of the substrate, to recycle the substrate for repeatedly producing thin single crystal silicons. Therefore, the substrate can be fully utilized, the purpose of decreasing the cost can be achieved and the application can be increased.06-06-2013
20130143408ETCH RESISTANT ALUMINA BASED COATINGS - Method of forming a protective hard mask layer on a substrate in a semiconductor etch process, comprising the step of applying by solution deposition on the substrate a solution or colloidal dispersion of an alumina polymer, said solution or dispersion being obtained by hydrolysis and condensation of monomers of at least one aluminium oxide precursor in a solvent or a solvent mixture in the presence of water and a catalyst. The invention can be used for making a hard mask in a TSV process to form a high aspect ratio via a structure on a semiconductor substrate.06-06-2013
20130178066METHOD AND APPARATUS FOR MANUFACTURING THREE-DIMENSIONAL-STRUCTURE MEMORY DEVICE - Provided is a method of manufacturing a memory device having a 3-dimensional structure, which includes alternately stacking one or more dielectric layers and one or more sacrificial layers on a substrate, forming a through hole passing through the dielectric layers and the sacrificial layers, forming a pattern filling the through hole, forming an opening passing through the dielectric layers and the sacrificial layers, and supplying an etchant through the opening to remove the sacrificial layers. The stacking of the dielectric layers includes supplying the substrate with one or more gases selected from the group consisting of SiH07-11-2013
20080214007METHOD FOR REMOVING DIAMOND LIKE CARBON RESIDUE FROM A DEPOSITION/ETCH CHAMBER USING A PLASMA CLEAN - Provided is a method for removing diamond like carbon residue from a deposition chamber. This method, in one embodiment, may include subjecting a deposition chamber including diamond like carbon residue to a plasma clean in the presence of fluorine containing gas and oxygen containing gas. The method may further include purging the deposition chamber having been subjected to the plasma clean with an inert gas, and pumping the deposition chamber having been subjected to the plasma clean.09-04-2008
20130095662INTEGRATED CIRCUIT METHOD WITH TRIPLE PATTERNING - The present disclosure provides one embodiment of an integrated circuit (IC) design method. The method includes receiving an IC design layout having a plurality of IC features. The method includes identifying, from the IC design layout, simple features as a first layout wherein the first layout does not violate design rules; and complex features as a second layout wherein the second layout violates the design rules. The method further includes generating a third layout and a fourth layout from the second layout wherein the third layout includes the complex features and connecting features to meet the design rules and the fourth layout includes trimming features.04-18-2013
20130115772Etching Method - The present invention relates to an etching method of capable of etching a silicon carbide substrate with a higher accuracy. A first etching step in which a silicon carbide substrate K is heated to a temperature equal to or higher than 200° C., SF6 gas is supplied into a processing chamber and plasma is generated from the SF6 gas, and a bias potential is applied to a platen, thereby isotropically etching the silicon carbide substrate K, and a second etching step in which the silicon carbide substrate K is heated to a temperature equal to or higher than 200° C., SF6 gas and O2 gas are supplied into the processing chamber and plasma is generated from the SF6 gas and the O2 gas, and a bias potential is applied to the platen on which the silicon carbide substrate K is placed, thereby etching the silicon carbide substrate K while forming a silicon oxide film as passivation film on the silicon carbide substrate K are alternately repeated.05-09-2013
20080206996SIDEWALL IMAGE TRANSFER PROCESSES FOR FORMING MULTIPLE LINE-WIDTHS - A method for simultaneously forming multiple line-widths, one of which is less than that achievable employing conventional lithographic techniques. The method includes providing a structure which includes a memory layer and a sidewall image transfer (SIT) layer on top of the memory layer. Then, the SIT layer is patterned resulting in a SIT region. Then, the SIT region is used as a blocking mask during directional etching of the memory layer resulting in a first memory region. Then, a side wall of the SIT region is retreated a retreating distance D in a reference direction resulting in a SIT portion. Said patterning comprises a lithographic process. The retreating distance D is less than a critical dimension CD associated with the lithographic process. The SIT region includes a first dimension W08-28-2008
20130149866BAFFLE PLATE FOR SEMICONDUCTOR PROCESSING APPARATUS - A baffle plate for redirecting a reactive gas flow within a process chamber of a semiconductor plasma processing apparatus includes a topside surface having a plurality of topside apertures for receiving the reactive gas flow and a bottomside surface having a plurality of bottomside apertures for emitting the reactive gas flow toward a semiconductor substrate. An outer portion of the baffle plate includes both topside apertures and bottomside apertures, while within an inner portion of the baffle plate for at least one of the topside surface and bottomside surface is a solid region throughout exclusive of any apertures. The inner portion has an outer dimension that is at least ten (10) percent of an outer dimension of the outer portion.06-13-2013
20100304568PATTERN FORMING METHOD - A pattern forming method includes forming a first photoresist on an underlying region, forming a second photoresist on the first photoresist, the second photoresist having an exposure sensitivity which is different from an exposure sensitivity of the first photoresist, radiating exposure light on the first and second photoresists via a photomask including a first transmissive region and a second transmissive region which cause a phase difference of 180° between transmissive light components passing therethrough, the first transmissive region and the second transmissive region being provided in a manner to neighbor in an irradiation region, and developing the first and second photoresists which have been irradiated with the exposure light, thereby forming a structure includes a first region where the underlying region is exposed, a second region where the first photoresist is exposed and a third region where the first photoresist and the second photoresist are left.12-02-2010
20100317194METHOD FOR FABRICATING OPENING - A method for fabricating openings is provided. A dielectric layer is formed on a substrate, and a first patterned mask layer is formed on the dielectric layer along a first direction. A second patterned mask layer is then formed on the dielectric layer along a second direction which intersects with the first direction. A portion of the dielectric layer is removed using the first patterned mask layer and the second patterned mask layer as a mask so as to from the openings. The dielectric layer, the first patterned mask layer and the second patterned mask layer have different etching selectivities.12-16-2010
20130157465METHODS FOR STRIPPING PHOTORESIST AND/OR CLEANING METAL REGIONS - Methods are provided for cleaning metal regions overlying semiconductor substrates. A method for removing material from a metal region comprises heating the metal region, forming a plasma from a gas comprising hydrogen and carbon dioxide, and exposing the metal region to the plasma.06-20-2013
20130157466SILICON NITRIDE FILMS FOR SEMICONDUCTOR DEVICE APPLICATIONS - The embodiments herein relate to plasma-enhanced chemical vapor deposition methods and apparatus for depositing silicon nitride on a substrate. The disclosed methods provide silicon nitride films having wet etch rates (e.g., in dilute hydrofluoric acid or hot phosphoric acid) suitable for certain applications such as vertical memory devices. Further, the methods provide silicon nitride films having defined levels of internal stress suitable for the applications in question. These silicon nitride film characteristics can be set or tuned by controlling, for example, the composition and flow rates of the precursors, as well as the RF power supplied to the plasma and the pressure in the reactor. In certain embodiments, a boron-containing precursor is added.06-20-2013
20120282776PHOTORESIST UNDERLAYER COMPOSITION AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE BY USING THE SAME - A photoresist underlayer composition includes a solvent, and a polysiloxane resin represented by Chemical Formula 1:11-08-2012
20130183828PATTERN FORMATION METHOD AND GUIDE PATTERN MATERIAL - According to one embodiment, a pattern formation method includes forming a pattern on a layer. The layer has a first surface energy and includes a silicon compound. The pattern has a second surface energy different from the first surface energy. The method includes forming a block polymer on the layer and the pattern. The method includes forming a structure selected from a lamellar structure and a cylindrical structure of the block polymer containing polymers arranged by microphase separation. The lamellar structure is oriented perpendicularly to the layer surface. The cylindrical structure is oriented so as to have an axis parallel to a normal line of the layer surface. The second surface energy is not less than a maximum value of surface energies of the polymers or not more than a minimum value of the surface energies of the polymers.07-18-2013
20110312183Method of Fine Patterning Semiconductor Device - For patterning during integrated circuit fabrication, a first pattern of first masking structures is formed, and a buffer layer is formed on exposed surfaces of the first masking structures. Also, a second pattern of second masking structures is formed in recesses between the buffer layer at sidewalls of the first masking structures. Furthermore, the first and masking structures are formed from spin-coating respective high carbon containing materials. Such first and second masking structures pattern a target layer with higher pitch than possible with traditional photolithography.12-22-2011
20130189844Method to increase the pattern density of integrated circuits using near-field EUV patterning technique - A novel near-field EUV patterning technique and the corresponding imaging film stacks are invented for integrated-circuit manufacturing. This invention pertains to methods of forming one and/or two dimensional features on an EUV near-field imaging material with patterned light absorbers sitting on its top. These methods can be used to produce integrated circuits with a feature density higher than what is possible using conventional EUV or optical DUV lithography.07-25-2013
20120028471METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes: forming a thin film on a substrate; forming a resist mask which forms a photoresist mask having an elliptical hole pattern on the thin film; shrinking a hole size of the second pattern by forming an insulating film on a side wall of the second pattern of the photoresist layer; and etching the thin film using the insulating film and the photoresist layer which form the second pattern having the shrinked hole size as a mask.02-02-2012
20120028470Increasing Robustness of a Dual Stress Liner Approach in a Semiconductor Device by Applying a Wet Chemistry - In a dual stress liner approach, unwanted material provided between closely spaced gate electrode structures may be removed to a significant degree on the basis of a wet chemical etch process, thereby reducing the risk of creating patterning-related irregularities. Consequently, the probability of contact failures in sophisticated interlayer dielectric material systems formed on the basis of a dual stress liner approach may be reduced.02-02-2012
20120028468METHOD OF FORMING A LAYER ON A SEMICONDUCTOR SUBSTRATE HAVING A PLURALITY OF TRENCHES - A method of fabricating a semiconductor device is illustrated. A substrate having a plurality of trenches is provided. The plurality of trenches include trenches having differing widths. A first layer is formed on the substrate including in the plurality of trenches. Forming the first layer creates an indentation in the first layer in a region overlying a trench (e.g., wide trench). A second layer is formed in the indentation. The first layer is etched while the second layer remains in the indentation. The second layer may protect the region of indentation from further reduction in thickness. In an embodiment, the first layer is polysilicon and the second layer is BARC of photoresist.02-02-2012
20130203256CONTROLLED GAS MIXING FOR SMOOTH SIDEWALL RAPID ALTERNATING ETCH PROCESS - A method for etching features in a silicon layer disposed below a mask in a plasma processing chamber a plurality of cycles is provided. A deposition phase forming a deposition on the silicon layer in the plasma processing chamber is provided comprising providing a deposition gas into the plasma processing chamber wherein the deposition gas comprises a halogen containing etchant component and a fluorocarbon deposition component, forming the deposition gas into a plasma, which provides a net deposition on the silicon layer, and stopping the flow of the deposition gas. A silicon etch phase is provided, comprising providing a silicon etch gas into the plasma processing chamber that is different than the deposition gas, forming the silicon etch gas into a plasma to etch the silicon layer, and stopping the flow of the silicon etch gas.08-08-2013
20130203255WAFERLESS AUTO CONDITIONING - A method for reducing contamination in an etch chamber is provided. A substrate with a metal containing layer is placed in the etch chamber. The metal containing layer is etched, producing nonvolatile metal residue deposits on surfaces of the etch chamber, wherein some of the metal residue of the metal residue deposits is in a first state. The substrate is removed from the etch chamber. The chamber is conditioned by converting metal residue in the first state to metal residue in a second state, where metal residue in the second state has stronger adhesion to surfaces of the etch chamber than metal residue in the first state.08-08-2013
20130210231METHOD OF FORMING CONTACT HOLE PATTERN - A method of forming a contact hole pattern, including: a block copolymer layer forming step in which a layer containing a block copolymer having a plurality of blocks bonded is formed on a substrate having on a surface thereof a thin film with a hole pattern formed, so as to cover the thin film; a phase separation step in which the layer containing the block copolymer is subjected to phase separation; a selective removing step in which phase of at least one block of the plurality of blocks constituting the block copolymer is removed, wherein hole diameter of the hole pattern formed on the thin film is 0.8 to 3.1 times period of the block copolymer, and in the layer forming step, thickness between upper face of the thin film and surface of the layer containing the block copolymer is 70% or less of thickness of the thin film.08-15-2013

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