Entries |
Document | Title | Date |
20080206991 | METHODS OF FORMING TRANSISTOR CONTACTS AND VIA OPENINGS - A method of forming contacts to a transistor comprises depositing a dielectric layer on a substrate having the transistor, etching a first opening in the dielectric layer that contacts a gate stack of the transistor, depositing a sacrificial material in the first opening, and etching a second and a third opening in the dielectric layer that contact a source and a drain region of the transistor, wherein the second and third openings are etched after the first opening is etched. By etching the opening to the gate stack first, defects such as contact-to-gate shorts are reduced or eliminated. | 08-28-2008 |
20080214004 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device and semiconductor device. One embodiment provides a semiconductor substrate with an active region and a margin region bordering on the active region. The spacer layer in the margin region is broken through at a selected location and at least part of the spacer layer is removed in the active region using a common process. The location is selected such that at least part of the semiconductor mesa structure is exposed and the spacer layer in the margin region is broken through to the conductive layer and not to the semiconductor substrate. | 09-04-2008 |
20080220609 | Methods of Forming Mask Patterns on Semiconductor Wafers that Compensate for Nonuniform Center-to-Edge Etch Rates During Photolithographic Processing - Methods of forming integrated circuit devices include steps to selectively widen portions of a mask pattern extending adjacent an outer edge of a semiconductor wafer. These steps to selectively widen portions of the mask pattern are performed so that more uniform center-to-edge critical dimensions (CD) can be achieved when the mask pattern is used to support photolithographically patterning of underlying layers (e.g., insulating layers, antireflective coatings, etc.). | 09-11-2008 |
20080233746 | METHOD FOR MANUFACTURING MOS TRANSISTORS UTILIZING A HYBRID HARD MASK - A method for manufacturing MOS transistor with hybrid hard mask includes providing a substrate having a dielectric layer and a polysilicon layer thereon, forming a hybrid hard mask having a middle hard mask and a spacer hard mask covering sidewalls of the middle hard mask on the polysilicon layer, performing a first etching process to etch the polysilicon layer and the dielectric layer through the hybrid hard mask to form a gate structure, performing a second etching process to form recesses in the substrate at two sides of the gate structure, and performing a SEG process to form epitaxial silicon layers in each recess. | 09-25-2008 |
20080233747 | Semiconductor Device Manufactured Using an Improved Plasma Etch Process for a Fully Silicided Gate Flow Process - In one aspect, there us provided a method of manufacturing a semiconductor device that comprises placing an oxide layer over a gate electrode and sidewall spacers located adjacent thereto, placing a protective layer over the oxide layer, conducting a plasma etch to remove portions of the protective layer and the first oxide layer that are located over the gate electrode and expose a surface of the gate electrode, wherein the plasma etch is selective to polysilicon. A soft etch is conducted subsequent to the plasma etch. The soft etch includes an inorganic-based fluorine containing gas and an inert gas, wherein the plasma etch leaves a film on the gate electrode that inhibits silicidation of the gate electrode and wherein the soft etch removes the film. The gate electrode is silicided with a metal subsequent to conducting the soft etch. | 09-25-2008 |
20080233748 | ETCH DEPTH DETERMINATION FOR SGT TECHNOLOGY - A method for determining the depth etch, a method of forming a shielded gate trench (SGT) structure and a semiconductor device wafer are disclosed. A material layer is formed over part of a substrate having a trench. The material fills the trench. A resist mask is placed over a test portion of the layer of material. The resist mask does not cover the trench. The layer of material is isotropically etched. An etch depth may be determined from a characteristic of etching of the material underneath the mask. Such a method may be used for forming SGT structures. The wafer may comprise a layer of material disposed on at least a portion of a surface of semiconductor wafer; a resist mask comprising an angle-shaped test portion disposed over a portion of the layer of material; and a ruler marking on the surface of the substrate proximate the test portion. | 09-25-2008 |
20080254625 | Method for Cleaning a Semiconductor Structure and Chemistry Thereof - A method for removing a etch residue (e.g., polymer or particle) from a semiconductor structure and using a cleaning chemistry and the composition of the chemistry is described. By providing a semiconductor structure with etch residue on it, the semiconductor substrate is then placed in a chemistry to remove the particle, wherein the chemistry comprises dilute hydrofluoric acid and a carboxylic acid. In one embodiment the carboxylic acid is selected from tartaric acid, acetic acid, citric acid, glycolic acid, oxalic acid, salicyclic acid, or phthalic acid, and the dilute hydrofluoric acid is approximately 0.1 weight % of hydrofluoric acid. | 10-16-2008 |
20080254626 | PROCESSING APPARATUS - A processing apparatus for transferring a relief pattern on a mold to a resist on a substrate through a compression of the mold against the resist, includes a supplier for supplying the resist between the substrate and the mold, and a recovery unit for recovering the resist. | 10-16-2008 |
20080254627 | METHOD FOR ADJUSTING FEATURE SIZE AND POSITION - Variations in the pitch of features formed using pitch multiplication are minimized by separately forming at least two sets of spacers. Mandrels are formed and the positions of their sidewalls are measured. A first set of spacers is formed on the sidewalls. The critical dimension of the spacers is selected based upon the sidewall positions, so that the spacers are centered at desired positions. The mandrels are removed and the spacers are used as mandrels for a subsequent spacer formation. A second material is then deposited on the first set of spacers, with the critical dimensions of the second set of spacers chosen so that these spacers are also centered at their desired positions. The first set of spacers is removed and the second set is used as a mask for etching a substrate. By selecting the critical dimensions of spacers based partly on the measured position of mandrels, the pitch of the spacers can be finely controlled. | 10-16-2008 |
20090042388 | METHOD OF CLEANING A SEMICONDUCTOR SUBSTRATE - A semiconductor substrate is first provided. The semiconductor substrate includes a material layer and a patterned photoresist layer disposed on the material layer. Subsequently, a contact etching process is performed on the material layer by utilizing the patterned photoresist layer as an etching mask so to form an etched hole in the material layer. Thereafter, a solvent cleaning process is carried out on the semiconductor substrate by utilizing a cleaning solvent. Next, a water cleaning process is performed on the semiconductor substrate by utilizing deionized water. The temperature of the deionized water is in a range from 30° C. to 99° C. | 02-12-2009 |
20090042389 | Double exposure semiconductor process for improved process margin - A double exposure semiconductor process is provided for improved process margin at reduced feature sizes. During a first processing sequence, features defining non-critical dimensions of a polysilicon interconnect structure are formed, while other portions of the polysilicon layer are left un-processed. During a second processing sequence, features that define the critical dimensions of the polysilicon interconnect structure are formed without the need to execute a photoresist trimming procedure. Accordingly, only an etch process is executed, which provides higher resolution processing to create the critical dimensions needed during the second processing sequence. | 02-12-2009 |
20090111266 | Method of Forming Gate of Semiconductor Device - A method of forming a gate of a semiconductor device comprising providing a semiconductor substrate over which a gate insulating layer, a first conductive layer, a dielectric layer, and a second conductive layer are sequentially formed, the semiconductor substrate defining gate line regions; removing he second conductive layer between gate line regions; removing the dielectric layer so that a top surface of the first conductive layer between the gate line regions is exposed; performing a first etch process in order to lower a height of the first conductive layer between the gate line region; removing he dielectric layer between the gate line regions; and, performing a second etch process in order to remove the first conductive layer between the gate line regions. | 04-30-2009 |
20090156005 | Cleaning liquid used in process for forming dual damascene structure and a process for treating substrate therewith - It is disclosed a cleaning liquid used in a process for forming a dual damascene structure comprising steps of etching a low dielectric layer (low-k layer) accumulated on a substrate having thereon a metallic layer to form a first etched-space; charging a sacrifice layer in the first etched-space; partially etching the low dielectric layer and the sacrifice layer to form a second etched-space connected to the first etched-space; and removing the sacrifice layer remaining in the first etched-space with the cleaning liquid, wherein the cleaning liquid comprises (a) 1-25 mass % of a quaternary ammonium hydroxide, such as TMAH and choline, (b) 30-70 mass % of a water soluble organic solvent, and (c) 20-60 mass % of water. The cleaning liquid attains in a well balanced manner such effects that a sacrifice layer used for forming a dual damascene structure is excellently removed, and a low dielectric layer is not damaged upon formation of a metallic wiring on a substrate having a metallic layer (such as a Cu layer) and the low dielectric layer formed thereon. | 06-18-2009 |
20090170316 | Double patterning with single hard mask - In general, in one aspect, a method includes forming a hard mask on a semiconductor substrate. A first resist layer is patterned on the hard mask as a first plurality of lines separated by a first defined pitch. The hard mask is etched to a portion of formed thickness to create a first plurality of fins in alignment with the first plurality of lines and the first resist layer is removed. A second resist layer is patterned on the hard mask as a second plurality of lines separated by a second defined pitch. The second plurality of lines is patterned between the first plurality of lines. The hard mask is etched to the portion of the formed thickness to create a second plurality of fins in alignment with the second plurality of lines. The first plurality of hard mask fins and the second plurality of hard mask fins are interwoven and have same thickness. | 07-02-2009 |
20090176370 | SINGLE SOI WAFER ACCELEROMETER FABRICATION PROCESS - Methods for producing a MEMS device from a single silicon-on-insulator (SOI) wafer. An SOI wafer includes a silicon (Si) handle layer, a Si mechanism layer and an insulator layer located between the Si handle and Si mechanism layers. An example method includes etching active components from the Si mechanism layer. Then, the exposed surfaces of the Si mechanism layer is doped with boron. Next, portions of the insulator layer proximate to the etched active components of the Si mechanism layer are removed and the Si handle layer is etched proximate to the etched active components. | 07-09-2009 |
20090186483 | ETCHING AMOUNT CALCULATING METHOD, STORAGE MEDIUM, AND ETCHING AMOUNT CALCULATING APPARATUS - An etching amount calculating method that can stably and accurately calculate the amount of etching even if a disturbance is added. Superposed interference light resulting from superposition of interference light of reflected light from a mask film and reflected light from the bottom of a concave portion on other interference light is received. A waveform in a predetermined time period is extracted from a superposed interference wave calculated from the superposed interference light. The period of an interference wave of the reflected light from the mask film and the reflected light from the bottom is detected from the distribution of frequencies of the extracted waveform. The steps described above are repeated while shifting the predetermined time period by a predetermined time, and the detected periods are integrated and averaged at each repetition. The etching amount of the concave portion is calculated based on the integrated and averaged periods. | 07-23-2009 |
20090191709 | Method for Manufacturing a Semiconductor Device - A polymer for immersion lithography comprising a repeating unit represented by Formula 1 and a photoresist composition containing the same. A photoresist film formed by the photoresist composition of the invention is highly resistant to dissolution, a photoacid generator in an aqueous solution for immersion lithography, thereby preventing contamination of an exposure lens and deformation of the photoresist pattern by exposure. | 07-30-2009 |
20090203211 | MULTI-CHAMBER SYSTEM HAVING COMPACT INSTALLATION SET-UP FOR AN ETCHING FACILITY FOR SEMICONDUCTOR DEVICE MANUFACTURING - A multi-chamber system of an etching facility for manufacturing semiconductor devices occupies a minimum amount of floor space in a clean room by installing a plurality of processing chambers in multi-layers and in parallel along a transfer path situated between the processing chambers. The multi-layers number | 08-13-2009 |
20090233443 | SUBSTRATE MOUNTING TABLE, SUBSTRATE PROCESSING APPARATUS AND TEMPERATURE CONTROL METHOD - A substrate mounting table for mounting a substrate in a substrate processing apparatus, includes a table body having a substrate mounting surface. An annular peripheral ridge portion is formed on the substrate mounting surface of the table body. The annular peripheral ridge portion makes contact with a peripheral edge portion of the substrate and forms a closed space for circulation of a heat transfer gas below the substrate, when the substrate is mounted on the substrate mounting surface of the table body. The table body has a heat transfer gas inlet port formed in a peripheral edge region of the substrate mounting surface, a heat transfer gas outlet port formed in a central region of the substrate mounting surface, and a flow path formed on the substrate mounting surface for forming a conductance C when the heat transfer gas flows from the inlet port to the outlet port. | 09-17-2009 |
20090246954 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device, includes forming a plurality of core portions arranged in a predetermined direction, on a to-be-processed film, forming a stacked sidewall portion in which a first sidewall portion and a second sidewall portion are stacked in that order, on each of side surfaces, of each of the core portions, removing the core portions to form a structure having a first space between the adjacent first sidewall portions and a second space between the adjacent second sidewall portions, and retreating at least one of the first sidewall portion and the second sidewall portion by a desired retreat amount to slim the stacked sidewall portion, after removing the core portions. | 10-01-2009 |
20090253263 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE CAPABLE OF DECREASING CRITICAL DIMENSION IN PERIPHERAL REGION - A method for fabricating a semiconductor device where a critical dimension in a peripheral region is decreased. The method includes the steps of: forming a silicon nitride layer on a substrate including a cell region and a peripheral region; forming a silicon oxynitride layer on the silicon nitride layer; forming a line-type photoresist pattern on the silicon oxynitride layer such that the photoresist pattern in the cell region has a width larger than that of a final pattern structure and the photoresist pattern in the peripheral region has a width that reduces an incidence of pattern collapse; etching the silicon oxynitride layer and the silicon nitride layer until widths of a remaining silicon oxynitride layer and a remaining silicon nitride layer are smaller than the width of the photoresist pattern used as an etch mask through suppressing generation of polymers; and over-etching the remaining silicon nitride layer. | 10-08-2009 |
20090291558 | MULTI-CHAMBER SYSTEM HAVING COMPACT INSTALLATION SET-UP FOR AN ETCHING FACILITY FOR SEMICONDUCTOR DEVICE MANUFACTURING - A multi-chamber system of an etching facility for manufacturing semiconductor devices occupies a minimum amount of floor space in a clean room by installing a plurality of processing chambers in multi-layers and in parallel along a transfer path situated between the processing chambers. The multi-layers number 2 to 5, and the transfer path can be rectangular in shape and need only be slightly wider than the diameter of a wafer. The total width of the multi-chamber system is the sum of the width of one processing chamber plus the width of the transfer path. | 11-26-2009 |
20090311861 | Methods of forming fine patterns in the fabrication of semiconductor devices - In a method of forming a semiconductor device, a feature layer is provided on a substrate and a mask layer is provided on the feature layer. A portion of the mask layer is removed in a first region of the semiconductor device where fine features of the feature layer are to be located, the mask layer remaining in a second region of the semiconductor device where broad features of the feature layer are to be located. A mold mask pattern is provided on the feature layer in the first region and on the mask layer in the second region. A spacer layer is provided on the mold mask pattern in the first region and in the second region. An etching process is performed to etch the spacer layer so that spacers remain at sidewalls of pattern features of the mold mask pattern, and to etch the mask layer in the second region to provide mask layer patterns in the second region. The feature layer is etched using the mask layer patterns as an etch mask in the second region and using the spacers as an etch mask in the first region to provide a feature layer pattern having fine features in the first region and broad features in the second region. | 12-17-2009 |
20100009536 | MULTILAYER LOW REFLECTIVITY HARD MASK AND PROCESS THEREFOR - A method utilizing a multilayer anti-reflective coating layer structure can achieve low reflectivity at high numerical apertures. The multilayer anti-reflective coating structure can be utilized as a hard mask forming various integrated circuit structures. A multilayer anti-reflective coating structure can be utilized to form gate stacks comprised of polysilicon and a dielectric layer. A photoresist is applied above the multilayer anti-reflective coating which can include silicon oxynitride (SiON) and silicon rich nitride (SiRN). | 01-14-2010 |
20100093171 | FABRICATION CUBIC BORON NITRIDE CONE-MICROSTRUCTURES AND THEIR ARRAYS - A conical structure of cubic Boron Nitride (cBN) is formed on a diamond layered substrate. A method of forming the cBN structure includes steps of (a) forming diamond nuclei on a substrate, (b) growing a layer of diamond film on the substrate, (c) depositing a cBN film on said diamond layer, (d) pre-depositing nanoscale etching masks on the the cBN film, and (e) etching the the deposited cBN film. In particular, though not exclusively, the cubic Boron Nitride structure has great potential applications in probe analytical and testing techniques including scanning probe microscopy (SPM) and nanoindentation, nanomechanics and nanomachining in progressing microelectromechanical system (MEMS) and nanoelectyromechanical system (NEMS) devices, field electron emission, vacuum microelectronic devices, sensors and different electrode systems including those used in electrochemistry. | 04-15-2010 |
20100093172 | METHOD OF FORMING FINE PATTERNS OF A SEMICONDUCTOR DEVICE - A method of forming fine patterns of a semiconductor device includes forming a plurality of first mask patterns on a substrate such that the plurality of first mask patterns are separated from one another by a space located therebetween, in a direction parallel to a main surface of the substrate, forming a plurality of capping films formed of a first material having a first solubility in a solvent on sidewalls and a top surface of the plurality of first mask patterns. The method further includes forming a second mask layer formed of a second material having a second solubility in the solvent, which is less than the first solubility, so as to fill the space located between the plurality of first mask patterns, and forming a plurality of second mask patterns corresponding to residual portions of the second mask layer which remain in the space located between the plurality of first mask patterns, after removing the plurality of capping films and a portion of the second mask layer using the solvent. | 04-15-2010 |
20100093173 | METHOD OF FORMING PATTERNS OF SEMICONDUCTOR DEVICE - A method in the fabrication of a semiconductor device simultaneously forms different patterns on the same level of the device. The device has a first area and a second area. A low density mask pattern of at least one relatively wide topographic feature is formed on the second area, a plurality of relatively narrow topographic features is formed on the first area, first spacers are formed on side walls of the narrow topographic features in the first area, the relatively narrow topographic features are removed, and the patterns of the first spacers and the relatively wide topographic feature(s) are simultaneously transcribed in the first and second areas, respectively. | 04-15-2010 |
20100099258 | SEMICONDUCTOR DEVICE CLEANING METHOD AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD USING THE SAME - A semiconductor device cleaning method includes etching one of a semiconductor substrate for forming a contact hole in the semiconductor substrate and the bottom of the contact hole on a semiconductor substrate, and cleaning the semiconductor substrate with a cleaning solution, wherein the cleaning solution includes a mixture of sulfuric acid (H | 04-22-2010 |
20100112815 | FLUID STORAGE AND DISPENSING SYSTEMS AND PROCESSES - Fluid storage and dispensing systems and processes involving various devices, structures and arrangements, as well as techniques and methods, for fluid storage and dispensing, including, without limitation, pre-connect verification couplings that are usefully employed in application to fluid storage and dispensing packages, to ensure proper coupling and avoid fluid contamination issues, empty detect systems that are usefully employed for fluid storage and dispensing packages incorporating liners that are pressure-compressed in the fluid dispensing operation, ergonomically enhanced structures for facilitating removal of a dispense connector from a capped vessel, cap integrity assurance systems for preventing misuse of vessel caps, and keycoding systems for ensuring coupling of proper dispense assemblies and vessels. Fluid storage and dispensing systems are described, which achieve zero or near-zero headspace character, and prevent or ameliorate solubilization effects in liquid dispensing from liners in overpack vessels. | 05-06-2010 |
20100130010 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE UNCONSTRAINED BY OPTICAL LIMIT AND APPARATUS OF FABRICATING THE SEMICONDUCTOR DEVICE - Provided are a method of fabricating a semiconductor device unconstrained by optical limit and an apparatus of fabricating the semiconductor device. The method includes: forming an etch target layer on a substrate; forming a hard mask layer on the etch target layer; forming first mask patterns on the hard mask layer; forming first spacers on sidewalls of the first mask patterns; forming hard mask patterns having an opening by using the first mask patterns and the first spacers as a mask to etch the hard mask layer; aligning second mask patterns on the hard mask patterns to fill the opening; forming second spacers on sidewalls of the second mask patterns; forming fine mask patterns by using the second mask patterns and the second spacers as a mask to etch the hard mask patterns; and forming fine patterns by using the fine mask patterns as a mask to etch the etch target layer. | 05-27-2010 |
20100130011 | SEMICONDUCTOR DEVICE FABRICATION METHOD - According to a disclosed semiconductor device fabrication method according to one embodiment of the present invention, a layer having a line-and-space pattern extending in one direction is etched using another layer having a line-and-space pattern extending in another direction intersecting the one direction, thereby obtaining a mask having two-dimensionally arranged dots. An underlying layer is etched using the mask, thereby providing two-dimensionally arranged pillars. | 05-27-2010 |
20100144147 | SAMPLE HOLDING TOOL, SAMPLE SUCTION DEVICE USING THE SAME AND SAMPLE PROCESSING METHOD USING THE SAME - A sample holding tool is provided with a base plate, a plurality of convex portions formed on the base plate so as to stick out from the upper face thereof; and at least one holding plate having a plurality of curved face portions corresponding to the convex portions, with a lower face concave portion of each of the curved face portions being made in contact with the tip portion of each of the convex portions, so that a sample is supported on the upper face convex portion of each of the curved face portions; thus, since the sample is supported by the curved face portion of the holding plate, the contact area to the sample is made very small so that it becomes possible to greatly reduce pointed peak portions, scratches and the like at contact portions between the sample and the curved face portions. Consequently, generation of particles due to abrasion of the sample can be reduced and the particles are reduced from intruding into scratches and voids and occasionally readhering to the sample. | 06-10-2010 |
20100144148 | METHOD FOR MANUFACTURE OF SEMICONDUCTOR DEVICE - A semiconductor device manufacturing method includes designing a resist structure including a film having antireflection function for exposure light and a resist on the film to be formed on a substrate, designing an exposure condition of the resist obtained by exposing and developing the resist such that a resist pattern is finished as designed, obtaining criteria value for estimating influence of a resist pattern upon a dimension or shape of a device pattern, the resist pattern being obtained by exposing the resist under the designed exposure condition and developing the exposed resist, the device pattern being obtained by etching the resist structure using the resist pattern as a mask, determining whether the designed exposure condition is acceptable or not based on the criteria value, and redesigning the exposure condition of the resist without changing the designed resist structure when the designed exposure condition is determined not acceptable. | 06-10-2010 |
20100167544 | DOOR ASSEMBLY FOR SUBSTRATE PROCESSING CHAMBER - A substrate processing apparatus includes an enclosure defining a reaction chamber, a substrate holder in the reaction chamber, and a door assembly. The door assembly has a substrate entrance with a tunnel extending to the reaction chamber, a door movable with respect to the substrate entrance, and a pattern of features. The features are located along a portion of the substrate entrance defining the tunnel. The features promote sticking of processing byproducts, produced in the reaction chamber, to the substrate entrance. A door mates with the entrance to form a seal that reduces flow through the tunnel to control the amount of byproducts that enter the tunnel. | 07-01-2010 |
20100173492 | METHOD OF FORMING SEMICONDUCTOR DEVICE PATTERNS - Provided is a method of forming patterns of a semiconductor device, whereby patterns having various widths can be simultaneously formed, and pattern density can be doubled by a double patterning process in a portion of the semiconductor device. In the method of forming patterns of a semiconductor device, a first mold mask pattern and a second mold mask patter having different widths are formed on a substrate. A pair of first spacers covering both sidewalls of the first mold mask pattern and a pair of second spacers covering both sidewalls of the second mold mask pattern are formed. The first mold mask pattern and the second mold mask pattern are removed, and a wide-width mask pattern covering the second spacer is formed. A lower layer is etched using the first spacers, the second spacers, and the wide-width mask pattern as an etch mask. | 07-08-2010 |
20100203727 | METHOD FOR INTEGRATED CIRCUIT FABRICATION USING PITCH MULTIPLICATION - Different sized features in the array and in the periphery of an integrated circuit are patterned on a substrate in a single step. In particular, a mixed pattern, combining two separately formed patterns, is formed on a single mask layer and then transferred to the underlying substrate. The first of the separately formed patterns is formed by pitch multiplication and the second of the separately formed patterns is formed by conventional photolithography. The first of the separately formed patterns includes lines that are below the resolution of the photolithographic process used to form the second of the separately formed patterns. These lines are made by forming a pattern on photoresist and then etching that pattern into an amorphous carbon layer. Sidewall pacers having widths less than the widths of the un-etched parts of the amorphous carbon are formed on the sidewalls of the amorphous carbon. The amorphous carbon is then removed, leaving behind the sidewall spacers as a mask pattern. Thus, the spacers form a mask having feature sizes less than the resolution of the photolithography process used to form the pattern on the photoresist. A protective material is deposited around the spacers. The spacers are further protected using a hard mask and then photoresist is formed and patterned over the hard mask. The photoresist pattern is transferred through the hard mask to the protective material. The pattern made out by the spacers and the temporary material is then transferred to an underlying amorphous carbon hard mask layer. The pattern, having features of difference sizes, is then transferred to the underlying substrate. | 08-12-2010 |
20100203728 | SEMICONDUCTOR DEVICE AND A MANUFACTURING METHOD THEREOF - A semiconductor device includes at least two adjacent memory cell blocks, each of the memory cell blocks having a plurality of memory cell units, each of memory cell units having a plurality of electrically reprogrammable and erasable memory cells connected in series, a plurality of cell gates for selecting the plurality of memory cells within the two adjacent memory cell blocks, each of the plurality of cell gates being formed with roughly rectangular closed loops or roughly U shaped open loops, each of the loops being connected to a corresponding cell of the memory cells in a corresponding memory cell unit of the plurality of memory cell units within one of the two adjacent memory cell blocks and being connected to a corresponding memory cell of the memory cells in a corresponding memory cell unit of the plurality of memory cell units within the other memory cell block of the two adjacent memory cell blocks and a plurality of pairs of first and second selection gates for selecting the memory cell block, the plurality of cell gates being located between one pair of the first and second selection gates within a corresponding block of the memory cell block. | 08-12-2010 |
20100216307 | SIMPLIFIED PITCH DOUBLING PROCESS FLOW - A method for fabricating a semiconductor device comprises patterning a layer of photoresist material to form a plurality of mandrels. The method further comprises depositing an oxide material over the plurality of mandrels by an atomic layer deposition (ALD) process. The method further comprises anisotropically etching the oxide material from exposed horizontal surfaces. The method further comprises selectively etching photoresist material. | 08-26-2010 |
20100221915 | METHOD AND APPARATUS FOR SEMICONDUCTOR PROCESSING - A method and apparatus for semiconductor processing is disclosed. In one embodiment, a method of transporting a wafer within a cluster tool, comprises placing the wafer into a first segment of a vacuum enclosure, the vacuum enclosure being attached to a processing chamber and a factory interface. The wafer is transported to a second segment of the vacuum enclosure using a vertical transport mechanism, wherein the second segment is above or below the first segment. | 09-02-2010 |
20100221916 | Methods of Etching Oxide, Reducing Roughness, and Forming Capacitor Constructions - The invention includes methods in which one or more components of a carboxylic acid having an aqueous acidic dissociation constant of at least 1×10 | 09-02-2010 |
20100248477 | Cleaning liquid used in process for forming dual damascene structure and a process for treating a substrate therewith - It is disclosed a cleaning liquid used in a process for forming a dual damascene structure comprising steps of etching a low dielectric layer (low-k layer) accumulated on a substrate having thereon a metallic layer to form a first etched-space; charging a sacrifice layer in the first etched-space; partially etching the low dielectric layer and the sacrifice layer to form a second etched-space connected to the first etched-space; and removing the sacrifice layer remaining in the first etched-space with the cleaning liquid, wherein the cleaning liquid comprises (a) 1-25 mass % of a quaternary ammonium hydroxide, such as TMAH and choline (b) 30-70 mass % of a water soluble organic solvent, and (c) 20-60 mass % of water. The cleaning liquid attains in a well balanced manner such effects that a sacrifice layer used for forming a dual damascene structure is excellently removed, and a low dielectric layer is not damaged upon formation of a metallic wiring on a substrate having a metallic layer (such as a Cu layer) and the low dielectric layer formed thereon. | 09-30-2010 |
20100267237 | METHODS FOR FABRICATING FINFET SEMICONDUCTOR DEVICES USING ASHABLE SACRIFICIAL MANDRELS - Methods are provided for fabricating a semiconductor device on and in a semiconductor substrate. In accordance with an exemplary embodiment of the invention, one method comprises forming a sacrificial mandrel overlying the substrate, the sacrificial mandrel having sidewalls. Sidewall spacers are formed adjacent the sidewalls of the sacrificial mandrel. The sacrificial mandrel is removed using an ashing process, and the substrate is etched using the sidewall spacers as an etch mask after removal of the sacrificial mandrel. | 10-21-2010 |
20100279505 | METHOD FOR FABRICATING PATTERNS ON A WAFER THROUGH AN EXPOSURE PROCESS - A method for forming patterns on a wafer includes forming a fence having a sloped face in an edge portion of the wafer. The sloped face is direct to an inside of the wafer. A first photoresist layer is formed which extends to cover the fence on the wafer. First photoresist patterns are formed by performing a first exposure and development on the first photoresist layer. An etch process is performed using the first photoresist patterns and the fence as an etch mask. The fence is formed by selectively exposing a negative resist using a light shielding blade, and at this time, the first photoresist layer is formed including a positive resist. | 11-04-2010 |
20100311242 | METHODS FOR FABRICATING SEMICONDUCTOR DEVICES - Methods are provided for fabricating a semiconductor device. One method comprises providing a first pattern having a first polygon, the first polygon having a first tonality and having a first side and a second side, the first side adjacent to a second polygon having a second tonality, and the second side adjacent to a third polygon having the second tonality, and forming a second pattern by reversing the tonality of the first pattern. The method further comprises forming a third pattern from the second pattern by converting the second polygon from the first tonality to the second tonality forming a fourth pattern from the second pattern by converting the third polygon from the first tonality to the second tonality forming a fifth pattern by reversing the tonality of the third pattern, and forming a sixth pattern by reversing the tonality of the fourth pattern. | 12-09-2010 |
20100330807 | SEMICONDUCTOR APPARATUS MANUFACTURING METHOD AND IMPRINT TEMPLATE - A method for manufacturing a semiconductor apparatus, includes: supplying a first imprint material onto a dicing region surrounding each chip of a semiconductor wafer; bringing a first template having a frame-like configuration into contact with the first imprint material and curing the first imprint material; peeling the first template from the first imprint material to form a first pattern in the first imprint material after the curing of the first imprint material; supplying a second imprint material onto a chip region of the semiconductor wafer on an inner side of the first pattern; bringing a second template into contact with the second imprint material and curing the second imprint material; peeling the second template from the second imprint material to form a second pattern in the second imprint material after the curing of the second imprint material; etching the semiconductor wafer, the first imprint material having the first pattern and the second imprint material having the second pattern being used as a mask. | 12-30-2010 |
20110014790 | METHODS FOR FABRICATING SEMICONDUCTOR DEVICES - Methods are provided for fabricating a semiconductor device on and in a semiconductor substrate. In one embodiment, a method comprises the steps of forming etch masking features overlying the semiconductor substrate, the etch masking features having a first thickness, and forming an etch barrier layer overlying the substrate, the etch barrier layer having a second thickness less than or substantially equal to the first thickness. The method also comprises removing the etch masking features to expose the substrate, and etching the substrate using the etch barrier layer as an etch mask. | 01-20-2011 |
20110027993 | METHODS OF FORMING FINE PATTERNS OF SEMICONDUCTOR DEVICE - A method of forming fine patterns of a semiconductor device is provided. The method includes forming plural preliminary first mask patterns, which are spaced apart from each other by a first distance in a direction parallel to a surface of a substrate, on the substrate; forming an acid solution layer on the substrate to cover the plural preliminary first mask patterns; forming plural first mask patterns which are spaced apart from each other by a second distance larger than the first distance, of which upper and side portions are surrounded by acid diffusion regions having first solubility; exposing the first acid diffusion regions by removing the acid solution layer; forming a second mask layer having second solubility lower than the first solubility in spaces between the acid diffusion regions; and forming plural second mask patterns located between the plural first mask patterns, respectively, by removing the acid diffusion regions by the dissolvent. | 02-03-2011 |
20110034029 | PATTERN FORMATION METHOD AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, a pattern formation method is disclosed. The method includes forming a plurality of regions on a foundation and the plurality of the regions correspond to different pattern sizes. The method includes separating each of a plurality of block copolymers from another one of the plurality of the block copolymers and segregating the each of the plurality of the block copolymers into a corresponding one of the regions. The method includes performing a phase separation of the each of the block copolymers of each of the regions. The method includes selectively removing a designated phase of each of the phase-separated block copolymers to form a pattern of the each of the block copolymers and the pattern has a different pattern size for the each of the regions. | 02-10-2011 |
20110070733 | TEMPLATE AND PATTERN FORMING METHOD - A template for imprinting in which a pattern is transferred onto a first substrate applied curable resin thereon, including a second substrate having a surface to be contacted with the curable resin, a concave portion provided on the surface and corresponding to a pattern to be transferred onto the first substrate, and at least one convex portion arranged in the concave portion to decrease volume of the concave portion. | 03-24-2011 |
20110070734 | MANUFACTURING A MICROELECTRONIC DEVICE COMPRISING SILICON AND GERMANIUM NANOWIRES INTEGRATED ON A SAME SUBSTRATE - The invention relates to a method for manufacturing a device comprising a structure with nanowires based on a semiconducting material such as Si and another structure with nanowires based on another semiconducting material such as SiGe, and is notably applied to the manufacturing of transistors. | 03-24-2011 |
20110076848 | SEMICONDUCTOR PROCESS CHAMBER AND SEAL | 03-31-2011 |
20110076849 | PROCESS FOR BONDING AND TRANSFERRING A LAYER - A method of fabricating a multilayer substrate may include bonding a front face of a donor substrate to a front face of a receiver substrate by molecular adhesion to form a stack and applying a heat treatment to the stack to consolidate a bond interface between the donor substrate and the receiver substrate. The method may further include thinning a back face of the donor substrate, trimming a periphery of the donor substrate and at least a portion of a periphery of the receiver substrate, and etching the back face of the donor substrate, the periphery of the donor substrate, and the at least a portion of the periphery of the receiver substrate subsequent to thinning the back face of the donor substrate and trimming the periphery of the donor substrate and the at least a portion of the periphery of the receiver substrate. | 03-31-2011 |
20110086511 | PHOTOMASK HAVING A REDUCED FIELD SIZE AND METHOD OF USING THE SAME - A photomask used for manufacturing a semiconductor device includes a substrate; and one or more layers disposed over the substrate, the one or more layers defining a full field area and a reduced field area with a primary pattern being formed in the reduced field area, wherein the full field area is defined by a width of at least 90 mm and a height of at least 100 mm, and the reduced field area is defined by a width within the range of approximately 20-80 mm and a height within the range of approximately 20-80 mm, a center point of the primary patterned area being spaced a predetermined distance from a center point of the photomask so that the primary patterned area avoids photomask defects. | 04-14-2011 |
20110104898 | Method of Forming Semiconductor Device - A method of forming a semiconductor device comprises forming a mask pattern over an etch target layer, forming an ion implantation region in the mask pattern through an ion implantation process, and forming an ion non-implantation region within the mask pattern, removing the ion implantation region on a top surface of the ion non-implantation region, removing the ion non-implantation region, and patterning the etch target layer by using spacers that comprise the ion implantation region as an etch mask. | 05-05-2011 |
20110111592 | ANGLE ION IMPLANT TO RE-SHAPE SIDEWALL IMAGE TRANSFER PATTERNS - A method for fabrication of features of an integrated circuit and device thereof include patterning a first structure on a surface of a semiconductor device and forming spacers about a periphery of the first structure. An angled ion implantation is applied to the device such that the spacers have protected portions and unprotected portions from the angled ion implantation wherein the unprotected portions have an etch rate greater than an etch rate of the protected portions. The unprotected portions and the first structure are selectively removed with respect to the protected portions. A layer below the protected portions of the spacer is patterned to form integrated circuit features. | 05-12-2011 |
20110111593 | PATTERN FORMATION METHOD, PATTERN FORMATION SYSTEM, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, a pattern formation method is disclosed. The method can form a patterning film on a substrate. The method can transfer a form pattern provided on a template onto an imprint material by bringing the template into contact with the imprint material. The imprint material is coated on the patterning film. In addition, the method can perform patterning including etching the patterning film using the imprint material including the transferred form pattern as a mask. The transferring is implemented using a condition determined based on data relating to at least one selected from a dimension and a shape of a pattern of the patterning film after the patterning. | 05-12-2011 |
20110130001 | Substrate Processing Apparatus - A substrate processing apparatus cleaning method that includes: containing a cleaning gas in a reaction tube without generating a gas flow of the cleaning gas in the reaction tube by supplying the cleaning gas into the reaction tube and by completely stopping exhaustion of the cleaning gas from the reaction tube or by exhausting the cleaning gas at an exhausting rate which substantially does not affect uniform diffusion of the cleaning gas in the reaction tube from at a point of time of a period from a predetermined point of time before the cleaning gas is supplied into the reaction tube to a point of time when several seconds are elapsed after starting of supply of the cleaning gas into the reaction tube; and thereafter exhausting the cleaning gas from the reaction tube. | 06-02-2011 |
20110151669 | Release Accumulative Charges by Tuning ESC Voltages in Via-Etchers - A method of forming an integrated circuit structure on a wafer includes providing a first etcher comprising a first electrostatic chuck (ESC); placing the wafer on the first ESC; and forming a via opening in the wafer using the first etcher. After the step of forming the via opening, a first reverse de-chuck voltage is applied to the first ESC to release the wafer. The method further includes placing the wafer on a second ESC of a second etcher; and performing an etching step to form an additional opening in the wafer using the second etcher. After the step of forming the additional opening, a second reverse de-chuck voltage is applied to the second ESC to release the wafer. The second reverse de-chuck voltage is different from the first reverse de-chuck voltage. | 06-23-2011 |
20110159691 | METHOD FOR FABRICATING FINE PATTERNS OF SEMICONDUCTOR DEVICE UTILIZING SELF-ALIGNED DOUBLE PATTERNING - A method for making a semiconductor device includes forming a first mask pattern on a device layer, forming a second mask pattern on the first mask pattern, etching the device layer not covered by the first and second mask patterns to thereby form a first trench, trimming the first mask pattern to form an intermediate mask pattern, depositing a material layer to fill the first trench, polishing the material layer to expose a top surface of the intermediate mask pattern, removing the intermediate mask pattern to form an opening, etching the device layer through the opening to thereby form a second trench. | 06-30-2011 |
20110171830 | SUBSTRATE PROCESSING METHOD, SYSTEM AND PROGRAM - A substrate processing method is used for a substrate processing system having a substrate processing device and a substrate transfer device. The substrate processing method includes a substrate transfer step of transferring a substrate and a substrate processing step of performing a predetermined process on the substrate. The substrate transfer step and the substrate processing step include a plurality of operations, and at least two operations among the plurality of the operations are performed simultaneously. Preferably, the substrate processing device includes an accommodating chamber, a mounting table placed in the accommodating chamber to be mounted thereon the substrate, and a heat transfer gas supply line for supplying a heat transfer gas to a space between the substrate mounted on the mounting table and the mounting table. | 07-14-2011 |
20110237077 | METHOD OF PRODUCING MICROSTRUCTURE OF NITRIDE SEMICONDUCTOR AND PHOTONIC CRYSTAL PREPARED ACCORDING TO THE METHOD - The method of producing a GaN-based microstructure includes a step of preparing a semiconductor structure provided with a trench formed in a main surface of the nitride semiconductor and a heat-treating mask covering a main surface of the nitride semiconductor excluding the trench, a first heat-treatment step of heat-treating the semiconductor structure under an atmosphere containing nitrogen element to form a crystallographic face of the nitride semiconductor on at least a part of a sidewall of the trench, a step of removing the heat-treating mask after the first heat-treatment step and a second heat-treatment step of heat-treating the semiconductor structure under an atmosphere containing nitrogen element to close an upper portion of the trench on the sidewall of which the crystallographic face is formed with a nitride semiconductor. | 09-29-2011 |
20110263125 | METHOD OF FORMING MARK IN IC-FABRICATING PROCESS - A method of forming a mark in an IC fabricating process is described. Two parts of the mark each including a plurality of linear patterns are respectively defined by two exposure steps that either belong to two lithography processes respectively or constitute a double-exposure process including X-dipole and Y-dipole exposure steps. | 10-27-2011 |
20110287630 | Methods of Processing Semiconductor Substrates In Forming Scribe Line Alignment Marks - A method of processing a semiconductor substrate in forming scribe line alignment marks includes forming pitch multiplied non-circuitry features within scribe line area of a semiconductor substrate. Individual of the features, in cross-section, have a maximum width which is less than a minimum photolithographic feature dimension used in lithographically patterning the substrate. Photoresist is deposited over the features. Such is patterned to form photoresist blocks that are individually received between a respective pair of the features in the cross-section. Individual of the features of the respective pairs have a laterally innermost sidewall in the cross-section. Individual of the photoresist blocks have an opposing pair of first pattern edges in the cross-section that are spaced laterally inward of the laterally innermost sidewalls of the respective pair of the features. Individual of the photoresist blocks have an opposing pair of second pattern edges in the cross-section that self-align laterally outward of the first pattern edges to the laterally innermost sidewalls of the features during the patterning. | 11-24-2011 |
20110318926 | Wiring structure, semiconductor device and manufacturing method thereof - A semiconductor device manufacturing method for manufacturing a semiconductor device having a transistor mounted in a wiring of a plural-layer structure includes in manufacturing the semiconductor device that is formed on a semiconductor element and includes a barrier insulating film, a porous interlayer insulating film, a wiring, a via plug formed by embedding a metal wiring material in a wiring trench, and a via hole formed in the porous interlayer insulating film, irradiating an electron beam or an ultraviolet ray onto at least a portion of the porous interlayer insulating film before forming an opening in the barrier insulating film. | 12-29-2011 |
20120034778 | Double Patterning Strategy for Contact Hole and Trench in Photolithography - A method of lithography patterning includes forming a first resist pattern on a substrate, the first resist pattern including a plurality of openings therein on the substrate; forming a second resist pattern on the substrate and within the plurality of openings of the first resist pattern, the second resist pattern including at least one opening therein on the substrate; and removing the first resist pattern to uncover the substrate underlying the first resist pattern. | 02-09-2012 |
20120034779 | APPARATUS FOR MANUFACTURING A SEMICONDUCTOR DEVICE - In a semiconductor device manufacturing method, an etching mask ( | 02-09-2012 |
20120070988 | METHODS AND APPARATUSES FACILITATING FLUID FLOW INTO VIA HOLES, VENTS, AND OTHER OPENINGS COMMUNICATING WITH SURFACES OF SUBSTRATES OF SEMICONDUCTOR DEVICE COMPONENTS - A method for removing material from surfaces of at least a portion of at least one recess or at least one aperture extending into a surface of a substrate includes pressurizing fluid so as to cause the fluid to flow into the at least one recess or at least one aperture. The fluid may be pressurized by generating a pressure differential across the substrate, which causes the fluid to flow into or through the at least one aperture or recess. Apparatus for pressurizing fluid so as to cause it to flow into or through recesses or apertures in a substrate are also disclosed. | 03-22-2012 |
20120083120 | SUBSTRATE PROCESSING APPARATUS AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A substrate processing apparatus includes a processing chamber in which a substrate is processed, a substrate holder configured to be loaded into and unloaded from the processing chamber while holding the substrate, a transfer chamber in which a charging operation for causing the substrate holder to hold an unprocessed substrate and a discharging operation for taking out a processed substrate from the substrate holder are performed, and a cleaning unit configured to blow clean air into the transfer chamber. The transfer chamber has a polygonal plan-view shape and includes corner areas. The cleaning unit is arranged in one of the corner areas of the transfer chamber. | 04-05-2012 |
20120108063 | BEAM DOSE COMPUTING METHOD AND WRITING METHOD AND RECORD CARRIER BODY AND WRITING APPARATUS - A beam dose computing method includes dividing a surface area of a target object into include first, second and third regions of different sizes, the third regions being less in size than the first and second regions, determining first corrected doses of a charged particle beam for correcting fogging effects in the first regions, determining corrected size values for correcting pattern line width deviations occurring due to loading effects in the second regions to create a map of base doses of the beam in respective of said second regions and to prepare a map of proximity effect correction coefficients in respective of said second regions, using the maps to determine second corrected doses of the beam for proximity effect correction in the third regions, and using the first and second corrected doses to determine an actual beam dose at each position on the surface of said object. | 05-03-2012 |
20120108064 | POLISHING COMPOSITION FOR SILICON WAFERS - A polishing composition for a silicon wafer includes a macromolecular compound, an abrasive, and an aqueous medium. The macromolecular compound includes a constitutional unit (a1) represented by the following general formula (1), a constitutional unit (a2) represented by the following general formula (2), and a constitutional unit (a3) represented by the following general formula (3). The total of the constitutional unit (a3) is 0.001 to 1.5 mol % of all the constitutional units of the macromolecular compound. | 05-03-2012 |
20120135602 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device having a cooling mechanism comprises a modified region forming step of converging a laser light at a sheet-like object to be processed made of silicon so as to form a modified region within the object along a line to form a modified region, an etching step of anisotropically etching the object after the modified region forming step so as to advance the etching selectively along the first modified region and form a flow path for circulating a coolant as a cooling mechanism within the object, and a functional device forming step of forming a functional device on one main face side of the object. | 05-31-2012 |
20120149196 | METHOD FOR ETCHING A MATERIAL IN THE PRESENCE OF SOLID PARTICLES - The invention relates to a method for etching a structure ( | 06-14-2012 |
20120156876 | SELF-ALIGNED NAND FLASH SELECT-GATE WORDLINES FOR SPACER DOUBLE PATTERNING - A method for double patterning is disclosed. In one embodiment the formation a pair of select gate wordlines on either side of a plurality of core wordlines begins by placing a spacer pattern around edges of a photoresist pattern is disclosed. The photoresist pattern is stripped away leaving the spacer pattern. A trim mask is placed over a portion of the spacer pattern. Portions of the spacer pattern are etched away that are not covered by the trim mask. The trim mask is removed, wherein first remaining portions of the spacer pattern define a plurality of core wordlines. A pad mask is placed such that the pad mask and second remaining portions of the spacer pattern define a select gate wordline on either side of the plurality of core wordlines. Finally at least one pattern transfer layer is etched through using the mad mask and the first and second remaining portions of the spacer pattern to etch the select gate wordlines and the plurality of core wordlines into a poly silicon layer. | 06-21-2012 |
20120156877 | Showerhead for Processing Chamber - A top assembly for a processing chamber having a back plate and a hub is provided. The back plate has a first portion and a second portion. The first portion is connected to the second portion through a central region of the back plate, wherein a gap is defined between opposing surfaces of the first and second portions outside the central region. The first portion includes an embedded heating element. The hub is affixed to a top surface of the second portion of the back plate over the central region. The hub has a top surface with a plurality of channel openings defined within a central region of the hub and a bottom surface having a central extension with a plurality of channels defined therethrough. The bottom surface includes an annular extension spaced apart from the central extension. | 06-21-2012 |
20120190197 | MASK PLATE, PATTENING METHOD AND METHOD FOR MANUFACTURING ARRAY SUBSTRATE - An embodiment of the disclosed technology provides a mask plate for photolithography process comprising a first pattern region, a second pattern region having a different exposure level from that of the first pattern region, and a redundant pattern provided between the first pattern region and the second pattern region, wherein the redundant pattern is configured for forming a redundant photoresist pattern so as to prevent developer diffusion at different concentrations across the photoresist redundant pattern. | 07-26-2012 |
20120270397 | Photomask and Method for Fabricating Source/Drain Electrode of Thin Film Transistor - A method is provided for fabricating source/drain electrodes of a thin film transistor. The method generally provides a substrate having a first gate electrode and a second gate electrode adjacent and electrically connected. The method further provides coating a photoresist layer on the metal layer, and performing an exposure process on the photoresist layer by a photomask. The method further performs a development process on the exposed photoresist layer to form a photoresist pattern layer with different thicknesses on the metal layer, and then etches the metal layer using the photoresist pattern layer as an etch mask, to form a pair of first source/drain electrodes on the first gate electrode and a pair of second source/drain electrodes on the second gate electrode. | 10-25-2012 |
20120276741 | BENIGN, LIQUID CHEMICAL SYSTEM-BASED BACK END OF LINE (BEOL) CLEANING - A back end of line cleaning process is performed using a liquid mixture containing at least two benign chemicals that can form a eutectic. In one embodiment, liquid mixtures of urea and choline chloride, at a molar ratio of 2:1, in the temperature range of 40° C. to 70° C. are used to remove etch residues on copper interconnects and dielectric layers created by g-line and DUV resists. In certain embodiments, eutectic, hypereutectic, and hypoeutectic compositions of the at least two benign chemicals are used. | 11-01-2012 |
20120282773 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - In one embodiment, a method of manufacturing a semiconductor device includes forming a conductive film whose upper surface and side surface are exposed and an insulation film whose upper surface is exposed, on a semiconductor substrate. The method further includes supplying oxidizing ions or nitriding ions contained in plasma generated by a microwave, a radio-frequency wave, or electron cyclotron resonance to the exposed side surface of the conductive film and the exposed upper surface of the insulation film, by applying a predetermined voltage to the semiconductor substrate, thereby performing anisotropic oxidation or anisotropic nitridation of the exposed side surface of the conductive film and the exposed upper surface of the insulation film. | 11-08-2012 |
20120282774 | Patterning Methods and Masks - Masks for patterning material layers of semiconductor devices, methods of patterning and methods of manufacturing semiconductor devices, and lithography systems are disclosed. A lithography mask includes a pattern of alternating lines and spaces, wherein the lines and spaces comprise different widths. When the lithography mask is used to pattern a material layer of a semiconductor device, the pattern of the material layer comprises alternating lines and spaces having substantially the same width. | 11-08-2012 |
20120322263 | METHODS OF ETCHING SINGLE CRYSTAL SILICON - A single crystal silicon etching method includes providing a single crystal silicon substrate having at least one trench therein. The substrate is exposed to a buffered fluoride etch solution which undercuts the silicon to provide lateral shelves when patterned in the <100> direction. The resulting structure includes an undercut feature when patterned in the <100> direction. | 12-20-2012 |
20130012023 | METHOD OF FORMING MICROPATTERN, METHOD OF FORMING DAMASCENE METALLIZATION, AND SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MEMORY DEVICE FABRICATED USING THE SAME - According to example embodiments, a method of forming micropatterns includes forming dummy patterns having first widths on a dummy region of a substrate, and forming cell patterns having second widths on an active line region of the substrate. The active line region may be adjacent to the dummy region and the second widths may be less than the first widths. The method may further include forming damascene metallization by forming a seed layer on the active line region and the dummy region, forming a conductive material layer on a whole surface of the substrate, and planarizing the conductive material layer to form metal lines. | 01-10-2013 |
20130012024 | STRUCTURE FOR MICROELECTRONICS AND MICROSYSTEM AND MANUFACTURING PROCESS - A process for making cavities in a multilayer structure by providing a multilayer structure that includes a surface layer, a planar support substrate and a buried layer between the layer and the support substrate, wherein the buried layer comprises areas of first and second materials with the first material having a higher etching rate than the second material; producing an opening in the surface layer that extends to the area(s) of the first material of the buried layer; and etching the first material to form at least one cavity in the buried layer. | 01-10-2013 |
20130023120 | METHOD OF FORMING MASK PATTERN AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of forming a mask pattern includes a first pattern forming step of etching an anti-reflection coating film by using as a mask a first line portion made up of a photo resist film formed on the anti-reflection film to form a pattern including a second line portion made up of the photo resist film and the anti-reflection film; an irradiation step of irradiating the photo resist film with electrons; a silicon oxide film forming step to cover the second line portion isotropically; and an etch back step of etching back the silicon oxide film such that the silicon oxide film is removed from the top of the second line portion as sidewalls of the second line portion. The method further includes a second pattern forming step of ashing the second line portion to form a mask pattern including a third line portion made up of the silicon oxide film and remains. | 01-24-2013 |
20130059438 | METHOD FOR FORMING PATTERN AND MASK PATTERN, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A pattern formation method, mask pattern formation method and a method for manufacturing semiconductor devices are provided in this disclosure, which are directed to the field of semiconductor processes. The pattern formation method comprises: providing a substrate; forming a polymer thin film containing a block copolymer on the substrate; forming a first pattern through imprinting the polymer thin film with a stamp; forming domains composed of different copolymer components through directed self assembly of the copolymer in the first pattern; selectively removing the domains composed of copolymer components to form a second pattern. In the embodiments of the present invention, finer pitch patterns can be obtained through combining the imprinting and DSA process without exposure, which as compared to the prior art methods has the advantage of simplicity. Furthermore, stamps used in imprinting may have relative larger pitches, facilitating and simplifying the manufacture and alignment of the stamps. | 03-07-2013 |
20130078809 | SILICON NITRIDE ETCHING IN A SINGLE WAFER APPARATUS - A single wafer etching apparatus and various methods implemented in the single wafer etching apparatus are disclosed. In an example, etching a silicon nitride layer in a single wafer etching apparatus includes: heating a phosphoric acid to a first temperature; heating a sulfuric acid to a second temperature; mixing the heated phosphoric acid and the heated sulfuric acid; heating the phosphoric acid/sulfuric acid mixture to a third temperature; and etching the silicon nitride layer with the heated phosphoric acid/sulfuric acid mixture. | 03-28-2013 |
20130130499 | SUBSTRATE PROCESSING METHOD AND SUBSTRATE PROCESSING APPARATUS - A substrate processing method for removing an Si-based film on a surface of a substrate accommodated in a processing chamber includes a first step in which the Si-based film on the surface of the substrate is transformed into a reaction product by a gas containing a halogen element and an alkaline gas in the processing chamber and a second step in which the reaction product is vaporized in the processing chamber which is depressurized to a pressure lower than a pressure during the first step. The first step and the second step are repeated two or more times. | 05-23-2013 |
20130130500 | COMPOSITION FOR REMOVAL OF NICKEL-PLATINUM ALLOY-BASED METALS - A composition for the removal of nickel-platinum alloy metal, said composition being characterised by including 3-55 mass % of at least one kind selected from the group consisting of hydrochloric acid, hydrobromic acid, and nitric acid, 0.5-20 mass % of a chelating agent other than oxalic acid, 0.1-4 mass % of an anionic surfactant, and water; and also characterised by not including fluorine-containing compounds or hydrogen peroxide, and having a pH of 1 or less. Nickel-platinum alloy metal can be selectively removed without damaging silicon substrate material. | 05-23-2013 |
20130143403 | TEXTURE-ETCHANT COMPOSITION FOR CRYSTALLINE SILICON WAFER AND METHOD FOR TEXTURE-ETCHING (1) - Disclosed herein is an etching composition for texturing a crystalline silicon wafer, comprising, based on a total amount of the composition: (A) 0.1 to 20 wt % of an alkaline compound; (B) 0.1 to 50 wt % of a cyclic compound having a boiling point of 100° C. or more; (C) 0.00001 to 10 wt % of a silica-containing compound; and (D) residual water. The etching composition can maximize the absorbance of light of the surface of a crystalline silicon wafer. | 06-06-2013 |
20130157463 | NEAR-INFRARED ABSORBING FILM COMPOSITION FOR LITHOGRAPHIC APPLICATION - The present invention relates to a near-infrared (NIR) film composition for use in vertical alignment and correction in the patterning of integrated semiconductor wafers and a pattern forming method using the composition. The NIR absorbing film composition includes a NIR absorbing dye having a polymethine cation and a crosslinkable anion, a crosslinkable polymer and a crosslinking agent. The patterning forming method includes aligning and focusing a focal plane position of a photoresist layer by sensing near-infrared emissions reflected from a substrate containing the photoresist layer and a NIR absorbing layer formed from the NIR absorbing film composition under the photoresist layer. The NIR absorbing film composition and the pattern forming method are especially useful for forming material patterns on a semiconductor substrate having complex buried topography. | 06-20-2013 |
20130203253 | METHOD OF FORMING PATTERN AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - In a method of forming a pattern according to an embodiment, a first oblique linear pattern arranged at a first oblique angle with respect to a first parallel linear pattern and a second oblique linear pattern arranged at a second oblique angle with respect to the first parallel linear pattern are formed. Then, a pattern is formed in a region in which the first oblique linear pattern overlaps the second oblique linear pattern. A second parallel linear pattern is formed using the first parallel linear pattern and the pattern such that the second parallel linear pattern is divided by the overlap region. At least one of the first and second oblique angles is an angle other than a right angle. | 08-08-2013 |
20130217228 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - According to one embodiment, a method for fabricating a semiconductor device includes performing a back surface processing to remove at least one of a scratch and a foreign material formed on a back surface of a substrate to be processed, a front surface of the substrate being retained in a non-contact state, contacting the back surface of the substrate to a stage to be retained, and providing a pattern on the front surface of the substrate by using lithography. | 08-22-2013 |
20130224953 | ABATEMENT AND STRIP PROCESS CHAMBER IN A LOAD LOCK CONFIGURATION - Embodiments of the present invention a load lock chamber including two or more isolated chamber volumes, wherein one chamber volume is configured for processing a substrate and another chamber volume is configured to provide cooling to a substrate. One embodiment of the present invention provides a load lock chamber having at least two isolated chamber volumes formed in a chamber body assembly. The at least two isolated chamber volumes may be vertically stacked. A first chamber volume may be used to process a substrate disposed therein using reactive species. A second chamber volume may include a cooled substrate support. | 08-29-2013 |
20130237058 | GAS SUPPLY DEVICE, SUBSTRATE PROCESSING APPARATUS AND SUBSTRATE PROCESSING METHOD - A gas supply mechanism includes a gas introduction member having gas inlet portions through which a gas is introduced into a processing chamber, a processing gas supply unit, a processing gas supply path, branch paths, an additional gas supply unit and an additional gas supply path. The gas inlet portions includes inner gas inlet portions for supplying the gas toward a region where a target substrate is positioned in the chamber and an outer gas inlet portion for introducing the gas toward a region outside an outermost periphery of the target substrate. The branch paths are connected to the inner gas inlet portions, and the additional gas supply path is connected to the outer gas inlet portion. | 09-12-2013 |
20130244427 | METHODS OF MAKING JOGGED LAYOUT ROUTINGS DOUBLE PATTERNING COMPLIANT - One illustrative method disclosed herein involves creating an overall target pattern that includes an odd-jogged feature with a crossover region that connects first and second line portions, wherein the crossover region has a first dimension in a first direction that is greater than a second dimension that is transverse to the first direction, decomposing the overall target pattern into a first sub-target pattern and a second sub-target pattern, wherein each of the sub-target patterns comprise a line portion and a first portion of the crossover region, and generating first and second sets of mask data corresponding to the first and second sub-target patterns, respectively. | 09-19-2013 |
20130244428 | METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE - In a method for manufacturing a silicon carbide semiconductor device, a conductive layer is formed on a silicon carbide layer. The silicon carbide layer and the conductive layer react with each other thus forming an alloy layer formed of a reaction layer in contact with the silicon carbide layer and a silicide layer on the reaction layer. A carbon component is removed from the silicide layer. A portion of the silicide layer is removed using an acid thus exposing at least a portion of the reaction layer. An electrode layer is formed on an upper side of the exposed reaction layer. | 09-19-2013 |
20130252424 | WAFER HOLDER WITH TAPERED REGION - An apparatus, a system and a method are disclosed. An exemplary apparatus includes a wafer holder including a first portion and a second portion. The first and second portions are formed of the same continuous material. The first portion includes a first upper surface and a first lower surface, and the second portion including a second upper surface and a second lower surface. The apparatus further includes an interface between the first and second portions. The interface provides for a transition such that the first upper surface of the first portion tends toward the second upper surface of the second portion. The apparatus further includes a tapered region formed in the first portion. The tapered region starts at a radial distance from a center line of the wafer holder and terminates at the interface. The tapered region has an initial thickness that gradually decreases to a final thickness. | 09-26-2013 |
20130273738 | MASK BLANK, METHOD OF MANUFACTURING THE SAME, TRANSFER MASK, AND METHOD OF MANUFACTURING THE SAME - Provided is a method of manufacturing a mask blank that is improved in cleaning resistance to ozone cleaning or the like, thus capable of preventing degradation of the mask performance due to the cleaning. The method is for manufacturing a mask blank having, on a substrate, a thin film which is formed at its surface with an antireflection layer made of a material containing a transition metal, and carries out a treatment of causing a highly concentrated ozone gas with a concentration of 50 to 100 vol % to act on the antireflection layer to thereby form a surface modified layer comprising a strong oxide film containing an oxide of the transition metal at a surface of the antireflection layer. | 10-17-2013 |
20130309867 | LATERAL SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR THE SAME - A manufacturing method for manufacturing a lateral semiconductor device having an SOI (Silicon on Insulator) substrate, the lateral semiconductor device comprising a semiconductor layer that includes a buried oxide layer and a drift region, the manufacturing method comprising an etching process of etching, by a predetermined depth, a LOCOS oxide that projects from a surface of the semiconductor layer by a predetermined thickness and is embedded in the semiconductor layer by a predetermined thickness, and a trench forming process of simultaneously forming a first trench extending from the drift region toward the buried oxide layer, and a second trench extending from a portion obtained by the etching in the etching process toward the buried oxide layer, at a same etching rate, and stopping forming the first trench and the second trench at a time when the second trench reaches the buried oxide layer. | 11-21-2013 |
20130316536 | SEMICONDUCTOR MANUFACTURING DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor manufacturing apparatus according to an embodiment includes a stage capable of mounting a semiconductor substrate thereon, a first irradiation part configured to irradiate an etching beam onto the semiconductor substrate from a first direction inclined at an arbitrary angle with respect to a vertical direction to a surface of the semiconductor substrate, and a second irradiation part configured to irradiate an etching beam onto the semiconductor substrate from a second direction inclined at an arbitrary angle with respect to the vertical direction. The first and second irradiation parts simultaneously irradiate the etching beams when processing the semiconductor substrate or a material on the semiconductor substrate. | 11-28-2013 |
20130316537 | SELF-ALIGNED NAND FLASH SELECT-GATE WORDLINES FOR SPACER DOUBLE PATTERNING - A method for double patterning is disclosed. In one embodiment the formation a pair of select gate wordlines on either side of a plurality of core wordlines begins by placing a spacer pattern around edges of a photoresist pattern is disclosed. The photoresist pattern is stripped away leaving the spacer pattern. A trim mask is placed over a portion of the spacer pattern. Portions of the spacer pattern are etched away that are not covered by the trim mask. The trim mask is removed, wherein first remaining portions of the spacer pattern define a plurality of core wordlines. A pad mask is placed such that the pad mask and second remaining portions of the spacer pattern define a select gate wordline on either side of the plurality of core wordlines. Finally at least one pattern transfer layer is etched through using the mad mask and the first and second remaining portions of the spacer pattern to etch the select gate wordlines and the plurality of core wordlines into a poly silicon layer. | 11-28-2013 |
20140004701 | TEXTURING OF MONOCRYSTALLINE SEMICONDUCTOR SUBSTRATES TO REDUCE INCIDENT LIGHT REFLECTANCE | 01-02-2014 |
20140004702 | HEATING PLATE WITH PLANAR HEATER ZONES FOR SEMICONDUCTOR PROCESSING | 01-02-2014 |
20140024215 | DOUBLE PATTERNING METHOD - Disclosed is an improved double patterning method for forming openings (e.g., vias or trenches) or mesas on a substrate. This method avoids the wafer topography effects seen in prior art double patterning techniques by ensuring that the substrate itself is only subjected to a single etch process. Specifically, in the method, a first mask layer is formed on the substrate and processed such that it has a doped region and multiple undoped regions within the doped region. Then, either the undoped regions or the doped region can be selectively removed in order to form a mask pattern above the substrate. Once the mask pattern is formed, an etch process can be performed to transfer the mask pattern into the substrate. Depending upon whether the undoped regions are removed or the doped region is removed, the mask pattern will form openings (e.g., vias or trenches) or mesas, respectively, on the substrate. | 01-23-2014 |
20140038412 | INTERCONNECT FORMATION USING A SIDEWALL MASK LAYER - Embodiments described herein provide approaches for interconnect formation in a semiconductor device using a sidewall mask layer. Specifically, a sidewall mask layer is deposited on a hard mask in a merged via region of the semiconductor device following removal of a planarization layer previously formed on the hard mask. The sidewall mask layer is conformally deposited on the hard mask, and acts like a sacrificial layer to protect the hard mask during a subsequent via etch. This reduces the via critical dimension (CD) and reduces the CD elongation along the hard mask line direction during the via etch. | 02-06-2014 |
20140051247 | FIN STRUCTURE FORMATION INCLUDING PARTIAL SPACER REMOVAL - A method of forming a semiconductor device includes forming a mandrel on top of a substrate; forming a first spacer adjacent to the mandrel on top of the substrate; forming a cut mask over the first spacer and the mandrel, such that the first spacer is partially exposed by the cut mask; partially removing the partially exposed first spacer; and etching the substrate to form a fin structure corresponding to the partially removed first spacer in the substrate. | 02-20-2014 |
20140051248 | INKJET PRINTABLE ETCH RESIST - The methods involve selectively depositing a resist containing a solid hydrogenated rosin resin and a liquid hydrogenated rosin resin ester as a mixture on a semiconductor followed by etching uncoated portions of the semiconductor and simultaneously inhibiting undercutting of the resist. The etched portions may then be metallized to form current tracks. | 02-20-2014 |
20140057437 | RINSING AGENT FOR LITHOGRAPHY, METHOD FOR FORMING A RESIST PATTERN, AND METHOD FOR PRODUCING A SEMICONDUCTOR DEVICE - To provide a rinsing agent for lithography, which contains C6-C8 straight-chain alkanediol, and water. | 02-27-2014 |
20140087561 | METHOD AND APPARATUS FOR SUBSTRATE TRANSFER AND RADICAL CONFINEMENT - Embodiments of the present invention provide an apparatus for transferring substrates and confining a processing environment in a chamber. One embodiment of the present invention provides a hoop assembly for using a processing chamber. The hoop assembly includes a confinement ring defining a confinement region therein, and three or more lifting fingers attached to the hoop. The three or more lifting fingers are configured to support a substrate outside the inner volume of the confinement ring. | 03-27-2014 |
20140141610 | NON-VOLATILE MEMORY DEVICES INCLUDING VERTICAL NAND STRINGS AND METHODS OF FORMING THE SAME - A NAND based non-volatile memory device can include a plurality of memory cells vertically arranged as a NAND string and a plurality of word line plates each electrically connected to a respective gate of the memory cells in the NAND string. A plurality of word line contacts can each be electrically connected to a respective word line plate, where the plurality of word line contacts are aligned to a bit line direction in the device. | 05-22-2014 |
20140179106 | IN-SITU METAL RESIDUE CLEAN - A method for forming devices in an oxide layer over a substrate, wherein a metal containing layer forms at least either an etch stop layer below the oxide layer or a patterned mask above the oxide layer, wherein a patterned organic mask is above the oxide layer is provided. The substrate is placed in a plasma processing chamber. The oxide layer is etched through the patterned organic mask, wherein metal residue from the metal containing layer forms metal residue on sidewalls of the oxide layer. The patterned organic mask is stripped. The metal residue is cleaned by the steps comprising providing a cleaning gas comprising BCl | 06-26-2014 |
20140187041 | High Dose Ion-Implanted Photoresist Removal Using Organic Solvent and Transition Metal Mixtures - Provided are methods for processing semiconductor substrates to remove high-dose ion implanted (HDI) photoresist structures without damaging other structures made of titanium nitride, tantalum nitride, hafnium oxide, and/or hafnium silicon oxide. The removal is performed using a mixture of an organic solvent, an oxidant, a metal-based catalyst, and one of a base or an acid. Some examples of suitable organic solvents include dimethyl sulfoxide, n-ethyl pyrrolidone, monomethyl ether, and ethyl lactate. Transition metals in their zero-oxidation state, such as metallic iron or metallic chromium, may be used as catalysts in this mixture. In some embodiments, a mixture includes ethyl lactate, of tetra-methyl ammonium hydroxide, and less than 1% by weight of the metal-based catalyst. The etching rate of the HDI photoresist may be at least about 100 Angstroms per minute, while other structures may remain substantially intact. | 07-03-2014 |
20140213054 | EXPOSING METHOD AND METHOD OF FORMING A PATTERN USING THE SAME - An exposing method includes irradiating a first light having a first energy to a first exposed region of a photoresist film through a first shot region of a mask, and irradiating a second light having a second energy to the first exposed region of the photoresist film through a second shot region of the mask. | 07-31-2014 |
20140213055 | SEMICONDUCTOR MANUFACTURING DEVICE AND PROCESSING METHOD - A semiconductor manufacturing device includes a stage, a plurality of pins, and a driving unit. The stage includes a mounting surface. The mounting surface has a first region for mounting thereon a substrate, and a second region for mounting thereon a focus ring. The second region is provided to surround the first region. A plurality of holes is formed in the stage. The holes extend in a direction that intersects the mounting surface while passing through the boundary between the first region and the second region. The pins are provided in the respective holes. Each of the pins has a first and a second upper end surface. The second. upper end surface is provided above the first upper end surface, and is offset towards the first region with respect to the first upper end surface. The driving unit moves the pins up and down in the aforementioned direction. | 07-31-2014 |
20140248773 | PATTERNING METHOD AND METHOD OF FORMING MEMORY DEVICE - A method of forming memory device is provided. A substrate having at least two cell areas and at least one peripheral area between the cell areas is provided. A target layer, a sacrificed layer and a first mask layer having first mask patterns in the cell areas and second mask patterns in the peripheral area are sequentially formed on the substrate. Sacrificed layer is partially removed to form sacrificed patterns by using the first mask layer as a mask. Spacers are formed on sidewalls of the sacrificed patterns. The sacrificed patterns and at least the spacers in the peripheral area are removed. A second mask layer is formed in the cell areas. Target layer is partially removed, using the second mask layer and remaining spacers as a mask, to form word lines in the cell areas and select gates in a portion of cell areas adjacent to the peripheral area. | 09-04-2014 |
20140256132 | METHOD FOR PATTERNING SEMICONDUCTOR STRUCTURE - A method for patterning a semiconductor structure is provided. The method comprises following steps. A first mask defining a first pattern in a first region and a second pattern in a second region adjacent to the first region is provided. The first pattern defined by the first mask is transferred to a first film structure in the first region, and the second pattern defined by the first mask is transferred to the first film structure in the second region. A second film structure is formed on the first film structure. A second mask defining a third pattern in the first region is provided. At least 50% of a part of the first region occupied by the first pattern defined by the first mask is identical with a part of the first region occupied by the third pattern defined by the second mask. | 09-11-2014 |
20140273454 | Wet Cleaning Method for Cleaning Small Pitch Features - A method for reducing contaminants in a semiconductor device is provided. The method includes cleaning the semiconductor substrate. The cleaning includes rotating the semiconductor substrate and dispersing an aerosol at a predetermined temperature to a surface of the semiconductor substrate or a layer formed on the substrate to be cleaned. The aerosol includes a chemical having a predetermined pressure and a gas having a predetermined flow rate. | 09-18-2014 |
20140342557 | METHOD FOR ETCHING A COMPLEX PATTERN - A method for etching a desired complex pattern in a first face of a substrate, including: simultaneous etching of at least a first and a second sub-pattern through the first face of the substrate, the etched sub-patterns being separated by at least one separating wall, a width of the first sub-pattern being greater than a width of the second sub-pattern at the first face, and a depth of the first sub-pattern being greater than a depth of the second sub-pattern in a direction perpendicular to the said first face; and removing or eliminating the separating wall to expose the desired complex pattern. | 11-20-2014 |
20140342558 | SUBSTRATE TREATING APPARATUS WITH SUBSTRATE REORDERING - A treating section has substrate treatment lines arranged one over the other for treating substrates while transporting the substrates substantially horizontally. An IF section transports the substrates fed from each substrate treatment line to an exposing machine provided separately from this apparatus. The substrates are transported to the exposing machine in the order in which the substrates are loaded into the treating section. The throughput of this apparatus can be improved greatly, without increasing the footprint, since the substrate treatment lines are arranged one over the other. Each substrate can be controlled easily since the order of the substrates transported to the exposing machine is in agreement with the order of the substrates loaded into the treating section. | 11-20-2014 |
20150011088 | METHODS AND APPARATUS FOR DEPOSITING AND/OR ETCHING MATERIAL ON A SUBSTRATE - Methods are disclosed for depositing material onto and/or etching material from a substrate in a surface processing tool having a processing chamber, a controller and one or more devices for adjusting the process parameters within the chamber. The method comprises: the controller instructing the one or more devices according to a series of control steps, each control step specifying a defined set of process parameters that the one or more devices are instructed to implement, wherein at least one of the control steps comprises the controller instructing the one or more devices to implement a defined set of constant process parameters for the duration of the step, including at least a chamber pressure and gas flow rate through the chamber, which duration is less than the corresponding gas residence time (T | 01-08-2015 |
20150017805 | WAFER PROCESSING APPARATUS HAVING INDEPENDENTLY ROTATABLE WAFER SUPPORT AND PROCESSING DISH - An apparatus for processing a wafer is disclosed that includes a wafer support and a processing base. The wafer support is configured to support a wafer in a processing position, and to rotate the wafer about a first substantially vertical axis while in the processing position. The processing base includes a shallow dish configured to receive processing chemistry. The wafer support places the wafer in contact with the processing chemistry while in the processing position. The shallow dish is rotatable about a second substantially vertical axis when the wafer support is in the processing position. The rotation of the wafer is independent of the rotation of the shallow dish. Further, the processing base may include a heating element, such as an infrared heating element, that is disposed to locally elevate the temperature of of the shallow dish and chemistry contained in it. | 01-15-2015 |
20150024594 | COOLED PIN LIFTER PADDLE FOR SEMICONDUCTOR SUBSTRATE PROCESSING APPARATUS - A semiconductor substrate processing apparatus includes a cooled pin lifter paddle for raising and lowering a semiconductor substrate. The semiconductor substrate processing apparatus comprises a processing chamber in which the semiconductor substrate is processed, a heated pedestal for supporting the semiconductor substrate in the processing chamber, and the cooled pin lifter paddle located below the pedestal. The cooled pin lifter paddle includes a heat shield and at least one flow passage in an outer peripheral portion thereof through which a coolant can be circulated to remove heat absorbed by the heat shield of the cooled pin lifter paddle. The cooled pin lifter paddle is vertically movable such that lift pins on an upper surface of the heat shield travel through corresponding holes in the pedestal and a source of coolant is in flow communication with the at least one flow passage. | 01-22-2015 |
20150072524 | METHOD OF REPAIRING DEFECT AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, in a method of repairing a defect on a template substrate for imprint lithography using a charged particle beam, a drift correction mark to correct drift of the charged particle beam is formed on the template substrate. The defect on the template substrate is repaired while correcting the drift of the charged particle beam with reference to the drift correction mark. The drift correction mark is removed. | 03-12-2015 |
20150079787 | METHOD AND STRUCTURE FOR CREATING CAVITIES WITH EXTREME ASPECT RATIOS - Embodiments relate to structures, systems and methods for more efficiently and effectively etching sacrificial and other layers in substrates and other structures. In embodiments, a substrate in which a sacrificial layer is to be removed to, e.g., form a cavity comprises an etch dispersion system comprising a trench, channel or other structure in which etch gas or another suitable gas, fluid or substance can flow to penetrate the substrate and remove the sacrificial layer. The trench, channel or other structure can be implemented along with openings or other apertures formed in the substrate, such as proximate one or more edges of the substrate, to even more quickly disperse etch gas or some other substance within the substrate. | 03-19-2015 |
20150309412 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE, PATTERN WRITING APPARATUS, RECORDING MEDIUM RECORDING PROGRAM, AND PATTERN TRANSFER APPARATUS - A method for fabricating a semiconductor device, includes dividing a pattern region of a desired pattern that is to be formed on a semiconductor substrate into a plurality of sub-regions; calculating combination condition including a shape of illumination light for transferring and a mask pattern obtained by correcting a partial pattern in the sub-region of the desired pattern formed on a mask used during transferring for each of the plurality of sub-regions, to make a dimension error of the partial pattern of each of the plurality of sub-regions smaller when transferred to the semiconductor substrate; and forming the desired pattern by making multiple exposures on the semiconductor substrate in such a way that the partial patterns of the sub-regions divided are sequentially transferred by transferring a pattern to the semiconductor substrate using the combination conditions calculated for each of the sub-regions. | 10-29-2015 |
20160020112 | APPARATUS AND METHOD FOR ETCHING SUBSTRATE, STAMP FOR ETCHING SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME - The inventive concepts relate to an apparatus and a method for etching a substrate, a stamp for etching a substrate, and a method for manufacturing the stamp. The method for etching a substrate includes bringing a substrate into contact with a stamp including a pattern on which a metal catalyst is formed, and etching the substrate by a chemical reaction between the metal catalyst and an etching solution. | 01-21-2016 |
20160079060 | Patterning of Nanostructures - A technique for forming nanostructures including introducing a plurality of molecular-size scale and/or nanoscale building blocks to a region near a substrate and simultaneously scanning a pattern on the substrate with an energy beam, wherein the energy beam causes a change in at least one physical property of at least a portion of the building blocks, such that a probability of the portion of the building blocks adhering to the pattern scanned by the energy beam is increased, and wherein the building blocks adhere to the pattern to form the structure. The energy beam and at least a portion of the building blocks may interact by electrostatic interaction to form the structure. | 03-17-2016 |
20160079100 | VACUUM CARRIER INTERFACE HAVING A SWITCHABLE REDUCED CAPACITY AIRLOCK CHAMBER - A vacuum carrier interface configured to interface with a transfer module, the vacuum carrier interface including an input interface configured to receive one or more substrates at atmospheric pressure; a substrate handling manifold configured to receive the one or more substrates from the input interface at atmospheric pressure and interface with the transfer module in a vacuum; an output interface configured to deliver one or more substrates to the transfer module from the substrate handling manifold; a vacuum manifold base plate and a lower pedestal, which are spaced apart, the vacuum manifold base plate and the lower pedestal forming a chamber between a lower surface of the vacuum manifold base plate and an upper surface of the lower pedestal; and an indexer configured to raise and lower the vacuum manifold base plate and the lower pedestal. | 03-17-2016 |
20160099171 | DIMENSION-CONTROLLED VIA FORMATION PROCESSING - Methods are provided for dimension-controlled via formation over a circuit structure, including over multiple adjacent conductive structures. The method(s) includes, for instance, providing a patterned multi-layer stack structure above the circuit structure, the stack structure including at least one layer, and a pattern transfer layer above the at least one layer, the pattern transfer layer being patterned with at least one via opening; providing a sidewall spacer layer within the at least one via opening to form at least one dimension-controlled via opening; and etching through the at least one layer of the stack structure using the at least one dimension-controlled via opening to facilitate providing the via(s) over the circuit structure. In one implementation, the stack structure includes a trench-opening within a patterned hard mask layer disposed between a dielectric layer and a planarization layer, and the via(s) is partially self-aligned to the trench. | 04-07-2016 |
20190148156 | PHOTO MASK AND METHOD OF MANUFACTURING SEMICONDUCTOR ELEMENT USING PHOTO MASK | 05-16-2019 |
20190148158 | ETCHING AND STRUCTURES FORMED THEREBY | 05-16-2019 |
20190148159 | Etching and Structures Formed Thereby | 05-16-2019 |