Class / Patent application number | Description | Number of patent applications / Date published |
438682000 | Silicide | 35 |
20080214002 | Cleaning solution and manufacturing method for semiconductor device - A method of manufacturing a semiconductor device forms an interlayer insulating film on a nickel silicide layer formed on a substrate, and forms a through hole by performing dry etching using a resist pattern, formed on the interlayer insulating film, as a mask and then removing the resist pattern by ashing. A wafer after an ashing process is cleaned using a cleaning solution comprised of aqueous solution having a content of the fluorine-containing compound of 1.0 to 5.0 mass %, a content of chelating agent of 0.2 to 5.0 mass %, and a content of the organic acid salt of 0.1 to 3.0 mass %. | 09-04-2008 |
20080293246 | VERTICAL FET WITH NANOWIRE CHANNELS AND A SILICIDED BOTTOM CONTACT - A vertical FET structure with nanowire forming the FET channels is disclosed. The nanowires are formed over a conductive silicide layer. The nanowires are gated by a surrounding gate. Top and bottom insulator plugs function as gate spacers and reduce the gate-source and gate-drain capacitance. | 11-27-2008 |
20080311747 | METAL-GERMANIUM PHYSICAL VAPOR DEPOSITION FOR SEMICONDUCTOR DEVICE DEFECT REDUCTION - The present invention provides a method of manufacturing a metal silicide electrode ( | 12-18-2008 |
20090011596 | ELECTRONIC DEVICE AND MANUFACTURING METHOD THEREOF - An electronic device includes an element group which generates a specific identification number and is composed of a plurality of elements. The specific identification number is set based on irregular deviation in electric characteristic of the elements which is caused due to a random failure in a manufacturing process. | 01-08-2009 |
20090029549 | METHOD OF SILICIDE FORMATION FOR NANO STRUCTURES - A method forms a first layer over a second layer that comprises silicon. A mask is formed and patterned over the insulator layer. Then, a heavy inert gas such as Xenon (Xe) is implanted through the openings in the mask, through the insulator layer, and into the regions of the silicon layer that are below the opening in the mask. The portions of the insulator layer that are below the openings in the mask are etched away and the mask is removed. A metal or metal alloy layer is formed over the first layer and the exposed regions of the second layer. At least the second layer is heated in a silicide process such that the metal and the exposed regions of the second layer combine to form silicide regions. After this, any remaining metal material can be removed to remove to leave the silicide regions adjacent non-silicide regions of the second layer. | 01-29-2009 |
20090081869 | Process for producing silicon compound - A process for producing a silicon compound can minimize the number of steps and can form a desired compound in a low-temperature environment. The process comprises: allowing a radical of a halogen gas to act on a member | 03-26-2009 |
20090111265 | SELECTIVE SILICIDE FORMATION USING RESIST ETCHBACK - Methods of selectively forming metal silicides on a memory device are provided. The methods can include forming a mask layer over the memory device; forming a patterned resist over the mask layer; removing upper portions of the patterned resist; forming a patterned mask layer by removing portions of the mask layer that are not covered by the patterned resist; and forming metal silicides on the memory device by a chemical reaction of a metal layer formed on the memory device with portions of the memory device that are not covered by the patterned mask layer. By preventing silicidation of underlying silicon containing layers/components of the memory device that are covered by the patterned mask layer, the methods can selectively form the metal silicides on the desired portions of the memory device. | 04-30-2009 |
20100075499 | METHOD AND APPARATUS FOR METAL SILICIDE FORMATION - Embodiments described herein include methods of forming metal silicide layers using a diffusionless annealing process. In one embodiment a method for forming a metal silicide material on a substrate is provided. The method comprises depositing a metal material over a silicon containing surface of a substrate, depositing a metal nitride material over the metal material, depositing a metallic contact material over the metal nitride material, and exposing the substrate to a diffusionless annealing process to form a metal silicide material. The short time-frame of the diffusionless annealing process reduces the time for the diffusion of nitrogen to the silicon containing interface to form silicon nitride thus minimizing the interfacial resistance. | 03-25-2010 |
20100144146 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - The step a) of forming a noble metal film or a metal film containing a noble metal on a semiconductor substrate containing silicon or a conductive film containing silicon is performed, the step b) of forming a silicide film containing a noble metal on the semiconductor substrate or the conductive film is performed, after the step a), by performing thermal treatment to the semiconductor substrate, the step c) of activating unreacted part of the noble metal using a first chemical solution is performed after the step b), and the step d) of dissolving the unreacted part of the noble metal activated in the step c) is performed. The step d) is performed within 30 minutes or less after the step c). | 06-10-2010 |
20100267236 | METHOD FOR REDUCING SILICIDE DEFECTS IN INTEGRATED CIRCUITS - A method for forming silicide contacts in integrated circuits (ICs) is described. A spacer pull-back etch is performed during the salicidation process to reduce the stress between the spacer and source/drain silicide contact at the spacer undercut. This prevents the propagation of surface defects into the substrate, thereby minimizing the occurrence of silicide pipe defects. The spacer pull-back etch can be performed after a first annealing step to form the silicide contacts. | 10-21-2010 |
20110104897 | CONTACT CLEAN BY REMOTE PLASMA AND REPAIR OF SILICIDE SURFACE - Embodiments provide methods for treating a metal silicide contact which includes positioning a substrate having an oxide layer disposed on a metal silicide contact surface within a processing chamber, cleaning the metal silicide contact surface to remove the oxide layer while forming a cleaned silicide contact surface during a cleaning process, and exposing the cleaned silicide contact surface to a silicon-containing compound to form a recovered silicide contact surface during a regeneration process. In some examples, the cleaning of the metal silicide contact surface includes cooling the substrate to an initial temperature of less than 65° C., forming reactive species from a gas mixture of ammonia and nitrogen trifluoride by igniting a plasma, exposing the oxide layer to the reactive species to form a thin film, and heating the substrate to about 100° C. or greater to remove the thin film from the substrate while forming the cleaned silicide contact surface. | 05-05-2011 |
20120276740 | METHODS FOR PRECLEANING A SUBSTRATE PRIOR TO METAL SILICIDE FABRICATION PROCESS - Methods for precleaning native oxides or other contaminants from a surface of a substrate prior to forming a metal silicide layer on the substrate. In one embodiment, a method for removing native oxides from a substrate includes transferring a substrate having an oxide layer disposed thereon into a processing chamber, performing a pretreatment process on the substrate by supplying a pretreatment gas mixture into the processing chamber, performing an oxide removal process on the substrate by supplying a cleaning gas mixture into the processing chamber, wherein the cleaning gas mixture includes at least an ammonium gas and a nitrogen trifluoride, and performing a post treatment process on the cleaned substrate by supplying a post treatment gas mixture into the processing chamber | 11-01-2012 |
20120315760 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes providing a substrate having a gate structure, a source region, and a drain region formed thereon, and the gate structure includes a gate insulating layer and a gate electrode. The method also includes forming a first stress layer on the substrate, removing the first stress layer, and forming a second stress layer on the substrate. | 12-13-2012 |
20120315761 | METHOD FOR MANUFACTURING NICKEL SILICIDE NANO-WIRES - A method for making nickel silicide nano-wire, the method includes the following steps. Firstly, a silicon substrate and a growing device, and the growing device including a reacting room are provided. Secondly, a silicon dioxide layer is formed on a surface of the silicon substrate. Thirdly, a titanium layer is formed on the silicon dioxide layer. Fourthly, the silicon substrate is placed into the reacting room, and the reacting room is heated to a temperature of 500˜1000° C. Finally, a plurality of nickel cluster is formed onto the surface of the silicon substrate. | 12-13-2012 |
20130149865 | METHOD AND STRUCTURE FOR DIFFERENTIAL SILICIDE AND RECESSED OR RAISED SOURCE/DRAIN TO IMPROVE FIELD EFFECT TRANSISTOR - A method forms an integrated circuit structure. The method patterns a protective layer over a first-type field effect transistor and removes a stress liner from above a second-type field effect transistors. Then, the method removes a first-type silicide layer from source and drain regions of the second-type field effect transistor, but leaves at least a portion of the first-type silicide layer on the gate conductor of the second-type field effect transistor. The method forms a second-type silicide layer on the gate conductor and the source and drain regions of the second-type field effect transistor. The second-type silicide layer that is formed is different than the first-type silicide layer. For example, the first-type silicide layer and the second-type silicide layer can comprise different materials, different thicknesses, different crystal orientations, and/or different chemical phases, etc. | 06-13-2013 |
20130203252 | ACTIVATION PROCESS TO IMPROVE METAL ADHESION - Native oxide removing and activating solutions containing fluoride ions and organic acids are used in the formation of metal layers on semiconductor wafers. The method may also be used in the formation of silicides and for preparing the metal silicides for additional metal plating and build-up. The solutions and methods may be used in the manufacture of photovoltaic devices and other electronic devices and components. | 08-08-2013 |
20130224952 | Curved Wafer Processing on Method and Apparatus - An apparatus for and a method of forming a semiconductor structure is provided. The apparatus includes a substrate holder that maintains a substrate such that the processing surface is curved, such as a convex or a concave shape. The substrate is held in place using point contacts, a plurality of continuous contacts extending partially around the substrate, and/or a continuous ring extending completely around the substrate. The processing may include, for example, forming source/drain regions, channel regions, silicides, stress memorization layers, or the like. | 08-29-2013 |
20130230986 | ADHESION IMPROVEMENT FOR LOW K DIELECTRICS TO CONDUCTIVE MATERIALS - Methods are provided for processing a substrate for depositing an adhesion layer between a conductive material and a dielectric layer. In one aspect, the invention provides a method for processing a substrate including positioning a substrate having a conductive material disposed thereon, introducing a reducing compound or a silicon based compound, exposing the conductive material to the reducing compound or the silicon based compound, and depositing a silicon carbide layer without breaking vacuum. | 09-05-2013 |
20130295767 | INCREASED TRANSISTOR PERFORMANCE BY IMPLEMENTING AN ADDITIONAL CLEANING PROCESS IN A STRESS LINER APPROACH - When forming sophisticated transistors on the basis of a highly stressed dielectric material formed above a transistor, the stress transfer efficiency may be increased by reducing the size of the spacer structure of the gate electrode structure prior to depositing the highly stressed material. Prior to the deposition of the highly stressed material, an additional cleaning process may be implemented in order to reduce the presence of any metal contaminants, in particular in the vicinity of the gate electrode structure, which would otherwise result in an increased fringing capacitance. | 11-07-2013 |
20130316535 | METHODS OF FORMING SEMICONDUCTOR DEVICES WITH METAL SILICIDE USING PRE-AMORPHIZATION IMPLANTS AND DEVICES SO FORMED - A method of forming a semiconductor device can be provided by forming an opening that exposes a surface of an elevated source/drain region. The size of the opening can be reduced and a pre-amorphization implant (PAI) can be performed into the elevated source/drain region, through the opening, to form an amorphized portion of the elevated source/drain region. A metal-silicide can be formed from a metal and the amorphized portion. | 11-28-2013 |
20140242796 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - To improve a semiconductor device having a nonvolatile memory. a first MISFET, a second MISFET, and a memory cell are formed, and a stopper film made of a silicon oxide film is formed thereover. Then, over the stopper film, a stress application film made of a silicon nitride film is formed, and the stress application film over the second MISFET and the memory cell is removed. Thereafter, heat treatment is performed to apply a stress to the first MISFET. Thus, a SMT is not applied to each of elements, but is applied selectively. This can reduce the degree of degradation of the second MISFET due to H (hydrogen) in the silicon nitride film forming the stress application film. This can also reduce the degree of degradation of the characteristics of the memory cell due to the H (hydrogen) in the silicon nitride film forming the stress application film. | 08-28-2014 |
20140342556 | REUSING ACTIVE AREA MASK FOR TRENCH TRANSFER EXPOSURE - A method of silicide formation in a semiconductor fabrication process is disclosed. An active area (RX) mask is used to form an active silicon area, and is then reused to form a trench transfer (TT) area. A trench block (TB) mask is logically ANDed with the active area (RX) mask to form a trench silicide (TS) region. | 11-20-2014 |
20150024593 | SEMICONDUCTOR DEVICE COMPRISING CAPACITIVE ELEMENT - A semiconductor device production method includes forming a transition metal film, irradiating a surface of the transition metal film with a mono-silane gas to form a silicon-containing transition metal film, and oxidizing the silicon-containing transition metal film by an oxygen plasma treatment, thereby forming a transition metal silicate film. | 01-22-2015 |
20150111381 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE AND COMPUTING SYSTEM FOR IMPLEMENTING THE METHOD - Provided are method of fabricating semiconductor device and computing system for implementing the method. The method of fabricating a semiconductor device includes forming a target layer, forming a first mask on the target layer to expose a first region, subsequently forming a second mask on the target layer to expose a second region separated from the first region in a first direction, subsequently forming a third mask in the exposed first region to divide the first region into a first sub region and a second sub region separated from each other in a second direction intersecting the first direction, and etching the target layer using the first through third masks such that the first and second sub regions and the second region are defined in the target layer. | 04-23-2015 |
20160086779 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SPUTTERING APPARATUS - Reliability of a semiconductor device is improved, and use efficiency of a sputtering apparatus is increased. When depositing thin films over a main surface of a semiconductor wafer using a magnetron sputtering apparatus in which a collimator is installed in a space between the semiconductor wafer and a target installed in a chamber, a region inner than a peripheral part of the collimator is made thinner than the peripheral part. Thus, it becomes possible to suppress deterioration in uniformity of the thin film in a wafer plane, which may occur as the integrated usage of the target increases. | 03-24-2016 |
438683000 | Of refractory group metal (i.e., titanium (Ti), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), molybdenum (Mo), tungsten (W), or alloy thereof) | 10 |
20080254622 | CMOS SILICIDE METAL GATE INTEGRATION - The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal gate that is formed using the integration scheme of the present invention has the same silicide metal phase and substantially the same height, regardless of the dimension of the silicide metal gate. The present invention also provides various methods of forming a CMOS structure having silicided contacts in which the polySi gate heights are substantially the same across the entire surface of a semiconductor structure. | 10-16-2008 |
20080280439 | OPTIMAL CONCENTRATION OF PLATINUM IN A NICKEL FILM TO FORM AND STABILIZE NICKEL MONOSILICIDE IN A MICROELECTRONIC DEVICE - A method of forming a nickel monosilicide layer on silicon-containing features of an electronic device that includes depositing a nickel film over the silicon-containing features. The nickel film is co-deposited with a selected material. The selected material has an atomic percentage in a range of about 10% to 25%. A single anneal step is then applied to the nickel film thus directly forming the nickel monosilicide layer. | 11-13-2008 |
20090298288 | SILICIDE FORMING METHOD AND SYSTEM THEREOF - Radical in a plasma generation chamber is supplied to a process chamber through an introducing aperture, and HF gas is supplied as a process gas from the vicinity of the radical introducing aperture. A native oxide film of the substrate surface of a IV group semiconductor doped an impurity is removed, with a good surface roughness equal to the wet cleaning. The substrate after the surface treatment is deposited with a metal material and metal silicide formation by thermal treatment is performed, and during these processes, the substrate is not exposed to the atmosphere, and a good contact resistance equal to or better than the wet process is obtained. | 12-03-2009 |
20110263124 | Method of fabricating semiconductor device - A method of fabricating a semiconductor device according to one embodiment includes: forming a plurality of Si-based pattern portions above a semiconductor substrate, the plurality of Si-based pattern portions being adjacent in a direction substantially parallel to a surface of the semiconductor substrate via insulating films; forming a metal film above the plurality of Si-based pattern portions and the insulating films so as to contact with the plurality of Si-based pattern portions; processing whole areas or upper portions of the plurality of Si-based pattern portions into a plurality of silicide layers by a silicidation reaction between the plurality of Si-based pattern portions and the metal film by heat treatment; and removing the plurality of silicide layers formed above the insulating films by applying planarizing treatment to the plurality of silicide layers. | 10-27-2011 |
20120009790 | METHOD FOR FABRICATING STORAGE NODE OF SEMICONDUCTOR DEVICE - A method for fabricating a storage node of a semiconductor device includes forming a sacrificial dielectric pattern with a storage node hole on a substrate, forming a support layer on the sacrificial dielectric pattern, forming a storage node, supported by the support layer, in the storage node hole, performing a full dip-out process to expose the outer wall of the storage node, and performing a cleaning process for removing or reducing a bridge-causing material formed on the surface of the support layer. | 01-12-2012 |
20120244704 | METHOD FOR REMOVING OXIDES - A method for removing native oxides from a substrate surface is provided. In one embodiment, the method comprises positioning a substrate having an oxide layer into a processing chamber, exposing the substrate to a gas mixture while forming a volatile film on the substrate and maintaining the substrate at a temperature below 65° C., heating the substrate to a temperature of at least about 75° C. to sublimate the volatile film and remove the oxide layer, and depositing a first layer on the substrate after heating the substrate. | 09-27-2012 |
20120295441 | METHOD FOR FORMING HARD MASK IN SEMICONDUCTOR DEVICE FABRICATION - A method for forming a hard mask in semiconductor device fabrication comprises: forming first and second patterned material layers on a third material layer, the second patterned material layer only covering the top of predetermined regions of the first patterned material layer; changing a property of exposed top and side portions of the first patterned material layer using the second patterned material layer as a mask, forming property-changed roofs at the exposed top portions of the first patterned material layer and forming property-changed sidewalls with a predetermined width at the exposed side portions of the first patterned material layer; removing the second patterned material layer and portions of the first patterned material layer with exposed tops and an unchanged property located between the property-changed sidewalls, to form the hard mask. | 11-22-2012 |
20140206190 | Silicide Formation in High-Aspect Ratio Structures - Embodiments of the present invention include methods of forming a silicide layer on a semiconductor substrate. In an exemplary embodiment, a metal layer may first be deposited above a semiconductor substrate using a chemical vapor deposition process with a metal amidinate precursor and then the semiconductor substrate may be annealed, causing the semiconductor substrate to react with the metal layer forming a metal-rich silicide layer on the semiconductor substrate. Embodiments may also include forming a low-oxygen capping layer above the metal layer prior to annealing the semiconductor substrate to protect the metal layer from oxidation. The low-oxygen capping layer may, for example, be made of titanium nitride containing less than 20 parts per million of oxygen. Embodiments may further include forming a silicide layer using the above process in a contact hole above a source/drain region of a field-effect transistor, and forming a metal contact above the silicide layer. | 07-24-2014 |
20140363972 | METHODS OF FORMING METAL SILICIDE REGIONS ON SEMICONDUCTOR DEVICES USING MILLISECOND ANNEALING TECHNIQUES - In one example, the method includes forming a metal layer on a silicon-containing structure, after forming the metal layer, performing an ion implantation process to implant silicon atoms into at least one of the metal layer and the silicon-containing structure and performing a first millisecond anneal process so as to form a first metal silicide region in the silicon-containing structure. | 12-11-2014 |
20150357512 | STRUCTURE WITH A METAL SILICIDE TRASPARENT CONDUCTIVE ELECTRODE AND A METHOD OF FORMING THE STRUCTURE - Disclosed are embodiments of a structure with a metal silicide transparent conductive electrode, which is commercially viable, robust and safe to use and, thus, optimal for incorporation into devices, such as flat panel displays, touch panels, solar cells, light emitting diodes (LEDs), organic optoelectronic devices, etc. Specifically, the structure can comprise a substrate (e.g., a glass or plastic substrate) and a transparent conducting film on that substrate. The transparent conducting film can comprise a metal silicide nanowire network. For example, in one embodiment, the metal silicide nanowire network can comprise multiple metal silicide nanowires fused together in a disorderly arrangement so that they form a mesh. In another embodiment, the metal silicide nanowire network can comprise multiple metal silicide nanowires patterned so that they form a grid. Also disclosed herein are various different method embodiments for forming such a structure. | 12-10-2015 |