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Plug formation (i.e., in viahole)

Subclass of:

438 - Semiconductor device manufacturing: process

438584000 - COATING WITH ELECTRICALLY OR THERMALLY CONDUCTIVE MATERIAL

438597000 - To form ohmic contact to semiconductive material

438674000 - Selective deposition of conductive layer

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DocumentTitleDate
20090124079METHOD FOR FABRICATING A CONDUCTIVE PLUG - A method for fabricating a conductive plug includes the steps of providing a substrate having at least a gate structure thereon, a first dielectric layer covering a surface of the substrate, a second dielectric layer disposed on the first dielectric layer, and at least a metal line formed within the second dielectric layer; forming a hard mask plug on the second dielectric layer; forming a third dielectric layer covering the second dielectric layer and the hard mask plug; removing a portion of the third dielectric layer to expose the hard mask plug; removing the hard mask plug to form a plug hole; and forming the conductive plug within the plug hole to electrically connect with the gate structure.05-14-2009
20110195573CLEANING LIQUID FOR LITHOGRAPHY AND METHOD FOR FORMING WIRING - Provided are a cleaning liquid for lithography that exhibits excellent corrosion suppression performance in relation to ILD materials, and excellent removal performance in relation to a resist film and a bottom antireflective coating film, and a method for forming a wiring using the cleaning liquid for lithography. The cleaning liquid for lithography according to the present invention includes a quaternary ammonium hydroxide, a water soluble organic solvent, water, and an inorganic base. The water soluble organic solvent contains a highly polar solvent having a dipole moment of no less than 3.0 D, a glycol ether solvent and a polyhydric alcohol, and the total content of the highly polar solvent and the glycol ether solvent is no less than 30% by mass relative to the total mass of the liquid for lithography.08-11-2011
20090137119NOVEL SEAL ISOLATION LINER FOR USE IN CONTACT HOLE FORMATION - A method is disclosed for etching a contact hole in a stack of dielectric layers. The method minimizes bridging defects between the contact hole and adjacent conductive structures. A substrate has a conductive material layer and an active device disposed thereon. An etch stop layer covers the device and the conductive material, A layer of interlevel dielectric and antireflective coating layers are then provided. A hole is etched through the stack using patterned photoresist. Ashing is used to remove all but the etch stop layer and the interlevel dielectric layer. An isolation liner is deposited over the interlevel dielectric layer, the sidewall surfaces of the hole and the exposed upper surface of the etch stop layer. Another etch removes the isolation liner disposed over the exposed upper surface of the etch stop layer, and removes the underlying etch stop layer to expose an upper surface of the conductive material layer.05-28-2009
20130078807WAFER LEVEL CHIP SCALE PACKAGE HAVING AN ENHANCED HEAT EXCHANGE EFFICIENCY WITH AN EMF SHIELD AND A METHOD FOR FABRICATING THE SAME - A wafer level chip scale package having an enhanced heat exchange efficiency with an EMF shield is presented. The wafer level chip scale package includes a semiconductor chip, an insulation layer, and a metal plate. The semiconductor chip has a plurality of bonding pads on an upper face thereof. The insulation layer is disposed over the upper face of the semiconductor chip and has openings that expose some portions of the bonding pads. The metal plate covers an upper face of the insulation layer and side faces of the semiconductor chip in which the metal plate is electrically insulated from the bonding pads.03-28-2013
20130078805SEMICONDUCTOR DEVICE MANUFACTURING METHOD - The present invention provides a semiconductor device manufacturing method. This method comprises: etching a first dielectric layer to form a recess; depositing a second dielectric layer over said first dielectric layer and said recess, such that said recess is enclosed by said first dielectric layer and said second dielectric layer to form an air gap; and performing etching, such that a first trench is formed in said first dielectric layer and said second dielectric layer, adjacent to said air gap. The first trench can be filled with a conductive material to form wiring.03-28-2013
20130078806Method for Fabricating Copper Interconnections in an Ultra Low Dielectric Constant Film - The invention relates to a method for fabricating copper interconnections in an ultra low dielectric constant film, comprising the following steps of: depositing an etching stop layer on a silicon wafer, depositing an ultra-low-k film on the etching stop layer, and depositing a SiO03-28-2013
20120164829FABRICATION OF THROUGH-SILICON VIAS ON SILICON WAFERS - A through-silicon via fabrication method includes etching a plurality of through holes in a silicon plate. An oxide liner is deposited on the surface of the silicon plate and on the sidewalls and bottom wall of the through holes. A metallic conductor is then deposited in the through holes. In another version, which may be used concurrently with the oxide liner, a silicon nitride passivation layer is deposited on the exposed back surface of the silicon plate of the substrate.06-28-2012
20090124080SEMICONDUCTOR DEVICE THAT IS ADVANTAGEOUS IN MICROFABRICATION AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a semiconductor substrate, a first memory cell transistor, a first select gate transistor, a second memory cell transistor, a second select gate transistor, a contact plug, silicon oxide films, and plasma films which are formed as the same layer as the silicon oxide films and are provided above upper surfaces of the first and the third gate electrodes.05-14-2009
20090042386Semiconductor device using metal nitride as insulating film and its manufacture method - A first insulating film is formed on a semiconductor substrate. A second insulating film made of insulating metal nitride is formed on the first insulating film. A recess is formed through the second insulating film and reaches a position deeper than an upper surface of the first insulating film. A conductive member is buried in the recess. A semiconductor device is provided whose interlayer insulating film can be worked easily even if it is made to have a low dielectric constant.02-12-2009
20130089983METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - The method includes forming a hole penetrating from one surface of a substrate to an electrode formed on the other surface of the substrate; forming an organic insulating film in the hole; removing at least a part of the organic insulating film formed in a bottom portion of the hole and not the organic insulating film formed on a side wall portion of the hole, to expose the electrode; cleaning an exposed surface of the electrode by using plasma of an inert gas; filling a conductive metal in the hole; removing at least a part of a surface of the organic insulating film by the reaction of oxygen plasma; and annealing the substrate in a dysoxidative atmosphere.04-11-2013
20130072020Method For Ensuring DPT Compliance for Auto-Routed Via Layers - A method of generating an integrated circuit with a DPT compatible via pattern using a reduced DPT compatible via design rule set. A reduced DPT compatible via design rule set. A method of forming an integrated circuit using a via pattern generated from a reduced DPT compatible design rule set.03-21-2013
20130072019METHODS FOR FORMING SEMICONDUCTOR DEVICES - Embodiments of methods for forming a semiconductor device are provided. The method includes forming a metal layer overlying a dielectric material. A thickness of the metal layer is reduced including oxidizing an exposed outer portion of the metal layer to form a metal oxide portion overlying a remaining portion of the metal layer and removing the metal oxide portion.03-21-2013
20130072018Repair of Damaged Surface Areas of Sensitive Low-K Dielectrics of Microstructure Devices After Plasma Processing by In Situ Treatment - Damaged surface areas of low-k dielectric materials may be efficiently repaired by avoiding the saturation of dangling silicon bonds after a reactive plasma treatment on the basis of OH groups, as is typically applied in conventional process strategies. The saturation of the dangling bond may be accomplished by directly initiating a chemical reaction with appropriate organic species, thereby providing superior reaction conditions, which in turn results in a more efficient restoration of the dielectric characteristics.03-21-2013
20090081867METHOD OF MANUFACTURING SUBSTRATE - The present disclosure relates to a method of manufacturing a substrate. The method includes: (a) forming through holes by applying an anisotropic etching to a silicon substrate from a first surface of the silicon substrate; (b) forming a first insulating film to cover the first surface of the silicon substrate, surfaces of the silicon substrate exposed from the through holes, and a second surface of the silicon substrate opposite to the first surface; (c) forming an opening in a portion of the first insulating film provided on the second surface, the portion of the first insulating film corresponding to an area in which the through holes are formed; (d) etching the silicon substrate using the first insulating film provided on the second surface as a mask, thereby forming a cavity in the silicon substrate; and (e) removing the first insulating film.03-26-2009
20090233441INTERCONNECTIONS FOR INTEGRATED CIRCUITS - The present invention discloses a method of manufacturing an integrated circuit on a semiconductor substrate having a semiconductor device provided thereon, including the steps of forming a copper layer having an overburden of a desired thickness, forming a layer of inert metal on the copper layer, annealing the copper layer and removing the layer of inert metal.09-17-2009
20080299770METHOD FOR INCREASING ETCH RATE DURING DEEP SILICON DRY ETCH - A method of increasing etch rate during deep silicon dry etch by altering the geometric shape of the etch mask is presented. By slightly altering the shape of the etch mask, the etch rate is increased in one area where an oval etch mask is used as compared to another areas where different geometrically-shaped etch masks are used even though nearly the same amount of silicon is exposed. Additionally, the depth of the via can be controlled by using different geometrically-shaped etch masks while maintaining virtually the same size in diameter for all the vias.12-04-2008
20120115330METAL-INSULATOR-SEMICONDUCTOR TUNNELING CONTACTS - A contact to a source or drain region. The contact has a conductive material, but that conductive material is separated from the source or drain region by an insulator.05-10-2012
20120115329DEPOSITING TUNGSTEN INTO HIGH ASPECT RATIO FEATURES - Methods and apparatuses for filling high aspect ratio features with tungsten-containing materials in a substantially void-free manner are provided. In certain embodiments, the method involves depositing an initial layer of a tungsten-containing material followed by selectively removing a portion of the initial layer to form a remaining layer, which is differentially passivated along the depth of the high-aspect ration feature. In certain embodiments, the remaining layer is more passivated near the feature opening than inside the feature. The method may proceed with depositing an additional layer of the same or other material over the remaining layer. The deposition rate during this later deposition operation is slower near the feature opening than inside the features due to the differential passivation of the remaining layer. This deposition variation, in turn, may aid in preventing premature closing of the feature and facilitate filling of the feature in a substantially void free manner.05-10-2012
20100087062HIGH TEMPERATURE BD DEVELOPMENT FOR MEMORY APPLICATIONS - A method and apparatus for depositing organosilicate dielectric layers having good adhesion properties and low dielectric constant. Embodiments are described in which layers are deposited at low temperature and at high temperature. The low temperature layers are generally post-treated, whereas the high temperature layers need no post treating. Adhesion of the layers is promoted by use of an initiation layer.04-08-2010
20120238093Methods of Fabricating Semiconductor Devices - A method of fabricating a semiconductor device includes forming a stacked structure in which 209-20-2012
20110136342SEMICONDUCTOR APPARATUS AND METHOD FOR MANUFACTURING THE SAME - A semiconductor apparatus including a semiconductor substrate, an insulating layer, a via hole, and a through-hole interconnection is provided. The insulating layer is formed on the semiconductor substrate. The via hole is formed through the semiconductor substrate and the insulating layer. The through-hole interconnection has a conductive layer formed on an insulating layer in the via hole. The surface of the insulating layer formed on the inner surface of the via hole is substantially planarized by filling a recessed portion on a boundary between the semiconductor substrate and the insulating layer formed on the semiconductor substrate.06-09-2011
20120100717TRENCH LITHOGRAPHY PROCESS - A process of forming an integrated circuit using a dual damascene interconnect process by etching a via hole in an ILD and filling the via hole with a sacrificial via fill material. A trench etch hard mask layer is formed over the ILD. An inorganic hard mask layer is formed over the trench etch hard mask layer. The inorganic hard mask layer is etched to form an etch mask for the trench etch hard mask layer, which is subsequently etched to form an etch mask for the trench etch process. The sacrificial via fill material etches at a comparable rate to the ILD layer. The trench etch hard mask layer is removed and the sacrificial via fill material is removed from the via hole.04-26-2012
20120100716Method to improve reliability (EM and TDDB) with post silylation plasma treatment process for copper damascene structures - A method for semiconductor fabrication includes etching a via and a trench in a dielectric material to yield an etched surface. The dielectric material may have an ultra-low K value (e.g., a K-value of less than or equal to 2.4). The etched surface is then processed with a gas-phase silylation process to yield a silylated surface. The silylated surface is processed with a plasma treatment process to yield a plasma treated surface. The plasma treated surface, in turn, is processed with a dilute hydrofluoric acid before a conductive metal is deposited in the via and the trench. Inclusion of the plasma treatment process reduces hollow metal defects caused by the silylation process and increases reliability of metal interconnects and improves barrier metallization.04-26-2012
20100167539METHOD FOR INSULATING WIRES OF SEMICONDUCTOR DEVICE - Disclosed herein is a method for insulating wires of a semiconductor device. One embodiment of the method includes forming first bit line stacks over a cell region of a semiconductor substrate and second bit line stacks over a peripheral region of the semiconductor substrate, and forming a Spin On Dielectric (SOD) layer to fill between the first and second bit line stacks. The method also includes etching back the SOD layer to expose upper side portions of the first and second bit line stacks, selectively removing a portion of the SOD layer present on the peripheral region, and depositing a High Density Plasma (HDP) insulation layer to cover a portion of the SOD layer present on the cell region, and to fill between the second bit line stacks present on the peripheral region.07-01-2010
20130023119METHODS FOR FABRICATING SEMICONDUCTOR DEVICES - In a method for fabricating a semiconductor device, a substrate is provided including an interlayer dielectric layer and first and second hard mask patterns sequentially stacked thereon. A first trench is provided in the interlayer dielectric layer through the second hard mask pattern and the first hard mask pattern. A filler material is provided on the interlayer dielectric layer and the second hard mask pattern to fill the first trench. An upper portion of the second hard mask pattern is exposed by partially removing the filler material. The second hard mask pattern is removed, and remaining filler material is removed from the first trench. A wiring is formed by filling the first trench with a conductive material.01-24-2013
20100267234FOCUSED ION BEAM DEEP NANO-PATTERNING APPARATUS AND METHOD - The present invention introduces a new technique allowing the fabrication of high-aspect ratio nanoscale semiconductor structures and local device modifications using FIB technology. The unwanted semiconductor sputtering in the beam tail region prevented by a thin slow-sputter-rate layer which responds much slower and mostly to the high-intensity ion beam center, thus acting as a saturated absorber funnel-like mask for the semiconductor. The protective layer can be deposited locally using FIB, thus enabling this technique for local device modifications, which is impossible using existing technology. Furthermore, such protective layers allow much higher resolution and nanoscale milling can be achieved with very high aspect ratios, e.g. Ti layer results in aspect ratio higher than 10 versus bare semiconductor milling ratio of about 3.10-21-2010
20120289046METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for forming a polysilicon layer includes forming an amorphous silicon layer over a substrate, performing a first thermal treatment of the amorphous silicon layer by performing an implantation with a gas that includes silicon (Si), and performing a second thermal treatment on the thermally treated layer at a temperature higher than a temperature of the first thermal treatment.11-15-2012
20090098732SEMICONDUCTOR DEVICE AND METHOD OF FORMING CONTACT PLUG OF SEMICONDUCTOR DEVICE - The present invention relates to a semiconductor device and a method of forming a contact plug of a semiconductor device. According to the method, a first dielectric layer is formed on a semiconductor substrate in which junction regions are formed. A hard mask is formed on the first dielectric layer. The hard mask and the first dielectric layer corresponding to the junction regions are etched to form trenches. Spacers are formed on sidewalls of the trenches. Contact holes are formed in the first dielectric layer using an etch process employing the spacers and the hard mask so that the junction regions are exposed. The contact holes are gap filled with a conductive material, thus forming contact plugs. Accordingly, bit lines can be easily formed on the contact plugs formed at narrow spaces with a high density.04-16-2009
20100112813MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE - A manufacturing method for a semiconductor device, including: forming a metallic layer and an interlayer insulation film on a semiconductor substrate sequentially; etching on the interlayer insulation film using fluorine-based etching gas to form an opening portion of a predetermined pattern, reaching the metallic layer; and supplying chlorine-based silane gas and discharging, thus forming a Si film at least on an internal surface of the opening portion without exposure to the atmosphere after the etching.05-06-2010
20110263122Method For Making A Laminated Chip And Method For Aligning a Lithographic Mask - A method for making a laminated chip includes: (a) forming a first conductive layer on a substrate; (b) forming an insulating layer on the first conductive layer opposite to the substrate; (c) bombarding the insulating layer using an electron beam to form a plurality of holes that expose the first conductive layer; and (d) forming a second conductive layer on the insulating layer such that a part of the second conductive layer extends into the holes to electrically connect to the first conductive layer.10-27-2011
20120190196Three Dimensional Integration and Methods of Through Silicon Via Creation - A method includes patterning a photoresist layer on a structure to define an opening and expose a first planar area on a substrate layer, forming doped portions of the substrate layer in the first planar area, removing a portion of the photoresist to form a second opening defining a second planar area on the substrate layer, and etching to form a first cavity having a first depth defined by the first opening to expose a first contact in the structure and to form a second cavity defined by the second opening to expose a second contact in the structure.07-26-2012
20120190195METHODS FOR FABRICATING SEMICONDUCTOR DEVICES HAVING LOCAL CONTACTS - Fabrication methods for semiconductor device structures are provided. One method for fabricating a semiconductor device structure that includes a gate structure overlying a semiconductor substrate and a doped region formed in the semiconductor substrate adjacent to the gate structure involves the steps of forming a first layer of dielectric material overlying the gate structure and the doped region, isotropically etching the first layer of dielectric material, forming a second layer of dielectric material overlying the first layer of dielectric material after isotropically etching the first layer, and forming a conductive contact that is electrically connected to the doped region within the first layer and the second layer.07-26-2012
20090087986Semiconductor devices using fine patterns and methods of forming fine patterns - Example embodiments may provide fine patterns for semiconductor devices and methods of forming fine patterns for semiconductor devices. Example methods may include forming a spacer pattern on a substrate and/or an insulating layer pattern adjacent to sides of the spacer pattern and/or disposed at the same level as the spacer pattern, forming a pair of recesses exposing sides of the spacer pattern by removing a portion of the insulating layer pattern, and/or filling a conductive material in the recesses.04-02-2009
20100099256SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE MANUFACTURING APPARATUS - There is provided a semiconductor device manufacturing apparatus and a semiconductor device manufacturing method capable of recovering a damage of a low dielectric insulating film exposed to CO04-22-2010
20090263970METHOD OF FORMING FINE PATTERN OF SEMICONDUCTOR DEVICE USING SIGE LAYER AS SACRIFICIAL LAYER, AND METHOD OF FORMING SELF-ALIGNED CONTACTS USING THE SAME - There are provided a method of forming a fine pattern of a semiconductor device using a silicon germanium sacrificial layer, and a method of forming a self-aligned contact using the same. The method of forming a self-aligned contact of a semiconductor device includes forming a conductive line structure having a conductive material layer, a hard mask layer, and a sidewall spacer on a substrate, and forming a silicon germanium (Si10-22-2009
20100099255METHOD OF FORMING A CONTACT THROUGH AN INSULATING LAYER - A method includes forming an insulating layer over a substrate, forming a masking layer over the insulating layer, forming a developable bottom anti-reflective coating (BARC) over the masking layer, forming a first photo resist layer over the developable BARC, exposing and developing portions of both the first photo resist layer and the developable BARC to form a first set of openings in the developable BARC, forming a second photo resist layer over the first set of openings and the developable BARC, exposing and developing portions of both the second photo resist layer and the developable BARC to form a second set of openings in the developable BARC, and extending each opening in the first and second set of openings through the masking layer and the insulating layer.04-22-2010
20090286396METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE HAVING A STEPPED THROUGH-HOLE - A DRAM device includes a contact plug in contact with a diffused region of a semiconductor substrate, and a via-plug in contact with top of the contact plug. The through-hole receiving the via-plug has stepped structure including a tapered upper portion formed by an anisotropic dry etching and a larger-diameter lower portion formed by an isotropic etching. The top of the contact plug has a diameter larger than the diameter of the bottom of the lower portion of the via-plug.11-19-2009
20090291556METHOD OF SELECTIVELY DEPOSITING MATERIALS ON A SUBSTRATE USING A SUPERCRITICAL FLUID - A method for depositing one or more materials on a substrate, such as for example, a semiconductor substrate that includes providing the substrate; applying a polymer film to at least a portion of a surface of the substrate; and exposing the semiconductor substrate to a supercritical fluid containing at least one reactant for a time sufficient for the supercritical fluid to swell the polymer and for the at least one reactant to penetrate the polymer film. The reactant is reacted to cause the deposition of the material on at least a portion of the substrate. The substrate is removed from the supercritical fluid, and the polymer film is removed. The process permits the precise deposition of materials without the need for removal of excess material using chemical, physical, or a combination of chemical and physical removal techniques.11-26-2009
20090170315Method for Forming Tungsten Plug - A method for forming a tungsten plug is provided. The method can include forming a first tungsten seed layer on an insulating layer having a via hole, forming a second tungsten seed layer on the first tungsten seed layer, and forming a tungsten-buried layer in the via hole. The second tungsten seed layer can be from about 1.3 times to about 2.5 times thicker than the first tungsten seed layer.07-02-2009
20080274613Method for the Protection of Openings in a Component During a Machining Process - The invention relates to a method for the protection of openings in a component, produced from an electrically-conducting material, in particular, from metal or a metal alloy, during a machining process against the ingress of material, whereby the openings are sealed with a filler material before the machining process, which is removed again after the machining process. The machining processes particularly concern coating processes and welding processes. Said method is characterized in that an electrically-conducting filler material is applied, the electrical conductivity of which matches the electrical conductivity of the base material.11-06-2008
20080293245SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device has a semiconductor substrate, a first insulating film formed on a surface of the semiconductor substrate, a first recess formed in the first insulating film, a first barrier film formed on an inner surface of the first insulating film except a top peripheral region of the first trench, a first conductive film formed in the first trench, and a covering film formed on an upper surface and a top peripheral region of the first conductive film and an upper surface of the first barrier film. The first conductive film includes copper.11-27-2008
20080311742MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - In one aspect of the present invention, a method of fabricating a semiconductor device may include forming a sacrificial film on a substrate, forming an insulating film on the sacrificial film, forming a plurality of first openings in the sacrificial film and the insulating film in a first region and a second region, depositing a conductive material in the plurality of the first openings, forming a second opening in the insulating film in the second region so as to expose the sacrificial film, and removing the sacrificial film in the first region via the second opening in the second region.12-18-2008
20100144143METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A SiOC film 06-10-2010
20080274614 FABRICATING METHOD OF METAL LINE - A method of fabricating a metal line using a dual damascene process which enhances reliability of the semiconductor device. The method includes forming a lower metal line in a first inter metal dielectric layer; and then sequentially forming a first anti-etch layer, a second inter metal dielectric layer and a second anti-etch layer over the first inter metal dielectric layer and the lower metal line, wherein the second inter metal dielectric includes a first trench formed therein; and then forming an oxide film on the second anti-etch layer and in the first trench; and then forming a first via hole by performing a first etching process on the oxide film, the second anti-etch layer and the second inter metal dielectric layer; and then forming a second trench and a second via hole by performing a second etching process using the second anti-etch layer as a mask; and then removing a portion of the first anti-etch layer exposed in the second via hole and the second anti-etch layer; and then forming an upper metal line in the second via hole and the second trench.11-06-2008
20110207323Method of forming and patterning conformal insulation layer in vias and etched structures - Vias are formed in a substrate using an etch process that forms an undercut profile below the mask layer. The vias are coated with a conformal insulating layer and an etch process is applied to the structures to remove the insulating layer from horizontal surfaces while leaving the insulating layers on the vertical sidewalls of the vias. The top regions of the vias are protected during the etchback process by the undercut hardmask.08-25-2011
20090163025METHODS FOR FORMING ALL TUNGSTEN CONTACTS AND LINES - Novel low-resistivity tungsten film stack schemes and methods for depositing them are provided. The film stacks include a mixed tungsten/tungsten-containing compound (e.g., WC) layer as a base for deposition of tungsten nucleation and/or bulk layers. According to various embodiments, these tungsten rich layers may be used as barrier and/or adhesion layers in tungsten contact metallization and bitlines. Deposition of the tungsten-rich layers involves exposing the substrate to a halogen-free organometallic tungsten precursor. The mixed tungsten/tungsten carbide layer is a thin, low resistivity film with excellent adhesion and a good base for subsequent tungsten plug or line formation.06-25-2009
20090004856METHOD OF FORMING CONTACT PLUG IN SEMICONDUCTOR DEVICE - A method of forming a contact plug in a semiconductor device comprising etching an interlayer insulating layer to form a patterned interlayer insulating layer having contact holes such that a distance between upper portions of the contact holes is minimized; forming a first insulating layer including a overhang portion for wrapping an upper portion of the patterned interlayer insulating layer; forming a liner-shaped second insulating layer on the patterned interlayer insulating layer including the first insulating layer, the second insulating layer being formed from material having a selectivity which differs from that of the first insulating layer; and at least partially removing the second insulating layer to increase a bottom critical dimension of the contact hole and removing the overhang portion of the first insulating layer. The invention can secure the bottom critical dimension of the contact hole as well as a distance between the upper portions of the contact holes when the contact plug is formed in a trench in a subsequent process so that the subsequent process margin can be secured. Also, the invention can inhibit an overhang or seam from being formed on the contact plug to enhance contact gap-fill capability and improve contact resistance.01-01-2009
20090325381PREVENTION AND REDUCTION OF SOLVENT AND SOLUTION PENETRATION INTO POROUS DIELECTRICS USING A THIN BARRIER LAYER - A method and apparatus for treating a substrate is provided. A porous dielectric layer is formed on the substrate. In some embodiments, the dielectric may be capped by a dense dielectric layer. The dielectric layers are patterned, and a dense dielectric layer deposited conformally over the substrate. The dense conformal dielectric layer seals the pores of the porous dielectric layer against contact with species that may infiltrate the pores. The portion of the dense conformal pore-sealing dielectric layer covering the field region and bottom portions of the pattern openings is removed by directional selective etch.12-31-2009
20090087987METHOD OF MAKING A SEMICONDUCTOR DEVICE HAVING IMPROVED CONTACTS - A semiconductor device and fabrication process wherein the device includes a conductive layer with a localized thick region positioned below the contact hole. In one embodiment of the invention, the thick region to which contact is made is formed by means of an opening in an underlayer of material. This embodiment of the device includes an underlayer of material having an opening therein; a layer of thin conductive material formed on the underlayer and in the opening; and overlayer of material having a contact hole therethrough formed on the layer of thin conductive material; a conductor contacting the layer of thin conductive material through the contact hole; and wherein the opening in the underlayer is positioned below the contact hole and sized and shaped to form a localized thick region in the layer of thin conductive material within the opening.04-02-2009
20090017623WAFER PROCESSING METHOD - A wafer processing method having a step of reducing the thickness of a wafer in only a device forming area where semiconductor chips are formed by grinding and etching the back side of the wafer to thereby form a recess on the back side of the wafer. At the same time, an annular projection is formed around the recess to thereby ensure the rigidity of the wafer. Accordingly, handling in shifting the wafer from the back side recess forming step to a subsequent step of forming a back side rewiring layer can be performed safely and easily.01-15-2009
20090209100FABRICATION METHOD FOR MEMORY DEVICE - The invention provides a method for fabricating a memory device. At first, a substrate having a plurality of gate electrode stacks and a source/drain region is provided, and a barrier layer and a sacrificial layer are sequentially formed on the substrate and cover the gate electrode stacks. A portion of the sacrificial layer is removed to form a sacrificial plug between the gate electrode stacks, and then a filling layer is formed over the substrate. Next, the sacrificial plug is removed, and a contact hole is formed. A clean step with a solution containing ammonia is carried out. The barrier layer at the bottom of the contact hole is removed, and a metal plug is then formed in the contact hole to electrically contact with the source/drain region.08-20-2009
20090221144Manufacturing method for nano scale Ge metal structure - Manufacturing methods for nano scale Ge include: Form dielectric layer on the substrate surface, then etch the dielectric layer to form openings of three different dimensions, then use chemical vapor deposition process to deposit Ge metal layer to cover the substrate, dielectric layer and the openings; then on the opening of three different dimensions, nano-dot, nano-disk and nano-ring are formed.09-03-2009
20120171864METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - The method of manufacturing the semiconductor device comprises the steps of forming a MOS transistor 07-05-2012
20100062600Method of manufacturing a semiconductor device - A method of manufacturing a semiconductor device includes the steps of forming a first insulating layer with a first opening; forming a first redistribution layer having a first via with a recess; forming a second insulating layer with a second opening on the first redistribution layer so that the second opening causes a part of the first redistribution layer including the recess to be exposed; depositing a conductive material layer and a photoresist film; irradiating a first area of the photoresist film with first exposure light, and irradiating a second area of the photoresist film with second exposure light, wherein the first area includes the second area and the second area includes an area corresponding to the first via; developing the photoresist film; and causing the conductive material layer to grow through a plating process, thereby forming the second redistribution layer having a second via stacked on the first via.03-11-2010
20110143538Semiconductor Processing Methods - Some embodiments include methods in which insulative material is simultaneously deposited across both a front side of a semiconductor substrate, and across a back side of the substrate. Subsequently, openings may be etched through the insulative material across the front side, and the substrate may then be dipped within a plating bath to grow conductive contact regions within the openings. The insulative material across the back side may protect the back side from being plated during the growth of the conductive contact regions over the front side. In some embodiments, plasma-enhanced atomic layer deposition may be utilized to for the deposition, and may be conducted at a temperature suitable to anneal passivation materials so that such annealing occurs simultaneously with the plasma-enhanced atomic layer deposition.06-16-2011
20100261349UV TREATMENT FOR CARBON-CONTAINING LOW-K DIELECTRIC REPAIR IN SEMICONDUCTOR PROCESSING - A method for the ultraviolet (UV) treatment of carbon-containing low-k dielectric enables process-induced damage repair. The method is particularly applicable in the context of damascene processing. A method provides for forming a semiconductor device by depositing a carbon-containing low-k dielectric layer on a substrate and forming a trench in the low-k dielectric layer, the trench having sidewalls ending at a bottom. The trench is then exposed to UV radiation and, optionally a gas phase source of —CH10-14-2010
20090104773METHOD OF FORMING CONTACT - A substrate having at least two metal oxide semiconductor devices of a same conductive type and a gap formed between the two devices is provided. A first stress layer is formed over the substrate to cover the metal-oxide semiconductor devices and the substrate, filling the gap. An etching back process is then performed to remove a portion of the stress material layer inside the gap. A second stress layer and a dielectric layer are sequentially formed on the first stress layer. The first stress layer and the second stress layer provide a same type of stress. A portion of the second stress layer is removed to form a contact opening. A second conductive layer is filled into the contact opening to form a contact.04-23-2009
20100151679SYSTEM FOR MODIFYING SMALL STRUCTURES - A charge transfer mechanism is used to locally deposit or remove material for a small structure. A local electrochemical cell is created without having to immerse the entire work piece in a bath. The charge transfer mechanism can be used together with a charged particle beam or laser system to modify small structures, such as integrated circuits or micro-electromechanical system. The charge transfer process can be performed in air or, in some embodiments, in a vacuum chamber.06-17-2010
20120142189METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes sequentially forming an etch stop layer and a mold layer over a substrate, forming an open region by selectively etching the mold layer until the etch stop layer is exposed, transforming a surface of the mold layer into an insulation layer by performing a surface treatment, and forming a conductive layer inside the open region.06-07-2012
20120142188ANCHORED DAMASCENE STRUCTURES - An anchored conductive damascene buried in a multi-density dielectric layer and method for forming the same, the anchored conductive damascene including a dielectric layer with an opening extending through a thickness of the dielectric layer; wherein the dielectric layer comprises at least one relatively higher density portion and a relatively lower density portion, the relatively lower density portion forming a contiguous major portion of the dielectric layer; and, wherein the opening in the relatively lower density portion has a lateral dimension relatively larger compared to the relatively higher density portion to form anchoring steps06-07-2012
20080311743METHOD OF FABRICATING OPENING AND PLUG - A method of fabricating an opening or plug is provided. In the process of forming the opening, before a photoresist layer is formed over a dielectric layer, a treatment process is performed to form a film on the dielectric layer, wherein the film can suppress the outgasing phenomenon of the dielectric layer and prevent the later formed photoresist layer from reacting with the running-off composition component from the dielectric layer. Therefore, the problem of incomplete development due to outgasing of the dielectric layer can be solved. Additionally, in the procedure for forming a plug, before a block layer is forming on a surface of a via, a treatment process is performed to form a film on the surface of the via. Therefore, the problem of having defects inside the block layer caused by outgasing of the dielectric layer can be overcome.12-18-2008
20080280436METHOD FOR FABRICATING AN INDUCTOR STRUCTURE OR A DUAL DAMASCENE STRUCTURE - A method for fabricating an inductor structure or a dual damascene structure is disclosed. First, a dielectric layer is provided. Subsequently, a first etching process is performed on the dielectric layer so as to form a first opening in the dielectric layer. A polymer is also formed in the first opening during the first etching process. Next, a polymer-removing step is performed to remove the polymer. Thereafter, a second etching process is performed on the dielectric layer to form a second opening in the dielectric layer. Furthermore, the first opening and the second opening are filled with a conductive material so as to form an inductor structure or a dual damascene structure.11-13-2008
20100311241THREE-STATE MASK AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAME - A three-state mask, which is used during exposure of a lithography process and formed in a regular pattern, includes a first transmission region to transmit substantially all incident light, second transmission regions to transmit a portion of incident light, and shield regions to block transmission of light. Therefore, the three-state mask shortens two lithography processes into one lithography process, eliminates misalignment between a via hole and a trench, prevents lowering of a sheet resistance (R12-09-2010
20100048019METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - A falling off of a through electrode is inhibited without decreasing a reliability of a semiconductor device including a through electrode. A semiconductor device 02-25-2010
20110244679Contact Elements of a Semiconductor Device Formed by Electroless Plating and Excess Material Removal with Reduced Sheer Forces - Contact elements in the contact level of a semiconductor device may be formed on the basis of a selective deposition technique, such as electroless plating, wherein an efficient planarization of the contact level is achieved without subjecting the contact elements to undue mechanical stress. In some illustrative embodiments, an overfilling of the contact openings may be reliably avoided and the planarization of the surface topography is accomplished on the basis of a non-critical polishing process. In other cases, electrochemical etch techniques are applied in combination with a conductive sacrificial current distribution layer in order to remove any excess material of the contact elements without inducing undue mechanical stress.10-06-2011
20100055902REDUCING CRITICAL DIMENSIONS OF VIAS AND CONTACTS ABOVE THE DEVICE LEVEL OF SEMICONDUCTOR DEVICES - Contact elements may be formed on the basis of a mask layer having openings, the width of which may be reduced by etching or deposition, thereby extending the process margins for a given lithography technique. Consequently, yield losses caused by short circuits in the contact level of sophisticated semiconductor devices may be reduced.03-04-2010
20090215264PROCESS FOR SELECTIVE GROWTH OF FILMS DURING ECP PLATING - Methods of controlling deposition of metal on field regions of a substrate in an electroplating process are provided. In one aspect, a dielectric layer is deposited under plasma on the field region of a patterned substrate, leaving a conductive surface exposed in the openings. Electroplating on the field region is reduced or eliminated, resulting in void-free features and minimal excess plating. In another aspect, a resistive layer, which may be a metal, is used in place of the dielectric. In a further aspect, the surface of the conductive field region is modified to change its chemical potential relative to the sidewalls and bottoms of the openings.08-27-2009
20110081778SEMICONDUCTOR DEVICE HAVING FINE PATTERN WIRING LINES INTEGRALLY FORMED WITH CONTACT PLUG AND METHOD OF MANUFACTURING SAME - A semiconductor device and method are disclosed in which an interlayer insulating layer is patterned using multiple overlaying masks to define the geometry of contact plugs and corresponding wiring layers separated by fine pitches.04-07-2011
20110250752METHOD OF MANUFACTURING A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - In forming five trenches buried with an intermediate conductive layer for connecting transfer MISFETs and driving MISFETs with vertical MISFETs formed thereover, in which the second and third trenches, and the first, fourth, and fifth trenches are formed separately by twice etching using first and second photoresist films as a mask. Since all the trenches can be formed at a good accuracy even in a case where the shortest distance between the first trench and the second or third trench, and the shortest distance between the second or third trench and the fourth trench is smaller than the resolution limit for the exposure light, the distance between each of the five trenches arranged in one identical memory cell can be reduced to be smaller than resolution limit for the exposure light.10-13-2011
20100003820METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes forming in order a barrier film, an insulating film, a first mask, and a second mask having etching properties different from those of the first mask on a substrate, removing the insulating film, the first mask, and the second mask to form a via hole in the insulating film, removing the second mask in a wiring trench forming region including the via hole, and etching the first mask using the second mask as a mask to remove the first mask in the wiring trench forming region. Removing the first mask in the wiring trench forming region includes etching the first mask and etching the barrier film at the bottom of the via hole to partially remove the barrier film at the bottom of the via hole.01-07-2010
20110256720Techniques for Impeding Reverse Engineering - Anti-reverse engineering techniques are provided. In one aspect, a method for forming at least one feature in an insulating layer is provided. The method comprises the following steps. Ions are selectively implanted in the insulating layer so as to form at least one implant region within the insulating layer, the implanted ions being configured to alter an etch rate through the insulating layer within the implant region. The insulating layer is etched to, at the same time, form at least one void both within the implant region and outside of the implant region, wherein the etch rate through the insulating layer within the implant region is different from an etch rate through the insulating layer outside of the implant region. The void is filled with at least one conductor material to form the feature in the insulating layer.10-20-2011
20110256719METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device includes forming a first contact opening having a relatively larger depth than a second contact opening to expose first and second contacts through an insulation layer, where the first and second contacts are located at different depths with respect to an upper surface of the insulation layer. Therefore, it is possible to prevent excessive over-etch of the second contact opening and minimize etching damage to the contact region exposed by the second contact opening.10-20-2011
20080214000POLISHING COMPOSITION AND POLISHING METHOD USING THE SAME - The present invention relates to a polishing composition more suitable for application in polishing semiconductor devices. The polishing composition consists of a liquid component including water and water-soluble amine. The water-soluble amine includes at least one of triethylenetetramine (TETA) and tetraethylenepentamine (TEPA) and is dissolved in the water.09-04-2008
20080254619METHOD OF FABRICATING A SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device is provided. First, a semiconductor substrate and a dielectric layer positioned on the semiconductor substrate are prepared. Subsequently, the dielectric layer is etched to form a hole structure in the dielectric layer. Afterward, a degas process is performed. An ultraviolet (UV) treatment is carried out to the semiconductor substrate in the degas process so as to expel at least a gas contained in the dielectric layer. Next, a barrier layer is formed on the sidewall and on the bottom of the hole structure. Furthermore, the hole structure is filled with a conductive material. Since the UV treatment can degas the dielectric layer efficiently, the formed semiconductor device can have a fine and stable structure.10-16-2008
20100285662METHODS OF FABRICATING INTEGRATED CIRCUIT DEVICES INCLUDING AIR SPACERS SEPARATING CONDUCTIVE STRUCTURES AND CONTACT PLUGS - An integrated circuit device includes first and second conductive structures spaced apart from one another on a substrate along a first direction. The first and second conductive structures extend in a second direction substantially perpendicular to the first direction. A contact plug is interposed between the first and second conductive structures and is separated therefrom along the first direction by respective air gaps on opposite sides of the contact plug. The air gaps define first and second air spacers that electrically insulate the contact plug from the first and second conductive structures, respectively. An upper insulation layer covers the first and second air spacers and the first and second conductive structures. The air spacers may sufficiently reduce the loading capacitance between the conductive structures. Related fabrication methods are also discussed.11-11-2010
20100167538METHOD FOR REMOVING NATIVE OXIDE REMAINING ON A SURFACE OF A SEMICONDUCTOR DEVICE DURING MANUFACTURING - A method for removing native oxide that remains on a surface of a semiconductor device is presented. The manufacturing method includes the steps of placing, supplying, moving, and annealing. The placing step includes placing a semiconductor substrate into a first process chamber. The supplying step includes supplying an etchant gas that reacts with the native oxide when the first process chamber is purged and sealed away from air. The moving step includes moving the semiconductor substrate with the byproduct formed on it into a second process chamber in which the moving step can be exposed to air. The annealing the semiconductor substrate in the second process chamber removes the byproduct.07-01-2010
20110189854CHEMICAL MECHANICAL POLISHING METHOD - A chemical-mechanical polishing process includes the steps of providing a semiconductor substrate having a first conductive line thereon, and then forming at least one dielectric layer over the substrate and the first conductive line. Next, a chemical-mechanical polishing method is used to polish the surface of the dielectric layer. Thereafter, a cap layer is formed over the polished dielectric layer. The method of forming the cap layer includes depositing silicon oxide using a chemical vapor deposition method with silicane (SiH08-04-2011
20110189852Method for Forming a Via in a Substrate and Substrate with a Via - The present invention relates to a method for forming a via in a substrate which includes the flowing steps of: (a) providing a substrate having a first surface and a second surface; (b) forming an accommodating groove and a plurality of pillars on the first surface of the substrate, the accommodating groove having a side wall and a bottom wall, the pillars remaining on the bottom wall of the accommodating groove; (c) forming a first insulating material in the accommodating groove and between the pillars; (d) removing the pillars so as to form a plurality of grooves in the first insulating material; and (e) forming a first conductive metal in the grooves. As a result, thicker insulating material can be formed in the via, and the thickness of the insulating material in the via is even.08-04-2011
20110189853NONVOLATILE SEMICONDUCTOR STORAGE APPARATUS AND METHOD FOR MANUFACTURING THE SAME - According to an aspect of the present invention, there is provided a nonvolatile semiconductor storage apparatus including: a substrate; a columnar semiconductor disposed perpendicular to the substrate; a charge storage laminated film disposed around the columnar semiconductor; a first conductor layer that is in contact with the charge storage laminated film and that has a first end portion having a first end face; a second conductor layer that is in contact with the charge storage laminated film, that is separated from the first conductor layer and that has a second end portion having a second end face; a first contact plug disposed on the first end face; and a second contact plug disposed on the second end face.08-04-2011
20110189851METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device, the method including providing a substrate; forming an underlying layer on the substrate; forming a sacrificial layer on the underlying layer; forming an opening in the sacrificial layer by patterning the sacrificial layer such that the opening exposes a predetermined region of the underlying layer; forming a mask layer in the opening; forming an oxide mask by partially or completely oxidizing the mask layer; removing the sacrificial layer; and etching the underlying layer using the oxide mask as an etch mask to form an underlying layer pattern.08-04-2011
20110136341FIELD EFFECT TRANSISTOR HAVING MULTIPLE PINCH OFF VOLTAGES - A compound field effect transistor having multiple pinch-off voltages, comprising first and second field effect transistors, each field effect transistor comprising a semiconductor layer, the semiconductor layer having an electrically conducting layer therein. An ohmic contact layer on the semiconductor layer, a source and a drain on the ohmic contact layer, at least one gate on the semiconductor layer between source and drain, at least one gate of the first transistor and one gate of the second transistor being matched gates, each gate having the same effective thickness of electrically conducting layer beneath it, but the gates having different gate lengths.06-09-2011
20110217844METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - The present invention provides a method of manufacturing a semiconductor device. The method includes stacking a SiO09-08-2011
20110217843PATTERNING MASK AND METHOD OF FORMATION OF MASK USING STEP DOUBLE PATTERNING - A method of forming a mask for use in fabricating an integrated circuit includes forming first non-removable portions of a photoresist material through a mask having a plurality of apertures, shifting the mask, forming second non-removable second portions of the photoresist material overlapping the first portions, and removing removable portions of the photoresist material arranged between the first and second portions. The formed photoresist mask may be used to form vias in an integrated circuit. The pattern of vias produced have the capability to exceed the current imaging resolution of a single exposure treatment.09-08-2011
20120302061SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In a semiconductor device having an LDMOSFET, a source electrode is at the back surface thereof. Therefore, to reduce electric resistance between a source contact region in the top surface and the source electrode at the back surface, a poly-silicon buried plug is provided which extends from the upper surface into a P11-29-2012
20120302060METHOD FOR MANUFACTURING MEMORY DEVICE - The disclosure provides a method for manufacturing a memory device, including: providing a plurality of gate structures formed on a substrate, wherein the gate structures comprise a cap layer disposed on the top of the gate structure, and each two adjacent gate structures are separated by a gap; blanketly forming a polysilicon layer on the substrate to fill the gap; performing a planarization process to the polysilicon layer, obtaining a polysilicon plug; and performing an oxidation process after the planarization process, converting a part of the polysilicon plug and a residual polysilicon layer over the gate structure to silicon oxide.11-29-2012
20120149193METHOD FOR MANUFACTURING A SEMICONDUCTOR MEMORY DEVICE - A method for forming a semiconductor device includes the following processes. An insulating film is formed over a semiconductor substrate. A hole is formed in the insulating film. A film including ZrAlO is formed over the insulating film and in the hole. Forming the film including ZrAlO may include, but is not limited to, the following processes. A first precursor including zirconium and a second precursor including aluminum are supplied into a reaction chamber at a supply amount ratio of the first precursor to the second precursor in the range from 2.5 to 3.5. The first precursor and the second precursor are exhausted from the reaction chamber. An oxidant is supplied into the reaction chamber to oxidize zirconium and aluminum. The oxidant is exhausted from the reaction chamber.06-14-2012
20110306208Method for Fabricating Semiconductor Device - Methods for forming a mold for a storage electrode in a semiconductor device include forming an interlayer dielectric layer including a contact plug on a substrate. A first mold dielectric layer is formed of a first material on the interlayer dielectric layer. A second mold dielectric layer is formed of a second material on the first mold dielectric layer. The second material has a different etch selectivity than the first material. A first opening is formed that penetrates the first and second mold dielectric layers. The first opening is dry etched to define a second opening having a larger width in the first mold dielectric layer than in the second mold dielectric layer based on the different etch selectivity of the first and second mold dielectric layers to define the mold for the storage electrode.12-15-2011
20120040530METHODS FOR FORMING ALL TUNGSTEN CONTACTS AND LINES - Novel low-resistivity tungsten film stack schemes and methods for depositing them are provided. The film stacks include a mixed tungsten/tungsten-containing compound (e.g., WC) layer as a base for deposition of tungsten nucleation and/or bulk layers. According to various embodiments, these tungsten rich layers may be used as barrier and/or adhesion layers in tungsten contact metallization and bitlines. Deposition of the tungsten-rich layers involves exposing the substrate to a halogen-free organometallic tungsten precursor. The mixed tungsten/tungsten carbide layer is a thin, low resistivity film with excellent adhesion and a good base for subsequent tungsten plug or line formation.02-16-2012
20120040529RESIST STRIPPING COMPOSITIONS AND METHODS FOR MANUFACTURING ELECTRICAL DEVICES - A liquid composition comprising (A) at least one polar organic solvent, selected from the group consisting of solvents exhibiting in the presence of from 0.06 to 4% by weight of dissolved tetramethylammonium hydroxide (B), the weight percentage being based on the complete weight of the respective test solution (AB), a constant removal rate at 50° C. for a 30 nm thick polymeric barrier anti-reflective layer containing deep UV absorbing chromophoric groups, (B) at least one quaternary ammonium hydroxide, and (C) at least one aromatic amine containing at least one primary amino group, a method for its preparation and a method for manufacturing electrical devices, employing the liquid composition as a resist stripping composition and its use for removing negative-tone and positive-tone photoresists and post etch residues in the manufacture of 3D Stacked Integrated Circuits and 3D Wafer Level Packagings by way of patterning Through Silicon Vias and/or by plating and bumping.02-16-2012
20120040528METHODS FOR PATTERNING MICROELECTRONIC DEVICES USING TWO SACRIFICIAL LAYERS - A lower layer of a microelectronic device may be patterned by forming a first sacrificial layer on the lower layer; patterning a plurality of spaced apart trenches in the first sacrificial layer; forming a second sacrificial layer in the plurality of spaced apart trenches; patterning the second sacrificial layer in the plurality of spaced apart trenches to define upper openings in the plurality of spaced apart trenches; and patterning the lower layer using the first and second sacrificial layers as a mask to form lower openings in the lower layer.02-16-2012
20110318923SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME INCLUDING A CONDUCTIVE STRUCTURE IS FORMED THROUGH AT LEAST ONE DIELECTRIC LAYER AFTER FORMING A VIA STRUCTURE - For forming a semiconductor device, a via structure is formed through at least one dielectric layer and at least a portion of a substrate. In addition, a protective buffer layer is formed onto the via structure. Furthermore, a conductive structure for an integrated circuit is formed over the substrate after forming the via structure and the protective buffer layer, with the conductive structure not being formed over the via structure. Thus, deterioration of the conductive and via structures is minimized.12-29-2011
20120045896Methods Of Forming Openings And Methods Of Patterning A Material - Some embodiments include methods of forming openings. For instance, a construction may have a material over a plurality of electrically conductive lines. A plurality of annular features may be formed over the material, with the annular features crossing the lines. A patterned mask may be formed over the annular features, with the patterned mask leaving segments of the annular features exposed through a window in the patterned mask. The exposed segments of the annular features may define a plurality of openings, and such openings may be transferred into the material to form openings extending to the electrically conductive lines.02-23-2012
20120009789Semiconductor device having seal ring structure and method of forming the same - A method of producing a semiconductor device includes forming, on a first insulating film formed on a substrate, a first groove in an element-forming region to form one of a via and a wiring therein, and a first seal ring groove in a seal ring part, forming one of a via and a wiring in the first groove and a first metal layer in the first seal ring groove, and then removing the metal material in a part exposed to an outside of the first groove and the first seal ring groove, forming a second insulating film on the first insulating film, forming, on the second insulating film, a second groove, and a second seal ring groove in the seal ring part on the first seal ring groove, and forming one of a via and a wiring in the second groove and a second metal layer.01-12-2012
20120009788CLEANING SOLUTION, CLEANING METHOD AND DAMASCENE PROCESS USING THE SAME - A cleaning solution is provided. The cleaning solution includes (a) 0.01-0.1 wt % of hydrofluoric acid (HF); (b) 1-5 wt % of a strong acid, wherein the strong acid is an inorganic acid; (c) 0.05-0.5 wt % of ammonium fluoride (NH01-12-2012
20120058640METHOD FOR FORMING AN INTERCONNECT STRUCTURE - A method for forming an interconnect structure includes forming a mandrel above a base layer, forming spacers on the mandrel, forming recesses in the base layer using the spacers as an etch template, and forming a conductive material in the recesses.03-08-2012
20120028465PROCESS TO FORM VIA HOLE IN SEMICONDUCTOR WAFER - A process to form a via hole in a semiconductor wafer is disclosed. The process includes steps of, preparing a metal mask and etching the wafer by the metal mask as the etching mask. The preparation of the metal mask includes steps of: coating a nega-resist on the back surface of the wafer, carrying out the photolithography for the coated nega-resist, plating a metal selectively by the patterned photoresist, and removing the patterned photoresist.02-02-2012
20120156875LASER BASED PROCESSING OF LAYERED MATERIALS - Systems and methods for laser based processing of layered materials. Methods may include selectively adjusting ultrafast laser output of an ultrafast laser device based upon one or more physical attributes of a layer of the layered material, applying the ultrafast laser output of the ultrafast laser device to the layer of the layered material along a tool path to ablate the layer along the tool path, and then re-executing the steps to ablate one or more additional layers, the re-execution occurring for each distinct layer of the layered material that is to be ablated.06-21-2012
20120064718METHOD OF FABRICATING COPPER DAMASCENE AND DUAL DAMASCENE INTERCONNECT WIRING - An integrated circuit and a method of manufacturing the integrated circuit, the method including: (a) providing a substrate; (b) forming a copper diffusion barrier layer on the substrate; (c) forming a dielectric layer on a top surface of the copper diffusion barrier layer; (d) forming a copper damascene or dual damascene wire in the dielectric layer, a top surface of the copper damascene or dual damascene wire coplanar with a top surface of the dielectric layer; (e) forming a first capping layer on the top surface of the wire and the top surface of the dielectric layer; (f) after step (e) performing one or more characterization procedures in relation to said integrated circuit; and (g) after step (e) forming a second capping layer on a top surface of the first capping layer.03-15-2012
20120064717METHOD FOR FORMING CVD-RU FILM AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICES - In a CVD-Ru film forming method, an Ru-film is formed on a substrate by means of CVD using a ruthenium carbonyl as a film-forming material before forming a Cu film. Then the substrate on which the aforementioned Ru film is formed is annealed in a hydrogen containing atmosphere.03-15-2012
20120070987SEMICONDUCTOR DEVICE HAVING DECREASED CONTACT RESISTANCE - Semiconductor devices having improved contact resistance and methods for fabricating such semiconductor devices are provided. These semiconductor devices include a semiconductor device structure and a contact. The contact is electrically and physically coupled to the semiconductor device structure at both a surface portion and a sidewall portion of the semiconductor device structure.03-22-2012
20120070985EXPOSURE METHOD AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, an exposure method is disclosed. The method can include applying light to a photomask by an illumination. The method can include converging diffracted beams emitted from the photomask by a lens. In addition, the method can include imaging a plurality of point images on an exposure surface. On the photomask, a light transmitting region is formed at a lattice point represented by nonorthogonal unit cell vectors, and in the illumination, a light emitting region is set so that three or more of the diffracted beams pass through positions equidistant from center of a pupil of the lens.03-22-2012
20120070986SEMICONDUCTOR DEVICE HAVING INSULATING FILM WITH SURFACE MODIFICATION LAYER AND METHOD FOR MANUFACTURING THE SAME - Provided is a semiconductor device, which includes an interlayer insulating film formed on a semiconductor substrate, a wiring layer filled in a recess formed in the interlayer insulating film, and a cap insulating film. The interlayer insulating film includes a first SiOCH film and a surface modification layer including an SiOCH film formed by modifying a surface layer of the first SiOCH film, the SiOCH film having a lower carbon concentration and a higher oxygen concentration than the first SiOCH film has. The cap insulating film contacts with surfaces of the metal wiring and the surface modification layer.03-22-2012
20110104895METHOD FOR FORMING A PLUG STRUCTURE - A method for forming a plug structure includes the following steps. A substrate is provided. The substrate includes a MOS device with a source/drain region, a dielectric layer disposed on the MOS device, an opening defined in the dielectric layer, and a first glue layer disposed on a sidewall and a bottom of the opening. A portion of the first glue layer disposed at the bottom of the opening is punched through to expose the source/drain region. A barrier layer is formed over the substrate after the first glue layer is punched through. The opening is filled with a conductive structure, wherein the barrier layer disposed at the bottom of the opening is remained when the conductive structure is filled into the opening.05-05-2011
20120122312METHODS FOR FORMING PLANARIZED HERMETIC BARRIER LAYERS AND STRUCTURES FORMED THEREBY - Methods and associated structures of forming a microelectronic structure are described. Those methods may comprise forming a conductive material in an interconnect opening within an interlayer dielectric material that is disposed on a substrate, forming a low density dielectric material on a surface of the dielectric layer and on a surface of the conductive material, and forming a high density dielectric barrier layer on the low density dielectric layer.05-17-2012
20090130848SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCTION THEREOF - A semiconductor device having a silicon substrate, an element isolating film, an active region, a gate electrode provided via a gate insulating film, a diffusion layer provided on the active region on opposite sides of the gate electrode, an interlayer insulating film, and a plug filled in a hole formed on the interlayer insulating film, wherein the semiconductor device further has a contact forming region surrounded by the element isolating film, and a conductive layer formed on the contact forming region, the gate electrode extends so as to overlap with a portion of the contact forming region and is connected to the conductive layer at the overlapping portion, and the plug contacts the conductive layer at another portion of the contact forming region and is electrically connected to the gate electrode via the conductive layer.05-21-2009
20110183518METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - There is provided a method of manufacturing a semiconductor device, which includes forming a TiN film as a hard mask directly on a second p-SiCOH film formed on a substrate, forming an opening passing through the TiN film and the second p-SiCOH film by photolithography and etching, cleaning the inside of the opening, removing the TiN film after cleaning the inside, and forming a second metal film filling the opening directly on the second p-SiCOH film after removing the TiN film.07-28-2011
20120164830METHODS OF FABRICATING SEMICONDUCTOR DEVICES - Provided is a method of fabricating a semiconductor device. The method includes: preparing a substrate with an etching target, and etching the etching target through a plasma-free etching process that uses an etching gas including one of interhalogen compound, F06-28-2012
20120164831Methods Of Forming Semiconductor Devices - Methods of forming a semiconductor device are provided. The methods may include forming a second insulation pattern on a first insulation pattern. The first insulation pattern may cover a plurality of conductive structures, and may include a hole therein. The second insulation pattern may include a trench therein that is connected with the hole. The methods may also include forming a spacer on sidewalls of the hole and the trench. The methods may further include forming a wiring structure in the hole and the trench.06-28-2012
20120220125METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes providing a substrate including first landing plugs and second landing plugs that are arrayed on a first line, forming a capping layer over the substrate, forming hole-type first trenches that expose the second landing plugs by selectively etching the capping layer, forming an insulation layer over the substrate including the first trenches, forming line-type second trenches that are stretched on the first line while overlapping with the first trenches by selectively etching the insulation layer, and forming a first conductive layer inside the second trenches.08-30-2012
20120220124METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes forming an insulation layer containing an impurity, forming a contact hole by etching the insulation layer, performing a treatment to decrease a concentration of the impurity on a surface of the insulation layer, and rinsing the contact hole.08-30-2012
20100330805METHODS FOR FORMING HIGH ASPECT RATIO FEATURES ON A SUBSTRATE - Methods for forming anisotropic features for high aspect ratio application in etch process are provided. The methods described herein advantageously facilitates profile and dimension control of features with high aspect ratios. In one embodiment, a method for anisotropic etching a dielectric layer on a substrate includes providing a substrate having a patterned mask layer disposed on a dielectric layer in an etch chamber, supplying a gas mixture including at least a fluorine and carbon containing gas and a silicon fluorine gas into the etch chamber, and etching features in the dielectric layer in the presence of a plasma formed from the gas mixture.12-30-2010
20100330806Method of forming contact hole arrays using a hybrid spacer technique - One embodiment of the invention provides a method of forming a plurality of contact holes, including forming a first feature and a second feature over an underlying material, forming sidewall spacers on the first and second features, removing the first and second features without removing the sidewall spacers, forming a cover mask at least partially exposing the sidewall spacers, and etching the underlying material using the cover mask and the sidewall spacers as a mask to form the plurality of contact holes.12-30-2010
20120214305Technique for Reducing Plasma-Induced Etch Damage During the Formation of Vias in Interlayer Dielectrics by Modified RF Power Ramp-Up - When performing plasma assisted etch processes for patterning complex metallization systems of microstructure devices, the probability of creating plasma-induced damage, such as arcing, may be reduced or substantially eliminated by using a superior ramp-up system for the high frequency power and the low frequency power. To this end, the high frequency power may be increased at a higher rate compared to the low frequency power component, wherein, additionally, a time delay may be applied so that, at any rate, the high frequency component reaches its target power level prior to the low frequency component.08-23-2012
20120214306METHOD FOR OBTAINING EXTREME SELECTIVITY OF METAL NITRIDES AND METAL OXIDES - Methods for etching metal nitrides and metal oxides include using ultradilute HF solutions and buffered, low-pH HF solutions containing a minimal amount of the hydrofluoric acid species H08-23-2012
20120214304SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The present invention provides a semiconductor device and a method of manufacturing the same. According to an embodiment of the present invention, a silicon oxide layer is formed over lower electrode contact plugs by using a selective oxidation process, wherein the silicon oxide layer has a thickness greater than an oxidized portion of an adjacent isolation layer (i.e., an isolation insulating layer). Accordingly, a concave contact area between a lower electrode and the lower electrode contact plug can be desirably be secured following etching of the silicon oxide layer in a subsequent process. Specifically, a width of the adjacent isolation layer does not need to be increased because sequential dry and wet etch processes expose the lower electrode contact plugs in a process of forming the lower electrodes.08-23-2012
20120135601METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device including a plurality of hole patterns is disclosed. The method includes: forming a plurality of first line patterns and a plurality of first space patterns extending in a first direction; forming a plurality of second line patterns and a plurality of second space patterns extending in a second direction, on the plurality of first line patterns and the plurality of first space patterns; forming a plurality of first hole patterns where the plurality of first space patterns and the plurality of second space patterns cross each other; and forming a plurality of second hole patterns where the plurality of first line patterns and the plurality of second line patterns cross each other.05-31-2012
20120077342SYSTEMS AND METHODS FOR SELECTIVE TUNGSTEN DEPOSITION IN VIAS - A method for processing a substrate includes providing a substrate including a metal layer, a dielectric layer arranged on the metal layer, and at least one of a via and a trench formed in the dielectric layer; depositing a metal using chemical vapor deposition (CVD) during a first deposition period, wherein the first deposition period is longer than a first nucleation period that is required to deposit the metal on the metal layer; stopping the first deposition period prior to a second nucleation delay period, wherein the second nucleation period is required to deposit the metal on the dielectric layer; performing the depositing and the stopping N times, where N is an integer greater than or equal to one; and after the performing, depositing the metal using CVD during a second deposition period that is longer than the second nucleation delay period.03-29-2012
20080311744MULTILAYER HARDMASK SCHEME FOR DAMAGE-FREE DUAL DAMASCENE PROCESSING OF SiCOH DIELECTRICS - Interconnect structures possessing an organosilicate glass based material for 90 nm and beyond BEOL technologies in which a multilayer hardmask using a line-first approach are described. The interconnect structure of the invention achieves respective improved device/interconnect performance and affords a substantial dual damascene process window owing to the non-exposure of the OSG material to resist removal plasmas and because of the alternating inorganic/organic multilayer hardmask stack. The latter feature implies that for every inorganic layer that is being etched during a specific etch step, the corresponding pattern transfer layer in the field is organic and vice-versa.12-18-2008
20100055903ENHANCING STRUCTURAL INTEGRITY OF LOW-K DIELECTRICS IN METALLIZATION SYSTEMS OF SEMICONDUCTOR DEVICES BY USING A CRACK SUPPRESSING MATERIAL LAYER - During the formation of metallization layers of sophisticated semiconductor devices, the damaging of sensitive dielectric materials, such as ULK materials, may be significantly reduced during a CMP process by applying a compressive stress level. This may be accomplished, in some illustrative embodiments, by forming a compressively stressed cap layer on the ULK material, thereby suppressing the propagation of micro cracks into the ULK material.03-04-2010
20120178257SOLUTIONS FOR CLEANING SEMICONDUCTOR STRUCTURES AND RELATED METHODS - A method for cleaning a semiconductor structure includes subjecting a semiconductor structure to an aqueous solution including at least one fluorine compound, and at least one strong acid, the aqueous solution having a pH of less than 1. In one embodiment, the aqueous solution includes water, hydrochloric acid, and hydrofluoric acid at a volumetric ratio of water to hydrochloric acid to hydrofluoric acid of 1000:32.5:1. The aqueous solution may be used to form a contact plug that has better contact resistance and improved critical dimension bias than conventional cleaning solutions.07-12-2012
20120225554METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING BOWING PREVENTION FILM - A method of manufacturing a semiconductor device, the method including sequentially forming a lower material film, a middle material film, and an upper material film on a semiconductor substrate; and forming an opening that vertically penetrates the upper material film, the middle material film, and the lower material film by etching the upper material film, the middle material film, and the lower material film, wherein the middle material film and the upper material film are formed of material films having etch rates lower than an etch rate of the lower material film with respect to an etchant for etching the lower material film.09-06-2012
20090035941METHODS AND APPARATUS FOR MANUFACTURING A SEMICONDUCTOR DEVICE IN A PROCESSING CHAMBER - An apparatus for manufacturing a semiconductor device includes a process chamber configured to perform a plurality of different processes on a substrate. A gas supply unit is configured to supply at least one process gas to the process chamber. At least one upper electrode unit is positioned at an upper portion of the process chamber. At least one lower electrode unit is opposite the upper electrode unit and configured to support a substrate thereon. A driving member is connected to at least one of the lower electrode unit and the upper electrode unit and is configured to move the lower electrode unit and/or the upper electrode unit to control a distance between the upper and the lower electrode units. A power supply unit is configured to apply a first power to the upper electrode unit and to apply a second power to the lower electrode unit.02-05-2009
20120264298METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device is disclosed. A method for manufacturing a semiconductor device includes forming a device isolation structure for defining an active region, forming a buried word line traversing the active region, forming one or more insulation film patterns over the buried word line, forming a line pattern including a first conductive material at a position between the insulation film patterns, and forming a plurality of storage node contacts (SNCs) by isolating the line pattern. As a result, when forming a bit line contact and a storage node contact, a fabrication margin is increased.10-18-2012
20110003476METHODS OF FORMING SEMICONDUCTOR DEVICES INCLUDING LANDING PADS FORMED BY ELECTROLESS PLATING - A semiconductor device in which an increase of contact resistance Rc between a metal contact and a plug due to misalignment between the metal contact and the plug can be reduced and the difficulty of a Cu filling process during the process of forming the plug may be reduced. The semiconductor device includes a substrate including an active area and a device isolation layer; a metal contact that is formed on the substrate and is electrically connected to the active area; a landing pad formed on the metal contact by electroless plating; and a plug that is formed on the landing pad and is electrically connected to the metal contact via the landing pad.01-06-2011
20120322261Methods for Via Structure with Improved Reliability - Methods for forming a via structure are provided. The method includes depositing a first-layer conductive line over a semiconductor substrate, forming a dielectric layer over the first-layer conductive line, forming a via opening in the dielectric layer and exposing the first-layer conductive line in the via opening, forming a recess portion in the first-layer conductive line, and filling the via opening to form a via extending through the dielectric layer to the first-layer conductive line. The via has a substantially tapered profile and substantially extends into the recess in the first-layer conductive line.12-20-2012
20120276739DIFFERENTIALLY RECESSED CONTACTS FOR MULTI-GATE TRANSISTOR OF SRAM CELL - A complementary metal-oxide-semiconductor static random access memory cell includes a plurality of P-channel multi-gate transistors and a plurality of N-channel multi-gate transistors. Each transistor includes a gate electrode and source and drain regions separated by the at least one gate electrode. The SRAM cell further includes a plurality of contacts formed within the source and drain regions of at least one transistor. A plurality of contacts of at least one transistor are recessed a predetermined recess amount, wherein a resistance of the at least one transistor is varied based upon the predetermined recess amount.11-01-2012
20100233878METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE FOR PREVENTING OCCURRENCE OF SHORT CIRCUIT BETWEEN BIT LINE CONTACT PLUG AND STORAGE NODE CONTACT PLUG - A method for manufacturing a semiconductor device includes the steps of forming a plug on a semiconductor substrate, forming an insulation layer over the semiconductor substrate having the plug formed thereon, defining a line type trench through a first etching of a partial thickness of the insulation layer; and defining a contact hole through a second etching of a portion of the insulation layer corresponding to the bottom of the trench so as to expose the plug.09-16-2010
20110294292METHOD OF FORMING A SHARED CONTACT IN A SEMICONDUCTOR DEVICE - A method for forming a shared contact in a semiconductor device having a gate electrode corresponding to a first transistor and a source/drain region corresponding to a second transistor is provided. The method includes forming a first opening in a dielectric layer overlying the gate electrode and the source/drain region, wherein the first opening extends substantially to the gate electrode corresponding to the first transistor. The method further includes after forming the first opening, forming a second opening, contiguous with the first opening, in the overlying dielectric layer, wherein the second opening extends substantially to the source/drain region corresponding to the second transistor. The method further includes forming the shared contact between the gate electrode corresponding to the first transistor and the source/drain region corresponding to the second transistor by filling the first opening and the second opening with a conductive material.12-01-2011
20110159690DEPOSITING TUNGSTEN INTO HIGH ASPECT RATIO FEATURES - Methods and apparatuses for filling high aspect ratio features with tungsten-containing materials in a substantially void-free manner are provided. In certain embodiments, the method involves depositing an initial layer of a tungsten-containing material followed by selectively removing a portion of the initial layer to form a remaining layer, which is differentially passivated along the depth of the high-aspect ration feature. In certain embodiments, the remaining layer is more passivated near the feature opening than inside the feature. The method may proceed with depositing an additional layer of the same or other material over the remaining layer. The deposition rate during this later deposition operation is slower near the feature opening than inside the features due to the differential passivation of the remaining layer. This deposition variation, in turn, may aid in preventing premature closing of the feature and facilitate filling of the feature in a substantially void free manner.06-30-2011
20080254620METHOD FOR FABRICATING LANDING PLUG OF SEMICONDUCTOR DEVICE - A method of fabricating a landing plug of a semiconductor device includes performing a double patterning process to separately form a landing plug contact hole for a storage node and a landing plug contact hole for a bit line, thereby facilitating forming a device having a half pitch of 30 nm.10-16-2008
20080248646METHOD OF FABRICATING A FLASH MEMORY DEVICE - In a method of fabricating a flash memory device, an interlayer dielectric layer is formed on a semiconductor substrate. The interlayer dielectric layer is etched to form first contact holes through which junction regions of a cell region are exposed. First contact plugs are formed within the first contact holes. A top surface of the interlayer dielectric layer is etched so that portions of the first contact plugs having the largest width are exposed. The interlayer dielectric layer is etched to form a second contact hole through which a junction region of a peri region is exposed. A second metal layer is formed over the first contact plugs and the interlayer dielectric layer so that the second contact hole is gap-filled. A second contact plug is formed within the second contact hole by removing the second metal layer and the exposed portions of the first contact plugs on the interlayer dielectric layer.10-09-2008
20080233743Method and Structure for Self-Aligned Device Contacts - Disclosed are embodiments of a semiconductor structure with a partially selfaligned contact in lower portion of the contact is enlarged to reduce resistance without impacting device yield. Additionally, the structure optionally incorporates a thick middle-of-the-line (MOL) nitride stress film to enhance carrier mobility. Embodiments of the method of forming the structure comprise forming a sacrificial section in the intended location of the contact. This section is patterned so that it is self-aligned to the gate electrodes and only occupies space that is intended for the future contact. Dielectric layer(s) (e.g., an optional stress layer followed by an interlayer dielectric) may be deposited once the sacrificial section is in place. Conventional contact lithography is used to etch a contact hole through the dielectric layer(s) to the sacrificial section. The sacrificial section is then selectively removed to form a cavity and the contact is formed in the cavity and contact hole.09-25-2008
20080233742METHOD OF DEPOSITING ALUMINUM LAYER AND METHOD OF FORMING CONTACT OF SEMICONDUCTOR DEVICE USING THE SAME - A contact hole is formed in an interlayer insulating layer disposed on a semiconductor substrate. The semiconductor substrate is loaded into a reaction chamber. A reaction gas including an aluminum precursor is injected into the reaction chamber. Reaction energy is supplied to the reaction chamber so as to allow thermal decomposition of the aluminum precursor. The injecting of the reaction gas and the supplying of the reaction energy are periodically repeated to deposit a first aluminum layer on the semiconductor substrate. A second aluminum layer is deposited to fill the contact hole.09-25-2008
20130171821METHOD OF FABRICATING METAL CONTACT USING DOUBLE PATTERNING TECHNOLOGY AND DEVICE FORMED THEREBY - Metal contacts are formed within a string overhead area using a double patterning technology (DPT) process thereby allowing for the reduction of a string overhead area and a concomitant reduction in the chip size of a semiconductor device. A first mask pattern is formed by etching a first mask layer, the first mask pattern including a first opening formed in a cell region and a first hole formed in a peripheral region. A first sacrificial pattern is formed on the first mask pattern and the exposed first insulating layer of the cell region using a double patterning technology process. Contact holes are formed by exposing the target layer by etching the first insulating layer using the first mask pattern and the first sacrificial pattern as an etch mask. Metal contacts are then formed in the contact holes.07-04-2013
20130178063METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING SILICON THROUGH VIA - A method of manufacturing semiconductor device having silicon through via is disclosed, and conductor can be fully filled in the silicon through via. First, a silicon substrate is provided. Then, the silicon substrate is etched to form a through silicon via (TSV), and the through silicon via extends down from a surface of the silicon substrate. Next, a barrier layer is formed on the silicon substrate and in the through silicon via. Then, a seed layer is formed on the barrier layer and in the through silicon via. Afterward, a wet treatment is performed on the seed layer over the silicon substrate and within the through silicon via. The through silicon via is then filled with a conductor.07-11-2013
20130171822TUNGSTEN FEATURE FILL WITH NUCLEATION INHIBITION - Described herein are methods of filling features with tungsten, and related systems and apparatus, involving inhibition of tungsten nucleation. In some embodiments, the methods involve selective inhibition along a feature profile. Methods of selectively inhibiting tungsten nucleation can include exposing the feature to a direct or remote plasma. In certain embodiments, the substrate can be biased during selective inhibition. Process parameters including bias power, exposure time, plasma power, process pressure and plasma chemistry can be used to tune the inhibition profile. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) wordlines. The methods may be used for both conformal fill and bottom-up/inside-out fill. Examples of applications include logic and memory contact fill, DRAM buried wordline fill, vertically integrated memory gate/wordline fill, and 3-D integration using through-silicon vias.07-04-2013
20130095657POST-ETCH TREATING METHOD - This disclosure relates to a post-etch treating method. An opening is formed by etching a stacked structure of a dielectric layer, an intermediate layer and a metal hard mask layer arranged in order from bottom to top. The treating method sequentially comprises steps of: performing a first cleaning process on the stacked structure with the opening so as to remove at least a part of the metal hard mask layer; and performing a second cleaning process on the stacked structure with the opening so as to remove etching residues.04-18-2013
20130115771Method of making semiconductor device - One or more embodiments may include a method of making a semiconductor structure, comprising: forming a first opening partially through a semiconductor substrate; forming a first dielectric layer over a sidewall surface of the first opening; and forming a second opening partially through a semiconductor substrate, the second opening being below the first opening.05-09-2013
20130130498REDUCING PATTERNING VARIABILITY OF TRENCHES IN METALLIZATION LAYER STACKS WITH A LOW-K MATERIAL BY REDUCING CONTAMINATION OF TRENCH DIELECTRICS - Generally, the present disclosure is related to various techniques that may be used for forming metallization systems in a highly efficient manner by filling via openings and trenches in a common fill process, while reducing negative effects during the patterning of the via opening and the trenches. One illustrative method disclosed herein includes, among other things, forming a via opening in a first dielectric material of a metallization layer of a semiconductor device. Moreover, a second dielectric material is formed above the first dielectric material, wherein the second dielectric material fills the via opening. Furthermore, the method also includes forming a trench in the second dielectric material so as to connect to the via opening, and filling the trench and the via opening with a metal in a common fill process.05-23-2013
20130149863METHOD FOR FABRICATING SEMICONDUCTOR DEVICE BY DAMASCENE PROCESS - A method for fabricating a semiconductor device includes forming a plurality of isolation patterns, isolated from each other by a plurality of trenches, over an underlying structure; forming a plurality of conductive lines filled in the trenches, forming contact holes by removing first portions of the isolation patterns, wherein the contact holes are defined by the plurality of conductive lines and second portions of the isolation patterns that remain after removing of the first portions of the isolation patterns, and forming plugs filled in the contact holes.06-13-2013
20130149864Semiconductor Device and Manufacturing Method Thereof - Wirings mainly containing copper are formed on an insulating film on a substrate. Then, after forming insulating films for reservoir pattern and a barrier insulating film, an insulating film for suppressing or preventing diffusion of copper is formed on upper and side surfaces of the wirings, the insulating film on the substrate, and the barrier insulating film. Here, thickness of the insulating film for suppressing or preventing diffusion of copper at the bottom of a narrow inter-wiring space is made smaller than that on the wirings, thereby efficiently reducing wiring capacitance of narrow-line pitches. Then, first and second low dielectric constant insulating films are formed. Here, a deposition rate of the first insulating film at an upper portion of the side surfaces of facing wirings is made higher than that at a lower portion thereof, thereby forming air gaps. Finally, the second insulating film is planarized by interlayer CMP.06-13-2013
20130183825METHOD FOR MANUFACTURING DAMASCENE STRUCTURE - A method for manufacturing a damascene structure includes providing a substrate having a dielectric layer formed thereon, forming at least a trench in the dielectric layer, forming at least a via hole and a dummy via hole in the dielectric layer, forming a first conductive layer filling up the trench, the via hole and the dummy via hole on the substrate, and performing a chemical mechanical polishing process to form a damascene structure and simultaneously to remove the dummy via hole.07-18-2013
20130189839METHOD TO FORM SILICIDE CONTACT IN TRENCHES - A method for forming silicide contacts includes forming a dielectric layer on a gate spacer, a gate stack, and a first semiconductor layer. The first semiconductor layer comprises source/drain regions. Contact trenches are formed in the dielectric layer so as to expose at least a portion of the source/drain regions. A second semiconductor layer is formed within the contact trenches. A metallic layer is formed on the second semiconductor layer. An anneal is performed to form a silicide region between the second semiconductor layer and the metallic layer. A conductive contact layer is formed on the metallic layer or the silicide region.07-25-2013
20120289047Method for Producing a Connection Region on a Side Wall of a Semiconductor Body - A method for producing a connection region on a side wall of a semiconductor body is disclosed. A first trench is produced on a first surface of a semiconductor body and extends into the semiconductor body. An insulation layer is formed on the side walls and on the bottom of the first trench, and the first trench is only partially filled. The unfilled part of the first trench is filled with an electrically conductive material. A separating trench is produced along the first trench in such a way that a side wall of the separating trench directly adjoins the first trench. The part of the insulation layer which adjoins the separating trench is at least partially removed, with the result that at least some of the electrically conductive material in the first trench is exposed.11-15-2012
20120094486METHOD FOR CREATING A METAL CRYSTALLINE REGION, IN PARTICULAR IN AN INTEGRATED CIRCUIT - The method comprises affixing a thin sheet of crystal (04-19-2012
20130210227USE OF CONTACTS TO CREATE DIFFERENTIAL STRESSES ON DEVICES - Disclosed herein are various methods and structures using contacts to create differential stresses on devices in an integrated circuit (IC) chip. An IC chip is disclosed having a p-type field effect transistor (PFET) and an n-type field effect transistor (NFET), a PFET contact to a source/drain region of the PFET and an NFET contact to a source/drain region of the NFET. In a first embodiment, a silicon germanium (SiGe) layer is included only under the PFET contact, between the PFET contact and the source/drain region of the PFET. In a second embodiment, either the PFET contact extends into the source/drain region of the PFET or the NFET contact extends into the source/drain region of the NFET.08-15-2013
20130210228METHOD OF FORMING PITCH MULTIPLIED CONTACTS - Methods of forming electrically conductive and/or semiconductive features for use in integrated circuits are disclosed. Various pattern transfer and etching steps can be used, in combination with pitch-reduction techniques, to create densely-packed features. The features can have a reduced pitch in one direction and a wider pitch in another direction. Conventional photo-lithography steps can be used in combination with pitch-reduction techniques to form elongate, pitch-reduced features such as bit-line contacts, for example.08-15-2013

Patent applications in class Plug formation (i.e., in viahole)