Class / Patent application number | Description | Number of patent applications / Date published |
438672000 | Plug formation (i.e., in viahole) | 31 |
20080233741 | Bulk-Isolated PN Diode and Method of Forming a Bulk-Isolated PN Diode - A technique for making a bulk isolated PN diode is disclosed. In one embodiment, a method may include providing a substrate having a doped region and disposing a dielectric material over the doped region. The method may also include forming first and second holes in the dielectric material exposing the doped region, and forming respective first and second polysilicon plugs within the first and second holes over the doped region. In one embodiment, the first and second polysilicon plugs are doped opposite one another such that a PN junction is formed between the first or second polysilicon plug and the doped region of the substrate, and has a cross-sectional area generally defined by the first or second hole adjacent the PN junction. Various devices, systems, and other methods are also disclosed. | 09-25-2008 |
20080261397 | Method for Manufacturing Semiconductor Device - There is provided a method for manufacturing a semiconductor device, which includes the steps of: providing a semiconductor substrate including a gate, a source and a drain, wherein the gate includes a gate dielectric layer disposed on the semiconductor substrate; forming an etching barrier layer on the semiconductor substrate; and subjecting the resulted structure to hydrogen annealing. According to the present invention, the interface energy level between a gate dielectric layer and a semiconductor substrate is lowered and the reliability of the semiconductor device is improved. | 10-23-2008 |
20080268640 | METHOD FOR FORMING BIT-LINE CONTACT PLUG AND TRANSISTOR STRUCTURE - A method for forming a bit-line contact plug includes providing a substrate including a transistor which includes a gate structure and a source/drain at both sides of the gate structure; forming a conductive layer, a bit-line contact material layer and a hard mask layer; performing an etching process using the conductive layer as an etching stop layer to etch the bit-line contact material layer and the hard mask layer and forming the bit-line contact plug on the source/drain. A transistor structure includes a gate structure and a source/drain at both sides of the gate structure, a conductive layer covering part of the gate structure and connected to the source/drain, and a bit-line contact plug disposed on the conductive layer and directly connected to the conductive layer. | 10-30-2008 |
20080318422 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - An aluminum gallium nitride/gallium nitride layer (III-V nitride semiconductor layer) is formed on the surface of a silicone carbide substrate. The aluminum gallium nitride/gallium nitride layer is dry-etched from an exposed surface, using a chlorine-based gas (first gas) and a surface via hole is thereby formed. A back via hole, which is to be connected to the surface via hole, is formed by dry-etching the silicon carbide substrate from an exposed back side using a fluorine-based gas (second gas). | 12-25-2008 |
20090117738 | METHOD FOR PRODUCING SUBSTRATE - A metallic film | 05-07-2009 |
20090170314 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes the steps of: (a) forming a low dielectric constant film over a semiconductor substrate; (b) forming a recess in the low dielectric constant film; (c) after the step (b), sequentially performing the steps of (c1) applying an organic solution to the low dielectric constant film and (c2) silylating the low dielectric constant film with a silylating solution; and (d) after the step (c), embedding a metal in the recess to form at least one of a via plug and a metal wiring in the low dielectric constant film. Performing the step (c1) before the step (c2) improves a penetration property of the silylating solution into the low dielectric constant film. | 07-02-2009 |
20090197408 | INCREASING ELECTROMIGRATION RESISTANCE IN AN INTERCONNECT STRUCTURE OF A SEMICONDUCTOR DEVICE BY FORMING AN ALLOY - By introducing a metallic species into an exposed surface area of a copper region, the electromigration behavior of this surface area may be significantly enhanced. The incorporation of the metallic species may be accomplished in a highly selective manner so as to not unduly affect dielectric material positioned adjacent to the metal region, thereby essentially avoiding undue increase of leakage currents. | 08-06-2009 |
20100144141 | Semiconductor Device and Method of Forming the Same - Provided are a semiconductor device and a method of forming the semiconductor device. The method may include forming a semiconductor pattern on a substrate, forming an interlayer insulating layer including an opening exposing the semiconductor pattern, forming a semiconductor ohmic pattern on the semiconductor pattern, forming an electrode ohmic layer on the semiconductor ohmic pattern, performing a wet etching on the electrode ohmic layer, and forming an electrode pattern on the etched electrode ohmic layer. | 06-10-2010 |
20100261347 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME8027 - A method of forming a semiconductor device includes the following processes. A first insulating film is formed over an etching stopper film. The etching stopper film has wet-etching resistance. A second insulating film is formed over the second etching stopper. The second insulating film is higher in wet-etching rate than the first insulating film. An opening is formed, which penetrates the etching stopper and the first and second insulating films. A bottom electrode is formed in the opening. The second insulating film is removed by carrying out a wet etching process to expose the bottom electrode. | 10-14-2010 |
20100261348 | Method for fabricating semiconductor package substrate having different thicknesses between wire bonding pad and ball pad - A method for fabricating a semiconductor package substrate, including: preparing a copper clad laminate and half etching a copper foil on a wire bonding pad side of the copper clad laminate; depositing a first etching resist on the opposite sides of the copper clad laminate; forming circuit patterns on the first etching resist, constructing circuits including a wire bonding pad and a ball pad after the model of the circuit patterns, and removing the first etching resist; applying a solder resist to the copper clad laminate in such a way to expose the wire bonding pad and the ball pad; and plating the wire bonding pad with gold and subjecting the ball pad to surface treatment. | 10-14-2010 |
20100297845 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes forming an interlayer dielectric layer having a plurality of contact holes over a substrate, forming a conductive layer by filling the contact holes to cover the interlayer dielectric layer, performing a first main etch process to partially etch the conductive layer to form a first conductive layer, performing a second main etch process to etch the first conductive layer using an etch gas having a slower etch rate with respect to the first conductive layer than an etch gas used in the first main etch process until an upper surface of the interlayer dielectric layer is exposed to form a second conductive layer, and performing an over-etch process to etch a certain portion of the second conductive layer, and at the same time, to etch a certain portion of the interlayer dielectric layer to form a landing plug. | 11-25-2010 |
20100330804 | Method for Fabricating Bitline in Semiconductor Device - A method of a fabricating a bitline in a semiconductor device, comprising: forming an interlayer insulation layer that defines a bitline contact hole on a semiconductor substrate; forming a contact layer to fill the bitline contact hole; forming a bitline contact by planarizing the contact layer; forming a bitline stack aligned with the bitline contact; forming a high aspect ratio process (HARP) layer that extends along the bitline stack and the interlayer insulation layer while covering a seam exposed in a side portion of the bitline stack by excessive planarization during formation of the bitline contact; and forming an interlayer gap-filling insulation layer on the HARP layer that gap-fills the entire bitline stack. | 12-30-2010 |
20110092069 | SELF-ALIGNED PATTERNED ETCH STOP LAYERS FOR SEMICONDUCTOR DEVICES - A method of forming a semiconductor device includes patterning a photoresist layer formed over a homogeneous semiconductor device layer to be etched; subjecting the semiconductor device to an implant process that selectively implants a sacrificial etch stop layer that is self-aligned in accordance with locations of features to be etched within the homogeneous semiconductor device layer, and at a desired depth for the features to be etched; etching a feature pattern defined by the patterned photoresist layer into the homogenous semiconductor device layer, stopping on the implanted sacrificial etch stop layer; and removing remaining portion of the implanted sacrificial etch stop layer prior to filling the etched feature pattern with a fill material. | 04-21-2011 |
20110159687 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes forming a plurality of plugs over a die region and an edge bead removal (EBR) region of a wafer, forming metal lines coupled to the plugs, removing the metal lines in the EBR region, forming an inter-layer dielectric layer over the wafer, and forming a plurality of contact holes that expose the metal lines by selectively etching the inter-layer dielectric layer through a dry etch process using a plasma etch device. | 06-30-2011 |
20110294291 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes a switch element provided in a surface area of a semiconductor substrate, a contact plug with an upper surface and a lower surface, and a function element provided on the upper surface of the contact plug. The lower surface of the contact plug is connected to the switch element. The upper surface of the contact plug has a maximum roughness of 0.2 nm or less. | 12-01-2011 |
20120196439 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME - In a method of forming a conductive pattern structure of a semiconductor device, a first insulating interlayer is formed on a substrate. A first wiring is formed to pass through the first insulating interlayer. An etch stop layer and a second insulating interlayer are sequentially formed on the first insulating interlayer. A second wiring is formed to pass through the second insulating interlayer and the etch stop layer. A dummy pattern is formed to pass through the second insulating layer and the etch stop layer at the same time as forming the second wiring. The second wiring is electrically connected to the first wiring. The dummy pattern is electrically isolated from the second wiring. | 08-02-2012 |
20130005144 | ELECTRONIC DEVICE - An electronic device is disclosed. In one embodiment, the electronic device includes a substrate, a plurality of conducting lines formed on a first conducting material that is disposed on the substrate, and a layer of a second conducting material disposed on the plurality of conducting lines. The conducting lines include a top face and a side face. The layer of the second conducting material includes a first thickness disposed on each of the top faces and a second thickness disposed on each of the side faces. To this end, the first thickness is greater than the second thickness. | 01-03-2013 |
20130005145 | METHODS OF FORMING A METAL PATTERN - A method of forming a metal pattern includes depositing a metal material over a photosensitive, insulative material and into a trench positioned over a bond pad. A photoresist material having a substantially planar surface may be formed over the metal material. A portion of the photoresist material may be etched to expose the metal material outside of the trench. The metal material may be isotropically etched to leave sidewalls of the metal protruding above surfaces of the photosensitive, insulative material outside of the trench. Some methods include removing a portion of a dielectric material to form at least one trench. Metal material and photoresist material may be deposited over the trench. A portion of the photoresist material may be etched to expose areas of the metal material. The metal material may be etched to form sidewalls of the metal material that protrude above the dielectric material. | 01-03-2013 |
20130012021 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes forming an interlayer dielectric film that has first and second trenches on first and second regions of a substrate, respectively, forming a first metal layer along a sidewall and a bottom surface of the first trench and along a top surface of the interlayer dielectric film in the first region, forming a second metal layer along a sidewall and a bottom surface of the second trench and along a top surface of the interlayer dielectric film in the second region, forming a first sacrificial layer pattern on the first metal layer such that the first sacrificial layer fills a portion of the first trench, forming a first electrode layer by etching the first metal layer and the second metal layer using the first sacrificial layer pattern, and removing the first sacrificial layer pattern. | 01-10-2013 |
20130023118 | METHOD FOR FORMING PATTERN AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE USING THE SAME - There is provided a method for forming a pattern comprising, forming a first layer on an underlying layer including a substrate, forming a first mask pattern including a first opening pattern on the first layer, and forming a second mask pattern including a second opening pattern on the first mask pattern, wherein the second opening pattern includes a first region overlapping the first opening pattern and a second region not overlapping the first opening pattern, and etching is performed using the second mask pattern such that a third opening pattern corresponding to the first region and exposing an upper surface of the underlying layer is formed in the first layer, and a fourth opening pattern corresponding to the second region is formed in the first mask pattern. | 01-24-2013 |
20130065394 | Process for Forming Contact Plugs - A method includes forming an etch stop layer over and contacting a gate electrode of a transistor, forming a sacrificial layer over the etch stop layer, and etching the sacrificial layer, the etch stop layer, and an inter-layer dielectric layer to form an opening. The opening is then filled with a metallic material. The sacrificial layer and excess portions of the metallic material over a top surface of the etch stop layer are removed using a removal step including a CMP process. The remaining portion of the metallic material forms a contact plug. | 03-14-2013 |
20130072017 | Lithographic Method for Making Networks of Conductors Connected by Vias - A method of lithography for formation of two networks of conductors connected by vias in microelectronic integrated circuits comprises, after formation of a first network of buried conductors under an insulating layer: deposition and etching of a sacrificial layer on a substrate, formation of spacers along all edges of elements of the sacrificial layer; removal of this layer; etching of a masking layer. Then, two successive etchings of the insulating layer are carried out, over two successive depths, one defining the depth of the conductors of the second network, the other defining a complement of depth needed at the desired locations for the vias. One of the etchings is defined by the masking layer and corresponds to the locations of the conductors of the second network; the other is defined both by the spacers and by openings in a layer etched by lithography and corresponds to the locations of the vias. Lastly, following the two etchings, the regions etched into the insulating material of the substrate are filled with a conductive material which forms the conductors and the vias at the same time. | 03-21-2013 |
20130095656 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes a switch element provided in a surface area of a semiconductor substrate, a contact plug with an upper surface and a lower surface, and a function element provided on the upper surface of the contact plug. The lower surface of the contact plug is connected to the switch element. The upper surface of the contact plug has a maximum roughness of 0.2 nm or less. | 04-18-2013 |
20130171820 | METHODS FOR THREE-DIMENSIONAL INTEGRATED CIRCUIT THROUGH HOLE VIA GAPFILL AND OVERBURDEN REMOVAL - Presented are methods and systems for fabricating three-dimensional integrated circuits having large diameter through-hole vias. One embodiment of the present invention provides a method of processing a wafer having holes for through-hole vias. The method comprises plating a gapfill metal on the wafer. The method also comprises chemically or electrochemically deplating a portion of the overburden metal. The method further comprises using chemical mechanical planarization to planarize the gapfill metal and to remove the remaining overburden metal. Another embodiment of the present invention is an integrated system comprising a process chamber for containing the wafer, a plating component integrated with the process chamber, and a deplating component integrated with the process chamber. The plating component is configured to electrochemically plate a gapfill metal onto the wafer to a least partially fill the holes. The deplating component is configured to chemically or to electrochemically remove a portion of the overburden metal formed by the plating component. | 07-04-2013 |
20130237055 | METHOD OF REDISTRIBUTING FUNCTIONAL ELEMENT - According to a method of redistributing a functional element of the present invention, an insulating resin layer is supplied onto a functional element wafer such as an LSI. A portion to be a via hole on an electrode pad of the functional element is filled with a sacrificial layer. The top of the sacrificial layer filled in the via hole is exposed from the insulating layer by grinding or polishing. Therefore, it is possible to prevent breakage of a brittle material such as a low-k material in the functional element, which would be caused by transmission of shearing stress when a conventional pillar or a conventional gold projecting electrode is used. The reliability, the yield, and the level of flatness can be improved by forming an interconnection conductive layer after the flattening process of grinding or polishing. Accordingly, a fine conductive interconnection can be formed. | 09-12-2013 |
20130244426 | METHOD FOR OBTAINING EXTREME SELECTIVITY OF METAL NITRIDES AND METAL OXIDES - Methods for etching metal nitrides and metal oxides include using ultradilute HF solutions and buffered, low-pH HF solutions containing a minimal amount of the hydrofluoric acid species H | 09-19-2013 |
20130302981 | Semiconductor Constructions And Methods Of Forming Patterns - Some embodiments include methods of forming patterns. A semiconductor substrate is formed to comprise an electrically insulative material over a set of electrically conductive structures. An interconnect region is defined across the electrically conductive structures, and regions on opposing sides of the interconnect region are defined as secondary regions. A two-dimensional array of features is formed over the electrically insulative material. The two-dimensional array extends across the interconnect region and across the secondary regions. A pattern of the two-dimensional array is transferred through the electrically insulative material of the interconnect region to form contact openings that extend through the electrically insulative material and to the electrically conductive structures, and no portions of the two-dimensional array of the secondary regions is transferred into the electrically insulative material. | 11-14-2013 |
20140154882 | METHODS FOR FABRICATING A SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes forming a device isolation layer pattern on a substrate to form an active region, the active region including a first contact forming region at a center p of the active region and second and third contact forming regions at edges of the active region, forming an insulating layer and a first conductive layer on the substrate, forming a mask pattern having an isolated shape on the first conductive layer, etching the first conductive layer and the insulating layer to expose the active region of the first contact forming region by using the mask pattern, to form an opening portion between pillar structures, forming a second conductive layer in the opening, and patterning the second conductive layer and the first preliminary conductive layer pattern to form a wiring structure contacting the first contact forming region and having an extended line shape. | 06-05-2014 |
20150056805 | METHODS OF FORMING SEMICONDUCTOR DEVICE USING BOWING CONTROL LAYER - A bowing control pattern is formed on an intermediate layer. A hardmask pattern is formed on the bowing control layer. The hardmask pattern has a first opening, and the bowing control pattern has a second opening. A third opening passes through the intermediate layer and is connected to the second opening. The bowing control pattern includes first and second edges on a lower end of the second opening, and a third edge on an upper end of the second opening. When a first point on the first edge, a second point on the second edge, and a third point on a horizontal line passing through the third edge are defined, an intersecting angle between a first side from the first point to the second point, and a second side from the second point to the third point is from about 50° to about 80°. | 02-26-2015 |
20160005601 | INTEGRATED CIRCUIT FABRICATION - A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a first region of a substrate. The method further comprises using pitch multiplication to produce at least two features in a lower masking layer for each feature in the photoresist layer. The features in the lower masking layer include looped ends. The method further comprises covering with a second photoresist layer a second region of the substrate including the looped ends in the lower masking layer. The method further comprises etching a pattern of trenches in the substrate through the features in the lower masking layer without etching in the second region. The trenches have a trench width. | 01-07-2016 |
20160181155 | METHOD FOR MAKING AN INTEGRATED CIRCUIT IN THREE DIMENSIONS | 06-23-2016 |