Class / Patent application number | Description | Number of patent applications / Date published |
438671000 | Utilizing multilayered mask | 21 |
20080268639 | Method of Manufacturing A Semiconductor Integrated Circuit Device - In forming five trenches buried with an intermediate conductive layer for connecting transfer MISFETs and driving MISFETs with vertical MISFETs formed thereover, in which the second and third trenches, and the first, fourth, and fifth trenches are formed separately by twice etching using first and second photoresist films as a mask. Since all the trenches can be formed at a good accuracy even in a case where the shortest distance between the first trench and the second or third trench, and the shortest distance between the second or third trench and the fourth trench is smaller than the resolution limit for the exposure light, the distance between each of the five trenches arranged in one identical memory cell can be reduced to be smaller than resolution limit for the exposure light. | 10-30-2008 |
20080286967 | METHOD FOR FABRICATING A BODY TO SUBSTRATE CONTACT OR TOPSIDE SUBSTRATE CONTACT IN SILICON-ON-INSULATOR DEVICES - A method of forming an electrical contact between an active semiconductor device layer and a base substrate. The method includes forming a first masking layer over an uppermost surface of the active semiconductor layer, patterning a window in the masking layer, and etching an opening down to the base substrate within an area defined by the window. The opening is filled with a semiconductor contact material while simultaneously adding a dopant to the semiconductor contact material thereby forming an electrical contact between the active semiconductor device layer and the base substrate. | 11-20-2008 |
20090117737 | POLYCONDUCTOR LINE END FORMATION AND RELATED MASK - Methods of forming adjacent polyconductor line ends and a mask therefor are disclosed. In one embodiment, the method includes forming a polyconductor layer over an isolation region; forming a mask over the polyconductor layer, the mask including shapes to create the polyconductor line ends and a correction element to ensure a designed proximity of the polyconductor line ends; and etching the polyconductor layer using the patterned photoresist mask to create the adjacent polyconductor line ends, wherein the correction element is removed during the etching. | 05-07-2009 |
20100035431 | Reticle Stages for Lithography Systems and Lithography Methods - Reticle stages for lithography systems and lithography methods are disclosed. In a preferred embodiment, a lithography reticle stage includes a first region adapted to support a first reticle, and at least one second region adapted to support a second reticle. | 02-11-2010 |
20110021022 | METHOD OF MANUFACTURING A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - In forming five trenches buried with an intermediate conductive layer for connecting transfer MISFETs and driving MISFETs with vertical MISFETs formed thereover, in which the second and third trenches, and the first, fourth, and fifth trenches are formed separately by twice etching using first and second photoresist films as a mask. Since all the trenches can be formed at a good accuracy even in a case where the shortest distance between the first trench and the second or third trench, and the shortest distance between the second or third trench and the fourth trench is smaller than the resolution limit for the exposure light, the distance between each of the five trenches arranged in one identical memory cell can be reduced to be smaller than resolution limit for the exposure light. | 01-27-2011 |
20110151668 | PITCH DIVISION PATTERNING TECHNIQUES - Embodiments of the invention comprise pitch division techniques to extend the capabilities of lithographic techniques beyond their minimum pitch. The pitch division techniques described herein employ additional processing to ensure pitch divided lines have the spatial isolation necessary to prevent shorting problems. The pitch division techniques described herein further employ processing acts to increase the structural robustness of high aspect ratio features. | 06-23-2011 |
20110159686 | METHOD FOR FORMING FINE PATTERN HAVING VARIABLE WIDTH AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAME - A method for forming a fine pattern having a variable width by simultaneously using an optimal focused electron beam and a defocused electron beam in a light exposure process Includes, after forming a first film on a substrate, forming a first film pattern including a first level area and a second level area having different distances from the substrate by changing a profile of an upper surface of the first film. A photoresist film having a first area covering the first level area and a second area covering the second level area is formed. To simultaneously light-expose the first area and the second area with the same width, a light exposure condition, in which an optimal focused electron beam is eradiated on the first area and a defocused electron beam is eradiated on the second area, is applied. A plurality of photoresist patterns continuously extending over the first level area and the second level area with different widths on the first level area and the second level area are formed by developing the light-exposed photoresist film. | 06-30-2011 |
20130059437 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, a method for manufacturing a semiconductor device includes forming a film containing boron on a semiconductor substrate, forming a film containing silicon oxide on the film containing boron, patterning the film containing silicon oxide and etching the film containing boron with a gas containing chlorine by using the patterned film containing silicon oxide as a mask. | 03-07-2013 |
20130102151 | METHODS OF MANUFACTURING NAND FLASH MEMORY DEVICES - A NAND flash memory device includes a plurality of continuous conductors disposed on a common level of a multilayer substrate, the plurality of continuous conductors including respective conductive lines extending in parallel along a first direction, respective contact pads disposed at ends of the respective conductive lines and respective conductive dummy lines extending in parallel from the contact pads along a second direction | 04-25-2013 |
20130149862 | METHOD FOR FORMING FINE PATTERN HAVING VARIABLE WIDTH AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAME - A method for forming a fine pattern having a variable width by simultaneously using an optimal focused electron beam and a defocused electron beam in a light exposure process Includes, after forming a first film on a substrate, forming a first film pattern including a first level area and a second level area having different distances from the substrate by changing a profile of an upper surface of the first film. A photoresist film having a first area covering the first level area and a second area covering the second level area is formed. To simultaneously light-expose the first area and the second area with the same width, a light exposure condition, in which an optimal focused electron beam is eradiated on the first area and a defocused electron beam is eradiated on the second area, is applied. A plurality of photoresist patterns continuously extending over the first level area and the second level area with different widths on the first level area and the second level area are formed by developing the light-exposed photoresist film. | 06-13-2013 |
20130157461 | METHOD FOR FABRICATING SEMICONDUCTOR MEMORY DEVICE - A method for fabricating a semiconductor device includes forming an etch-target layer over a substrate having a first region and a second region, stacking first and second hard mask layers over the etch-target layer, forming spacer patterns over the second hard mask layer of the first area, etching the second hard mask layer using the spacer patterns as an etch barrier, forming a hard mask pattern over the first hard mask layer of the second region, etching the first hard mask layer using the second hard mask layer of the first region and the hard mask pattern of the second region as etch barriers, removing the hard mask pattern of the second region, and etching the etch-target layer using the first and second hard mask layers of the first region and the first hard mask layer of the second region as etch barriers. | 06-20-2013 |
20140065822 | METHOD FOR FORMING PATTERN - A method for forming a pattern according to an embodiment, includes forming a first film pattern having a wide width dimension above a processed film; forming a second film pattern covering a portion of the first film pattern and a third film pattern connected to the second film pattern together above the processed film, the third film pattern having a width dimension narrower than the first film pattern, and to be a line pattern of a line and space pattern; forming a fourth film pattern on a side face of the first film pattern and a plurality of film patterns by the fourth film to be a line pattern of a line and space pattern on both side faces of the third film pattern; and removing the second film pattern and the third film pattern. | 03-06-2014 |
20140273447 | COMPOSITION FOR FORMING TITANIUM-CONTAINING RESIST UNDERLAYER FILM AND PATTERNING PROCESS - The invention provides a composition for forming a titanium-containing resist underlayer film comprising: as a component (A), compounds selected from titanium compounds represented by the following general formulae (A-1) and (A-2) and a titanium-containing compound obtained by hydrolysis and/or condensation of the titanium compounds, as a component (B), compounds selected from titanium compounds represented by the following general formulae (B-1) and (B-2) and a titanium-containing compound obtained by hydrolysis and/or condensation of the titanium compounds, and as a component (D), solvent. There can be provided a composition for forming a titanium-containing resist underlayer film to form a resist underlayer film having favorable pattern adhesiveness and excellent etching selectivity. | 09-18-2014 |
20140273448 | COMPOSITION FOR FORMING TITANIUM-CONTAINING RESIST UNDERLAYER FILM AND PATTERNING PROCESS - The invention provides a composition for forming a titanium-containing underlayer film comprising: as a component (A), a titanium-containing compound obtained by reacting a divalent or a trivalent alcohol represented by the following general formula (A-2) to one or more kinds of compounds selected from a titanium compound represented by the following general formula (A-1) and a titanium-containing compound obtained by hydrolysis and/or condensation of the titanium compound and as a component (C), solvent. There can be provided a composition for forming a titanium-containing underlayer film that is excellent in storage stability without changes in characteristics, pattern adhesiveness relative to a fine pattern, and etching selectivity relative to conventional organic film and silicon-containing film. | 09-18-2014 |
20150017804 | METHOD OF FORMING A PATTERN IN A SEMICONDUCTOR DEVICE AND METHOD OF FORMING A GATE USING THE SAME - A method of forming a pattern in a semiconductor device is described. A substrate divided into cell and peripheral regions is provided, and an object layer is formed on a substrate. A buffer pattern is formed on the object layer in the cell region along a first direction. A spacer is formed along a sidewall of the buffer pattern in the cell region, and a hard mask layer remains on the object layer in the peripheral region. The buffer layer is removed, and the spacer is separated along a second direction different from the first direction, thereby forming a cell hard mask pattern. A peripheral hard mask pattern is formed in the peripheral region. A minute pattern is formed using the cell and peripheral hard mask patterns in the substrate. Therefore, a line width variation or an edge line roughness due to the photolithography process is minimized. | 01-15-2015 |
20150037977 | MASK AND PATTERN FORMING METHOD - According to one embodiment, a mask includes a line-and-space mask pattern. The mask has a separation portion separating a line pattern in a predetermined region within the line-and-space mask pattern. The mask also includes a connection pattern arranged in a crossing direction crossing the extending direction of the line pattern connecting the separated line patterns. The connection pattern is arranged on a position where the end of the line pattern, which is separated by the separation portion, projects from the connection pattern. | 02-05-2015 |
20150093897 | Methods of Fabricating Semiconductor Devices - Semiconductor devices and methods of fabricating the same are provided. The methods include preparing a template having a three dimensional (3D) stair type structure formed in intaglio, forming an imprint pattern having the stair type structure using the template, and simultaneously forming stair type patterns on a substrate using the imprint pattern. | 04-02-2015 |
20150140813 | Methods of Forming Non-Volatile Memory Devices Including Vertical NAND Strings - A NAND based non-volatile memory device can include a plurality of memory cells vertically arranged as a NAND string and a plurality of word line plates each electrically connected to a respective gate of the memory cells in the NAND string. A plurality of word line contacts can each be electrically connected to a respective word line plate, where the plurality of word line contacts are aligned to a bit line direction in the device. | 05-21-2015 |
20160005624 | METHOD OF FORMING A PATTERN IN A SEMICONDUCTOR DEVICE AND METHOD OF FORMING A GATE USING THE SAME - A method of forming a pattern in a semiconductor device is described. A substrate divided into cell and peripheral regions is provided, and an object layer is formed on a substrate. A buffer pattern is formed on the object layer in the cell region along a first direction. A spacer is formed along a sidewall of the buffer pattern in the cell region, and a hard mask layer remains on the object layer in the peripheral region. The buffer layer is removed, and the spacer is separated along a second direction different from the first direction, thereby forming a cell hard mask pattern. A peripheral hard mask pattern is formed in the peripheral region. A minute pattern is formed using the cell and peripheral hard mask patterns in the substrate. Therefore, a line width variation or an edge line roughness due to the photolithography process is minimized. | 01-07-2016 |
20160027681 | HARD-MASK DEFINED BIT PATTERN SUBSTRATE - Provided is an apparatus that includes a substrate; a first hard-mask pattern that includes a number of first features disposed over a top surface of the substrate; and a second hard-mask pattern disposed over the first hard-mask layer. The second hard-mask pattern includes a number of second features overlapping one or more of the first features. | 01-28-2016 |
20160126137 | COMBINING CUT MASK LITHOGRAPHY AND CONVENTIONAL LITHOGRAPHY TO ACHIEVE SUB-THRESHOLD PATTERN FEATURES - Features are fabricated on a semiconductor chip. The features are smaller than the threshold of the lithography used to create the chip. A method includes patterning a first portion of a feature (such as a local interconnect) and a second portion of the feature to be separated by a predetermined distance, such as a line tip to tip space or a line space. The method further includes patterning the first portion with a cut mask to form a first sub-portion (e.g., a contact) and a second sub-portion. A dimension of the first sub-portion is less than a dimension of a second predetermined distance, which may be a line length resolution of a lithographic process having a specified width resolution. A feature of a semiconductor device includes a first portion and a second portion having a dimension less than a lithographic resolution of the first portion. | 05-05-2016 |