Entries |
Document | Title | Date |
20080200028 | METHODS OF POSITIONING AND/OR ORIENTING NANOSTRUCTURES - Methods of positioning and orienting nanostructures, and particularly nanowires, on surfaces for subsequent use or integration. The methods utilize mask based processes alone or in combination with flow based alignment of the nanostructures to provide oriented and positioned nanostructures on surfaces. Also provided are populations of positioned and/or oriented nanostructures, devices that include populations of positioned and/or oriented nanostructures, systems for positioning and/or orienting nanostructures, and related devices, systems and methods. | 08-21-2008 |
20080261395 | Semiconductor Device, Method for Manufacturing Semiconductor Devices and Mask Systems Used in the Manufacturing of Semiconductor Devices - Semiconductor device with a first structure comprising a plurality of at least in part parallel linear structures, a second structure comprising a plurality of pad structures, forming at least in part one of the group of linear structure, curved structure, piecewise linear structure and piecewise curved structure which is positioned at an angle to the first structure, and the plurality of pad structures are intersecting at least one of the linear structures in the first structure. An electronic device with at least one semiconductor device, methods for manufacturing a semiconductor device and a mask system are also covered. | 10-23-2008 |
20080274612 | SHIELDED CAPACITOR STRUCTURE - A method and apparatus if provided for shielding a capacitor structure formed in a semiconductor device. In a capacitor formed in an integrated circuit, one or more shields are disposed around layers of conductive strips to shield the capacitor. The shields confine the electric fields between the limits of the shields. | 11-06-2008 |
20080293244 | Methods of Positioning and/or Orienting Nanostructures - Methods of positioning and orienting nanostructures, and particularly nanowires, on surfaces for subsequent use or integration. The methods utilize mask based processes alone or in combination with flow based alignment of the nanostructures to provide oriented and positioned nanostructures on surfaces. Also provided are populations of positioned and/or oriented nanostructures, devices that include populations of positioned and/or oriented nanostructures, systems for positioning and/or orienting nanostructures, and related devices, systems and methods. | 11-27-2008 |
20080318419 | CHARGE DISSIPATION OF CAVITIES - Structures and methods for the dissipation of charge build-up during the formation of cavities in semiconductor substrates. | 12-25-2008 |
20090017620 | Method of manufacturing semiconductor device for dual damascene wiring - A method of manufacturing a semiconductor device includes forming a via hole in an interlayer dielectric film, forming a wiring trench in said interlayer dielectric film for connecting to the via hole, and forming a dual damascene wiring trench in the interlayer dielectric film for forming a dual damascene wiring which is connected to a conductive film. In forming the via hole, the via hole is formed in a bow shape and, in forming the wiring trench, the wiring trench is formed by etching to a position where a diameter of the via hole becomes substantially a maximum to provide a via having a forward taper shape under the wiring trench. | 01-15-2009 |
20090068837 | LINE ENDS FORMING - Methods of forming line ends and a related memory cell including the line ends are disclosed. In one embodiment, the method includes forming a first device element and a second device element separated from the first device element by a space; and forming a first line extending from the first device element, the first line including a bulbous line end over the space and distanced from the first device element, and a second line extending from the second device element, the second line including a bulbous line end over the space and distanced from the second device element. | 03-12-2009 |
20090104771 | METHOD FOR MAKING A SELF-CONVERGED VOID AND BOTTOM ELECTRODE FOR MEMORY CELL - A base layer, comprising an electrically conductive element, is formed. An upper layer, including a third, lower planarization stop layer, a second layer and a first, upper layer is formed on the base layer. A keyhole opening is formed through the upper layer to expose a surface of an electrically conductive element in the base layer. The first layer has an overhanging portion extending into the opening so that the opening in the first layer is shorter than in the second layer. A dielectric material is deposited into the keyhole opening to create a self-converged void within the deposited dielectric material. In some examples the keyhole forming step comprises increasing the volume of the first layer while in other examples the keyhole forming step comprises etching back the second layer. | 04-23-2009 |
20090149023 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE HAVING THREE-DIMENSIONAL STACKED STRUCTURE - A method of fabricating a semiconductor device having a three-dimensional stacked structure is provided, which realizes easily the electrical interconnection between the stacked semiconductor circuit layers along the stacking direction by using buried interconnections. | 06-11-2009 |
20090156000 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device is provided, which includes forming a coated film by coating a solution containing a solvent and an organic component above an insulating film located above a semiconductor substrate and having a recess, baking the coated film at a first temperature which does not accomplish cross-linking of the organic component to obtain an organic film precursor, polishing the organic film precursor using a first slurry containing first resin particles and a water-soluble polymer to planarize a surface of the organic film precursor, and polishing the organic film precursor where the surface is planarized using a second slurry containing second resin particles and a water-soluble polymer to leave the organic film precursor in the recess, thereby exposing the insulating film, an average particle diameter of the second resin particles being smaller than that of the first resin particles. | 06-18-2009 |
20090221143 | METHOD OF CLEANING AND PROCESS FOR PRODUCING SEMICONDUCTOR DEVICE - A method of cleaning for removing metal compounds attached to a surface of a substrate, wherein the cleaning is conducted by supplying a supercritical fluid of carbon dioxide comprising at least one of triallylamine and tris(3-aminopropyl)amine to the surface of the substrate and a process for producing a semiconductor device using the method of cleaning are provided. In accordance with the method of cleaning and the method for producing a semiconductor device using the method, etching residues or polishing residues containing metal compounds are efficiently removed selectively from the electroconductive material forming the electroconductive layer. When the electroconductive layer is a wiring, an increase in resistance due to residual metal compounds can be suppressed, and an increase in the leak current due to diffusion of the metal from the metal compounds to the insulating film can be prevented. Therefore, reliability on the wiring is improved, and the yield of the semiconductor device can be increased. | 09-03-2009 |
20090280646 | MANUFACTURING METHOD FOR MICRO-TRANSFORMERS - A micro-transformer manufacturing method is provided, which can improve throughput, prevent a crack from entering an insulating film between coils, and manufacture the micro-transformer without using a mask material having a high selection ratio. An insulating film is deposited on the whole face of a semiconductor substrate having an impurity-diffused region. This insulating film is partially removed to form a first opening and a second opening. A primary coil is formed such that a center pad contacts the impurity-diffused region through the first opening. A thin insulating film is deposited on the primary coil. An insulator material having a secondary coil formed thereon is adhered onto the insulating film on the primary coil by adhesive tape. The insulator material is sized to not cover both a pad, connected with the center pad of the primary coil through the impurity-diffused region, and an outer-end pad of the primary coil. | 11-12-2009 |
20090286394 | Method for Forming Self-Assembled Mono-Layer Liner for Cu/Porous Low-k Interconnections - A method for fabricating an integrated circuit comprises forming a low-k dielectric layer over a semiconductor substrate, etching the low-k dielectric layer to form an opening, and treating the low-k dielectric layer with a gaseous organic chemical to cause a reaction between the low-k dielectric layer and the gaseous organic chemical. The gaseous organic chemical is free from silicon. | 11-19-2009 |
20090286395 | Butted Source Contact and Well Strap - A butted contact structure forming a source contact electrically connecting a voltage node and a well region and method for forming the same, the butted contact structure including an active region having a well region disposed adjacent an electrical isolation region on a semiconductor substrate; a MOSFET device including a source and drain region on the active region; and, a conductive contact having a first portion formed to the source region and a second portion formed through the electrical isolation region to the doped well region. | 11-19-2009 |
20090305501 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE USING A CHEMICAL MECHANICAL POLISHING PROCESS - A method of fabricating a semiconductor device by using a chemical-mechanical polishing (CMP) process includes forming an insulating layer on a semiconductor wafer, etching the insulating layer to form via-holes, and forming a conductive layer on the insulating layer to fill the via-holes. The method further includes performing a first polishing process to etch the conductive layer until an upper surface of the insulating layer is exposed,, performing a second polishing process to etch the insulating layer to a predetermined thickness and performing a third polishing process to remove protrusions of the conductive layer. | 12-10-2009 |
20100003818 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device according to one embodiment includes: forming a porous film above a semiconductor substrate; forming an altered layer by applying alteration treatment to a first pattern region of the porous film up to a predetermined depth; forming a first concave portion by etching a second pattern region to a depth deeper than the predetermined depth, the second pattern region at least partially overlapping the first pattern region of the porous film having the altered layer formed therein; and forming a second concave portion by selectively removing the altered layer from the porous film after forming the first concave portion. | 01-07-2010 |
20100055899 | PARTICLE REDUCTION IN PECVD PROCESSES FOR DEPOSITING LOW-K MATERIAL BY USING A PLASMA ASSISTED POST-DEPOSITION STEP - When forming dielectric materials of reduced dielectric constant in sophisticated metallization systems, the creation of defect particles on the dielectric material may be reduced during a plasma enhanced deposition process by inserting an inert plasma step after the actual deposition step. | 03-04-2010 |
20100081278 | Methods for Nanoscale Feature Imprint Molding - Methods for fabricating nanoscale features are disclosed. One technique involves depositing onto a substrate, where the first layer may be a silicon layer and may subsequently be etched. A second layer and third layer may be deposited on the etch first layer, followed by the deposition of a silicon cap. The second and third layer may be etched, exposing edges of the second and third layers. The cap and first layer may be removed and either the second or third layer may be etched, creating a nanoscale pattern. | 04-01-2010 |
20100099253 | Method for Structuring a Layered Stack - One implementation is a method for fabricating a semiconductor on a substrate. A first layer is formed on the substrate. An implanted pattern is introduced into the first layer by implanting using a structured implantation mask arranged over the first layer. A structured second layer is formed on the first layer after removing the implantation mask. A first pattern is generated in the substrate using the second layer as a mask. The first layer is developed with regard to the implanted pattern. A second pattern is generated in the substrate using the first layer as a mask. | 04-22-2010 |
20100112809 | Multilevel imprint lithography - A mold with a protruding pattern is provided that is pressed into a thin polymer film via an imprinting process. Controlled connections between nanowires and microwires and other lithographically-made elements of electronic circuitry are provided. An imprint stamp is configured to form arrays of approximately parallel nanowires which have (1) micro dimensions in the X direction, (2) nano dimensions and nano spacing in the Y direction, and three or more distinct heights in the Z direction. The stamp thus formed can be used to connect specific individual nanowires to specific microscopic regions of microscopic wires or pads. The protruding pattern in the mold creates recesses in the thin polymer film, so the polymer layer acquires the reverse of the pattern on the mold. After the mold is removed, the film is processed such that the polymer pattern can be transferred on a metal/semiconductor pattern on the substrate. | 05-06-2010 |
20100112810 | Resistive random access memory and method for manufacturing the same - A resistive random access memory including, an insulating layer, a hard mask layer, a bottom electrode, a memory cell and a top electrode is provided. The insulating layer is disposed on the bottom electrode. The insulating layer has a contact hole having a first width. The hard mask layer has an opening. A portion of the memory cell is exposed from the opening and has a second width smaller than the first width. The top electrode is disposed on the insulating layer and is coupled with the memory cell. | 05-06-2010 |
20100130007 | BOTTOM UP PLATING BY ORGANIC SURFACE PASSIVATION AND DIFFERENTIAL PLATING RETARDATION - Embodiments of the present invention generally relates to an apparatus and a method for processing semiconductor substrates. One embodiment provides a method provides a method for processing a substrate comprising forming a seed layer over a substrate having trench or via structures formed therein, coating a portion of the seed layer with an organic passivation film, and immersing the trench or via structures in a plating solution to deposit a conductive material over the seed layer not covered by the organic passivation film. | 05-27-2010 |
20100144139 | Methods For Fabricating Semiconductor Components With Conductive Interconnects Having Planar Surfaces - A backside method for fabricating a semiconductor component with a conductive interconnect includes the step of providing a semiconductor substrate having a circuit side, a backside, and a substrate contact on the circuit side. The method also includes the steps of forming a substrate opening from the backside to the substrate contact, and then bonding the conductive interconnect to an inner surface of the substrate contact. | 06-10-2010 |
20100190337 | Method of Forming Metal Wirings of Semiconductor Device - A method of forming metal wirings of a semiconductor device includes providing a semiconductor substrate having a number of underlying conductive patterns separated from each other with a first insulating layer interposed between the underlying conductive patterns. The method also includes forming auxiliary patterns over the underlying conductive patterns, respectively, forming a second insulating layer over the first insulating layer to fill a space between the auxiliary patterns, removing the auxiliary patterns to form damascene patterns through which the underlying conductive patterns are respectively exposed, and filling interiors of the damascene patterns with a metal material. | 07-29-2010 |
20100210106 | SEMICONDUCTOR DEVICE HAVING A INTERLAYER INSULATION FILM WITH LOW DIELECTRIC CONSTANT AND HIGH MECHANICAL STRENGTH - A method for fabricating a semiconductor includes the steps of forming a porous insulation film and wires on a substrate, the wires embedded in the porous insulation film having a portion adjacent to the wires and a remote portion spaced apart from the wires; and applying an energy beam to the remote portion to change the structure of the porous insulation film such that an Young's modulus of the porous insulation film increased so as to substantially reinforce the strength of the porous insulation film. | 08-19-2010 |
20100210107 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device and a manufacturing method thereof are provided for the improvement of the reliability of copper damascene wiring in which a film between wiring layers and a film between via layers are comprised of an SiOC film with low dielectric constant. A film between wiring layers, a film between wiring layers, and a film between via layers are respectively comprised of an SiOC film, and stopper insulating films and a cap insulating film are comprised of a laminated film of an SiCN film A and an SiC film B. By doing so, it becomes possible to reduce the leakage current of the film between wiring layers, the film between wiring layers, and the film between via layers, and also possible to improve the adhesion of the film between wiring layers, the film between wiring layers, and the film between via layers to the stopper insulating films and the cap insulating film. | 08-19-2010 |
20100233877 | Method of disposing dummy pattern - A method of disposing a dummy pattern includes the steps of obtaining an inter-wiring parasitic capacity and a wiring total parasitic capacity for each wiring using wiring layout data and initial dummy pattern layout data; creating a first data base based on the inter-wiring parasitic capacity; creating a second data base based on the wiring total parasitic capacity; performing dynamic and static simulations for creating a third data base storing the results of the dynamic and static simulations, the result of the dynamic simulation being information about the first wiring, and the result of the static simulation being information about the second wiring; and performing an additional insertion of dummy pattern near a third wiring, the third wiring being determined to be a wiring which is capable of be affected by voltage noise based on the data in the third data base. | 09-16-2010 |
20100273325 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device may include, but is not limited to the following processes. A mask layer is formed over a gate electrode portion and a wiring portion adjacent to the gate electrode portion. The mask layer includes a first portion covering the wiring portion. Then, at least a part of the first portion is removed. | 10-28-2010 |
20100279504 | INTEGRATED CIRCUIT PACKAGE SYSTEM INCLUDING HONEYCOMB MOLDING - A method of manufacture of an integrated circuit package system includes: providing a substrate with a top surface; configuring the top surface to include electrical contacts and an integrated circuit; providing a structure over the substrate with only a honeycomb meshwork of posts contacting the top surface of the substrate; and depositing a material to prevent warpage of the substrate on the top surface of the substrate and over the integrated circuit, the material patterned to have discrete hollow conduits that expose the electrical contacts. | 11-04-2010 |
20100285661 | SEMICONDUCTOR ELEMENT AND DISPLAY DEVICE USING THE SAME - Provided is a semiconductor element including: a semiconductor having an active layer; a gate insulating film which is in contact with the semiconductor, a gate electrode opposite to the active layer through the gate insulating film; a first nitride insulating film formed over the active layer; a photosensitive organic resin film formed on the first nitride insulating film; a second nitride insulating film formed on the photosensitive organic resin film; and a wiring provided on the second nitride insulating film, in which a first opening portion is provided in the photosensitive organic resin film, an inner wall surface of the first opening portion is covered with the second nitride insulating film, a second opening portion is provided in a laminate including the gate insulating film, the first nitride insulating film, and the second nitride insulating film inside the first opening portion, and the semiconductor is connected with the wiring through the first opening portion and the second opening portion. | 11-11-2010 |
20100304564 | SELECTIVE LOCAL INTERCONNECT TO GATE IN A SELF ALIGNED LOCAL INTERCONNECT PROCESS - A semiconductor device fabrication process includes forming a gate of a transistor on a semiconductor substrate using a hard mask. The hard mask is selectively removed in one or more selected regions over the gate. The removal of the hard mask in the selected regions allows the gate to be connected to an upper metal layer through at least one insulating layer located substantially over the transistor. Conductive material is deposited in one or more trenches formed through the at least one insulating layer. The conductive material forms a local interconnect to the gate in at least one of the selected regions. | 12-02-2010 |
20100311239 | Method for forming dual damascene pattern - A method for forming a dual damascene pattern includes preparing a multi-functional hard mask composition including a silicon resin as a base resin, wherein the silicon resin comprises about 20 to 45% silicon molecules by weight, based on a total weight of the resin; forming a deposition structure by sequentially forming a self-arrangement contact (SAC) insulating film, a first dielectric film, an etching barrier film, and a second dielectric film over a hardwiring layer; etching the deposition structure to expose the hardwiring layer, thereby forming a via hole; coating the multi-functional hard mask composition over the second dielectric film and in the via hole to form a multi-functional hard mask film; and etching the resulting structure to expose a part of the first dielectric film using a photoresist pattern as an etching mask, thereby forming a trench having a width greater than that of the via hole. | 12-09-2010 |
20100330802 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A semiconductor manufacturing method includes forming a word line crossing with an active region on a semiconductor substrate; forming a diffusion layer region; forming a first insulating film as high as a bit line to be formed; etching the first insulating film, while using, as a mask, a pattern having a linear aperture extending to the active region on the first insulating film so as to form a groove pattern for exposing the surface of the semiconductor substrate; embedding a conductive film in the groove pattern; forming a mask pattern passing over a portion, in which a bit contact is formed, on the first insulating film; and removing the first insulating film and the conductive layer until the upper layer insulating film of the word line is exposed, while using the mask pattern as a mask so as to isolate a bit contact from another contact. | 12-30-2010 |
20110027989 | INCREASED DENSITY OF LOW-K DIELECTRIC MATERIALS IN SEMICONDUCTOR DEVICES BY APPLYING A UV TREATMENT - A silicon-based low-k dielectric material is formed on the basis of a single precursor material, such as OMTCS, without incorporating a porogen species. To this end, the initial deposition of the low-k dielectric material may be formed on the basis of a reduced process temperature, while a subsequent treatment, such as a UV treatment, may allow the adjustment of the final material characteristics without causing undue out-gassing of volatile organic components. | 02-03-2011 |
20110053371 | SEMICONDUCTOR PROCESS - A semiconductor manufacturing process is provided. First, a substrate is provided, wherein a patterned conductive layer, a dielectric layer and a patterned metal hard mask layer are sequentially formed thereon. Thereafter, a portion of the dielectric layer is removed to form a damascene opening exposing the patterned conductive layer. Afterwards, the dielectric layer is heated to above 200° C. Thereafter, a plasma treatment process is performed on the damascene opening, wherein the gases used to generate the plasma include hydrogen gas and inert gas. Afterwards, a conductive layer is formed in the damascene opening to fill therein. | 03-03-2011 |
20110065275 | Methods of manufacturing semiconductor devices - Provided are methods of manufacturing semiconductor devices by which two different kinds of contact holes with different sizes are formed using one photolithography process. The methods include preparing a semiconductor substrate in which an active region is titled in a diagonal direction. A hard mask is formed on the entire surface of the semiconductor substrate. A mask hole is patterned not to overlap a word line. A first oxide layer is deposited on the hard mask, and the hard mask is removed to form a piston-shaped sacrificial pattern. A first polysilicon (poly-Si) layer is deposited on the sacrificial pattern and patterned to form a cylindrical first sacrificial mask surrounding the piston-shaped sacrificial pattern. A second oxide layer is coated on the first sacrificial mask to such an extent as to form voids. A second poly-Si layer is deposited in the voids and patterned to form a pillar-shaped second sacrificial mask. The second oxide layer is removed to expose the active region. The sectional area of a buried contact (BC) storage contact pad may be increased, while the sectional area of a direct contact (DC) bit line contact pad may be reduced. | 03-17-2011 |
20110081776 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A first insulating film is formed on or above a substrate, and a first conductor is formed in an upper portion of the formed first insulating film. Then, a second insulating film is formed on the first insulating film so as to cover the first conductor. Then, a film quality alteration process is performed for the second insulating film. Moreover, a third insulating film is formed on the second insulating film, and a curing process is performed for the formed third insulating film. | 04-07-2011 |
20110104894 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes etching a semiconductor substrate using a hard mask layer as a barrier to form a trench defining a plurality of active regions, forming a gap-fill layer to gap-fill a portion of the inside of the trench so that the hard mask layer becomes a protrusion, forming spacers covering both sides of the protrusion, removing one of the spacers using a doped etch barrier as an etch barrier, and etching the gap-fill layer using a remaining spacer as an etch barrier to form a side trench exposing one side of the active region. | 05-05-2011 |
20110159684 | SRAM CELL WITH T-SHAPED CONTACT - An integrated circuit containing an array of SRAM cells with T-shaped contacts in the inverters, in which drain connecting segments may extend beyond gate connecting segments by a distance greater than 10 percent of a separation distance between ends of opposite drain connecting segments. The drain connecting segments may also extend beyond gate connecting segments by a distance greater than one-third of the width of the gate connecting segments. A process of forming an integrated circuit containing an array of SRAM cells with T-shaped contacts in which drain connecting segments may extend beyond gate connecting segments by a distance greater than 10 percent of a separation distance between ends of opposite drain connecting segments. A process may also form the drain connecting segments to extend beyond gate connecting segments by greater than one-third of the width of the gate connecting segments. | 06-30-2011 |
20110294290 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A three-dimensional semiconductor memory device includes a stacked structure including a plurality of conductive patterns, an active pillar penetrating the stacked structure, and a data storage pattern between the active pillar and the conductive patterns, wherein the active pillar includes a vertical semiconductor pattern penetrating the stacked structure and protruding semiconductor patterns between the vertical semiconductor pattern and the data storage pattern, the protruding semiconductor patterns having a different crystalline structure from that of the vertical semiconductor pattern. | 12-01-2011 |
20110306206 | Methods Of Forming Contact Openings And Methods Of Increasing Contact Area In Only One Of X and Y Axes In The Fabrication Of Integrated Circuitry - A method of forming contact openings in the fabrication of integrated circuitry includes forming a mask which includes at least one of photoresist and amorphous carbon received over a plurality of spaced conductive line constructions. The conductive line constructions include insulative caps and insulative sidewalls. The mask includes a plurality of spaced lines and trench spaces between adjacent of the spaced lines. The spaced lines and the trench spaces angle relative to the conductive line constructions. The trench spaces are received over node locations which are received between adjacent of the conductive line constructions. The at least one of photoresist and amorphous carbon is treated with a plasma to reduce lateral width of the spaced lines and to increase lateral width of the trench spaces. After the treating, contact openings are etched to the node locations selectively relative to the insulative caps and the insulative sidewalls. | 12-15-2011 |
20110318921 | Methods Of Forming An Interconnect Between A Substrate Bit Line Contact And A Bit Line In DRAM - The invention includes methods of electrically interconnecting different elevation conductive structures, methods of forming capacitors, methods of forming an interconnect between a substrate bit line contact and a bit line in DRAM, and methods of forming DRAM memory cells. In one implementation, a method of electrically interconnecting different elevation conductive structures includes forming a first conductive structure comprising a first electrically conductive surface at a first elevation of a substrate. A nanowhisker is grown from the first electrically conductive surface, and is provided to be electrically conductive. Electrically insulative material is provided about the nanowhisker. An electrically conductive material is deposited over the electrically insulative material in electrical contact with the nanowhisker at a second elevation which is elevationally outward of the first elevation, and the electrically conductive material is provided into a second conductive structure. Other aspects and implementations are contemplated. | 12-29-2011 |
20120003832 | METHOD OF REDUCING EROSION OF A METAL CAP LAYER DURING VIA PATTERNING IN SEMICONDUCTOR DEVICES - During the patterning of via openings in sophisticated metallization systems of semiconductor devices, the opening may extend through a conductive cap layer and an appropriate ion bombardment may be established to redistribute material of the underlying metal region to exposed sidewall portions of the conductive cap layer, thereby establishing a protective material. Consequently, in a subsequent wet chemical etch process, the probability for undue material removal of the conductive cap layer may be greatly reduced. | 01-05-2012 |
20120009783 | Solder Bump With Inner Core Pillar in Semiconductor Package - A flip chip semiconductor package has a substrate with a plurality of active devices. A contact pad is formed on the substrate in electrical contact with the plurality of active devices. A passivation layer, second barrier layer, and adhesion layer are formed between the substrate and an intermediate conductive layer. The intermediate conductive layer is in electrical contact with the contact pad. A copper inner core pillar is formed by plating over the intermediate conductive layer. The inner core pillar has a rectangular, cylindrical, toroidal, or hollow cylinder form factor. A solder bump is formed around the inner core pillar by plating solder material and reflowing the solder material to form the solder bump. A first barrier layer and wetting layer are formed between the inner core pillar and solder bump. The solder bump is in electrical contact with the intermediate conductive layer. | 01-12-2012 |
20120058638 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - According to one embodiment, a semiconductor device manufacturing method comprises defining a region in which absorptance of light illuminated for annealing to a substrate on which a pattern of a semiconductor integrated circuit is formed is not larger than a preset value as a coarse pattern region, locally forming a thin film that enhances light absorptance on the coarse pattern region, and annealing the substrate by illuminating light onto the substrate on which the pattern of the integrated circuit and thin film are formed. | 03-08-2012 |
20120058639 | SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME - A method of forming a nonvolatile memory device includes providing conductive pillars disposed in a first insulating layer and disposed on a semiconductor substrate, providing an etch stop layer on the first insulating layer, disposing a mold layer on the etch stop layer, and forming grooves in the mold layer. The grooves respectively extend over the conductive pillars in a first direction. The method further includes patterning the etch stop layer using the grooves to form holes respectively corresponding to the conductive pillars, and filling a metal into the grooves and the holes. The metal in the holes contacts the conductive pillars. | 03-08-2012 |
20120094484 | NANO-TUBE THERMAL INTERFACE STRUCTURE - A structure, comprising: a semiconductor structure having an electrically and thermally conductive layer disposed on one surface of the semiconductor structure; an electrically and thermally conductive heat sink; a electrically and thermally conductive carrier layer; a plurality of electrically and thermally nano-tubes, a first portion of the plurality of nano-tubes having proximal ends disposed on a first surface of the carrier layer and a second portion of the plurality of nano-tubes having proximal ends disposed on an opposite surface of the carrier layer; and a plurality of electrically and thermally conductive heat conductive tips disposed on distal ends of the plurality of nano-tubes, the plurality of heat conductive tips on the first portion of the plurality of nano-tubes being attached to the conductive layer, the plurality of heat conductive tips on the second portion of the plurality of nano-tubes being attached to the heat sink. | 04-19-2012 |
20120196438 | CHIP PACKAGE STRUCTURE - The formation of the conductive wire of a chip package consists of a plurality of steps. Coat a first dielectric layer on the pad-mounting surface and a slot is formed on each bonding pad correspondingly. Then coat a second dielectric layer and produce a wiring slot corresponding to each bonding pad and the slot thereof. Next each wiring slot is filled with electrically conductive metal so as to form a conductive wire. Later Coat a third dielectric layer and a corresponding slot is formed on one end of each conductive wire while this slot is filled with electrically conductive metal to form a solder point. The above steps can further be repeated so as to form an upper-layer and a lower-layer conductive wire. Thereby precision of the chip package, use efficiency of the wafer and yield rate of manufacturing processes are all improved. | 08-02-2012 |
20120202346 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - Certain embodiments provide a method for manufacturing a semiconductor device including forming first and second insulating films on first and second regions formed on a semiconductor substrate, respectively, selectively irradiating UV light to a second contact region where the second contact is to be formed in the second insulating film, forming first and second opening on the first and second insulating films by concurrently etching a first contact region in the first insulating film where the first contact is to be formed and the second contact region after having irradiated the UV light, respectively, forming first and second contacts in the first and second openings. The second insulating film differs from the first insulating film in the membrane stress, and is an insulating film with an etching rate that approaches an etching rate of the first insulating film by the UV light being irradiated. | 08-09-2012 |
20120202347 | THROUGH SILICON VIAS USING CARBON NANOTUBES - The various embodiments of the present invention provide carbon nanotube (CNT)-based TSVs and methods of making the same. The CNT-based TSVs embodiments comprise a silicon wafer having a plurality of through-vias defined therein, and a support layer comprising a CNT catalyst layer disposed beneath the silicon wafer to facilitate CNT growth through the plurality of through-vias. Once CNT arrays have grown inside and through the through-vias, the support layer and accompanying CNT catalyst layer can be removed from the silicon wafer, which will result in the CNTs remaining in the TSVs. | 08-09-2012 |
20120208364 | METHOD FOR OPENING ONE-SIDE CONTACT REGION OF VERTICAL TRANSISTOR AND METHOD FOR FABRICATING ONE-SIDE JUNCTION REGION USING THE SAME - A method for opening a one-side contact region of a vertical transistor is provided. The one-side contact region of the vertical transistor is opened using a polysilicon layer, a certain portion of which can be selectively removed by a selective ion implantation process. In order to selectively remove the polysilicon layer formed on one of both sides of an active region, at which the one-side contact is to be formed, impurity ion implantation is performed in a direction vertical to the polysilicon layer by a plasma doping process, and a tilt ion implantation using an existing ion implantation process is performed. In this manner, the polysilicon layer is selectively doped, and the undoped portion of the polysilicon layer is selectively removed. | 08-16-2012 |
20120258592 | Layouts of POLY Cut Openings Overlapping Active Regions - A method of forming integrated circuits includes forming a mask layer over a gate electrode line, wherein the gate electrode line is over a well region of a semiconductor substrate; forming an opening in the mask layer, wherein a portion of the gate electrode line and a well pickup region of the well region are exposed through the opening; and removing the portion of the gate electrode line through the opening. | 10-11-2012 |
20120258593 | SRAM CELL WITH T-SHAPED CONTACT - An integrated circuit containing an array of SRAM cells with T-shaped contacts in the inverters, in which drain connecting segments may extend beyond gate connecting segments by a distance greater than 10 percent of a separation distance between ends of opposite drain connecting segments. The drain connecting segments may also extend beyond gate connecting segments by a distance greater than one-third of the width of the gate connecting segments. A process of forming an integrated circuit containing an array of SRAM cells with T-shaped contacts in which drain connecting segments may extend beyond gate connecting segments by a distance greater than 10 percent of a separation distance between ends of opposite drain connecting segments. A process may also form the drain connecting segments to extend beyond gate connecting segments by greater than one-third of the width of the gate connecting segments. | 10-11-2012 |
20120264293 | SRAM CELL WITH T-SHAPED CONTACT - An integrated circuit containing an array of SRAM cells with T-shaped contacts in the inverters, in which drain connecting segments may extend beyond gate connecting segments by a distance greater than | 10-18-2012 |
20120264294 | SRAM CELL WITH T-SHAPED CONTACT - An integrated circuit containing an array of SRAM cells with T-shaped contacts in the inverters, in which drain connecting segments may extend beyond gate connecting segments by a distance greater than 10 percent of a separation distance between ends of opposite drain connecting segments. The drain connecting segments may also extend beyond gate connecting segments by a distance greater than one-third of the width of the gate connecting segments. A process of forming an integrated circuit containing an array of SRAM cells with T-shaped contacts in which drain connecting segments may extend beyond gate connecting segments by a distance greater than 10 percent of a separation distance between ends of opposite drain connecting segments. A process may also form the drain connecting segments to extend beyond gate connecting segments by greater than one-third of the width of the gate connecting segments. | 10-18-2012 |
20120264295 | STRUCTURE AND METHOD OF REDUCING ELECTROMIGRATION CRACKING AND EXTRUSION EFFECTS IN SEMICONDUCTOR DEVICES - A structure for reducing electromigration cracking and extrusion effects in semiconductor devices includes a first metal line formed in a first dielectric layer; a cap layer formed over the first metal line and first dielectric layer; a second dielectric layer formed over the cap layer; and a void formed in the second dielectric layer, stopping on the cap layer, wherein the void is located in a manner so as to isolate structural damage due to electromigration effects of the first metal line, the effects including one or more of extrusions of metal material from the first metal line and cracks from delamination of the cap layer with respect to the first dielectric layer. | 10-18-2012 |
20120282771 | ELECTRODE ARRAYS AND METHODS OF FABRICATING THE SAME USING PRINTING PLATES TO ARRANGE PARTICLES IN AN ARRAY - Electrode arrays and methods of fabricating the same using a printing plate to arrange conductive particles in alignment with an array of electrodes are provided. In one embodiment, a semiconductor device comprises: a semiconductor topography comprising an array of electrodes disposed upon a semiconductor substrate; a dielectric layer residing upon the semiconductor topography; and at least one conductive particle disposed in or on the dielectric layer in alignment with at least one of the array of electrodes. | 11-08-2012 |
20120322259 | DEFECT FREE DEEP TRENCH METHOD FOR SEMICONDUCTOR CHIP - A method for forming large substantially defect-free void areas on a semiconductor integrated circuit chip includes processing the chip through the passivation level processing operations then forming one or more openings in a designated blank area of the integrated circuit chip in a separate dedicated etching operation. The one or more openings may constitute 5-10% or more of the total area of the semiconductor chip. The void areas are deep trench openings that extend through the passivation layer and through all of the other material layers in the blank area exposing the substrate surface in one embodiment and through all material layers except for a field oxide layer formed directly on the substrate in another embodiment. | 12-20-2012 |
20120329275 | BORDERLESS INTERCONNECT LINE STRUCTURE SELF-ALIGNED TO UPPER AND LOWER LEVEL CONTACT VIAS - A metal layer is deposited on a planar surface on which top surfaces of underlying metal vias are exposed. The metal layer is patterned to form at least one metal block, which has a horizontal cross-sectional area of a metal line to be formed and at least one overlying metal via to be formed. Each upper portion of underlying metal vias is recessed outside of the area of a metal block located directly above. The upper portion of the at least one metal block is lithographically patterned to form an integrated line and via structure including a metal line having a substantially constant width and at least one overlying metal via having the same substantially constant width and borderlessly aligned to the metal line. An overlying-level dielectric material layer is deposited and planarized so that top surface(s) of the at least one overlying metal via is/are exposed. | 12-27-2012 |
20130005143 | METHOD AND APPARATUS PROVIDING AIR-GAP INSULATION BETWEEN ADJACENT CONDUCTORS USING NANOPARTICLES - A semiconductor device and a method of forming it are disclosed in which at least two adjacent conductors have an air-gap insulator between them which is covered by nanoparticles of insulating material being a size which prevent the nanoparticles from substantially entering into the air-gap. | 01-03-2013 |
20130029487 | MANUFACTURING METHOD OF DEVICE - A device manufacturing method includes: sequentially forming a first sacrificial film, a first support film, a second sacrificial film, and a second support film on a semiconductor substrate; forming a hole to pass through these films; forming a crown-shaped electrode covering an inner surface of the hole and connected to the second support film and the first support film; forming a first opening in the second support film into a first pattern designed such that the connection between the crown-shaped electrode and the second support film is at least partially maintained; removing at least a part of the second sacrificial film through the first opening; forming a second opening in the first support film with use of the first opening; and removing the first sacrificial film through the second opening. This method is able to prevent misalignment of openings between the support films. | 01-31-2013 |
20130072016 | METHODS OF FORMING CONDUCTIVE CONTACTS WITH REDUCED DIMENSIONS - Disclosed herein are various methods of forming conductive contacts with reduced dimensions and various semiconductor devices incorporating such conductive contacts. In one example, one method disclosed herein includes forming a layer of insulating material above a semiconducting substrate, wherein the layer of material has a first thickness, forming a plurality of contact openings in the layer of material having the first thickness and forming an organic material in at least a portion of each of the contact openings. This illustrative method further includes the steps of, after forming the organic material, performing an etching process to reduce the first thickness of the layer of insulating material to a second thickness that is less than the first thickness, after performing the etching process, removing the organic material from the contact openings and forming a conductive contact in each of the contact openings. | 03-21-2013 |
20130078803 | SEMICONDUCTOR DEVICE INCLUDING A CIRCUIT AREA AND A MONITOR AREA HAVING A PLURALITY OF MONITOR LAYERS AND METHOD FOR MANUFACTURING THE SAME - In a circuit area wherein a semiconductor integrated circuit is to be formed, an isolation insulating film is formed on a surface of a semiconductor substrate, and, at the same time, five isolation insulating films extending in one specific direction are formed within a monitor area at a fixed spacing. Then, a gate insulation film and a gate electrode are formed within the circuit area on the semiconductor substrate, and, at the same time, five gate insulation films and five gate electrodes extending in the same direction as the isolation insulating films are formed within the monitor area at the same spacing as that of the isolation insulating films. | 03-28-2013 |
20130095654 | METHODS OF MANUFACTURING A VERTICAL TYPE SEMICONDUCTOR DEVICE - According to example embodiments of inventive concepts, a method includes forming cell patterns and insulating interlayers between the cell patterns on the substrate. An upper insulating interlayer including initial and preliminary contact holes is formed on an uppermost cell pattern. A first reflection limiting layer pattern and a first photoresist layer pattern are formed for exposing a first preliminary contact hole while covering inlet portion of the initial and preliminary contact holes. A first etching process is performed on layers under the first preliminary contact hole to expose the cell pattern at a lower position than a bottom of the first preliminary contact hole. A partial removing process of sidewall portions of the first reflection limiting layer pattern and the first photoresist layer pattern and an etching process on exposed layers through bottom portions of the preliminary contact holes are repeated for forming contact holes having different depths. | 04-18-2013 |
20130137261 | METHOD OF MODIFYING A LOW K DIELECTRIC LAYER HAVING ETCHED FEATURES AND THE RESULTING PRODUCT - A dielectric layer having features etched thereon and a low dielectric constant, and that is carried by a semiconductor substrate. The etched dielectric layer is modified so its surface energy is reduced by at least one of: (a) applying thermal energy to the layer to cause the layer temperature to be between 100 C and 400 C; (b) irradiating the layer with electromagnetic energy; and/or (c) irradiating the layer with free ions. | 05-30-2013 |
20130164934 | MANUFACTURING METHOD OF A SEMICONDUCTOR DEVICE AND METHOD FOR CREATING A LAYOUT THEREOF - A method for manufacturing a semiconductor device of one embodiment of the present invention includes: forming an insulation layer to be processed over a substrate; forming a first sacrificial layer in a first area over the substrate, the first sacrificial layer being patterned to form in the first area a functioning wiring connected to an element; forming a second sacrificial layer in a second area over the substrate, the second sacrificial layer being patterned to form in the second area a dummy wiring; forming a third sacrificial layer at a side wall of the first sacrificial layer and forming a fourth sacrificial layer at a side wall of the second sacrificial layer, the third sacrificial layer and the fourth sacrificial layer being separated; forming a concavity by etching the insulation layer to be processed using the third sacrificial layer and the fourth sacrificial layer as a mask; and filling a conductive material in the concavity. | 06-27-2013 |
20130178061 | METHOD OF MANUFACTURING POROUS FILM AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - First, a porous insulating film | 07-11-2013 |
20130210226 | PATTERN FORMATION METHOD - According to one embodiment, a pattern formation method comprises forming a hard mask material on a processed film on a wiring, forming a guide layer on the hard mask material, forming a tetragonal opening in the guide layer, coating the opening with a block polymer, heating the block polymer to form a micro phase separation structure film in which first polymer parts and second polymer parts parallel to the wiring are alternately arranged, removing the second polymer part while leaving the first polymer part, processing the hard mask material with the guide layer and the first polymer part as a mask to form a first hole pattern in the hard mask material, and processing the processed film with the hard mask material as a mask to form a second hole pattern corresponding to the first hole pattern in the processed film. | 08-15-2013 |
20130252420 | METHOD FOR FORMING FINE PITCH STRUCTURES - A mold having an open interior volume is used to define patterns. The mold has a ceiling, floor and sidewalls that define the interior volume and inhibit deposition. One end of the mold is open and an opposite end has a sidewall that acts as a seed sidewall. A first material is deposited on the seed sidewall. A second material is deposited on the deposited first material. The deposition of the first and second materials is alternated, thereby forming alternating rows of the first and second materials in the interior volume. The mold and seed layer are subsequently selectively removed. In addition, one of the first or second materials is selectively removed, thereby forming a pattern including free-standing rows of the remaining material. The free-standing rows can be utilized as structures in a final product, e.g., an integrated circuit, or can be used as hard mask structures to pattern an underlying substrate. The mold and rows of material can be formed on multiple levels. The rows on different levels can crisscross one another. Selectively removing material from some of the rows can from openings to form, e.g., contact vias. | 09-26-2013 |
20130267092 | Methods of Forming a Fine Pattern on a Substrate and Methods of Forming a Semiconductor Device Having a Fine Pattern - The inventive concept provides methods of manufacturing semiconductor devices having a fine pattern. In some embodiments, the methods comprise forming an etch-target film on a substrate, forming a first mask pattern on the etch-target film, forming a second mask pattern by performing an ion implantation process in the first mask pattern, and etching the etch-target film using the second mask pattern. | 10-10-2013 |
20130302980 | TUNGSTEN FEATURE FILL - Described herein are methods of filling features with tungsten and related systems and apparatus. The methods include inside-out fill techniques as well as conformal deposition in features. Inside-out fill techniques can include selective deposition on etched tungsten layers in features. Conformal and non-conformal etch techniques can be used according to various implementations. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) word lines. Examples of applications include logic and memory contact fill, DRAM buried word line fill, vertically integrated memory gate/word line fill, and 3-D integration with through-silicon vias (TSVs). | 11-14-2013 |
20130323925 | PATTERN FORMING METHOD, MOLD AND DATA PROCESSING METHOD - According to one embodiment, a pattern forming method is disclosed. The method can include forming an insulating layer on a major surface of a substrate. The method can include forming first and second openings on the insulating layer. The first opening has a first length in a first direction along the major surface, and the second opening has a second length longer than the first length in the first direction. The method can include forming a first pattern in the first opening. The method can include forming a second pattern in the second opening. The method can include forming a self-assembled material film contacting the insulating layer, the first pattern and the second pattern. The method can include forming a third pattern with guidance of the second pattern. In addition, the method can include forming a fourth pattern contacting the first pattern based on the third pattern. | 12-05-2013 |
20130330923 | MIDDLE OF LINE STRUCTURES AND METHODS FOR FABRICATION - A contact structure includes a permanent antireflection coating formed on a substrate having contact pads. A patterned dielectric layer is formed on the antireflective coating. The patterned dielectric layer and the permanent antireflective coating form openings. The openings correspond with locations of the contact pads. Contact structures are formed in the openings to make electrical contact with the contacts pads such that the patterned dielectric layer and the permanent antireflective coating each have a conductively filled region forming the contact structures. | 12-12-2013 |
20130337646 | METHOD FOR FORMING STAIRCASE WORD LINES IN A 3D NON-VOLATILE MEMORY HAVING VERTICAL BIT LINES - A 3D nonvolatile memory has memory elements arranged in a three-dimensional pattern defined by rectangular coordinates having x, y and z-directions and with a plurality of parallel planes stacked in the z-direction over a semiconductor substrate. It has vertical local bit lines and a plurality of staircase word lines. Each staircase word line has a series of alternating segments and risers elongated respectively in the x-direction and z-direction traversing across the plurality of planes in the z-direction with a segment in each plane. Methods of forming a slab of multi-plane memory with staircase word lines include processes with one masking and with two maskings for forming each plane. | 12-19-2013 |
20140051246 | METHODS OF FABRICATING A SEMICONDUCTOR DEVICE - Methods of fabricating a semiconductor device are provided. The methods may include preparing a semiconductor substrate, forming insulating patterns including a trench on the semiconductor substrate, conformally forming a metal layer covering an inner surface of the trench on the insulating patterns, conformally forming a protecting layer on the metal layer, and performing a chemical mechanical polishing (CMP) process on the protecting layer and the metal layer until top surfaces of the insulating patterns are exposed, thereby forming a metal pattern and a protecting pattern in the trench. The CMP process may use a slurry including polishing particles having negative charges. | 02-20-2014 |
20140065820 | PATTERN STRUCTURES IN SEMICONDUCTOR DEVICES AND METHODS OF FORMING PATTERN STRUCTURES IN SEMICONDUCTOR DEVICES - A pattern structure in a semiconductor device includes an extending line and a pad connected with an end portion of the extending line. The pad may have a width that is larger than a width of the extending line. The pad includes a protruding portion extending from a lateral portion of the pad. The pattern structure may be formed by simplified processes and may be employed in various semiconductor devices requiring minute patterns and pads. | 03-06-2014 |
20140120718 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device includes: forming a metal layer containing Al; forming an insulating film on the metal layer; forming an opening pattern to the insulating film, the metal layer being exposed in the opening pattern; and forming a wiring layer in the opening pattern, a first portion being disposed between an edge of the wiring layer and an edge of the opening pattern, a width of the first portion being 1 μm or less, and the metal layer being exposed in the first portion. | 05-01-2014 |
20140134840 | METHOD FOR MANUFACTURING STRETCHABLE THIN FILM TRANSISTOR - Provided is a method for manufacturing a stretchable thin film transistor. The method for manufacturing a stretchable thin film transistor includes forming a mold substrate, forming a stretchable insulator on the mold substrate, forming a flat substrate on the stretchable insulator, removing the mold substrate, forming discontinuous and corrugated wires on the stretchable insulator, forming a thin film transistor connected between the wires, and removing the flat substrate. | 05-15-2014 |
20140141608 | SEMICONDUCTOR COMPONENT AND METHODS FOR PRODUCING A SEMICONDUCTOR COMPONENT - A method for producing a semiconductor component with a semiconductor body includes providing a substrate of a first conductivity type. A buried semiconductor layer of a second conductivity type is provided on the substrate. A functional unit semiconductor layer is provided on the buried semiconductor layer. At least one trench, which reaches into the substrate, is formed in the semiconductor body. An insulating layer is formed, which covers inner walls of the trench and electrically insulates the trench interior from the functional unit semiconductor layer and the buried semiconductor layer, the insulating layer having at least one opening in the region of the trench bottom. The at least one trench is filled with an electrically conductive semiconductor material of the first conductivity type, wherein the electrically conductive semiconductor material forms an electrical contact from a surface of the semiconductor body to the substrate. | 05-22-2014 |
20140179101 | SEMICONDUCTOR DEVICE WITH AIR GAP AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device includes forming a semiconductor structure having an open portion over a substrate, forming a sacrificial spacer on sidewalls of the open portion, forming a recessed first plug in the open portion, forming an air gap by removing the sacrificial spacer, forming a capping layer to expose the top surface of the recessed first plug and to cap the air gap, forming a protective layer over the capping layer and the recessed first plug, forming an ohmic contact layer over the protective layer, and forming a second plug over the ohmic contact layer. | 06-26-2014 |
20140179102 | SEMICONDUCTOR DEVICE WITH AIR GAPS AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device includes forming a plurality of bit line structures over a substrate, forming contact holes between the bit line structures, forming sacrificial spacers on sidewalls of the contact holes, forming first plugs recessed inside the contact holes, forming air gaps by removing the sacrificial spacers, forming conductive capping layers capping the first plugs and the air gaps, and forming second plugs over the conductive capping layers. | 06-26-2014 |
20140242793 | PATTERN FORMING METHOD AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, a core material is ejected onto an object using an inkjet method to form a core pattern on the object, a mask pattern is formed on the object so as to embed the core pattern, and the core pattern which is embedded in the mask pattern is removed. | 08-28-2014 |
20140273439 | SEMICONDUCTOR DEVICE CHANNELS - A semiconductor device and a method of manufacture are provided. The semiconductor device includes one or more layers having channels adapted to carry signals or deliver power. The semiconductor device may include at least two channels having a substantially equivalent cross-sectional area. Conductors in separate channels may have different cross-sectional areas. A spacer dielectric on a side of a channel may be included. The method of manufacture includes establishing a signal conductor layer including a first channel and a second channel having a substantially equivalent cross-sectional area, introducing a spacer dielectric on a side of the second channel, introducing a first conductor in the first channel having a first cross-sectional area, and introducing a second conductor in the second channel having a second cross-sectional area where the second cross-sectional area is smaller than the first cross-sectional area. | 09-18-2014 |
20140273440 | SEMICONDUCTOR DEVICE CHANNELS - A semiconductor device and a method of manufacture are provided. The semiconductor device includes one or more layers having channels adapted to carry signals or deliver power. The semiconductor device may include a signal channel and a power channel. The power channel may include power channel cross-sectional portions. A first conductor in the power channel may have a first cross-sectional area. A second conductor in the signal channel may have a second cross-sectional area. The second cross-sectional area may be smaller than the first cross-sectional area. The method of manufacture includes establishing a signal conductor layer including a signal channel and a power channel, introducing a first conductor in the power channel having a first cross-sectional area, and introducing a second conductor in the signal channel having a second cross-sectional area where the second cross-sectional area is smaller than the first cross-sectional area. | 09-18-2014 |
20140273441 | METHOD FOR FORMING PATTERNS OF SEMICONDUCTOR DEVICE USING SADP PROCESS - To fabricate patterns of a semiconductor device, a mask film is formed on a substrate. A plurality of first patterns and a plurality of second patterns are formed on the mask film. The plurality of first patterns is spaced apart from each other at a first distance. The plurality of second patterns is spaced apart from each other at a second distance. The second distance is different from the first distance. A spacer film is conformally formed on the plurality of first patterns and the plurality of second patterns to a predetermined thickness. The spacer film fills spaces between the plurality of second patterns. A part of the spacer film is partially removed to form a plurality of spacer film patterns are formed on side walls of the plurality of the first patterns. The plurality of first patterns and the plurality of second patterns are removed. A plurality of patterns is formed on the substrate using the plurality of spacer film as a mask. | 09-18-2014 |
20140273442 | Spacer Etching Process For Integrated Circuit Design - A method of forming a target pattern includes forming a first material layer on a substrate; performing a first patterning process using a first layout to form a first plurality of trenches in the first material layer; performing a second patterning process using a second layout to form a second plurality of trenches in the first material layer; forming spacer features on sidewalls of both the first plurality of trenches and the second plurality of trenches, the spacer features having a thickness; removing the first material layer; etching the substrate using the spacer features as an etch mask; and thereafter removing the spacer features. The target pattern is to be formed with the first layout and the second layout. | 09-18-2014 |
20140302672 | Method of Forming Metal Contacts in the Barrier Layer of a Group III-N HEMT - Metal contact openings are etched in the barrier layer of a group III-N HEMT with a first gas combination that etches down into the barrier layer, and a second gas combination that etches further down into the barrier layer to a depth that lies above the top surface of a channel layer that touches and lies below the barrier layer. | 10-09-2014 |
20140302673 | Method of Forming Metal Contacts With Low Contact Resistances in a Group III-N HEMT - Metal contacts with low contact resistances are formed in a group III-N HEMT by forming metal contact openings in the barrier layer of the group III-N HEMT to have depths that correspond to low contact resistances. The metal contact openings are etched in the barrier layer with a first gas combination that etches down into the barrier layer, and a second gas combination that etches further down into the barrier layer. | 10-09-2014 |
20140315383 | METHODS OF MAKING INTEGRATED CIRCUITS - A method of making an integrated circuit including forming a seal ring structure around a circuit where the seal ring structure has a first portion and a tilted portion. The first portion of the seal ring structure is substantially parallel with an edge of the circuit. The tilted portion of the seal ring structure forms an obtuse angle with the first portion. The method further includes forming a first pad which is electrically coupled with the seal ring structure. The method further includes disposing a leakage current test structure in an area enclosed by the seal ring where at least one portion of the leakage current test structure is substantially parallel with the tilted portion of the seal ring structure. The method further includes forming a second pad which is electrically coupled with the leakage current test structure. | 10-23-2014 |
20140342553 | Method for Forming Semiconductor Structure Having Opening - According to one embodiment of the present invention, a method for forming a semiconductor structure having an opening is provided. First, a substrate is provided, wherein a first region and a second region are defined on the substrate and an overlapping area of the first region and the second region is defined as a third region. Then, a material layer is formed on the substrate. A first hard mask and a second hard mask are formed on the material layer. The first hard mask in the first region is removed to form a patterned first hard mask. The second hard mask in the third region is removed to form a patterned second hard mask. Lastly, the material layer is patterned by using the patterned second hard mask layer as a mask to form at least an opening in the third region only. | 11-20-2014 |
20140342554 | METHOD FOR MANUFACTURING THIN FILM TRANSISTOR ARRAY - A thin film transistor (TFT) array includes a substrate, a thin film transistor, a first wall, a transparent electrode and a color resist. The thin film transistor is disposed on the substrate. The first wall is disposed on the substrate and separates a first contact hole from a pixel region on the substrate, wherein the first contact hole exposes a drain electrode of the thin film transistor. The first wall has a first sidewall facing towards the first contact hole and a second sidewall facing towards the pixel region, wherein the slope of the first sidewall is gentler than the slope of the second sidewall. The transparent electrode is electrically connected to the drain electrode of the thin film transistor through the first contact hole. The pixel region is filled with the color resist. | 11-20-2014 |
20140370704 | METHODS OF FORMING SEMICONDUCTOR DEVICES INCLUDING LOW-K DIELECTRIC LAYER - Methods of forming a dielectric layer are provided. The methods may include introducing oxygen radicals and organic silicon precursors into a chamber to form a preliminary dielectric layer on a substrate. Each of the organic silicon precursors may include a carbon bridge and a porogen such that the preliminary dielectric layer may include carbon bridges and porogens. The methods may also include removing at least some of the porogens from the preliminary dielectric layer to form a porous dielectric layer including the carbon bridges. | 12-18-2014 |
20140377950 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device, including forming a molding layer; forming a damascene mask layer and mask layer on the molding layer; forming a mask layer pattern by etching the mask layer; forming a damascene pattern by partially etching the damascene mask layer; forming a damascene mask layer on the mask layer pattern to bury the damascene pattern; forming a damascene pattern partially overlapping the damascene pattern by etching the damascene mask layer and the mask layer pattern; connecting the damascene pattern and the damascene pattern by removing a portion of the mask layer pattern exposed by the damascene pattern; forming a damascene mask layer on the damascene mask layer to bury the damascene pattern; and forming a trench under the damascene patterns by etching the damascene mask layers and the molding layer using remaining portions of the mask layer pattern. | 12-25-2014 |
20150011085 | METHOD FOR FORMING FINE PITCH STRUCTURES - A mold having an open interior volume is used to define patterns. The mold has a ceiling, floor and sidewalls that define the interior volume and inhibit deposition. One end of the mold is open and an opposite end has a sidewall that acts as a seed sidewall. A first material is deposited on the seed sidewall. A second material is deposited on the deposited first material. The deposition of the first and second materials is alternated, thereby forming alternating rows of the first and second materials in the interior volume. The mold and seed layer are subsequently selectively removed. In addition, one of the first or second materials is selectively removed, thereby forming a pattern including free-standing rows of the remaining material. The free-standing rows can be utilized as structures in a final product, e.g., an integrated circuit, or can be used as hard mask structures to pattern an underlying substrate. The mold and rows of material can be formed on multiple levels. The rows on different levels can crisscross one another. Selectively removing material from some of the rows can from openings to form, e.g., contact vias. | 01-08-2015 |
20150024589 | METHOD FOR ASSEMBLING A MICROELECTRONIC CHIP ELEMENT ON A WIRE ELEMENT, AND INSTALLATION ENABLING ASSEMBLY TO BE PERFORMED - Method for assembling includes: providing a system to transfer wire element from wire element supply device to wire element storage device; stretching wire element between supply and storage devices by tensioning; providing an individualized reservoir and separated chip elements, each including a connection terminal including a top with free access facing in which chip element is not present; transporting the chip element from reservoir to an assembly area between supply and storage devices in which wire element is tightly stretched in assembly area; fixing electrically conducting wire element to chip element connection terminal in assembly area; and adding electrically insulating material on chip element after latter has been fixed to wire element forming a cover, the addition of material being performed on surface of chip element including connection terminal fixed to wire element to cover at least the connection terminal and portion of wire element at fixing point of latter. | 01-22-2015 |
20150037976 | METHOD OF MAKING A STRUCTURE - A method of making a structure includes forming a first supporting member over a substrate, the first supporting member comprising a first material and having a first width defined along a reference plane. The method further includes forming a second supporting member over the substrate, the second supporting member having a second width defined along the reference plane, and the first supporting member and the second supporting member being separated by a gap region. The first width is at least 10 times the second width, and a gap width of the gap region being from 5 to 30 times the second width. | 02-05-2015 |
20150044868 | SEMICONDUCTOR DEVICES INCLUDING SPACERS ON SIDEWALLS OF CONDUCTIVE LINES AND METHODS OF MANUFACTURING THE SAME - Semiconductor devices are provided that include spacers on sidewalls of conductive lines, as well as methods for manufacturing the same. A method for manufacturing a semiconductor device includes forming bit lines on a semiconductor substrate. Triple-layered bit line spacers are formed on respective sidewalls of the bit lines. An interlayer insulation layer is formed on the bit lines and the triple-layered bit line spacers. Storage node contact plugs that penetrate the interlayer insulation layer are formed between the bit lines. Portions of the triple-layered bit line spacers are etched to form recessed regions. An insulation layer is formed on the substrate including the recessed regions. Storage node electrodes electrically connected to the storage node contact plugs are formed. | 02-12-2015 |
20150056802 | INTERCONNECT STRUCTURE AND METHOD FOR FORMING THE SAME - Embodiments of an interconnect structure and methods for forming an interconnect structure are provided. The method includes forming a low-k dielectric layer over a substrate, forming an opening in the low-k dielectric layer, forming a conductor in the opening, forming a capping layer over the conductor, and forming an etch stop layer over the capping layer and the low-k dielectric layer. The etch stop layer includes an N element with a content ratio not less than about 25 at %. | 02-26-2015 |
20150056803 | TUNGSTEN FEATURE FILL - Described herein are methods of filling features with tungsten and related systems and apparatus. The methods include inside-out fill techniques as well as conformal deposition in features. Inside-out fill techniques can include selective deposition on etched tungsten layers in features. Conformal and non-conformal etch techniques can be used according to various implementations. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) word lines. Examples of applications include logic and memory contact fill, DRAM buried word line fill, vertically integrated memory gate/word line fill, and 3-D integration with through-silicon vias (TSVs). | 02-26-2015 |
20150064902 | Methods of Fabricating Semiconductor Devices - A method of fabricating a semiconductor device includes forming a stacked structure in which 2 | 03-05-2015 |
20150072520 | VIA NETWORK STRUCTURES AND METHOD THEREFOR - A circuit device is configured with robust circuit connectors. In connection with various example embodiments, an integrated circuit device includes one or more via network layers below a bond pad contact, connecting the bond pad contact with one or more underlying metal layers. Each via network layer includes a plurality of via strips extending about parallel to the bond pad contact and in different directions to structurally support the bond pad contact. | 03-12-2015 |
20150072521 | MICROSTRUCTURE MANUFACTURING METHOD - A microstructure manufacturing method includes forming a first insulating film on an Si substrate, exposing an Si surface by removing a part of the first insulating film, forming a recessed portion by etching the Si substrate from the exposed Si surface, forming a second insulating film on a sidewall and a bottom of the recessed portion, forming an Si exposed surface by removing at least a part of the second insulating film formed on the bottom of the recessed portion, and filling the recessed portion with a metal from the Si exposed surface by electrolytic plating. | 03-12-2015 |
20150093895 | SEMICONDUCTOR DEVICES AND FABRICATING METHODS THEREOF - Fabricating methods of a semiconductor device are provided. The fabricating methods may include forming a mold layer, forming a catalyst pattern including noble metal on the mold layer and etching the mold layer using the catalyst pattern as a catalyst. Etching the mold layer may include performing a wet etching process. | 04-02-2015 |
20150104938 | METHOD FOR FORMING DAMASCENE OPENING AND APPLICATIONS THEREOF - A method for forming a damascene opening, wherein the method comprises steps as follows: Firstly, a semiconductor structure comprising an inter-metal dielectric (IMD), a first hard mask layer and a second hard mask layer stacked in sequence is provided, wherein the semiconductor structure has at least one trench extending downwards from the second hard mask layer to the IMD. A plasma treatment is then performed to modify a portion of the first hard mask layer exposed from the trench. Subsequently, a wet treatment is performed to remove the second hard mask layer and a portion of the first hard mask layer, wherein the plasma-modified portion of the first patterned hard mask layer has a first removing rate substantially less than a second removing rate of the second hard mask layer in the wet treatment. | 04-16-2015 |
20150132948 | Method Of Fabricating A Semiconductor Device, And Chemical Mechanical Polish Tool - The present disclosure provides a method of fabricating a semiconductor device with metal interconnections and a design of a tool for performing such a method. In one embodiment, a method of fabricating a semiconductor device, the method includes providing a semiconductor substrate, depositing a dielectric layer over the semiconductor substrate, forming at least one trench in the dielectric layer, and forming a metallization layer in the trench and over the dielectric layer. The method further includes performing a chemical mechanical polishing process to planarize the metallization layer and the dielectric layer, performing a surface treatment on the planarized dielectric layer to form a protection layer, cleaning the planarized metallization layer and the treated dielectric layer to remove residue from the chemical mechanical polishing process, and drying the cleaned metallization layer and dielectric layer in an inert gas environment. | 05-14-2015 |
20150140810 | METHOD OF FORMING WIRINGS - A method of manufacturing a wiring includes sequentially forming a first insulation layer, a first layer, and a second layer on a substrate, etching an upper portion of the second layer a plurality of times to form a second layer pattern including a first recess having a shape of a staircase, etching a portion of the second layer pattern and a portion of the first layer under the first recess to form a first layer pattern including a second recess having a shape of a staircase similar to the first recess, etching a portion of the first layer pattern under the second recess to form a first opening exposing a portion of a top surface of the first insulation layer, etching the exposed portion of the first insulation layer to form a second opening through the first insulation layer, and forming a wiring filling the second opening. | 05-21-2015 |
20150147881 | PASSIVATION ASH/OXIDATION OF BARE COPPER - A semiconductor wafer has a clean, high quality Cu oxide formed at the surface of exposed Cu when an extended non-fabrication process time (such as shipping to an assembly/test site or prolonged storage) is expected. | 05-28-2015 |
20150311115 | Methods of Forming Memory Arrays - Some embodiments include methods of forming memory arrays. An assembly is formed which has an upper level over a lower level. The lower level includes circuitry. The upper level includes semiconductor material within a memory array region, and includes insulative material in a region peripheral to the memory array region. First and second trenches are formed to extend into the semiconductor material. The first and second trenches pattern the semiconductor material into a plurality of pedestals. The second trenches extend into the peripheral region. Contact openings are formed within the peripheral region to extend from the second trenches to the first level of circuitry. Conductive material is formed within the second trenches and within the contact openings. The conductive material forms sense/access lines within the second trenches and forms electrical contacts within the contact openings to electrically couple the sense/access lines to the lower level of circuitry. | 10-29-2015 |
20150318201 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device, including (a) forming an interlayer insulating film over a semiconductor substrate; (b) forming a third hard mask film over the interlayer insulating film; (c) forming a second hard mask film over the third hard mask film; (d) forming a first hard mask film over the second hard mask film; (e) after the step (d), forming a first opening in the first hard mask film and a second opening in the second hard mask film by etching the first and second hard mask films, respectively; (f) after the step (e), etching the first hard mask film so as to expand the first opening; and (g) after the step (f), etching the third hard mask film and a part of the interlayer insulating film in the second opening by using the second hard mask film as a mask. | 11-05-2015 |
20150318202 | METAL LAYER END-CUT FLOW - A method of patterning a metal layer is disclosed. The method includes providing a substrate and forming a material layer over the substrate. The method includes forming a second material layer over the first material layer. The method includes performing a first patterning process to the second material layer to form a trench in the second material layer. The first patterning process defines a width size of the trench, the width size being measured in a first direction. The method includes performing a second patterning process to the trench to transform the trench. The second patterning process defines a length size of the transformed trench. The length size is measured in a second direction different from the first direction. The method also includes filling the transformed trench with a conductive material. | 11-05-2015 |
20150318209 | Self-Aligned Semiconductor Fabrication With Fosse Features - The present disclosure describes methods for transferring a desired layout into a target layer on a semiconductor substrate. An embodiment of the methods includes forming a first desired layout feature as a first line over the target layer; forming a spacer around the first line; depositing a spacer-surrounding material layer; removing the spacer to form a fosse pattern trench surrounding the first line; and transferring the fosse pattern trench into the target layer to form a fosse feature trench in the target layer, wherein the fosse feature trench surrounds a first portion of the target layer that is underneath a protection layer. In some embodiments, the method further includes patterning a second desired layout feature of the desired layout into the target layer wherein the fosse feature trench and the protection layer serve to self-align the second desired layout feature with the first portion of the target layer. | 11-05-2015 |
20150325479 | METHOD FOR FORMING SELF-ALIGNED CONTACTS/VIAS WITH HIGH CORNER SELECTIVITY - A method of etching self-aligned contact/via features in a low-k dielectric layer disposed below a hardmask, which is disposed below a planarization layer. At least one cycle is provided, where each cycle comprises thinning the planarization layer, forming a deposition layer on the hardmask and planarization layer; and etching the low-k dielectric layer masked by the deposition layer. | 11-12-2015 |
20150332955 | SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME - The present disclosure describes semiconductor devices and methods of fabricating the same. The method includes forming an interlayer insulating layer on a substrate and forming conductive patterns in the interlayer insulating layer. A pore density of an upper portion of the interlayer insulating layer is higher than that of a lower portion of the interlayer insulating layer, and a pore density of an intermediate portion of the interlayer insulating layer gradually increases toward the upper portion of the interlayer insulating layer. An air gap is provided between the conductive patterns. | 11-19-2015 |
20150348839 | DIRECTED SELF ASSEMBLY OF BLOCK COPOLYMERS TO FORM VIAS ALIGNED WITH INTERCONNECTS - A method of an aspect includes forming an interconnect line etch opening in a hardmask layer. The hardmask layer is over a dielectric layer that has an interconnect line disposed therein. The interconnect line etch opening is formed aligned over the interconnect line. A block copolymer is introduced into the interconnect line etch opening. The block copolymer is assembled to form a plurality of assembled structures that are spaced along a length of the interconnect line etch opening. An assembled structure is directly aligned over the interconnect line that is disposed within the dielectric layer. | 12-03-2015 |
20150357185 | METHODS OF PROVIDING DIELECTRIC TO CONDUCTOR ADHESION IN PACKAGE STRUCTURES - Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include forming a CVD dielectric material on a package dielectric material, and then forming a conductive material on the CVD dielectric material. | 12-10-2015 |
20150364369 | Conductive Line System and Process - A system and method for providing a conductive line is provided. In an embodiment the conductive line is formed by forming two passivation layers, wherein each passivation layer is independently patterned. Once formed, a seed layer is deposited into the two passivation layers, and a conductive material is deposited to fill and overfill the patterns within the two passivation layers. A planarization process such as a chemical mechanical polish may then be utilized in order to remove excess conductive material and form the conductive lines within the two passivation layers. | 12-17-2015 |
20150371897 | Trench Formation using Horn Shaped Spacer - A method includes forming a mandrel layer over a target layer, and etching the mandrel layer to form mandrels. The mandrels have top widths greater than respective bottom widths, and the mandrels define a first opening in the mandrel layer. The first opening has an I-shape and includes two parallel portions and a connecting portion interconnecting the two parallel portions. Spacers are formed on sidewalls of the first opening. The spacers fill the connecting portion, wherein a center portion of each of the two parallel portions is unfilled by the spacers. Portions of the first opening that are unfilled by the spacers are extended into the target layer. | 12-24-2015 |
20150371899 | MINIMIZING VOID FORMATION IN SEMICONDUCTOR VIAS AND TRENCHES - Circuit structure fabrication methods are provided which include: patterning at least one opening within a dielectric layer disposed over a substrate structure; providing a liner material within the at least one opening of the dielectric layer; disposing a surfactant over at least a portion of the liner material; and depositing, using an electroless process, a conductive material over the liner material to form a conductive structure, and the disposed surfactant inhibits formation of a void within the conductive structure. | 12-24-2015 |
20150371903 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing one or more semiconductor devices may include the following steps: providing a dielectric layer on a substrate structure that includes a first electrode and a second electrode; providing a first mask on the dielectric layer; providing a second mask, which overlaps the first mask and has a designated structure, wherein a portion of the first mask is positioned between a first portion and a second portion of the designated structure in a layout view of a process structure that includes the first mask and the second mask; and performing a removal process through the first portion of the designated structure and through the second portion of the designated structure to form a first contact hole and a second contact hole in a remaining portion of the dielectric layer, wherein the two contact holes expose the two electrodes, respectively. | 12-24-2015 |
20150380307 | METHODS OF FORMING OPENINGS IN SEMICONDUCTOR STRUCTURES - A method of forming a semiconductor structure comprises forming pools of acidic or basic material in a substrate structure. A resist is formed over the pools of acidic or basic material and the substrate structure. The acidic or basic material is diffused from the pools into portions of the resist proximal to the pools more than into portions of the resist distal to the pools. Then, the resist is exposed to a developer to remove a greater amount of the resist portions proximal to the pools compared to the resist portions distal to the pools to form openings in the resist. The openings have wider portions proximal to the substrate structure and narrower portions distal to the substrate structure. The method may further comprise forming features in the openings of the resist. The features have wider portions proximal to the substrate structure and narrower portions distal to the substrate structure. | 12-31-2015 |
20160005615 | METHOD OF FORMING PATTERNS OF SEMICONDUCTOR DEVICE - A method of forming patterns of a semiconductor device includes forming a material film on a substrate, forming a hard mask on the material film, forming a first mold mask pattern and a second mold mask pattern on the hard mask, forming a pair of first spacers to cover opposite sidewalls of the first mold mask pattern, and a pair of second spacers to cover opposite sidewalls of the second mold mask pattern, forming a first gap and a second gap to expose the hard mask by removing the first mold mask pattern and the second mold mask pattern, the first gap being formed between the pair of first spacers and the second gap being formed between the pair of second spacers, forming a mask pattern on the hard mask to cover the first gap and expose the second gap, forming an auxiliary pattern to cover the second gap, removing the mask pattern; and forming a hard mask pattern by patterning the hard mask using the first spacers, the second spacers and the auxiliary pattern as a mask. | 01-07-2016 |
20160013098 | METHOD FOR FABRICATING INTERLAYER DIELECTRIC LAYER | 01-14-2016 |
20160013103 | Self-Aligned Double Patterning | 01-14-2016 |
20160020140 | ANISOTROPIC MATERIAL DAMAGE PROCESS FOR ETCHING LOW-K DIELECTRIC MATERIALS - In one example, a method includes forming a mask layer above or in a dielectric material. The dielectric material is exposed to photon radiation in an ambient atmosphere comprising a carbon gettering agent to generate damaged portions of the dielectric material. The mask layer blocks the photon radiation. The damaged portions of the dielectric material are removed. | 01-21-2016 |
20160020212 | SEMICONDUCTOR DEVICE INCLUDING A CAPACITOR AND A METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device is provided. The method includes sequentially forming a mold layer and a preliminary support layer on a substrate, forming a plurality of lower electrodes through the preliminary support layer and the mold layer, removing a portion of the preliminary support layer between the plurality of lower electrodes to form a preliminary support layer pattern having an open area exposing a top surface of the mold layer, removing the mold layer to form a void between the substrate and the preliminary support layer pattern, filling the open area and the void with a sacrificial layer, and replacing the preliminary support layer pattern with a support pattern. | 01-21-2016 |
20160027687 | INTERCONNECT LEVEL STRUCTURES FOR CONFINING STITCH-INDUCED VIA STRUCTURES - A design layout is provided such that an underlying conductive line structure underlies a stitch region in an overlying conductive line structure. A stitch-induced via structure can be formed between the underlying conductive line structure and the overlying conductive line structure when a stitch region in a hard mask layer is etched multiple times. At least one of the underlying conductive line structure and the overlying conductive line structure is electrically isolated from other conductive line structures in a same design level so as to avoid unintentional electrical shorts. | 01-28-2016 |
20160042994 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes: forming a semiconductor element having an electrode on a main surface of a semiconductor substrate; forming a first resin film that encloses a side of the electrode while keeping a distance from the electrode of the semiconductor element on the main surface of the semiconductor substrate; and forming a hollow structure around the electrode of the semiconductor element by bonding a second resin film that covers over the electrode while keeping a distance from the electrode of the semiconductor element to a top surface of the first resin film. | 02-11-2016 |
20160049327 | METHODS OF FABRICATING BEOL INTERLAYER STRUCTURES - Methods are provided for fabricating an interlayer structure useful in, for instance, providing BEOL interconnect for circuit structures. The method includes, for instance, providing an interlayer structure, including: providing an uncured insulating layer above a substrate structure; forming an energy removal film over the uncured insulated layer; forming at least one opening through the energy removal film and extending at least partially into the uncured insulating layer; and applying energy to cure the uncured insulating layer, establishing a cured insulating layer, and decomposing in part the energy removal film, establishing a reduced thickness, energy removal film over the cured insulating layer, the interlayer structure including the cured insulating layer, and the applying energy decreasing an aspect ratio(s) of the one opening(s). In one implementation, the uncured insulating layer includes porogens which also decompose partially during applying energy to further improve the aspect ratio(s). | 02-18-2016 |
20160056074 | METHOD FOR VOID-FREE COBALT GAP FILL - Provided herein are methods of depositing void-free cobalt into features with high aspect ratios. Methods involve (a) partially filling a feature with cobalt, (b) exposing the feature to a plasma generated from nitrogen-containing gas to selectively inhibit cobalt nucleation on surfaces near or at the top of the feature, optionally repeating (a) and (b), and depositing bulk cobalt into the feature by chemical vapor deposition. Methods may also involve exposing a feature including a barrier layer to a plasma generated from nitrogen-containing gas to selectively inhibit cobalt nucleation. The methods may be performed at low temperatures less than about 400° C. using cobalt-containing precursors. | 02-25-2016 |
20160064336 | INVISIBLE DUMMY FEATURES AND METHOD FOR FORMING THE SAME - A plurality of first miniature elements of an overlay mark is formed in a first layer. A plurality of second miniature elements of the overlay mark is formed in a second layer different from the first layer. A plurality of dummy features is formed around the overlay mark. The dummy features are formed such that they each have a dimension below a resolution of an alignment detection tool configured to optically scan the overlay mark in an alignment process. | 03-03-2016 |
20160093528 | FEATURE FILL WITH NUCLEATION INHIBITION - Described herein are methods of filling features with tungsten, and related systems and apparatus, involving inhibition of tungsten nucleation. In some embodiments, the methods involve selective inhibition along a feature profile. Methods of selectively inhibiting tungsten nucleation can include exposing the feature to a direct or remote plasma. Pre-inhibition and post-inhibition treatments are used to modulate the inhibition effect, facilitating feature fill using inhibition across a wide process window. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) wordlines. The methods may be used for both conformal fill and bottom-up/inside-out fill. Examples of applications include logic and memory contact fill, DRAM buried wordline fill, vertically integrated memory gate and wordline fill, and 3-D integration using through-silicon vias. | 03-31-2016 |
20160104646 | METHOD FOR FORMING SEMICONDUCTOR DEVICE - A manufacturing method for forming a semiconductor device includes: first, a substrate is provided, a fin structure is formed on the substrate, and a plurality of gate structures are formed on the fin structure, next, a hard mask layer and a first photoresist layer are formed on the fin structure, an first etching process is then performed on the first photoresist layer, afterwards, a plurality of patterned photoresist layers are formed on the remaining first photoresist layer and the remaining hard mask layer, where each patterned photoresist layer is disposed right above each gate structure, and the width of each patterned photoresist is larger than the width of each gate structure, and the patterned photoresist layer is used as a hard mask to perform an second etching process to form a plurality of second trenches. | 04-14-2016 |
20160126100 | SEMICONDUCTOR DEVICE WITH EQUIPOTENTIAL RING CONTACT AT CURVED PORTION OF EQUIPOTENTIAL RING ELECTRODE AND METHOD OF MANUFACTURING THE SAME - A downsized semiconductor device having an excellent reverse characteristic, and a method of manufacturing the semiconductor device is sought to improve. The semiconductor device comprises a semiconductor body having a polygonal contour. An active area is formed in the semiconductor body. An EQR electrode is formed so as to surround the active area and to have curved portions of the EQR electrode along the corners of the semiconductor body. An interlayer insulating film is formed to cover the active area and the EQR electrode. The EQR electrode is embedded in the interlayer insulating film around the active area. EQR contacts are in contact with the curved portions of the EQR electrode and the semiconductor body outside the curved portions, and have at least side walls covered with the interlayer insulating film. | 05-05-2016 |
20160133512 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING A PLURALITY OF ETCH STOP LAYERS - A method of manufacturing the semiconductor device includes providing a first interlayer dielectric layer having a conductive pattern, sequentially forming a first etch stop layer, a second etch stop layer, a second interlayer dielectric layer and a mask pattern on the first interlayer dielectric layer, forming an opening in the second interlayer dielectric layer using the mask pattern as a mask, the opening exposing the second etch stop layer, and performing an etching process including simultaneously removing the mask pattern and the second etch stop layer exposed by the opening to expose the first etch stop layer. | 05-12-2016 |
20160145097 | MEMS SWITCHES WITH REDUCED SWITCHING VOLTAGE AND METHODS OF MANUFACTURE - MEMS switches and methods of manufacturing MEMS switches is provided. The MEMS switch having at least two cantilevered electrodes having ends which overlap and which are structured and operable to contact one another upon an application of a voltage by at least one fixed electrode. | 05-26-2016 |
20160155649 | Method for Planarizing Semiconductor Device | 06-02-2016 |
20160163590 | METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES - Disclosed is a method of manufacturing a semiconductor device. A preliminary wafer-carrier assembly is formed in such a way that a wafer structure having a plurality of via structures is adhered to a light-penetrating carrier by a photodegradable adhesive. A wafer-carrier assembly having an optical shielding layer for inhibiting or preventing a light penetration is formed such that the wafer structure, the carrier and the adhesive are covered with the optical shielding layer except for the backside of the wafer structure through which the via structures are exposed. An interconnector is formed on the backside of the wafer structure such that the via structures make contact with the interconnector, and the wafer structure and the carrier are separated from each other by irradiating a light to the wafer-carrier assembly. Accordingly, the adhesive is inhibited or prevented from being dissolved during a plasma process on the wafer-carrier assembly. | 06-09-2016 |
20160172198 | Simultaneous Hydrophilization of Photoresist and Metal Surface Preparation: Methods, Systems, and Products | 06-16-2016 |
20160172238 | SELECTIVE SEALANT REMOVAL | 06-16-2016 |
20160181110 | Lithographic Technique for Feature Cut by Line-End Shrink | 06-23-2016 |
20160190002 | High Boiling Temperature Solvent Additives for Semiconductor Processing - A method for forming an interconnect structure includes forming a patterned layer over a substrate, the patterned layer having an opening therein. A dielectric material is filled in the opening. The dielectric material has a precursor and a solvent, the solvent having a boiling point temperature greater than a precursor cross-linking temperature. A thermal treatment is performed on the dielectric material to form a dielectric layer. | 06-30-2016 |
20160190003 | REDUCING DEFECTS AND IMPROVING RELIABILITY OF BEOL METAL FILL - A method of reducing defects in and improving reliability of Back-End-Of-Line (BEOL) metal fill includes providing a starting metallization structure for semiconductor device(s), the metallization structure including a bottom layer of contact(s) surrounded by a dielectric material. The starting metallization structure further includes an etch-stop layer over the bottom layer, a layer of dielectric material over the etch-stop layer, a first layer of hard mask material over the dielectric layer, a layer of work function hard mask material over the first hard mask layer, a second layer of hard mask material over the work function hard mask layer, via(s) to the first hard mask layer and other via(s) into the etch-stop layer. The method further includes protecting the other via(s) while removing the second hard mask layer and the layer of work function hard mask material, and filling the vias with metal. Protecting the other via(s) may include, prior to the removing, filling the other via(s) with an Energy Removal Film (ERF) up to a top surface of the first hard mask layer, and, after the removing, removing the ERF material. | 06-30-2016 |
20160190006 | MECHANISMS FOR FORMING SEMICONDUCTOR DEVICE STRUCTURE WITH FEATURE OPENING - A method for forming a semiconductor device structure is provided. The method includes forming a dielectric layer over a semiconductor substrate and forming a hard mask layer over the dielectric layer. The method also includes performing a plasma etching process to etch the hard mask layer to form an opening, and a gas mixture used in the plasma etching process includes a nitrogen-containing gas, a halogen-containing gas, and a carbon-containing gas. The gas mixture has a volumetric concentration of the nitrogen-containing gas in a range from about 20% to about 30%. A volumetric concentration ratio of the carbon-containing gas to the halogen-containing gas in the gas mixture is equal to about 0.3. The method further includes etching the dielectric layer through the opening in the hard mask layer to form a feature opening in the dielectric layer. The method includes forming a conductive material in the feature opening. | 06-30-2016 |
20160197081 | SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME | 07-07-2016 |
20160204026 | Contact Etch Stop Layers of a Field Effect Transistor | 07-14-2016 |
20180025937 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE | 01-25-2018 |
20190148386 | SRAM CELL WITH T-SHAPED CONTACT | 05-16-2019 |