Class / Patent application number | Description | Number of patent applications / Date published |
438658000 | Altering composition of conductor | 22 |
20090087984 | FORMING METHOD OF ELECTRODE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A forming method of an electrode includes the steps of providing an electrode material on a conductive part; exposing the electrode material at a temperature equal to or higher than a melting point of the electrode material in an oxidizing atmosphere; and exposing the melted electrode material, in a reducing atmosphere, at a temperature equal to or higher than the melting point of the electrode material and lower than the temperature at which the electrode material is exposed in the oxidizing atmosphere. | 04-02-2009 |
20090087985 | Selective formation of a compound comprising a semi-conducting material and a metallic material in a substrate through a germanium oxide layer - An area made from a compound of a metallic material and semi-conducting material is produced selectively in a substrate made from semi-conducting material by previously forming a germanium oxide layer with a thickness comprised between 3 nm and 5 nm over a predefined part of a surface of the substrate and a silicon oxide layer on the rest of the surface. A metallic layer is deposited on the oxide layers. The metallic material is chosen such that its oxide is thermodynamically more stable than germanium oxide and thermodynamically less stable than silicon oxide. Thermal annealing is then performed to obtain reduction of the germanium oxide by said metallic material followed by formation of the compound, at the level of said part of the surface of the substrate. The metallic layer is then removed. | 04-02-2009 |
20090124077 | Method for forming poly-silicon film - A poly-silicon film formation method for forming a poly-silicon film doped with phosphorous or boron includes heating a target substrate placed in a vacuum atmosphere inside a reaction container, and supplying into the reaction container a silicon film formation gas, a doping gas for doping a film with phosphorous or boron, and a grain size adjusting gas containing a component to retard columnar crystal formation from a poly-silicon crystal and to promote miniaturization of the poly-silicon crystal, thereby depositing a silicon film doped with phosphorous or boron on the target substrate. | 05-14-2009 |
20100015801 | Method of forming a seam-free tungsten plug - A plug comprises a first insulating interlayer, a tungsten pattern and a tungsten oxide pattern. The first insulating interlayer has a contact hole formed therethrough on a substrate. The tungsten pattern is formed in the contact hole. The tungsten pattern has a top surface lower than an upper face of the first insulating interlayer. The tungsten oxide pattern is formed in the contact hole and on the tungsten pattern. The tungsten oxide pattern has a level face. | 01-21-2010 |
20100048018 | Doped Layers for Reducing Electromigration - A method of fabricating metal interconnects with reduced electromigration includes depositing metal interconnects on a substrate comprising electronic devices. A layer is deposited on the metal interconnects. The layer is doped with at least one dopant having a dopant concentration that increases an electromigration resistance of the metal atoms. | 02-25-2010 |
20100330801 | Method of Fabricating Landing Plug in Semiconductor Device - A method of fabricating a landing plug in a semiconductor memory device, which in one embodiment includes forming a landing plug contact hole on a semiconductor substrate having an impurity region to expose the impurity region; forming a landing plug by filling the landing plug contact hole with a polysilicon layer, wherein the landing plug is divided into a first region, a second region, a third region, and a fourth region from a lower portion of the landing plug, and the first region is doped with a first doping concentration that is relatively lowest, the second region is doped with a second doping concentration that is higher than the first doping concentration, the third region is doped with a third doping concentration that is higher than the second doping concentration and the fourth region is not doped; and annealing the resulting product formed with the landing plug. | 12-30-2010 |
20110008961 | METHOD FOR FABRICATING INTEGRATED CIRCUIT STRUCTURES - A method for fabricating an integrated circuit structure includes the steps of forming a second dielectric layer on a substrate including a first conductive layer and a first dielectric layer, forming the second dielectric layer on the first conductive layer and the first dielectric layer, forming a hole exposing the first conductive layer in the second dielectric layer, forming a barrier layer inside the hole, and forming a second conductive layer on the barrier layer. In one embodiment of the present invention, the forming of the barrier layer comprises the steps of forming a metal layer in the hole, and performing a treating process in an atmosphere including a plasma formed from a gas including oxidant to form a metal oxide layer on the metal layer. In another embodiment of the present invention, the forming of the barrier layer comprises the steps of forming a metal nitride layer in the hole, and performing a treating process in an atmosphere including a plasma formed from a gas including oxidant to form a metal oxide layer on the metal and metal nitride layer. | 01-13-2011 |
20120077341 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - In a semiconductor device manufacturing method according to an exemplary embodiment, a sulfur-containing film containing sulfur is deposited on an n-type semiconductor, a first metal film containing a first metal is deposited on the sulfur-containing film, a heat treatment is performed to form a metal semiconductor compound film by reacting the n-type semiconductor and the sulfur-containing film, and to introduce sulfur to an interface between the n-type semiconductor and the metal semiconductor compound film being formed. | 03-29-2012 |
20120252210 | METHOD FOR MODIFYING METAL CAP LAYERS IN SEMICONDUCTOR DEVICES - A method for forming a semiconductor device with improved electromigration (EM) and stress migration (SM) properties. The method includes providing a planarized patterned substrate containing a copper (Cu) metal surface and a low-k dielectric layer surface, selectively depositing a metal cap layer on the Cu metal surface, and modifying the metal cap layer by exposing the metal cap layer to a process gas containing ammonia (NH | 10-04-2012 |
20120270393 | METAL SILICIDE, METAL GERMANIDE, METHODS FOR MAKING THE SAME - In one aspect, methods of silicidation and germanidation are provided. In some embodiments, methods for forming metal silicide can include forming a non-oxide interface, such as germanium or solid antimony, over exposed silicon regions of a substrate. Metal oxide is formed over the interface layer. Annealing and reducing causes metal from the metal oxide to react with the underlying silicon and form metal silicide. Additionally, metal germanide can be formed by reduction of metal oxide over germanium, whether or not any underlying silicon is also silicided. In other embodiments, nickel is deposited directly and an interface layer is not used. In another aspect, methods of depositing nickel thin films by vapor phase deposition processes are provided. In some embodiments, nickel thin films are deposited by ALD. | 10-25-2012 |
20130005142 | METHOD AND APPARATUS FOR FORMING SILICON FILM - Provided is a method and apparatus for forming a silicon film, which are capable of suppressing generation of a void or seam. The method includes performing a first film-forming process, performing an etching process, performing a doping process, and performing a second film-forming process. In the first film-forming process, a non-doped silicon film that is not doped with an impurity is formed so as to embed a groove of an object. In the etching process, the non-doped silicon film formed via the first film-forming process is etched. In the doping process, the non-doped silicon film etched via the etching process is doped with an impurity. In the second film-forming process, an impurity-doped silicon film is formed so as to embed the silicon film doped via the doping process. | 01-03-2013 |
20130065391 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, METHOD OF PROCESSING SUBSTRATE, SUBSTRATE PROCESSING APPARATUS AND COMPUTER-READABLE RECORDING MEDIUM - A method of manufacturing a semiconductor device, includes: alternately performing (i) a first step of alternately supplying a first raw material containing a first metal element and a halogen element and a second raw material containing a second metal element and carbon to a substrate by a first predetermined number of times, and (ii) a second step of supplying a nitridation raw material to the substrate, by a second predetermined number of times, wherein alternating the first and second steps forms a metal carbonitride film containing the first metal element having a predetermined thickness on the substrate. | 03-14-2013 |
20130143402 | Method of forming Cu thin film - The disclosure provides a method for forming a dense Cu thin film by atomic layer deposition, comprising the following steps of: (A) providing an additive gas; (B) choosing a copper-containing metal-organic complex as a precursor; (C) using a carrier gas to introduce the additive gas into the precursor cell mixing with the precursor; (D) pre-depositing the precursor on the surface of the substrate with a TaN | 06-06-2013 |
20140187039 | Method for Tuning the Effective Work Function of a Gate Structure in a Semiconductor Device - A method for tuning the effective work function of a gate structure in a semiconductor device is described. The semiconductor device is part of an integrated circuit and the gate structure has a metal layer and a high-k dielectric layer separating the metal layer from an active layer of the semiconductor device. The method includes providing an interconnect structure of the integrated circuit on top of the gate structure, the interconnect structure comprising a layer stack comprising at least a pre-metal dielectric layer comprising a metal filled connecting via connected to the gate structure through the pre-metal dielectric layer, and the interconnect structure having an upper exposed metal portion; and, thereafter, exposing at least a portion of the upper exposed metal portion to a plasma under predetermined exposure conditions, to tune the effective work function of the gate structure. | 07-03-2014 |
20160035852 | METAL SILICIDE, METAL GERMANIDE, METHODS FOR MAKING THE SAME - In one aspect, methods of silicidation and germanidation are provided. In some embodiments, methods for forming metal silicide can include forming a non-oxide interface, such as germanium or solid antimony, over exposed silicon regions of a substrate. Metal oxide is formed over the interface layer. Annealing and reducing causes metal from the metal oxide to react with the underlying silicon and form metal silicide. Additionally, metal germanide can be formed by reduction of metal oxide over germanium, whether or not any underlying silicon is also silicided. In other embodiments, nickel is deposited directly and an interface layer is not used. In another aspect, methods of depositing nickel thin films by vapor phase deposition processes are provided. In some embodiments, nickel thin films are deposited by ALD. | 02-04-2016 |
438659000 | Implantation of ion into conductor | 7 |
20090117735 | IMPLANTATION OF MULTIPLE SPECIES TO ADDRESS COPPER RELIABILITY - A first species and a second species are implanted into a conductor of a substrate, which may be copper. The first species and second species may be implanted sequentially or at least partly simultaneously. Diffusion of the first species within the conductor of the substrate is prevented by the presence of the second species. In one particular example, the first species is silicon and the second species is nitrogen, although other combinations are possible. | 05-07-2009 |
20090275198 | Vapor Phase Methods for Forming Electrodes in Phase Change Memory Devices - A method for forming electrode materials uniformly and conformally within openings having small dimensions, including sublithographic dimensions, or high aspect ratios. The method includes the steps of providing an insulator layer having an opening formed therein, and forming a conformal conductive or semiresistive material over and within the opening. The method is a CVD or ALD process for forming metal nitride, metal aluminum nitride, and metal silicon nitride electrode compositions. The methods utilize metal precursors containing one or more ligands selected from alkyl, allyl, alkene, alkyne, acyl, amide, amine, immine, imide, azide, hydrazine, silyl, alkylsilyl, silylamine, chelating, hydride, cyclic, carbocyclic, cyclopentadienyl, phosphine, carbonyl, or halide. Suitable precursors include monometallic precursors having the general formula MR | 11-05-2009 |
20100248473 | SELECTIVE DEPOSITION OF METAL-CONTAINING CAP LAYERS FOR SEMICONDUCTOR DEVICES - A method for integrating metal-containing cap layers into copper (Cu) metallization of semiconductor devices. In one embodiment, the method includes providing a patterned substrate containing metal surfaces and dielectric layer surfaces, and modifying the dielectric layer surfaces by exposure to a reactant gas containing a hydrophobic functional group, where the modifying substitutes a hydrophilic functional group in the dielectric layer surfaces with a hydrophobic functional group. The method further includes depositing metal-containing cap layers selectively on the metal surfaces by exposing the modified dielectric layer surfaces and the metal surfaces to a deposition gas containing metal-containing precursor vapor. | 09-30-2010 |
20120088365 | TECHNIQUE FOR FORMING METAL LINES IN A SEMICONDUCTOR BY ADAPTING THE TEMPERATURE DEPENDENCE OF THE LINE RESISTANCE - By moderately introducing defects into a highly conductive material, such as copper, the resistance versus temperature behavior may be significantly modified so that enhanced electromigration behavior and/or electrical performance may be obtained in metallization structures of advanced semiconductor devices. The defect-related portion of the resistance may be moderately increased so as to change the slope of the resistance versus temperature curve, thereby allowing the incorporation of impurity atoms for enhancing the electromigration endurance while not unduly increasing the overall resistance at the operating temperature or even reducing the corresponding resistance at the specified operating temperature. Thus, by appropriately designing the electrical resistance for a target operating temperature, both the electromigration behavior and the electrical performance may be enhanced. | 04-12-2012 |
20120282769 | METHODS OF FORMING INTEGRATED CIRCUIT DEVICES HAVING ELECTRICALLY CONDUCTIVE LAYERS THEREIN WITH PARTIALLY NITRIDATED SIDEWALLS - Methods of forming integrated circuit devices include forming an electrically conductive layer containing silicon on a substrate and forming a mask pattern on the electrically conductive layer. The electrically conductive layer is selectively etched to define a first sidewall thereon, using the mask pattern as an etching mask. The first sidewall of the electrically conductive layer may be exposed to a nitrogen plasma to thereby form a first silicon nitride layer on the first sidewall. The electrically conductive layer is then selectively etched again to expose a second sidewall thereon that is free of the first silicon nitride layer. The mask pattern may be used again as an etching mask during this second step of selectively etching the electrically conductive layer. | 11-08-2012 |
20130280906 | SEMICONDUCTOR DEVICE INCLUDING A DEEP CONTACT AND A METHOD OF MANUFACTURING SUCH A DEVICE - A semiconductor device includes a buried layer and a deep contact for providing a low resistive connection to the buried layer. The deep contact is formed by doped polycrystalline silicon. A method of manufacturing a semiconductor device and a deep contact for providing a low resistive connection to the buried layer, with the steps of forming a buried layer, providing an active region adjacent the buried layer and forming a deep contact for providing a low resistive connection to the buried layer by patterning a contact shape for the deep contact on an upper surface of the active region, removing part of the active region underneath the contact shape to create a deep contact cavity. Subsequently a polycrystalline silicon layer for filling the deep contact cavity is deposited and doped. | 10-24-2013 |
20140179100 | Method to Control Depth Profiles of Dopants Using a Remote Plasma Source - Methods and apparatus for processing using a remote plasma source are disclosed. The apparatus includes an outer chamber enclosing a substrate support, a remote plasma source, and a showerhead. A substrate heater can be mounted in the substrate support. A transport system moves the substrate support and is capable of positioning the substrate. The remote plasma source may be used to provide a plasma surface treatment or as a source to incorporate dopants into a pre-deposited layer. | 06-26-2014 |